system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Author Oleksandr Borysov
* Task1
*/
#include <stdio.h>
#include <curand.h>
#include <curand_kernel.h>
#include <math.h>
#include <time.h>
#define SEED 34237
#define MAX 32767
#define PLOT_DATA_FILE "plotData_1.txt"
__global__ void getPI(double* result, unsigned long* steps) {
double x, y, z;
long count = 0;
curandState_t state;
curand_init(SEED, 0, 0, &state);
for (unsigned long i = 0; i < *steps; ++i) {
x = ((double) ((curand(&state)) % MAX)) / MAX;
y = ((double) ((curand(&state)) % MAX)) / MAX;
z = sqrt((x * x) + (y * y));
if (z <= 1) {
++count;
}
}
*result = ((double) count / *steps) * 4.0;
}
int main()
{
cudaError_t cudaStatus;
double* d_result;
double result;
unsigned long* d_stepNumber;
unsigned long stepNumber;
clock_t begin = clock();
printf("Type number of steps \n");
scanf("%lu", &stepNumber);
// Allocate memory in GPU
cudaStatus = cudaMalloc(&d_result, sizeof(double));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc d_result failed!");
goto Error;
}
cudaStatus = cudaMalloc(&d_stepNumber, sizeof(long));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc d_stepNumber failed!");
goto Error;
}
cudaStatus = cudaMemcpy(d_stepNumber, &stepNumber, sizeof(long), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy d_stepNumber failed!");
goto Error;
}
// Call cuda method
getPI<<<1, 1>>>(d_result, d_stepNumber);
// Check for any errors launching the kernel
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Chek result
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "getPI failed!");
return 1;
}
cudaStatus = cudaMemcpy(&result, d_result, sizeof(double), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy result failed!");
goto Error;
}
printf("Calculated PI is = %f.\n", result);
Error:
cudaFree(d_result);
cudaFree(d_stepNumber);
if (cudaStatus == 0) {
double time_spent = (double) (clock() - begin) / CLOCKS_PER_SEC;
FILE* dataPlotFile;
dataPlotFile = fopen(PLOT_DATA_FILE, "a");
fprintf(dataPlotFile, "%d %f\n", stepNumber, time_spent);
fclose(dataPlotFile);
printf("%d %f\n", stepNumber, time_spent);
}
return cudaStatus;
} | .file "tmpxft_00163b7f_00000000-6_Monte_Carlo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z5getPIPdPmPdPm
.type _Z26__device_stub__Z5getPIPdPmPdPm, @function
_Z26__device_stub__Z5getPIPdPmPdPm:
.LFB2296:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5getPIPdPm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2296:
.size _Z26__device_stub__Z5getPIPdPmPdPm, .-_Z26__device_stub__Z5getPIPdPmPdPm
.globl _Z5getPIPdPm
.type _Z5getPIPdPm, @function
_Z5getPIPdPm:
.LFB2297:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z5getPIPdPmPdPm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2297:
.size _Z5getPIPdPm, .-_Z5getPIPdPm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Type number of steps \n"
.LC1:
.string "%lu"
.LC2:
.string "cudaMalloc d_result failed!"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "cudaMalloc d_stepNumber failed!"
.align 8
.LC4:
.string "cudaMemcpy d_stepNumber failed!"
.section .rodata.str1.1
.LC5:
.string "addKernel launch failed: %s\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "cudaDeviceSynchronize returned error code %d after launching addKernel!\n"
.section .rodata.str1.1
.LC7:
.string "cudaMemcpy result failed!"
.LC8:
.string "Calculated PI is = %f.\n"
.LC10:
.string "a"
.LC11:
.string "plotData_1.txt"
.LC12:
.string "%d %f\n"
.text
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
call clock@PLT
movq %rax, %rbp
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq %rsp, %rdi
movl $8, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L24
leaq 8(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L25
leaq 16(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L26
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L16:
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L28
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L29
leaq 40(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L30
movsd 40(%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC9(%rip), %xmm0
movq %xmm0, %rbp
leaq .LC10(%rip), %rsi
leaq .LC11(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movq %rbp, %xmm0
movq 16(%rsp), %rcx
leaq .LC12(%rip), %r13
movq %r13, %rdx
movl $2, %esi
movq %rax, %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq %r12, %rdi
call fclose@PLT
movq %rbp, %xmm0
movq 16(%rsp), %rdx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L20
.L24:
movl %eax, %ebx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L13:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
.L20:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl %ebx, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L26:
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L27:
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z5getPIPdPmPdPm
jmp .L16
.L28:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L29:
movl %eax, %ecx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L30:
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z5getPIPdPm"
.LC14:
.string "precalc_xorwow_matrix"
.LC15:
.string "precalc_xorwow_offset_matrix"
.LC16:
.string "mrg32k3aM1"
.LC17:
.string "mrg32k3aM2"
.LC18:
.string "mrg32k3aM1SubSeq"
.LC19:
.string "mrg32k3aM2SubSeq"
.LC20:
.string "mrg32k3aM1Seq"
.LC21:
.string "mrg32k3aM2Seq"
.LC22:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2299:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z5getPIPdPm(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC9:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Author Oleksandr Borysov
* Task1
*/
#include <stdio.h>
#include <curand.h>
#include <curand_kernel.h>
#include <math.h>
#include <time.h>
#define SEED 34237
#define MAX 32767
#define PLOT_DATA_FILE "plotData_1.txt"
__global__ void getPI(double* result, unsigned long* steps) {
double x, y, z;
long count = 0;
curandState_t state;
curand_init(SEED, 0, 0, &state);
for (unsigned long i = 0; i < *steps; ++i) {
x = ((double) ((curand(&state)) % MAX)) / MAX;
y = ((double) ((curand(&state)) % MAX)) / MAX;
z = sqrt((x * x) + (y * y));
if (z <= 1) {
++count;
}
}
*result = ((double) count / *steps) * 4.0;
}
int main()
{
cudaError_t cudaStatus;
double* d_result;
double result;
unsigned long* d_stepNumber;
unsigned long stepNumber;
clock_t begin = clock();
printf("Type number of steps \n");
scanf("%lu", &stepNumber);
// Allocate memory in GPU
cudaStatus = cudaMalloc(&d_result, sizeof(double));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc d_result failed!");
goto Error;
}
cudaStatus = cudaMalloc(&d_stepNumber, sizeof(long));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc d_stepNumber failed!");
goto Error;
}
cudaStatus = cudaMemcpy(d_stepNumber, &stepNumber, sizeof(long), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy d_stepNumber failed!");
goto Error;
}
// Call cuda method
getPI<<<1, 1>>>(d_result, d_stepNumber);
// Check for any errors launching the kernel
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Chek result
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "getPI failed!");
return 1;
}
cudaStatus = cudaMemcpy(&result, d_result, sizeof(double), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy result failed!");
goto Error;
}
printf("Calculated PI is = %f.\n", result);
Error:
cudaFree(d_result);
cudaFree(d_stepNumber);
if (cudaStatus == 0) {
double time_spent = (double) (clock() - begin) / CLOCKS_PER_SEC;
FILE* dataPlotFile;
dataPlotFile = fopen(PLOT_DATA_FILE, "a");
fprintf(dataPlotFile, "%d %f\n", stepNumber, time_spent);
fclose(dataPlotFile);
printf("%d %f\n", stepNumber, time_spent);
}
return cudaStatus;
} | /*
* Author Oleksandr Borysov
* Task1
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <math.h>
#include <time.h>
#define SEED 34237
#define MAX 32767
#define PLOT_DATA_FILE "plotData_1.txt"
__global__ void getPI(double* result, unsigned long* steps) {
double x, y, z;
long count = 0;
hiprandState_t state;
hiprand_init(SEED, 0, 0, &state);
for (unsigned long i = 0; i < *steps; ++i) {
x = ((double) ((hiprand(&state)) % MAX)) / MAX;
y = ((double) ((hiprand(&state)) % MAX)) / MAX;
z = sqrt((x * x) + (y * y));
if (z <= 1) {
++count;
}
}
*result = ((double) count / *steps) * 4.0;
}
int main()
{
hipError_t cudaStatus;
double* d_result;
double result;
unsigned long* d_stepNumber;
unsigned long stepNumber;
clock_t begin = clock();
printf("Type number of steps \n");
scanf("%lu", &stepNumber);
// Allocate memory in GPU
cudaStatus = hipMalloc(&d_result, sizeof(double));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc d_result failed!");
goto Error;
}
cudaStatus = hipMalloc(&d_stepNumber, sizeof(long));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc d_stepNumber failed!");
goto Error;
}
cudaStatus = hipMemcpy(d_stepNumber, &stepNumber, sizeof(long), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy d_stepNumber failed!");
goto Error;
}
// Call cuda method
getPI<<<1, 1>>>(d_result, d_stepNumber);
// Check for any errors launching the kernel
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Chek result
if (cudaStatus != hipSuccess) {
fprintf(stderr, "getPI failed!");
return 1;
}
cudaStatus = hipMemcpy(&result, d_result, sizeof(double), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy result failed!");
goto Error;
}
printf("Calculated PI is = %f.\n", result);
Error:
hipFree(d_result);
hipFree(d_stepNumber);
if (cudaStatus == 0) {
double time_spent = (double) (clock() - begin) / CLOCKS_PER_SEC;
FILE* dataPlotFile;
dataPlotFile = fopen(PLOT_DATA_FILE, "a");
fprintf(dataPlotFile, "%d %f\n", stepNumber, time_spent);
fclose(dataPlotFile);
printf("%d %f\n", stepNumber, time_spent);
}
return cudaStatus;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Author Oleksandr Borysov
* Task1
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <math.h>
#include <time.h>
#define SEED 34237
#define MAX 32767
#define PLOT_DATA_FILE "plotData_1.txt"
__global__ void getPI(double* result, unsigned long* steps) {
double x, y, z;
long count = 0;
hiprandState_t state;
hiprand_init(SEED, 0, 0, &state);
for (unsigned long i = 0; i < *steps; ++i) {
x = ((double) ((hiprand(&state)) % MAX)) / MAX;
y = ((double) ((hiprand(&state)) % MAX)) / MAX;
z = sqrt((x * x) + (y * y));
if (z <= 1) {
++count;
}
}
*result = ((double) count / *steps) * 4.0;
}
int main()
{
hipError_t cudaStatus;
double* d_result;
double result;
unsigned long* d_stepNumber;
unsigned long stepNumber;
clock_t begin = clock();
printf("Type number of steps \n");
scanf("%lu", &stepNumber);
// Allocate memory in GPU
cudaStatus = hipMalloc(&d_result, sizeof(double));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc d_result failed!");
goto Error;
}
cudaStatus = hipMalloc(&d_stepNumber, sizeof(long));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc d_stepNumber failed!");
goto Error;
}
cudaStatus = hipMemcpy(d_stepNumber, &stepNumber, sizeof(long), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy d_stepNumber failed!");
goto Error;
}
// Call cuda method
getPI<<<1, 1>>>(d_result, d_stepNumber);
// Check for any errors launching the kernel
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Chek result
if (cudaStatus != hipSuccess) {
fprintf(stderr, "getPI failed!");
return 1;
}
cudaStatus = hipMemcpy(&result, d_result, sizeof(double), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy result failed!");
goto Error;
}
printf("Calculated PI is = %f.\n", result);
Error:
hipFree(d_result);
hipFree(d_stepNumber);
if (cudaStatus == 0) {
double time_spent = (double) (clock() - begin) / CLOCKS_PER_SEC;
FILE* dataPlotFile;
dataPlotFile = fopen(PLOT_DATA_FILE, "a");
fprintf(dataPlotFile, "%d %f\n", stepNumber, time_spent);
fclose(dataPlotFile);
printf("%d %f\n", stepNumber, time_spent);
}
return cudaStatus;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5getPIPdPm
.globl _Z5getPIPdPm
.p2align 8
.type _Z5getPIPdPm,@function
_Z5getPIPdPm:
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_load_b64 s[4:5], s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u64 s[4:5], 0
s_cbranch_scc1 .LBB0_4
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v1, 0
s_mov_b32 s12, 0xbe83d4e7
s_mov_b32 s2, 0xb2754e17
s_mov_b32 s3, 0xa96f9d04
s_mov_b32 s10, 0x8f14727c
s_mov_b32 s11, 0xab71c01b
s_mov_b32 s8, 0x35e15adf
s_mov_b32 s9, 0x35e6e2a4
s_mov_b64 s[6:7], s[4:5]
.LBB0_2:
s_mov_b32 s14, s10
s_lshr_b32 s10, s2, 2
s_mov_b32 s13, s3
s_mov_b32 s3, s11
s_lshr_b32 s11, s12, 2
s_xor_b32 s2, s10, s2
s_lshl_b32 s10, s3, 4
s_xor_b32 s11, s11, s12
s_lshl_b32 s12, s2, 1
s_lshl_b32 s15, s11, 1
s_xor_b32 s10, s12, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s2, s10, s2
s_xor_b32 s10, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s2, s10, 4
s_add_i32 s12, s10, s8
s_xor_b32 s2, s15, s2
s_mul_hi_u32 s15, s12, 0x20005
s_xor_b32 s2, s2, s11
s_sub_i32 s12, s12, s15
s_xor_b32 s11, s2, s10
s_lshr_b32 s2, s12, 1
s_add_i32 s12, s11, s9
s_add_i32 s2, s2, s15
s_mul_hi_u32 s15, s12, 0x20005
s_lshr_b32 s2, s2, 14
s_sub_i32 s12, s12, s15
s_mulk_i32 s2, 0x7fff
s_lshr_b32 s12, s12, 1
s_sub_i32 s2, s10, s2
s_add_i32 s12, s12, s15
s_add_i32 s2, s8, s2
s_lshr_b32 s12, s12, 14
v_cvt_f64_u32_e32 v[2:3], s2
s_mulk_i32 s12, 0x7fff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_sub_i32 s2, s11, s12
s_mov_b32 s12, s14
s_add_i32 s2, s8, s2
s_add_i32 s2, s2, 0x587c5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f64_u32_e32 v[4:5], s2
v_div_scale_f64 v[6:7], null, 0x40dfffc0, 0x40dfffc0, v[2:3]
v_div_scale_f64 v[18:19], vcc_lo, v[2:3], 0x40dfffc0, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_div_scale_f64 v[8:9], null, 0x40dfffc0, 0x40dfffc0, v[4:5]
v_div_scale_f64 v[20:21], s2, v[4:5], 0x40dfffc0, v[4:5]
v_rcp_f64_e32 v[10:11], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[12:13], v[8:9]
s_waitcnt_depctr 0xfff
v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
v_mul_f64 v[14:15], v[18:19], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[16:17], v[20:21], v[12:13]
v_fma_f64 v[6:7], -v[6:7], v[14:15], v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[8:9], -v[8:9], v[16:17], v[20:21]
v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[14:15]
s_mov_b32 vcc_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[16:17]
v_div_fixup_f64 v[2:3], v[6:7], 0x40dfffc0, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[4:5], v[8:9], 0x40dfffc0, v[4:5]
v_mul_f64 v[4:5], v[4:5], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[2:3], v[2:3], v[4:5]
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[2:3]
v_cndmask_b32_e64 v4, 0, 1, vcc_lo
s_and_b32 s2, vcc_lo, exec_lo
s_cselect_b32 s2, 0xffffff80, 0
s_add_u32 s6, s6, -1
s_addc_u32 s7, s7, -1
v_lshlrev_b32_e32 v4, 8, v4
s_add_i32 s8, s8, 0xb0f8a
s_add_i32 s9, s9, 0xb0f8a
s_cmp_eq_u64 s[6:7], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[2:3], v[2:3], v4
v_rsq_f64_e32 v[4:5], v[2:3]
v_cmp_class_f64_e64 vcc_lo, v[2:3], 0x260
s_waitcnt_depctr 0xfff
v_mul_f64 v[6:7], v[2:3], v[4:5]
v_mul_f64 v[4:5], v[4:5], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[4:5], v[6:7], 0.5
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_fma_f64 v[4:5], v[4:5], v[8:9], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[6:7], v[6:7], v[2:3]
v_fma_f64 v[6:7], v[8:9], v[4:5], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[6:7], v[6:7], v[2:3]
v_fma_f64 v[4:5], v[8:9], v[4:5], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ldexp_f64 v[4:5], v[4:5], s2
s_mov_b32 s2, s13
v_dual_cndmask_b32 v3, v5, v3 :: v_dual_cndmask_b32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_ge_f64_e32 vcc_lo, 1.0, v[2:3]
v_cndmask_b32_e64 v2, 0, 1, vcc_lo
v_add_co_u32 v0, vcc_lo, v0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_cbranch_scc0 .LBB0_2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f64_i32_e32 v[1:2], v1
v_cvt_f64_u32_e32 v[3:4], v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[1:2], v[1:2], 32
v_add_f64 v[0:1], v[1:2], v[3:4]
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v1, 0
.LBB0_5:
v_cvt_f64_u32_e32 v[2:3], s5
v_cvt_f64_u32_e32 v[4:5], s4
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[2:3], v[2:3], 32
v_add_f64 v[2:3], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[0:1]
v_rcp_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_div_scale_f64 v[8:9], vcc_lo, v[0:1], v[2:3], v[0:1]
v_mul_f64 v[10:11], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fixup_f64 v[0:1], v[4:5], v[2:3], v[0:1]
v_mov_b32_e32 v2, 0
v_mul_f64 v[0:1], v[0:1], 4.0
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5getPIPdPm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 22
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5getPIPdPm, .Lfunc_end0-_Z5getPIPdPm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5getPIPdPm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5getPIPdPm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 22
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Author Oleksandr Borysov
* Task1
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <math.h>
#include <time.h>
#define SEED 34237
#define MAX 32767
#define PLOT_DATA_FILE "plotData_1.txt"
__global__ void getPI(double* result, unsigned long* steps) {
double x, y, z;
long count = 0;
hiprandState_t state;
hiprand_init(SEED, 0, 0, &state);
for (unsigned long i = 0; i < *steps; ++i) {
x = ((double) ((hiprand(&state)) % MAX)) / MAX;
y = ((double) ((hiprand(&state)) % MAX)) / MAX;
z = sqrt((x * x) + (y * y));
if (z <= 1) {
++count;
}
}
*result = ((double) count / *steps) * 4.0;
}
int main()
{
hipError_t cudaStatus;
double* d_result;
double result;
unsigned long* d_stepNumber;
unsigned long stepNumber;
clock_t begin = clock();
printf("Type number of steps \n");
scanf("%lu", &stepNumber);
// Allocate memory in GPU
cudaStatus = hipMalloc(&d_result, sizeof(double));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc d_result failed!");
goto Error;
}
cudaStatus = hipMalloc(&d_stepNumber, sizeof(long));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc d_stepNumber failed!");
goto Error;
}
cudaStatus = hipMemcpy(d_stepNumber, &stepNumber, sizeof(long), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy d_stepNumber failed!");
goto Error;
}
// Call cuda method
getPI<<<1, 1>>>(d_result, d_stepNumber);
// Check for any errors launching the kernel
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Chek result
if (cudaStatus != hipSuccess) {
fprintf(stderr, "getPI failed!");
return 1;
}
cudaStatus = hipMemcpy(&result, d_result, sizeof(double), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy result failed!");
goto Error;
}
printf("Calculated PI is = %f.\n", result);
Error:
hipFree(d_result);
hipFree(d_stepNumber);
if (cudaStatus == 0) {
double time_spent = (double) (clock() - begin) / CLOCKS_PER_SEC;
FILE* dataPlotFile;
dataPlotFile = fopen(PLOT_DATA_FILE, "a");
fprintf(dataPlotFile, "%d %f\n", stepNumber, time_spent);
fclose(dataPlotFile);
printf("%d %f\n", stepNumber, time_spent);
}
return cudaStatus;
} | .text
.file "Monte_Carlo.hip"
.globl _Z20__device_stub__getPIPdPm # -- Begin function _Z20__device_stub__getPIPdPm
.p2align 4, 0x90
.type _Z20__device_stub__getPIPdPm,@function
_Z20__device_stub__getPIPdPm: # @_Z20__device_stub__getPIPdPm
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5getPIPdPm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z20__device_stub__getPIPdPm, .Lfunc_end0-_Z20__device_stub__getPIPdPm
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
callq clock
movq %rax, %rbx
movl $.Lstr, %edi
callq puts@PLT
movq %rsp, %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
leaq 16(%rsp), %rdi
movl $8, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $8, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_3
# %bb.6:
movq 8(%rsp), %rdi
movq %rsp, %rsi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_7
# %bb.8:
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 32(%rsp)
leaq 96(%rsp), %rax
movq %rax, 40(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z5getPIPdPm, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_11
# %bb.12:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_13
# %bb.14:
movq 16(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_15
# %bb.16:
movsd 32(%rsp), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.9, %edi
movb $1, %al
callq printf
xorl %ebp, %ebp
jmp .LBB1_17
.LBB1_1:
movl %eax, %ebp
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $26, %esi
jmp .LBB1_5
.LBB1_3:
movl %eax, %ebp
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
jmp .LBB1_4
.LBB1_7:
movl %eax, %ebp
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
.LBB1_4:
movl $30, %esi
jmp .LBB1_5
.LBB1_11:
movq stderr(%rip), %r14
movl %eax, %ebp
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_17
.LBB1_13:
movq stderr(%rip), %rdi
movl $.L.str.6, %esi
movl %eax, %ebp
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB1_17
.LBB1_15:
movl %eax, %ebp
movq stderr(%rip), %rcx
movl $.L.str.8, %edi
movl $24, %esi
.LBB1_5:
movl $1, %edx
callq fwrite@PLT
.LBB1_17:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl %ebp, %eax
testl %ebp, %ebp
jne .LBB1_19
# %bb.18:
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
movl $.L.str.10, %edi
movl $.L.str.11, %esi
callq fopen
movq %rax, %rbx
movq (%rsp), %rdx
movl $.L.str.12, %esi
movq %rax, %rdi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq fprintf
movq %rbx, %rdi
callq fclose
movq (%rsp), %rsi
movl $.L.str.12, %edi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl %ebp, %eax
.LBB1_19:
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5getPIPdPm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5getPIPdPm,@object # @_Z5getPIPdPm
.section .rodata,"a",@progbits
.globl _Z5getPIPdPm
.p2align 3, 0x0
_Z5getPIPdPm:
.quad _Z20__device_stub__getPIPdPm
.size _Z5getPIPdPm, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%lu"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipMalloc d_result failed!"
.size .L.str.2, 27
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipMalloc d_stepNumber failed!"
.size .L.str.3, 31
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMemcpy d_stepNumber failed!"
.size .L.str.4, 31
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "addKernel launch failed: %s\n"
.size .L.str.5, 29
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipDeviceSynchronize returned error code %d after launching addKernel!\n"
.size .L.str.6, 72
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "hipMemcpy result failed!"
.size .L.str.8, 25
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Calculated PI is = %f.\n"
.size .L.str.9, 24
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "plotData_1.txt"
.size .L.str.10, 15
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "a"
.size .L.str.11, 2
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "%d %f\n"
.size .L.str.12, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5getPIPdPm"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Type number of steps "
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__getPIPdPm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5getPIPdPm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00163b7f_00000000-6_Monte_Carlo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z5getPIPdPmPdPm
.type _Z26__device_stub__Z5getPIPdPmPdPm, @function
_Z26__device_stub__Z5getPIPdPmPdPm:
.LFB2296:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5getPIPdPm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2296:
.size _Z26__device_stub__Z5getPIPdPmPdPm, .-_Z26__device_stub__Z5getPIPdPmPdPm
.globl _Z5getPIPdPm
.type _Z5getPIPdPm, @function
_Z5getPIPdPm:
.LFB2297:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z5getPIPdPmPdPm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2297:
.size _Z5getPIPdPm, .-_Z5getPIPdPm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Type number of steps \n"
.LC1:
.string "%lu"
.LC2:
.string "cudaMalloc d_result failed!"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "cudaMalloc d_stepNumber failed!"
.align 8
.LC4:
.string "cudaMemcpy d_stepNumber failed!"
.section .rodata.str1.1
.LC5:
.string "addKernel launch failed: %s\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "cudaDeviceSynchronize returned error code %d after launching addKernel!\n"
.section .rodata.str1.1
.LC7:
.string "cudaMemcpy result failed!"
.LC8:
.string "Calculated PI is = %f.\n"
.LC10:
.string "a"
.LC11:
.string "plotData_1.txt"
.LC12:
.string "%d %f\n"
.text
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
call clock@PLT
movq %rax, %rbp
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq %rsp, %rdi
movl $8, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L24
leaq 8(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L25
leaq 16(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L26
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L16:
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L28
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L29
leaq 40(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L30
movsd 40(%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC9(%rip), %xmm0
movq %xmm0, %rbp
leaq .LC10(%rip), %rsi
leaq .LC11(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movq %rbp, %xmm0
movq 16(%rsp), %rcx
leaq .LC12(%rip), %r13
movq %r13, %rdx
movl $2, %esi
movq %rax, %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq %r12, %rdi
call fclose@PLT
movq %rbp, %xmm0
movq 16(%rsp), %rdx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L20
.L24:
movl %eax, %ebx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L13:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
.L20:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl %ebx, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L26:
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L27:
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z5getPIPdPmPdPm
jmp .L16
.L28:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L29:
movl %eax, %ecx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L30:
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z5getPIPdPm"
.LC14:
.string "precalc_xorwow_matrix"
.LC15:
.string "precalc_xorwow_offset_matrix"
.LC16:
.string "mrg32k3aM1"
.LC17:
.string "mrg32k3aM2"
.LC18:
.string "mrg32k3aM1SubSeq"
.LC19:
.string "mrg32k3aM2SubSeq"
.LC20:
.string "mrg32k3aM1Seq"
.LC21:
.string "mrg32k3aM2Seq"
.LC22:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2299:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z5getPIPdPm(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC9:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Monte_Carlo.hip"
.globl _Z20__device_stub__getPIPdPm # -- Begin function _Z20__device_stub__getPIPdPm
.p2align 4, 0x90
.type _Z20__device_stub__getPIPdPm,@function
_Z20__device_stub__getPIPdPm: # @_Z20__device_stub__getPIPdPm
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5getPIPdPm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z20__device_stub__getPIPdPm, .Lfunc_end0-_Z20__device_stub__getPIPdPm
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
callq clock
movq %rax, %rbx
movl $.Lstr, %edi
callq puts@PLT
movq %rsp, %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
leaq 16(%rsp), %rdi
movl $8, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $8, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_3
# %bb.6:
movq 8(%rsp), %rdi
movq %rsp, %rsi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_7
# %bb.8:
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 32(%rsp)
leaq 96(%rsp), %rax
movq %rax, 40(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z5getPIPdPm, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_11
# %bb.12:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_13
# %bb.14:
movq 16(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_15
# %bb.16:
movsd 32(%rsp), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.9, %edi
movb $1, %al
callq printf
xorl %ebp, %ebp
jmp .LBB1_17
.LBB1_1:
movl %eax, %ebp
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $26, %esi
jmp .LBB1_5
.LBB1_3:
movl %eax, %ebp
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
jmp .LBB1_4
.LBB1_7:
movl %eax, %ebp
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
.LBB1_4:
movl $30, %esi
jmp .LBB1_5
.LBB1_11:
movq stderr(%rip), %r14
movl %eax, %ebp
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_17
.LBB1_13:
movq stderr(%rip), %rdi
movl $.L.str.6, %esi
movl %eax, %ebp
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB1_17
.LBB1_15:
movl %eax, %ebp
movq stderr(%rip), %rcx
movl $.L.str.8, %edi
movl $24, %esi
.LBB1_5:
movl $1, %edx
callq fwrite@PLT
.LBB1_17:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl %ebp, %eax
testl %ebp, %ebp
jne .LBB1_19
# %bb.18:
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
movl $.L.str.10, %edi
movl $.L.str.11, %esi
callq fopen
movq %rax, %rbx
movq (%rsp), %rdx
movl $.L.str.12, %esi
movq %rax, %rdi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq fprintf
movq %rbx, %rdi
callq fclose
movq (%rsp), %rsi
movl $.L.str.12, %edi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl %ebp, %eax
.LBB1_19:
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5getPIPdPm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5getPIPdPm,@object # @_Z5getPIPdPm
.section .rodata,"a",@progbits
.globl _Z5getPIPdPm
.p2align 3, 0x0
_Z5getPIPdPm:
.quad _Z20__device_stub__getPIPdPm
.size _Z5getPIPdPm, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%lu"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipMalloc d_result failed!"
.size .L.str.2, 27
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipMalloc d_stepNumber failed!"
.size .L.str.3, 31
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMemcpy d_stepNumber failed!"
.size .L.str.4, 31
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "addKernel launch failed: %s\n"
.size .L.str.5, 29
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipDeviceSynchronize returned error code %d after launching addKernel!\n"
.size .L.str.6, 72
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "hipMemcpy result failed!"
.size .L.str.8, 25
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Calculated PI is = %f.\n"
.size .L.str.9, 24
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "plotData_1.txt"
.size .L.str.10, 15
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "a"
.size .L.str.11, 2
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "%d %f\n"
.size .L.str.12, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5getPIPdPm"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Type number of steps "
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__getPIPdPm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5getPIPdPm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#define min(a, b) ((a) < (b) ? (a) : (b))
#define num_threads 512
typedef unsigned char uint8_t;
struct Size{
int width = 0, height = 0;
Size() = default;
Size(int w, int h)
:width(w), height(h){}
};
// 计算仿射变换矩阵
// 计算的矩阵是居中缩放
struct AffineMatrix{
/*
建议先阅读代码，若有疑问，可点击抖音短视频进行辅助讲解(建议1.5倍速观看)
- https://v.douyin.com/Nhr5UdL/
*/
float i2d[6]; // image to dst(network), 2x3 matrix
float d2i[6]; // dst to image, 2x3 matrix
// 这里其实是求解imat的逆矩阵，由于这个3x3矩阵的第三行是确定的0, 0, 1，因此可以简写如下
void invertAffineTransform(float imat[6], float omat[6]){
float i00 = imat[0]; float i01 = imat[1]; float i02 = imat[2];
float i10 = imat[3]; float i11 = imat[4]; float i12 = imat[5];
// 计算行列式
float D = i00 * i11 - i01 * i10;
D = D != 0 ? 1.0 / D : 0;
// 计算剩余的伴随矩阵除以行列式
float A11 = i11 * D;
float A22 = i00 * D;
float A12 = -i01 * D;
float A21 = -i10 * D;
float b1 = -A11 * i02 - A12 * i12;
float b2 = -A21 * i02 - A22 * i12;
omat[0] = A11; omat[1] = A12; omat[2] = b1;
omat[3] = A21; omat[4] = A22; omat[5] = b2;
}
void compute(const Size& from, const Size& to){
float scale_x = to.width / (float)from.width;
float scale_y = to.height / (float)from.height;
// 这里取min的理由是
// 1. M矩阵是 from * M = to的方式进行映射，因此scale的分母一定是from
// 2. 取最小，即根据宽高比，算出最小的比例，如果取最大，则势必有一部分超出图像范围而被裁剪掉，这不是我们要的
// **
float scale = min(scale_x, scale_y); // 缩放比例辅助视频讲解 https://v.douyin.com/NhrH8Gm/
/**
这里的仿射变换矩阵实质上是2x3的矩阵，具体实现是
scale, 0, -scale * from.width * 0.5 + to.width * 0.5
0, scale, -scale * from.height * 0.5 + to.height * 0.5
这里可以想象成，是经历过缩放、平移、平移三次变换后的组合，M = TPS
例如第一个S矩阵，定义为把输入的from图像，等比缩放scale倍，到to尺度下
S = [
scale, 0, 0
0, scale, 0
0, 0, 1
]
P矩阵定义为第一次平移变换矩阵，将图像的原点，从左上角，移动到缩放(scale)后图像的中心上
P = [
1, 0, -scale * from.width * 0.5
0, 1, -scale * from.height * 0.5
0, 0, 1
]
T矩阵定义为第二次平移变换矩阵，将图像从原点移动到目标（to）图的中心上
T = [
1, 0, to.width * 0.5,
0, 1, to.height * 0.5,
0, 0, 1
]
通过将3个矩阵顺序乘起来，即可得到下面的表达式：
M = [
scale, 0, -scale * from.width * 0.5 + to.width * 0.5
0, scale, -scale * from.height * 0.5 + to.height * 0.5
0, 0, 1
]
去掉第三行就得到opencv需要的输入2x3矩阵
**/
/*
+ scale * 0.5 - 0.5 的主要原因是使得中心更加对齐，下采样不明显，但是上采样时就比较明显
参考：https://www.iteye.com/blog/handspeaker-1545126
*/
i2d[0] = scale; i2d[1] = 0; i2d[2] =
-scale * from.width * 0.5 + to.width * 0.5 + scale * 0.5 - 0.5;
i2d[3] = 0; i2d[4] = scale; i2d[5] =
-scale * from.height * 0.5 + to.height * 0.5 + scale * 0.5 - 0.5;
invertAffineTransform(i2d, d2i);
}
};
__device__ void affine_project(float* matrix, int x, int y, float* proj_x, float* proj_y){
// matrix
// m0, m1, m2
// m3, m4, m5
*proj_x = matrix[0] * x + matrix[1] * y + matrix[2];
*proj_y = matrix[3] * x + matrix[4] * y + matrix[5];
}
__global__ void warp_affine_bilinear_kernel(
uint8_t* src, int src_line_size, int src_width, int src_height,
uint8_t* dst, int dst_line_size, int dst_width, int dst_height,
uint8_t fill_value, AffineMatrix matrix
){
/*
建议先阅读代码，若有疑问，可点击抖音短视频进行辅助讲解(建议1.5倍速观看)
- https://v.douyin.com/Nhr4vTF/
*/
int dx = blockDim.x * blockIdx.x + threadIdx.x;
int dy = blockDim.y * blockIdx.y + threadIdx.y;
if (dx >= dst_width || dy >= dst_height) return;
float c0 = fill_value, c1 = fill_value, c2 = fill_value;
float src_x = 0; float src_y = 0;
affine_project(matrix.d2i, dx, dy, &src_x, &src_y);
/*
建议先阅读代码，若有疑问，可点击抖音短视频进行辅助讲解(建议1.5倍速观看)
- 双线性理论讲解：https://v.douyin.com/NhrH2tb/
- 代码代码：https://v.douyin.com/NhrBqpc/
*/
if(src_x < -1 || src_x >= src_width || src_y < -1 || src_y >= src_height){
// out of range
// src_x < -1时，其高位high_x < 0，超出范围
// src_x >= -1时，其高位high_x >= 0，存在取值
}else{
int y_low = floorf(src_y);
int x_low = floorf(src_x);
int y_high = y_low + 1;
int x_high = x_low + 1;
uint8_t const_values[] = {fill_value, fill_value, fill_value};
float ly = src_y - y_low;
float lx = src_x - x_low;
float hy = 1 - ly;
float hx = 1 - lx;
float w1 = hy * hx, w2 = hy * lx, w3 = ly * hx, w4 = ly * lx;
uint8_t* v1 = const_values;
uint8_t* v2 = const_values;
uint8_t* v3 = const_values;
uint8_t* v4 = const_values;
if(y_low >= 0){
if (x_low >= 0)
v1 = src + y_low * src_line_size + x_low * 3;
if (x_high < src_width)
v2 = src + y_low * src_line_size + x_high * 3;
}
if(y_high < src_height){
if (x_low >= 0)
v3 = src + y_high * src_line_size + x_low * 3;
if (x_high < src_width)
v4 = src + y_high * src_line_size + x_high * 3;
}
c0 = floorf(w1 * v1[0] + w2 * v2[0] + w3 * v3[0] + w4 * v4[0] + 0.5f);
c1 = floorf(w1 * v1[1] + w2 * v2[1] + w3 * v3[1] + w4 * v4[1] + 0.5f);
c2 = floorf(w1 * v1[2] + w2 * v2[2] + w3 * v3[2] + w4 * v4[2] + 0.5f);
}
uint8_t* pdst = dst + dy * dst_line_size + dx * 3;
pdst[0] = c0; pdst[1] = c1; pdst[2] = c2;
}
void warp_affine_bilinear(
/*
建议先阅读代码，若有疑问，可点击抖音短视频进行辅助讲解(建议1.5倍速观看)
- https://v.douyin.com/Nhre7fV/
*/
uint8_t* src, int src_line_size, int src_width, int src_height,
uint8_t* dst, int dst_line_size, int dst_width, int dst_height,
uint8_t fill_value
){
dim3 block_size(32, 32); // blocksize最大就是1024，这里用2d来看更好理解
dim3 grid_size((dst_width + 31) / 32, (dst_height + 31) / 32);
AffineMatrix affine;
affine.compute(Size(src_width, src_height), Size(dst_width, dst_height));
warp_affine_bilinear_kernel<<<grid_size, block_size, 0, nullptr>>>(
src, src_line_size, src_width, src_height,
dst, dst_line_size, dst_width, dst_height,
fill_value, affine
);
} | code for sm_80
Function : _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fc60000000f00 */
/*0010*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002600 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0040*/ S2R R12, SR_CTAID.X ; /* 0x00000000000c7919 */
/* 0x000e680000002500 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R9, R9, c[0x0][0x4], R0 ; /* 0x0000010009097a24 */
/* 0x001fca00078e0200 */
/*0070*/ ISETP.GE.AND P0, PT, R9, c[0x0][0x188], PT ; /* 0x0000620009007a0c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD R12, R12, c[0x0][0x0], R3 ; /* 0x000000000c0c7a24 */
/* 0x002fca00078e0203 */
/*0090*/ ISETP.GE.OR P0, PT, R12, c[0x0][0x184], P0 ; /* 0x000061000c007a0c */
/* 0x000fda0000706670 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ I2F R2, R9 ; /* 0x0000000900027306 */
/* 0x000e220000201400 */
/*00c0*/ LDC.U8 R10, c[0x0][0x18c] ; /* 0x00006300ff0a7b82 */
/* 0x000e620000000000 */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ BSSY B0, 0x8d0 ; /* 0x000007e000007945 */
/* 0x000fea0003800000 */
/*00f0*/ I2F R0, R12 ; /* 0x0000000c00007306 */
/* 0x000eb00000201400 */
/*0100*/ I2F R7, c[0x0][0x16c] ; /* 0x00005b0000077b06 */
/* 0x000ee20000201400 */
/*0110*/ FMUL R3, R2, c[0x0][0x1ac] ; /* 0x00006b0002037a20 */
/* 0x001fc40000400000 */
/*0120*/ FMUL R5, R2, c[0x0][0x1b8] ; /* 0x00006e0002057a20 */
/* 0x000fe20000400000 */
/*0130*/ IADD3 R2, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001027a10 */
/* 0x000fe20007f3e0ff */
/*0140*/ FFMA R3, R0, c[0x0][0x1a8], R3 ; /* 0x00006a0000037a23 */
/* 0x004fc60000000003 */
/*0150*/ I2F R4, c[0x0][0x170] ; /* 0x00005c0000047b06 */
/* 0x000e220000201400 */
/*0160*/ FFMA R5, R0, c[0x0][0x1b4], R5 ; /* 0x00006d0000057a23 */
/* 0x000fe40000000005 */
/*0170*/ FADD R14, R3, c[0x0][0x1b0] ; /* 0x00006c00030e7621 */
/* 0x000fe40000000000 */
/*0180*/ FADD R15, R5, c[0x0][0x1bc] ; /* 0x00006f00050f7621 */
/* 0x000fe40000000000 */
/*0190*/ IMAD.X R3, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff037624 */
/* 0x000fe200008e06ff */
/*01a0*/ FSETP.GE.AND P0, PT, R14.reuse, R7, PT ; /* 0x000000070e00720b */
/* 0x048fe20003f06000 */
/*01b0*/ I2F.U8 R16, R10 ; /* 0x0000000a00107306 */
/* 0x002e660000001000 */
/*01c0*/ FSETP.LT.OR P0, PT, R14, -1, P0 ; /* 0xbf8000000e00780b */
/* 0x000fc80000701400 */
/*01d0*/ FSETP.LT.OR P0, PT, R15, -1, P0 ; /* 0xbf8000000f00780b */
/* 0x000fc80000701400 */
/*01e0*/ FSETP.GE.OR P0, PT, R15, R4, P0 ; /* 0x000000040f00720b */
/* 0x001fe40000706400 */
/*01f0*/ MOV R0, R16 ; /* 0x0000001000007202 */
/* 0x002fe20000000f00 */
/*0200*/ IMAD.MOV.U32 R4, RZ, RZ, R16 ; /* 0x000000ffff047224 */
/* 0x000fd400078e0010 */
/*0210*/ @P0 BRA 0x8c0 ; /* 0x000006a000000947 */
/* 0x000fea0003800000 */
/*0220*/ F2I.FLOOR.NTZ R13, R15 ; /* 0x0000000f000d7305 */
/* 0x000e220000207100 */
/*0230*/ BSSY B1, 0x430 ; /* 0x000001f000017945 */
/* 0x000fe20003800000 */
/*0240*/ STL.U8 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x000fe20000100000 */
/*0250*/ MOV R6, R2.reuse ; /* 0x0000000200067202 */
/* 0x080fe20000000f00 */
/*0260*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0003 */
/*0270*/ MOV R4, R2 ; /* 0x0000000200047202 */
/* 0x000fe20000000f00 */
/*0280*/ STL.U8 [R1+0x1], R10 ; /* 0x0000010a01007387 */
/* 0x000fe20000100000 */
/*0290*/ MOV R5, R3.reuse ; /* 0x0000000300057202 */
/* 0x080fe20000000f00 */
/*02a0*/ F2I.FLOOR.NTZ R0, R14 ; /* 0x0000000e00007305 */
/* 0x000e620000207100 */
/*02b0*/ MOV R11, R3 ; /* 0x00000003000b7202 */
/* 0x000fe20000000f00 */
/*02c0*/ STL.U8 [R1+0x2], R10 ; /* 0x0000020a01007387 */
/* 0x0005e20000100000 */
/*02d0*/ ISETP.GE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x001fc40003f26270 */
/*02e0*/ IADD3 R8, R13, 0x1, RZ ; /* 0x000000010d087810 */
/* 0x000fe20007ffe0ff */
/*02f0*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x004fc600078e0002 */
/*0300*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */
/* 0x000fe40003f06270 */
/*0310*/ IADD3 R21, R0, 0x1, RZ ; /* 0x0000000100157810 */
/* 0x002fca0007ffe0ff */
/*0320*/ @!P1 BRA 0x420 ; /* 0x000000f000009947 */
/* 0x000fea0003800000 */
/*0330*/ ISETP.GE.AND P2, PT, R21, c[0x0][0x16c], PT ; /* 0x00005b0015007a0c */
/* 0x000fe40003f46270 */
/*0340*/ ISETP.GE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fd60003f26270 */
/*0350*/ @!P2 MOV R19, 0x3 ; /* 0x000000030013a802 */
/* 0x000fe20000000f00 */
/*0360*/ @!P2 IMAD R20, R13.reuse, c[0x0][0x168], RZ ; /* 0x00005a000d14aa24 */
/* 0x040fe400078e02ff */
/*0370*/ @P1 IMAD R17, R13, c[0x0][0x168], RZ ; /* 0x00005a000d111a24 */
/* 0x000fe400078e02ff */
/*0380*/ @P1 IMAD R18, R0.reuse, 0x3, RZ ; /* 0x0000000300121824 */
/* 0x040fe400078e02ff */
/*0390*/ @!P2 IMAD R19, R0, R19, 0x3 ; /* 0x000000030013a424 */
/* 0x000fc600078e0213 */
/*03a0*/ @P1 IADD3 R6, P3, P4, R18, c[0x0][0x160], R17.reuse ; /* 0x0000580012061a10 */
/* 0x100fe40007c7e011 */
/*03b0*/ @!P2 IADD3 R4, P5, P6, R19, c[0x0][0x160], R20 ; /* 0x000058001304aa10 */
/* 0x000fe40007ebe014 */
/*03c0*/ @P1 SHF.R.S32.HI R17, RZ, 0x1f, R17 ; /* 0x0000001fff111819 */
/* 0x000fe40000011411 */
/*03d0*/ @P1 SHF.R.S32.HI R18, RZ, 0x1f, R18 ; /* 0x0000001fff121819 */
/* 0x000fe40000011412 */
/*03e0*/ @!P2 SHF.R.S32.HI R20, RZ, 0x1f, R20 ; /* 0x0000001fff14a819 */
/* 0x000fe40000011414 */
/*03f0*/ @!P2 SHF.R.S32.HI R19, RZ, 0x1f, R19 ; /* 0x0000001fff13a819 */
/* 0x000fc40000011413 */
/*0400*/ @P1 IADD3.X R7, R18, c[0x0][0x164], R17, P3, P4 ; /* 0x0000590012071a10 */
/* 0x000fe40001fe8411 */
/*0410*/ @!P2 IADD3.X R5, R19, c[0x0][0x164], R20, P5, P6 ; /* 0x000059001305aa10 */
/* 0x000fe40002fec414 */
/*0420*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0430*/ BSSY B1, 0x5a0 ; /* 0x0000016000017945 */
/* 0x000fe20003800000 */
/*0440*/ @P0 BRA 0x590 ; /* 0x0000014000000947 */
/* 0x000fea0003800000 */
/*0450*/ ISETP.GE.AND P1, PT, R21, c[0x0][0x16c], PT ; /* 0x00005b0015007a0c */
/* 0x000fe40003f26270 */
/*0460*/ MOV R10, R2 ; /* 0x00000002000a7202 */
/* 0x000fd60000000f00 */
/*0470*/ @!P1 IMAD.MOV.U32 R11, RZ, RZ, 0x3 ; /* 0x00000003ff0b9424 */
/* 0x000fe400078e00ff */
/*0480*/ @!P1 IMAD R17, R8, c[0x0][0x168], RZ ; /* 0x00005a0008119a24 */
/* 0x000fe400078e02ff */
/*0490*/ @!P1 IMAD R19, R0, R11, 0x3 ; /* 0x0000000300139424 */
/* 0x000fe200078e020b */
/*04a0*/ MOV R11, R3 ; /* 0x00000003000b7202 */
/* 0x000fe40000000f00 */
/*04b0*/ @!P1 SHF.R.S32.HI R18, RZ, 0x1f, R17 ; /* 0x0000001fff129819 */
/* 0x000fe40000011411 */
/*04c0*/ @!P1 IADD3 R17, P0, R19, R17, RZ ; /* 0x0000001113119210 */
/* 0x000fc80007f1e0ff */
/*04d0*/ @!P1 LEA.HI.X.SX32 R18, R19, R18, 0x1, P0 ; /* 0x0000001213129211 */
/* 0x000fe400000f0eff */
/*04e0*/ @!P1 IADD3 R10, P0, R17, c[0x0][0x160], RZ ; /* 0x00005800110a9a10 */
/* 0x000fc80007f1e0ff */
/*04f0*/ @!P1 IADD3.X R11, R18, c[0x0][0x164], RZ, P0, !PT ; /* 0x00005900120b9a10 */
/* 0x000fca00007fe4ff */
/*0500*/ @!P1 LDG.E.U8 R17, [R10.64] ; /* 0x000000040a119981 */
/* 0x000ea2000c1e1100 */
/*0510*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f46270 */
/*0520*/ @P2 IMAD R8, R8, c[0x0][0x168], RZ ; /* 0x00005a0008082a24 */
/* 0x000fe400078e02ff */
/*0530*/ @P2 IMAD R19, R0, 0x3, RZ ; /* 0x0000000300132824 */
/* 0x000fe200078e02ff */
/*0540*/ @!P1 I2F.U16 R16, R17 ; /* 0x0000001100109306 */
/* 0x0040680000101000 */
/*0550*/ @P2 IADD3 R2, P0, P1, R19, c[0x0][0x160], R8.reuse ; /* 0x0000580013022a10 */
/* 0x100fe4000791e008 */
/*0560*/ @P2 SHF.R.S32.HI R8, RZ, 0x1f, R8 ; /* 0x0000001fff082819 */
/* 0x000fe40000011408 */
/*0570*/ @P2 SHF.R.S32.HI R19, RZ, 0x1f, R19 ; /* 0x0000001fff132819 */
/* 0x000fc80000011413 */
/*0580*/ @P2 IADD3.X R3, R19, c[0x0][0x164], R8, P0, P1 ; /* 0x0000590013032a10 */
/* 0x000fe400007e2408 */
/*0590*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x001fea0003800000 */
/*05a0*/ LD.E.U8 R18, [R4.64] ; /* 0x0000000404127980 */
/* 0x0000a8000c101100 */
/*05b0*/ LD.E.U8 R19, [R4.64+0x1] ; /* 0x0000010404137980 */
/* 0x0000e8000c101100 */
/*05c0*/ LD.E.U8 R21, [R4.64+0x2] ; /* 0x0000020404157980 */
/* 0x000128000c101100 */
/*05d0*/ LD.E.U8 R17, [R6.64] ; /* 0x0000000406117980 */
/* 0x000b28000c101100 */
/*05e0*/ LD.E.U8 R8, [R6.64+0x1] ; /* 0x0000010406087980 */
/* 0x000b28000c101100 */
/*05f0*/ LD.E.U8 R20, [R6.64+0x2] ; /* 0x0000020406147980 */
/* 0x000b28000c101100 */
/*0600*/ LD.E.U8 R23, [R2.64] ; /* 0x0000000402177980 */
/* 0x000328000c101100 */
/*0610*/ LD.E.U8 R22, [R2.64+0x1] ; /* 0x0000010402167980 */
/* 0x000328000c101100 */
/*0620*/ LD.E.U8 R24, [R2.64+0x2] ; /* 0x0000020402187980 */
/* 0x000328000c101100 */
/*0630*/ LD.E.U8 R25, [R10.64+0x1] ; /* 0x000001040a197980 */
/* 0x000f28000c101100 */
/*0640*/ LD.E.U8 R26, [R10.64+0x2] ; /* 0x000002040a1a7980 */
/* 0x000f22000c101100 */
/*0650*/ I2F R28, R13 ; /* 0x0000000d001c7306 */
/* 0x000e300000201400 */
/*0660*/ I2F R7, R0 ; /* 0x0000000000077306 */
/* 0x020f620000201400 */
/*0670*/ FADD R28, R15, -R28 ; /* 0x8000001c0f1c7221 */
/* 0x001fc80000000000 */
/*0680*/ FADD R2, -R28, 1 ; /* 0x3f8000001c027421 */
/* 0x002fe40000000100 */
/*0690*/ FADD R7, R14, -R7 ; /* 0x800000070e077221 */
/* 0x020fc80000000000 */
/*06a0*/ FADD R5, -R7.reuse, 1 ; /* 0x3f80000007057421 */
/* 0x040fe40000000100 */
/*06b0*/ FMUL R0, R7, R2 ; /* 0x0000000207007220 */
/* 0x000fe40000400000 */
/*06c0*/ FMUL R3, R2, R5.reuse ; /* 0x0000000502037220 */
/* 0x080fe40000400000 */
/*06d0*/ FMUL R5, R28.reuse, R5 ; /* 0x000000051c057220 */
/* 0x040fe40000400000 */
/*06e0*/ FMUL R7, R28, R7 ; /* 0x000000071c077220 */
/* 0x000fe20000400000 */
/*06f0*/ I2F.U16 R18, R18 ; /* 0x0000001200127306 */
/* 0x004e300000101000 */
/*0700*/ I2F.U16 R19, R19 ; /* 0x0000001300137306 */
/* 0x008e700000101000 */
/*0710*/ I2F.U16 R21, R21 ; /* 0x0000001500157306 */
/* 0x010eb00000101000 */
/*0720*/ I2F.U16 R17, R17 ; /* 0x0000001100117306 */
/* 0x000ef00000101000 */
/*0730*/ I2F.U16 R8, R8 ; /* 0x0000000800087306 */
/* 0x000f300000101000 */
/*0740*/ I2F.U16 R20, R20 ; /* 0x0000001400147306 */
/* 0x000f700000101000 */
/*0750*/ I2F.U16 R23, R23 ; /* 0x0000001700177306 */
/* 0x000e300000101000 */
/*0760*/ I2F.U16 R22, R22 ; /* 0x0000001600167306 */
/* 0x000eb00000101000 */
/*0770*/ I2F.U16 R24, R24 ; /* 0x0000001800187306 */
/* 0x000ee20000101000 */
/*0780*/ FMUL R18, R0, R18 ; /* 0x0000001200127220 */
/* 0x001fc40000400000 */
/*0790*/ FMUL R19, R0, R19 ; /* 0x0000001300137220 */
/* 0x002fca0000400000 */
/*07a0*/ I2F.U16 R25, R25 ; /* 0x0000001900197306 */
/* 0x000e220000101000 */
/*07b0*/ FMUL R21, R0, R21 ; /* 0x0000001500157220 */
/* 0x004fce0000400000 */
/*07c0*/ I2F.U16 R26, R26 ; /* 0x0000001a001a7306 */
/* 0x000e620000101000 */
/*07d0*/ FFMA R18, R3.reuse, R17, R18 ; /* 0x0000001103127223 */
/* 0x048fe40000000012 */
/*07e0*/ FFMA R8, R3.reuse, R8, R19 ; /* 0x0000000803087223 */
/* 0x050fe40000000013 */
/*07f0*/ FFMA R20, R3, R20, R21 ; /* 0x0000001403147223 */
/* 0x020fe40000000015 */
/*0800*/ FFMA R18, R5.reuse, R23, R18 ; /* 0x0000001705127223 */
/* 0x040fe40000000012 */
/*0810*/ FFMA R8, R5.reuse, R22, R8 ; /* 0x0000001605087223 */
/* 0x040fe40000000008 */
/*0820*/ FFMA R20, R5, R24, R20 ; /* 0x0000001805147223 */
/* 0x000fc40000000014 */
/*0830*/ FFMA R18, R7.reuse, R16, R18 ; /* 0x0000001007127223 */
/* 0x040fe40000000012 */
/*0840*/ FFMA R8, R7.reuse, R25, R8 ; /* 0x0000001907087223 */
/* 0x041fe40000000008 */
/*0850*/ FFMA R20, R7, R26, R20 ; /* 0x0000001a07147223 */
/* 0x002fe40000000014 */
/*0860*/ FADD R18, R18, 0.5 ; /* 0x3f00000012127421 */
/* 0x000fe40000000000 */
/*0870*/ FADD R8, R8, 0.5 ; /* 0x3f00000008087421 */
/* 0x000fe40000000000 */
/*0880*/ FADD R20, R20, 0.5 ; /* 0x3f00000014147421 */
/* 0x000fe20000000000 */
/*0890*/ FRND.FLOOR R16, R18 ; /* 0x0000001200107307 */
/* 0x0000700000205000 */
/*08a0*/ FRND.FLOOR R0, R8 ; /* 0x0000000800007307 */
/* 0x0000b00000205000 */
/*08b0*/ FRND.FLOOR R4, R20 ; /* 0x0000001400047307 */
/* 0x0000e40000205000 */
/*08c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*08d0*/ IMAD R2, R9, c[0x0][0x180], RZ ; /* 0x0000600009027a24 */
/* 0x000fe200078e02ff */
/*08e0*/ F2I.U32.TRUNC.NTZ R5, R16 ; /* 0x0000001000057305 */
/* 0x000e62000020f000 */
/*08f0*/ IMAD R3, R12, 0x3, RZ ; /* 0x000000030c037824 */
/* 0x000fc600078e02ff */
/*0900*/ SHF.R.S32.HI R6, RZ, 0x1f, R2 ; /* 0x0000001fff067819 */
/* 0x000fe40000011402 */
/*0910*/ IADD3 R2, P0, P1, R2, c[0x0][0x178], R3.reuse ; /* 0x00005e0002027a10 */
/* 0x100fe4000791e003 */
/*0920*/ F2I.U32.TRUNC.NTZ R7, R0 ; /* 0x0000000000077305 */
/* 0x004ea2000020f000 */
/*0930*/ SHF.R.S32.HI R3, RZ, 0x1f, R3 ; /* 0x0000001fff037819 */
/* 0x000fc80000011403 */
/*0940*/ IADD3.X R3, R6, c[0x0][0x17c], R3, P0, P1 ; /* 0x00005f0006037a10 */
/* 0x000fc600007e2403 */
/*0950*/ F2I.U32.TRUNC.NTZ R9, R4 ; /* 0x0000000400097305 */
/* 0x008ee4000020f000 */
/*0960*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe8000c101104 */
/*0970*/ STG.E.U8 [R2.64+0x1], R7 ; /* 0x0000010702007986 */
/* 0x004fe8000c101104 */
/*0980*/ STG.E.U8 [R2.64+0x2], R9 ; /* 0x0000020902007986 */
/* 0x008fe2000c101104 */
/*0990*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09a0*/ BRA 0x9a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#define min(a, b) ((a) < (b) ? (a) : (b))
#define num_threads 512
typedef unsigned char uint8_t;
struct Size{
int width = 0, height = 0;
Size() = default;
Size(int w, int h)
:width(w), height(h){}
};
// 计算仿射变换矩阵
// 计算的矩阵是居中缩放
struct AffineMatrix{
/*
建议先阅读代码，若有疑问，可点击抖音短视频进行辅助讲解(建议1.5倍速观看)
- https://v.douyin.com/Nhr5UdL/
*/
float i2d[6]; // image to dst(network), 2x3 matrix
float d2i[6]; // dst to image, 2x3 matrix
// 这里其实是求解imat的逆矩阵，由于这个3x3矩阵的第三行是确定的0, 0, 1，因此可以简写如下
void invertAffineTransform(float imat[6], float omat[6]){
float i00 = imat[0]; float i01 = imat[1]; float i02 = imat[2];
float i10 = imat[3]; float i11 = imat[4]; float i12 = imat[5];
// 计算行列式
float D = i00 * i11 - i01 * i10;
D = D != 0 ? 1.0 / D : 0;
// 计算剩余的伴随矩阵除以行列式
float A11 = i11 * D;
float A22 = i00 * D;
float A12 = -i01 * D;
float A21 = -i10 * D;
float b1 = -A11 * i02 - A12 * i12;
float b2 = -A21 * i02 - A22 * i12;
omat[0] = A11; omat[1] = A12; omat[2] = b1;
omat[3] = A21; omat[4] = A22; omat[5] = b2;
}
void compute(const Size& from, const Size& to){
float scale_x = to.width / (float)from.width;
float scale_y = to.height / (float)from.height;
// 这里取min的理由是
// 1. M矩阵是 from * M = to的方式进行映射，因此scale的分母一定是from
// 2. 取最小，即根据宽高比，算出最小的比例，如果取最大，则势必有一部分超出图像范围而被裁剪掉，这不是我们要的
// **
float scale = min(scale_x, scale_y); // 缩放比例辅助视频讲解 https://v.douyin.com/NhrH8Gm/
/**
这里的仿射变换矩阵实质上是2x3的矩阵，具体实现是
scale, 0, -scale * from.width * 0.5 + to.width * 0.5
0, scale, -scale * from.height * 0.5 + to.height * 0.5
这里可以想象成，是经历过缩放、平移、平移三次变换后的组合，M = TPS
例如第一个S矩阵，定义为把输入的from图像，等比缩放scale倍，到to尺度下
S = [
scale, 0, 0
0, scale, 0
0, 0, 1
]
P矩阵定义为第一次平移变换矩阵，将图像的原点，从左上角，移动到缩放(scale)后图像的中心上
P = [
1, 0, -scale * from.width * 0.5
0, 1, -scale * from.height * 0.5
0, 0, 1
]
T矩阵定义为第二次平移变换矩阵，将图像从原点移动到目标（to）图的中心上
T = [
1, 0, to.width * 0.5,
0, 1, to.height * 0.5,
0, 0, 1
]
通过将3个矩阵顺序乘起来，即可得到下面的表达式：
M = [
scale, 0, -scale * from.width * 0.5 + to.width * 0.5
0, scale, -scale * from.height * 0.5 + to.height * 0.5
0, 0, 1
]
去掉第三行就得到opencv需要的输入2x3矩阵
**/
/*
+ scale * 0.5 - 0.5 的主要原因是使得中心更加对齐，下采样不明显，但是上采样时就比较明显
参考：https://www.iteye.com/blog/handspeaker-1545126
*/
i2d[0] = scale; i2d[1] = 0; i2d[2] =
-scale * from.width * 0.5 + to.width * 0.5 + scale * 0.5 - 0.5;
i2d[3] = 0; i2d[4] = scale; i2d[5] =
-scale * from.height * 0.5 + to.height * 0.5 + scale * 0.5 - 0.5;
invertAffineTransform(i2d, d2i);
}
};
__device__ void affine_project(float* matrix, int x, int y, float* proj_x, float* proj_y){
// matrix
// m0, m1, m2
// m3, m4, m5
*proj_x = matrix[0] * x + matrix[1] * y + matrix[2];
*proj_y = matrix[3] * x + matrix[4] * y + matrix[5];
}
__global__ void warp_affine_bilinear_kernel(
uint8_t* src, int src_line_size, int src_width, int src_height,
uint8_t* dst, int dst_line_size, int dst_width, int dst_height,
uint8_t fill_value, AffineMatrix matrix
){
/*
建议先阅读代码，若有疑问，可点击抖音短视频进行辅助讲解(建议1.5倍速观看)
- https://v.douyin.com/Nhr4vTF/
*/
int dx = blockDim.x * blockIdx.x + threadIdx.x;
int dy = blockDim.y * blockIdx.y + threadIdx.y;
if (dx >= dst_width || dy >= dst_height) return;
float c0 = fill_value, c1 = fill_value, c2 = fill_value;
float src_x = 0; float src_y = 0;
affine_project(matrix.d2i, dx, dy, &src_x, &src_y);
/*
建议先阅读代码，若有疑问，可点击抖音短视频进行辅助讲解(建议1.5倍速观看)
- 双线性理论讲解：https://v.douyin.com/NhrH2tb/
- 代码代码：https://v.douyin.com/NhrBqpc/
*/
if(src_x < -1 || src_x >= src_width || src_y < -1 || src_y >= src_height){
// out of range
// src_x < -1时，其高位high_x < 0，超出范围
// src_x >= -1时，其高位high_x >= 0，存在取值
}else{
int y_low = floorf(src_y);
int x_low = floorf(src_x);
int y_high = y_low + 1;
int x_high = x_low + 1;
uint8_t const_values[] = {fill_value, fill_value, fill_value};
float ly = src_y - y_low;
float lx = src_x - x_low;
float hy = 1 - ly;
float hx = 1 - lx;
float w1 = hy * hx, w2 = hy * lx, w3 = ly * hx, w4 = ly * lx;
uint8_t* v1 = const_values;
uint8_t* v2 = const_values;
uint8_t* v3 = const_values;
uint8_t* v4 = const_values;
if(y_low >= 0){
if (x_low >= 0)
v1 = src + y_low * src_line_size + x_low * 3;
if (x_high < src_width)
v2 = src + y_low * src_line_size + x_high * 3;
}
if(y_high < src_height){
if (x_low >= 0)
v3 = src + y_high * src_line_size + x_low * 3;
if (x_high < src_width)
v4 = src + y_high * src_line_size + x_high * 3;
}
c0 = floorf(w1 * v1[0] + w2 * v2[0] + w3 * v3[0] + w4 * v4[0] + 0.5f);
c1 = floorf(w1 * v1[1] + w2 * v2[1] + w3 * v3[1] + w4 * v4[1] + 0.5f);
c2 = floorf(w1 * v1[2] + w2 * v2[2] + w3 * v3[2] + w4 * v4[2] + 0.5f);
}
uint8_t* pdst = dst + dy * dst_line_size + dx * 3;
pdst[0] = c0; pdst[1] = c1; pdst[2] = c2;
}
void warp_affine_bilinear(
/*
建议先阅读代码，若有疑问，可点击抖音短视频进行辅助讲解(建议1.5倍速观看)
- https://v.douyin.com/Nhre7fV/
*/
uint8_t* src, int src_line_size, int src_width, int src_height,
uint8_t* dst, int dst_line_size, int dst_width, int dst_height,
uint8_t fill_value
){
dim3 block_size(32, 32); // blocksize最大就是1024，这里用2d来看更好理解
dim3 grid_size((dst_width + 31) / 32, (dst_height + 31) / 32);
AffineMatrix affine;
affine.compute(Size(src_width, src_height), Size(dst_width, dst_height));
warp_affine_bilinear_kernel<<<grid_size, block_size, 0, nullptr>>>(
src, src_line_size, src_width, src_height,
dst, dst_line_size, dst_width, dst_height,
fill_value, affine
);
} | .file "tmpxft_000c5cd3_00000000-6_affine.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2036:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2036:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14affine_projectPfiiS_S_
.type _Z14affine_projectPfiiS_S_, @function
_Z14affine_projectPfiiS_S_:
.LFB2032:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2032:
.size _Z14affine_projectPfiiS_S_, .-_Z14affine_projectPfiiS_S_
.globl _Z70__device_stub__Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrixPhiiiS_iiihR12AffineMatrix
.type _Z70__device_stub__Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrixPhiiiS_iiihR12AffineMatrix, @function
_Z70__device_stub__Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrixPhiiiS_iiihR12AffineMatrix:
.LFB2058:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movl %ecx, 28(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 24(%rsp)
movl 240(%rsp), %eax
movb %al, 12(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
movq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z70__device_stub__Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrixPhiiiS_iiihR12AffineMatrix, .-_Z70__device_stub__Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrixPhiiiS_iiihR12AffineMatrix
.globl _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.type _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix, @function
_Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 40(%rsp), %rax
pushq %rax
.cfi_def_cfa_offset 24
movzbl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z70__device_stub__Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrixPhiiiS_iiihR12AffineMatrix
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix, .-_Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.globl _Z20warp_affine_bilinearPhiiiS_iiih
.type _Z20warp_affine_bilinearPhiiiS_iiih, @function
_Z20warp_affine_bilinearPhiiiS_iiih:
.LFB2033:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 24(%rsp)
movl %esi, 36(%rsp)
movl %edx, %r13d
movl %ecx, %r12d
movq %r8, 40(%rsp)
movl %r9d, %r14d
movl 208(%rsp), %ebx
movl 216(%rsp), %ebp
movl 224(%rsp), %r15d
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $32, 56(%rsp)
movl $32, 60(%rsp)
movl $1, 64(%rsp)
leal 62(%rbx), %eax
movl %ebx, %edx
addl $31, %edx
cmovns %edx, %eax
sarl $5, %eax
movl %eax, 68(%rsp)
leal 62(%rbp), %eax
movl %ebp, %edx
addl $31, %edx
cmovns %edx, %eax
sarl $5, %eax
movl %eax, 72(%rsp)
movl $1, 76(%rsp)
pxor %xmm6, %xmm6
cvtsi2ssl %r13d, %xmm6
movss %xmm6, 16(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
divss %xmm6, %xmm0
pxor %xmm3, %xmm3
cvtsi2ssl %ecx, %xmm3
movss %xmm3, 20(%rsp)
pxor %xmm1, %xmm1
cvtsi2ssl %ebp, %xmm1
divss %xmm3, %xmm1
minss %xmm1, %xmm0
movss %xmm0, 32(%rsp)
mulss %xmm0, %xmm0
pxor %xmm1, %xmm1
ucomiss %xmm1, %xmm0
jp .L22
movss %xmm1, 12(%rsp)
jne .L22
.L16:
movl 64(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movq 68(%rsp), %rdi
movl 76(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L13:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movss .LC1(%rip), %xmm1
divss %xmm0, %xmm1
movss %xmm1, 12(%rsp)
jmp .L16
.L24:
movss .LC2(%rip), %xmm3
movss 32(%rsp), %xmm6
movaps %xmm6, %xmm1
xorps %xmm3, %xmm1
pxor %xmm5, %xmm5
cvtss2sd %xmm6, %xmm5
movsd .LC3(%rip), %xmm4
mulsd %xmm4, %xmm5
movss 16(%rsp), %xmm2
mulss %xmm1, %xmm2
cvtss2sd %xmm2, %xmm2
mulsd %xmm4, %xmm2
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
mulsd %xmm4, %xmm0
addsd %xmm0, %xmm2
addsd %xmm5, %xmm2
subsd %xmm4, %xmm2
cvtsd2ss %xmm2, %xmm2
mulss 20(%rsp), %xmm1
cvtss2sd %xmm1, %xmm1
mulsd %xmm4, %xmm1
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd %xmm4, %xmm0
addsd %xmm1, %xmm0
addsd %xmm5, %xmm0
subsd %xmm4, %xmm0
cvtsd2ss %xmm0, %xmm0
movaps %xmm6, %xmm5
movss 12(%rsp), %xmm4
mulss %xmm4, %xmm5
mulss .LC4(%rip), %xmm4
movaps %xmm4, %xmm1
movss %xmm6, 80(%rsp)
movl $0x00000000, 84(%rsp)
movss %xmm2, 88(%rsp)
movl $0x00000000, 92(%rsp)
movss %xmm6, 96(%rsp)
movss %xmm0, 100(%rsp)
movss %xmm5, 104(%rsp)
movss %xmm4, 108(%rsp)
movaps %xmm5, %xmm4
xorps %xmm3, %xmm4
mulss %xmm2, %xmm4
movaps %xmm0, %xmm6
mulss %xmm1, %xmm6
subss %xmm6, %xmm4
movss %xmm4, 112(%rsp)
movss %xmm1, 116(%rsp)
movss %xmm5, 120(%rsp)
xorps %xmm3, %xmm1
mulss %xmm2, %xmm1
mulss %xmm5, %xmm0
subss %xmm0, %xmm1
movss %xmm1, 124(%rsp)
leaq 80(%rsp), %rax
pushq %rax
.cfi_def_cfa_offset 216
movzbl %r15b, %r15d
pushq %r15
.cfi_def_cfa_offset 224
pushq %rbp
.cfi_def_cfa_offset 232
pushq %rbx
.cfi_def_cfa_offset 240
movl %r14d, %r9d
movq 72(%rsp), %r8
movl %r12d, %ecx
movl %r13d, %edx
movl 68(%rsp), %esi
movq 56(%rsp), %rdi
call _Z70__device_stub__Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrixPhiiiS_iiihR12AffineMatrix
addq $32, %rsp
.cfi_def_cfa_offset 208
jmp .L13
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2033:
.size _Z20warp_affine_bilinearPhiiiS_iiih, .-_Z20warp_affine_bilinearPhiiiS_iiih
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC2:
.long -2147483648
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1071644672
.set .LC4,.LC2
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#define min(a, b) ((a) < (b) ? (a) : (b))
#define num_threads 512
typedef unsigned char uint8_t;
struct Size{
int width = 0, height = 0;
Size() = default;
Size(int w, int h)
:width(w), height(h){}
};
// 计算仿射变换矩阵
// 计算的矩阵是居中缩放
struct AffineMatrix{
/*
建议先阅读代码，若有疑问，可点击抖音短视频进行辅助讲解(建议1.5倍速观看)
- https://v.douyin.com/Nhr5UdL/
*/
float i2d[6]; // image to dst(network), 2x3 matrix
float d2i[6]; // dst to image, 2x3 matrix
// 这里其实是求解imat的逆矩阵，由于这个3x3矩阵的第三行是确定的0, 0, 1，因此可以简写如下
void invertAffineTransform(float imat[6], float omat[6]){
float i00 = imat[0]; float i01 = imat[1]; float i02 = imat[2];
float i10 = imat[3]; float i11 = imat[4]; float i12 = imat[5];
// 计算行列式
float D = i00 * i11 - i01 * i10;
D = D != 0 ? 1.0 / D : 0;
// 计算剩余的伴随矩阵除以行列式
float A11 = i11 * D;
float A22 = i00 * D;
float A12 = -i01 * D;
float A21 = -i10 * D;
float b1 = -A11 * i02 - A12 * i12;
float b2 = -A21 * i02 - A22 * i12;
omat[0] = A11; omat[1] = A12; omat[2] = b1;
omat[3] = A21; omat[4] = A22; omat[5] = b2;
}
void compute(const Size& from, const Size& to){
float scale_x = to.width / (float)from.width;
float scale_y = to.height / (float)from.height;
// 这里取min的理由是
// 1. M矩阵是 from * M = to的方式进行映射，因此scale的分母一定是from
// 2. 取最小，即根据宽高比，算出最小的比例，如果取最大，则势必有一部分超出图像范围而被裁剪掉，这不是我们要的
// **
float scale = min(scale_x, scale_y); // 缩放比例辅助视频讲解 https://v.douyin.com/NhrH8Gm/
/**
这里的仿射变换矩阵实质上是2x3的矩阵，具体实现是
scale, 0, -scale * from.width * 0.5 + to.width * 0.5
0, scale, -scale * from.height * 0.5 + to.height * 0.5
这里可以想象成，是经历过缩放、平移、平移三次变换后的组合，M = TPS
例如第一个S矩阵，定义为把输入的from图像，等比缩放scale倍，到to尺度下
S = [
scale, 0, 0
0, scale, 0
0, 0, 1
]
P矩阵定义为第一次平移变换矩阵，将图像的原点，从左上角，移动到缩放(scale)后图像的中心上
P = [
1, 0, -scale * from.width * 0.5
0, 1, -scale * from.height * 0.5
0, 0, 1
]
T矩阵定义为第二次平移变换矩阵，将图像从原点移动到目标（to）图的中心上
T = [
1, 0, to.width * 0.5,
0, 1, to.height * 0.5,
0, 0, 1
]
通过将3个矩阵顺序乘起来，即可得到下面的表达式：
M = [
scale, 0, -scale * from.width * 0.5 + to.width * 0.5
0, scale, -scale * from.height * 0.5 + to.height * 0.5
0, 0, 1
]
去掉第三行就得到opencv需要的输入2x3矩阵
**/
/*
+ scale * 0.5 - 0.5 的主要原因是使得中心更加对齐，下采样不明显，但是上采样时就比较明显
参考：https://www.iteye.com/blog/handspeaker-1545126
*/
i2d[0] = scale; i2d[1] = 0; i2d[2] =
-scale * from.width * 0.5 + to.width * 0.5 + scale * 0.5 - 0.5;
i2d[3] = 0; i2d[4] = scale; i2d[5] =
-scale * from.height * 0.5 + to.height * 0.5 + scale * 0.5 - 0.5;
invertAffineTransform(i2d, d2i);
}
};
__device__ void affine_project(float* matrix, int x, int y, float* proj_x, float* proj_y){
// matrix
// m0, m1, m2
// m3, m4, m5
*proj_x = matrix[0] * x + matrix[1] * y + matrix[2];
*proj_y = matrix[3] * x + matrix[4] * y + matrix[5];
}
__global__ void warp_affine_bilinear_kernel(
uint8_t* src, int src_line_size, int src_width, int src_height,
uint8_t* dst, int dst_line_size, int dst_width, int dst_height,
uint8_t fill_value, AffineMatrix matrix
){
/*
建议先阅读代码，若有疑问，可点击抖音短视频进行辅助讲解(建议1.5倍速观看)
- https://v.douyin.com/Nhr4vTF/
*/
int dx = blockDim.x * blockIdx.x + threadIdx.x;
int dy = blockDim.y * blockIdx.y + threadIdx.y;
if (dx >= dst_width || dy >= dst_height) return;
float c0 = fill_value, c1 = fill_value, c2 = fill_value;
float src_x = 0; float src_y = 0;
affine_project(matrix.d2i, dx, dy, &src_x, &src_y);
/*
建议先阅读代码，若有疑问，可点击抖音短视频进行辅助讲解(建议1.5倍速观看)
- 双线性理论讲解：https://v.douyin.com/NhrH2tb/
- 代码代码：https://v.douyin.com/NhrBqpc/
*/
if(src_x < -1 || src_x >= src_width || src_y < -1 || src_y >= src_height){
// out of range
// src_x < -1时，其高位high_x < 0，超出范围
// src_x >= -1时，其高位high_x >= 0，存在取值
}else{
int y_low = floorf(src_y);
int x_low = floorf(src_x);
int y_high = y_low + 1;
int x_high = x_low + 1;
uint8_t const_values[] = {fill_value, fill_value, fill_value};
float ly = src_y - y_low;
float lx = src_x - x_low;
float hy = 1 - ly;
float hx = 1 - lx;
float w1 = hy * hx, w2 = hy * lx, w3 = ly * hx, w4 = ly * lx;
uint8_t* v1 = const_values;
uint8_t* v2 = const_values;
uint8_t* v3 = const_values;
uint8_t* v4 = const_values;
if(y_low >= 0){
if (x_low >= 0)
v1 = src + y_low * src_line_size + x_low * 3;
if (x_high < src_width)
v2 = src + y_low * src_line_size + x_high * 3;
}
if(y_high < src_height){
if (x_low >= 0)
v3 = src + y_high * src_line_size + x_low * 3;
if (x_high < src_width)
v4 = src + y_high * src_line_size + x_high * 3;
}
c0 = floorf(w1 * v1[0] + w2 * v2[0] + w3 * v3[0] + w4 * v4[0] + 0.5f);
c1 = floorf(w1 * v1[1] + w2 * v2[1] + w3 * v3[1] + w4 * v4[1] + 0.5f);
c2 = floorf(w1 * v1[2] + w2 * v2[2] + w3 * v3[2] + w4 * v4[2] + 0.5f);
}
uint8_t* pdst = dst + dy * dst_line_size + dx * 3;
pdst[0] = c0; pdst[1] = c1; pdst[2] = c2;
}
void warp_affine_bilinear(
/*
建议先阅读代码，若有疑问，可点击抖音短视频进行辅助讲解(建议1.5倍速观看)
- https://v.douyin.com/Nhre7fV/
*/
uint8_t* src, int src_line_size, int src_width, int src_height,
uint8_t* dst, int dst_line_size, int dst_width, int dst_height,
uint8_t fill_value
){
dim3 block_size(32, 32); // blocksize最大就是1024，这里用2d来看更好理解
dim3 grid_size((dst_width + 31) / 32, (dst_height + 31) / 32);
AffineMatrix affine;
affine.compute(Size(src_width, src_height), Size(dst_width, dst_height));
warp_affine_bilinear_kernel<<<grid_size, block_size, 0, nullptr>>>(
src, src_line_size, src_width, src_height,
dst, dst_line_size, dst_width, dst_height,
fill_value, affine
);
} | #include <hip/hip_runtime.h>
#define min(a, b) ((a) < (b) ? (a) : (b))
#define num_threads 512
typedef unsigned char uint8_t;
struct Size{
int width = 0, height = 0;
Size() = default;
Size(int w, int h)
:width(w), height(h){}
};
// 计算仿射变换矩阵
// 计算的矩阵是居中缩放
struct AffineMatrix{
/*
建议先阅读代码，若有疑问，可点击抖音短视频进行辅助讲解(建议1.5倍速观看)
- https://v.douyin.com/Nhr5UdL/
*/
float i2d[6]; // image to dst(network), 2x3 matrix
float d2i[6]; // dst to image, 2x3 matrix
// 这里其实是求解imat的逆矩阵，由于这个3x3矩阵的第三行是确定的0, 0, 1，因此可以简写如下
void invertAffineTransform(float imat[6], float omat[6]){
float i00 = imat[0]; float i01 = imat[1]; float i02 = imat[2];
float i10 = imat[3]; float i11 = imat[4]; float i12 = imat[5];
// 计算行列式
float D = i00 * i11 - i01 * i10;
D = D != 0 ? 1.0 / D : 0;
// 计算剩余的伴随矩阵除以行列式
float A11 = i11 * D;
float A22 = i00 * D;
float A12 = -i01 * D;
float A21 = -i10 * D;
float b1 = -A11 * i02 - A12 * i12;
float b2 = -A21 * i02 - A22 * i12;
omat[0] = A11; omat[1] = A12; omat[2] = b1;
omat[3] = A21; omat[4] = A22; omat[5] = b2;
}
void compute(const Size& from, const Size& to){
float scale_x = to.width / (float)from.width;
float scale_y = to.height / (float)from.height;
// 这里取min的理由是
// 1. M矩阵是 from * M = to的方式进行映射，因此scale的分母一定是from
// 2. 取最小，即根据宽高比，算出最小的比例，如果取最大，则势必有一部分超出图像范围而被裁剪掉，这不是我们要的
// **
float scale = min(scale_x, scale_y); // 缩放比例辅助视频讲解 https://v.douyin.com/NhrH8Gm/
/**
这里的仿射变换矩阵实质上是2x3的矩阵，具体实现是
scale, 0, -scale * from.width * 0.5 + to.width * 0.5
0, scale, -scale * from.height * 0.5 + to.height * 0.5
这里可以想象成，是经历过缩放、平移、平移三次变换后的组合，M = TPS
例如第一个S矩阵，定义为把输入的from图像，等比缩放scale倍，到to尺度下
S = [
scale, 0, 0
0, scale, 0
0, 0, 1
]
P矩阵定义为第一次平移变换矩阵，将图像的原点，从左上角，移动到缩放(scale)后图像的中心上
P = [
1, 0, -scale * from.width * 0.5
0, 1, -scale * from.height * 0.5
0, 0, 1
]
T矩阵定义为第二次平移变换矩阵，将图像从原点移动到目标（to）图的中心上
T = [
1, 0, to.width * 0.5,
0, 1, to.height * 0.5,
0, 0, 1
]
通过将3个矩阵顺序乘起来，即可得到下面的表达式：
M = [
scale, 0, -scale * from.width * 0.5 + to.width * 0.5
0, scale, -scale * from.height * 0.5 + to.height * 0.5
0, 0, 1
]
去掉第三行就得到opencv需要的输入2x3矩阵
**/
/*
+ scale * 0.5 - 0.5 的主要原因是使得中心更加对齐，下采样不明显，但是上采样时就比较明显
参考：https://www.iteye.com/blog/handspeaker-1545126
*/
i2d[0] = scale; i2d[1] = 0; i2d[2] =
-scale * from.width * 0.5 + to.width * 0.5 + scale * 0.5 - 0.5;
i2d[3] = 0; i2d[4] = scale; i2d[5] =
-scale * from.height * 0.5 + to.height * 0.5 + scale * 0.5 - 0.5;
invertAffineTransform(i2d, d2i);
}
};
__device__ void affine_project(float* matrix, int x, int y, float* proj_x, float* proj_y){
// matrix
// m0, m1, m2
// m3, m4, m5
*proj_x = matrix[0] * x + matrix[1] * y + matrix[2];
*proj_y = matrix[3] * x + matrix[4] * y + matrix[5];
}
__global__ void warp_affine_bilinear_kernel(
uint8_t* src, int src_line_size, int src_width, int src_height,
uint8_t* dst, int dst_line_size, int dst_width, int dst_height,
uint8_t fill_value, AffineMatrix matrix
){
/*
建议先阅读代码，若有疑问，可点击抖音短视频进行辅助讲解(建议1.5倍速观看)
- https://v.douyin.com/Nhr4vTF/
*/
int dx = blockDim.x * blockIdx.x + threadIdx.x;
int dy = blockDim.y * blockIdx.y + threadIdx.y;
if (dx >= dst_width || dy >= dst_height) return;
float c0 = fill_value, c1 = fill_value, c2 = fill_value;
float src_x = 0; float src_y = 0;
affine_project(matrix.d2i, dx, dy, &src_x, &src_y);
/*
建议先阅读代码，若有疑问，可点击抖音短视频进行辅助讲解(建议1.5倍速观看)
- 双线性理论讲解：https://v.douyin.com/NhrH2tb/
- 代码代码：https://v.douyin.com/NhrBqpc/
*/
if(src_x < -1 || src_x >= src_width || src_y < -1 || src_y >= src_height){
// out of range
// src_x < -1时，其高位high_x < 0，超出范围
// src_x >= -1时，其高位high_x >= 0，存在取值
}else{
int y_low = floorf(src_y);
int x_low = floorf(src_x);
int y_high = y_low + 1;
int x_high = x_low + 1;
uint8_t const_values[] = {fill_value, fill_value, fill_value};
float ly = src_y - y_low;
float lx = src_x - x_low;
float hy = 1 - ly;
float hx = 1 - lx;
float w1 = hy * hx, w2 = hy * lx, w3 = ly * hx, w4 = ly * lx;
uint8_t* v1 = const_values;
uint8_t* v2 = const_values;
uint8_t* v3 = const_values;
uint8_t* v4 = const_values;
if(y_low >= 0){
if (x_low >= 0)
v1 = src + y_low * src_line_size + x_low * 3;
if (x_high < src_width)
v2 = src + y_low * src_line_size + x_high * 3;
}
if(y_high < src_height){
if (x_low >= 0)
v3 = src + y_high * src_line_size + x_low * 3;
if (x_high < src_width)
v4 = src + y_high * src_line_size + x_high * 3;
}
c0 = floorf(w1 * v1[0] + w2 * v2[0] + w3 * v3[0] + w4 * v4[0] + 0.5f);
c1 = floorf(w1 * v1[1] + w2 * v2[1] + w3 * v3[1] + w4 * v4[1] + 0.5f);
c2 = floorf(w1 * v1[2] + w2 * v2[2] + w3 * v3[2] + w4 * v4[2] + 0.5f);
}
uint8_t* pdst = dst + dy * dst_line_size + dx * 3;
pdst[0] = c0; pdst[1] = c1; pdst[2] = c2;
}
void warp_affine_bilinear(
/*
建议先阅读代码，若有疑问，可点击抖音短视频进行辅助讲解(建议1.5倍速观看)
- https://v.douyin.com/Nhre7fV/
*/
uint8_t* src, int src_line_size, int src_width, int src_height,
uint8_t* dst, int dst_line_size, int dst_width, int dst_height,
uint8_t fill_value
){
dim3 block_size(32, 32); // blocksize最大就是1024，这里用2d来看更好理解
dim3 grid_size((dst_width + 31) / 32, (dst_height + 31) / 32);
AffineMatrix affine;
affine.compute(Size(src_width, src_height), Size(dst_width, dst_height));
warp_affine_bilinear_kernel<<<grid_size, block_size, 0, nullptr>>>(
src, src_line_size, src_width, src_height,
dst, dst_line_size, dst_width, dst_height,
fill_value, affine
);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define min(a, b) ((a) < (b) ? (a) : (b))
#define num_threads 512
typedef unsigned char uint8_t;
struct Size{
int width = 0, height = 0;
Size() = default;
Size(int w, int h)
:width(w), height(h){}
};
// 计算仿射变换矩阵
// 计算的矩阵是居中缩放
struct AffineMatrix{
/*
建议先阅读代码，若有疑问，可点击抖音短视频进行辅助讲解(建议1.5倍速观看)
- https://v.douyin.com/Nhr5UdL/
*/
float i2d[6]; // image to dst(network), 2x3 matrix
float d2i[6]; // dst to image, 2x3 matrix
// 这里其实是求解imat的逆矩阵，由于这个3x3矩阵的第三行是确定的0, 0, 1，因此可以简写如下
void invertAffineTransform(float imat[6], float omat[6]){
float i00 = imat[0]; float i01 = imat[1]; float i02 = imat[2];
float i10 = imat[3]; float i11 = imat[4]; float i12 = imat[5];
// 计算行列式
float D = i00 * i11 - i01 * i10;
D = D != 0 ? 1.0 / D : 0;
// 计算剩余的伴随矩阵除以行列式
float A11 = i11 * D;
float A22 = i00 * D;
float A12 = -i01 * D;
float A21 = -i10 * D;
float b1 = -A11 * i02 - A12 * i12;
float b2 = -A21 * i02 - A22 * i12;
omat[0] = A11; omat[1] = A12; omat[2] = b1;
omat[3] = A21; omat[4] = A22; omat[5] = b2;
}
void compute(const Size& from, const Size& to){
float scale_x = to.width / (float)from.width;
float scale_y = to.height / (float)from.height;
// 这里取min的理由是
// 1. M矩阵是 from * M = to的方式进行映射，因此scale的分母一定是from
// 2. 取最小，即根据宽高比，算出最小的比例，如果取最大，则势必有一部分超出图像范围而被裁剪掉，这不是我们要的
// **
float scale = min(scale_x, scale_y); // 缩放比例辅助视频讲解 https://v.douyin.com/NhrH8Gm/
/**
这里的仿射变换矩阵实质上是2x3的矩阵，具体实现是
scale, 0, -scale * from.width * 0.5 + to.width * 0.5
0, scale, -scale * from.height * 0.5 + to.height * 0.5
这里可以想象成，是经历过缩放、平移、平移三次变换后的组合，M = TPS
例如第一个S矩阵，定义为把输入的from图像，等比缩放scale倍，到to尺度下
S = [
scale, 0, 0
0, scale, 0
0, 0, 1
]
P矩阵定义为第一次平移变换矩阵，将图像的原点，从左上角，移动到缩放(scale)后图像的中心上
P = [
1, 0, -scale * from.width * 0.5
0, 1, -scale * from.height * 0.5
0, 0, 1
]
T矩阵定义为第二次平移变换矩阵，将图像从原点移动到目标（to）图的中心上
T = [
1, 0, to.width * 0.5,
0, 1, to.height * 0.5,
0, 0, 1
]
通过将3个矩阵顺序乘起来，即可得到下面的表达式：
M = [
scale, 0, -scale * from.width * 0.5 + to.width * 0.5
0, scale, -scale * from.height * 0.5 + to.height * 0.5
0, 0, 1
]
去掉第三行就得到opencv需要的输入2x3矩阵
**/
/*
+ scale * 0.5 - 0.5 的主要原因是使得中心更加对齐，下采样不明显，但是上采样时就比较明显
参考：https://www.iteye.com/blog/handspeaker-1545126
*/
i2d[0] = scale; i2d[1] = 0; i2d[2] =
-scale * from.width * 0.5 + to.width * 0.5 + scale * 0.5 - 0.5;
i2d[3] = 0; i2d[4] = scale; i2d[5] =
-scale * from.height * 0.5 + to.height * 0.5 + scale * 0.5 - 0.5;
invertAffineTransform(i2d, d2i);
}
};
__device__ void affine_project(float* matrix, int x, int y, float* proj_x, float* proj_y){
// matrix
// m0, m1, m2
// m3, m4, m5
*proj_x = matrix[0] * x + matrix[1] * y + matrix[2];
*proj_y = matrix[3] * x + matrix[4] * y + matrix[5];
}
__global__ void warp_affine_bilinear_kernel(
uint8_t* src, int src_line_size, int src_width, int src_height,
uint8_t* dst, int dst_line_size, int dst_width, int dst_height,
uint8_t fill_value, AffineMatrix matrix
){
/*
建议先阅读代码，若有疑问，可点击抖音短视频进行辅助讲解(建议1.5倍速观看)
- https://v.douyin.com/Nhr4vTF/
*/
int dx = blockDim.x * blockIdx.x + threadIdx.x;
int dy = blockDim.y * blockIdx.y + threadIdx.y;
if (dx >= dst_width || dy >= dst_height) return;
float c0 = fill_value, c1 = fill_value, c2 = fill_value;
float src_x = 0; float src_y = 0;
affine_project(matrix.d2i, dx, dy, &src_x, &src_y);
/*
建议先阅读代码，若有疑问，可点击抖音短视频进行辅助讲解(建议1.5倍速观看)
- 双线性理论讲解：https://v.douyin.com/NhrH2tb/
- 代码代码：https://v.douyin.com/NhrBqpc/
*/
if(src_x < -1 || src_x >= src_width || src_y < -1 || src_y >= src_height){
// out of range
// src_x < -1时，其高位high_x < 0，超出范围
// src_x >= -1时，其高位high_x >= 0，存在取值
}else{
int y_low = floorf(src_y);
int x_low = floorf(src_x);
int y_high = y_low + 1;
int x_high = x_low + 1;
uint8_t const_values[] = {fill_value, fill_value, fill_value};
float ly = src_y - y_low;
float lx = src_x - x_low;
float hy = 1 - ly;
float hx = 1 - lx;
float w1 = hy * hx, w2 = hy * lx, w3 = ly * hx, w4 = ly * lx;
uint8_t* v1 = const_values;
uint8_t* v2 = const_values;
uint8_t* v3 = const_values;
uint8_t* v4 = const_values;
if(y_low >= 0){
if (x_low >= 0)
v1 = src + y_low * src_line_size + x_low * 3;
if (x_high < src_width)
v2 = src + y_low * src_line_size + x_high * 3;
}
if(y_high < src_height){
if (x_low >= 0)
v3 = src + y_high * src_line_size + x_low * 3;
if (x_high < src_width)
v4 = src + y_high * src_line_size + x_high * 3;
}
c0 = floorf(w1 * v1[0] + w2 * v2[0] + w3 * v3[0] + w4 * v4[0] + 0.5f);
c1 = floorf(w1 * v1[1] + w2 * v2[1] + w3 * v3[1] + w4 * v4[1] + 0.5f);
c2 = floorf(w1 * v1[2] + w2 * v2[2] + w3 * v3[2] + w4 * v4[2] + 0.5f);
}
uint8_t* pdst = dst + dy * dst_line_size + dx * 3;
pdst[0] = c0; pdst[1] = c1; pdst[2] = c2;
}
void warp_affine_bilinear(
/*
建议先阅读代码，若有疑问，可点击抖音短视频进行辅助讲解(建议1.5倍速观看)
- https://v.douyin.com/Nhre7fV/
*/
uint8_t* src, int src_line_size, int src_width, int src_height,
uint8_t* dst, int dst_line_size, int dst_width, int dst_height,
uint8_t fill_value
){
dim3 block_size(32, 32); // blocksize最大就是1024，这里用2d来看更好理解
dim3 grid_size((dst_width + 31) / 32, (dst_height + 31) / 32);
AffineMatrix affine;
affine.compute(Size(src_width, src_height), Size(dst_width, dst_height));
warp_affine_bilinear_kernel<<<grid_size, block_size, 0, nullptr>>>(
src, src_line_size, src_width, src_height,
dst, dst_line_size, dst_width, dst_height,
fill_value, affine
);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.globl _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.p2align 8
.type _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix,@function
_Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix:
s_clause 0x1
s_load_b32 s6, s[2:3], 0x6c
s_load_b64 s[4:5], s[2:3], 0x24
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s6, 0xffff
s_lshr_b32 s6, s6, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s14, s7, v[3:4]
v_mad_u64_u32 v[2:3], null, s15, s6, v[4:5]
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s4, s5, v2
s_and_b32 s4, vcc_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_18
s_clause 0x2
s_load_b64 s[4:5], s[2:3], 0x48
s_load_b32 s11, s[2:3], 0x2c
s_load_b32 s6, s[2:3], 0x50
v_cvt_f32_i32_e32 v7, v1
v_cvt_f32_i32_e32 v8, v2
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
v_cvt_f32_ubyte0_e32 v3, s11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v5, s4, v7 :: v_dual_mov_b32 v6, v3
v_fmac_f32_e32 v5, s5, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v15, s6, v5
v_mov_b32_e32 v5, v3
v_cmpx_ngt_f32_e32 -1.0, v15
s_cbranch_execz .LBB0_17
s_clause 0x2
s_load_b64 s[4:5], s[2:3], 0x54
s_load_b64 s[6:7], s[2:3], 0xc
s_load_b32 s9, s[2:3], 0x5c
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v5, s4, v7
v_cvt_f32_i32_e32 v6, s6
v_mov_b32_e32 v7, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v5, s5, v8
v_cmp_nge_f32_e32 vcc_lo, v15, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v16, s9, v5
v_cvt_f32_i32_e32 v5, s7
v_cmp_nge_f32_e64 s4, v16, v5
v_mov_b32_e32 v5, v3
v_cmp_ngt_f32_e64 s5, -1.0, v16
s_delay_alu instid0(VALU_DEP_3)
s_and_b32 s4, vcc_lo, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s4, s4, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s9, s4
s_cbranch_execz .LBB0_16
s_load_b64 s[0:1], s[0:1], 0x4
v_dual_mov_b32 v10, s11 :: v_dual_and_b32 v3, 0x3ff, v0
v_bfe_u32 v0, v0, 20, 10
s_clause 0x1
s_load_b64 s[4:5], s[2:3], 0x0
s_load_b32 s10, s[2:3], 0x8
s_waitcnt lgkmcnt(0)
s_lshr_b32 s0, s0, 16
v_mul_u32_u24_e32 v4, s1, v4
s_mul_i32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s0, v3
s_mov_b64 s[0:1], src_shared_base
s_mov_b32 s0, exec_lo
v_add3_u32 v0, v3, v4, v0
v_floor_f32_e32 v3, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshl_add_u32 v9, v0, 1, v0
v_floor_f32_e32 v0, v16
v_cvt_i32_f32_e32 v17, v3
ds_store_b8 v9, v10
ds_store_b8 v9, v10 offset:1
ds_store_b8 v9, v10 offset:2
v_cmp_ne_u32_e32 vcc_lo, -1, v9
v_cvt_i32_f32_e32 v0, v0
v_cndmask_b32_e32 v5, 0, v9, vcc_lo
v_cndmask_b32_e64 v6, 0, s1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v3, v5 :: v_dual_add_nc_u32 v18, 1, v17
v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
v_mov_b32_e32 v4, v6
v_cmpx_lt_i32_e32 -1, v0
s_cbranch_execz .LBB0_9
v_mul_lo_u32 v10, v0, s10
v_dual_mov_b32 v3, v5 :: v_dual_mov_b32 v4, v6
s_mov_b32 s1, exec_lo
v_cmpx_lt_i32_e32 -1, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v3, 31, v10
v_lshl_add_u32 v4, v17, 1, v17
v_add_co_u32 v7, vcc_lo, s4, v10
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, v7, v4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v8, vcc_lo
s_or_b32 exec_lo, exec_lo, s1
v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
s_mov_b32 s1, exec_lo
v_cmpx_gt_i32_e64 s6, v18
v_ashrrev_i32_e32 v7, 31, v10
v_lshl_add_u32 v8, v18, 1, v18
v_add_co_u32 v10, vcc_lo, s4, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v7, vcc_lo
v_ashrrev_i32_e32 v12, 31, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v10, v8
v_add_co_ci_u32_e32 v8, vcc_lo, v11, v12, vcc_lo
s_or_b32 exec_lo, exec_lo, s1
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v10, 2, v9
v_dual_mov_b32 v14, v6 :: v_dual_add_nc_u32 v11, 1, v9
v_mov_b32_e32 v13, v5
s_mov_b64 s[12:13], src_shared_base
v_cmp_ne_u32_e32 vcc_lo, -1, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e64 s0, -1, v11
v_add_nc_u32_e32 v19, 1, v0
v_cndmask_b32_e32 v9, 0, v10, vcc_lo
v_cndmask_b32_e64 v11, 0, v11, s0
v_cndmask_b32_e64 v10, 0, s13, vcc_lo
v_cndmask_b32_e64 v12, 0, s13, s0
s_mov_b32 s0, exec_lo
v_cmpx_gt_i32_e64 s7, v19
s_cbranch_execz .LBB0_15
v_mul_lo_u32 v19, v19, s10
v_dual_mov_b32 v14, v6 :: v_dual_mov_b32 v13, v5
s_mov_b32 s1, exec_lo
v_cmpx_lt_i32_e32 -1, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v13, 31, v19
v_lshl_add_u32 v14, v17, 1, v17
v_add_co_u32 v20, vcc_lo, s4, v19
v_add_co_ci_u32_e32 v21, vcc_lo, s5, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v13, vcc_lo, v20, v14
v_add_co_ci_u32_e32 v14, vcc_lo, 0, v21, vcc_lo
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s1, exec_lo
v_cmpx_gt_i32_e64 s6, v18
v_ashrrev_i32_e32 v5, 31, v19
v_lshl_add_u32 v6, v18, 1, v18
v_add_co_u32 v9, vcc_lo, s4, v19
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v5, vcc_lo
v_ashrrev_i32_e32 v11, 31, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v9, v6
v_add_co_ci_u32_e32 v6, vcc_lo, v10, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, v5, 2
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v6, vcc_lo
v_add_co_u32 v11, vcc_lo, v5, 1
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v6, vcc_lo
s_or_b32 exec_lo, exec_lo, s1
.LBB0_15:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s0
flat_load_u8 v18, v[3:4]
flat_load_u8 v19, v[7:8]
flat_load_u8 v20, v[13:14]
flat_load_u8 v5, v[5:6]
s_clause 0x1
flat_load_u8 v6, v[7:8] offset:1
flat_load_u8 v7, v[7:8] offset:2
s_clause 0x1
flat_load_u8 v8, v[3:4] offset:1
flat_load_u8 v3, v[3:4] offset:2
s_clause 0x1
flat_load_u8 v4, v[13:14] offset:1
flat_load_u8 v13, v[13:14] offset:2
flat_load_u8 v11, v[11:12]
flat_load_u8 v9, v[9:10]
v_cvt_f32_i32_e32 v0, v0
v_cvt_f32_i32_e32 v10, v17
s_waitcnt vmcnt(9) lgkmcnt(9)
v_cvt_f32_ubyte0_e32 v17, v20
s_waitcnt vmcnt(8) lgkmcnt(8)
v_cvt_f32_ubyte0_e32 v5, v5
s_waitcnt vmcnt(7) lgkmcnt(7)
v_cvt_f32_ubyte0_e32 v6, v6
s_waitcnt vmcnt(6) lgkmcnt(6)
v_cvt_f32_ubyte0_e32 v7, v7
v_sub_f32_e32 v0, v16, v0
s_waitcnt vmcnt(4) lgkmcnt(4)
v_cvt_f32_ubyte0_e32 v3, v3
v_sub_f32_e32 v10, v15, v10
v_cvt_f32_ubyte0_e32 v8, v8
s_waitcnt vmcnt(3) lgkmcnt(3)
v_cvt_f32_ubyte0_e32 v4, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_sub_f32 v12, 1.0, v0 :: v_dual_mul_f32 v15, v0, v10
v_sub_f32_e32 v14, 1.0, v10
v_mul_f32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f32_e32 v16, v12, v14
v_cvt_f32_ubyte0_e32 v12, v18
v_dual_mul_f32 v7, v10, v7 :: v_dual_mul_f32 v0, v0, v14
v_cvt_f32_ubyte0_e32 v14, v19
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_mul_f32 v6, v10, v6 :: v_dual_fmac_f32 v7, v16, v3
s_waitcnt vmcnt(1) lgkmcnt(1)
v_cvt_f32_ubyte0_e32 v3, v11
v_mul_f32_e32 v14, v10, v14
v_cvt_f32_ubyte0_e32 v10, v13
v_fmac_f32_e32 v6, v16, v8
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cvt_f32_ubyte0_e32 v8, v9
v_fmac_f32_e32 v14, v16, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v6, v0, v4
v_fmac_f32_e32 v14, v0, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v7, v0, v10 :: v_dual_fmac_f32 v6, v15, v3
v_fmac_f32_e32 v14, v15, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v7, v15, v8 :: v_dual_add_f32 v4, 0.5, v6
v_add_f32_e32 v0, 0.5, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v6, 0.5, v7
v_floor_f32_e32 v5, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_floor_f32_e32 v3, v0
v_floor_f32_e32 v7, v6
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v6, v3
v_mov_b32_e32 v3, v7
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s8
s_clause 0x1
s_load_b32 s4, s[2:3], 0x20
s_load_b64 s[0:1], s[2:3], 0x18
v_lshl_add_u32 v1, v1, 1, v1
v_cvt_i32_f32_e32 v6, v6
v_cvt_i32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v1
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v0, v2, s4
v_ashrrev_i32_e32 v2, 31, v0
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
v_add_co_u32 v0, vcc_lo, v0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, v2, v4, vcc_lo
v_cvt_i32_f32_e32 v2, v5
s_clause 0x2
global_store_b8 v[0:1], v6, off
global_store_b8 v[0:1], v2, off offset:1
global_store_b8 v[0:1], v3, off offset:2
.LBB0_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.amdhsa_group_segment_fixed_size 3072
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 352
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 1
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 22
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix, .Lfunc_end0-_Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 1
.value_kind: by_value
- .offset: 48
.size: 48
.value_kind: by_value
- .offset: 96
.size: 4
.value_kind: hidden_block_count_x
- .offset: 100
.size: 4
.value_kind: hidden_block_count_y
- .offset: 104
.size: 4
.value_kind: hidden_block_count_z
- .offset: 108
.size: 2
.value_kind: hidden_group_size_x
- .offset: 110
.size: 2
.value_kind: hidden_group_size_y
- .offset: 112
.size: 2
.value_kind: hidden_group_size_z
- .offset: 114
.size: 2
.value_kind: hidden_remainder_x
- .offset: 116
.size: 2
.value_kind: hidden_remainder_y
- .offset: 118
.size: 2
.value_kind: hidden_remainder_z
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 152
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 160
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 3072
.kernarg_segment_align: 8
.kernarg_segment_size: 352
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 22
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define min(a, b) ((a) < (b) ? (a) : (b))
#define num_threads 512
typedef unsigned char uint8_t;
struct Size{
int width = 0, height = 0;
Size() = default;
Size(int w, int h)
:width(w), height(h){}
};
// 计算仿射变换矩阵
// 计算的矩阵是居中缩放
struct AffineMatrix{
/*
建议先阅读代码，若有疑问，可点击抖音短视频进行辅助讲解(建议1.5倍速观看)
- https://v.douyin.com/Nhr5UdL/
*/
float i2d[6]; // image to dst(network), 2x3 matrix
float d2i[6]; // dst to image, 2x3 matrix
// 这里其实是求解imat的逆矩阵，由于这个3x3矩阵的第三行是确定的0, 0, 1，因此可以简写如下
void invertAffineTransform(float imat[6], float omat[6]){
float i00 = imat[0]; float i01 = imat[1]; float i02 = imat[2];
float i10 = imat[3]; float i11 = imat[4]; float i12 = imat[5];
// 计算行列式
float D = i00 * i11 - i01 * i10;
D = D != 0 ? 1.0 / D : 0;
// 计算剩余的伴随矩阵除以行列式
float A11 = i11 * D;
float A22 = i00 * D;
float A12 = -i01 * D;
float A21 = -i10 * D;
float b1 = -A11 * i02 - A12 * i12;
float b2 = -A21 * i02 - A22 * i12;
omat[0] = A11; omat[1] = A12; omat[2] = b1;
omat[3] = A21; omat[4] = A22; omat[5] = b2;
}
void compute(const Size& from, const Size& to){
float scale_x = to.width / (float)from.width;
float scale_y = to.height / (float)from.height;
// 这里取min的理由是
// 1. M矩阵是 from * M = to的方式进行映射，因此scale的分母一定是from
// 2. 取最小，即根据宽高比，算出最小的比例，如果取最大，则势必有一部分超出图像范围而被裁剪掉，这不是我们要的
// **
float scale = min(scale_x, scale_y); // 缩放比例辅助视频讲解 https://v.douyin.com/NhrH8Gm/
/**
这里的仿射变换矩阵实质上是2x3的矩阵，具体实现是
scale, 0, -scale * from.width * 0.5 + to.width * 0.5
0, scale, -scale * from.height * 0.5 + to.height * 0.5
这里可以想象成，是经历过缩放、平移、平移三次变换后的组合，M = TPS
例如第一个S矩阵，定义为把输入的from图像，等比缩放scale倍，到to尺度下
S = [
scale, 0, 0
0, scale, 0
0, 0, 1
]
P矩阵定义为第一次平移变换矩阵，将图像的原点，从左上角，移动到缩放(scale)后图像的中心上
P = [
1, 0, -scale * from.width * 0.5
0, 1, -scale * from.height * 0.5
0, 0, 1
]
T矩阵定义为第二次平移变换矩阵，将图像从原点移动到目标（to）图的中心上
T = [
1, 0, to.width * 0.5,
0, 1, to.height * 0.5,
0, 0, 1
]
通过将3个矩阵顺序乘起来，即可得到下面的表达式：
M = [
scale, 0, -scale * from.width * 0.5 + to.width * 0.5
0, scale, -scale * from.height * 0.5 + to.height * 0.5
0, 0, 1
]
去掉第三行就得到opencv需要的输入2x3矩阵
**/
/*
+ scale * 0.5 - 0.5 的主要原因是使得中心更加对齐，下采样不明显，但是上采样时就比较明显
参考：https://www.iteye.com/blog/handspeaker-1545126
*/
i2d[0] = scale; i2d[1] = 0; i2d[2] =
-scale * from.width * 0.5 + to.width * 0.5 + scale * 0.5 - 0.5;
i2d[3] = 0; i2d[4] = scale; i2d[5] =
-scale * from.height * 0.5 + to.height * 0.5 + scale * 0.5 - 0.5;
invertAffineTransform(i2d, d2i);
}
};
__device__ void affine_project(float* matrix, int x, int y, float* proj_x, float* proj_y){
// matrix
// m0, m1, m2
// m3, m4, m5
*proj_x = matrix[0] * x + matrix[1] * y + matrix[2];
*proj_y = matrix[3] * x + matrix[4] * y + matrix[5];
}
__global__ void warp_affine_bilinear_kernel(
uint8_t* src, int src_line_size, int src_width, int src_height,
uint8_t* dst, int dst_line_size, int dst_width, int dst_height,
uint8_t fill_value, AffineMatrix matrix
){
/*
建议先阅读代码，若有疑问，可点击抖音短视频进行辅助讲解(建议1.5倍速观看)
- https://v.douyin.com/Nhr4vTF/
*/
int dx = blockDim.x * blockIdx.x + threadIdx.x;
int dy = blockDim.y * blockIdx.y + threadIdx.y;
if (dx >= dst_width || dy >= dst_height) return;
float c0 = fill_value, c1 = fill_value, c2 = fill_value;
float src_x = 0; float src_y = 0;
affine_project(matrix.d2i, dx, dy, &src_x, &src_y);
/*
建议先阅读代码，若有疑问，可点击抖音短视频进行辅助讲解(建议1.5倍速观看)
- 双线性理论讲解：https://v.douyin.com/NhrH2tb/
- 代码代码：https://v.douyin.com/NhrBqpc/
*/
if(src_x < -1 || src_x >= src_width || src_y < -1 || src_y >= src_height){
// out of range
// src_x < -1时，其高位high_x < 0，超出范围
// src_x >= -1时，其高位high_x >= 0，存在取值
}else{
int y_low = floorf(src_y);
int x_low = floorf(src_x);
int y_high = y_low + 1;
int x_high = x_low + 1;
uint8_t const_values[] = {fill_value, fill_value, fill_value};
float ly = src_y - y_low;
float lx = src_x - x_low;
float hy = 1 - ly;
float hx = 1 - lx;
float w1 = hy * hx, w2 = hy * lx, w3 = ly * hx, w4 = ly * lx;
uint8_t* v1 = const_values;
uint8_t* v2 = const_values;
uint8_t* v3 = const_values;
uint8_t* v4 = const_values;
if(y_low >= 0){
if (x_low >= 0)
v1 = src + y_low * src_line_size + x_low * 3;
if (x_high < src_width)
v2 = src + y_low * src_line_size + x_high * 3;
}
if(y_high < src_height){
if (x_low >= 0)
v3 = src + y_high * src_line_size + x_low * 3;
if (x_high < src_width)
v4 = src + y_high * src_line_size + x_high * 3;
}
c0 = floorf(w1 * v1[0] + w2 * v2[0] + w3 * v3[0] + w4 * v4[0] + 0.5f);
c1 = floorf(w1 * v1[1] + w2 * v2[1] + w3 * v3[1] + w4 * v4[1] + 0.5f);
c2 = floorf(w1 * v1[2] + w2 * v2[2] + w3 * v3[2] + w4 * v4[2] + 0.5f);
}
uint8_t* pdst = dst + dy * dst_line_size + dx * 3;
pdst[0] = c0; pdst[1] = c1; pdst[2] = c2;
}
void warp_affine_bilinear(
/*
建议先阅读代码，若有疑问，可点击抖音短视频进行辅助讲解(建议1.5倍速观看)
- https://v.douyin.com/Nhre7fV/
*/
uint8_t* src, int src_line_size, int src_width, int src_height,
uint8_t* dst, int dst_line_size, int dst_width, int dst_height,
uint8_t fill_value
){
dim3 block_size(32, 32); // blocksize最大就是1024，这里用2d来看更好理解
dim3 grid_size((dst_width + 31) / 32, (dst_height + 31) / 32);
AffineMatrix affine;
affine.compute(Size(src_width, src_height), Size(dst_width, dst_height));
warp_affine_bilinear_kernel<<<grid_size, block_size, 0, nullptr>>>(
src, src_line_size, src_width, src_height,
dst, dst_line_size, dst_width, dst_height,
fill_value, affine
);
} | .text
.file "affine.hip"
.globl _Z42__device_stub__warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix # -- Begin function _Z42__device_stub__warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.p2align 4, 0x90
.type _Z42__device_stub__warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix,@function
_Z42__device_stub__warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix: # @_Z42__device_stub__warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z42__device_stub__warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix, .Lfunc_end0-_Z42__device_stub__warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z20warp_affine_bilinearPhiiiS_iiih
.LCPI1_0:
.long 0x3f800000 # float 1
.LCPI1_1:
.long 0x80000000 # float -0
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_2:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_3:
.quad 0x3fe0000000000000 # double 0.5
.LCPI1_4:
.quad 0xbfe0000000000000 # double -0.5
.text
.globl _Z20warp_affine_bilinearPhiiiS_iiih
.p2align 4, 0x90
.type _Z20warp_affine_bilinearPhiiiS_iiih,@function
_Z20warp_affine_bilinearPhiiiS_iiih: # @_Z20warp_affine_bilinearPhiiiS_iiih
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, 12(%rsp) # 4-byte Spill
movq %r8, 88(%rsp) # 8-byte Spill
movl %ecx, %r15d
movl %edx, %ebx
movl %esi, %ebp
movl 312(%rsp), %r12d
movl 304(%rsp), %r14d
leal 31(%r14), %eax
leal 62(%r14), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $5, %ecx
leal 31(%r12), %edx
leal 62(%r12), %eax
testl %edx, %edx
cmovnsl %edx, %eax
movq %rdi, %r13
sarl $5, %eax
shlq $32, %rax
orq %rcx, %rax
movabsq $137438953504, %rdx # imm = 0x2000000020
movq %rax, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.1:
movq %r13, %rdi
movq 88(%rsp), %r13 # 8-byte Reload
movl 12(%rsp), %esi # 4-byte Reload
cvtsi2ss %r14d, %xmm0
cvtsi2ss %ebx, %xmm6
cvtsi2ss %r12d, %xmm1
movzbl 320(%rsp), %eax
cvtsi2ss %r15d, %xmm5
divss %xmm6, %xmm0
divss %xmm5, %xmm1
minss %xmm1, %xmm0
movaps %xmm0, %xmm2
mulss %xmm0, %xmm2
xorps %xmm1, %xmm1
ucomiss %xmm1, %xmm2
jne .LBB1_2
jnp .LBB1_3
.LBB1_2: # %select.true.sink
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm2, %xmm1
.LBB1_3: # %select.end
movss .LCPI1_1(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
mulss %xmm1, %xmm2
movaps .LCPI1_2(%rip), %xmm4 # xmm4 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
movaps %xmm2, %xmm3
xorps %xmm4, %xmm3
cvtss2sd %xmm0, %xmm7
movsd .LCPI1_3(%rip), %xmm8 # xmm8 = mem[0],zero
mulsd %xmm8, %xmm7
cvtsi2sd %r14d, %xmm9
mulsd %xmm8, %xmm9
mulss %xmm0, %xmm6
cvtss2sd %xmm6, %xmm6
movsd .LCPI1_4(%rip), %xmm10 # xmm10 = mem[0],zero
mulsd %xmm10, %xmm6
addsd %xmm9, %xmm6
addsd %xmm7, %xmm6
addsd %xmm10, %xmm6
cvtsd2ss %xmm6, %xmm6
mulss %xmm6, %xmm3
mulss %xmm0, %xmm1
xorps %xmm9, %xmm9
cvtsi2sd %r12d, %xmm9
mulsd %xmm8, %xmm9
mulss %xmm0, %xmm5
cvtss2sd %xmm5, %xmm5
mulsd %xmm10, %xmm5
addsd %xmm9, %xmm5
addsd %xmm7, %xmm5
addsd %xmm10, %xmm5
cvtsd2ss %xmm5, %xmm5
movaps %xmm1, %xmm7
mulss %xmm5, %xmm7
subss %xmm7, %xmm3
xorps %xmm1, %xmm4
mulss %xmm6, %xmm4
movaps %xmm2, %xmm7
mulss %xmm5, %xmm7
subss %xmm7, %xmm4
movss %xmm0, 40(%rsp)
movl $0, 44(%rsp)
movss %xmm6, 48(%rsp)
movl $0, 52(%rsp)
movss %xmm0, 56(%rsp)
movss %xmm5, 60(%rsp)
movss %xmm1, 64(%rsp)
movss %xmm2, 68(%rsp)
movss %xmm4, 72(%rsp)
movss %xmm2, 76(%rsp)
movss %xmm1, 80(%rsp)
movss %xmm3, 84(%rsp)
movq %rdi, 152(%rsp)
movl %ebp, 36(%rsp)
movl %ebx, 32(%rsp)
movl %r15d, 28(%rsp)
movq %r13, 144(%rsp)
movl %esi, 24(%rsp)
movl %r14d, 20(%rsp)
movl %r12d, 16(%rsp)
movb %al, 11(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 36(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rax
movq %rax, 176(%rsp)
leaq 28(%rsp), %rax
movq %rax, 184(%rsp)
leaq 144(%rsp), %rax
movq %rax, 192(%rsp)
leaq 24(%rsp), %rax
movq %rax, 200(%rsp)
leaq 20(%rsp), %rax
movq %rax, 208(%rsp)
leaq 16(%rsp), %rax
movq %rax, 216(%rsp)
leaq 11(%rsp), %rax
movq %rax, 224(%rsp)
leaq 40(%rsp), %rax
movq %rax, 232(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z20warp_affine_bilinearPhiiiS_iiih, .Lfunc_end1-_Z20warp_affine_bilinearPhiiiS_iiih
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix,@object # @_Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.section .rodata,"a",@progbits
.globl _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.p2align 3, 0x0
_Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix:
.quad _Z42__device_stub__warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.size _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix"
.size .L__unnamed_1, 57
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fc60000000f00 */
/*0010*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002600 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0040*/ S2R R12, SR_CTAID.X ; /* 0x00000000000c7919 */
/* 0x000e680000002500 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R9, R9, c[0x0][0x4], R0 ; /* 0x0000010009097a24 */
/* 0x001fca00078e0200 */
/*0070*/ ISETP.GE.AND P0, PT, R9, c[0x0][0x188], PT ; /* 0x0000620009007a0c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD R12, R12, c[0x0][0x0], R3 ; /* 0x000000000c0c7a24 */
/* 0x002fca00078e0203 */
/*0090*/ ISETP.GE.OR P0, PT, R12, c[0x0][0x184], P0 ; /* 0x000061000c007a0c */
/* 0x000fda0000706670 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ I2F R2, R9 ; /* 0x0000000900027306 */
/* 0x000e220000201400 */
/*00c0*/ LDC.U8 R10, c[0x0][0x18c] ; /* 0x00006300ff0a7b82 */
/* 0x000e620000000000 */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ BSSY B0, 0x8d0 ; /* 0x000007e000007945 */
/* 0x000fea0003800000 */
/*00f0*/ I2F R0, R12 ; /* 0x0000000c00007306 */
/* 0x000eb00000201400 */
/*0100*/ I2F R7, c[0x0][0x16c] ; /* 0x00005b0000077b06 */
/* 0x000ee20000201400 */
/*0110*/ FMUL R3, R2, c[0x0][0x1ac] ; /* 0x00006b0002037a20 */
/* 0x001fc40000400000 */
/*0120*/ FMUL R5, R2, c[0x0][0x1b8] ; /* 0x00006e0002057a20 */
/* 0x000fe20000400000 */
/*0130*/ IADD3 R2, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001027a10 */
/* 0x000fe20007f3e0ff */
/*0140*/ FFMA R3, R0, c[0x0][0x1a8], R3 ; /* 0x00006a0000037a23 */
/* 0x004fc60000000003 */
/*0150*/ I2F R4, c[0x0][0x170] ; /* 0x00005c0000047b06 */
/* 0x000e220000201400 */
/*0160*/ FFMA R5, R0, c[0x0][0x1b4], R5 ; /* 0x00006d0000057a23 */
/* 0x000fe40000000005 */
/*0170*/ FADD R14, R3, c[0x0][0x1b0] ; /* 0x00006c00030e7621 */
/* 0x000fe40000000000 */
/*0180*/ FADD R15, R5, c[0x0][0x1bc] ; /* 0x00006f00050f7621 */
/* 0x000fe40000000000 */
/*0190*/ IMAD.X R3, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff037624 */
/* 0x000fe200008e06ff */
/*01a0*/ FSETP.GE.AND P0, PT, R14.reuse, R7, PT ; /* 0x000000070e00720b */
/* 0x048fe20003f06000 */
/*01b0*/ I2F.U8 R16, R10 ; /* 0x0000000a00107306 */
/* 0x002e660000001000 */
/*01c0*/ FSETP.LT.OR P0, PT, R14, -1, P0 ; /* 0xbf8000000e00780b */
/* 0x000fc80000701400 */
/*01d0*/ FSETP.LT.OR P0, PT, R15, -1, P0 ; /* 0xbf8000000f00780b */
/* 0x000fc80000701400 */
/*01e0*/ FSETP.GE.OR P0, PT, R15, R4, P0 ; /* 0x000000040f00720b */
/* 0x001fe40000706400 */
/*01f0*/ MOV R0, R16 ; /* 0x0000001000007202 */
/* 0x002fe20000000f00 */
/*0200*/ IMAD.MOV.U32 R4, RZ, RZ, R16 ; /* 0x000000ffff047224 */
/* 0x000fd400078e0010 */
/*0210*/ @P0 BRA 0x8c0 ; /* 0x000006a000000947 */
/* 0x000fea0003800000 */
/*0220*/ F2I.FLOOR.NTZ R13, R15 ; /* 0x0000000f000d7305 */
/* 0x000e220000207100 */
/*0230*/ BSSY B1, 0x430 ; /* 0x000001f000017945 */
/* 0x000fe20003800000 */
/*0240*/ STL.U8 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x000fe20000100000 */
/*0250*/ MOV R6, R2.reuse ; /* 0x0000000200067202 */
/* 0x080fe20000000f00 */
/*0260*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0003 */
/*0270*/ MOV R4, R2 ; /* 0x0000000200047202 */
/* 0x000fe20000000f00 */
/*0280*/ STL.U8 [R1+0x1], R10 ; /* 0x0000010a01007387 */
/* 0x000fe20000100000 */
/*0290*/ MOV R5, R3.reuse ; /* 0x0000000300057202 */
/* 0x080fe20000000f00 */
/*02a0*/ F2I.FLOOR.NTZ R0, R14 ; /* 0x0000000e00007305 */
/* 0x000e620000207100 */
/*02b0*/ MOV R11, R3 ; /* 0x00000003000b7202 */
/* 0x000fe20000000f00 */
/*02c0*/ STL.U8 [R1+0x2], R10 ; /* 0x0000020a01007387 */
/* 0x0005e20000100000 */
/*02d0*/ ISETP.GE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x001fc40003f26270 */
/*02e0*/ IADD3 R8, R13, 0x1, RZ ; /* 0x000000010d087810 */
/* 0x000fe20007ffe0ff */
/*02f0*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x004fc600078e0002 */
/*0300*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */
/* 0x000fe40003f06270 */
/*0310*/ IADD3 R21, R0, 0x1, RZ ; /* 0x0000000100157810 */
/* 0x002fca0007ffe0ff */
/*0320*/ @!P1 BRA 0x420 ; /* 0x000000f000009947 */
/* 0x000fea0003800000 */
/*0330*/ ISETP.GE.AND P2, PT, R21, c[0x0][0x16c], PT ; /* 0x00005b0015007a0c */
/* 0x000fe40003f46270 */
/*0340*/ ISETP.GE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fd60003f26270 */
/*0350*/ @!P2 MOV R19, 0x3 ; /* 0x000000030013a802 */
/* 0x000fe20000000f00 */
/*0360*/ @!P2 IMAD R20, R13.reuse, c[0x0][0x168], RZ ; /* 0x00005a000d14aa24 */
/* 0x040fe400078e02ff */
/*0370*/ @P1 IMAD R17, R13, c[0x0][0x168], RZ ; /* 0x00005a000d111a24 */
/* 0x000fe400078e02ff */
/*0380*/ @P1 IMAD R18, R0.reuse, 0x3, RZ ; /* 0x0000000300121824 */
/* 0x040fe400078e02ff */
/*0390*/ @!P2 IMAD R19, R0, R19, 0x3 ; /* 0x000000030013a424 */
/* 0x000fc600078e0213 */
/*03a0*/ @P1 IADD3 R6, P3, P4, R18, c[0x0][0x160], R17.reuse ; /* 0x0000580012061a10 */
/* 0x100fe40007c7e011 */
/*03b0*/ @!P2 IADD3 R4, P5, P6, R19, c[0x0][0x160], R20 ; /* 0x000058001304aa10 */
/* 0x000fe40007ebe014 */
/*03c0*/ @P1 SHF.R.S32.HI R17, RZ, 0x1f, R17 ; /* 0x0000001fff111819 */
/* 0x000fe40000011411 */
/*03d0*/ @P1 SHF.R.S32.HI R18, RZ, 0x1f, R18 ; /* 0x0000001fff121819 */
/* 0x000fe40000011412 */
/*03e0*/ @!P2 SHF.R.S32.HI R20, RZ, 0x1f, R20 ; /* 0x0000001fff14a819 */
/* 0x000fe40000011414 */
/*03f0*/ @!P2 SHF.R.S32.HI R19, RZ, 0x1f, R19 ; /* 0x0000001fff13a819 */
/* 0x000fc40000011413 */
/*0400*/ @P1 IADD3.X R7, R18, c[0x0][0x164], R17, P3, P4 ; /* 0x0000590012071a10 */
/* 0x000fe40001fe8411 */
/*0410*/ @!P2 IADD3.X R5, R19, c[0x0][0x164], R20, P5, P6 ; /* 0x000059001305aa10 */
/* 0x000fe40002fec414 */
/*0420*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0430*/ BSSY B1, 0x5a0 ; /* 0x0000016000017945 */
/* 0x000fe20003800000 */
/*0440*/ @P0 BRA 0x590 ; /* 0x0000014000000947 */
/* 0x000fea0003800000 */
/*0450*/ ISETP.GE.AND P1, PT, R21, c[0x0][0x16c], PT ; /* 0x00005b0015007a0c */
/* 0x000fe40003f26270 */
/*0460*/ MOV R10, R2 ; /* 0x00000002000a7202 */
/* 0x000fd60000000f00 */
/*0470*/ @!P1 IMAD.MOV.U32 R11, RZ, RZ, 0x3 ; /* 0x00000003ff0b9424 */
/* 0x000fe400078e00ff */
/*0480*/ @!P1 IMAD R17, R8, c[0x0][0x168], RZ ; /* 0x00005a0008119a24 */
/* 0x000fe400078e02ff */
/*0490*/ @!P1 IMAD R19, R0, R11, 0x3 ; /* 0x0000000300139424 */
/* 0x000fe200078e020b */
/*04a0*/ MOV R11, R3 ; /* 0x00000003000b7202 */
/* 0x000fe40000000f00 */
/*04b0*/ @!P1 SHF.R.S32.HI R18, RZ, 0x1f, R17 ; /* 0x0000001fff129819 */
/* 0x000fe40000011411 */
/*04c0*/ @!P1 IADD3 R17, P0, R19, R17, RZ ; /* 0x0000001113119210 */
/* 0x000fc80007f1e0ff */
/*04d0*/ @!P1 LEA.HI.X.SX32 R18, R19, R18, 0x1, P0 ; /* 0x0000001213129211 */
/* 0x000fe400000f0eff */
/*04e0*/ @!P1 IADD3 R10, P0, R17, c[0x0][0x160], RZ ; /* 0x00005800110a9a10 */
/* 0x000fc80007f1e0ff */
/*04f0*/ @!P1 IADD3.X R11, R18, c[0x0][0x164], RZ, P0, !PT ; /* 0x00005900120b9a10 */
/* 0x000fca00007fe4ff */
/*0500*/ @!P1 LDG.E.U8 R17, [R10.64] ; /* 0x000000040a119981 */
/* 0x000ea2000c1e1100 */
/*0510*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f46270 */
/*0520*/ @P2 IMAD R8, R8, c[0x0][0x168], RZ ; /* 0x00005a0008082a24 */
/* 0x000fe400078e02ff */
/*0530*/ @P2 IMAD R19, R0, 0x3, RZ ; /* 0x0000000300132824 */
/* 0x000fe200078e02ff */
/*0540*/ @!P1 I2F.U16 R16, R17 ; /* 0x0000001100109306 */
/* 0x0040680000101000 */
/*0550*/ @P2 IADD3 R2, P0, P1, R19, c[0x0][0x160], R8.reuse ; /* 0x0000580013022a10 */
/* 0x100fe4000791e008 */
/*0560*/ @P2 SHF.R.S32.HI R8, RZ, 0x1f, R8 ; /* 0x0000001fff082819 */
/* 0x000fe40000011408 */
/*0570*/ @P2 SHF.R.S32.HI R19, RZ, 0x1f, R19 ; /* 0x0000001fff132819 */
/* 0x000fc80000011413 */
/*0580*/ @P2 IADD3.X R3, R19, c[0x0][0x164], R8, P0, P1 ; /* 0x0000590013032a10 */
/* 0x000fe400007e2408 */
/*0590*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x001fea0003800000 */
/*05a0*/ LD.E.U8 R18, [R4.64] ; /* 0x0000000404127980 */
/* 0x0000a8000c101100 */
/*05b0*/ LD.E.U8 R19, [R4.64+0x1] ; /* 0x0000010404137980 */
/* 0x0000e8000c101100 */
/*05c0*/ LD.E.U8 R21, [R4.64+0x2] ; /* 0x0000020404157980 */
/* 0x000128000c101100 */
/*05d0*/ LD.E.U8 R17, [R6.64] ; /* 0x0000000406117980 */
/* 0x000b28000c101100 */
/*05e0*/ LD.E.U8 R8, [R6.64+0x1] ; /* 0x0000010406087980 */
/* 0x000b28000c101100 */
/*05f0*/ LD.E.U8 R20, [R6.64+0x2] ; /* 0x0000020406147980 */
/* 0x000b28000c101100 */
/*0600*/ LD.E.U8 R23, [R2.64] ; /* 0x0000000402177980 */
/* 0x000328000c101100 */
/*0610*/ LD.E.U8 R22, [R2.64+0x1] ; /* 0x0000010402167980 */
/* 0x000328000c101100 */
/*0620*/ LD.E.U8 R24, [R2.64+0x2] ; /* 0x0000020402187980 */
/* 0x000328000c101100 */
/*0630*/ LD.E.U8 R25, [R10.64+0x1] ; /* 0x000001040a197980 */
/* 0x000f28000c101100 */
/*0640*/ LD.E.U8 R26, [R10.64+0x2] ; /* 0x000002040a1a7980 */
/* 0x000f22000c101100 */
/*0650*/ I2F R28, R13 ; /* 0x0000000d001c7306 */
/* 0x000e300000201400 */
/*0660*/ I2F R7, R0 ; /* 0x0000000000077306 */
/* 0x020f620000201400 */
/*0670*/ FADD R28, R15, -R28 ; /* 0x8000001c0f1c7221 */
/* 0x001fc80000000000 */
/*0680*/ FADD R2, -R28, 1 ; /* 0x3f8000001c027421 */
/* 0x002fe40000000100 */
/*0690*/ FADD R7, R14, -R7 ; /* 0x800000070e077221 */
/* 0x020fc80000000000 */
/*06a0*/ FADD R5, -R7.reuse, 1 ; /* 0x3f80000007057421 */
/* 0x040fe40000000100 */
/*06b0*/ FMUL R0, R7, R2 ; /* 0x0000000207007220 */
/* 0x000fe40000400000 */
/*06c0*/ FMUL R3, R2, R5.reuse ; /* 0x0000000502037220 */
/* 0x080fe40000400000 */
/*06d0*/ FMUL R5, R28.reuse, R5 ; /* 0x000000051c057220 */
/* 0x040fe40000400000 */
/*06e0*/ FMUL R7, R28, R7 ; /* 0x000000071c077220 */
/* 0x000fe20000400000 */
/*06f0*/ I2F.U16 R18, R18 ; /* 0x0000001200127306 */
/* 0x004e300000101000 */
/*0700*/ I2F.U16 R19, R19 ; /* 0x0000001300137306 */
/* 0x008e700000101000 */
/*0710*/ I2F.U16 R21, R21 ; /* 0x0000001500157306 */
/* 0x010eb00000101000 */
/*0720*/ I2F.U16 R17, R17 ; /* 0x0000001100117306 */
/* 0x000ef00000101000 */
/*0730*/ I2F.U16 R8, R8 ; /* 0x0000000800087306 */
/* 0x000f300000101000 */
/*0740*/ I2F.U16 R20, R20 ; /* 0x0000001400147306 */
/* 0x000f700000101000 */
/*0750*/ I2F.U16 R23, R23 ; /* 0x0000001700177306 */
/* 0x000e300000101000 */
/*0760*/ I2F.U16 R22, R22 ; /* 0x0000001600167306 */
/* 0x000eb00000101000 */
/*0770*/ I2F.U16 R24, R24 ; /* 0x0000001800187306 */
/* 0x000ee20000101000 */
/*0780*/ FMUL R18, R0, R18 ; /* 0x0000001200127220 */
/* 0x001fc40000400000 */
/*0790*/ FMUL R19, R0, R19 ; /* 0x0000001300137220 */
/* 0x002fca0000400000 */
/*07a0*/ I2F.U16 R25, R25 ; /* 0x0000001900197306 */
/* 0x000e220000101000 */
/*07b0*/ FMUL R21, R0, R21 ; /* 0x0000001500157220 */
/* 0x004fce0000400000 */
/*07c0*/ I2F.U16 R26, R26 ; /* 0x0000001a001a7306 */
/* 0x000e620000101000 */
/*07d0*/ FFMA R18, R3.reuse, R17, R18 ; /* 0x0000001103127223 */
/* 0x048fe40000000012 */
/*07e0*/ FFMA R8, R3.reuse, R8, R19 ; /* 0x0000000803087223 */
/* 0x050fe40000000013 */
/*07f0*/ FFMA R20, R3, R20, R21 ; /* 0x0000001403147223 */
/* 0x020fe40000000015 */
/*0800*/ FFMA R18, R5.reuse, R23, R18 ; /* 0x0000001705127223 */
/* 0x040fe40000000012 */
/*0810*/ FFMA R8, R5.reuse, R22, R8 ; /* 0x0000001605087223 */
/* 0x040fe40000000008 */
/*0820*/ FFMA R20, R5, R24, R20 ; /* 0x0000001805147223 */
/* 0x000fc40000000014 */
/*0830*/ FFMA R18, R7.reuse, R16, R18 ; /* 0x0000001007127223 */
/* 0x040fe40000000012 */
/*0840*/ FFMA R8, R7.reuse, R25, R8 ; /* 0x0000001907087223 */
/* 0x041fe40000000008 */
/*0850*/ FFMA R20, R7, R26, R20 ; /* 0x0000001a07147223 */
/* 0x002fe40000000014 */
/*0860*/ FADD R18, R18, 0.5 ; /* 0x3f00000012127421 */
/* 0x000fe40000000000 */
/*0870*/ FADD R8, R8, 0.5 ; /* 0x3f00000008087421 */
/* 0x000fe40000000000 */
/*0880*/ FADD R20, R20, 0.5 ; /* 0x3f00000014147421 */
/* 0x000fe20000000000 */
/*0890*/ FRND.FLOOR R16, R18 ; /* 0x0000001200107307 */
/* 0x0000700000205000 */
/*08a0*/ FRND.FLOOR R0, R8 ; /* 0x0000000800007307 */
/* 0x0000b00000205000 */
/*08b0*/ FRND.FLOOR R4, R20 ; /* 0x0000001400047307 */
/* 0x0000e40000205000 */
/*08c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*08d0*/ IMAD R2, R9, c[0x0][0x180], RZ ; /* 0x0000600009027a24 */
/* 0x000fe200078e02ff */
/*08e0*/ F2I.U32.TRUNC.NTZ R5, R16 ; /* 0x0000001000057305 */
/* 0x000e62000020f000 */
/*08f0*/ IMAD R3, R12, 0x3, RZ ; /* 0x000000030c037824 */
/* 0x000fc600078e02ff */
/*0900*/ SHF.R.S32.HI R6, RZ, 0x1f, R2 ; /* 0x0000001fff067819 */
/* 0x000fe40000011402 */
/*0910*/ IADD3 R2, P0, P1, R2, c[0x0][0x178], R3.reuse ; /* 0x00005e0002027a10 */
/* 0x100fe4000791e003 */
/*0920*/ F2I.U32.TRUNC.NTZ R7, R0 ; /* 0x0000000000077305 */
/* 0x004ea2000020f000 */
/*0930*/ SHF.R.S32.HI R3, RZ, 0x1f, R3 ; /* 0x0000001fff037819 */
/* 0x000fc80000011403 */
/*0940*/ IADD3.X R3, R6, c[0x0][0x17c], R3, P0, P1 ; /* 0x00005f0006037a10 */
/* 0x000fc600007e2403 */
/*0950*/ F2I.U32.TRUNC.NTZ R9, R4 ; /* 0x0000000400097305 */
/* 0x008ee4000020f000 */
/*0960*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe8000c101104 */
/*0970*/ STG.E.U8 [R2.64+0x1], R7 ; /* 0x0000010702007986 */
/* 0x004fe8000c101104 */
/*0980*/ STG.E.U8 [R2.64+0x2], R9 ; /* 0x0000020902007986 */
/* 0x008fe2000c101104 */
/*0990*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09a0*/ BRA 0x9a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.globl _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.p2align 8
.type _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix,@function
_Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix:
s_clause 0x1
s_load_b32 s6, s[2:3], 0x6c
s_load_b64 s[4:5], s[2:3], 0x24
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s6, 0xffff
s_lshr_b32 s6, s6, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s14, s7, v[3:4]
v_mad_u64_u32 v[2:3], null, s15, s6, v[4:5]
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s4, s5, v2
s_and_b32 s4, vcc_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_18
s_clause 0x2
s_load_b64 s[4:5], s[2:3], 0x48
s_load_b32 s11, s[2:3], 0x2c
s_load_b32 s6, s[2:3], 0x50
v_cvt_f32_i32_e32 v7, v1
v_cvt_f32_i32_e32 v8, v2
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
v_cvt_f32_ubyte0_e32 v3, s11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v5, s4, v7 :: v_dual_mov_b32 v6, v3
v_fmac_f32_e32 v5, s5, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v15, s6, v5
v_mov_b32_e32 v5, v3
v_cmpx_ngt_f32_e32 -1.0, v15
s_cbranch_execz .LBB0_17
s_clause 0x2
s_load_b64 s[4:5], s[2:3], 0x54
s_load_b64 s[6:7], s[2:3], 0xc
s_load_b32 s9, s[2:3], 0x5c
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v5, s4, v7
v_cvt_f32_i32_e32 v6, s6
v_mov_b32_e32 v7, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v5, s5, v8
v_cmp_nge_f32_e32 vcc_lo, v15, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v16, s9, v5
v_cvt_f32_i32_e32 v5, s7
v_cmp_nge_f32_e64 s4, v16, v5
v_mov_b32_e32 v5, v3
v_cmp_ngt_f32_e64 s5, -1.0, v16
s_delay_alu instid0(VALU_DEP_3)
s_and_b32 s4, vcc_lo, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s4, s4, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s9, s4
s_cbranch_execz .LBB0_16
s_load_b64 s[0:1], s[0:1], 0x4
v_dual_mov_b32 v10, s11 :: v_dual_and_b32 v3, 0x3ff, v0
v_bfe_u32 v0, v0, 20, 10
s_clause 0x1
s_load_b64 s[4:5], s[2:3], 0x0
s_load_b32 s10, s[2:3], 0x8
s_waitcnt lgkmcnt(0)
s_lshr_b32 s0, s0, 16
v_mul_u32_u24_e32 v4, s1, v4
s_mul_i32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s0, v3
s_mov_b64 s[0:1], src_shared_base
s_mov_b32 s0, exec_lo
v_add3_u32 v0, v3, v4, v0
v_floor_f32_e32 v3, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshl_add_u32 v9, v0, 1, v0
v_floor_f32_e32 v0, v16
v_cvt_i32_f32_e32 v17, v3
ds_store_b8 v9, v10
ds_store_b8 v9, v10 offset:1
ds_store_b8 v9, v10 offset:2
v_cmp_ne_u32_e32 vcc_lo, -1, v9
v_cvt_i32_f32_e32 v0, v0
v_cndmask_b32_e32 v5, 0, v9, vcc_lo
v_cndmask_b32_e64 v6, 0, s1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v3, v5 :: v_dual_add_nc_u32 v18, 1, v17
v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
v_mov_b32_e32 v4, v6
v_cmpx_lt_i32_e32 -1, v0
s_cbranch_execz .LBB0_9
v_mul_lo_u32 v10, v0, s10
v_dual_mov_b32 v3, v5 :: v_dual_mov_b32 v4, v6
s_mov_b32 s1, exec_lo
v_cmpx_lt_i32_e32 -1, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v3, 31, v10
v_lshl_add_u32 v4, v17, 1, v17
v_add_co_u32 v7, vcc_lo, s4, v10
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, v7, v4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v8, vcc_lo
s_or_b32 exec_lo, exec_lo, s1
v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
s_mov_b32 s1, exec_lo
v_cmpx_gt_i32_e64 s6, v18
v_ashrrev_i32_e32 v7, 31, v10
v_lshl_add_u32 v8, v18, 1, v18
v_add_co_u32 v10, vcc_lo, s4, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v7, vcc_lo
v_ashrrev_i32_e32 v12, 31, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v10, v8
v_add_co_ci_u32_e32 v8, vcc_lo, v11, v12, vcc_lo
s_or_b32 exec_lo, exec_lo, s1
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v10, 2, v9
v_dual_mov_b32 v14, v6 :: v_dual_add_nc_u32 v11, 1, v9
v_mov_b32_e32 v13, v5
s_mov_b64 s[12:13], src_shared_base
v_cmp_ne_u32_e32 vcc_lo, -1, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e64 s0, -1, v11
v_add_nc_u32_e32 v19, 1, v0
v_cndmask_b32_e32 v9, 0, v10, vcc_lo
v_cndmask_b32_e64 v11, 0, v11, s0
v_cndmask_b32_e64 v10, 0, s13, vcc_lo
v_cndmask_b32_e64 v12, 0, s13, s0
s_mov_b32 s0, exec_lo
v_cmpx_gt_i32_e64 s7, v19
s_cbranch_execz .LBB0_15
v_mul_lo_u32 v19, v19, s10
v_dual_mov_b32 v14, v6 :: v_dual_mov_b32 v13, v5
s_mov_b32 s1, exec_lo
v_cmpx_lt_i32_e32 -1, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v13, 31, v19
v_lshl_add_u32 v14, v17, 1, v17
v_add_co_u32 v20, vcc_lo, s4, v19
v_add_co_ci_u32_e32 v21, vcc_lo, s5, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v13, vcc_lo, v20, v14
v_add_co_ci_u32_e32 v14, vcc_lo, 0, v21, vcc_lo
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s1, exec_lo
v_cmpx_gt_i32_e64 s6, v18
v_ashrrev_i32_e32 v5, 31, v19
v_lshl_add_u32 v6, v18, 1, v18
v_add_co_u32 v9, vcc_lo, s4, v19
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v5, vcc_lo
v_ashrrev_i32_e32 v11, 31, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v9, v6
v_add_co_ci_u32_e32 v6, vcc_lo, v10, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, v5, 2
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v6, vcc_lo
v_add_co_u32 v11, vcc_lo, v5, 1
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v6, vcc_lo
s_or_b32 exec_lo, exec_lo, s1
.LBB0_15:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s0
flat_load_u8 v18, v[3:4]
flat_load_u8 v19, v[7:8]
flat_load_u8 v20, v[13:14]
flat_load_u8 v5, v[5:6]
s_clause 0x1
flat_load_u8 v6, v[7:8] offset:1
flat_load_u8 v7, v[7:8] offset:2
s_clause 0x1
flat_load_u8 v8, v[3:4] offset:1
flat_load_u8 v3, v[3:4] offset:2
s_clause 0x1
flat_load_u8 v4, v[13:14] offset:1
flat_load_u8 v13, v[13:14] offset:2
flat_load_u8 v11, v[11:12]
flat_load_u8 v9, v[9:10]
v_cvt_f32_i32_e32 v0, v0
v_cvt_f32_i32_e32 v10, v17
s_waitcnt vmcnt(9) lgkmcnt(9)
v_cvt_f32_ubyte0_e32 v17, v20
s_waitcnt vmcnt(8) lgkmcnt(8)
v_cvt_f32_ubyte0_e32 v5, v5
s_waitcnt vmcnt(7) lgkmcnt(7)
v_cvt_f32_ubyte0_e32 v6, v6
s_waitcnt vmcnt(6) lgkmcnt(6)
v_cvt_f32_ubyte0_e32 v7, v7
v_sub_f32_e32 v0, v16, v0
s_waitcnt vmcnt(4) lgkmcnt(4)
v_cvt_f32_ubyte0_e32 v3, v3
v_sub_f32_e32 v10, v15, v10
v_cvt_f32_ubyte0_e32 v8, v8
s_waitcnt vmcnt(3) lgkmcnt(3)
v_cvt_f32_ubyte0_e32 v4, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_sub_f32 v12, 1.0, v0 :: v_dual_mul_f32 v15, v0, v10
v_sub_f32_e32 v14, 1.0, v10
v_mul_f32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f32_e32 v16, v12, v14
v_cvt_f32_ubyte0_e32 v12, v18
v_dual_mul_f32 v7, v10, v7 :: v_dual_mul_f32 v0, v0, v14
v_cvt_f32_ubyte0_e32 v14, v19
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_mul_f32 v6, v10, v6 :: v_dual_fmac_f32 v7, v16, v3
s_waitcnt vmcnt(1) lgkmcnt(1)
v_cvt_f32_ubyte0_e32 v3, v11
v_mul_f32_e32 v14, v10, v14
v_cvt_f32_ubyte0_e32 v10, v13
v_fmac_f32_e32 v6, v16, v8
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cvt_f32_ubyte0_e32 v8, v9
v_fmac_f32_e32 v14, v16, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v6, v0, v4
v_fmac_f32_e32 v14, v0, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v7, v0, v10 :: v_dual_fmac_f32 v6, v15, v3
v_fmac_f32_e32 v14, v15, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v7, v15, v8 :: v_dual_add_f32 v4, 0.5, v6
v_add_f32_e32 v0, 0.5, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v6, 0.5, v7
v_floor_f32_e32 v5, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_floor_f32_e32 v3, v0
v_floor_f32_e32 v7, v6
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v6, v3
v_mov_b32_e32 v3, v7
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s8
s_clause 0x1
s_load_b32 s4, s[2:3], 0x20
s_load_b64 s[0:1], s[2:3], 0x18
v_lshl_add_u32 v1, v1, 1, v1
v_cvt_i32_f32_e32 v6, v6
v_cvt_i32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v1
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v0, v2, s4
v_ashrrev_i32_e32 v2, 31, v0
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
v_add_co_u32 v0, vcc_lo, v0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, v2, v4, vcc_lo
v_cvt_i32_f32_e32 v2, v5
s_clause 0x2
global_store_b8 v[0:1], v6, off
global_store_b8 v[0:1], v2, off offset:1
global_store_b8 v[0:1], v3, off offset:2
.LBB0_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.amdhsa_group_segment_fixed_size 3072
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 352
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 1
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 22
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix, .Lfunc_end0-_Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 1
.value_kind: by_value
- .offset: 48
.size: 48
.value_kind: by_value
- .offset: 96
.size: 4
.value_kind: hidden_block_count_x
- .offset: 100
.size: 4
.value_kind: hidden_block_count_y
- .offset: 104
.size: 4
.value_kind: hidden_block_count_z
- .offset: 108
.size: 2
.value_kind: hidden_group_size_x
- .offset: 110
.size: 2
.value_kind: hidden_group_size_y
- .offset: 112
.size: 2
.value_kind: hidden_group_size_z
- .offset: 114
.size: 2
.value_kind: hidden_remainder_x
- .offset: 116
.size: 2
.value_kind: hidden_remainder_y
- .offset: 118
.size: 2
.value_kind: hidden_remainder_z
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 152
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 160
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 3072
.kernarg_segment_align: 8
.kernarg_segment_size: 352
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 22
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c5cd3_00000000-6_affine.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2036:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2036:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14affine_projectPfiiS_S_
.type _Z14affine_projectPfiiS_S_, @function
_Z14affine_projectPfiiS_S_:
.LFB2032:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2032:
.size _Z14affine_projectPfiiS_S_, .-_Z14affine_projectPfiiS_S_
.globl _Z70__device_stub__Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrixPhiiiS_iiihR12AffineMatrix
.type _Z70__device_stub__Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrixPhiiiS_iiihR12AffineMatrix, @function
_Z70__device_stub__Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrixPhiiiS_iiihR12AffineMatrix:
.LFB2058:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movl %ecx, 28(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 24(%rsp)
movl 240(%rsp), %eax
movb %al, 12(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
movq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z70__device_stub__Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrixPhiiiS_iiihR12AffineMatrix, .-_Z70__device_stub__Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrixPhiiiS_iiihR12AffineMatrix
.globl _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.type _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix, @function
_Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 40(%rsp), %rax
pushq %rax
.cfi_def_cfa_offset 24
movzbl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z70__device_stub__Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrixPhiiiS_iiihR12AffineMatrix
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix, .-_Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.globl _Z20warp_affine_bilinearPhiiiS_iiih
.type _Z20warp_affine_bilinearPhiiiS_iiih, @function
_Z20warp_affine_bilinearPhiiiS_iiih:
.LFB2033:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 24(%rsp)
movl %esi, 36(%rsp)
movl %edx, %r13d
movl %ecx, %r12d
movq %r8, 40(%rsp)
movl %r9d, %r14d
movl 208(%rsp), %ebx
movl 216(%rsp), %ebp
movl 224(%rsp), %r15d
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $32, 56(%rsp)
movl $32, 60(%rsp)
movl $1, 64(%rsp)
leal 62(%rbx), %eax
movl %ebx, %edx
addl $31, %edx
cmovns %edx, %eax
sarl $5, %eax
movl %eax, 68(%rsp)
leal 62(%rbp), %eax
movl %ebp, %edx
addl $31, %edx
cmovns %edx, %eax
sarl $5, %eax
movl %eax, 72(%rsp)
movl $1, 76(%rsp)
pxor %xmm6, %xmm6
cvtsi2ssl %r13d, %xmm6
movss %xmm6, 16(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
divss %xmm6, %xmm0
pxor %xmm3, %xmm3
cvtsi2ssl %ecx, %xmm3
movss %xmm3, 20(%rsp)
pxor %xmm1, %xmm1
cvtsi2ssl %ebp, %xmm1
divss %xmm3, %xmm1
minss %xmm1, %xmm0
movss %xmm0, 32(%rsp)
mulss %xmm0, %xmm0
pxor %xmm1, %xmm1
ucomiss %xmm1, %xmm0
jp .L22
movss %xmm1, 12(%rsp)
jne .L22
.L16:
movl 64(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movq 68(%rsp), %rdi
movl 76(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L13:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movss .LC1(%rip), %xmm1
divss %xmm0, %xmm1
movss %xmm1, 12(%rsp)
jmp .L16
.L24:
movss .LC2(%rip), %xmm3
movss 32(%rsp), %xmm6
movaps %xmm6, %xmm1
xorps %xmm3, %xmm1
pxor %xmm5, %xmm5
cvtss2sd %xmm6, %xmm5
movsd .LC3(%rip), %xmm4
mulsd %xmm4, %xmm5
movss 16(%rsp), %xmm2
mulss %xmm1, %xmm2
cvtss2sd %xmm2, %xmm2
mulsd %xmm4, %xmm2
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
mulsd %xmm4, %xmm0
addsd %xmm0, %xmm2
addsd %xmm5, %xmm2
subsd %xmm4, %xmm2
cvtsd2ss %xmm2, %xmm2
mulss 20(%rsp), %xmm1
cvtss2sd %xmm1, %xmm1
mulsd %xmm4, %xmm1
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd %xmm4, %xmm0
addsd %xmm1, %xmm0
addsd %xmm5, %xmm0
subsd %xmm4, %xmm0
cvtsd2ss %xmm0, %xmm0
movaps %xmm6, %xmm5
movss 12(%rsp), %xmm4
mulss %xmm4, %xmm5
mulss .LC4(%rip), %xmm4
movaps %xmm4, %xmm1
movss %xmm6, 80(%rsp)
movl $0x00000000, 84(%rsp)
movss %xmm2, 88(%rsp)
movl $0x00000000, 92(%rsp)
movss %xmm6, 96(%rsp)
movss %xmm0, 100(%rsp)
movss %xmm5, 104(%rsp)
movss %xmm4, 108(%rsp)
movaps %xmm5, %xmm4
xorps %xmm3, %xmm4
mulss %xmm2, %xmm4
movaps %xmm0, %xmm6
mulss %xmm1, %xmm6
subss %xmm6, %xmm4
movss %xmm4, 112(%rsp)
movss %xmm1, 116(%rsp)
movss %xmm5, 120(%rsp)
xorps %xmm3, %xmm1
mulss %xmm2, %xmm1
mulss %xmm5, %xmm0
subss %xmm0, %xmm1
movss %xmm1, 124(%rsp)
leaq 80(%rsp), %rax
pushq %rax
.cfi_def_cfa_offset 216
movzbl %r15b, %r15d
pushq %r15
.cfi_def_cfa_offset 224
pushq %rbp
.cfi_def_cfa_offset 232
pushq %rbx
.cfi_def_cfa_offset 240
movl %r14d, %r9d
movq 72(%rsp), %r8
movl %r12d, %ecx
movl %r13d, %edx
movl 68(%rsp), %esi
movq 56(%rsp), %rdi
call _Z70__device_stub__Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrixPhiiiS_iiihR12AffineMatrix
addq $32, %rsp
.cfi_def_cfa_offset 208
jmp .L13
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2033:
.size _Z20warp_affine_bilinearPhiiiS_iiih, .-_Z20warp_affine_bilinearPhiiiS_iiih
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC2:
.long -2147483648
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1071644672
.set .LC4,.LC2
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "affine.hip"
.globl _Z42__device_stub__warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix # -- Begin function _Z42__device_stub__warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.p2align 4, 0x90
.type _Z42__device_stub__warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix,@function
_Z42__device_stub__warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix: # @_Z42__device_stub__warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z42__device_stub__warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix, .Lfunc_end0-_Z42__device_stub__warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z20warp_affine_bilinearPhiiiS_iiih
.LCPI1_0:
.long 0x3f800000 # float 1
.LCPI1_1:
.long 0x80000000 # float -0
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_2:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_3:
.quad 0x3fe0000000000000 # double 0.5
.LCPI1_4:
.quad 0xbfe0000000000000 # double -0.5
.text
.globl _Z20warp_affine_bilinearPhiiiS_iiih
.p2align 4, 0x90
.type _Z20warp_affine_bilinearPhiiiS_iiih,@function
_Z20warp_affine_bilinearPhiiiS_iiih: # @_Z20warp_affine_bilinearPhiiiS_iiih
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, 12(%rsp) # 4-byte Spill
movq %r8, 88(%rsp) # 8-byte Spill
movl %ecx, %r15d
movl %edx, %ebx
movl %esi, %ebp
movl 312(%rsp), %r12d
movl 304(%rsp), %r14d
leal 31(%r14), %eax
leal 62(%r14), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $5, %ecx
leal 31(%r12), %edx
leal 62(%r12), %eax
testl %edx, %edx
cmovnsl %edx, %eax
movq %rdi, %r13
sarl $5, %eax
shlq $32, %rax
orq %rcx, %rax
movabsq $137438953504, %rdx # imm = 0x2000000020
movq %rax, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.1:
movq %r13, %rdi
movq 88(%rsp), %r13 # 8-byte Reload
movl 12(%rsp), %esi # 4-byte Reload
cvtsi2ss %r14d, %xmm0
cvtsi2ss %ebx, %xmm6
cvtsi2ss %r12d, %xmm1
movzbl 320(%rsp), %eax
cvtsi2ss %r15d, %xmm5
divss %xmm6, %xmm0
divss %xmm5, %xmm1
minss %xmm1, %xmm0
movaps %xmm0, %xmm2
mulss %xmm0, %xmm2
xorps %xmm1, %xmm1
ucomiss %xmm1, %xmm2
jne .LBB1_2
jnp .LBB1_3
.LBB1_2: # %select.true.sink
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm2, %xmm1
.LBB1_3: # %select.end
movss .LCPI1_1(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
mulss %xmm1, %xmm2
movaps .LCPI1_2(%rip), %xmm4 # xmm4 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
movaps %xmm2, %xmm3
xorps %xmm4, %xmm3
cvtss2sd %xmm0, %xmm7
movsd .LCPI1_3(%rip), %xmm8 # xmm8 = mem[0],zero
mulsd %xmm8, %xmm7
cvtsi2sd %r14d, %xmm9
mulsd %xmm8, %xmm9
mulss %xmm0, %xmm6
cvtss2sd %xmm6, %xmm6
movsd .LCPI1_4(%rip), %xmm10 # xmm10 = mem[0],zero
mulsd %xmm10, %xmm6
addsd %xmm9, %xmm6
addsd %xmm7, %xmm6
addsd %xmm10, %xmm6
cvtsd2ss %xmm6, %xmm6
mulss %xmm6, %xmm3
mulss %xmm0, %xmm1
xorps %xmm9, %xmm9
cvtsi2sd %r12d, %xmm9
mulsd %xmm8, %xmm9
mulss %xmm0, %xmm5
cvtss2sd %xmm5, %xmm5
mulsd %xmm10, %xmm5
addsd %xmm9, %xmm5
addsd %xmm7, %xmm5
addsd %xmm10, %xmm5
cvtsd2ss %xmm5, %xmm5
movaps %xmm1, %xmm7
mulss %xmm5, %xmm7
subss %xmm7, %xmm3
xorps %xmm1, %xmm4
mulss %xmm6, %xmm4
movaps %xmm2, %xmm7
mulss %xmm5, %xmm7
subss %xmm7, %xmm4
movss %xmm0, 40(%rsp)
movl $0, 44(%rsp)
movss %xmm6, 48(%rsp)
movl $0, 52(%rsp)
movss %xmm0, 56(%rsp)
movss %xmm5, 60(%rsp)
movss %xmm1, 64(%rsp)
movss %xmm2, 68(%rsp)
movss %xmm4, 72(%rsp)
movss %xmm2, 76(%rsp)
movss %xmm1, 80(%rsp)
movss %xmm3, 84(%rsp)
movq %rdi, 152(%rsp)
movl %ebp, 36(%rsp)
movl %ebx, 32(%rsp)
movl %r15d, 28(%rsp)
movq %r13, 144(%rsp)
movl %esi, 24(%rsp)
movl %r14d, 20(%rsp)
movl %r12d, 16(%rsp)
movb %al, 11(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 36(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rax
movq %rax, 176(%rsp)
leaq 28(%rsp), %rax
movq %rax, 184(%rsp)
leaq 144(%rsp), %rax
movq %rax, 192(%rsp)
leaq 24(%rsp), %rax
movq %rax, 200(%rsp)
leaq 20(%rsp), %rax
movq %rax, 208(%rsp)
leaq 16(%rsp), %rax
movq %rax, 216(%rsp)
leaq 11(%rsp), %rax
movq %rax, 224(%rsp)
leaq 40(%rsp), %rax
movq %rax, 232(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z20warp_affine_bilinearPhiiiS_iiih, .Lfunc_end1-_Z20warp_affine_bilinearPhiiiS_iiih
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix,@object # @_Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.section .rodata,"a",@progbits
.globl _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.p2align 3, 0x0
_Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix:
.quad _Z42__device_stub__warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.size _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix"
.size .L__unnamed_1, 57
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27warp_affine_bilinear_kernelPhiiiS_iiih12AffineMatrix
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
# define MAX(a, b) ((a) > (b) ? (a) : (b))
# define GAUSSIAN_KERNEL_SIZE 3
# define SOBEL_KERNEL_SIZE 5
# define TILE_WIDTH 32
# define SMEM_SIZE 128
__global__ void lowHysterisis(int width, int height, float *d_nonMax, float* d_highThreshHyst, float lowThreshold, float *d_lowThreshHyst) {
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.y * blockDim.y;
if ((ix > 0) && (ix < (width - 1)) && (iy > 0) && iy < (height - 1)) {
int tid = iy * width + ix;
d_lowThreshHyst[tid] = d_highThreshHyst[tid];
if (d_highThreshHyst[tid] == 1) {
// Determine neighbour indices
int eastN = tid + 1;
int westN = tid - 1;
int northN = tid - width;
int southN = tid + width;
int southEastN = southN + 1;
int northEastN = northN + 1;
int southWestN = southN - 1;
int northWestN = northN - 1;
if (d_nonMax[eastN] > lowThreshold)
d_lowThreshHyst[eastN] = 1.0f;
if (d_nonMax[westN] > lowThreshold)
d_lowThreshHyst[westN] = 1.0f;
if (d_nonMax[northN] > lowThreshold)
d_lowThreshHyst[northN] = 1.0f;
if (d_nonMax[southN] > lowThreshold)
d_lowThreshHyst[southN] = 1.0f;
if (d_nonMax[southEastN] > lowThreshold)
d_lowThreshHyst[southEastN] = 1.0f;
if (d_nonMax[northEastN] > lowThreshold)
d_lowThreshHyst[northEastN] = 1.0f;
if (d_nonMax[southWestN] > lowThreshold)
d_lowThreshHyst[southWestN] = 1.0f;
if (d_nonMax[northWestN] > lowThreshold)
d_lowThreshHyst[northWestN] = 1.0f;
}
}
} | code for sm_80
Function : _Z13lowHysterisisiiPfS_fS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe40000000000 */
/*0030*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ UIADD3 UR4, -UR5, UR6, URZ ; /* 0x0000000605047290 */
/* 0x000fc6000fffe13f */
/*0060*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0070*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0090*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe2000bf06270 */
/*00a0*/ UIADD3 UR4, -UR5, UR7, URZ ; /* 0x0000000705047290 */
/* 0x000fe2000fffe13f */
/*00b0*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fe400078e0205 */
/*00c0*/ ISETP.LT.OR P0, PT, R0, 0x1, P0 ; /* 0x000000010000780c */
/* 0x000fc80000701670 */
/*00d0*/ ISETP.LT.OR P0, PT, R3, 0x1, P0 ; /* 0x000000010300780c */
/* 0x000fc80000701670 */
/*00e0*/ ISETP.GE.OR P0, PT, R3, UR4, P0 ; /* 0x0000000403007c0c */
/* 0x000fda0008706670 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0110*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0120*/ IMAD R0, R3, c[0x0][0x160], R0 ; /* 0x0000580003007a24 */
/* 0x000fc800078e0200 */
/*0130*/ IMAD.WIDE R4, R0, R7, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fca00078e0207 */
/*0140*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IMAD.WIDE R2, R0, R7, c[0x0][0x180] ; /* 0x0000600000027625 */
/* 0x000fca00078e0207 */
/*0160*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0041e8000c101904 */
/*0170*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0180*/ FSETP.NEU.AND P0, PT, R6, 1, PT ; /* 0x3f8000000600780b */
/* 0x004fda0003f0d000 */
/*0190*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.WIDE R8, R0, R7, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x001fca00078e0207 */
/*01b0*/ LDG.E R4, [R8.64+0x4] ; /* 0x0000040408047981 */
/* 0x000ea4000c1e1900 */
/*01c0*/ FSETP.GT.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0b */
/* 0x004fda0003f04000 */
/*01d0*/ @P0 IMAD.MOV.U32 R15, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff0f0424 */
/* 0x000fca00078e00ff */
/*01e0*/ @P0 STG.E [R2.64+0x4], R15 ; /* 0x0000040f02000986 */
/* 0x0001e8000c101904 */
/*01f0*/ LDG.E R4, [R8.64+-0x4] ; /* 0xfffffc0408047981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IADD3 R6, R0, -c[0x0][0x160], RZ ; /* 0x8000580000067a10 */
/* 0x000fe40007ffe0ff */
/*0210*/ FSETP.GT.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0b */
/* 0x004fc60003f04000 */
/*0220*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fd400078e0207 */
/*0230*/ @P0 IMAD.MOV.U32 R17, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff110424 */
/* 0x000fca00078e00ff */
/*0240*/ @P0 STG.E [R2.64+-0x4], R17 ; /* 0xfffffc1102000986 */
/* 0x0003e8000c101904 */
/*0250*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea2000c1e1900 */
/*0260*/ SHF.R.S32.HI R11, RZ, 0x1f, R6 ; /* 0x0000001fff0b7819 */
/* 0x000fe40000011406 */
/*0270*/ IADD3 R0, R0, c[0x0][0x160], RZ ; /* 0x0000580000007a10 */
/* 0x000fca0007ffe0ff */
/*0280*/ IMAD.WIDE R8, R0, R7, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x000fe200078e0207 */
/*0290*/ FSETP.GT.AND P0, PT, R10, c[0x0][0x178], PT ; /* 0x00005e000a007a0b */
/* 0x004fda0003f04000 */
/*02a0*/ @P0 LEA R12, P1, R6, c[0x0][0x180], 0x2 ; /* 0x00006000060c0a11 */
/* 0x000fe200078210ff */
/*02b0*/ @P0 IMAD.MOV.U32 R15, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff0f0424 */
/* 0x001fc600078e00ff */
/*02c0*/ @P0 LEA.HI.X R13, R6, c[0x0][0x184], R11, 0x2, P1 ; /* 0x00006100060d0a11 */
/* 0x000fca00008f140b */
/*02d0*/ @P0 STG.E [R12.64], R15 ; /* 0x0000000f0c000986 */
/* 0x000fe8000c101904 */
/*02e0*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x000ea4000c1e1900 */
/*02f0*/ FSETP.GT.AND P0, PT, R10, c[0x0][0x178], PT ; /* 0x00005e000a007a0b */
/* 0x004fda0003f04000 */
/*0300*/ @P0 IMAD.WIDE R2, R7, c[0x0][0x160], R2 ; /* 0x0000580007020a25 */
/* 0x002fe200078e0202 */
/*0310*/ @P0 MOV R17, 0x3f800000 ; /* 0x3f80000000110802 */
/* 0x000fca0000000f00 */
/*0320*/ @P0 STG.E [R2.64], R17 ; /* 0x0000001102000986 */
/* 0x0001e8000c101904 */
/*0330*/ LDG.E R10, [R8.64+0x4] ; /* 0x00000404080a7981 */
/* 0x000ea4000c1e1900 */
/*0340*/ FSETP.GT.AND P0, PT, R10, c[0x0][0x178], PT ; /* 0x00005e000a007a0b */
/* 0x004fe40003f04000 */
/*0350*/ IADD3 R10, R0, -0x1, RZ ; /* 0xffffffff000a7810 */
/* 0x000fca0007ffe0ff */
/*0360*/ IMAD.WIDE R10, R10, R7, c[0x0][0x180] ; /* 0x000060000a0a7625 */
/* 0x000fcc00078e0207 */
/*0370*/ @P0 IMAD.MOV.U32 R19, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff130424 */
/* 0x000fca00078e00ff */
/*0380*/ @P0 STG.E [R10.64+0x8], R19 ; /* 0x000008130a000986 */
/* 0x0003e8000c101904 */
/*0390*/ LDG.E R0, [R4.64+0x4] ; /* 0x0000040404007981 */
/* 0x000ea2000c1e1900 */
/*03a0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fca0007ffe0ff */
/*03b0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x180] ; /* 0x0000600006067625 */
/* 0x000fe200078e0207 */
/*03c0*/ FSETP.GT.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0b */
/* 0x004fda0003f04000 */
/*03d0*/ @P0 IMAD.MOV.U32 R3, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff030424 */
/* 0x001fca00078e00ff */
/*03e0*/ @P0 STG.E [R6.64+0x8], R3 ; /* 0x0000080306000986 */
/* 0x0003e8000c101904 */
/*03f0*/ LDG.E R8, [R8.64+-0x4] ; /* 0xfffffc0408087981 */
/* 0x000ea4000c1e1900 */
/*0400*/ FSETP.GT.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0b */
/* 0x004fda0003f04000 */
/*0410*/ @P0 MOV R13, 0x3f800000 ; /* 0x3f800000000d0802 */
/* 0x000fca0000000f00 */
/*0420*/ @P0 STG.E [R10.64], R13 ; /* 0x0000000d0a000986 */
/* 0x0003e8000c101904 */
/*0430*/ LDG.E R0, [R4.64+-0x4] ; /* 0xfffffc0404007981 */
/* 0x000ea4000c1e1900 */
/*0440*/ FSETP.GT.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0b */
/* 0x004fda0003f04000 */
/*0450*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0460*/ IMAD.MOV.U32 R3, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff037424 */
/* 0x002fca00078e00ff */
/*0470*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x000fe2000c101904 */
/*0480*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0490*/ BRA 0x490; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
# define MAX(a, b) ((a) > (b) ? (a) : (b))
# define GAUSSIAN_KERNEL_SIZE 3
# define SOBEL_KERNEL_SIZE 5
# define TILE_WIDTH 32
# define SMEM_SIZE 128
__global__ void lowHysterisis(int width, int height, float *d_nonMax, float* d_highThreshHyst, float lowThreshold, float *d_lowThreshHyst) {
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.y * blockDim.y;
if ((ix > 0) && (ix < (width - 1)) && (iy > 0) && iy < (height - 1)) {
int tid = iy * width + ix;
d_lowThreshHyst[tid] = d_highThreshHyst[tid];
if (d_highThreshHyst[tid] == 1) {
// Determine neighbour indices
int eastN = tid + 1;
int westN = tid - 1;
int northN = tid - width;
int southN = tid + width;
int southEastN = southN + 1;
int northEastN = northN + 1;
int southWestN = southN - 1;
int northWestN = northN - 1;
if (d_nonMax[eastN] > lowThreshold)
d_lowThreshHyst[eastN] = 1.0f;
if (d_nonMax[westN] > lowThreshold)
d_lowThreshHyst[westN] = 1.0f;
if (d_nonMax[northN] > lowThreshold)
d_lowThreshHyst[northN] = 1.0f;
if (d_nonMax[southN] > lowThreshold)
d_lowThreshHyst[southN] = 1.0f;
if (d_nonMax[southEastN] > lowThreshold)
d_lowThreshHyst[southEastN] = 1.0f;
if (d_nonMax[northEastN] > lowThreshold)
d_lowThreshHyst[northEastN] = 1.0f;
if (d_nonMax[southWestN] > lowThreshold)
d_lowThreshHyst[southWestN] = 1.0f;
if (d_nonMax[northWestN] > lowThreshold)
d_lowThreshHyst[northWestN] = 1.0f;
}
}
} | .file "tmpxft_001442a4_00000000-6_lowHysterisis.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z13lowHysterisisiiPfS_fS_iiPfS_fS_
.type _Z40__device_stub__Z13lowHysterisisiiPfS_fS_iiPfS_fS_, @function
_Z40__device_stub__Z13lowHysterisisiiPfS_fS_iiPfS_fS_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13lowHysterisisiiPfS_fS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z13lowHysterisisiiPfS_fS_iiPfS_fS_, .-_Z40__device_stub__Z13lowHysterisisiiPfS_fS_iiPfS_fS_
.globl _Z13lowHysterisisiiPfS_fS_
.type _Z13lowHysterisisiiPfS_fS_, @function
_Z13lowHysterisisiiPfS_fS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13lowHysterisisiiPfS_fS_iiPfS_fS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13lowHysterisisiiPfS_fS_, .-_Z13lowHysterisisiiPfS_fS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13lowHysterisisiiPfS_fS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13lowHysterisisiiPfS_fS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
# define MAX(a, b) ((a) > (b) ? (a) : (b))
# define GAUSSIAN_KERNEL_SIZE 3
# define SOBEL_KERNEL_SIZE 5
# define TILE_WIDTH 32
# define SMEM_SIZE 128
__global__ void lowHysterisis(int width, int height, float *d_nonMax, float* d_highThreshHyst, float lowThreshold, float *d_lowThreshHyst) {
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.y * blockDim.y;
if ((ix > 0) && (ix < (width - 1)) && (iy > 0) && iy < (height - 1)) {
int tid = iy * width + ix;
d_lowThreshHyst[tid] = d_highThreshHyst[tid];
if (d_highThreshHyst[tid] == 1) {
// Determine neighbour indices
int eastN = tid + 1;
int westN = tid - 1;
int northN = tid - width;
int southN = tid + width;
int southEastN = southN + 1;
int northEastN = northN + 1;
int southWestN = southN - 1;
int northWestN = northN - 1;
if (d_nonMax[eastN] > lowThreshold)
d_lowThreshHyst[eastN] = 1.0f;
if (d_nonMax[westN] > lowThreshold)
d_lowThreshHyst[westN] = 1.0f;
if (d_nonMax[northN] > lowThreshold)
d_lowThreshHyst[northN] = 1.0f;
if (d_nonMax[southN] > lowThreshold)
d_lowThreshHyst[southN] = 1.0f;
if (d_nonMax[southEastN] > lowThreshold)
d_lowThreshHyst[southEastN] = 1.0f;
if (d_nonMax[northEastN] > lowThreshold)
d_lowThreshHyst[northEastN] = 1.0f;
if (d_nonMax[southWestN] > lowThreshold)
d_lowThreshHyst[southWestN] = 1.0f;
if (d_nonMax[northWestN] > lowThreshold)
d_lowThreshHyst[northWestN] = 1.0f;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
# define MAX(a, b) ((a) > (b) ? (a) : (b))
# define GAUSSIAN_KERNEL_SIZE 3
# define SOBEL_KERNEL_SIZE 5
# define TILE_WIDTH 32
# define SMEM_SIZE 128
__global__ void lowHysterisis(int width, int height, float *d_nonMax, float* d_highThreshHyst, float lowThreshold, float *d_lowThreshHyst) {
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.y * blockDim.y;
if ((ix > 0) && (ix < (width - 1)) && (iy > 0) && iy < (height - 1)) {
int tid = iy * width + ix;
d_lowThreshHyst[tid] = d_highThreshHyst[tid];
if (d_highThreshHyst[tid] == 1) {
// Determine neighbour indices
int eastN = tid + 1;
int westN = tid - 1;
int northN = tid - width;
int southN = tid + width;
int southEastN = southN + 1;
int northEastN = northN + 1;
int southWestN = southN - 1;
int northWestN = northN - 1;
if (d_nonMax[eastN] > lowThreshold)
d_lowThreshHyst[eastN] = 1.0f;
if (d_nonMax[westN] > lowThreshold)
d_lowThreshHyst[westN] = 1.0f;
if (d_nonMax[northN] > lowThreshold)
d_lowThreshHyst[northN] = 1.0f;
if (d_nonMax[southN] > lowThreshold)
d_lowThreshHyst[southN] = 1.0f;
if (d_nonMax[southEastN] > lowThreshold)
d_lowThreshHyst[southEastN] = 1.0f;
if (d_nonMax[northEastN] > lowThreshold)
d_lowThreshHyst[northEastN] = 1.0f;
if (d_nonMax[southWestN] > lowThreshold)
d_lowThreshHyst[southWestN] = 1.0f;
if (d_nonMax[northWestN] > lowThreshold)
d_lowThreshHyst[northWestN] = 1.0f;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
# define MAX(a, b) ((a) > (b) ? (a) : (b))
# define GAUSSIAN_KERNEL_SIZE 3
# define SOBEL_KERNEL_SIZE 5
# define TILE_WIDTH 32
# define SMEM_SIZE 128
__global__ void lowHysterisis(int width, int height, float *d_nonMax, float* d_highThreshHyst, float lowThreshold, float *d_lowThreshHyst) {
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.y * blockDim.y;
if ((ix > 0) && (ix < (width - 1)) && (iy > 0) && iy < (height - 1)) {
int tid = iy * width + ix;
d_lowThreshHyst[tid] = d_highThreshHyst[tid];
if (d_highThreshHyst[tid] == 1) {
// Determine neighbour indices
int eastN = tid + 1;
int westN = tid - 1;
int northN = tid - width;
int southN = tid + width;
int southEastN = southN + 1;
int northEastN = northN + 1;
int southWestN = southN - 1;
int northWestN = northN - 1;
if (d_nonMax[eastN] > lowThreshold)
d_lowThreshHyst[eastN] = 1.0f;
if (d_nonMax[westN] > lowThreshold)
d_lowThreshHyst[westN] = 1.0f;
if (d_nonMax[northN] > lowThreshold)
d_lowThreshHyst[northN] = 1.0f;
if (d_nonMax[southN] > lowThreshold)
d_lowThreshHyst[southN] = 1.0f;
if (d_nonMax[southEastN] > lowThreshold)
d_lowThreshHyst[southEastN] = 1.0f;
if (d_nonMax[northEastN] > lowThreshold)
d_lowThreshHyst[northEastN] = 1.0f;
if (d_nonMax[southWestN] > lowThreshold)
d_lowThreshHyst[southWestN] = 1.0f;
if (d_nonMax[northWestN] > lowThreshold)
d_lowThreshHyst[northWestN] = 1.0f;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13lowHysterisisiiPfS_fS_
.globl _Z13lowHysterisisiiPfS_fS_
.p2align 8
.type _Z13lowHysterisisiiPfS_fS_,@function
_Z13lowHysterisisiiPfS_fS_:
s_load_b32 s4, s[0:1], 0x34
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
s_mov_b32 s4, exec_lo
v_cmpx_lt_i32_e32 0, v1
s_cbranch_execz .LBB0_19
s_load_b32 s2, s[2:3], 0xc
s_load_b64 s[6:7], s[0:1], 0x0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_add_i32 s3, s7, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
s_add_i32 s2, s6, -1
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s2, s3, v4
v_cmp_lt_i32_e64 s3, 0, v4
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_19
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x20
v_mad_u64_u32 v[2:3], null, v4, s6, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v5, v[3:4], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v5, off
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_eq_f32_e32 vcc_lo, 1.0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_19
s_load_b64 s[4:5], s[0:1], 0x8
v_add_nc_u32_e32 v0, 1, v2
s_load_b32 s0, s[0:1], 0x18
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[3:4], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 s0, v3
s_cbranch_execz .LBB0_5
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_mov_b32_e32 v3, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v0, -1, v2
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v1, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 s0, v3
s_cbranch_execz .LBB0_7
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_mov_b32_e32 v3, 1.0
global_store_b32 v[0:1], v3, off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s1
v_subrev_nc_u32_e32 v0, s6, v2
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[3:4], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 s0, v3
s_cbranch_execz .LBB0_9
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_mov_b32_e32 v1, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_store_b32 v[3:4], v1, off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v1, s6, v2
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 s0, v4
s_cbranch_execz .LBB0_11
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_mov_b32_e32 v4, 1.0
global_store_b32 v[2:3], v4, off
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v2, 1, v1
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 s0, v4
s_cbranch_execz .LBB0_13
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_mov_b32_e32 v4, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[2:3], v4, off
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v2, 1, v0
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 s0, v4
s_cbranch_execz .LBB0_15
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_mov_b32_e32 v4, 1.0
global_store_b32 v[2:3], v4, off
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v1, -1, v1
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 s0, v3
s_cbranch_execz .LBB0_17
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_mov_b32_e32 v3, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_store_b32 v[1:2], v3, off
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v0, -1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_lt_f32_e32 vcc_lo, s0, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_19
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_mov_b32_e32 v2, 1.0
global_store_b32 v[0:1], v2, off
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13lowHysterisisiiPfS_fS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13lowHysterisisiiPfS_fS_, .Lfunc_end0-_Z13lowHysterisisiiPfS_fS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13lowHysterisisiiPfS_fS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13lowHysterisisiiPfS_fS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
# define MAX(a, b) ((a) > (b) ? (a) : (b))
# define GAUSSIAN_KERNEL_SIZE 3
# define SOBEL_KERNEL_SIZE 5
# define TILE_WIDTH 32
# define SMEM_SIZE 128
__global__ void lowHysterisis(int width, int height, float *d_nonMax, float* d_highThreshHyst, float lowThreshold, float *d_lowThreshHyst) {
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.y * blockDim.y;
if ((ix > 0) && (ix < (width - 1)) && (iy > 0) && iy < (height - 1)) {
int tid = iy * width + ix;
d_lowThreshHyst[tid] = d_highThreshHyst[tid];
if (d_highThreshHyst[tid] == 1) {
// Determine neighbour indices
int eastN = tid + 1;
int westN = tid - 1;
int northN = tid - width;
int southN = tid + width;
int southEastN = southN + 1;
int northEastN = northN + 1;
int southWestN = southN - 1;
int northWestN = northN - 1;
if (d_nonMax[eastN] > lowThreshold)
d_lowThreshHyst[eastN] = 1.0f;
if (d_nonMax[westN] > lowThreshold)
d_lowThreshHyst[westN] = 1.0f;
if (d_nonMax[northN] > lowThreshold)
d_lowThreshHyst[northN] = 1.0f;
if (d_nonMax[southN] > lowThreshold)
d_lowThreshHyst[southN] = 1.0f;
if (d_nonMax[southEastN] > lowThreshold)
d_lowThreshHyst[southEastN] = 1.0f;
if (d_nonMax[northEastN] > lowThreshold)
d_lowThreshHyst[northEastN] = 1.0f;
if (d_nonMax[southWestN] > lowThreshold)
d_lowThreshHyst[southWestN] = 1.0f;
if (d_nonMax[northWestN] > lowThreshold)
d_lowThreshHyst[northWestN] = 1.0f;
}
}
} | .text
.file "lowHysterisis.hip"
.globl _Z28__device_stub__lowHysterisisiiPfS_fS_ # -- Begin function _Z28__device_stub__lowHysterisisiiPfS_fS_
.p2align 4, 0x90
.type _Z28__device_stub__lowHysterisisiiPfS_fS_,@function
_Z28__device_stub__lowHysterisisiiPfS_fS_: # @_Z28__device_stub__lowHysterisisiiPfS_fS_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movss %xmm0, 12(%rsp)
movq %r8, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13lowHysterisisiiPfS_fS_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__lowHysterisisiiPfS_fS_, .Lfunc_end0-_Z28__device_stub__lowHysterisisiiPfS_fS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13lowHysterisisiiPfS_fS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13lowHysterisisiiPfS_fS_,@object # @_Z13lowHysterisisiiPfS_fS_
.section .rodata,"a",@progbits
.globl _Z13lowHysterisisiiPfS_fS_
.p2align 3, 0x0
_Z13lowHysterisisiiPfS_fS_:
.quad _Z28__device_stub__lowHysterisisiiPfS_fS_
.size _Z13lowHysterisisiiPfS_fS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13lowHysterisisiiPfS_fS_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__lowHysterisisiiPfS_fS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13lowHysterisisiiPfS_fS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13lowHysterisisiiPfS_fS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe40000000000 */
/*0030*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ UIADD3 UR4, -UR5, UR6, URZ ; /* 0x0000000605047290 */
/* 0x000fc6000fffe13f */
/*0060*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0070*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0090*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe2000bf06270 */
/*00a0*/ UIADD3 UR4, -UR5, UR7, URZ ; /* 0x0000000705047290 */
/* 0x000fe2000fffe13f */
/*00b0*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fe400078e0205 */
/*00c0*/ ISETP.LT.OR P0, PT, R0, 0x1, P0 ; /* 0x000000010000780c */
/* 0x000fc80000701670 */
/*00d0*/ ISETP.LT.OR P0, PT, R3, 0x1, P0 ; /* 0x000000010300780c */
/* 0x000fc80000701670 */
/*00e0*/ ISETP.GE.OR P0, PT, R3, UR4, P0 ; /* 0x0000000403007c0c */
/* 0x000fda0008706670 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0110*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0120*/ IMAD R0, R3, c[0x0][0x160], R0 ; /* 0x0000580003007a24 */
/* 0x000fc800078e0200 */
/*0130*/ IMAD.WIDE R4, R0, R7, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fca00078e0207 */
/*0140*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IMAD.WIDE R2, R0, R7, c[0x0][0x180] ; /* 0x0000600000027625 */
/* 0x000fca00078e0207 */
/*0160*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0041e8000c101904 */
/*0170*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0180*/ FSETP.NEU.AND P0, PT, R6, 1, PT ; /* 0x3f8000000600780b */
/* 0x004fda0003f0d000 */
/*0190*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.WIDE R8, R0, R7, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x001fca00078e0207 */
/*01b0*/ LDG.E R4, [R8.64+0x4] ; /* 0x0000040408047981 */
/* 0x000ea4000c1e1900 */
/*01c0*/ FSETP.GT.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0b */
/* 0x004fda0003f04000 */
/*01d0*/ @P0 IMAD.MOV.U32 R15, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff0f0424 */
/* 0x000fca00078e00ff */
/*01e0*/ @P0 STG.E [R2.64+0x4], R15 ; /* 0x0000040f02000986 */
/* 0x0001e8000c101904 */
/*01f0*/ LDG.E R4, [R8.64+-0x4] ; /* 0xfffffc0408047981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IADD3 R6, R0, -c[0x0][0x160], RZ ; /* 0x8000580000067a10 */
/* 0x000fe40007ffe0ff */
/*0210*/ FSETP.GT.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0b */
/* 0x004fc60003f04000 */
/*0220*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fd400078e0207 */
/*0230*/ @P0 IMAD.MOV.U32 R17, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff110424 */
/* 0x000fca00078e00ff */
/*0240*/ @P0 STG.E [R2.64+-0x4], R17 ; /* 0xfffffc1102000986 */
/* 0x0003e8000c101904 */
/*0250*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea2000c1e1900 */
/*0260*/ SHF.R.S32.HI R11, RZ, 0x1f, R6 ; /* 0x0000001fff0b7819 */
/* 0x000fe40000011406 */
/*0270*/ IADD3 R0, R0, c[0x0][0x160], RZ ; /* 0x0000580000007a10 */
/* 0x000fca0007ffe0ff */
/*0280*/ IMAD.WIDE R8, R0, R7, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x000fe200078e0207 */
/*0290*/ FSETP.GT.AND P0, PT, R10, c[0x0][0x178], PT ; /* 0x00005e000a007a0b */
/* 0x004fda0003f04000 */
/*02a0*/ @P0 LEA R12, P1, R6, c[0x0][0x180], 0x2 ; /* 0x00006000060c0a11 */
/* 0x000fe200078210ff */
/*02b0*/ @P0 IMAD.MOV.U32 R15, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff0f0424 */
/* 0x001fc600078e00ff */
/*02c0*/ @P0 LEA.HI.X R13, R6, c[0x0][0x184], R11, 0x2, P1 ; /* 0x00006100060d0a11 */
/* 0x000fca00008f140b */
/*02d0*/ @P0 STG.E [R12.64], R15 ; /* 0x0000000f0c000986 */
/* 0x000fe8000c101904 */
/*02e0*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x000ea4000c1e1900 */
/*02f0*/ FSETP.GT.AND P0, PT, R10, c[0x0][0x178], PT ; /* 0x00005e000a007a0b */
/* 0x004fda0003f04000 */
/*0300*/ @P0 IMAD.WIDE R2, R7, c[0x0][0x160], R2 ; /* 0x0000580007020a25 */
/* 0x002fe200078e0202 */
/*0310*/ @P0 MOV R17, 0x3f800000 ; /* 0x3f80000000110802 */
/* 0x000fca0000000f00 */
/*0320*/ @P0 STG.E [R2.64], R17 ; /* 0x0000001102000986 */
/* 0x0001e8000c101904 */
/*0330*/ LDG.E R10, [R8.64+0x4] ; /* 0x00000404080a7981 */
/* 0x000ea4000c1e1900 */
/*0340*/ FSETP.GT.AND P0, PT, R10, c[0x0][0x178], PT ; /* 0x00005e000a007a0b */
/* 0x004fe40003f04000 */
/*0350*/ IADD3 R10, R0, -0x1, RZ ; /* 0xffffffff000a7810 */
/* 0x000fca0007ffe0ff */
/*0360*/ IMAD.WIDE R10, R10, R7, c[0x0][0x180] ; /* 0x000060000a0a7625 */
/* 0x000fcc00078e0207 */
/*0370*/ @P0 IMAD.MOV.U32 R19, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff130424 */
/* 0x000fca00078e00ff */
/*0380*/ @P0 STG.E [R10.64+0x8], R19 ; /* 0x000008130a000986 */
/* 0x0003e8000c101904 */
/*0390*/ LDG.E R0, [R4.64+0x4] ; /* 0x0000040404007981 */
/* 0x000ea2000c1e1900 */
/*03a0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fca0007ffe0ff */
/*03b0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x180] ; /* 0x0000600006067625 */
/* 0x000fe200078e0207 */
/*03c0*/ FSETP.GT.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0b */
/* 0x004fda0003f04000 */
/*03d0*/ @P0 IMAD.MOV.U32 R3, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff030424 */
/* 0x001fca00078e00ff */
/*03e0*/ @P0 STG.E [R6.64+0x8], R3 ; /* 0x0000080306000986 */
/* 0x0003e8000c101904 */
/*03f0*/ LDG.E R8, [R8.64+-0x4] ; /* 0xfffffc0408087981 */
/* 0x000ea4000c1e1900 */
/*0400*/ FSETP.GT.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0b */
/* 0x004fda0003f04000 */
/*0410*/ @P0 MOV R13, 0x3f800000 ; /* 0x3f800000000d0802 */
/* 0x000fca0000000f00 */
/*0420*/ @P0 STG.E [R10.64], R13 ; /* 0x0000000d0a000986 */
/* 0x0003e8000c101904 */
/*0430*/ LDG.E R0, [R4.64+-0x4] ; /* 0xfffffc0404007981 */
/* 0x000ea4000c1e1900 */
/*0440*/ FSETP.GT.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0b */
/* 0x004fda0003f04000 */
/*0450*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0460*/ IMAD.MOV.U32 R3, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff037424 */
/* 0x002fca00078e00ff */
/*0470*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x000fe2000c101904 */
/*0480*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0490*/ BRA 0x490; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13lowHysterisisiiPfS_fS_
.globl _Z13lowHysterisisiiPfS_fS_
.p2align 8
.type _Z13lowHysterisisiiPfS_fS_,@function
_Z13lowHysterisisiiPfS_fS_:
s_load_b32 s4, s[0:1], 0x34
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
s_mov_b32 s4, exec_lo
v_cmpx_lt_i32_e32 0, v1
s_cbranch_execz .LBB0_19
s_load_b32 s2, s[2:3], 0xc
s_load_b64 s[6:7], s[0:1], 0x0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_add_i32 s3, s7, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
s_add_i32 s2, s6, -1
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s2, s3, v4
v_cmp_lt_i32_e64 s3, 0, v4
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_19
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x20
v_mad_u64_u32 v[2:3], null, v4, s6, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v5, v[3:4], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v5, off
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_eq_f32_e32 vcc_lo, 1.0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_19
s_load_b64 s[4:5], s[0:1], 0x8
v_add_nc_u32_e32 v0, 1, v2
s_load_b32 s0, s[0:1], 0x18
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[3:4], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 s0, v3
s_cbranch_execz .LBB0_5
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_mov_b32_e32 v3, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v0, -1, v2
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v1, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 s0, v3
s_cbranch_execz .LBB0_7
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_mov_b32_e32 v3, 1.0
global_store_b32 v[0:1], v3, off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s1
v_subrev_nc_u32_e32 v0, s6, v2
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[3:4], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 s0, v3
s_cbranch_execz .LBB0_9
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_mov_b32_e32 v1, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_store_b32 v[3:4], v1, off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v1, s6, v2
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 s0, v4
s_cbranch_execz .LBB0_11
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_mov_b32_e32 v4, 1.0
global_store_b32 v[2:3], v4, off
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v2, 1, v1
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 s0, v4
s_cbranch_execz .LBB0_13
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_mov_b32_e32 v4, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[2:3], v4, off
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v2, 1, v0
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 s0, v4
s_cbranch_execz .LBB0_15
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_mov_b32_e32 v4, 1.0
global_store_b32 v[2:3], v4, off
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v1, -1, v1
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 s0, v3
s_cbranch_execz .LBB0_17
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_mov_b32_e32 v3, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_store_b32 v[1:2], v3, off
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v0, -1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_lt_f32_e32 vcc_lo, s0, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_19
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_mov_b32_e32 v2, 1.0
global_store_b32 v[0:1], v2, off
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13lowHysterisisiiPfS_fS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13lowHysterisisiiPfS_fS_, .Lfunc_end0-_Z13lowHysterisisiiPfS_fS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13lowHysterisisiiPfS_fS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13lowHysterisisiiPfS_fS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001442a4_00000000-6_lowHysterisis.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z13lowHysterisisiiPfS_fS_iiPfS_fS_
.type _Z40__device_stub__Z13lowHysterisisiiPfS_fS_iiPfS_fS_, @function
_Z40__device_stub__Z13lowHysterisisiiPfS_fS_iiPfS_fS_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13lowHysterisisiiPfS_fS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z13lowHysterisisiiPfS_fS_iiPfS_fS_, .-_Z40__device_stub__Z13lowHysterisisiiPfS_fS_iiPfS_fS_
.globl _Z13lowHysterisisiiPfS_fS_
.type _Z13lowHysterisisiiPfS_fS_, @function
_Z13lowHysterisisiiPfS_fS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13lowHysterisisiiPfS_fS_iiPfS_fS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13lowHysterisisiiPfS_fS_, .-_Z13lowHysterisisiiPfS_fS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13lowHysterisisiiPfS_fS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13lowHysterisisiiPfS_fS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lowHysterisis.hip"
.globl _Z28__device_stub__lowHysterisisiiPfS_fS_ # -- Begin function _Z28__device_stub__lowHysterisisiiPfS_fS_
.p2align 4, 0x90
.type _Z28__device_stub__lowHysterisisiiPfS_fS_,@function
_Z28__device_stub__lowHysterisisiiPfS_fS_: # @_Z28__device_stub__lowHysterisisiiPfS_fS_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movss %xmm0, 12(%rsp)
movq %r8, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13lowHysterisisiiPfS_fS_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__lowHysterisisiiPfS_fS_, .Lfunc_end0-_Z28__device_stub__lowHysterisisiiPfS_fS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13lowHysterisisiiPfS_fS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13lowHysterisisiiPfS_fS_,@object # @_Z13lowHysterisisiiPfS_fS_
.section .rodata,"a",@progbits
.globl _Z13lowHysterisisiiPfS_fS_
.p2align 3, 0x0
_Z13lowHysterisisiiPfS_fS_:
.quad _Z28__device_stub__lowHysterisisiiPfS_fS_
.size _Z13lowHysterisisiiPfS_fS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13lowHysterisisiiPfS_fS_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__lowHysterisisiiPfS_fS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13lowHysterisisiiPfS_fS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<bits/stdc++.h>
using namespace std;
#define MAX_VAL 100000000
__global__ void compute(int *d_r, int *d_u, int *d_v, int *depth, int *max_depth, int nodes, int edges){
int idx = threadIdx.x;
int i;
__shared__ int done;
__shared__ int curr_depth;
for(i=idx; i<nodes; i+=1024){
depth[i] = MAX_VAL;
}
if(idx==0){
depth[0] = 0;
curr_depth = 0;
done=0;
}
__syncthreads();
while(!done){
if(idx == 0){
done = 1;
}
__syncthreads();
for(i=idx; i<nodes; i+=1024){
if(depth[i] == curr_depth){
done = 0;
for(int j = d_r[i]; j<d_r[i+1]; j++){
int to = d_v[j];
if(depth[to] > curr_depth + 1){
depth[to] = curr_depth + 1;
}
}
}
}
if(idx==0 && done==0){
curr_depth++;
}
__syncthreads();
}
if(idx == 0)
*max_depth = curr_depth-1;
}
int main(int argc, char *argv[]){
if(argc<2){
cout << "Usage: " << argv[0] << " <graph_file_name>\n";
return 0;
}
ifstream input;
input.open(argv[1]);
int nodes, edges, i, j;
input >> nodes;
input >> edges;
// allocating host memory
int *h_r = (int*)malloc((nodes+1)*sizeof(int));
int *h_u = (int*)malloc(edges*2*sizeof(int));
int *h_v = (int*)malloc(edges*2*sizeof(int));
// reading the inputs
for(i=0; i<nodes+1; i++){
input >> h_r[i];
}
for(i=0; i<nodes+1; i++){
for(j=h_r[i]; j<h_r[i+1]; j++){
h_u[j] = i;
}
}
for(i=0; i<edges*2; i++){
input >> h_v[i];
}
// allocating device memory
int *d_r, *d_u, *d_v, *d_depth, *max_depth;
cudaMalloc((void**)&d_r, (nodes+1)*sizeof(int));
cudaMalloc((void**)&d_u, edges*2*sizeof(int));
cudaMalloc((void**)&d_v, edges*2*sizeof(int));
cudaMalloc((void**)&d_depth, nodes*sizeof(int));
cudaMalloc((void**)&max_depth, sizeof(int));
// copying data to device
cudaMemcpy(d_r, h_r, (nodes+1)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_u, h_u, edges*2*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_v, h_v, edges*2*sizeof(int), cudaMemcpyHostToDevice);
// timer
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
// kernel call
printf("Starting Computation\n");
compute<<< 1,1024 >>> (d_r, d_u, d_v, d_depth, max_depth, nodes, edges);
printf("Finished computation\n");
// timer
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
cout<<"Compute time in GPU: "<<milliseconds<<"ms"<<endl;
// copying the results to host
int *result = (int *)malloc(sizeof(int));
cudaMemcpy(result, max_depth, sizeof(int), cudaMemcpyDeviceToHost);
printf("Depth : %d\n", result[0]);
// solution check
int *h_depth = (int*) malloc(nodes*sizeof(int));
cudaMemcpy(h_depth, d_depth, nodes*sizeof(int), cudaMemcpyDeviceToHost);
int *h_check_depth = (int*)malloc(nodes*sizeof(int));
freopen(argv[2], "r", stdin);
for(int i = 0; i < nodes; i++) {
cin>>h_check_depth[i];
}
bool flag = true;
int count = 0;
for(int i = 0; i < nodes; i++) {
if(h_depth[i] != h_check_depth[i]) {
printf("Found %d, Expected %d\n",h_depth[i], h_check_depth[i]);
flag = false;
count++;
}
}
if(flag) {
cout<<"Solution is correct!\n";
}
else {
cout<<"Solution is incorrect!"<<endl;
cout<<count<<" testcases failed.\n";
}
} | code for sm_80
Function : _Z7computePiS_S_S_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x5b0 ; /* 0x0000057000007945 */
/* 0x000fe20003800000 */
/*0040*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x188], PT ; /* 0x0000620000007a0c */
/* 0x001fda0003f26270 */
/*0050*/ @P1 BRA 0x5a0 ; /* 0x0000054000001947 */
/* 0x000fea0003800000 */
/*0060*/ LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff027212 */
/* 0x000fe200078e33ff */
/*0070*/ BSSY B1, 0x180 ; /* 0x0000010000017945 */
/* 0x000fe60003800000 */
/*0080*/ IADD3 R2, R2, c[0x0][0x188], RZ ; /* 0x0000620002027a10 */
/* 0x000fc80007ffe0ff */
/*0090*/ LEA.HI R3, R2.reuse, 0x1, RZ, 0x16 ; /* 0x0000000102037811 */
/* 0x040fe400078fb0ff */
/*00a0*/ ISETP.GE.U32.AND P2, PT, R2, 0xc00, PT ; /* 0x00000c000200780c */
/* 0x000fe20003f46070 */
/*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0000 */
/*00c0*/ LOP3.LUT P0, R3, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303037812 */
/* 0x000fda000780c0ff */
/*00d0*/ @!P0 BRA 0x170 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R9, RZ, RZ, 0x5f5e100 ; /* 0x05f5e100ff097424 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD.WIDE R4, R2.reuse, R7, c[0x0][0x178] ; /* 0x00005e0002047625 */
/* 0x040fe200078e0207 */
/*0120*/ IADD3 R3, R3, -0x1, RZ ; /* 0xffffffff03037810 */
/* 0x000fe40007ffe0ff */
/*0130*/ IADD3 R2, R2, 0x400, RZ ; /* 0x0000040002027810 */
/* 0x000fe40007ffe0ff */
/*0140*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e2000c101904 */
/*0150*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0160*/ @P0 BRA 0x110 ; /* 0xffffffa000000947 */
/* 0x001fea000383ffff */
/*0170*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0180*/ @!P2 BRA 0x5a0 ; /* 0x000004100000a947 */
/* 0x000fea0003800000 */
/*0190*/ IADD3 R3, -R2, c[0x0][0x188], RZ ; /* 0x0000620002037a10 */
/* 0x000fe20007ffe1ff */
/*01a0*/ BSSY B1, 0x3e0 ; /* 0x0000023000017945 */
/* 0x000fe20003800000 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*01c0*/ ISETP.GT.AND P2, PT, R3, 0x3000, PT ; /* 0x000030000300780c */
/* 0x000fda0003f44270 */
/*01d0*/ @!P2 BRA 0x3d0 ; /* 0x000001f00000a947 */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff037624 */
/* 0x000fe200078e00ff */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0200*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe400078e00ff */
/*0210*/ IMAD.MOV.U32 R15, RZ, RZ, 0x5f5e100 ; /* 0x05f5e100ff0f7424 */
/* 0x000fe200078e00ff */
/*0220*/ IADD3 R3, R3, -0x3000, RZ ; /* 0xffffd00003037810 */
/* 0x000fe40007ffe0ff */
/*0230*/ IADD3 R4, R2.reuse, 0x1000, RZ ; /* 0x0000100002047810 */
/* 0x041fe20007ffe0ff */
/*0240*/ IMAD.WIDE R10, R2.reuse, R13.reuse, c[0x0][0x178] ; /* 0x00005e00020a7625 */
/* 0x0c0fe200078e020d */
/*0250*/ IADD3 R6, R2.reuse, 0x2000, RZ ; /* 0x0000200002067810 */
/* 0x040fe40007ffe0ff */
/*0260*/ IADD3 R8, R2, 0x3000, RZ ; /* 0x0000300002087810 */
/* 0x000fe20007ffe0ff */
/*0270*/ IMAD.WIDE R4, R4, R13, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fe200078e020d */
/*0280*/ STG.E [R10.64], R15 ; /* 0x0000000f0a007986 */
/* 0x0001e2000c101904 */
/*0290*/ IADD3 R2, R2, 0x4000, RZ ; /* 0x0000400002027810 */
/* 0x000fc40007ffe0ff */
/*02a0*/ IMAD.WIDE R6, R6, R13, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fe200078e020d */
/*02b0*/ STG.E [R10.64+0x1000], R15 ; /* 0x0010000f0a007986 */
/* 0x0001e2000c101904 */
/*02c0*/ ISETP.GE.AND P2, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fe40003f46270 */
/*02d0*/ IMAD.WIDE R8, R8, R13, c[0x0][0x178] ; /* 0x00005e0008087625 */
/* 0x000fe200078e020d */
/*02e0*/ STG.E [R10.64+0x2000], R15 ; /* 0x0020000f0a007986 */
/* 0x0001e8000c101904 */
/*02f0*/ STG.E [R10.64+0x3000], R15 ; /* 0x0030000f0a007986 */
/* 0x0001e8000c101904 */
/*0300*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x0001e8000c101904 */
/*0310*/ STG.E [R4.64+0x1000], R15 ; /* 0x0010000f04007986 */
/* 0x0001e8000c101904 */
/*0320*/ STG.E [R4.64+0x2000], R15 ; /* 0x0020000f04007986 */
/* 0x0001e8000c101904 */
/*0330*/ STG.E [R4.64+0x3000], R15 ; /* 0x0030000f04007986 */
/* 0x0001e8000c101904 */
/*0340*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0001e8000c101904 */
/*0350*/ STG.E [R6.64+0x1000], R15 ; /* 0x0010000f06007986 */
/* 0x0001e8000c101904 */
/*0360*/ STG.E [R6.64+0x2000], R15 ; /* 0x0020000f06007986 */
/* 0x0001e8000c101904 */
/*0370*/ STG.E [R6.64+0x3000], R15 ; /* 0x0030000f06007986 */
/* 0x0001e8000c101904 */
/*0380*/ STG.E [R8.64], R15 ; /* 0x0000000f08007986 */
/* 0x0001e8000c101904 */
/*0390*/ STG.E [R8.64+0x1000], R15 ; /* 0x0010000f08007986 */
/* 0x0001e8000c101904 */
/*03a0*/ STG.E [R8.64+0x2000], R15 ; /* 0x0020000f08007986 */
/* 0x0001e8000c101904 */
/*03b0*/ STG.E [R8.64+0x3000], R15 ; /* 0x0030000f08007986 */
/* 0x0001e2000c101904 */
/*03c0*/ @!P2 BRA 0x230 ; /* 0xfffffe600000a947 */
/* 0x000fea000383ffff */
/*03d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*03e0*/ IADD3 R3, -R2, c[0x0][0x188], RZ ; /* 0x0000620002037a10 */
/* 0x000fe20007ffe1ff */
/*03f0*/ BSSY B1, 0x520 ; /* 0x0000012000017945 */
/* 0x000fe60003800000 */
/*0400*/ ISETP.GT.AND P2, PT, R3, 0x1000, PT ; /* 0x000010000300780c */
/* 0x000fda0003f44270 */
/*0410*/ @!P2 BRA 0x510 ; /* 0x000000f00000a947 */
/* 0x000fea0003800000 */
/*0420*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x001fe200078e00ff */
/*0430*/ IADD3 R6, R2.reuse, 0x1000, RZ ; /* 0x0000100002067810 */
/* 0x040fe20007ffe0ff */
/*0440*/ IMAD.MOV.U32 R3, RZ, RZ, 0x5f5e100 ; /* 0x05f5e100ff037424 */
/* 0x000fe200078e00ff */
/*0450*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0460*/ IMAD.WIDE R4, R2.reuse, R7, c[0x0][0x178] ; /* 0x00005e0002047625 */
/* 0x040fe200078e0207 */
/*0470*/ IADD3 R2, R2, 0x2000, RZ ; /* 0x0000200002027810 */
/* 0x000fc60007ffe0ff */
/*0480*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fe200078e0207 */
/*0490*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0001e8000c101904 */
/*04a0*/ STG.E [R4.64+0x1000], R3 ; /* 0x0010000304007986 */
/* 0x0001e8000c101904 */
/*04b0*/ STG.E [R4.64+0x2000], R3 ; /* 0x0020000304007986 */
/* 0x0001e8000c101904 */
/*04c0*/ STG.E [R4.64+0x3000], R3 ; /* 0x0030000304007986 */
/* 0x0001e8000c101904 */
/*04d0*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x0001e8000c101904 */
/*04e0*/ STG.E [R6.64+0x1000], R3 ; /* 0x0010000306007986 */
/* 0x0001e8000c101904 */
/*04f0*/ STG.E [R6.64+0x2000], R3 ; /* 0x0020000306007986 */
/* 0x0001e8000c101904 */
/*0500*/ STG.E [R6.64+0x3000], R3 ; /* 0x0030000306007986 */
/* 0x0001e4000c101904 */
/*0510*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0520*/ ISETP.LT.OR P0, PT, R2, c[0x0][0x188], P0 ; /* 0x0000620002007a0c */
/* 0x000fda0000701670 */
/*0530*/ @P0 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff030424 */
/* 0x001fe400078e00ff */
/*0540*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, 0x5f5e100 ; /* 0x05f5e100ff050424 */
/* 0x000fe400078e00ff */
/*0550*/ @P0 IMAD.WIDE R2, R2, R3, c[0x0][0x178] ; /* 0x00005e0002020625 */
/* 0x000fca00078e0203 */
/*0560*/ @P0 STG.E [R2.64], R5 ; /* 0x0000000502000986 */
/* 0x0001e8000c101904 */
/*0570*/ @P0 STG.E [R2.64+0x1000], R5 ; /* 0x0010000502000986 */
/* 0x0001e8000c101904 */
/*0580*/ @P0 STG.E [R2.64+0x2000], R5 ; /* 0x0020000502000986 */
/* 0x0001e8000c101904 */
/*0590*/ @P0 STG.E [R2.64+0x3000], R5 ; /* 0x0030000502000986 */
/* 0x0001e4000c101904 */
/*05a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05b0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*05c0*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff028624 */
/* 0x001fe200078e00ff */
/*05d0*/ @!P0 STS.64 [RZ], RZ ; /* 0x000000ffff008388 */
/* 0x000fe20000000a00 */
/*05e0*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff038624 */
/* 0x000fca00078e00ff */
/*05f0*/ @!P0 STG.E [R2.64], RZ ; /* 0x000000ff02008986 */
/* 0x000fe8000c101904 */
/*0600*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0610*/ LDS R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x000e240000000800 */
/*0620*/ ISETP.NE.AND P2, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x001fda0003f45270 */
/*0630*/ @P2 BRA 0x9b0 ; /* 0x0000037000002947 */
/* 0x000fea0003800000 */
/*0640*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff028424 */
/* 0x000fe200078e00ff */
/*0650*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0660*/ BSSY B0, 0x930 ; /* 0x000002c000007945 */
/* 0x000fe60003800000 */
/*0670*/ @!P0 STS [RZ], R2 ; /* 0x00000002ff008388 */
/* 0x0001e80000000800 */
/*0680*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0690*/ @P1 BRA 0x920 ; /* 0x0000028000001947 */
/* 0x000fea0003800000 */
/*06a0*/ LDS R8, [0x4] ; /* 0x00000400ff087984 */
/* 0x001e220000000800 */
/*06b0*/ IMAD.MOV.U32 R10, RZ, RZ, R0 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0000 */
/*06c0*/ IADD3 R9, R8, 0x1, RZ ; /* 0x0000000108097810 */
/* 0x001fc40007ffe0ff */
/*06d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*06e0*/ IMAD.WIDE R2, R10, R5, c[0x0][0x178] ; /* 0x00005e000a027625 */
/* 0x001fcc00078e0205 */
/*06f0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0700*/ BSSY B1, 0x8f0 ; /* 0x000001e000017945 */
/* 0x000fe20003800000 */
/*0710*/ ISETP.NE.AND P2, PT, R3, R8, PT ; /* 0x000000080300720c */
/* 0x004fda0003f45270 */
/*0720*/ @P2 BRA 0x8e0 ; /* 0x000001b000002947 */
/* 0x000fea0003800000 */
/*0730*/ SHF.R.S32.HI R3, RZ, 0x1f, R10 ; /* 0x0000001fff037819 */
/* 0x000fe4000001140a */
/*0740*/ LEA R2, P2, R10, c[0x0][0x160], 0x2 ; /* 0x000058000a027a11 */
/* 0x000fc800078410ff */
/*0750*/ LEA.HI.X R3, R10, c[0x0][0x164], R3, 0x2, P2 ; /* 0x000059000a037a11 */
/* 0x000fca00010f1403 */
/*0760*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R7, [R2.64+0x4] ; /* 0x0000040402077981 */
/* 0x000ea8000c1e1900 */
/*0780*/ STS [RZ], RZ ; /* 0x000000ffff007388 */
/* 0x000fe20000000800 */
/*0790*/ ISETP.GE.AND P2, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x004fda0003f46270 */
/*07a0*/ @P2 BRA 0x8e0 ; /* 0x0000013000002947 */
/* 0x000fea0003800000 */
/*07b0*/ IMAD.MOV.U32 R11, RZ, RZ, R4 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0004 */
/*07c0*/ IMAD.MOV.U32 R12, RZ, RZ, R7 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0007 */
/*07d0*/ IMAD.WIDE R4, R11, R5, c[0x0][0x170] ; /* 0x00005c000b047625 */
/* 0x000fca00078e0205 */
/*07e0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x001ea2000c1e1900 */
/*07f0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*0800*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x004fca00078e0207 */
/*0810*/ LDG.E R14, [R6.64] ; /* 0x00000004060e7981 */
/* 0x000ea2000c1e1900 */
/*0820*/ BSSY B2, 0x8b0 ; /* 0x0000008000027945 */
/* 0x000fe20003800000 */
/*0830*/ IADD3 R4, P2, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fe40007f5e0ff */
/*0840*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fe40007ffe0ff */
/*0850*/ ISETP.GT.AND P3, PT, R14, R9, PT ; /* 0x000000090e00720c */
/* 0x004fda0003f64270 */
/*0860*/ @!P3 BRA 0x8a0 ; /* 0x000000300000b947 */
/* 0x000fea0003800000 */
/*0870*/ IADD3 R9, R8, 0x1, RZ ; /* 0x0000000108097810 */
/* 0x000fca0007ffe0ff */
/*0880*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e8000c101904 */
/*0890*/ LDG.E R12, [R2.64+0x4] ; /* 0x00000404020c7981 */
/* 0x000164000c1e1900 */
/*08a0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*08b0*/ ISETP.GE.AND P3, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x020fe20003f66270 */
/*08c0*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fd800010e0605 */
/*08d0*/ @!P3 BRA 0x7e0 ; /* 0xffffff000000b947 */
/* 0x000fea000383ffff */
/*08e0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08f0*/ IADD3 R10, R10, 0x400, RZ ; /* 0x000004000a0a7810 */
/* 0x000fc80007ffe0ff */
/*0900*/ ISETP.GE.AND P2, PT, R10, c[0x0][0x188], PT ; /* 0x000062000a007a0c */
/* 0x000fda0003f46270 */
/*0910*/ @!P2 BRA 0x6d0 ; /* 0xfffffdb00000a947 */
/* 0x000fea000383ffff */
/*0920*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0930*/ LDS.64 R2, [RZ] ; /* 0x00000000ff027984 */
/* 0x000e240000000a00 */
/*0940*/ LOP3.LUT P2, RZ, R2, R0, RZ, 0xfc, !PT ; /* 0x0000000002ff7212 */
/* 0x001fda000784fcff */
/*0950*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fca0007ffe0ff */
/*0960*/ @!P2 STS [0x4], R3 ; /* 0x00000403ff00a388 */
/* 0x000fe80000000800 */
/*0970*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0980*/ LDS R2, [RZ] ; /* 0x00000000ff027984 */
/* 0x000e240000000800 */
/*0990*/ ISETP.NE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x001fda0003f45270 */
/*09a0*/ @!P2 BRA 0x640 ; /* 0xfffffc900000a947 */
/* 0x000fea000383ffff */
/*09b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*09c0*/ LDS R5, [0x4] ; /* 0x00000400ff057984 */
/* 0x000e220000000800 */
/*09d0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff027624 */
/* 0x000fe400078e00ff */
/*09e0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff037624 */
/* 0x000fe200078e00ff */
/*09f0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x001fca0007ffe0ff */
/*0a00*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0a10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a20*/ BRA 0xa20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<bits/stdc++.h>
using namespace std;
#define MAX_VAL 100000000
__global__ void compute(int *d_r, int *d_u, int *d_v, int *depth, int *max_depth, int nodes, int edges){
int idx = threadIdx.x;
int i;
__shared__ int done;
__shared__ int curr_depth;
for(i=idx; i<nodes; i+=1024){
depth[i] = MAX_VAL;
}
if(idx==0){
depth[0] = 0;
curr_depth = 0;
done=0;
}
__syncthreads();
while(!done){
if(idx == 0){
done = 1;
}
__syncthreads();
for(i=idx; i<nodes; i+=1024){
if(depth[i] == curr_depth){
done = 0;
for(int j = d_r[i]; j<d_r[i+1]; j++){
int to = d_v[j];
if(depth[to] > curr_depth + 1){
depth[to] = curr_depth + 1;
}
}
}
}
if(idx==0 && done==0){
curr_depth++;
}
__syncthreads();
}
if(idx == 0)
*max_depth = curr_depth-1;
}
int main(int argc, char *argv[]){
if(argc<2){
cout << "Usage: " << argv[0] << " <graph_file_name>\n";
return 0;
}
ifstream input;
input.open(argv[1]);
int nodes, edges, i, j;
input >> nodes;
input >> edges;
// allocating host memory
int *h_r = (int*)malloc((nodes+1)*sizeof(int));
int *h_u = (int*)malloc(edges*2*sizeof(int));
int *h_v = (int*)malloc(edges*2*sizeof(int));
// reading the inputs
for(i=0; i<nodes+1; i++){
input >> h_r[i];
}
for(i=0; i<nodes+1; i++){
for(j=h_r[i]; j<h_r[i+1]; j++){
h_u[j] = i;
}
}
for(i=0; i<edges*2; i++){
input >> h_v[i];
}
// allocating device memory
int *d_r, *d_u, *d_v, *d_depth, *max_depth;
cudaMalloc((void**)&d_r, (nodes+1)*sizeof(int));
cudaMalloc((void**)&d_u, edges*2*sizeof(int));
cudaMalloc((void**)&d_v, edges*2*sizeof(int));
cudaMalloc((void**)&d_depth, nodes*sizeof(int));
cudaMalloc((void**)&max_depth, sizeof(int));
// copying data to device
cudaMemcpy(d_r, h_r, (nodes+1)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_u, h_u, edges*2*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_v, h_v, edges*2*sizeof(int), cudaMemcpyHostToDevice);
// timer
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
// kernel call
printf("Starting Computation\n");
compute<<< 1,1024 >>> (d_r, d_u, d_v, d_depth, max_depth, nodes, edges);
printf("Finished computation\n");
// timer
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
cout<<"Compute time in GPU: "<<milliseconds<<"ms"<<endl;
// copying the results to host
int *result = (int *)malloc(sizeof(int));
cudaMemcpy(result, max_depth, sizeof(int), cudaMemcpyDeviceToHost);
printf("Depth : %d\n", result[0]);
// solution check
int *h_depth = (int*) malloc(nodes*sizeof(int));
cudaMemcpy(h_depth, d_depth, nodes*sizeof(int), cudaMemcpyDeviceToHost);
int *h_check_depth = (int*)malloc(nodes*sizeof(int));
freopen(argv[2], "r", stdin);
for(int i = 0; i < nodes; i++) {
cin>>h_check_depth[i];
}
bool flag = true;
int count = 0;
for(int i = 0; i < nodes; i++) {
if(h_depth[i] != h_check_depth[i]) {
printf("Found %d, Expected %d\n",h_depth[i], h_check_depth[i]);
flag = false;
count++;
}
}
if(flag) {
cout<<"Solution is correct!\n";
}
else {
cout<<"Solution is incorrect!"<<endl;
cout<<count<<" testcases failed.\n";
}
} | .file "tmpxft_00059193_00000000-6_parallel_BFS_edge_parallel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB10862:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10862:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z7computePiS_S_S_S_iiPiS_S_S_S_ii
.type _Z36__device_stub__Z7computePiS_S_S_S_iiPiS_S_S_S_ii, @function
_Z36__device_stub__Z7computePiS_S_S_S_iiPiS_S_S_S_ii:
.LFB10884:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7computePiS_S_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10884:
.size _Z36__device_stub__Z7computePiS_S_S_S_iiPiS_S_S_S_ii, .-_Z36__device_stub__Z7computePiS_S_S_S_iiPiS_S_S_S_ii
.globl _Z7computePiS_S_S_S_ii
.type _Z7computePiS_S_S_S_ii, @function
_Z7computePiS_S_S_S_ii:
.LFB10885:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z36__device_stub__Z7computePiS_S_S_S_iiPiS_S_S_S_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10885:
.size _Z7computePiS_S_S_S_ii, .-_Z7computePiS_S_S_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7computePiS_S_S_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB10887:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computePiS_S_S_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10887:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC1:
.string "Usage: "
.LC2:
.string " <graph_file_name>\n"
.LC3:
.string "Starting Computation\n"
.LC4:
.string "Finished computation\n"
.LC6:
.string "Compute time in GPU: "
.LC7:
.string "ms"
.LC8:
.string "Depth : %d\n"
.LC9:
.string "r"
.LC10:
.string "Found %d, Expected %d\n"
.LC11:
.string "Solution is correct!\n"
.LC12:
.string "Solution is incorrect!"
.LC13:
.string " testcases failed.\n"
.text
.globl main
.type main, @function
main:
.LFB10859:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA10859
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $648, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rsi, %r14
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
cmpl $1, %edi
jle .L43
leaq -576(%rbp), %rbx
movq %rbx, %rdi
.LEHB0:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE0:
movq 8(%r14), %rsi
movl $8, %edx
movq %rbx, %rdi
.LEHB1:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
.LEHE1:
jmp .L44
.L43:
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB2:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%r14), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.LEHE2:
jmp .L15
.L44:
leaq -664(%rbp), %rsi
movq %rbx, %rdi
.LEHB3:
call _ZNSirsERi@PLT
leaq -660(%rbp), %rsi
movq %rbx, %rdi
call _ZNSirsERi@PLT
movl -664(%rbp), %r15d
leal 1(%r15), %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r12
movl -660(%rbp), %eax
leal (%rax,%rax), %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, -688(%rbp)
testl %r15d, %r15d
js .L16
movq %r12, -680(%rbp)
movl $0, %ebx
leaq -576(%rbp), %r15
jmp .L17
.L46:
addl $1, %ebx
movl -664(%rbp), %eax
addq $4, -680(%rbp)
cmpl %ebx, %eax
jl .L45
.L17:
movq -680(%rbp), %rsi
movq %r15, %rdi
call _ZNSirsERi@PLT
jmp .L46
.L45:
testl %eax, %eax
js .L16
leal 1(%rax), %r9d
movl $0, %esi
.L20:
movl %esi, %edx
movl (%r12,%rsi,4), %edi
movl 4(%r12,%rsi,4), %ecx
cmpl %ecx, %edi
jge .L18
movslq %edi, %r8
leaq 0(%r13,%r8,4), %rax
subl %edi, %ecx
addq %r8, %rcx
leaq 0(%r13,%rcx,4), %rcx
.L19:
movl %edx, (%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L19
.L18:
addq $1, %rsi
cmpq %r9, %rsi
jne .L20
.L16:
cmpl $0, -660(%rbp)
jle .L21
movq -688(%rbp), %rax
movq %rax, -680(%rbp)
movl $0, %ebx
leaq -576(%rbp), %r15
jmp .L22
.L47:
addl $1, %ebx
addq $4, -680(%rbp)
movl -660(%rbp), %eax
addl %eax, %eax
cmpl %ebx, %eax
jle .L21
.L22:
movq -680(%rbp), %rsi
movq %r15, %rdi
call _ZNSirsERi@PLT
jmp .L47
.L21:
movl -664(%rbp), %eax
leal 1(%rax), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq -656(%rbp), %rdi
call cudaMalloc@PLT
movl -660(%rbp), %eax
leal (%rax,%rax), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq -648(%rbp), %rdi
call cudaMalloc@PLT
movl -660(%rbp), %eax
leal (%rax,%rax), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq -640(%rbp), %rdi
call cudaMalloc@PLT
movslq -664(%rbp), %rsi
salq $2, %rsi
leaq -632(%rbp), %rdi
call cudaMalloc@PLT
leaq -624(%rbp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl -664(%rbp), %eax
leal 1(%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r12, %rsi
movq -656(%rbp), %rdi
call cudaMemcpy@PLT
movl -660(%rbp), %eax
leal (%rax,%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r13, %rsi
movq -648(%rbp), %rdi
call cudaMemcpy@PLT
movl -660(%rbp), %eax
leal (%rax,%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq -688(%rbp), %rsi
movq -640(%rbp), %rdi
call cudaMemcpy@PLT
leaq -616(%rbp), %rdi
call cudaEventCreate@PLT
leaq -608(%rbp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq -616(%rbp), %rdi
call cudaEventRecord@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1024, -588(%rbp)
movl $1, -584(%rbp)
movl $1, -580(%rbp)
movl $1, -600(%rbp)
movl $1, -596(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -588(%rbp), %rdx
movl $1, %ecx
movq -600(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L23
subq $8, %rsp
movl -660(%rbp), %eax
pushq %rax
movl -664(%rbp), %r9d
movq -624(%rbp), %r8
movq -632(%rbp), %rcx
movq -640(%rbp), %rdx
movq -648(%rbp), %rsi
movq -656(%rbp), %rdi
.cfi_escape 0x2e,0x10
call _Z36__device_stub__Z7computePiS_S_S_S_iiPiS_S_S_S_ii
addq $16, %rsp
.L23:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
.cfi_escape 0x2e,0
call __printf_chk@PLT
movl $0, %esi
movq -608(%rbp), %rdi
call cudaEventRecord@PLT
movq -608(%rbp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, -588(%rbp)
leaq -588(%rbp), %rdi
movq -608(%rbp), %rdx
movq -616(%rbp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd -588(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC7(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movl $4, %edx
movq -624(%rbp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movl (%rbx), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq -664(%rbp), %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movl $2, %ecx
movq %rbx, %rdx
movq -632(%rbp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movslq -664(%rbp), %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r13
movq 16(%r14), %rdi
movq stdin(%rip), %rdx
leaq .LC9(%rip), %rsi
call freopen@PLT
cmpl $0, -664(%rbp)
jle .L32
movq %r13, %rdi
movl $0, %ebx
leaq _ZSt3cin(%rip), %r14
jmp .L25
.L49:
addl $1, %ebx
movl -664(%rbp), %eax
movq %r15, %rsi
addq $4, %rsi
movq %rsi, %rdi
cmpl %ebx, %eax
jle .L48
.L25:
movq %rdi, %r15
movq %rdi, %rsi
movq %r14, %rdi
call _ZNSirsERi@PLT
jmp .L49
.L48:
testl %eax, %eax
jle .L32
movl $0, %ebx
movl $0, %r15d
movl $1, %eax
leaq .LC10(%rip), %r14
jmp .L27
.L51:
movl %r15d, %eax
addl $1, %eax
movl %eax, %r15d
movl $0, %eax
.L26:
addq $1, %rbx
cmpl %ebx, -664(%rbp)
jle .L50
.L27:
movl (%r12,%rbx,4), %edx
movl 0(%r13,%rbx,4), %ecx
cmpl %ecx, %edx
je .L26
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L51
.L50:
testb %al, %al
jne .L32
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L52
.L32:
leaq .LC11(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L29
.L52:
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl %r15d, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.LEHE3:
.L29:
leaq -576(%rbp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
.L15:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L53
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L34:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq -576(%rbp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L31
call __stack_chk_fail@PLT
.L31:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10859:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA10859:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE10859-.LLSDACSB10859
.LLSDACSB10859:
.uleb128 .LEHB0-.LFB10859
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB10859
.uleb128 .LEHE1-.LEHB1
.uleb128 .L34-.LFB10859
.uleb128 0
.uleb128 .LEHB2-.LFB10859
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB10859
.uleb128 .LEHE3-.LEHB3
.uleb128 .L34-.LFB10859
.uleb128 0
.uleb128 .LEHB4-.LFB10859
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE10859:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<bits/stdc++.h>
using namespace std;
#define MAX_VAL 100000000
__global__ void compute(int *d_r, int *d_u, int *d_v, int *depth, int *max_depth, int nodes, int edges){
int idx = threadIdx.x;
int i;
__shared__ int done;
__shared__ int curr_depth;
for(i=idx; i<nodes; i+=1024){
depth[i] = MAX_VAL;
}
if(idx==0){
depth[0] = 0;
curr_depth = 0;
done=0;
}
__syncthreads();
while(!done){
if(idx == 0){
done = 1;
}
__syncthreads();
for(i=idx; i<nodes; i+=1024){
if(depth[i] == curr_depth){
done = 0;
for(int j = d_r[i]; j<d_r[i+1]; j++){
int to = d_v[j];
if(depth[to] > curr_depth + 1){
depth[to] = curr_depth + 1;
}
}
}
}
if(idx==0 && done==0){
curr_depth++;
}
__syncthreads();
}
if(idx == 0)
*max_depth = curr_depth-1;
}
int main(int argc, char *argv[]){
if(argc<2){
cout << "Usage: " << argv[0] << " <graph_file_name>\n";
return 0;
}
ifstream input;
input.open(argv[1]);
int nodes, edges, i, j;
input >> nodes;
input >> edges;
// allocating host memory
int *h_r = (int*)malloc((nodes+1)*sizeof(int));
int *h_u = (int*)malloc(edges*2*sizeof(int));
int *h_v = (int*)malloc(edges*2*sizeof(int));
// reading the inputs
for(i=0; i<nodes+1; i++){
input >> h_r[i];
}
for(i=0; i<nodes+1; i++){
for(j=h_r[i]; j<h_r[i+1]; j++){
h_u[j] = i;
}
}
for(i=0; i<edges*2; i++){
input >> h_v[i];
}
// allocating device memory
int *d_r, *d_u, *d_v, *d_depth, *max_depth;
cudaMalloc((void**)&d_r, (nodes+1)*sizeof(int));
cudaMalloc((void**)&d_u, edges*2*sizeof(int));
cudaMalloc((void**)&d_v, edges*2*sizeof(int));
cudaMalloc((void**)&d_depth, nodes*sizeof(int));
cudaMalloc((void**)&max_depth, sizeof(int));
// copying data to device
cudaMemcpy(d_r, h_r, (nodes+1)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_u, h_u, edges*2*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_v, h_v, edges*2*sizeof(int), cudaMemcpyHostToDevice);
// timer
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
// kernel call
printf("Starting Computation\n");
compute<<< 1,1024 >>> (d_r, d_u, d_v, d_depth, max_depth, nodes, edges);
printf("Finished computation\n");
// timer
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
cout<<"Compute time in GPU: "<<milliseconds<<"ms"<<endl;
// copying the results to host
int *result = (int *)malloc(sizeof(int));
cudaMemcpy(result, max_depth, sizeof(int), cudaMemcpyDeviceToHost);
printf("Depth : %d\n", result[0]);
// solution check
int *h_depth = (int*) malloc(nodes*sizeof(int));
cudaMemcpy(h_depth, d_depth, nodes*sizeof(int), cudaMemcpyDeviceToHost);
int *h_check_depth = (int*)malloc(nodes*sizeof(int));
freopen(argv[2], "r", stdin);
for(int i = 0; i < nodes; i++) {
cin>>h_check_depth[i];
}
bool flag = true;
int count = 0;
for(int i = 0; i < nodes; i++) {
if(h_depth[i] != h_check_depth[i]) {
printf("Found %d, Expected %d\n",h_depth[i], h_check_depth[i]);
flag = false;
count++;
}
}
if(flag) {
cout<<"Solution is correct!\n";
}
else {
cout<<"Solution is incorrect!"<<endl;
cout<<count<<" testcases failed.\n";
}
} | #include <hip/hip_runtime.h>
#include<bits/stdc++.h>
using namespace std;
#define MAX_VAL 100000000
__global__ void compute(int *d_r, int *d_u, int *d_v, int *depth, int *max_depth, int nodes, int edges){
int idx = threadIdx.x;
int i;
__shared__ int done;
__shared__ int curr_depth;
for(i=idx; i<nodes; i+=1024){
depth[i] = MAX_VAL;
}
if(idx==0){
depth[0] = 0;
curr_depth = 0;
done=0;
}
__syncthreads();
while(!done){
if(idx == 0){
done = 1;
}
__syncthreads();
for(i=idx; i<nodes; i+=1024){
if(depth[i] == curr_depth){
done = 0;
for(int j = d_r[i]; j<d_r[i+1]; j++){
int to = d_v[j];
if(depth[to] > curr_depth + 1){
depth[to] = curr_depth + 1;
}
}
}
}
if(idx==0 && done==0){
curr_depth++;
}
__syncthreads();
}
if(idx == 0)
*max_depth = curr_depth-1;
}
int main(int argc, char *argv[]){
if(argc<2){
cout << "Usage: " << argv[0] << " <graph_file_name>\n";
return 0;
}
ifstream input;
input.open(argv[1]);
int nodes, edges, i, j;
input >> nodes;
input >> edges;
// allocating host memory
int *h_r = (int*)malloc((nodes+1)*sizeof(int));
int *h_u = (int*)malloc(edges*2*sizeof(int));
int *h_v = (int*)malloc(edges*2*sizeof(int));
// reading the inputs
for(i=0; i<nodes+1; i++){
input >> h_r[i];
}
for(i=0; i<nodes+1; i++){
for(j=h_r[i]; j<h_r[i+1]; j++){
h_u[j] = i;
}
}
for(i=0; i<edges*2; i++){
input >> h_v[i];
}
// allocating device memory
int *d_r, *d_u, *d_v, *d_depth, *max_depth;
hipMalloc((void**)&d_r, (nodes+1)*sizeof(int));
hipMalloc((void**)&d_u, edges*2*sizeof(int));
hipMalloc((void**)&d_v, edges*2*sizeof(int));
hipMalloc((void**)&d_depth, nodes*sizeof(int));
hipMalloc((void**)&max_depth, sizeof(int));
// copying data to device
hipMemcpy(d_r, h_r, (nodes+1)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_u, h_u, edges*2*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_v, h_v, edges*2*sizeof(int), hipMemcpyHostToDevice);
// timer
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
// kernel call
printf("Starting Computation\n");
compute<<< 1,1024 >>> (d_r, d_u, d_v, d_depth, max_depth, nodes, edges);
printf("Finished computation\n");
// timer
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
cout<<"Compute time in GPU: "<<milliseconds<<"ms"<<endl;
// copying the results to host
int *result = (int *)malloc(sizeof(int));
hipMemcpy(result, max_depth, sizeof(int), hipMemcpyDeviceToHost);
printf("Depth : %d\n", result[0]);
// solution check
int *h_depth = (int*) malloc(nodes*sizeof(int));
hipMemcpy(h_depth, d_depth, nodes*sizeof(int), hipMemcpyDeviceToHost);
int *h_check_depth = (int*)malloc(nodes*sizeof(int));
freopen(argv[2], "r", stdin);
for(int i = 0; i < nodes; i++) {
cin>>h_check_depth[i];
}
bool flag = true;
int count = 0;
for(int i = 0; i < nodes; i++) {
if(h_depth[i] != h_check_depth[i]) {
printf("Found %d, Expected %d\n",h_depth[i], h_check_depth[i]);
flag = false;
count++;
}
}
if(flag) {
cout<<"Solution is correct!\n";
}
else {
cout<<"Solution is incorrect!"<<endl;
cout<<count<<" testcases failed.\n";
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<bits/stdc++.h>
using namespace std;
#define MAX_VAL 100000000
__global__ void compute(int *d_r, int *d_u, int *d_v, int *depth, int *max_depth, int nodes, int edges){
int idx = threadIdx.x;
int i;
__shared__ int done;
__shared__ int curr_depth;
for(i=idx; i<nodes; i+=1024){
depth[i] = MAX_VAL;
}
if(idx==0){
depth[0] = 0;
curr_depth = 0;
done=0;
}
__syncthreads();
while(!done){
if(idx == 0){
done = 1;
}
__syncthreads();
for(i=idx; i<nodes; i+=1024){
if(depth[i] == curr_depth){
done = 0;
for(int j = d_r[i]; j<d_r[i+1]; j++){
int to = d_v[j];
if(depth[to] > curr_depth + 1){
depth[to] = curr_depth + 1;
}
}
}
}
if(idx==0 && done==0){
curr_depth++;
}
__syncthreads();
}
if(idx == 0)
*max_depth = curr_depth-1;
}
int main(int argc, char *argv[]){
if(argc<2){
cout << "Usage: " << argv[0] << " <graph_file_name>\n";
return 0;
}
ifstream input;
input.open(argv[1]);
int nodes, edges, i, j;
input >> nodes;
input >> edges;
// allocating host memory
int *h_r = (int*)malloc((nodes+1)*sizeof(int));
int *h_u = (int*)malloc(edges*2*sizeof(int));
int *h_v = (int*)malloc(edges*2*sizeof(int));
// reading the inputs
for(i=0; i<nodes+1; i++){
input >> h_r[i];
}
for(i=0; i<nodes+1; i++){
for(j=h_r[i]; j<h_r[i+1]; j++){
h_u[j] = i;
}
}
for(i=0; i<edges*2; i++){
input >> h_v[i];
}
// allocating device memory
int *d_r, *d_u, *d_v, *d_depth, *max_depth;
hipMalloc((void**)&d_r, (nodes+1)*sizeof(int));
hipMalloc((void**)&d_u, edges*2*sizeof(int));
hipMalloc((void**)&d_v, edges*2*sizeof(int));
hipMalloc((void**)&d_depth, nodes*sizeof(int));
hipMalloc((void**)&max_depth, sizeof(int));
// copying data to device
hipMemcpy(d_r, h_r, (nodes+1)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_u, h_u, edges*2*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_v, h_v, edges*2*sizeof(int), hipMemcpyHostToDevice);
// timer
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
// kernel call
printf("Starting Computation\n");
compute<<< 1,1024 >>> (d_r, d_u, d_v, d_depth, max_depth, nodes, edges);
printf("Finished computation\n");
// timer
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
cout<<"Compute time in GPU: "<<milliseconds<<"ms"<<endl;
// copying the results to host
int *result = (int *)malloc(sizeof(int));
hipMemcpy(result, max_depth, sizeof(int), hipMemcpyDeviceToHost);
printf("Depth : %d\n", result[0]);
// solution check
int *h_depth = (int*) malloc(nodes*sizeof(int));
hipMemcpy(h_depth, d_depth, nodes*sizeof(int), hipMemcpyDeviceToHost);
int *h_check_depth = (int*)malloc(nodes*sizeof(int));
freopen(argv[2], "r", stdin);
for(int i = 0; i < nodes; i++) {
cin>>h_check_depth[i];
}
bool flag = true;
int count = 0;
for(int i = 0; i < nodes; i++) {
if(h_depth[i] != h_check_depth[i]) {
printf("Found %d, Expected %d\n",h_depth[i], h_check_depth[i]);
flag = false;
count++;
}
}
if(flag) {
cout<<"Solution is correct!\n";
}
else {
cout<<"Solution is incorrect!"<<endl;
cout<<count<<" testcases failed.\n";
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7computePiS_S_S_S_ii
.globl _Z7computePiS_S_S_S_ii
.p2align 8
.type _Z7computePiS_S_S_S_ii,@function
_Z7computePiS_S_S_S_ii:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x28
s_load_b64 s[6:7], s[0:1], 0x18
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s5, v0
s_cbranch_execz .LBB0_3
v_dual_mov_b32 v4, v0 :: v_dual_lshlrev_b32 v1, 2, v0
v_mov_b32_e32 v3, 0x5f5e100
s_mov_b32 s4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s2, s6, v1
v_add_co_ci_u32_e64 v2, null, s7, 0, s2
.LBB0_2:
v_add_nc_u32_e32 v4, 0x400, v4
global_store_b32 v[1:2], v3, off
v_add_co_u32 v1, s2, v1, 0x1000
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v2, s2, 0, v2, s2
v_cmp_le_i32_e32 vcc_lo, s5, v4
s_or_b32 s4, vcc_lo, s4
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_eq_u32_e64 s2, 0, v0
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, v1
global_store_b32 v3, v1, s[6:7]
ds_store_b64 v3, v[1:2]
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s3
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v2 offset:4
s_waitcnt lgkmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v1
s_cbranch_vccz .LBB0_9
.LBB0_6:
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_8
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x20
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, -1, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_9:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b64 s[10:11], s[0:1], 0x10
v_cmp_gt_i32_e64 s3, s5, v0
v_mov_b32_e32 v10, 1
s_branch .LBB0_11
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v2 offset:4
s_waitcnt lgkmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_cbranch_vccz .LBB0_6
.LBB0_11:
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_13
ds_store_b32 v2, v10 offset:4
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s12, s3
s_cbranch_execz .LBB0_22
ds_load_b32 v11, v2
s_mov_b32 s13, 0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, v0 :: v_dual_add_nc_u32 v12, 1, v11
s_branch .LBB0_16
.LBB0_15:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s14
v_add_nc_u32_e32 v1, 0x400, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s5, v1
s_or_b32 s13, vcc_lo, s13
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_22
.LBB0_16:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s14, exec_lo
v_add_co_u32 v5, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 v5, v11
s_cbranch_execz .LBB0_15
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
ds_store_b32 v2, v2 offset:4
global_load_b64 v[5:6], v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v5, v6
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_15
v_ashrrev_i32_e32 v6, 31, v5
s_mov_b32 s15, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s10, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_20
.p2align 6
.LBB0_19:
s_or_b32 exec_lo, exec_lo, s4
global_load_b32 v8, v[3:4], off offset:4
v_add_nc_u32_e32 v5, 1, v5
v_add_co_u32 v6, s4, v6, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v7, s4, 0, v7, s4
s_waitcnt vmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, v5, v8
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execz .LBB0_15
.LBB0_20:
global_load_b32 v8, v[6:7], off
s_mov_b32 s4, exec_lo
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v8, vcc_lo, s6, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
global_load_b32 v13, v[8:9], off
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 v13, v12
s_cbranch_execz .LBB0_19
global_store_b32 v[8:9], v12, off
s_branch .LBB0_19
.LBB0_22:
s_or_b32 exec_lo, exec_lo, s12
ds_load_b32 v1, v2 offset:4
s_waitcnt lgkmcnt(0)
v_readfirstlane_b32 s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 0
s_cselect_b32 s4, -1, 0
s_and_b32 s12, s2, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s12
s_cbranch_execz .LBB0_10
ds_load_b32 v1, v2
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, 1, v1
ds_store_b32 v2, v1
s_branch .LBB0_10
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7computePiS_S_S_S_ii
.amdhsa_group_segment_fixed_size 8
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7computePiS_S_S_S_ii, .Lfunc_end0-_Z7computePiS_S_S_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 8
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7computePiS_S_S_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7computePiS_S_S_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<bits/stdc++.h>
using namespace std;
#define MAX_VAL 100000000
__global__ void compute(int *d_r, int *d_u, int *d_v, int *depth, int *max_depth, int nodes, int edges){
int idx = threadIdx.x;
int i;
__shared__ int done;
__shared__ int curr_depth;
for(i=idx; i<nodes; i+=1024){
depth[i] = MAX_VAL;
}
if(idx==0){
depth[0] = 0;
curr_depth = 0;
done=0;
}
__syncthreads();
while(!done){
if(idx == 0){
done = 1;
}
__syncthreads();
for(i=idx; i<nodes; i+=1024){
if(depth[i] == curr_depth){
done = 0;
for(int j = d_r[i]; j<d_r[i+1]; j++){
int to = d_v[j];
if(depth[to] > curr_depth + 1){
depth[to] = curr_depth + 1;
}
}
}
}
if(idx==0 && done==0){
curr_depth++;
}
__syncthreads();
}
if(idx == 0)
*max_depth = curr_depth-1;
}
int main(int argc, char *argv[]){
if(argc<2){
cout << "Usage: " << argv[0] << " <graph_file_name>\n";
return 0;
}
ifstream input;
input.open(argv[1]);
int nodes, edges, i, j;
input >> nodes;
input >> edges;
// allocating host memory
int *h_r = (int*)malloc((nodes+1)*sizeof(int));
int *h_u = (int*)malloc(edges*2*sizeof(int));
int *h_v = (int*)malloc(edges*2*sizeof(int));
// reading the inputs
for(i=0; i<nodes+1; i++){
input >> h_r[i];
}
for(i=0; i<nodes+1; i++){
for(j=h_r[i]; j<h_r[i+1]; j++){
h_u[j] = i;
}
}
for(i=0; i<edges*2; i++){
input >> h_v[i];
}
// allocating device memory
int *d_r, *d_u, *d_v, *d_depth, *max_depth;
hipMalloc((void**)&d_r, (nodes+1)*sizeof(int));
hipMalloc((void**)&d_u, edges*2*sizeof(int));
hipMalloc((void**)&d_v, edges*2*sizeof(int));
hipMalloc((void**)&d_depth, nodes*sizeof(int));
hipMalloc((void**)&max_depth, sizeof(int));
// copying data to device
hipMemcpy(d_r, h_r, (nodes+1)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_u, h_u, edges*2*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_v, h_v, edges*2*sizeof(int), hipMemcpyHostToDevice);
// timer
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
// kernel call
printf("Starting Computation\n");
compute<<< 1,1024 >>> (d_r, d_u, d_v, d_depth, max_depth, nodes, edges);
printf("Finished computation\n");
// timer
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
cout<<"Compute time in GPU: "<<milliseconds<<"ms"<<endl;
// copying the results to host
int *result = (int *)malloc(sizeof(int));
hipMemcpy(result, max_depth, sizeof(int), hipMemcpyDeviceToHost);
printf("Depth : %d\n", result[0]);
// solution check
int *h_depth = (int*) malloc(nodes*sizeof(int));
hipMemcpy(h_depth, d_depth, nodes*sizeof(int), hipMemcpyDeviceToHost);
int *h_check_depth = (int*)malloc(nodes*sizeof(int));
freopen(argv[2], "r", stdin);
for(int i = 0; i < nodes; i++) {
cin>>h_check_depth[i];
}
bool flag = true;
int count = 0;
for(int i = 0; i < nodes; i++) {
if(h_depth[i] != h_check_depth[i]) {
printf("Found %d, Expected %d\n",h_depth[i], h_check_depth[i]);
flag = false;
count++;
}
}
if(flag) {
cout<<"Solution is correct!\n";
}
else {
cout<<"Solution is incorrect!"<<endl;
cout<<count<<" testcases failed.\n";
}
} | .text
.file "parallel_BFS_edge_parallel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__computePiS_S_S_S_ii # -- Begin function _Z22__device_stub__computePiS_S_S_S_ii
.p2align 4, 0x90
.type _Z22__device_stub__computePiS_S_S_S_ii,@function
_Z22__device_stub__computePiS_S_S_S_ii: # @_Z22__device_stub__computePiS_S_S_S_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computePiS_S_S_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__computePiS_S_S_S_ii, .Lfunc_end0-_Z22__device_stub__computePiS_S_S_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $760, %rsp # imm = 0x2F8
.cfi_def_cfa_offset 816
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
cmpl $1, %edi
jg .LBB1_5
# %bb.1:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rbx
testq %rbx, %rbx
je .LBB1_2
# %bb.3:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq strlen
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_4
.LBB1_5:
.cfi_escape 0x2e, 0x00
leaq 240(%rsp), %r14
movq %r14, %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev
movq 8(%rbx), %rsi
leaq 256(%rsp), %rdi
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $8, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.6: # %.noexc
movq 240(%rsp), %rcx
addq -24(%rcx), %r14
xorl %esi, %esi
testq %rax, %rax
jne .LBB1_8
# %bb.7:
movl 32(%r14), %esi
orl $4, %esi
.LBB1_8: # %.invoke
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp3:
# %bb.9: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
.Ltmp5:
movq %rbx, 80(%rsp) # 8-byte Spill
.cfi_escape 0x2e, 0x00
leaq 240(%rsp), %rdi
leaq 8(%rsp), %rsi
callq _ZNSirsERi
.Ltmp6:
# %bb.10:
.Ltmp7:
.cfi_escape 0x2e, 0x00
leaq 240(%rsp), %rdi
leaq 12(%rsp), %rsi
callq _ZNSirsERi
.Ltmp8:
# %bb.11:
movslq 8(%rsp), %rax
leaq 4(,%rax,4), %rdi
.cfi_escape 0x2e, 0x00
callq malloc
movq %rax, %r12
movslq 12(%rsp), %r14
shlq $3, %r14
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq malloc
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq malloc
movq %rax, %r14
movl 8(%rsp), %eax
testl %eax, %eax
js .LBB1_15
# %bb.12: # %.lr.ph.preheader
movq $-1, %rbx
leaq 240(%rsp), %r13
movq %r12, %rbp
.p2align 4, 0x90
.LBB1_13: # %.lr.ph
# =>This Inner Loop Header: Depth=1
.Ltmp10:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movq %rbp, %rsi
callq _ZNSirsERi
.Ltmp11:
# %bb.14: # in Loop: Header=BB1_13 Depth=1
movslq 8(%rsp), %rax
incq %rbx
addq $4, %rbp
cmpq %rax, %rbx
jl .LBB1_13
.LBB1_15: # %.preheader128
testl %eax, %eax
js .LBB1_20
# %bb.16: # %.lr.ph138.preheader
incl %eax
xorl %ecx, %ecx
jmp .LBB1_17
.p2align 4, 0x90
.LBB1_19: # %.loopexit127
# in Loop: Header=BB1_17 Depth=1
incq %rcx
cmpq %rax, %rcx
je .LBB1_20
.LBB1_17: # %.lr.ph138
# =>This Loop Header: Depth=1
# Child Loop BB1_18 Depth 2
movslq (%r12,%rcx,4), %rdx
movslq 4(%r12,%rcx,4), %rsi
cmpl %esi, %edx
jge .LBB1_19
.p2align 4, 0x90
.LBB1_18: # %.lr.ph134
# Parent Loop BB1_17 Depth=1
# => This Inner Loop Header: Depth=2
movl %ecx, (%r15,%rdx,4)
incq %rdx
cmpq %rdx, %rsi
jne .LBB1_18
jmp .LBB1_19
.LBB1_20: # %.preheader126
cmpl $0, 12(%rsp)
jle .LBB1_24
# %bb.21: # %.lr.ph140.preheader
xorl %ebx, %ebx
leaq 240(%rsp), %r13
movq %r14, %rbp
.p2align 4, 0x90
.LBB1_22: # %.lr.ph140
# =>This Inner Loop Header: Depth=1
.Ltmp13:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movq %rbp, %rsi
callq _ZNSirsERi
.Ltmp14:
# %bb.23: # in Loop: Header=BB1_22 Depth=1
incq %rbx
movslq 12(%rsp), %rax
addq %rax, %rax
addq $4, %rbp
cmpq %rax, %rbx
jl .LBB1_22
.LBB1_24: # %._crit_edge
movslq 8(%rsp), %rax
leaq 4(,%rax,4), %rsi
.Ltmp16:
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rdi
callq hipMalloc
.Ltmp17:
# %bb.25:
movslq 12(%rsp), %rsi
shlq $3, %rsi
.Ltmp18:
.cfi_escape 0x2e, 0x00
leaq 64(%rsp), %rdi
callq hipMalloc
.Ltmp19:
# %bb.26:
movslq 12(%rsp), %rsi
shlq $3, %rsi
.Ltmp20:
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
callq hipMalloc
.Ltmp21:
# %bb.27:
movslq 8(%rsp), %rsi
shlq $2, %rsi
.Ltmp22:
.cfi_escape 0x2e, 0x00
leaq 48(%rsp), %rdi
callq hipMalloc
.Ltmp23:
# %bb.28:
.Ltmp24:
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
movl $4, %esi
callq hipMalloc
.Ltmp25:
# %bb.29:
movq 72(%rsp), %rdi
movslq 8(%rsp), %rax
leaq 4(,%rax,4), %rdx
.Ltmp26:
.cfi_escape 0x2e, 0x00
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp27:
# %bb.30:
movq 64(%rsp), %rdi
movslq 12(%rsp), %rdx
shlq $3, %rdx
.Ltmp28:
.cfi_escape 0x2e, 0x00
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp29:
# %bb.31:
movq 56(%rsp), %rdi
movslq 12(%rsp), %rdx
shlq $3, %rdx
.Ltmp30:
.cfi_escape 0x2e, 0x00
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp31:
# %bb.32:
.Ltmp33:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
callq hipEventCreate
.Ltmp34:
# %bb.33:
.Ltmp35:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
callq hipEventCreate
.Ltmp36:
# %bb.34:
movq 32(%rsp), %rdi
.Ltmp37:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp38:
# %bb.35:
.cfi_escape 0x2e, 0x00
movl $.Lstr, %edi
callq puts@PLT
.Ltmp39:
.cfi_escape 0x2e, 0x00
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $4294968320, %rdx # imm = 0x100000400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp40:
# %bb.36:
testl %eax, %eax
jne .LBB1_39
# %bb.37:
movq 72(%rsp), %rax
movq 64(%rsp), %rcx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
movl 8(%rsp), %r8d
movl 12(%rsp), %r9d
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movq %rsi, 144(%rsp)
movq %rdi, 136(%rsp)
movl %r8d, 28(%rsp)
movl %r9d, 24(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 144(%rsp), %rax
movq %rax, 200(%rsp)
leaq 136(%rsp), %rax
movq %rax, 208(%rsp)
leaq 28(%rsp), %rax
movq %rax, 216(%rsp)
leaq 24(%rsp), %rax
movq %rax, 224(%rsp)
.Ltmp41:
.cfi_escape 0x2e, 0x00
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp42:
# %bb.38: # %.noexc90
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
.Ltmp43:
.cfi_escape 0x2e, 0x10
leaq 176(%rsp), %r9
movl $_Z7computePiS_S_S_S_ii, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp44:
.LBB1_39:
.cfi_escape 0x2e, 0x00
movl $.Lstr.1, %edi
callq puts@PLT
movq 16(%rsp), %rdi
.Ltmp45:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp46:
# %bb.40:
movq 16(%rsp), %rdi
.Ltmp47:
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
.Ltmp48:
# %bb.41:
movl $0, 176(%rsp)
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
.Ltmp50:
.cfi_escape 0x2e, 0x00
leaq 176(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp51:
# %bb.42:
.Ltmp52:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp53:
# %bb.43: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit93
movss 176(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp54:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp55:
# %bb.44: # %_ZNSolsEf.exit
.Ltmp56:
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $.L.str.5, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp57:
# %bb.45: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit96
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB1_46
# %bb.54: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_56
# %bb.55:
movzbl 67(%r15), %eax
jmp .LBB1_58
.LBB1_2:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_4: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_95
.LBB1_56:
.Ltmp58:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp59:
# %bb.57: # %.noexc107
movq (%r15), %rax
.Ltmp60:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp61:
.LBB1_58: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp62:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp63:
# %bb.59: # %.noexc109
.Ltmp64:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp65:
# %bb.60: # %_ZNSolsEPFRSoS_E.exit
.cfi_escape 0x2e, 0x00
movl $4, %edi
callq malloc
movq %rax, %r14
movq 40(%rsp), %rsi
.Ltmp66:
.cfi_escape 0x2e, 0x00
movl $4, %edx
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp67:
# %bb.61:
movl (%r14), %esi
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movslq 8(%rsp), %r15
shlq $2, %r15
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq malloc
movq %rax, %r14
movq 48(%rsp), %rsi
.Ltmp69:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
.Ltmp70:
# %bb.62:
movslq 8(%rsp), %rdi
shlq $2, %rdi
.cfi_escape 0x2e, 0x00
callq malloc
movq %rax, %r15
movq 80(%rsp), %rax # 8-byte Reload
movq 16(%rax), %rdi
movq stdin(%rip), %rdx
.Ltmp72:
.cfi_escape 0x2e, 0x00
movl $.L.str.7, %esi
callq freopen
.Ltmp73:
# %bb.63: # %.preheader125
cmpl $0, 8(%rsp)
jle .LBB1_67
# %bb.64: # %.lr.ph142.preheader
xorl %r12d, %r12d
movq %r15, %rbx
.p2align 4, 0x90
.LBB1_65: # %.lr.ph142
# =>This Inner Loop Header: Depth=1
.Ltmp75:
.cfi_escape 0x2e, 0x00
movl $_ZSt3cin, %edi
movq %rbx, %rsi
callq _ZNSirsERi
.Ltmp76:
# %bb.66: # in Loop: Header=BB1_65 Depth=1
incq %r12
movslq 8(%rsp), %rax
addq $4, %rbx
cmpq %rax, %r12
jl .LBB1_65
.LBB1_67: # %.preheader
cmpl $0, 8(%rsp)
jle .LBB1_68
# %bb.76: # %.lr.ph146.preheader
movb $1, %bpl
xorl %r12d, %r12d
xorl %ebx, %ebx
jmp .LBB1_77
.p2align 4, 0x90
.LBB1_79: # in Loop: Header=BB1_77 Depth=1
incq %r12
movslq 8(%rsp), %rax
cmpq %rax, %r12
jge .LBB1_73
.LBB1_77: # %.lr.ph146
# =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %esi
movl (%r15,%r12,4), %edx
cmpl %edx, %esi
je .LBB1_79
# %bb.78: # in Loop: Header=BB1_77 Depth=1
.cfi_escape 0x2e, 0x00
xorl %ebp, %ebp
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
incl %ebx
jmp .LBB1_79
.LBB1_73: # %._crit_edge147.loopexit
testb $1, %bpl
sete %al
testb %al, %al
je .LBB1_75
.LBB1_81:
.Ltmp78:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp79:
# %bb.82: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit101
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_83
# %bb.85: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i112
cmpb $0, 56(%r14)
je .LBB1_87
# %bb.86:
movzbl 67(%r14), %eax
jmp .LBB1_89
.LBB1_68:
xorl %eax, %eax
xorl %ebx, %ebx
testb %al, %al
jne .LBB1_81
.LBB1_75:
movl $21, %edx
movl $.L.str.9, %esi
movl $_ZSt4cout, %edi
jmp .LBB1_93
.LBB1_87:
.Ltmp80:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp81:
# %bb.88: # %.noexc117
movq (%r14), %rax
.Ltmp82:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp83:
.LBB1_89: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i114
.Ltmp84:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp85:
# %bb.90: # %.noexc119
.Ltmp86:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp87:
# %bb.91: # %_ZNSolsEPFRSoS_E.exit103
.Ltmp88:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
.Ltmp89:
# %bb.92:
movq %rax, %rdi
movl $19, %edx
movl $.L.str.11, %esi
.LBB1_93: # %.invoke167
.Ltmp90:
.cfi_escape 0x2e, 0x00
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp91:
# %bb.94: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit99
.cfi_escape 0x2e, 0x00
leaq 240(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 496(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
.LBB1_95:
xorl %eax, %eax
addq $760, %rsp # imm = 0x2F8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_46:
.cfi_def_cfa_offset 816
.Ltmp95:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp96:
# %bb.53: # %.noexc106
.LBB1_83:
.Ltmp92:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp93:
# %bb.84: # %.noexc116
.LBB1_71:
.Ltmp74:
jmp .LBB1_97
.LBB1_70:
.Ltmp71:
jmp .LBB1_97
.LBB1_69:
.Ltmp68:
jmp .LBB1_97
.LBB1_48:
.Ltmp9:
jmp .LBB1_97
.LBB1_47:
.Ltmp4:
jmp .LBB1_97
.LBB1_80:
.Ltmp94:
jmp .LBB1_97
.LBB1_52:
.Ltmp49:
jmp .LBB1_97
.LBB1_96:
.Ltmp97:
jmp .LBB1_97
.LBB1_51:
.Ltmp32:
jmp .LBB1_97
.LBB1_72:
.Ltmp77:
jmp .LBB1_97
.LBB1_49: # %.loopexit
.Ltmp15:
jmp .LBB1_97
.LBB1_50: # %.loopexit.split-lp
.Ltmp12:
.LBB1_97:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 240(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 496(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp8-.Ltmp5 # Call between .Ltmp5 and .Ltmp8
.uleb128 .Ltmp9-.Lfunc_begin0 # jumps to .Ltmp9
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp11-.Ltmp10 # Call between .Ltmp10 and .Ltmp11
.uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp14-.Ltmp13 # Call between .Ltmp13 and .Ltmp14
.uleb128 .Ltmp15-.Lfunc_begin0 # jumps to .Ltmp15
.byte 0 # On action: cleanup
.uleb128 .Ltmp16-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp31-.Ltmp16 # Call between .Ltmp16 and .Ltmp31
.uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32
.byte 0 # On action: cleanup
.uleb128 .Ltmp33-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp48-.Ltmp33 # Call between .Ltmp33 and .Ltmp48
.uleb128 .Ltmp49-.Lfunc_begin0 # jumps to .Ltmp49
.byte 0 # On action: cleanup
.uleb128 .Ltmp50-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp57-.Ltmp50 # Call between .Ltmp50 and .Ltmp57
.uleb128 .Ltmp97-.Lfunc_begin0 # jumps to .Ltmp97
.byte 0 # On action: cleanup
.uleb128 .Ltmp57-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp58-.Ltmp57 # Call between .Ltmp57 and .Ltmp58
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp58-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp65-.Ltmp58 # Call between .Ltmp58 and .Ltmp65
.uleb128 .Ltmp97-.Lfunc_begin0 # jumps to .Ltmp97
.byte 0 # On action: cleanup
.uleb128 .Ltmp66-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp67-.Ltmp66 # Call between .Ltmp66 and .Ltmp67
.uleb128 .Ltmp68-.Lfunc_begin0 # jumps to .Ltmp68
.byte 0 # On action: cleanup
.uleb128 .Ltmp69-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp70-.Ltmp69 # Call between .Ltmp69 and .Ltmp70
.uleb128 .Ltmp71-.Lfunc_begin0 # jumps to .Ltmp71
.byte 0 # On action: cleanup
.uleb128 .Ltmp72-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp73-.Ltmp72 # Call between .Ltmp72 and .Ltmp73
.uleb128 .Ltmp74-.Lfunc_begin0 # jumps to .Ltmp74
.byte 0 # On action: cleanup
.uleb128 .Ltmp75-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp76-.Ltmp75 # Call between .Ltmp75 and .Ltmp76
.uleb128 .Ltmp77-.Lfunc_begin0 # jumps to .Ltmp77
.byte 0 # On action: cleanup
.uleb128 .Ltmp78-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Ltmp91-.Ltmp78 # Call between .Ltmp78 and .Ltmp91
.uleb128 .Ltmp94-.Lfunc_begin0 # jumps to .Ltmp94
.byte 0 # On action: cleanup
.uleb128 .Ltmp95-.Lfunc_begin0 # >> Call Site 16 <<
.uleb128 .Ltmp96-.Ltmp95 # Call between .Ltmp95 and .Ltmp96
.uleb128 .Ltmp97-.Lfunc_begin0 # jumps to .Ltmp97
.byte 0 # On action: cleanup
.uleb128 .Ltmp92-.Lfunc_begin0 # >> Call Site 17 <<
.uleb128 .Ltmp93-.Ltmp92 # Call between .Ltmp92 and .Ltmp93
.uleb128 .Ltmp94-.Lfunc_begin0 # jumps to .Ltmp94
.byte 0 # On action: cleanup
.uleb128 .Ltmp93-.Lfunc_begin0 # >> Call Site 18 <<
.uleb128 .Lfunc_end1-.Ltmp93 # Call between .Ltmp93 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computePiS_S_S_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computePiS_S_S_S_ii,@object # @_Z7computePiS_S_S_S_ii
.section .rodata,"a",@progbits
.globl _Z7computePiS_S_S_S_ii
.p2align 3, 0x0
_Z7computePiS_S_S_S_ii:
.quad _Z22__device_stub__computePiS_S_S_S_ii
.size _Z7computePiS_S_S_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage: "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " <graph_file_name>\n"
.size .L.str.1, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Compute time in GPU: "
.size .L.str.4, 22
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "ms"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Depth : %d\n"
.size .L.str.6, 12
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "r"
.size .L.str.7, 2
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Found %d, Expected %d\n"
.size .L.str.8, 23
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Solution is correct!\n"
.size .L.str.9, 22
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Solution is incorrect!"
.size .L.str.10, 23
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " testcases failed.\n"
.size .L.str.11, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7computePiS_S_S_S_ii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Starting Computation"
.size .Lstr, 21
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Finished computation"
.size .Lstr.1, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computePiS_S_S_S_ii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z7computePiS_S_S_S_ii
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7computePiS_S_S_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x5b0 ; /* 0x0000057000007945 */
/* 0x000fe20003800000 */
/*0040*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x188], PT ; /* 0x0000620000007a0c */
/* 0x001fda0003f26270 */
/*0050*/ @P1 BRA 0x5a0 ; /* 0x0000054000001947 */
/* 0x000fea0003800000 */
/*0060*/ LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff027212 */
/* 0x000fe200078e33ff */
/*0070*/ BSSY B1, 0x180 ; /* 0x0000010000017945 */
/* 0x000fe60003800000 */
/*0080*/ IADD3 R2, R2, c[0x0][0x188], RZ ; /* 0x0000620002027a10 */
/* 0x000fc80007ffe0ff */
/*0090*/ LEA.HI R3, R2.reuse, 0x1, RZ, 0x16 ; /* 0x0000000102037811 */
/* 0x040fe400078fb0ff */
/*00a0*/ ISETP.GE.U32.AND P2, PT, R2, 0xc00, PT ; /* 0x00000c000200780c */
/* 0x000fe20003f46070 */
/*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0000 */
/*00c0*/ LOP3.LUT P0, R3, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303037812 */
/* 0x000fda000780c0ff */
/*00d0*/ @!P0 BRA 0x170 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R9, RZ, RZ, 0x5f5e100 ; /* 0x05f5e100ff097424 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD.WIDE R4, R2.reuse, R7, c[0x0][0x178] ; /* 0x00005e0002047625 */
/* 0x040fe200078e0207 */
/*0120*/ IADD3 R3, R3, -0x1, RZ ; /* 0xffffffff03037810 */
/* 0x000fe40007ffe0ff */
/*0130*/ IADD3 R2, R2, 0x400, RZ ; /* 0x0000040002027810 */
/* 0x000fe40007ffe0ff */
/*0140*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e2000c101904 */
/*0150*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0160*/ @P0 BRA 0x110 ; /* 0xffffffa000000947 */
/* 0x001fea000383ffff */
/*0170*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0180*/ @!P2 BRA 0x5a0 ; /* 0x000004100000a947 */
/* 0x000fea0003800000 */
/*0190*/ IADD3 R3, -R2, c[0x0][0x188], RZ ; /* 0x0000620002037a10 */
/* 0x000fe20007ffe1ff */
/*01a0*/ BSSY B1, 0x3e0 ; /* 0x0000023000017945 */
/* 0x000fe20003800000 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*01c0*/ ISETP.GT.AND P2, PT, R3, 0x3000, PT ; /* 0x000030000300780c */
/* 0x000fda0003f44270 */
/*01d0*/ @!P2 BRA 0x3d0 ; /* 0x000001f00000a947 */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff037624 */
/* 0x000fe200078e00ff */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0200*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe400078e00ff */
/*0210*/ IMAD.MOV.U32 R15, RZ, RZ, 0x5f5e100 ; /* 0x05f5e100ff0f7424 */
/* 0x000fe200078e00ff */
/*0220*/ IADD3 R3, R3, -0x3000, RZ ; /* 0xffffd00003037810 */
/* 0x000fe40007ffe0ff */
/*0230*/ IADD3 R4, R2.reuse, 0x1000, RZ ; /* 0x0000100002047810 */
/* 0x041fe20007ffe0ff */
/*0240*/ IMAD.WIDE R10, R2.reuse, R13.reuse, c[0x0][0x178] ; /* 0x00005e00020a7625 */
/* 0x0c0fe200078e020d */
/*0250*/ IADD3 R6, R2.reuse, 0x2000, RZ ; /* 0x0000200002067810 */
/* 0x040fe40007ffe0ff */
/*0260*/ IADD3 R8, R2, 0x3000, RZ ; /* 0x0000300002087810 */
/* 0x000fe20007ffe0ff */
/*0270*/ IMAD.WIDE R4, R4, R13, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fe200078e020d */
/*0280*/ STG.E [R10.64], R15 ; /* 0x0000000f0a007986 */
/* 0x0001e2000c101904 */
/*0290*/ IADD3 R2, R2, 0x4000, RZ ; /* 0x0000400002027810 */
/* 0x000fc40007ffe0ff */
/*02a0*/ IMAD.WIDE R6, R6, R13, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fe200078e020d */
/*02b0*/ STG.E [R10.64+0x1000], R15 ; /* 0x0010000f0a007986 */
/* 0x0001e2000c101904 */
/*02c0*/ ISETP.GE.AND P2, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fe40003f46270 */
/*02d0*/ IMAD.WIDE R8, R8, R13, c[0x0][0x178] ; /* 0x00005e0008087625 */
/* 0x000fe200078e020d */
/*02e0*/ STG.E [R10.64+0x2000], R15 ; /* 0x0020000f0a007986 */
/* 0x0001e8000c101904 */
/*02f0*/ STG.E [R10.64+0x3000], R15 ; /* 0x0030000f0a007986 */
/* 0x0001e8000c101904 */
/*0300*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x0001e8000c101904 */
/*0310*/ STG.E [R4.64+0x1000], R15 ; /* 0x0010000f04007986 */
/* 0x0001e8000c101904 */
/*0320*/ STG.E [R4.64+0x2000], R15 ; /* 0x0020000f04007986 */
/* 0x0001e8000c101904 */
/*0330*/ STG.E [R4.64+0x3000], R15 ; /* 0x0030000f04007986 */
/* 0x0001e8000c101904 */
/*0340*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0001e8000c101904 */
/*0350*/ STG.E [R6.64+0x1000], R15 ; /* 0x0010000f06007986 */
/* 0x0001e8000c101904 */
/*0360*/ STG.E [R6.64+0x2000], R15 ; /* 0x0020000f06007986 */
/* 0x0001e8000c101904 */
/*0370*/ STG.E [R6.64+0x3000], R15 ; /* 0x0030000f06007986 */
/* 0x0001e8000c101904 */
/*0380*/ STG.E [R8.64], R15 ; /* 0x0000000f08007986 */
/* 0x0001e8000c101904 */
/*0390*/ STG.E [R8.64+0x1000], R15 ; /* 0x0010000f08007986 */
/* 0x0001e8000c101904 */
/*03a0*/ STG.E [R8.64+0x2000], R15 ; /* 0x0020000f08007986 */
/* 0x0001e8000c101904 */
/*03b0*/ STG.E [R8.64+0x3000], R15 ; /* 0x0030000f08007986 */
/* 0x0001e2000c101904 */
/*03c0*/ @!P2 BRA 0x230 ; /* 0xfffffe600000a947 */
/* 0x000fea000383ffff */
/*03d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*03e0*/ IADD3 R3, -R2, c[0x0][0x188], RZ ; /* 0x0000620002037a10 */
/* 0x000fe20007ffe1ff */
/*03f0*/ BSSY B1, 0x520 ; /* 0x0000012000017945 */
/* 0x000fe60003800000 */
/*0400*/ ISETP.GT.AND P2, PT, R3, 0x1000, PT ; /* 0x000010000300780c */
/* 0x000fda0003f44270 */
/*0410*/ @!P2 BRA 0x510 ; /* 0x000000f00000a947 */
/* 0x000fea0003800000 */
/*0420*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x001fe200078e00ff */
/*0430*/ IADD3 R6, R2.reuse, 0x1000, RZ ; /* 0x0000100002067810 */
/* 0x040fe20007ffe0ff */
/*0440*/ IMAD.MOV.U32 R3, RZ, RZ, 0x5f5e100 ; /* 0x05f5e100ff037424 */
/* 0x000fe200078e00ff */
/*0450*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0460*/ IMAD.WIDE R4, R2.reuse, R7, c[0x0][0x178] ; /* 0x00005e0002047625 */
/* 0x040fe200078e0207 */
/*0470*/ IADD3 R2, R2, 0x2000, RZ ; /* 0x0000200002027810 */
/* 0x000fc60007ffe0ff */
/*0480*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fe200078e0207 */
/*0490*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0001e8000c101904 */
/*04a0*/ STG.E [R4.64+0x1000], R3 ; /* 0x0010000304007986 */
/* 0x0001e8000c101904 */
/*04b0*/ STG.E [R4.64+0x2000], R3 ; /* 0x0020000304007986 */
/* 0x0001e8000c101904 */
/*04c0*/ STG.E [R4.64+0x3000], R3 ; /* 0x0030000304007986 */
/* 0x0001e8000c101904 */
/*04d0*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x0001e8000c101904 */
/*04e0*/ STG.E [R6.64+0x1000], R3 ; /* 0x0010000306007986 */
/* 0x0001e8000c101904 */
/*04f0*/ STG.E [R6.64+0x2000], R3 ; /* 0x0020000306007986 */
/* 0x0001e8000c101904 */
/*0500*/ STG.E [R6.64+0x3000], R3 ; /* 0x0030000306007986 */
/* 0x0001e4000c101904 */
/*0510*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0520*/ ISETP.LT.OR P0, PT, R2, c[0x0][0x188], P0 ; /* 0x0000620002007a0c */
/* 0x000fda0000701670 */
/*0530*/ @P0 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff030424 */
/* 0x001fe400078e00ff */
/*0540*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, 0x5f5e100 ; /* 0x05f5e100ff050424 */
/* 0x000fe400078e00ff */
/*0550*/ @P0 IMAD.WIDE R2, R2, R3, c[0x0][0x178] ; /* 0x00005e0002020625 */
/* 0x000fca00078e0203 */
/*0560*/ @P0 STG.E [R2.64], R5 ; /* 0x0000000502000986 */
/* 0x0001e8000c101904 */
/*0570*/ @P0 STG.E [R2.64+0x1000], R5 ; /* 0x0010000502000986 */
/* 0x0001e8000c101904 */
/*0580*/ @P0 STG.E [R2.64+0x2000], R5 ; /* 0x0020000502000986 */
/* 0x0001e8000c101904 */
/*0590*/ @P0 STG.E [R2.64+0x3000], R5 ; /* 0x0030000502000986 */
/* 0x0001e4000c101904 */
/*05a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05b0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*05c0*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff028624 */
/* 0x001fe200078e00ff */
/*05d0*/ @!P0 STS.64 [RZ], RZ ; /* 0x000000ffff008388 */
/* 0x000fe20000000a00 */
/*05e0*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff038624 */
/* 0x000fca00078e00ff */
/*05f0*/ @!P0 STG.E [R2.64], RZ ; /* 0x000000ff02008986 */
/* 0x000fe8000c101904 */
/*0600*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0610*/ LDS R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x000e240000000800 */
/*0620*/ ISETP.NE.AND P2, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x001fda0003f45270 */
/*0630*/ @P2 BRA 0x9b0 ; /* 0x0000037000002947 */
/* 0x000fea0003800000 */
/*0640*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff028424 */
/* 0x000fe200078e00ff */
/*0650*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0660*/ BSSY B0, 0x930 ; /* 0x000002c000007945 */
/* 0x000fe60003800000 */
/*0670*/ @!P0 STS [RZ], R2 ; /* 0x00000002ff008388 */
/* 0x0001e80000000800 */
/*0680*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0690*/ @P1 BRA 0x920 ; /* 0x0000028000001947 */
/* 0x000fea0003800000 */
/*06a0*/ LDS R8, [0x4] ; /* 0x00000400ff087984 */
/* 0x001e220000000800 */
/*06b0*/ IMAD.MOV.U32 R10, RZ, RZ, R0 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0000 */
/*06c0*/ IADD3 R9, R8, 0x1, RZ ; /* 0x0000000108097810 */
/* 0x001fc40007ffe0ff */
/*06d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*06e0*/ IMAD.WIDE R2, R10, R5, c[0x0][0x178] ; /* 0x00005e000a027625 */
/* 0x001fcc00078e0205 */
/*06f0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0700*/ BSSY B1, 0x8f0 ; /* 0x000001e000017945 */
/* 0x000fe20003800000 */
/*0710*/ ISETP.NE.AND P2, PT, R3, R8, PT ; /* 0x000000080300720c */
/* 0x004fda0003f45270 */
/*0720*/ @P2 BRA 0x8e0 ; /* 0x000001b000002947 */
/* 0x000fea0003800000 */
/*0730*/ SHF.R.S32.HI R3, RZ, 0x1f, R10 ; /* 0x0000001fff037819 */
/* 0x000fe4000001140a */
/*0740*/ LEA R2, P2, R10, c[0x0][0x160], 0x2 ; /* 0x000058000a027a11 */
/* 0x000fc800078410ff */
/*0750*/ LEA.HI.X R3, R10, c[0x0][0x164], R3, 0x2, P2 ; /* 0x000059000a037a11 */
/* 0x000fca00010f1403 */
/*0760*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R7, [R2.64+0x4] ; /* 0x0000040402077981 */
/* 0x000ea8000c1e1900 */
/*0780*/ STS [RZ], RZ ; /* 0x000000ffff007388 */
/* 0x000fe20000000800 */
/*0790*/ ISETP.GE.AND P2, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x004fda0003f46270 */
/*07a0*/ @P2 BRA 0x8e0 ; /* 0x0000013000002947 */
/* 0x000fea0003800000 */
/*07b0*/ IMAD.MOV.U32 R11, RZ, RZ, R4 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0004 */
/*07c0*/ IMAD.MOV.U32 R12, RZ, RZ, R7 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0007 */
/*07d0*/ IMAD.WIDE R4, R11, R5, c[0x0][0x170] ; /* 0x00005c000b047625 */
/* 0x000fca00078e0205 */
/*07e0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x001ea2000c1e1900 */
/*07f0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*0800*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x004fca00078e0207 */
/*0810*/ LDG.E R14, [R6.64] ; /* 0x00000004060e7981 */
/* 0x000ea2000c1e1900 */
/*0820*/ BSSY B2, 0x8b0 ; /* 0x0000008000027945 */
/* 0x000fe20003800000 */
/*0830*/ IADD3 R4, P2, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fe40007f5e0ff */
/*0840*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fe40007ffe0ff */
/*0850*/ ISETP.GT.AND P3, PT, R14, R9, PT ; /* 0x000000090e00720c */
/* 0x004fda0003f64270 */
/*0860*/ @!P3 BRA 0x8a0 ; /* 0x000000300000b947 */
/* 0x000fea0003800000 */
/*0870*/ IADD3 R9, R8, 0x1, RZ ; /* 0x0000000108097810 */
/* 0x000fca0007ffe0ff */
/*0880*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e8000c101904 */
/*0890*/ LDG.E R12, [R2.64+0x4] ; /* 0x00000404020c7981 */
/* 0x000164000c1e1900 */
/*08a0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*08b0*/ ISETP.GE.AND P3, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x020fe20003f66270 */
/*08c0*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fd800010e0605 */
/*08d0*/ @!P3 BRA 0x7e0 ; /* 0xffffff000000b947 */
/* 0x000fea000383ffff */
/*08e0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08f0*/ IADD3 R10, R10, 0x400, RZ ; /* 0x000004000a0a7810 */
/* 0x000fc80007ffe0ff */
/*0900*/ ISETP.GE.AND P2, PT, R10, c[0x0][0x188], PT ; /* 0x000062000a007a0c */
/* 0x000fda0003f46270 */
/*0910*/ @!P2 BRA 0x6d0 ; /* 0xfffffdb00000a947 */
/* 0x000fea000383ffff */
/*0920*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0930*/ LDS.64 R2, [RZ] ; /* 0x00000000ff027984 */
/* 0x000e240000000a00 */
/*0940*/ LOP3.LUT P2, RZ, R2, R0, RZ, 0xfc, !PT ; /* 0x0000000002ff7212 */
/* 0x001fda000784fcff */
/*0950*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fca0007ffe0ff */
/*0960*/ @!P2 STS [0x4], R3 ; /* 0x00000403ff00a388 */
/* 0x000fe80000000800 */
/*0970*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0980*/ LDS R2, [RZ] ; /* 0x00000000ff027984 */
/* 0x000e240000000800 */
/*0990*/ ISETP.NE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x001fda0003f45270 */
/*09a0*/ @!P2 BRA 0x640 ; /* 0xfffffc900000a947 */
/* 0x000fea000383ffff */
/*09b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*09c0*/ LDS R5, [0x4] ; /* 0x00000400ff057984 */
/* 0x000e220000000800 */
/*09d0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff027624 */
/* 0x000fe400078e00ff */
/*09e0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff037624 */
/* 0x000fe200078e00ff */
/*09f0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x001fca0007ffe0ff */
/*0a00*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0a10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a20*/ BRA 0xa20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7computePiS_S_S_S_ii
.globl _Z7computePiS_S_S_S_ii
.p2align 8
.type _Z7computePiS_S_S_S_ii,@function
_Z7computePiS_S_S_S_ii:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x28
s_load_b64 s[6:7], s[0:1], 0x18
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s5, v0
s_cbranch_execz .LBB0_3
v_dual_mov_b32 v4, v0 :: v_dual_lshlrev_b32 v1, 2, v0
v_mov_b32_e32 v3, 0x5f5e100
s_mov_b32 s4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s2, s6, v1
v_add_co_ci_u32_e64 v2, null, s7, 0, s2
.LBB0_2:
v_add_nc_u32_e32 v4, 0x400, v4
global_store_b32 v[1:2], v3, off
v_add_co_u32 v1, s2, v1, 0x1000
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v2, s2, 0, v2, s2
v_cmp_le_i32_e32 vcc_lo, s5, v4
s_or_b32 s4, vcc_lo, s4
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_eq_u32_e64 s2, 0, v0
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, v1
global_store_b32 v3, v1, s[6:7]
ds_store_b64 v3, v[1:2]
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s3
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v2 offset:4
s_waitcnt lgkmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v1
s_cbranch_vccz .LBB0_9
.LBB0_6:
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_8
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x20
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, -1, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_9:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b64 s[10:11], s[0:1], 0x10
v_cmp_gt_i32_e64 s3, s5, v0
v_mov_b32_e32 v10, 1
s_branch .LBB0_11
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v2 offset:4
s_waitcnt lgkmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_cbranch_vccz .LBB0_6
.LBB0_11:
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_13
ds_store_b32 v2, v10 offset:4
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s12, s3
s_cbranch_execz .LBB0_22
ds_load_b32 v11, v2
s_mov_b32 s13, 0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, v0 :: v_dual_add_nc_u32 v12, 1, v11
s_branch .LBB0_16
.LBB0_15:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s14
v_add_nc_u32_e32 v1, 0x400, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s5, v1
s_or_b32 s13, vcc_lo, s13
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_22
.LBB0_16:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s14, exec_lo
v_add_co_u32 v5, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 v5, v11
s_cbranch_execz .LBB0_15
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
ds_store_b32 v2, v2 offset:4
global_load_b64 v[5:6], v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v5, v6
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_15
v_ashrrev_i32_e32 v6, 31, v5
s_mov_b32 s15, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s10, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_20
.p2align 6
.LBB0_19:
s_or_b32 exec_lo, exec_lo, s4
global_load_b32 v8, v[3:4], off offset:4
v_add_nc_u32_e32 v5, 1, v5
v_add_co_u32 v6, s4, v6, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v7, s4, 0, v7, s4
s_waitcnt vmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, v5, v8
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execz .LBB0_15
.LBB0_20:
global_load_b32 v8, v[6:7], off
s_mov_b32 s4, exec_lo
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v8, vcc_lo, s6, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
global_load_b32 v13, v[8:9], off
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 v13, v12
s_cbranch_execz .LBB0_19
global_store_b32 v[8:9], v12, off
s_branch .LBB0_19
.LBB0_22:
s_or_b32 exec_lo, exec_lo, s12
ds_load_b32 v1, v2 offset:4
s_waitcnt lgkmcnt(0)
v_readfirstlane_b32 s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 0
s_cselect_b32 s4, -1, 0
s_and_b32 s12, s2, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s12
s_cbranch_execz .LBB0_10
ds_load_b32 v1, v2
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, 1, v1
ds_store_b32 v2, v1
s_branch .LBB0_10
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7computePiS_S_S_S_ii
.amdhsa_group_segment_fixed_size 8
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7computePiS_S_S_S_ii, .Lfunc_end0-_Z7computePiS_S_S_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 8
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7computePiS_S_S_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7computePiS_S_S_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00059193_00000000-6_parallel_BFS_edge_parallel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB10862:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10862:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z7computePiS_S_S_S_iiPiS_S_S_S_ii
.type _Z36__device_stub__Z7computePiS_S_S_S_iiPiS_S_S_S_ii, @function
_Z36__device_stub__Z7computePiS_S_S_S_iiPiS_S_S_S_ii:
.LFB10884:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7computePiS_S_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10884:
.size _Z36__device_stub__Z7computePiS_S_S_S_iiPiS_S_S_S_ii, .-_Z36__device_stub__Z7computePiS_S_S_S_iiPiS_S_S_S_ii
.globl _Z7computePiS_S_S_S_ii
.type _Z7computePiS_S_S_S_ii, @function
_Z7computePiS_S_S_S_ii:
.LFB10885:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z36__device_stub__Z7computePiS_S_S_S_iiPiS_S_S_S_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10885:
.size _Z7computePiS_S_S_S_ii, .-_Z7computePiS_S_S_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7computePiS_S_S_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB10887:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computePiS_S_S_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10887:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC1:
.string "Usage: "
.LC2:
.string " <graph_file_name>\n"
.LC3:
.string "Starting Computation\n"
.LC4:
.string "Finished computation\n"
.LC6:
.string "Compute time in GPU: "
.LC7:
.string "ms"
.LC8:
.string "Depth : %d\n"
.LC9:
.string "r"
.LC10:
.string "Found %d, Expected %d\n"
.LC11:
.string "Solution is correct!\n"
.LC12:
.string "Solution is incorrect!"
.LC13:
.string " testcases failed.\n"
.text
.globl main
.type main, @function
main:
.LFB10859:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA10859
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $648, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rsi, %r14
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
cmpl $1, %edi
jle .L43
leaq -576(%rbp), %rbx
movq %rbx, %rdi
.LEHB0:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE0:
movq 8(%r14), %rsi
movl $8, %edx
movq %rbx, %rdi
.LEHB1:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
.LEHE1:
jmp .L44
.L43:
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB2:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%r14), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.LEHE2:
jmp .L15
.L44:
leaq -664(%rbp), %rsi
movq %rbx, %rdi
.LEHB3:
call _ZNSirsERi@PLT
leaq -660(%rbp), %rsi
movq %rbx, %rdi
call _ZNSirsERi@PLT
movl -664(%rbp), %r15d
leal 1(%r15), %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r12
movl -660(%rbp), %eax
leal (%rax,%rax), %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, -688(%rbp)
testl %r15d, %r15d
js .L16
movq %r12, -680(%rbp)
movl $0, %ebx
leaq -576(%rbp), %r15
jmp .L17
.L46:
addl $1, %ebx
movl -664(%rbp), %eax
addq $4, -680(%rbp)
cmpl %ebx, %eax
jl .L45
.L17:
movq -680(%rbp), %rsi
movq %r15, %rdi
call _ZNSirsERi@PLT
jmp .L46
.L45:
testl %eax, %eax
js .L16
leal 1(%rax), %r9d
movl $0, %esi
.L20:
movl %esi, %edx
movl (%r12,%rsi,4), %edi
movl 4(%r12,%rsi,4), %ecx
cmpl %ecx, %edi
jge .L18
movslq %edi, %r8
leaq 0(%r13,%r8,4), %rax
subl %edi, %ecx
addq %r8, %rcx
leaq 0(%r13,%rcx,4), %rcx
.L19:
movl %edx, (%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L19
.L18:
addq $1, %rsi
cmpq %r9, %rsi
jne .L20
.L16:
cmpl $0, -660(%rbp)
jle .L21
movq -688(%rbp), %rax
movq %rax, -680(%rbp)
movl $0, %ebx
leaq -576(%rbp), %r15
jmp .L22
.L47:
addl $1, %ebx
addq $4, -680(%rbp)
movl -660(%rbp), %eax
addl %eax, %eax
cmpl %ebx, %eax
jle .L21
.L22:
movq -680(%rbp), %rsi
movq %r15, %rdi
call _ZNSirsERi@PLT
jmp .L47
.L21:
movl -664(%rbp), %eax
leal 1(%rax), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq -656(%rbp), %rdi
call cudaMalloc@PLT
movl -660(%rbp), %eax
leal (%rax,%rax), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq -648(%rbp), %rdi
call cudaMalloc@PLT
movl -660(%rbp), %eax
leal (%rax,%rax), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq -640(%rbp), %rdi
call cudaMalloc@PLT
movslq -664(%rbp), %rsi
salq $2, %rsi
leaq -632(%rbp), %rdi
call cudaMalloc@PLT
leaq -624(%rbp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl -664(%rbp), %eax
leal 1(%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r12, %rsi
movq -656(%rbp), %rdi
call cudaMemcpy@PLT
movl -660(%rbp), %eax
leal (%rax,%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r13, %rsi
movq -648(%rbp), %rdi
call cudaMemcpy@PLT
movl -660(%rbp), %eax
leal (%rax,%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq -688(%rbp), %rsi
movq -640(%rbp), %rdi
call cudaMemcpy@PLT
leaq -616(%rbp), %rdi
call cudaEventCreate@PLT
leaq -608(%rbp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq -616(%rbp), %rdi
call cudaEventRecord@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1024, -588(%rbp)
movl $1, -584(%rbp)
movl $1, -580(%rbp)
movl $1, -600(%rbp)
movl $1, -596(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -588(%rbp), %rdx
movl $1, %ecx
movq -600(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L23
subq $8, %rsp
movl -660(%rbp), %eax
pushq %rax
movl -664(%rbp), %r9d
movq -624(%rbp), %r8
movq -632(%rbp), %rcx
movq -640(%rbp), %rdx
movq -648(%rbp), %rsi
movq -656(%rbp), %rdi
.cfi_escape 0x2e,0x10
call _Z36__device_stub__Z7computePiS_S_S_S_iiPiS_S_S_S_ii
addq $16, %rsp
.L23:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
.cfi_escape 0x2e,0
call __printf_chk@PLT
movl $0, %esi
movq -608(%rbp), %rdi
call cudaEventRecord@PLT
movq -608(%rbp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, -588(%rbp)
leaq -588(%rbp), %rdi
movq -608(%rbp), %rdx
movq -616(%rbp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd -588(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC7(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movl $4, %edx
movq -624(%rbp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movl (%rbx), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq -664(%rbp), %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movl $2, %ecx
movq %rbx, %rdx
movq -632(%rbp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movslq -664(%rbp), %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r13
movq 16(%r14), %rdi
movq stdin(%rip), %rdx
leaq .LC9(%rip), %rsi
call freopen@PLT
cmpl $0, -664(%rbp)
jle .L32
movq %r13, %rdi
movl $0, %ebx
leaq _ZSt3cin(%rip), %r14
jmp .L25
.L49:
addl $1, %ebx
movl -664(%rbp), %eax
movq %r15, %rsi
addq $4, %rsi
movq %rsi, %rdi
cmpl %ebx, %eax
jle .L48
.L25:
movq %rdi, %r15
movq %rdi, %rsi
movq %r14, %rdi
call _ZNSirsERi@PLT
jmp .L49
.L48:
testl %eax, %eax
jle .L32
movl $0, %ebx
movl $0, %r15d
movl $1, %eax
leaq .LC10(%rip), %r14
jmp .L27
.L51:
movl %r15d, %eax
addl $1, %eax
movl %eax, %r15d
movl $0, %eax
.L26:
addq $1, %rbx
cmpl %ebx, -664(%rbp)
jle .L50
.L27:
movl (%r12,%rbx,4), %edx
movl 0(%r13,%rbx,4), %ecx
cmpl %ecx, %edx
je .L26
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L51
.L50:
testb %al, %al
jne .L32
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L52
.L32:
leaq .LC11(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L29
.L52:
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl %r15d, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.LEHE3:
.L29:
leaq -576(%rbp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
.L15:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L53
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L34:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq -576(%rbp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L31
call __stack_chk_fail@PLT
.L31:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10859:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA10859:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE10859-.LLSDACSB10859
.LLSDACSB10859:
.uleb128 .LEHB0-.LFB10859
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB10859
.uleb128 .LEHE1-.LEHB1
.uleb128 .L34-.LFB10859
.uleb128 0
.uleb128 .LEHB2-.LFB10859
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB10859
.uleb128 .LEHE3-.LEHB3
.uleb128 .L34-.LFB10859
.uleb128 0
.uleb128 .LEHB4-.LFB10859
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE10859:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "parallel_BFS_edge_parallel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__computePiS_S_S_S_ii # -- Begin function _Z22__device_stub__computePiS_S_S_S_ii
.p2align 4, 0x90
.type _Z22__device_stub__computePiS_S_S_S_ii,@function
_Z22__device_stub__computePiS_S_S_S_ii: # @_Z22__device_stub__computePiS_S_S_S_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computePiS_S_S_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__computePiS_S_S_S_ii, .Lfunc_end0-_Z22__device_stub__computePiS_S_S_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $760, %rsp # imm = 0x2F8
.cfi_def_cfa_offset 816
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
cmpl $1, %edi
jg .LBB1_5
# %bb.1:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rbx
testq %rbx, %rbx
je .LBB1_2
# %bb.3:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq strlen
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_4
.LBB1_5:
.cfi_escape 0x2e, 0x00
leaq 240(%rsp), %r14
movq %r14, %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev
movq 8(%rbx), %rsi
leaq 256(%rsp), %rdi
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $8, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.6: # %.noexc
movq 240(%rsp), %rcx
addq -24(%rcx), %r14
xorl %esi, %esi
testq %rax, %rax
jne .LBB1_8
# %bb.7:
movl 32(%r14), %esi
orl $4, %esi
.LBB1_8: # %.invoke
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp3:
# %bb.9: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
.Ltmp5:
movq %rbx, 80(%rsp) # 8-byte Spill
.cfi_escape 0x2e, 0x00
leaq 240(%rsp), %rdi
leaq 8(%rsp), %rsi
callq _ZNSirsERi
.Ltmp6:
# %bb.10:
.Ltmp7:
.cfi_escape 0x2e, 0x00
leaq 240(%rsp), %rdi
leaq 12(%rsp), %rsi
callq _ZNSirsERi
.Ltmp8:
# %bb.11:
movslq 8(%rsp), %rax
leaq 4(,%rax,4), %rdi
.cfi_escape 0x2e, 0x00
callq malloc
movq %rax, %r12
movslq 12(%rsp), %r14
shlq $3, %r14
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq malloc
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq malloc
movq %rax, %r14
movl 8(%rsp), %eax
testl %eax, %eax
js .LBB1_15
# %bb.12: # %.lr.ph.preheader
movq $-1, %rbx
leaq 240(%rsp), %r13
movq %r12, %rbp
.p2align 4, 0x90
.LBB1_13: # %.lr.ph
# =>This Inner Loop Header: Depth=1
.Ltmp10:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movq %rbp, %rsi
callq _ZNSirsERi
.Ltmp11:
# %bb.14: # in Loop: Header=BB1_13 Depth=1
movslq 8(%rsp), %rax
incq %rbx
addq $4, %rbp
cmpq %rax, %rbx
jl .LBB1_13
.LBB1_15: # %.preheader128
testl %eax, %eax
js .LBB1_20
# %bb.16: # %.lr.ph138.preheader
incl %eax
xorl %ecx, %ecx
jmp .LBB1_17
.p2align 4, 0x90
.LBB1_19: # %.loopexit127
# in Loop: Header=BB1_17 Depth=1
incq %rcx
cmpq %rax, %rcx
je .LBB1_20
.LBB1_17: # %.lr.ph138
# =>This Loop Header: Depth=1
# Child Loop BB1_18 Depth 2
movslq (%r12,%rcx,4), %rdx
movslq 4(%r12,%rcx,4), %rsi
cmpl %esi, %edx
jge .LBB1_19
.p2align 4, 0x90
.LBB1_18: # %.lr.ph134
# Parent Loop BB1_17 Depth=1
# => This Inner Loop Header: Depth=2
movl %ecx, (%r15,%rdx,4)
incq %rdx
cmpq %rdx, %rsi
jne .LBB1_18
jmp .LBB1_19
.LBB1_20: # %.preheader126
cmpl $0, 12(%rsp)
jle .LBB1_24
# %bb.21: # %.lr.ph140.preheader
xorl %ebx, %ebx
leaq 240(%rsp), %r13
movq %r14, %rbp
.p2align 4, 0x90
.LBB1_22: # %.lr.ph140
# =>This Inner Loop Header: Depth=1
.Ltmp13:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movq %rbp, %rsi
callq _ZNSirsERi
.Ltmp14:
# %bb.23: # in Loop: Header=BB1_22 Depth=1
incq %rbx
movslq 12(%rsp), %rax
addq %rax, %rax
addq $4, %rbp
cmpq %rax, %rbx
jl .LBB1_22
.LBB1_24: # %._crit_edge
movslq 8(%rsp), %rax
leaq 4(,%rax,4), %rsi
.Ltmp16:
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rdi
callq hipMalloc
.Ltmp17:
# %bb.25:
movslq 12(%rsp), %rsi
shlq $3, %rsi
.Ltmp18:
.cfi_escape 0x2e, 0x00
leaq 64(%rsp), %rdi
callq hipMalloc
.Ltmp19:
# %bb.26:
movslq 12(%rsp), %rsi
shlq $3, %rsi
.Ltmp20:
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
callq hipMalloc
.Ltmp21:
# %bb.27:
movslq 8(%rsp), %rsi
shlq $2, %rsi
.Ltmp22:
.cfi_escape 0x2e, 0x00
leaq 48(%rsp), %rdi
callq hipMalloc
.Ltmp23:
# %bb.28:
.Ltmp24:
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
movl $4, %esi
callq hipMalloc
.Ltmp25:
# %bb.29:
movq 72(%rsp), %rdi
movslq 8(%rsp), %rax
leaq 4(,%rax,4), %rdx
.Ltmp26:
.cfi_escape 0x2e, 0x00
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp27:
# %bb.30:
movq 64(%rsp), %rdi
movslq 12(%rsp), %rdx
shlq $3, %rdx
.Ltmp28:
.cfi_escape 0x2e, 0x00
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp29:
# %bb.31:
movq 56(%rsp), %rdi
movslq 12(%rsp), %rdx
shlq $3, %rdx
.Ltmp30:
.cfi_escape 0x2e, 0x00
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp31:
# %bb.32:
.Ltmp33:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
callq hipEventCreate
.Ltmp34:
# %bb.33:
.Ltmp35:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
callq hipEventCreate
.Ltmp36:
# %bb.34:
movq 32(%rsp), %rdi
.Ltmp37:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp38:
# %bb.35:
.cfi_escape 0x2e, 0x00
movl $.Lstr, %edi
callq puts@PLT
.Ltmp39:
.cfi_escape 0x2e, 0x00
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $4294968320, %rdx # imm = 0x100000400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp40:
# %bb.36:
testl %eax, %eax
jne .LBB1_39
# %bb.37:
movq 72(%rsp), %rax
movq 64(%rsp), %rcx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
movl 8(%rsp), %r8d
movl 12(%rsp), %r9d
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movq %rsi, 144(%rsp)
movq %rdi, 136(%rsp)
movl %r8d, 28(%rsp)
movl %r9d, 24(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 144(%rsp), %rax
movq %rax, 200(%rsp)
leaq 136(%rsp), %rax
movq %rax, 208(%rsp)
leaq 28(%rsp), %rax
movq %rax, 216(%rsp)
leaq 24(%rsp), %rax
movq %rax, 224(%rsp)
.Ltmp41:
.cfi_escape 0x2e, 0x00
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp42:
# %bb.38: # %.noexc90
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
.Ltmp43:
.cfi_escape 0x2e, 0x10
leaq 176(%rsp), %r9
movl $_Z7computePiS_S_S_S_ii, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp44:
.LBB1_39:
.cfi_escape 0x2e, 0x00
movl $.Lstr.1, %edi
callq puts@PLT
movq 16(%rsp), %rdi
.Ltmp45:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp46:
# %bb.40:
movq 16(%rsp), %rdi
.Ltmp47:
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
.Ltmp48:
# %bb.41:
movl $0, 176(%rsp)
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
.Ltmp50:
.cfi_escape 0x2e, 0x00
leaq 176(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp51:
# %bb.42:
.Ltmp52:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp53:
# %bb.43: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit93
movss 176(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp54:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp55:
# %bb.44: # %_ZNSolsEf.exit
.Ltmp56:
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $.L.str.5, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp57:
# %bb.45: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit96
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB1_46
# %bb.54: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_56
# %bb.55:
movzbl 67(%r15), %eax
jmp .LBB1_58
.LBB1_2:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_4: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_95
.LBB1_56:
.Ltmp58:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp59:
# %bb.57: # %.noexc107
movq (%r15), %rax
.Ltmp60:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp61:
.LBB1_58: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp62:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp63:
# %bb.59: # %.noexc109
.Ltmp64:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp65:
# %bb.60: # %_ZNSolsEPFRSoS_E.exit
.cfi_escape 0x2e, 0x00
movl $4, %edi
callq malloc
movq %rax, %r14
movq 40(%rsp), %rsi
.Ltmp66:
.cfi_escape 0x2e, 0x00
movl $4, %edx
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp67:
# %bb.61:
movl (%r14), %esi
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movslq 8(%rsp), %r15
shlq $2, %r15
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq malloc
movq %rax, %r14
movq 48(%rsp), %rsi
.Ltmp69:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
.Ltmp70:
# %bb.62:
movslq 8(%rsp), %rdi
shlq $2, %rdi
.cfi_escape 0x2e, 0x00
callq malloc
movq %rax, %r15
movq 80(%rsp), %rax # 8-byte Reload
movq 16(%rax), %rdi
movq stdin(%rip), %rdx
.Ltmp72:
.cfi_escape 0x2e, 0x00
movl $.L.str.7, %esi
callq freopen
.Ltmp73:
# %bb.63: # %.preheader125
cmpl $0, 8(%rsp)
jle .LBB1_67
# %bb.64: # %.lr.ph142.preheader
xorl %r12d, %r12d
movq %r15, %rbx
.p2align 4, 0x90
.LBB1_65: # %.lr.ph142
# =>This Inner Loop Header: Depth=1
.Ltmp75:
.cfi_escape 0x2e, 0x00
movl $_ZSt3cin, %edi
movq %rbx, %rsi
callq _ZNSirsERi
.Ltmp76:
# %bb.66: # in Loop: Header=BB1_65 Depth=1
incq %r12
movslq 8(%rsp), %rax
addq $4, %rbx
cmpq %rax, %r12
jl .LBB1_65
.LBB1_67: # %.preheader
cmpl $0, 8(%rsp)
jle .LBB1_68
# %bb.76: # %.lr.ph146.preheader
movb $1, %bpl
xorl %r12d, %r12d
xorl %ebx, %ebx
jmp .LBB1_77
.p2align 4, 0x90
.LBB1_79: # in Loop: Header=BB1_77 Depth=1
incq %r12
movslq 8(%rsp), %rax
cmpq %rax, %r12
jge .LBB1_73
.LBB1_77: # %.lr.ph146
# =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %esi
movl (%r15,%r12,4), %edx
cmpl %edx, %esi
je .LBB1_79
# %bb.78: # in Loop: Header=BB1_77 Depth=1
.cfi_escape 0x2e, 0x00
xorl %ebp, %ebp
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
incl %ebx
jmp .LBB1_79
.LBB1_73: # %._crit_edge147.loopexit
testb $1, %bpl
sete %al
testb %al, %al
je .LBB1_75
.LBB1_81:
.Ltmp78:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp79:
# %bb.82: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit101
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_83
# %bb.85: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i112
cmpb $0, 56(%r14)
je .LBB1_87
# %bb.86:
movzbl 67(%r14), %eax
jmp .LBB1_89
.LBB1_68:
xorl %eax, %eax
xorl %ebx, %ebx
testb %al, %al
jne .LBB1_81
.LBB1_75:
movl $21, %edx
movl $.L.str.9, %esi
movl $_ZSt4cout, %edi
jmp .LBB1_93
.LBB1_87:
.Ltmp80:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp81:
# %bb.88: # %.noexc117
movq (%r14), %rax
.Ltmp82:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp83:
.LBB1_89: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i114
.Ltmp84:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp85:
# %bb.90: # %.noexc119
.Ltmp86:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp87:
# %bb.91: # %_ZNSolsEPFRSoS_E.exit103
.Ltmp88:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
.Ltmp89:
# %bb.92:
movq %rax, %rdi
movl $19, %edx
movl $.L.str.11, %esi
.LBB1_93: # %.invoke167
.Ltmp90:
.cfi_escape 0x2e, 0x00
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp91:
# %bb.94: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit99
.cfi_escape 0x2e, 0x00
leaq 240(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 496(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
.LBB1_95:
xorl %eax, %eax
addq $760, %rsp # imm = 0x2F8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_46:
.cfi_def_cfa_offset 816
.Ltmp95:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp96:
# %bb.53: # %.noexc106
.LBB1_83:
.Ltmp92:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp93:
# %bb.84: # %.noexc116
.LBB1_71:
.Ltmp74:
jmp .LBB1_97
.LBB1_70:
.Ltmp71:
jmp .LBB1_97
.LBB1_69:
.Ltmp68:
jmp .LBB1_97
.LBB1_48:
.Ltmp9:
jmp .LBB1_97
.LBB1_47:
.Ltmp4:
jmp .LBB1_97
.LBB1_80:
.Ltmp94:
jmp .LBB1_97
.LBB1_52:
.Ltmp49:
jmp .LBB1_97
.LBB1_96:
.Ltmp97:
jmp .LBB1_97
.LBB1_51:
.Ltmp32:
jmp .LBB1_97
.LBB1_72:
.Ltmp77:
jmp .LBB1_97
.LBB1_49: # %.loopexit
.Ltmp15:
jmp .LBB1_97
.LBB1_50: # %.loopexit.split-lp
.Ltmp12:
.LBB1_97:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 240(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 496(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp8-.Ltmp5 # Call between .Ltmp5 and .Ltmp8
.uleb128 .Ltmp9-.Lfunc_begin0 # jumps to .Ltmp9
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp11-.Ltmp10 # Call between .Ltmp10 and .Ltmp11
.uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp14-.Ltmp13 # Call between .Ltmp13 and .Ltmp14
.uleb128 .Ltmp15-.Lfunc_begin0 # jumps to .Ltmp15
.byte 0 # On action: cleanup
.uleb128 .Ltmp16-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp31-.Ltmp16 # Call between .Ltmp16 and .Ltmp31
.uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32
.byte 0 # On action: cleanup
.uleb128 .Ltmp33-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp48-.Ltmp33 # Call between .Ltmp33 and .Ltmp48
.uleb128 .Ltmp49-.Lfunc_begin0 # jumps to .Ltmp49
.byte 0 # On action: cleanup
.uleb128 .Ltmp50-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp57-.Ltmp50 # Call between .Ltmp50 and .Ltmp57
.uleb128 .Ltmp97-.Lfunc_begin0 # jumps to .Ltmp97
.byte 0 # On action: cleanup
.uleb128 .Ltmp57-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp58-.Ltmp57 # Call between .Ltmp57 and .Ltmp58
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp58-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp65-.Ltmp58 # Call between .Ltmp58 and .Ltmp65
.uleb128 .Ltmp97-.Lfunc_begin0 # jumps to .Ltmp97
.byte 0 # On action: cleanup
.uleb128 .Ltmp66-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp67-.Ltmp66 # Call between .Ltmp66 and .Ltmp67
.uleb128 .Ltmp68-.Lfunc_begin0 # jumps to .Ltmp68
.byte 0 # On action: cleanup
.uleb128 .Ltmp69-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp70-.Ltmp69 # Call between .Ltmp69 and .Ltmp70
.uleb128 .Ltmp71-.Lfunc_begin0 # jumps to .Ltmp71
.byte 0 # On action: cleanup
.uleb128 .Ltmp72-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp73-.Ltmp72 # Call between .Ltmp72 and .Ltmp73
.uleb128 .Ltmp74-.Lfunc_begin0 # jumps to .Ltmp74
.byte 0 # On action: cleanup
.uleb128 .Ltmp75-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp76-.Ltmp75 # Call between .Ltmp75 and .Ltmp76
.uleb128 .Ltmp77-.Lfunc_begin0 # jumps to .Ltmp77
.byte 0 # On action: cleanup
.uleb128 .Ltmp78-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Ltmp91-.Ltmp78 # Call between .Ltmp78 and .Ltmp91
.uleb128 .Ltmp94-.Lfunc_begin0 # jumps to .Ltmp94
.byte 0 # On action: cleanup
.uleb128 .Ltmp95-.Lfunc_begin0 # >> Call Site 16 <<
.uleb128 .Ltmp96-.Ltmp95 # Call between .Ltmp95 and .Ltmp96
.uleb128 .Ltmp97-.Lfunc_begin0 # jumps to .Ltmp97
.byte 0 # On action: cleanup
.uleb128 .Ltmp92-.Lfunc_begin0 # >> Call Site 17 <<
.uleb128 .Ltmp93-.Ltmp92 # Call between .Ltmp92 and .Ltmp93
.uleb128 .Ltmp94-.Lfunc_begin0 # jumps to .Ltmp94
.byte 0 # On action: cleanup
.uleb128 .Ltmp93-.Lfunc_begin0 # >> Call Site 18 <<
.uleb128 .Lfunc_end1-.Ltmp93 # Call between .Ltmp93 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computePiS_S_S_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computePiS_S_S_S_ii,@object # @_Z7computePiS_S_S_S_ii
.section .rodata,"a",@progbits
.globl _Z7computePiS_S_S_S_ii
.p2align 3, 0x0
_Z7computePiS_S_S_S_ii:
.quad _Z22__device_stub__computePiS_S_S_S_ii
.size _Z7computePiS_S_S_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage: "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " <graph_file_name>\n"
.size .L.str.1, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Compute time in GPU: "
.size .L.str.4, 22
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "ms"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Depth : %d\n"
.size .L.str.6, 12
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "r"
.size .L.str.7, 2
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Found %d, Expected %d\n"
.size .L.str.8, 23
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Solution is correct!\n"
.size .L.str.9, 22
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Solution is incorrect!"
.size .L.str.10, 23
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " testcases failed.\n"
.size .L.str.11, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7computePiS_S_S_S_ii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Starting Computation"
.size .Lstr, 21
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Finished computation"
.size .Lstr.1, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computePiS_S_S_S_ii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z7computePiS_S_S_S_ii
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //Consant memeory 64KB max, 2^16 bytes, 2^14 integers, 16384
#include <stdio.h>
#include <cuda.h>
// size of vectors, has to be known at compile time, max available
#define N 8192
// Constants held in constant memory
__device__ __constant__ int dev_a_Cont[N];
__device__ __constant__ int dev_b_Cont[N];
// regular global memory for comparison
__device__ int dev_a[N];
__device__ int dev_b[N];
// result in device global memory
__device__ int dev_c[N]; //device global memory for result
// kernel routines
__global__ void add_Cont() {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < N){
dev_c[tid] = dev_a_Cont[tid] + dev_b_Cont[tid];
}
}
__global__ void add() {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < N){
dev_c[tid] = dev_a[tid] + dev_b[tid];
}
}
int main() {
// threads per block and blocks per grid
int T = 128, B = 64;
int a[N],b[N],c[N]; //statically declared host vectors
cudaEvent_t start, stop; // cuda events to measure time
float elapsed_time,elapsed_time_Cont;
cudaEventCreate(&start); // timing objects
cudaEventCreate(&stop);
/*----------- GPU not using constant memory ------------------------*/
printf("GPU not using constant memory\n");
for(int i=0;i<N;i++) { // load arrays with some numbers
a[i] = i;
b[i] = i*2;
}
// copy vectors to constant memory
cudaMemcpyToSymbol(dev_a,a,N*sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(dev_b,b,N*sizeof(int),0,cudaMemcpyHostToDevice);
cudaEventRecord(start, 0); // start time
add<<<B,T>>>(); // does not need array ptrs now
cudaThreadSynchronize(); // wait for all threads to complete
cudaEventRecord(stop, 0); // instrument code to measure end time
cudaMemcpyFromSymbol(a,dev_a,N*sizeof(int),0,cudaMemcpyDeviceToHost);
cudaMemcpyFromSymbol(b,dev_b,N*sizeof(int),0,cudaMemcpyDeviceToHost);
cudaMemcpyFromSymbol(c,dev_c,N*sizeof(int),0,cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed_time, start, stop);
printf("Checking results\n");
for(int i=0;i<N;i++) {
if (a[i] + b[i] != c[i]) {
printf("ERROR IN COMPUTATION\n");
break;
}
}
// print out execution time
printf("Time to calculate results: %f ms.\n", elapsed_time);
/*----------- GPU using constant memory ------------------------*/
printf("GPU using constant memory\n");
for(int i=0;i<N;i++) { // load arrays with some numbers
a[i] = i;
b[i] = i*2;
}
// copy vectors to constant memory
cudaMemcpyToSymbol(dev_a_Cont,a,N*sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(dev_b_Cont,b,N*sizeof(int),0,cudaMemcpyHostToDevice);
cudaEventRecord(start, 0); // start time
add_Cont<<<B,T>>>(); // does not need array ptrs now
cudaThreadSynchronize(); // wait for all threads to complete
cudaEventRecord(stop, 0); // instrument code to measure end time
cudaMemcpyFromSymbol(a,dev_a_Cont,N*sizeof(int),0,cudaMemcpyDeviceToHost);
cudaMemcpyFromSymbol(b,dev_b_Cont,N*sizeof(int),0,cudaMemcpyDeviceToHost);
cudaMemcpyFromSymbol(c,dev_c,N*sizeof(int),0,cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed_time_Cont, start, stop);
printf("Checking results\n");
for(int i=0;i<N;i++) {
if (a[i] + b[i] != c[i]) {
printf("ERROR IN COMPUTATION\n");
break;
}
}
// print out execution time
printf("Time to calculate results: %f ms.\n", elapsed_time_Cont);
printf("Speedup using constant memory = %f\n",elapsed_time/elapsed_time_Cont);
/* ----------- clean up, no malloc free needed ---------*/
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | code for sm_80
Function : _Z3addv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0x1fff, PT ; /* 0x00001fff0600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x4][0x8] ; /* 0x0100020006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x4][0x0] ; /* 0x0100000006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x4][0x10] ; /* 0x0100040006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8add_Contv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R2, 0x1fff, PT ; /* 0x00001fff0200780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.WIDE R2, R2, 0x4, RZ ; /* 0x0000000402027825 */
/* 0x000fe200078e02ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0080*/ IADD3 R0, R2.reuse, 0x10000, RZ ; /* 0x0001000002007810 */
/* 0x040fe40007ffe0ff */
/*0090*/ MOV R4, R2 ; /* 0x0000000200047202 */
/* 0x000fe40000000f00 */
/*00a0*/ IADD3 R2, P0, R2, c[0x4][0x10], RZ ; /* 0x0100040002027a10 */
/* 0x000fe40007f1e0ff */
/*00b0*/ LDC R0, c[0x3][R0+-0x8000] ; /* 0x00e0000000007b82 */
/* 0x000e240000000800 */
/*00c0*/ IADD3.X R3, R3, c[0x4][0x14], RZ, P0, !PT ; /* 0x0100050003037a10 */
/* 0x000fcc00007fe4ff */
/*00d0*/ LDC R5, c[0x3][R4] ; /* 0x00c0000004057b82 */
/* 0x000e240000000800 */
/*00e0*/ IMAD.IADD R5, R0, 0x1, R5 ; /* 0x0000000100057824 */
/* 0x001fca00078e0205 */
/*00f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //Consant memeory 64KB max, 2^16 bytes, 2^14 integers, 16384
#include <stdio.h>
#include <cuda.h>
// size of vectors, has to be known at compile time, max available
#define N 8192
// Constants held in constant memory
__device__ __constant__ int dev_a_Cont[N];
__device__ __constant__ int dev_b_Cont[N];
// regular global memory for comparison
__device__ int dev_a[N];
__device__ int dev_b[N];
// result in device global memory
__device__ int dev_c[N]; //device global memory for result
// kernel routines
__global__ void add_Cont() {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < N){
dev_c[tid] = dev_a_Cont[tid] + dev_b_Cont[tid];
}
}
__global__ void add() {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < N){
dev_c[tid] = dev_a[tid] + dev_b[tid];
}
}
int main() {
// threads per block and blocks per grid
int T = 128, B = 64;
int a[N],b[N],c[N]; //statically declared host vectors
cudaEvent_t start, stop; // cuda events to measure time
float elapsed_time,elapsed_time_Cont;
cudaEventCreate(&start); // timing objects
cudaEventCreate(&stop);
/*----------- GPU not using constant memory ------------------------*/
printf("GPU not using constant memory\n");
for(int i=0;i<N;i++) { // load arrays with some numbers
a[i] = i;
b[i] = i*2;
}
// copy vectors to constant memory
cudaMemcpyToSymbol(dev_a,a,N*sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(dev_b,b,N*sizeof(int),0,cudaMemcpyHostToDevice);
cudaEventRecord(start, 0); // start time
add<<<B,T>>>(); // does not need array ptrs now
cudaThreadSynchronize(); // wait for all threads to complete
cudaEventRecord(stop, 0); // instrument code to measure end time
cudaMemcpyFromSymbol(a,dev_a,N*sizeof(int),0,cudaMemcpyDeviceToHost);
cudaMemcpyFromSymbol(b,dev_b,N*sizeof(int),0,cudaMemcpyDeviceToHost);
cudaMemcpyFromSymbol(c,dev_c,N*sizeof(int),0,cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed_time, start, stop);
printf("Checking results\n");
for(int i=0;i<N;i++) {
if (a[i] + b[i] != c[i]) {
printf("ERROR IN COMPUTATION\n");
break;
}
}
// print out execution time
printf("Time to calculate results: %f ms.\n", elapsed_time);
/*----------- GPU using constant memory ------------------------*/
printf("GPU using constant memory\n");
for(int i=0;i<N;i++) { // load arrays with some numbers
a[i] = i;
b[i] = i*2;
}
// copy vectors to constant memory
cudaMemcpyToSymbol(dev_a_Cont,a,N*sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(dev_b_Cont,b,N*sizeof(int),0,cudaMemcpyHostToDevice);
cudaEventRecord(start, 0); // start time
add_Cont<<<B,T>>>(); // does not need array ptrs now
cudaThreadSynchronize(); // wait for all threads to complete
cudaEventRecord(stop, 0); // instrument code to measure end time
cudaMemcpyFromSymbol(a,dev_a_Cont,N*sizeof(int),0,cudaMemcpyDeviceToHost);
cudaMemcpyFromSymbol(b,dev_b_Cont,N*sizeof(int),0,cudaMemcpyDeviceToHost);
cudaMemcpyFromSymbol(c,dev_c,N*sizeof(int),0,cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed_time_Cont, start, stop);
printf("Checking results\n");
for(int i=0;i<N;i++) {
if (a[i] + b[i] != c[i]) {
printf("ERROR IN COMPUTATION\n");
break;
}
}
// print out execution time
printf("Time to calculate results: %f ms.\n", elapsed_time_Cont);
printf("Speedup using constant memory = %f\n",elapsed_time/elapsed_time_Cont);
/* ----------- clean up, no malloc free needed ---------*/
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | .file "tmpxft_000cf00b_00000000-6_constantMemory.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8add_Contvv
.type _Z26__device_stub__Z8add_Contvv, @function
_Z26__device_stub__Z8add_Contvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8add_Contv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z8add_Contvv, .-_Z26__device_stub__Z8add_Contvv
.globl _Z8add_Contv
.type _Z8add_Contv, @function
_Z8add_Contv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8add_Contvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8add_Contv, .-_Z8add_Contv
.globl _Z21__device_stub__Z3addvv
.type _Z21__device_stub__Z3addvv, @function
_Z21__device_stub__Z3addvv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z3addv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z21__device_stub__Z3addvv, .-_Z21__device_stub__Z3addvv
.globl _Z3addv
.type _Z3addv, @function
_Z3addv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z21__device_stub__Z3addvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z3addv, .-_Z3addv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "GPU not using constant memory\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Checking results\n"
.LC2:
.string "ERROR IN COMPUTATION\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "Time to calculate results: %f ms.\n"
.section .rodata.str1.1
.LC4:
.string "GPU using constant memory\n"
.section .rodata.str1.8
.align 8
.LC5:
.string "Speedup using constant memory = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
leaq -98304(%rsp), %r11
.cfi_def_cfa 11, 98312
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $72, %rsp
.cfi_def_cfa_offset 98384
movq %fs:40, %rax
movq %rax, 98360(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L20:
movl %eax, 48(%rsp,%rax,4)
leal (%rax,%rax), %edx
movl %edx, 32816(%rsp,%rax,4)
addq $1, %rax
cmpq $8192, %rax
jne .L20
leaq 48(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $32768, %edx
leaq _ZL5dev_a(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 32816(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $32768, %edx
leaq _ZL5dev_b(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $128, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $64, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L21:
call cudaThreadSynchronize@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
leaq 48(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $32768, %edx
leaq _ZL5dev_a(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
leaq 32816(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $32768, %edx
leaq _ZL5dev_b(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
leaq 65584(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $32768, %edx
leaq _ZL5dev_c(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
leaq 65584(%rsp), %rcx
.L24:
movl 32816(%rsp,%rax), %edx
addl 48(%rsp,%rax), %edx
cmpl (%rax,%rcx), %edx
jne .L37
addq $4, %rax
cmpq $32768, %rax
jne .L24
jmp .L23
.L36:
call _Z21__device_stub__Z3addvv
jmp .L21
.L37:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L23:
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L25:
movl %eax, 48(%rsp,%rax,4)
leal (%rax,%rax), %edx
movl %edx, 32816(%rsp,%rax,4)
addq $1, %rax
cmpq $8192, %rax
jne .L25
leaq 48(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $32768, %edx
leaq _ZL10dev_a_Cont(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 32816(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $32768, %edx
leaq _ZL10dev_b_Cont(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $128, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $64, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L26:
call cudaThreadSynchronize@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
leaq 48(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $32768, %edx
leaq _ZL10dev_a_Cont(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
leaq 32816(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $32768, %edx
leaq _ZL10dev_b_Cont(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
leaq 65584(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $32768, %edx
leaq _ZL5dev_c(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 36(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
leaq 65584(%rsp), %rcx
.L29:
movl 32816(%rsp,%rax), %edx
addl 48(%rsp,%rax), %edx
cmpl (%rax,%rcx), %edx
jne .L39
addq $4, %rax
cmpq $32768, %rax
jne .L29
jmp .L28
.L38:
call _Z26__device_stub__Z8add_Contvv
jmp .L26
.L39:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L28:
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 4(%rsp), %xmm0
divss 36(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 98360(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $98376, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3addv"
.LC7:
.string "_Z8add_Contv"
.LC8:
.string "dev_a_Cont"
.LC9:
.string "dev_b_Cont"
.LC10:
.string "dev_a"
.LC11:
.string "dev_b"
.LC12:
.string "dev_c"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z8add_Contv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $32768, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10dev_a_Cont(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $32768, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10dev_b_Cont(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $32768, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5dev_a(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $32768, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5dev_b(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $32768, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5dev_c(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL5dev_c
.comm _ZL5dev_c,32768,32
.local _ZL5dev_b
.comm _ZL5dev_b,32768,32
.local _ZL5dev_a
.comm _ZL5dev_a,32768,32
.local _ZL10dev_b_Cont
.comm _ZL10dev_b_Cont,32768,32
.local _ZL10dev_a_Cont
.comm _ZL10dev_a_Cont,32768,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //Consant memeory 64KB max, 2^16 bytes, 2^14 integers, 16384
#include <stdio.h>
#include <cuda.h>
// size of vectors, has to be known at compile time, max available
#define N 8192
// Constants held in constant memory
__device__ __constant__ int dev_a_Cont[N];
__device__ __constant__ int dev_b_Cont[N];
// regular global memory for comparison
__device__ int dev_a[N];
__device__ int dev_b[N];
// result in device global memory
__device__ int dev_c[N]; //device global memory for result
// kernel routines
__global__ void add_Cont() {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < N){
dev_c[tid] = dev_a_Cont[tid] + dev_b_Cont[tid];
}
}
__global__ void add() {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < N){
dev_c[tid] = dev_a[tid] + dev_b[tid];
}
}
int main() {
// threads per block and blocks per grid
int T = 128, B = 64;
int a[N],b[N],c[N]; //statically declared host vectors
cudaEvent_t start, stop; // cuda events to measure time
float elapsed_time,elapsed_time_Cont;
cudaEventCreate(&start); // timing objects
cudaEventCreate(&stop);
/*----------- GPU not using constant memory ------------------------*/
printf("GPU not using constant memory\n");
for(int i=0;i<N;i++) { // load arrays with some numbers
a[i] = i;
b[i] = i*2;
}
// copy vectors to constant memory
cudaMemcpyToSymbol(dev_a,a,N*sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(dev_b,b,N*sizeof(int),0,cudaMemcpyHostToDevice);
cudaEventRecord(start, 0); // start time
add<<<B,T>>>(); // does not need array ptrs now
cudaThreadSynchronize(); // wait for all threads to complete
cudaEventRecord(stop, 0); // instrument code to measure end time
cudaMemcpyFromSymbol(a,dev_a,N*sizeof(int),0,cudaMemcpyDeviceToHost);
cudaMemcpyFromSymbol(b,dev_b,N*sizeof(int),0,cudaMemcpyDeviceToHost);
cudaMemcpyFromSymbol(c,dev_c,N*sizeof(int),0,cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed_time, start, stop);
printf("Checking results\n");
for(int i=0;i<N;i++) {
if (a[i] + b[i] != c[i]) {
printf("ERROR IN COMPUTATION\n");
break;
}
}
// print out execution time
printf("Time to calculate results: %f ms.\n", elapsed_time);
/*----------- GPU using constant memory ------------------------*/
printf("GPU using constant memory\n");
for(int i=0;i<N;i++) { // load arrays with some numbers
a[i] = i;
b[i] = i*2;
}
// copy vectors to constant memory
cudaMemcpyToSymbol(dev_a_Cont,a,N*sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(dev_b_Cont,b,N*sizeof(int),0,cudaMemcpyHostToDevice);
cudaEventRecord(start, 0); // start time
add_Cont<<<B,T>>>(); // does not need array ptrs now
cudaThreadSynchronize(); // wait for all threads to complete
cudaEventRecord(stop, 0); // instrument code to measure end time
cudaMemcpyFromSymbol(a,dev_a_Cont,N*sizeof(int),0,cudaMemcpyDeviceToHost);
cudaMemcpyFromSymbol(b,dev_b_Cont,N*sizeof(int),0,cudaMemcpyDeviceToHost);
cudaMemcpyFromSymbol(c,dev_c,N*sizeof(int),0,cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed_time_Cont, start, stop);
printf("Checking results\n");
for(int i=0;i<N;i++) {
if (a[i] + b[i] != c[i]) {
printf("ERROR IN COMPUTATION\n");
break;
}
}
// print out execution time
printf("Time to calculate results: %f ms.\n", elapsed_time_Cont);
printf("Speedup using constant memory = %f\n",elapsed_time/elapsed_time_Cont);
/* ----------- clean up, no malloc free needed ---------*/
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | //Consant memeory 64KB max, 2^16 bytes, 2^14 integers, 16384
#include <stdio.h>
#include <hip/hip_runtime.h>
// size of vectors, has to be known at compile time, max available
#define N 8192
// Constants held in constant memory
__device__ __constant__ int dev_a_Cont[N];
__device__ __constant__ int dev_b_Cont[N];
// regular global memory for comparison
__device__ int dev_a[N];
__device__ int dev_b[N];
// result in device global memory
__device__ int dev_c[N]; //device global memory for result
// kernel routines
__global__ void add_Cont() {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < N){
dev_c[tid] = dev_a_Cont[tid] + dev_b_Cont[tid];
}
}
__global__ void add() {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < N){
dev_c[tid] = dev_a[tid] + dev_b[tid];
}
}
int main() {
// threads per block and blocks per grid
int T = 128, B = 64;
int a[N],b[N],c[N]; //statically declared host vectors
hipEvent_t start, stop; // cuda events to measure time
float elapsed_time,elapsed_time_Cont;
hipEventCreate(&start); // timing objects
hipEventCreate(&stop);
/*----------- GPU not using constant memory ------------------------*/
printf("GPU not using constant memory\n");
for(int i=0;i<N;i++) { // load arrays with some numbers
a[i] = i;
b[i] = i*2;
}
// copy vectors to constant memory
hipMemcpyToSymbol(HIP_SYMBOL(dev_a),a,N*sizeof(int),0,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(dev_b),b,N*sizeof(int),0,hipMemcpyHostToDevice);
hipEventRecord(start, 0); // start time
add<<<B,T>>>(); // does not need array ptrs now
hipDeviceSynchronize(); // wait for all threads to complete
hipEventRecord(stop, 0); // instrument code to measure end time
hipMemcpyFromSymbol(a,HIP_SYMBOL(dev_a),N*sizeof(int),0,hipMemcpyDeviceToHost);
hipMemcpyFromSymbol(b,HIP_SYMBOL(dev_b),N*sizeof(int),0,hipMemcpyDeviceToHost);
hipMemcpyFromSymbol(c,HIP_SYMBOL(dev_c),N*sizeof(int),0,hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed_time, start, stop);
printf("Checking results\n");
for(int i=0;i<N;i++) {
if (a[i] + b[i] != c[i]) {
printf("ERROR IN COMPUTATION\n");
break;
}
}
// print out execution time
printf("Time to calculate results: %f ms.\n", elapsed_time);
/*----------- GPU using constant memory ------------------------*/
printf("GPU using constant memory\n");
for(int i=0;i<N;i++) { // load arrays with some numbers
a[i] = i;
b[i] = i*2;
}
// copy vectors to constant memory
hipMemcpyToSymbol(HIP_SYMBOL(dev_a_Cont),a,N*sizeof(int),0,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(dev_b_Cont),b,N*sizeof(int),0,hipMemcpyHostToDevice);
hipEventRecord(start, 0); // start time
add_Cont<<<B,T>>>(); // does not need array ptrs now
hipDeviceSynchronize(); // wait for all threads to complete
hipEventRecord(stop, 0); // instrument code to measure end time
hipMemcpyFromSymbol(a,HIP_SYMBOL(dev_a_Cont),N*sizeof(int),0,hipMemcpyDeviceToHost);
hipMemcpyFromSymbol(b,HIP_SYMBOL(dev_b_Cont),N*sizeof(int),0,hipMemcpyDeviceToHost);
hipMemcpyFromSymbol(c,HIP_SYMBOL(dev_c),N*sizeof(int),0,hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed_time_Cont, start, stop);
printf("Checking results\n");
for(int i=0;i<N;i++) {
if (a[i] + b[i] != c[i]) {
printf("ERROR IN COMPUTATION\n");
break;
}
}
// print out execution time
printf("Time to calculate results: %f ms.\n", elapsed_time_Cont);
printf("Speedup using constant memory = %f\n",elapsed_time/elapsed_time_Cont);
/* ----------- clean up, no malloc free needed ---------*/
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //Consant memeory 64KB max, 2^16 bytes, 2^14 integers, 16384
#include <stdio.h>
#include <hip/hip_runtime.h>
// size of vectors, has to be known at compile time, max available
#define N 8192
// Constants held in constant memory
__device__ __constant__ int dev_a_Cont[N];
__device__ __constant__ int dev_b_Cont[N];
// regular global memory for comparison
__device__ int dev_a[N];
__device__ int dev_b[N];
// result in device global memory
__device__ int dev_c[N]; //device global memory for result
// kernel routines
__global__ void add_Cont() {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < N){
dev_c[tid] = dev_a_Cont[tid] + dev_b_Cont[tid];
}
}
__global__ void add() {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < N){
dev_c[tid] = dev_a[tid] + dev_b[tid];
}
}
int main() {
// threads per block and blocks per grid
int T = 128, B = 64;
int a[N],b[N],c[N]; //statically declared host vectors
hipEvent_t start, stop; // cuda events to measure time
float elapsed_time,elapsed_time_Cont;
hipEventCreate(&start); // timing objects
hipEventCreate(&stop);
/*----------- GPU not using constant memory ------------------------*/
printf("GPU not using constant memory\n");
for(int i=0;i<N;i++) { // load arrays with some numbers
a[i] = i;
b[i] = i*2;
}
// copy vectors to constant memory
hipMemcpyToSymbol(HIP_SYMBOL(dev_a),a,N*sizeof(int),0,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(dev_b),b,N*sizeof(int),0,hipMemcpyHostToDevice);
hipEventRecord(start, 0); // start time
add<<<B,T>>>(); // does not need array ptrs now
hipDeviceSynchronize(); // wait for all threads to complete
hipEventRecord(stop, 0); // instrument code to measure end time
hipMemcpyFromSymbol(a,HIP_SYMBOL(dev_a),N*sizeof(int),0,hipMemcpyDeviceToHost);
hipMemcpyFromSymbol(b,HIP_SYMBOL(dev_b),N*sizeof(int),0,hipMemcpyDeviceToHost);
hipMemcpyFromSymbol(c,HIP_SYMBOL(dev_c),N*sizeof(int),0,hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed_time, start, stop);
printf("Checking results\n");
for(int i=0;i<N;i++) {
if (a[i] + b[i] != c[i]) {
printf("ERROR IN COMPUTATION\n");
break;
}
}
// print out execution time
printf("Time to calculate results: %f ms.\n", elapsed_time);
/*----------- GPU using constant memory ------------------------*/
printf("GPU using constant memory\n");
for(int i=0;i<N;i++) { // load arrays with some numbers
a[i] = i;
b[i] = i*2;
}
// copy vectors to constant memory
hipMemcpyToSymbol(HIP_SYMBOL(dev_a_Cont),a,N*sizeof(int),0,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(dev_b_Cont),b,N*sizeof(int),0,hipMemcpyHostToDevice);
hipEventRecord(start, 0); // start time
add_Cont<<<B,T>>>(); // does not need array ptrs now
hipDeviceSynchronize(); // wait for all threads to complete
hipEventRecord(stop, 0); // instrument code to measure end time
hipMemcpyFromSymbol(a,HIP_SYMBOL(dev_a_Cont),N*sizeof(int),0,hipMemcpyDeviceToHost);
hipMemcpyFromSymbol(b,HIP_SYMBOL(dev_b_Cont),N*sizeof(int),0,hipMemcpyDeviceToHost);
hipMemcpyFromSymbol(c,HIP_SYMBOL(dev_c),N*sizeof(int),0,hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed_time_Cont, start, stop);
printf("Checking results\n");
for(int i=0;i<N;i++) {
if (a[i] + b[i] != c[i]) {
printf("ERROR IN COMPUTATION\n");
break;
}
}
// print out execution time
printf("Time to calculate results: %f ms.\n", elapsed_time_Cont);
printf("Speedup using constant memory = %f\n",elapsed_time/elapsed_time_Cont);
/* ----------- clean up, no malloc free needed ---------*/
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8add_Contv
.globl _Z8add_Contv
.p2align 8
.type _Z8add_Contv,@function
_Z8add_Contv:
s_load_b32 s0, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s0, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_mov_b32 s0, exec_lo
v_cmpx_gt_i32_e32 0x2000, v1
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, dev_a_Cont@rel32@lo+4
s_addc_u32 s1, s1, dev_a_Cont@rel32@hi+12
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, dev_b_Cont@rel32@lo+4
s_addc_u32 s3, s3, dev_b_Cont@rel32@hi+12
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v0, s0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, v0, s2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, dev_c@rel32@lo+4
s_addc_u32 s1, s1, dev_c@rel32@hi+12
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_u32 v0, vcc_lo, v0, s0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8add_Contv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8add_Contv, .Lfunc_end0-_Z8add_Contv
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3addv
.globl _Z3addv
.p2align 8
.type _Z3addv,@function
_Z3addv:
s_load_b32 s0, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s0, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_mov_b32 s0, exec_lo
v_cmpx_gt_i32_e32 0x2000, v1
s_cbranch_execz .LBB1_2
v_ashrrev_i32_e32 v2, 31, v1
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, dev_a@rel32@lo+4
s_addc_u32 s1, s1, dev_a@rel32@hi+12
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, dev_b@rel32@lo+4
s_addc_u32 s3, s3, dev_b@rel32@hi+12
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v0, s0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, v0, s2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, dev_c@rel32@lo+4
s_addc_u32 s1, s1, dev_c@rel32@hi+12
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_u32 v0, vcc_lo, v0, s0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3addv, .Lfunc_end1-_Z3addv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected dev_a_Cont
.type dev_a_Cont,@object
.section .bss,"aw",@nobits
.globl dev_a_Cont
.p2align 4, 0x0
dev_a_Cont:
.zero 32768
.size dev_a_Cont, 32768
.protected dev_b_Cont
.type dev_b_Cont,@object
.globl dev_b_Cont
.p2align 4, 0x0
dev_b_Cont:
.zero 32768
.size dev_b_Cont, 32768
.protected dev_a
.type dev_a,@object
.globl dev_a
.p2align 4, 0x0
dev_a:
.zero 32768
.size dev_a, 32768
.protected dev_b
.type dev_b,@object
.globl dev_b
.p2align 4, 0x0
dev_b:
.zero 32768
.size dev_b, 32768
.protected dev_c
.type dev_c,@object
.globl dev_c
.p2align 4, 0x0
dev_c:
.zero 32768
.size dev_c, 32768
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym dev_a_Cont
.addrsig_sym dev_b_Cont
.addrsig_sym dev_a
.addrsig_sym dev_b
.addrsig_sym dev_c
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8add_Contv
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8add_Contv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addv
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //Consant memeory 64KB max, 2^16 bytes, 2^14 integers, 16384
#include <stdio.h>
#include <hip/hip_runtime.h>
// size of vectors, has to be known at compile time, max available
#define N 8192
// Constants held in constant memory
__device__ __constant__ int dev_a_Cont[N];
__device__ __constant__ int dev_b_Cont[N];
// regular global memory for comparison
__device__ int dev_a[N];
__device__ int dev_b[N];
// result in device global memory
__device__ int dev_c[N]; //device global memory for result
// kernel routines
__global__ void add_Cont() {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < N){
dev_c[tid] = dev_a_Cont[tid] + dev_b_Cont[tid];
}
}
__global__ void add() {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < N){
dev_c[tid] = dev_a[tid] + dev_b[tid];
}
}
int main() {
// threads per block and blocks per grid
int T = 128, B = 64;
int a[N],b[N],c[N]; //statically declared host vectors
hipEvent_t start, stop; // cuda events to measure time
float elapsed_time,elapsed_time_Cont;
hipEventCreate(&start); // timing objects
hipEventCreate(&stop);
/*----------- GPU not using constant memory ------------------------*/
printf("GPU not using constant memory\n");
for(int i=0;i<N;i++) { // load arrays with some numbers
a[i] = i;
b[i] = i*2;
}
// copy vectors to constant memory
hipMemcpyToSymbol(HIP_SYMBOL(dev_a),a,N*sizeof(int),0,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(dev_b),b,N*sizeof(int),0,hipMemcpyHostToDevice);
hipEventRecord(start, 0); // start time
add<<<B,T>>>(); // does not need array ptrs now
hipDeviceSynchronize(); // wait for all threads to complete
hipEventRecord(stop, 0); // instrument code to measure end time
hipMemcpyFromSymbol(a,HIP_SYMBOL(dev_a),N*sizeof(int),0,hipMemcpyDeviceToHost);
hipMemcpyFromSymbol(b,HIP_SYMBOL(dev_b),N*sizeof(int),0,hipMemcpyDeviceToHost);
hipMemcpyFromSymbol(c,HIP_SYMBOL(dev_c),N*sizeof(int),0,hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed_time, start, stop);
printf("Checking results\n");
for(int i=0;i<N;i++) {
if (a[i] + b[i] != c[i]) {
printf("ERROR IN COMPUTATION\n");
break;
}
}
// print out execution time
printf("Time to calculate results: %f ms.\n", elapsed_time);
/*----------- GPU using constant memory ------------------------*/
printf("GPU using constant memory\n");
for(int i=0;i<N;i++) { // load arrays with some numbers
a[i] = i;
b[i] = i*2;
}
// copy vectors to constant memory
hipMemcpyToSymbol(HIP_SYMBOL(dev_a_Cont),a,N*sizeof(int),0,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(dev_b_Cont),b,N*sizeof(int),0,hipMemcpyHostToDevice);
hipEventRecord(start, 0); // start time
add_Cont<<<B,T>>>(); // does not need array ptrs now
hipDeviceSynchronize(); // wait for all threads to complete
hipEventRecord(stop, 0); // instrument code to measure end time
hipMemcpyFromSymbol(a,HIP_SYMBOL(dev_a_Cont),N*sizeof(int),0,hipMemcpyDeviceToHost);
hipMemcpyFromSymbol(b,HIP_SYMBOL(dev_b_Cont),N*sizeof(int),0,hipMemcpyDeviceToHost);
hipMemcpyFromSymbol(c,HIP_SYMBOL(dev_c),N*sizeof(int),0,hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed_time_Cont, start, stop);
printf("Checking results\n");
for(int i=0;i<N;i++) {
if (a[i] + b[i] != c[i]) {
printf("ERROR IN COMPUTATION\n");
break;
}
}
// print out execution time
printf("Time to calculate results: %f ms.\n", elapsed_time_Cont);
printf("Speedup using constant memory = %f\n",elapsed_time/elapsed_time_Cont);
/* ----------- clean up, no malloc free needed ---------*/
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
} | .text
.file "constantMemory.hip"
.globl _Z23__device_stub__add_Contv # -- Begin function _Z23__device_stub__add_Contv
.p2align 4, 0x90
.type _Z23__device_stub__add_Contv,@function
_Z23__device_stub__add_Contv: # @_Z23__device_stub__add_Contv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8add_Contv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__add_Contv, .Lfunc_end0-_Z23__device_stub__add_Contv
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addv # -- Begin function _Z18__device_stub__addv
.p2align 4, 0x90
.type _Z18__device_stub__addv,@function
_Z18__device_stub__addv: # @_Z18__device_stub__addv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z3addv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z18__device_stub__addv, .Lfunc_end1-_Z18__device_stub__addv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $98400, %rsp # imm = 0x18060
.cfi_def_cfa_offset 98432
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %ecx, 32864(%rsp,%rcx,4)
movl %eax, 96(%rsp,%rcx,4)
incq %rcx
addl $2, %eax
cmpq $8192, %rcx # imm = 0x2000
jne .LBB2_1
# %bb.2:
movabsq $4294967360, %rbx # imm = 0x100000040
leaq 32864(%rsp), %rsi
movl $dev_a, %edi
movl $32768, %edx # imm = 0x8000
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 96(%rsp), %rsi
movl $dev_b, %edi
movl $32768, %edx # imm = 0x8000
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 64(%rbx), %r14
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
leaq 65632(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 65632(%rsp), %rsi
movl 65640(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addv, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movq 8(%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
leaq 32864(%rsp), %rdi
movl $dev_a, %esi
movl $32768, %edx # imm = 0x8000
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
leaq 96(%rsp), %rdi
movl $dev_b, %esi
movl $32768, %edx # imm = 0x8000
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
leaq 65632(%rsp), %rdi
movl $dev_c, %esi
movl $32768, %edx # imm = 0x8000
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 36(%rsp), %rdi
callq hipEventElapsedTime
movl $.Lstr.4, %edi
callq puts@PLT
.p2align 4, 0x90
.LBB2_6: # =>This Inner Loop Header: Depth=1
movl 96(%rsp,%r15,4), %eax
addl 32864(%rsp,%r15,4), %eax
cmpl 65632(%rsp,%r15,4), %eax
jne .LBB2_7
# %bb.5: # in Loop: Header=BB2_6 Depth=1
incq %r15
cmpq $8192, %r15 # imm = 0x2000
jne .LBB2_6
jmp .LBB2_8
.LBB2_7:
movl $.Lstr.5, %edi
callq puts@PLT
.LBB2_8: # %.loopexit59
movss 36(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movl $.Lstr.3, %edi
callq puts@PLT
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_9: # =>This Inner Loop Header: Depth=1
movl %ecx, 32864(%rsp,%rcx,4)
movl %eax, 96(%rsp,%rcx,4)
incq %rcx
addl $2, %eax
cmpq $8192, %rcx # imm = 0x2000
jne .LBB2_9
# %bb.10:
leaq 32864(%rsp), %rsi
movl $dev_a_Cont, %edi
movl $32768, %edx # imm = 0x8000
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 96(%rsp), %rsi
movl $dev_b_Cont, %edi
movl $32768, %edx # imm = 0x8000
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_12
# %bb.11:
leaq 24(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8add_Contv, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_12:
callq hipDeviceSynchronize
movq 8(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
leaq 32864(%rsp), %rdi
movl $dev_a_Cont, %esi
movl $32768, %edx # imm = 0x8000
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
leaq 96(%rsp), %rdi
movl $dev_b_Cont, %esi
movl $32768, %edx # imm = 0x8000
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
leaq 65632(%rsp), %rdi
movl $dev_c, %esi
movl $32768, %edx # imm = 0x8000
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 24(%rsp), %rdi
callq hipEventElapsedTime
movl $.Lstr.4, %edi
callq puts@PLT
.p2align 4, 0x90
.LBB2_14: # =>This Inner Loop Header: Depth=1
movl 96(%rsp,%rbx,4), %eax
addl 32864(%rsp,%rbx,4), %eax
cmpl 65632(%rsp,%rbx,4), %eax
jne .LBB2_15
# %bb.13: # in Loop: Header=BB2_14 Depth=1
incq %rbx
cmpq $8192, %rbx # imm = 0x2000
jne .LBB2_14
jmp .LBB2_16
.LBB2_15:
movl $.Lstr.5, %edi
callq puts@PLT
.LBB2_16: # %.loopexit
movss 24(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movss 36(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 24(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $98400, %rsp # imm = 0x18060
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8add_Contv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addv, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $dev_a_Cont, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $32768, %r9d # imm = 0x8000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $dev_b_Cont, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $32768, %r9d # imm = 0x8000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $dev_a, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $32768, %r9d # imm = 0x8000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $dev_b, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movl $32768, %r9d # imm = 0x8000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $dev_c, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movl $32768, %r9d # imm = 0x8000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type dev_a_Cont,@object # @dev_a_Cont
.local dev_a_Cont
.comm dev_a_Cont,32768,16
.type dev_b_Cont,@object # @dev_b_Cont
.local dev_b_Cont
.comm dev_b_Cont,32768,16
.type dev_a,@object # @dev_a
.local dev_a
.comm dev_a,32768,16
.type dev_b,@object # @dev_b
.local dev_b
.comm dev_b,32768,16
.type dev_c,@object # @dev_c
.local dev_c
.comm dev_c,32768,16
.type _Z8add_Contv,@object # @_Z8add_Contv
.section .rodata,"a",@progbits
.globl _Z8add_Contv
.p2align 3, 0x0
_Z8add_Contv:
.quad _Z23__device_stub__add_Contv
.size _Z8add_Contv, 8
.type _Z3addv,@object # @_Z3addv
.globl _Z3addv
.p2align 3, 0x0
_Z3addv:
.quad _Z18__device_stub__addv
.size _Z3addv, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "Time to calculate results: %f ms.\n"
.size .L.str.3, 35
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Speedup using constant memory = %f\n"
.size .L.str.5, 36
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8add_Contv"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3addv"
.size .L__unnamed_2, 8
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "dev_a_Cont"
.size .L__unnamed_3, 11
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "dev_b_Cont"
.size .L__unnamed_4, 11
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "dev_a"
.size .L__unnamed_5, 6
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "dev_b"
.size .L__unnamed_6, 6
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "dev_c"
.size .L__unnamed_7, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "GPU not using constant memory"
.size .Lstr, 30
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "GPU using constant memory"
.size .Lstr.3, 26
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Checking results"
.size .Lstr.4, 17
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "ERROR IN COMPUTATION"
.size .Lstr.5, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__add_Contv
.addrsig_sym _Z18__device_stub__addv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym dev_a_Cont
.addrsig_sym dev_b_Cont
.addrsig_sym dev_a
.addrsig_sym dev_b
.addrsig_sym dev_c
.addrsig_sym _Z8add_Contv
.addrsig_sym _Z3addv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0x1fff, PT ; /* 0x00001fff0600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x4][0x8] ; /* 0x0100020006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x4][0x0] ; /* 0x0100000006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x4][0x10] ; /* 0x0100040006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8add_Contv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R2, 0x1fff, PT ; /* 0x00001fff0200780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.WIDE R2, R2, 0x4, RZ ; /* 0x0000000402027825 */
/* 0x000fe200078e02ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0080*/ IADD3 R0, R2.reuse, 0x10000, RZ ; /* 0x0001000002007810 */
/* 0x040fe40007ffe0ff */
/*0090*/ MOV R4, R2 ; /* 0x0000000200047202 */
/* 0x000fe40000000f00 */
/*00a0*/ IADD3 R2, P0, R2, c[0x4][0x10], RZ ; /* 0x0100040002027a10 */
/* 0x000fe40007f1e0ff */
/*00b0*/ LDC R0, c[0x3][R0+-0x8000] ; /* 0x00e0000000007b82 */
/* 0x000e240000000800 */
/*00c0*/ IADD3.X R3, R3, c[0x4][0x14], RZ, P0, !PT ; /* 0x0100050003037a10 */
/* 0x000fcc00007fe4ff */
/*00d0*/ LDC R5, c[0x3][R4] ; /* 0x00c0000004057b82 */
/* 0x000e240000000800 */
/*00e0*/ IMAD.IADD R5, R0, 0x1, R5 ; /* 0x0000000100057824 */
/* 0x001fca00078e0205 */
/*00f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8add_Contv
.globl _Z8add_Contv
.p2align 8
.type _Z8add_Contv,@function
_Z8add_Contv:
s_load_b32 s0, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s0, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_mov_b32 s0, exec_lo
v_cmpx_gt_i32_e32 0x2000, v1
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, dev_a_Cont@rel32@lo+4
s_addc_u32 s1, s1, dev_a_Cont@rel32@hi+12
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, dev_b_Cont@rel32@lo+4
s_addc_u32 s3, s3, dev_b_Cont@rel32@hi+12
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v0, s0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, v0, s2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, dev_c@rel32@lo+4
s_addc_u32 s1, s1, dev_c@rel32@hi+12
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_u32 v0, vcc_lo, v0, s0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8add_Contv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8add_Contv, .Lfunc_end0-_Z8add_Contv
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3addv
.globl _Z3addv
.p2align 8
.type _Z3addv,@function
_Z3addv:
s_load_b32 s0, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s0, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_mov_b32 s0, exec_lo
v_cmpx_gt_i32_e32 0x2000, v1
s_cbranch_execz .LBB1_2
v_ashrrev_i32_e32 v2, 31, v1
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, dev_a@rel32@lo+4
s_addc_u32 s1, s1, dev_a@rel32@hi+12
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, dev_b@rel32@lo+4
s_addc_u32 s3, s3, dev_b@rel32@hi+12
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v0, s0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, v0, s2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, dev_c@rel32@lo+4
s_addc_u32 s1, s1, dev_c@rel32@hi+12
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_u32 v0, vcc_lo, v0, s0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3addv, .Lfunc_end1-_Z3addv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected dev_a_Cont
.type dev_a_Cont,@object
.section .bss,"aw",@nobits
.globl dev_a_Cont
.p2align 4, 0x0
dev_a_Cont:
.zero 32768
.size dev_a_Cont, 32768
.protected dev_b_Cont
.type dev_b_Cont,@object
.globl dev_b_Cont
.p2align 4, 0x0
dev_b_Cont:
.zero 32768
.size dev_b_Cont, 32768
.protected dev_a
.type dev_a,@object
.globl dev_a
.p2align 4, 0x0
dev_a:
.zero 32768
.size dev_a, 32768
.protected dev_b
.type dev_b,@object
.globl dev_b
.p2align 4, 0x0
dev_b:
.zero 32768
.size dev_b, 32768
.protected dev_c
.type dev_c,@object
.globl dev_c
.p2align 4, 0x0
dev_c:
.zero 32768
.size dev_c, 32768
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym dev_a_Cont
.addrsig_sym dev_b_Cont
.addrsig_sym dev_a
.addrsig_sym dev_b
.addrsig_sym dev_c
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8add_Contv
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8add_Contv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addv
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000cf00b_00000000-6_constantMemory.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8add_Contvv
.type _Z26__device_stub__Z8add_Contvv, @function
_Z26__device_stub__Z8add_Contvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8add_Contv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z8add_Contvv, .-_Z26__device_stub__Z8add_Contvv
.globl _Z8add_Contv
.type _Z8add_Contv, @function
_Z8add_Contv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8add_Contvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8add_Contv, .-_Z8add_Contv
.globl _Z21__device_stub__Z3addvv
.type _Z21__device_stub__Z3addvv, @function
_Z21__device_stub__Z3addvv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z3addv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z21__device_stub__Z3addvv, .-_Z21__device_stub__Z3addvv
.globl _Z3addv
.type _Z3addv, @function
_Z3addv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z21__device_stub__Z3addvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z3addv, .-_Z3addv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "GPU not using constant memory\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Checking results\n"
.LC2:
.string "ERROR IN COMPUTATION\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "Time to calculate results: %f ms.\n"
.section .rodata.str1.1
.LC4:
.string "GPU using constant memory\n"
.section .rodata.str1.8
.align 8
.LC5:
.string "Speedup using constant memory = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
leaq -98304(%rsp), %r11
.cfi_def_cfa 11, 98312
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $72, %rsp
.cfi_def_cfa_offset 98384
movq %fs:40, %rax
movq %rax, 98360(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L20:
movl %eax, 48(%rsp,%rax,4)
leal (%rax,%rax), %edx
movl %edx, 32816(%rsp,%rax,4)
addq $1, %rax
cmpq $8192, %rax
jne .L20
leaq 48(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $32768, %edx
leaq _ZL5dev_a(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 32816(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $32768, %edx
leaq _ZL5dev_b(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $128, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $64, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L21:
call cudaThreadSynchronize@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
leaq 48(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $32768, %edx
leaq _ZL5dev_a(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
leaq 32816(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $32768, %edx
leaq _ZL5dev_b(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
leaq 65584(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $32768, %edx
leaq _ZL5dev_c(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
leaq 65584(%rsp), %rcx
.L24:
movl 32816(%rsp,%rax), %edx
addl 48(%rsp,%rax), %edx
cmpl (%rax,%rcx), %edx
jne .L37
addq $4, %rax
cmpq $32768, %rax
jne .L24
jmp .L23
.L36:
call _Z21__device_stub__Z3addvv
jmp .L21
.L37:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L23:
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L25:
movl %eax, 48(%rsp,%rax,4)
leal (%rax,%rax), %edx
movl %edx, 32816(%rsp,%rax,4)
addq $1, %rax
cmpq $8192, %rax
jne .L25
leaq 48(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $32768, %edx
leaq _ZL10dev_a_Cont(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 32816(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $32768, %edx
leaq _ZL10dev_b_Cont(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $128, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $64, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L26:
call cudaThreadSynchronize@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
leaq 48(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $32768, %edx
leaq _ZL10dev_a_Cont(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
leaq 32816(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $32768, %edx
leaq _ZL10dev_b_Cont(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
leaq 65584(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $32768, %edx
leaq _ZL5dev_c(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 36(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
leaq 65584(%rsp), %rcx
.L29:
movl 32816(%rsp,%rax), %edx
addl 48(%rsp,%rax), %edx
cmpl (%rax,%rcx), %edx
jne .L39
addq $4, %rax
cmpq $32768, %rax
jne .L29
jmp .L28
.L38:
call _Z26__device_stub__Z8add_Contvv
jmp .L26
.L39:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L28:
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 4(%rsp), %xmm0
divss 36(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 98360(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $98376, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3addv"
.LC7:
.string "_Z8add_Contv"
.LC8:
.string "dev_a_Cont"
.LC9:
.string "dev_b_Cont"
.LC10:
.string "dev_a"
.LC11:
.string "dev_b"
.LC12:
.string "dev_c"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z8add_Contv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $32768, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10dev_a_Cont(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $32768, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10dev_b_Cont(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $32768, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5dev_a(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $32768, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5dev_b(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $32768, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5dev_c(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL5dev_c
.comm _ZL5dev_c,32768,32
.local _ZL5dev_b
.comm _ZL5dev_b,32768,32
.local _ZL5dev_a
.comm _ZL5dev_a,32768,32
.local _ZL10dev_b_Cont
.comm _ZL10dev_b_Cont,32768,32
.local _ZL10dev_a_Cont
.comm _ZL10dev_a_Cont,32768,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "constantMemory.hip"
.globl _Z23__device_stub__add_Contv # -- Begin function _Z23__device_stub__add_Contv
.p2align 4, 0x90
.type _Z23__device_stub__add_Contv,@function
_Z23__device_stub__add_Contv: # @_Z23__device_stub__add_Contv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8add_Contv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__add_Contv, .Lfunc_end0-_Z23__device_stub__add_Contv
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addv # -- Begin function _Z18__device_stub__addv
.p2align 4, 0x90
.type _Z18__device_stub__addv,@function
_Z18__device_stub__addv: # @_Z18__device_stub__addv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z3addv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z18__device_stub__addv, .Lfunc_end1-_Z18__device_stub__addv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $98400, %rsp # imm = 0x18060
.cfi_def_cfa_offset 98432
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %ecx, 32864(%rsp,%rcx,4)
movl %eax, 96(%rsp,%rcx,4)
incq %rcx
addl $2, %eax
cmpq $8192, %rcx # imm = 0x2000
jne .LBB2_1
# %bb.2:
movabsq $4294967360, %rbx # imm = 0x100000040
leaq 32864(%rsp), %rsi
movl $dev_a, %edi
movl $32768, %edx # imm = 0x8000
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 96(%rsp), %rsi
movl $dev_b, %edi
movl $32768, %edx # imm = 0x8000
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 64(%rbx), %r14
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
leaq 65632(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 65632(%rsp), %rsi
movl 65640(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addv, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movq 8(%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
leaq 32864(%rsp), %rdi
movl $dev_a, %esi
movl $32768, %edx # imm = 0x8000
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
leaq 96(%rsp), %rdi
movl $dev_b, %esi
movl $32768, %edx # imm = 0x8000
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
leaq 65632(%rsp), %rdi
movl $dev_c, %esi
movl $32768, %edx # imm = 0x8000
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 36(%rsp), %rdi
callq hipEventElapsedTime
movl $.Lstr.4, %edi
callq puts@PLT
.p2align 4, 0x90
.LBB2_6: # =>This Inner Loop Header: Depth=1
movl 96(%rsp,%r15,4), %eax
addl 32864(%rsp,%r15,4), %eax
cmpl 65632(%rsp,%r15,4), %eax
jne .LBB2_7
# %bb.5: # in Loop: Header=BB2_6 Depth=1
incq %r15
cmpq $8192, %r15 # imm = 0x2000
jne .LBB2_6
jmp .LBB2_8
.LBB2_7:
movl $.Lstr.5, %edi
callq puts@PLT
.LBB2_8: # %.loopexit59
movss 36(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movl $.Lstr.3, %edi
callq puts@PLT
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_9: # =>This Inner Loop Header: Depth=1
movl %ecx, 32864(%rsp,%rcx,4)
movl %eax, 96(%rsp,%rcx,4)
incq %rcx
addl $2, %eax
cmpq $8192, %rcx # imm = 0x2000
jne .LBB2_9
# %bb.10:
leaq 32864(%rsp), %rsi
movl $dev_a_Cont, %edi
movl $32768, %edx # imm = 0x8000
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 96(%rsp), %rsi
movl $dev_b_Cont, %edi
movl $32768, %edx # imm = 0x8000
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_12
# %bb.11:
leaq 24(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8add_Contv, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_12:
callq hipDeviceSynchronize
movq 8(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
leaq 32864(%rsp), %rdi
movl $dev_a_Cont, %esi
movl $32768, %edx # imm = 0x8000
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
leaq 96(%rsp), %rdi
movl $dev_b_Cont, %esi
movl $32768, %edx # imm = 0x8000
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
leaq 65632(%rsp), %rdi
movl $dev_c, %esi
movl $32768, %edx # imm = 0x8000
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 24(%rsp), %rdi
callq hipEventElapsedTime
movl $.Lstr.4, %edi
callq puts@PLT
.p2align 4, 0x90
.LBB2_14: # =>This Inner Loop Header: Depth=1
movl 96(%rsp,%rbx,4), %eax
addl 32864(%rsp,%rbx,4), %eax
cmpl 65632(%rsp,%rbx,4), %eax
jne .LBB2_15
# %bb.13: # in Loop: Header=BB2_14 Depth=1
incq %rbx
cmpq $8192, %rbx # imm = 0x2000
jne .LBB2_14
jmp .LBB2_16
.LBB2_15:
movl $.Lstr.5, %edi
callq puts@PLT
.LBB2_16: # %.loopexit
movss 24(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movss 36(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 24(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $98400, %rsp # imm = 0x18060
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8add_Contv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addv, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $dev_a_Cont, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $32768, %r9d # imm = 0x8000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $dev_b_Cont, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $32768, %r9d # imm = 0x8000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $dev_a, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $32768, %r9d # imm = 0x8000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $dev_b, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movl $32768, %r9d # imm = 0x8000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $dev_c, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movl $32768, %r9d # imm = 0x8000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type dev_a_Cont,@object # @dev_a_Cont
.local dev_a_Cont
.comm dev_a_Cont,32768,16
.type dev_b_Cont,@object # @dev_b_Cont
.local dev_b_Cont
.comm dev_b_Cont,32768,16
.type dev_a,@object # @dev_a
.local dev_a
.comm dev_a,32768,16
.type dev_b,@object # @dev_b
.local dev_b
.comm dev_b,32768,16
.type dev_c,@object # @dev_c
.local dev_c
.comm dev_c,32768,16
.type _Z8add_Contv,@object # @_Z8add_Contv
.section .rodata,"a",@progbits
.globl _Z8add_Contv
.p2align 3, 0x0
_Z8add_Contv:
.quad _Z23__device_stub__add_Contv
.size _Z8add_Contv, 8
.type _Z3addv,@object # @_Z3addv
.globl _Z3addv
.p2align 3, 0x0
_Z3addv:
.quad _Z18__device_stub__addv
.size _Z3addv, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "Time to calculate results: %f ms.\n"
.size .L.str.3, 35
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Speedup using constant memory = %f\n"
.size .L.str.5, 36
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8add_Contv"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3addv"
.size .L__unnamed_2, 8
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "dev_a_Cont"
.size .L__unnamed_3, 11
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "dev_b_Cont"
.size .L__unnamed_4, 11
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "dev_a"
.size .L__unnamed_5, 6
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "dev_b"
.size .L__unnamed_6, 6
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "dev_c"
.size .L__unnamed_7, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "GPU not using constant memory"
.size .Lstr, 30
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "GPU using constant memory"
.size .Lstr.3, 26
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Checking results"
.size .Lstr.4, 17
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "ERROR IN COMPUTATION"
.size .Lstr.5, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__add_Contv
.addrsig_sym _Z18__device_stub__addv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym dev_a_Cont
.addrsig_sym dev_b_Cont
.addrsig_sym dev_a
.addrsig_sym dev_b
.addrsig_sym dev_c
.addrsig_sym _Z8add_Contv
.addrsig_sym _Z3addv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<bits/stdc++.h>
using namespace std;
void vector_sum(vector<float> a,float &cpu_res,int n) {
for (int i = 0; i < n; i++) {
cpu_res += a[i];
}
}
void vector_min(vector<float> a,float &cpu_res,int n){
cpu_res = INT_MAX;
for (int i = 0; i < n; i++) {
cpu_res = min(cpu_res,a[i]);
}
}
void vector_max(vector<float> a,float &cpu_res,int n){
cpu_res = INT_MIN;
for (int i = 0; i < n; i++) {
cpu_res = max(cpu_res,a[i]);
}
}
void vector_sd(vector<float> a,float sum,double &cpu_res_sd,int n){
double mean = (double)sum/(double)n;
double s = 0;
for(int i=0;i<n;i++){
s += ((a[i]-mean)*(a[i]-mean));
}
cpu_res_sd = (double)s/(double)n;
}
__global__ void cuda_vector_sum(float* a,int n) {
const int tid=threadIdx.x;
int no_of_threads=blockDim.x;
for(int step=1;step < n; step *= 2,no_of_threads /= 2){
if (tid <= no_of_threads){
int ind=2*step*tid;
if((ind+step) >= n){
a[ind] = a[ind] + 0;
}else{
a[ind] = a[ind] + a[ind+step];
}
}
}
}
__global__ void cuda_vector_min(float* a,int n) {
const int tid=threadIdx.x;
int no_of_threads=blockDim.x;
for(int step=1;step < n; step *= 2,no_of_threads /= 2){
if (tid <= no_of_threads){
int ind=2*step*tid;
if((ind+step) >= n){
a[ind] = min(a[ind],FLT_MAX);
}else{
a[ind] = min(a[ind],a[ind+step]);
}
}
}
}
__global__ void cuda_vector_max(float* a,int n) {
const int tid=threadIdx.x;
int no_of_threads=blockDim.x;
for(int step=1;step < n; step *= 2,no_of_threads /= 2){
if (tid <= no_of_threads){
int ind=2*step*tid;
if((ind+step) >= n){
a[ind] = max(a[ind],FLT_MIN);
}else{
a[ind] = max(a[ind],a[ind+step]);
}
}
}
}
__global__ void cuda_update_arr(float *a,double mean){
const int tid=threadIdx.x;
a[tid] = (a[tid]-mean)*(a[tid]-mean);
}
int main() {
int N = 2048;
vector<float> a(N);
srand(time(0));
generate(begin(a), end(a), []() { return (float(rand())/float((RAND_MAX)) * 100.0); });
for(auto item:a)
cout<<item<<" ";
cout<<'\n';
float cpu_res=0,gpu_res=0;
double cpu_res_sd = 0,gpu_res_sd = 0;
cout<<"CPU: "<<'\n';
//-------------------------------------------------------------------
// Sum calculation
vector_sum(a,cpu_res,N);
cout << "Vector Sum using CPU :"<<cpu_res<<" \n";
// Average calculation
cout << "Vector Average using CPU :"<<(double)cpu_res/(double)N<<" \n";
vector_sd(a,cpu_res,cpu_res_sd,N);
cout << "Vector Standard Deviation using CPU :"<<fixed<<setprecision(2)<<sqrt(cpu_res_sd)<<" \n";
vector_min(a,cpu_res,N);
cout << "Vector Min using CPU :"<<cpu_res<<" \n";
vector_max(a,cpu_res,N);
cout << "Vector Max using CPU :"<<cpu_res<<" \n";
cout<<"GPU: "<<'\n';
//-------------------------------------------------------------------
// Allocate memory on the device
size_t bytes = sizeof(float) * N;
float* d_a;
cudaMalloc(&d_a, bytes);
//-------------------------------------------------------------------
// Copy data from the host to the device (CPU to GPU)
cudaMemcpy(d_a, a.data(), bytes, cudaMemcpyHostToDevice);
cuda_vector_sum <<<1,N/2>>> (d_a,N);
cudaMemcpy(&gpu_res, d_a, sizeof(float), cudaMemcpyDeviceToHost);
cout << "Vector Sum using GPU :"<<gpu_res<<" \n";
//-------------------------------------------------------------------
cout << "Vector Average using GPU :"<<(double)gpu_res/(double)N<<" \n";
//-------------------------------------------------------------------
double mean = (double)gpu_res/(double)N;
cudaMemcpy(d_a, a.data(), bytes, cudaMemcpyHostToDevice);
cuda_update_arr<<<1,N>>>(d_a,mean);
cuda_vector_sum<<<1,N/2>>>(d_a,N);
cudaMemcpy(&gpu_res, d_a, sizeof(float), cudaMemcpyDeviceToHost);
gpu_res = (double)gpu_res/(double)N;
cout << "Vector Standard Deviation using GPU :"<<fixed<<setprecision(2)<<sqrt(gpu_res)<<" \n";
//-------------------------------------------------------------------
cudaMemcpy(d_a, a.data(), bytes, cudaMemcpyHostToDevice);
gpu_res = INT_MAX;
cuda_vector_min <<<1,N/2>>> (d_a,N);
cudaMemcpy(&gpu_res, d_a, sizeof(float), cudaMemcpyDeviceToHost);
cout << "Vector Min using GPU :"<<gpu_res<<" \n";
//-------------------------------------------------------------------
cudaMemcpy(d_a, a.data(), bytes, cudaMemcpyHostToDevice);
gpu_res = INT_MIN;
cuda_vector_max <<<1,N/2>>> (d_a,N);
cudaMemcpy(&gpu_res, d_a, sizeof(float), cudaMemcpyDeviceToHost);
cout << "Vector Max using GPU :"<<gpu_res<<" \n";
//-------------------------------------------------------------------
// Free memory on device
cudaFree(d_a);
} | code for sm_80
Function : _Z15cuda_update_arrPfd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0203 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0060*/ F2F.F64.F32 R4, R0 ; /* 0x0000000000047310 */
/* 0x004e240000201800 */
/*0070*/ DADD R4, R4, -c[0x0][0x168] ; /* 0x80005a0004047629 */
/* 0x001e0c0000000000 */
/*0080*/ DMUL R4, R4, R4 ; /* 0x0000000404047228 */
/* 0x001e140000000000 */
/*0090*/ F2F.F32.F64 R5, R4 ; /* 0x0000000400057310 */
/* 0x001e240000301000 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15cuda_vector_maxPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0050*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fe200000001ff */
/*0060*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0080*/ ISETP.GT.AND P0, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x001fe2000bf04270 */
/*0090*/ BSSY B0, 0x190 ; /* 0x000000f000007945 */
/* 0x000fd80003800000 */
/*00a0*/ @P0 BRA 0x180 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD R0, R7, R6, RZ ; /* 0x0000000607007224 */
/* 0x000fe400078e02ff */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*00d0*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fca00000006ff */
/*00e0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0205 */
/*00f0*/ LDG.E R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IMAD.IADD R0, R0, 0x1, R7 ; /* 0x0000000100007824 */
/* 0x000fca00078e0207 */
/*0110*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0120*/ @!P0 IMAD.WIDE R2, R7, 0x4, R4 ; /* 0x0000000407028825 */
/* 0x000fe200078e0204 */
/*0130*/ @P0 FMNMX R11, R9, 1.175494350822287508e-38, !PT ; /* 0x00800000090b0809 */
/* 0x004fca0007800000 */
/*0140*/ @P0 STG.E [R4.64], R11 ; /* 0x0000000b04000986 */
/* 0x0001e8000c101906 */
/*0150*/ @!P0 LDG.E R2, [R2.64] ; /* 0x0000000602028981 */
/* 0x000ea4000c1e1900 */
/*0160*/ @!P0 FMNMX R9, R9, R2, !PT ; /* 0x0000000209098209 */
/* 0x004fca0007800000 */
/*0170*/ @!P0 STG.E [R4.64], R9 ; /* 0x0000000904008986 */
/* 0x0001e4000c101906 */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0190*/ SHF.L.U32 R7, R7, 0x1, RZ ; /* 0x0000000107077819 */
/* 0x000fe200000006ff */
/*01a0*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fc6000f8f083f */
/*01b0*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fe20003f06270 */
/*01c0*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fd80008011404 */
/*01d0*/ @!P0 BRA 0x80 ; /* 0xfffffea000008947 */
/* 0x000fea000383ffff */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15cuda_vector_minPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0050*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fe200000001ff */
/*0060*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0080*/ ISETP.GT.AND P0, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x001fe2000bf04270 */
/*0090*/ BSSY B0, 0x190 ; /* 0x000000f000007945 */
/* 0x000fd80003800000 */
/*00a0*/ @P0 BRA 0x180 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD R0, R7, R6, RZ ; /* 0x0000000607007224 */
/* 0x000fe400078e02ff */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*00d0*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fca00000006ff */
/*00e0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0205 */
/*00f0*/ LDG.E R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IMAD.IADD R0, R0, 0x1, R7 ; /* 0x0000000100007824 */
/* 0x000fca00078e0207 */
/*0110*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0120*/ @!P0 IMAD.WIDE R2, R7, 0x4, R4 ; /* 0x0000000407028825 */
/* 0x000fe200078e0204 */
/*0130*/ @P0 FMNMX R11, R9, 3.40282346638528859812e+38, PT ; /* 0x7f7fffff090b0809 */
/* 0x004fca0003800000 */
/*0140*/ @P0 STG.E [R4.64], R11 ; /* 0x0000000b04000986 */
/* 0x0001e8000c101906 */
/*0150*/ @!P0 LDG.E R2, [R2.64] ; /* 0x0000000602028981 */
/* 0x000ea4000c1e1900 */
/*0160*/ @!P0 FMNMX R9, R9, R2, PT ; /* 0x0000000209098209 */
/* 0x004fca0003800000 */
/*0170*/ @!P0 STG.E [R4.64], R9 ; /* 0x0000000904008986 */
/* 0x0001e4000c101906 */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0190*/ SHF.L.U32 R7, R7, 0x1, RZ ; /* 0x0000000107077819 */
/* 0x000fe200000006ff */
/*01a0*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fc6000f8f083f */
/*01b0*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fe20003f06270 */
/*01c0*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fd80008011404 */
/*01d0*/ @!P0 BRA 0x80 ; /* 0xfffffea000008947 */
/* 0x000fea000383ffff */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15cuda_vector_sumPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R0, c[0x0][0x168] ; /* 0x00005a0000007a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0050*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe200078e00ff */
/*0060*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0080*/ ISETP.GT.AND P0, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x001fe2000bf04270 */
/*0090*/ BSSY B0, 0x190 ; /* 0x000000f000007945 */
/* 0x000fd80003800000 */
/*00a0*/ @P0 BRA 0x180 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD R0, R7, R6, RZ ; /* 0x0000000607007224 */
/* 0x000fc800078e02ff */
/*00d0*/ IMAD.SHL.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007824 */
/* 0x000fca00078e00ff */
/*00e0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0205 */
/*00f0*/ LDG.E R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IADD3 R0, R0, R7, RZ ; /* 0x0000000700007210 */
/* 0x000fc80007ffe0ff */
/*0110*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0120*/ @!P0 IMAD.WIDE R2, R7, 0x4, R4 ; /* 0x0000000407028825 */
/* 0x000fc800078e0204 */
/*0130*/ @P0 FADD R11, RZ, R9 ; /* 0x00000009ff0b0221 */
/* 0x004fca0000000000 */
/*0140*/ @P0 STG.E [R4.64], R11 ; /* 0x0000000b04000986 */
/* 0x0001e8000c101906 */
/*0150*/ @!P0 LDG.E R2, [R2.64] ; /* 0x0000000602028981 */
/* 0x000ea4000c1e1900 */
/*0160*/ @!P0 FADD R9, R9, R2 ; /* 0x0000000209098221 */
/* 0x004fca0000000000 */
/*0170*/ @!P0 STG.E [R4.64], R9 ; /* 0x0000000904008986 */
/* 0x0001e4000c101906 */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0190*/ IMAD.SHL.U32 R7, R7, 0x2, RZ ; /* 0x0000000207077824 */
/* 0x000fe200078e00ff */
/*01a0*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fc8000f8f083f */
/*01b0*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fe20003f06270 */
/*01c0*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fd80008011404 */
/*01d0*/ @!P0 BRA 0x80 ; /* 0xfffffea000008947 */
/* 0x000fea000383ffff */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<bits/stdc++.h>
using namespace std;
void vector_sum(vector<float> a,float &cpu_res,int n) {
for (int i = 0; i < n; i++) {
cpu_res += a[i];
}
}
void vector_min(vector<float> a,float &cpu_res,int n){
cpu_res = INT_MAX;
for (int i = 0; i < n; i++) {
cpu_res = min(cpu_res,a[i]);
}
}
void vector_max(vector<float> a,float &cpu_res,int n){
cpu_res = INT_MIN;
for (int i = 0; i < n; i++) {
cpu_res = max(cpu_res,a[i]);
}
}
void vector_sd(vector<float> a,float sum,double &cpu_res_sd,int n){
double mean = (double)sum/(double)n;
double s = 0;
for(int i=0;i<n;i++){
s += ((a[i]-mean)*(a[i]-mean));
}
cpu_res_sd = (double)s/(double)n;
}
__global__ void cuda_vector_sum(float* a,int n) {
const int tid=threadIdx.x;
int no_of_threads=blockDim.x;
for(int step=1;step < n; step *= 2,no_of_threads /= 2){
if (tid <= no_of_threads){
int ind=2*step*tid;
if((ind+step) >= n){
a[ind] = a[ind] + 0;
}else{
a[ind] = a[ind] + a[ind+step];
}
}
}
}
__global__ void cuda_vector_min(float* a,int n) {
const int tid=threadIdx.x;
int no_of_threads=blockDim.x;
for(int step=1;step < n; step *= 2,no_of_threads /= 2){
if (tid <= no_of_threads){
int ind=2*step*tid;
if((ind+step) >= n){
a[ind] = min(a[ind],FLT_MAX);
}else{
a[ind] = min(a[ind],a[ind+step]);
}
}
}
}
__global__ void cuda_vector_max(float* a,int n) {
const int tid=threadIdx.x;
int no_of_threads=blockDim.x;
for(int step=1;step < n; step *= 2,no_of_threads /= 2){
if (tid <= no_of_threads){
int ind=2*step*tid;
if((ind+step) >= n){
a[ind] = max(a[ind],FLT_MIN);
}else{
a[ind] = max(a[ind],a[ind+step]);
}
}
}
}
__global__ void cuda_update_arr(float *a,double mean){
const int tid=threadIdx.x;
a[tid] = (a[tid]-mean)*(a[tid]-mean);
}
int main() {
int N = 2048;
vector<float> a(N);
srand(time(0));
generate(begin(a), end(a), []() { return (float(rand())/float((RAND_MAX)) * 100.0); });
for(auto item:a)
cout<<item<<" ";
cout<<'\n';
float cpu_res=0,gpu_res=0;
double cpu_res_sd = 0,gpu_res_sd = 0;
cout<<"CPU: "<<'\n';
//-------------------------------------------------------------------
// Sum calculation
vector_sum(a,cpu_res,N);
cout << "Vector Sum using CPU :"<<cpu_res<<" \n";
// Average calculation
cout << "Vector Average using CPU :"<<(double)cpu_res/(double)N<<" \n";
vector_sd(a,cpu_res,cpu_res_sd,N);
cout << "Vector Standard Deviation using CPU :"<<fixed<<setprecision(2)<<sqrt(cpu_res_sd)<<" \n";
vector_min(a,cpu_res,N);
cout << "Vector Min using CPU :"<<cpu_res<<" \n";
vector_max(a,cpu_res,N);
cout << "Vector Max using CPU :"<<cpu_res<<" \n";
cout<<"GPU: "<<'\n';
//-------------------------------------------------------------------
// Allocate memory on the device
size_t bytes = sizeof(float) * N;
float* d_a;
cudaMalloc(&d_a, bytes);
//-------------------------------------------------------------------
// Copy data from the host to the device (CPU to GPU)
cudaMemcpy(d_a, a.data(), bytes, cudaMemcpyHostToDevice);
cuda_vector_sum <<<1,N/2>>> (d_a,N);
cudaMemcpy(&gpu_res, d_a, sizeof(float), cudaMemcpyDeviceToHost);
cout << "Vector Sum using GPU :"<<gpu_res<<" \n";
//-------------------------------------------------------------------
cout << "Vector Average using GPU :"<<(double)gpu_res/(double)N<<" \n";
//-------------------------------------------------------------------
double mean = (double)gpu_res/(double)N;
cudaMemcpy(d_a, a.data(), bytes, cudaMemcpyHostToDevice);
cuda_update_arr<<<1,N>>>(d_a,mean);
cuda_vector_sum<<<1,N/2>>>(d_a,N);
cudaMemcpy(&gpu_res, d_a, sizeof(float), cudaMemcpyDeviceToHost);
gpu_res = (double)gpu_res/(double)N;
cout << "Vector Standard Deviation using GPU :"<<fixed<<setprecision(2)<<sqrt(gpu_res)<<" \n";
//-------------------------------------------------------------------
cudaMemcpy(d_a, a.data(), bytes, cudaMemcpyHostToDevice);
gpu_res = INT_MAX;
cuda_vector_min <<<1,N/2>>> (d_a,N);
cudaMemcpy(&gpu_res, d_a, sizeof(float), cudaMemcpyDeviceToHost);
cout << "Vector Min using GPU :"<<gpu_res<<" \n";
//-------------------------------------------------------------------
cudaMemcpy(d_a, a.data(), bytes, cudaMemcpyHostToDevice);
gpu_res = INT_MIN;
cuda_vector_max <<<1,N/2>>> (d_a,N);
cudaMemcpy(&gpu_res, d_a, sizeof(float), cudaMemcpyDeviceToHost);
cout << "Vector Max using GPU :"<<gpu_res<<" \n";
//-------------------------------------------------------------------
// Free memory on device
cudaFree(d_a);
} | .file "tmpxft_001bab9f_00000000-6_operations_on_Vector.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB10871:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10871:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10vector_sumSt6vectorIfSaIfEERfi
.type _Z10vector_sumSt6vectorIfSaIfEERfi, @function
_Z10vector_sumSt6vectorIfSaIfEERfi:
.LFB10859:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L3
movslq %edx, %rdx
leaq 0(,%rdx,4), %rcx
movl $0, %eax
.L5:
movq (%rdi), %rdx
movss (%rsi), %xmm0
addss (%rdx,%rax), %xmm0
movss %xmm0, (%rsi)
addq $4, %rax
cmpq %rcx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE10859:
.size _Z10vector_sumSt6vectorIfSaIfEERfi, .-_Z10vector_sumSt6vectorIfSaIfEERfi
.globl _Z10vector_minSt6vectorIfSaIfEERfi
.type _Z10vector_minSt6vectorIfSaIfEERfi, @function
_Z10vector_minSt6vectorIfSaIfEERfi:
.LFB10860:
.cfi_startproc
endbr64
movl $0x4f000000, (%rsi)
testl %edx, %edx
jle .L12
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r13
movq %rsi, %rbp
movslq %edx, %rdx
leaq 0(,%rdx,4), %r12
movl $0, %ebx
.L9:
movq 0(%r13), %rax
movss (%rax,%rbx), %xmm0
movss 0(%rbp), %xmm1
call fminf@PLT
movss %xmm0, 0(%rbp)
addq $4, %rbx
cmpq %r12, %rbx
jne .L9
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE10860:
.size _Z10vector_minSt6vectorIfSaIfEERfi, .-_Z10vector_minSt6vectorIfSaIfEERfi
.globl _Z10vector_maxSt6vectorIfSaIfEERfi
.type _Z10vector_maxSt6vectorIfSaIfEERfi, @function
_Z10vector_maxSt6vectorIfSaIfEERfi:
.LFB10861:
.cfi_startproc
endbr64
movl $0xcf000000, (%rsi)
testl %edx, %edx
jle .L20
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r13
movq %rsi, %rbp
movslq %edx, %rdx
leaq 0(,%rdx,4), %r12
movl $0, %ebx
.L17:
movq 0(%r13), %rax
movss (%rax,%rbx), %xmm0
movss 0(%rbp), %xmm1
call fmaxf@PLT
movss %xmm0, 0(%rbp)
addq $4, %rbx
cmpq %r12, %rbx
jne .L17
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE10861:
.size _Z10vector_maxSt6vectorIfSaIfEERfi, .-_Z10vector_maxSt6vectorIfSaIfEERfi
.globl _Z9vector_sdSt6vectorIfSaIfEEfRdi
.type _Z9vector_sdSt6vectorIfSaIfEEfRdi, @function
_Z9vector_sdSt6vectorIfSaIfEEfRdi:
.LFB10862:
.cfi_startproc
endbr64
pxor %xmm3, %xmm3
cvtsi2sdl %edx, %xmm3
cvtss2sd %xmm0, %xmm0
divsd %xmm3, %xmm0
testl %edx, %edx
jle .L26
movq (%rdi), %rax
movslq %edx, %rdx
leaq (%rax,%rdx,4), %rdx
pxor %xmm2, %xmm2
.L25:
pxor %xmm1, %xmm1
cvtss2sd (%rax), %xmm1
subsd %xmm0, %xmm1
mulsd %xmm1, %xmm1
addsd %xmm1, %xmm2
addq $4, %rax
cmpq %rdx, %rax
jne .L25
.L24:
divsd %xmm3, %xmm2
movsd %xmm2, (%rsi)
ret
.L26:
pxor %xmm2, %xmm2
jmp .L24
.cfi_endproc
.LFE10862:
.size _Z9vector_sdSt6vectorIfSaIfEEfRdi, .-_Z9vector_sdSt6vectorIfSaIfEEfRdi
.globl _Z36__device_stub__Z15cuda_vector_sumPfiPfi
.type _Z36__device_stub__Z15cuda_vector_sumPfiPfi, @function
_Z36__device_stub__Z15cuda_vector_sumPfiPfi:
.LFB10893:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15cuda_vector_sumPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10893:
.size _Z36__device_stub__Z15cuda_vector_sumPfiPfi, .-_Z36__device_stub__Z15cuda_vector_sumPfiPfi
.globl _Z15cuda_vector_sumPfi
.type _Z15cuda_vector_sumPfi, @function
_Z15cuda_vector_sumPfi:
.LFB10894:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z15cuda_vector_sumPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10894:
.size _Z15cuda_vector_sumPfi, .-_Z15cuda_vector_sumPfi
.globl _Z36__device_stub__Z15cuda_vector_minPfiPfi
.type _Z36__device_stub__Z15cuda_vector_minPfiPfi, @function
_Z36__device_stub__Z15cuda_vector_minPfiPfi:
.LFB10895:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L41
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15cuda_vector_minPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10895:
.size _Z36__device_stub__Z15cuda_vector_minPfiPfi, .-_Z36__device_stub__Z15cuda_vector_minPfiPfi
.globl _Z15cuda_vector_minPfi
.type _Z15cuda_vector_minPfi, @function
_Z15cuda_vector_minPfi:
.LFB10896:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z15cuda_vector_minPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10896:
.size _Z15cuda_vector_minPfi, .-_Z15cuda_vector_minPfi
.globl _Z36__device_stub__Z15cuda_vector_maxPfiPfi
.type _Z36__device_stub__Z15cuda_vector_maxPfiPfi, @function
_Z36__device_stub__Z15cuda_vector_maxPfiPfi:
.LFB10897:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L48
.L44:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L49
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15cuda_vector_maxPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L44
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10897:
.size _Z36__device_stub__Z15cuda_vector_maxPfiPfi, .-_Z36__device_stub__Z15cuda_vector_maxPfiPfi
.globl _Z15cuda_vector_maxPfi
.type _Z15cuda_vector_maxPfi, @function
_Z15cuda_vector_maxPfi:
.LFB10898:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z15cuda_vector_maxPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10898:
.size _Z15cuda_vector_maxPfi, .-_Z15cuda_vector_maxPfi
.globl _Z36__device_stub__Z15cuda_update_arrPfdPfd
.type _Z36__device_stub__Z15cuda_update_arrPfdPfd, @function
_Z36__device_stub__Z15cuda_update_arrPfdPfd:
.LFB10899:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movsd %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L56
.L52:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L57
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15cuda_update_arrPfd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L52
.L57:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10899:
.size _Z36__device_stub__Z15cuda_update_arrPfdPfd, .-_Z36__device_stub__Z15cuda_update_arrPfdPfd
.globl _Z15cuda_update_arrPfd
.type _Z15cuda_update_arrPfd, @function
_Z15cuda_update_arrPfd:
.LFB10900:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z15cuda_update_arrPfdPfd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10900:
.size _Z15cuda_update_arrPfd, .-_Z15cuda_update_arrPfd
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "_Z15cuda_update_arrPfd"
.LC4:
.string "_Z15cuda_vector_maxPfi"
.LC5:
.string "_Z15cuda_vector_minPfi"
.LC6:
.string "_Z15cuda_vector_sumPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB10902:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z15cuda_update_arrPfd(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z15cuda_vector_maxPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z15cuda_vector_minPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z15cuda_vector_sumPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10902:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEED2Ev
.type _ZNSt6vectorIfSaIfEED2Ev, @function
_ZNSt6vectorIfSaIfEED2Ev:
.LFB11592:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L65
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L65:
ret
.cfi_endproc
.LFE11592:
.size _ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev
.weak _ZNSt6vectorIfSaIfEED1Ev
.set _ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev
.section .text._ZNSt6vectorIfSaIfEEC2ERKS1_,"axG",@progbits,_ZNSt6vectorIfSaIfEEC5ERKS1_,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEEC2ERKS1_
.type _ZNSt6vectorIfSaIfEEC2ERKS1_, @function
_ZNSt6vectorIfSaIfEEC2ERKS1_:
.LFB11604:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %rsi, %r13
movq 8(%rsi), %r12
subq (%rsi), %r12
movq $0, (%rdi)
movq $0, 8(%rdi)
movq $0, 16(%rdi)
je .L73
movabsq $9223372036854775804, %rax
cmpq %r12, %rax
jb .L75
movq %r12, %rdi
call _Znwm@PLT
movq %rax, %rbp
.L69:
movq %rbp, (%rbx)
movq %rbp, 8(%rbx)
addq %rbp, %r12
movq %r12, 16(%rbx)
movq 0(%r13), %rsi
movq 8(%r13), %r12
subq %rsi, %r12
cmpq $4, %r12
jle .L71
movq %r12, %rdx
movq %rbp, %rdi
call memmove@PLT
.L72:
addq %r12, %rbp
movq %rbp, 8(%rbx)
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L75:
.cfi_restore_state
call _ZSt28__throw_bad_array_new_lengthv@PLT
.L73:
movl $0, %ebp
jmp .L69
.L71:
jne .L72
movss (%rsi), %xmm0
movss %xmm0, 0(%rbp)
jmp .L72
.cfi_endproc
.LFE11604:
.size _ZNSt6vectorIfSaIfEEC2ERKS1_, .-_ZNSt6vectorIfSaIfEEC2ERKS1_
.weak _ZNSt6vectorIfSaIfEEC1ERKS1_
.set _ZNSt6vectorIfSaIfEEC1ERKS1_,_ZNSt6vectorIfSaIfEEC2ERKS1_
.section .rodata.str1.1
.LC10:
.string " "
.LC11:
.string "CPU: "
.LC12:
.string "Vector Sum using CPU :"
.LC13:
.string " \n"
.LC14:
.string "Vector Average using CPU :"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC16:
.string "Vector Standard Deviation using CPU :"
.section .rodata.str1.1
.LC17:
.string "Vector Min using CPU :"
.LC18:
.string "Vector Max using CPU :"
.LC19:
.string "GPU: "
.LC20:
.string "Vector Sum using GPU :"
.LC21:
.string "Vector Average using GPU :"
.section .rodata.str1.8
.align 8
.LC23:
.string "Vector Standard Deviation using GPU :"
.section .rodata.str1.1
.LC24:
.string "Vector Min using GPU :"
.LC25:
.string "Vector Max using GPU :"
.text
.globl main
.type main, @function
main:
.LFB10863:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA10863
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
addq $-128, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $8192, %edi
.LEHB0:
call _Znwm@PLT
.LEHE0:
movq %rax, %r13
movq %rax, 64(%rsp)
leaq 8192(%rax), %rdx
movq %rdx, 80(%rsp)
movl $0x00000000, (%rax)
leaq 4(%rax), %rax
.L77:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L77
movq %rdx, 72(%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r13, %rbx
leaq 8192(%r13), %r12
movq %r13, %rbp
.L78:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC8(%rip), %xmm0
mulss .LC9(%rip), %xmm0
movss %xmm0, 0(%rbp)
addq $4, %rbp
cmpq %r12, %rbp
jne .L78
leaq _ZSt4cout(%rip), %rbp
leaq .LC10(%rip), %r14
jmp .L79
.L105:
movq %rax, %rdi
movl $1, %edx
movq %r14, %rsi
.LEHB1:
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, %r12
je .L104
.L79:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L105
.L104:
movl $10, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movl $0x00000000, 24(%rsp)
movl $0x00000000, 28(%rsp)
movq $0x000000000, 32(%rsp)
leaq .LC11(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
leaq 64(%rsp), %rsi
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEEC1ERKS1_
leaq 24(%rsp), %rsi
leaq 96(%rsp), %rbx
movl $2048, %edx
movq %rbx, %rdi
call _Z10vector_sumSt6vectorIfSaIfEERfi
movq %rbx, %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movss 24(%rsp), %xmm2
movss %xmm2, 12(%rsp)
pxor %xmm4, %xmm4
cvtss2sd %xmm2, %xmm4
movq %xmm4, %rbx
movapd %xmm4, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC14(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm3
mulsd .LC15(%rip), %xmm3
movapd %xmm3, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 64(%rsp), %rsi
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEEC1ERKS1_
leaq 32(%rsp), %rsi
leaq 96(%rsp), %rbx
movl $2048, %edx
movss 12(%rsp), %xmm0
movq %rbx, %rdi
call _Z9vector_sdSt6vectorIfSaIfEEfRdi
movq %rbx, %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq .LC16(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movq (%rax), %rax
movq %rbx, %rdx
addq -24(%rax), %rdx
movl 24(%rdx), %eax
andl $-261, %eax
orl $4, %eax
movl %eax, 24(%rdx)
movq (%rbx), %rax
movq -24(%rax), %rax
movq $2, 8(%rbx,%rax)
movsd 32(%rsp), %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L100
sqrtsd %xmm0, %xmm0
.L82:
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L106
.L100:
call sqrt@PLT
jmp .L82
.L106:
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 64(%rsp), %rsi
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEEC1ERKS1_
leaq 24(%rsp), %rsi
leaq 96(%rsp), %rbx
movl $2048, %edx
movq %rbx, %rdi
call _Z10vector_minSt6vectorIfSaIfEERfi
movq %rbx, %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq .LC17(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 24(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 64(%rsp), %rsi
movq %rbx, %rdi
call _ZNSt6vectorIfSaIfEEC1ERKS1_
leaq 24(%rsp), %rsi
movl $2048, %edx
movq %rbx, %rdi
call _Z10vector_maxSt6vectorIfSaIfEERfi
movq %rbx, %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq .LC18(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 24(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC19(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
leaq 40(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8192, %edx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L83
movl $2048, %esi
movq 40(%rsp), %rdi
call _Z36__device_stub__Z15cuda_vector_sumPfiPfi
.L83:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 40(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC20(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC21(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
mulsd .LC15(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl 28(%rsp), %ebx
movl $1, %ecx
movl $8192, %edx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $2048, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L84
movd %ebx, %xmm5
pxor %xmm0, %xmm0
cvtss2sd %xmm5, %xmm0
mulsd .LC15(%rip), %xmm0
movq 40(%rsp), %rdi
call _Z36__device_stub__Z15cuda_update_arrPfdPfd
.L84:
movl $1024, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L85
movl $2048, %esi
movq 40(%rsp), %rdi
call _Z36__device_stub__Z15cuda_vector_sumPfiPfi
.L85:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 40(%rsp), %rsi
call cudaMemcpy@PLT
movss .LC22(%rip), %xmm0
mulss 28(%rsp), %xmm0
movss %xmm0, 28(%rsp)
leaq .LC23(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movq (%rax), %rax
movq %rbx, %rdx
addq -24(%rax), %rdx
movl 24(%rdx), %eax
andl $-261, %eax
orl $4, %eax
movl %eax, 24(%rdx)
movq (%rbx), %rax
movq -24(%rax), %rax
movq $2, 8(%rbx,%rax)
movss 28(%rsp), %xmm0
pxor %xmm1, %xmm1
ucomiss %xmm0, %xmm1
ja .L101
sqrtss %xmm0, %xmm0
.L88:
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L107
.L101:
call sqrtf@PLT
jmp .L88
.L107:
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $1, %ecx
movl $8192, %edx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $0x4f000000, 28(%rsp)
movl $1024, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L89
movl $2048, %esi
movq 40(%rsp), %rdi
call _Z36__device_stub__Z15cuda_vector_minPfiPfi
.L89:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 40(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC24(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $1, %ecx
movl $8192, %edx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $0xcf000000, 28(%rsp)
movl $1024, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L90
movl $2048, %esi
movq 40(%rsp), %rdi
call _Z36__device_stub__Z15cuda_vector_maxPfiPfi
.L90:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 40(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC25(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
.LEHE1:
leaq 64(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L108
movl $0, %eax
subq $-128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L94:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L92
call __stack_chk_fail@PLT
.L92:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L108:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10863:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA10863:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE10863-.LLSDACSB10863
.LLSDACSB10863:
.uleb128 .LEHB0-.LFB10863
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB10863
.uleb128 .LEHE1-.LEHB1
.uleb128 .L94-.LFB10863
.uleb128 0
.uleb128 .LEHB2-.LFB10863
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE10863:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC8:
.long 805306368
.align 4
.LC9:
.long 1120403456
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC15:
.long 0
.long 1061158912
.section .rodata.cst4
.align 4
.LC22:
.long 973078528
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<bits/stdc++.h>
using namespace std;
void vector_sum(vector<float> a,float &cpu_res,int n) {
for (int i = 0; i < n; i++) {
cpu_res += a[i];
}
}
void vector_min(vector<float> a,float &cpu_res,int n){
cpu_res = INT_MAX;
for (int i = 0; i < n; i++) {
cpu_res = min(cpu_res,a[i]);
}
}
void vector_max(vector<float> a,float &cpu_res,int n){
cpu_res = INT_MIN;
for (int i = 0; i < n; i++) {
cpu_res = max(cpu_res,a[i]);
}
}
void vector_sd(vector<float> a,float sum,double &cpu_res_sd,int n){
double mean = (double)sum/(double)n;
double s = 0;
for(int i=0;i<n;i++){
s += ((a[i]-mean)*(a[i]-mean));
}
cpu_res_sd = (double)s/(double)n;
}
__global__ void cuda_vector_sum(float* a,int n) {
const int tid=threadIdx.x;
int no_of_threads=blockDim.x;
for(int step=1;step < n; step *= 2,no_of_threads /= 2){
if (tid <= no_of_threads){
int ind=2*step*tid;
if((ind+step) >= n){
a[ind] = a[ind] + 0;
}else{
a[ind] = a[ind] + a[ind+step];
}
}
}
}
__global__ void cuda_vector_min(float* a,int n) {
const int tid=threadIdx.x;
int no_of_threads=blockDim.x;
for(int step=1;step < n; step *= 2,no_of_threads /= 2){
if (tid <= no_of_threads){
int ind=2*step*tid;
if((ind+step) >= n){
a[ind] = min(a[ind],FLT_MAX);
}else{
a[ind] = min(a[ind],a[ind+step]);
}
}
}
}
__global__ void cuda_vector_max(float* a,int n) {
const int tid=threadIdx.x;
int no_of_threads=blockDim.x;
for(int step=1;step < n; step *= 2,no_of_threads /= 2){
if (tid <= no_of_threads){
int ind=2*step*tid;
if((ind+step) >= n){
a[ind] = max(a[ind],FLT_MIN);
}else{
a[ind] = max(a[ind],a[ind+step]);
}
}
}
}
__global__ void cuda_update_arr(float *a,double mean){
const int tid=threadIdx.x;
a[tid] = (a[tid]-mean)*(a[tid]-mean);
}
int main() {
int N = 2048;
vector<float> a(N);
srand(time(0));
generate(begin(a), end(a), []() { return (float(rand())/float((RAND_MAX)) * 100.0); });
for(auto item:a)
cout<<item<<" ";
cout<<'\n';
float cpu_res=0,gpu_res=0;
double cpu_res_sd = 0,gpu_res_sd = 0;
cout<<"CPU: "<<'\n';
//-------------------------------------------------------------------
// Sum calculation
vector_sum(a,cpu_res,N);
cout << "Vector Sum using CPU :"<<cpu_res<<" \n";
// Average calculation
cout << "Vector Average using CPU :"<<(double)cpu_res/(double)N<<" \n";
vector_sd(a,cpu_res,cpu_res_sd,N);
cout << "Vector Standard Deviation using CPU :"<<fixed<<setprecision(2)<<sqrt(cpu_res_sd)<<" \n";
vector_min(a,cpu_res,N);
cout << "Vector Min using CPU :"<<cpu_res<<" \n";
vector_max(a,cpu_res,N);
cout << "Vector Max using CPU :"<<cpu_res<<" \n";
cout<<"GPU: "<<'\n';
//-------------------------------------------------------------------
// Allocate memory on the device
size_t bytes = sizeof(float) * N;
float* d_a;
cudaMalloc(&d_a, bytes);
//-------------------------------------------------------------------
// Copy data from the host to the device (CPU to GPU)
cudaMemcpy(d_a, a.data(), bytes, cudaMemcpyHostToDevice);
cuda_vector_sum <<<1,N/2>>> (d_a,N);
cudaMemcpy(&gpu_res, d_a, sizeof(float), cudaMemcpyDeviceToHost);
cout << "Vector Sum using GPU :"<<gpu_res<<" \n";
//-------------------------------------------------------------------
cout << "Vector Average using GPU :"<<(double)gpu_res/(double)N<<" \n";
//-------------------------------------------------------------------
double mean = (double)gpu_res/(double)N;
cudaMemcpy(d_a, a.data(), bytes, cudaMemcpyHostToDevice);
cuda_update_arr<<<1,N>>>(d_a,mean);
cuda_vector_sum<<<1,N/2>>>(d_a,N);
cudaMemcpy(&gpu_res, d_a, sizeof(float), cudaMemcpyDeviceToHost);
gpu_res = (double)gpu_res/(double)N;
cout << "Vector Standard Deviation using GPU :"<<fixed<<setprecision(2)<<sqrt(gpu_res)<<" \n";
//-------------------------------------------------------------------
cudaMemcpy(d_a, a.data(), bytes, cudaMemcpyHostToDevice);
gpu_res = INT_MAX;
cuda_vector_min <<<1,N/2>>> (d_a,N);
cudaMemcpy(&gpu_res, d_a, sizeof(float), cudaMemcpyDeviceToHost);
cout << "Vector Min using GPU :"<<gpu_res<<" \n";
//-------------------------------------------------------------------
cudaMemcpy(d_a, a.data(), bytes, cudaMemcpyHostToDevice);
gpu_res = INT_MIN;
cuda_vector_max <<<1,N/2>>> (d_a,N);
cudaMemcpy(&gpu_res, d_a, sizeof(float), cudaMemcpyDeviceToHost);
cout << "Vector Max using GPU :"<<gpu_res<<" \n";
//-------------------------------------------------------------------
// Free memory on device
cudaFree(d_a);
} | #include <hip/hip_runtime.h>
#include<bits/stdc++.h>
using namespace std;
void vector_sum(vector<float> a,float &cpu_res,int n) {
for (int i = 0; i < n; i++) {
cpu_res += a[i];
}
}
void vector_min(vector<float> a,float &cpu_res,int n){
cpu_res = INT_MAX;
for (int i = 0; i < n; i++) {
cpu_res = min(cpu_res,a[i]);
}
}
void vector_max(vector<float> a,float &cpu_res,int n){
cpu_res = INT_MIN;
for (int i = 0; i < n; i++) {
cpu_res = max(cpu_res,a[i]);
}
}
void vector_sd(vector<float> a,float sum,double &cpu_res_sd,int n){
double mean = (double)sum/(double)n;
double s = 0;
for(int i=0;i<n;i++){
s += ((a[i]-mean)*(a[i]-mean));
}
cpu_res_sd = (double)s/(double)n;
}
__global__ void cuda_vector_sum(float* a,int n) {
const int tid=threadIdx.x;
int no_of_threads=blockDim.x;
for(int step=1;step < n; step *= 2,no_of_threads /= 2){
if (tid <= no_of_threads){
int ind=2*step*tid;
if((ind+step) >= n){
a[ind] = a[ind] + 0;
}else{
a[ind] = a[ind] + a[ind+step];
}
}
}
}
__global__ void cuda_vector_min(float* a,int n) {
const int tid=threadIdx.x;
int no_of_threads=blockDim.x;
for(int step=1;step < n; step *= 2,no_of_threads /= 2){
if (tid <= no_of_threads){
int ind=2*step*tid;
if((ind+step) >= n){
a[ind] = min(a[ind],FLT_MAX);
}else{
a[ind] = min(a[ind],a[ind+step]);
}
}
}
}
__global__ void cuda_vector_max(float* a,int n) {
const int tid=threadIdx.x;
int no_of_threads=blockDim.x;
for(int step=1;step < n; step *= 2,no_of_threads /= 2){
if (tid <= no_of_threads){
int ind=2*step*tid;
if((ind+step) >= n){
a[ind] = max(a[ind],FLT_MIN);
}else{
a[ind] = max(a[ind],a[ind+step]);
}
}
}
}
__global__ void cuda_update_arr(float *a,double mean){
const int tid=threadIdx.x;
a[tid] = (a[tid]-mean)*(a[tid]-mean);
}
int main() {
int N = 2048;
vector<float> a(N);
srand(time(0));
generate(begin(a), end(a), []() { return (float(rand())/float((RAND_MAX)) * 100.0); });
for(auto item:a)
cout<<item<<" ";
cout<<'\n';
float cpu_res=0,gpu_res=0;
double cpu_res_sd = 0,gpu_res_sd = 0;
cout<<"CPU: "<<'\n';
//-------------------------------------------------------------------
// Sum calculation
vector_sum(a,cpu_res,N);
cout << "Vector Sum using CPU :"<<cpu_res<<" \n";
// Average calculation
cout << "Vector Average using CPU :"<<(double)cpu_res/(double)N<<" \n";
vector_sd(a,cpu_res,cpu_res_sd,N);
cout << "Vector Standard Deviation using CPU :"<<fixed<<setprecision(2)<<sqrt(cpu_res_sd)<<" \n";
vector_min(a,cpu_res,N);
cout << "Vector Min using CPU :"<<cpu_res<<" \n";
vector_max(a,cpu_res,N);
cout << "Vector Max using CPU :"<<cpu_res<<" \n";
cout<<"GPU: "<<'\n';
//-------------------------------------------------------------------
// Allocate memory on the device
size_t bytes = sizeof(float) * N;
float* d_a;
hipMalloc(&d_a, bytes);
//-------------------------------------------------------------------
// Copy data from the host to the device (CPU to GPU)
hipMemcpy(d_a, a.data(), bytes, hipMemcpyHostToDevice);
cuda_vector_sum <<<1,N/2>>> (d_a,N);
hipMemcpy(&gpu_res, d_a, sizeof(float), hipMemcpyDeviceToHost);
cout << "Vector Sum using GPU :"<<gpu_res<<" \n";
//-------------------------------------------------------------------
cout << "Vector Average using GPU :"<<(double)gpu_res/(double)N<<" \n";
//-------------------------------------------------------------------
double mean = (double)gpu_res/(double)N;
hipMemcpy(d_a, a.data(), bytes, hipMemcpyHostToDevice);
cuda_update_arr<<<1,N>>>(d_a,mean);
cuda_vector_sum<<<1,N/2>>>(d_a,N);
hipMemcpy(&gpu_res, d_a, sizeof(float), hipMemcpyDeviceToHost);
gpu_res = (double)gpu_res/(double)N;
cout << "Vector Standard Deviation using GPU :"<<fixed<<setprecision(2)<<sqrt(gpu_res)<<" \n";
//-------------------------------------------------------------------
hipMemcpy(d_a, a.data(), bytes, hipMemcpyHostToDevice);
gpu_res = INT_MAX;
cuda_vector_min <<<1,N/2>>> (d_a,N);
hipMemcpy(&gpu_res, d_a, sizeof(float), hipMemcpyDeviceToHost);
cout << "Vector Min using GPU :"<<gpu_res<<" \n";
//-------------------------------------------------------------------
hipMemcpy(d_a, a.data(), bytes, hipMemcpyHostToDevice);
gpu_res = INT_MIN;
cuda_vector_max <<<1,N/2>>> (d_a,N);
hipMemcpy(&gpu_res, d_a, sizeof(float), hipMemcpyDeviceToHost);
cout << "Vector Max using GPU :"<<gpu_res<<" \n";
//-------------------------------------------------------------------
// Free memory on device
hipFree(d_a);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<bits/stdc++.h>
using namespace std;
void vector_sum(vector<float> a,float &cpu_res,int n) {
for (int i = 0; i < n; i++) {
cpu_res += a[i];
}
}
void vector_min(vector<float> a,float &cpu_res,int n){
cpu_res = INT_MAX;
for (int i = 0; i < n; i++) {
cpu_res = min(cpu_res,a[i]);
}
}
void vector_max(vector<float> a,float &cpu_res,int n){
cpu_res = INT_MIN;
for (int i = 0; i < n; i++) {
cpu_res = max(cpu_res,a[i]);
}
}
void vector_sd(vector<float> a,float sum,double &cpu_res_sd,int n){
double mean = (double)sum/(double)n;
double s = 0;
for(int i=0;i<n;i++){
s += ((a[i]-mean)*(a[i]-mean));
}
cpu_res_sd = (double)s/(double)n;
}
__global__ void cuda_vector_sum(float* a,int n) {
const int tid=threadIdx.x;
int no_of_threads=blockDim.x;
for(int step=1;step < n; step *= 2,no_of_threads /= 2){
if (tid <= no_of_threads){
int ind=2*step*tid;
if((ind+step) >= n){
a[ind] = a[ind] + 0;
}else{
a[ind] = a[ind] + a[ind+step];
}
}
}
}
__global__ void cuda_vector_min(float* a,int n) {
const int tid=threadIdx.x;
int no_of_threads=blockDim.x;
for(int step=1;step < n; step *= 2,no_of_threads /= 2){
if (tid <= no_of_threads){
int ind=2*step*tid;
if((ind+step) >= n){
a[ind] = min(a[ind],FLT_MAX);
}else{
a[ind] = min(a[ind],a[ind+step]);
}
}
}
}
__global__ void cuda_vector_max(float* a,int n) {
const int tid=threadIdx.x;
int no_of_threads=blockDim.x;
for(int step=1;step < n; step *= 2,no_of_threads /= 2){
if (tid <= no_of_threads){
int ind=2*step*tid;
if((ind+step) >= n){
a[ind] = max(a[ind],FLT_MIN);
}else{
a[ind] = max(a[ind],a[ind+step]);
}
}
}
}
__global__ void cuda_update_arr(float *a,double mean){
const int tid=threadIdx.x;
a[tid] = (a[tid]-mean)*(a[tid]-mean);
}
int main() {
int N = 2048;
vector<float> a(N);
srand(time(0));
generate(begin(a), end(a), []() { return (float(rand())/float((RAND_MAX)) * 100.0); });
for(auto item:a)
cout<<item<<" ";
cout<<'\n';
float cpu_res=0,gpu_res=0;
double cpu_res_sd = 0,gpu_res_sd = 0;
cout<<"CPU: "<<'\n';
//-------------------------------------------------------------------
// Sum calculation
vector_sum(a,cpu_res,N);
cout << "Vector Sum using CPU :"<<cpu_res<<" \n";
// Average calculation
cout << "Vector Average using CPU :"<<(double)cpu_res/(double)N<<" \n";
vector_sd(a,cpu_res,cpu_res_sd,N);
cout << "Vector Standard Deviation using CPU :"<<fixed<<setprecision(2)<<sqrt(cpu_res_sd)<<" \n";
vector_min(a,cpu_res,N);
cout << "Vector Min using CPU :"<<cpu_res<<" \n";
vector_max(a,cpu_res,N);
cout << "Vector Max using CPU :"<<cpu_res<<" \n";
cout<<"GPU: "<<'\n';
//-------------------------------------------------------------------
// Allocate memory on the device
size_t bytes = sizeof(float) * N;
float* d_a;
hipMalloc(&d_a, bytes);
//-------------------------------------------------------------------
// Copy data from the host to the device (CPU to GPU)
hipMemcpy(d_a, a.data(), bytes, hipMemcpyHostToDevice);
cuda_vector_sum <<<1,N/2>>> (d_a,N);
hipMemcpy(&gpu_res, d_a, sizeof(float), hipMemcpyDeviceToHost);
cout << "Vector Sum using GPU :"<<gpu_res<<" \n";
//-------------------------------------------------------------------
cout << "Vector Average using GPU :"<<(double)gpu_res/(double)N<<" \n";
//-------------------------------------------------------------------
double mean = (double)gpu_res/(double)N;
hipMemcpy(d_a, a.data(), bytes, hipMemcpyHostToDevice);
cuda_update_arr<<<1,N>>>(d_a,mean);
cuda_vector_sum<<<1,N/2>>>(d_a,N);
hipMemcpy(&gpu_res, d_a, sizeof(float), hipMemcpyDeviceToHost);
gpu_res = (double)gpu_res/(double)N;
cout << "Vector Standard Deviation using GPU :"<<fixed<<setprecision(2)<<sqrt(gpu_res)<<" \n";
//-------------------------------------------------------------------
hipMemcpy(d_a, a.data(), bytes, hipMemcpyHostToDevice);
gpu_res = INT_MAX;
cuda_vector_min <<<1,N/2>>> (d_a,N);
hipMemcpy(&gpu_res, d_a, sizeof(float), hipMemcpyDeviceToHost);
cout << "Vector Min using GPU :"<<gpu_res<<" \n";
//-------------------------------------------------------------------
hipMemcpy(d_a, a.data(), bytes, hipMemcpyHostToDevice);
gpu_res = INT_MIN;
cuda_vector_max <<<1,N/2>>> (d_a,N);
hipMemcpy(&gpu_res, d_a, sizeof(float), hipMemcpyDeviceToHost);
cout << "Vector Max using GPU :"<<gpu_res<<" \n";
//-------------------------------------------------------------------
// Free memory on device
hipFree(d_a);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15cuda_vector_sumPfi
.globl _Z15cuda_vector_sumPfi
.p2align 8
.type _Z15cuda_vector_sumPfi,@function
_Z15cuda_vector_sumPfi:
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 2
s_cbranch_scc1 .LBB0_7
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_mov_b32 s4, 1
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v7, v1
global_store_b32 v[3:4], v1, off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s5
s_lshl_b32 s4, s4, 1
s_lshr_b32 s3, s3, 1
s_cmp_ge_i32 s4, s2
s_cbranch_scc1 .LBB0_7
.LBB0_4:
s_mov_b32 s5, exec_lo
v_cmpx_ge_u32_e64 s3, v0
s_cbranch_execz .LBB0_3
v_mul_lo_u32 v1, s4, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 1, v1
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v5, s4, v1
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_load_b32 v7, v[3:4], off
v_cmpx_gt_i32_e64 s2, v5
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
global_load_b32 v1, v[5:6], off
s_branch .LBB0_2
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15cuda_vector_sumPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 7
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15cuda_vector_sumPfi, .Lfunc_end0-_Z15cuda_vector_sumPfi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15cuda_vector_minPfi
.globl _Z15cuda_vector_minPfi
.p2align 8
.type _Z15cuda_vector_minPfi,@function
_Z15cuda_vector_minPfi:
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 2
s_cbranch_scc1 .LBB1_7
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_mov_b32 s4, 1
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_4
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s6
s_waitcnt vmcnt(0)
v_max_f32_e32 v1, v1, v1
v_max_f32_e32 v5, v7, v7
s_delay_alu instid0(VALU_DEP_1)
v_min_f32_e32 v1, v5, v1
global_store_b32 v[3:4], v1, off
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s5
s_lshl_b32 s4, s4, 1
s_lshr_b32 s3, s3, 1
s_cmp_ge_i32 s4, s2
s_cbranch_scc1 .LBB1_7
.LBB1_4:
s_mov_b32 s5, exec_lo
v_cmpx_ge_u32_e64 s3, v0
s_cbranch_execz .LBB1_3
v_mul_lo_u32 v1, s4, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 1, v1
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v5, s4, v1
v_mov_b32_e32 v1, 0x7f7fffff
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_load_b32 v7, v[3:4], off
v_cmpx_gt_i32_e64 s2, v5
s_cbranch_execz .LBB1_2
v_mov_b32_e32 v6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
global_load_b32 v1, v[5:6], off
s_branch .LBB1_2
.LBB1_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15cuda_vector_minPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 7
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15cuda_vector_minPfi, .Lfunc_end1-_Z15cuda_vector_minPfi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15cuda_vector_maxPfi
.globl _Z15cuda_vector_maxPfi
.p2align 8
.type _Z15cuda_vector_maxPfi,@function
_Z15cuda_vector_maxPfi:
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 2
s_cbranch_scc1 .LBB2_7
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_mov_b32 s4, 1
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_set_inst_prefetch_distance 0x1
s_branch .LBB2_4
.p2align 6
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s6
s_waitcnt vmcnt(0)
v_max_f32_e32 v1, v1, v1
v_max_f32_e32 v5, v7, v7
s_delay_alu instid0(VALU_DEP_1)
v_max_f32_e32 v1, v5, v1
global_store_b32 v[3:4], v1, off
.LBB2_3:
s_or_b32 exec_lo, exec_lo, s5
s_lshl_b32 s4, s4, 1
s_lshr_b32 s3, s3, 1
s_cmp_ge_i32 s4, s2
s_cbranch_scc1 .LBB2_7
.LBB2_4:
s_mov_b32 s5, exec_lo
v_cmpx_ge_u32_e64 s3, v0
s_cbranch_execz .LBB2_3
v_mul_lo_u32 v1, s4, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 1, v1
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v5, s4, v1
v_mov_b32_e32 v1, 0x800000
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_load_b32 v7, v[3:4], off
v_cmpx_gt_i32_e64 s2, v5
s_cbranch_execz .LBB2_2
v_mov_b32_e32 v6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
global_load_b32 v1, v[5:6], off
s_branch .LBB2_2
.LBB2_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15cuda_vector_maxPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 7
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z15cuda_vector_maxPfi, .Lfunc_end2-_Z15cuda_vector_maxPfi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15cuda_update_arrPfd
.globl _Z15cuda_update_arrPfd
.p2align 8
.type _Z15cuda_update_arrPfd,@function
_Z15cuda_update_arrPfd:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v0, v2, s[0:1]
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[0:1], v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], -s[2:3]
v_mul_f64 v[0:1], v[0:1], v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v0, v[0:1]
global_store_b32 v2, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15cuda_update_arrPfd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z15cuda_update_arrPfd, .Lfunc_end3-_Z15cuda_update_arrPfd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15cuda_vector_sumPfi
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: _Z15cuda_vector_sumPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15cuda_vector_minPfi
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: _Z15cuda_vector_minPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15cuda_vector_maxPfi
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: _Z15cuda_vector_maxPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15cuda_update_arrPfd
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z15cuda_update_arrPfd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<bits/stdc++.h>
using namespace std;
void vector_sum(vector<float> a,float &cpu_res,int n) {
for (int i = 0; i < n; i++) {
cpu_res += a[i];
}
}
void vector_min(vector<float> a,float &cpu_res,int n){
cpu_res = INT_MAX;
for (int i = 0; i < n; i++) {
cpu_res = min(cpu_res,a[i]);
}
}
void vector_max(vector<float> a,float &cpu_res,int n){
cpu_res = INT_MIN;
for (int i = 0; i < n; i++) {
cpu_res = max(cpu_res,a[i]);
}
}
void vector_sd(vector<float> a,float sum,double &cpu_res_sd,int n){
double mean = (double)sum/(double)n;
double s = 0;
for(int i=0;i<n;i++){
s += ((a[i]-mean)*(a[i]-mean));
}
cpu_res_sd = (double)s/(double)n;
}
__global__ void cuda_vector_sum(float* a,int n) {
const int tid=threadIdx.x;
int no_of_threads=blockDim.x;
for(int step=1;step < n; step *= 2,no_of_threads /= 2){
if (tid <= no_of_threads){
int ind=2*step*tid;
if((ind+step) >= n){
a[ind] = a[ind] + 0;
}else{
a[ind] = a[ind] + a[ind+step];
}
}
}
}
__global__ void cuda_vector_min(float* a,int n) {
const int tid=threadIdx.x;
int no_of_threads=blockDim.x;
for(int step=1;step < n; step *= 2,no_of_threads /= 2){
if (tid <= no_of_threads){
int ind=2*step*tid;
if((ind+step) >= n){
a[ind] = min(a[ind],FLT_MAX);
}else{
a[ind] = min(a[ind],a[ind+step]);
}
}
}
}
__global__ void cuda_vector_max(float* a,int n) {
const int tid=threadIdx.x;
int no_of_threads=blockDim.x;
for(int step=1;step < n; step *= 2,no_of_threads /= 2){
if (tid <= no_of_threads){
int ind=2*step*tid;
if((ind+step) >= n){
a[ind] = max(a[ind],FLT_MIN);
}else{
a[ind] = max(a[ind],a[ind+step]);
}
}
}
}
__global__ void cuda_update_arr(float *a,double mean){
const int tid=threadIdx.x;
a[tid] = (a[tid]-mean)*(a[tid]-mean);
}
int main() {
int N = 2048;
vector<float> a(N);
srand(time(0));
generate(begin(a), end(a), []() { return (float(rand())/float((RAND_MAX)) * 100.0); });
for(auto item:a)
cout<<item<<" ";
cout<<'\n';
float cpu_res=0,gpu_res=0;
double cpu_res_sd = 0,gpu_res_sd = 0;
cout<<"CPU: "<<'\n';
//-------------------------------------------------------------------
// Sum calculation
vector_sum(a,cpu_res,N);
cout << "Vector Sum using CPU :"<<cpu_res<<" \n";
// Average calculation
cout << "Vector Average using CPU :"<<(double)cpu_res/(double)N<<" \n";
vector_sd(a,cpu_res,cpu_res_sd,N);
cout << "Vector Standard Deviation using CPU :"<<fixed<<setprecision(2)<<sqrt(cpu_res_sd)<<" \n";
vector_min(a,cpu_res,N);
cout << "Vector Min using CPU :"<<cpu_res<<" \n";
vector_max(a,cpu_res,N);
cout << "Vector Max using CPU :"<<cpu_res<<" \n";
cout<<"GPU: "<<'\n';
//-------------------------------------------------------------------
// Allocate memory on the device
size_t bytes = sizeof(float) * N;
float* d_a;
hipMalloc(&d_a, bytes);
//-------------------------------------------------------------------
// Copy data from the host to the device (CPU to GPU)
hipMemcpy(d_a, a.data(), bytes, hipMemcpyHostToDevice);
cuda_vector_sum <<<1,N/2>>> (d_a,N);
hipMemcpy(&gpu_res, d_a, sizeof(float), hipMemcpyDeviceToHost);
cout << "Vector Sum using GPU :"<<gpu_res<<" \n";
//-------------------------------------------------------------------
cout << "Vector Average using GPU :"<<(double)gpu_res/(double)N<<" \n";
//-------------------------------------------------------------------
double mean = (double)gpu_res/(double)N;
hipMemcpy(d_a, a.data(), bytes, hipMemcpyHostToDevice);
cuda_update_arr<<<1,N>>>(d_a,mean);
cuda_vector_sum<<<1,N/2>>>(d_a,N);
hipMemcpy(&gpu_res, d_a, sizeof(float), hipMemcpyDeviceToHost);
gpu_res = (double)gpu_res/(double)N;
cout << "Vector Standard Deviation using GPU :"<<fixed<<setprecision(2)<<sqrt(gpu_res)<<" \n";
//-------------------------------------------------------------------
hipMemcpy(d_a, a.data(), bytes, hipMemcpyHostToDevice);
gpu_res = INT_MAX;
cuda_vector_min <<<1,N/2>>> (d_a,N);
hipMemcpy(&gpu_res, d_a, sizeof(float), hipMemcpyDeviceToHost);
cout << "Vector Min using GPU :"<<gpu_res<<" \n";
//-------------------------------------------------------------------
hipMemcpy(d_a, a.data(), bytes, hipMemcpyHostToDevice);
gpu_res = INT_MIN;
cuda_vector_max <<<1,N/2>>> (d_a,N);
hipMemcpy(&gpu_res, d_a, sizeof(float), hipMemcpyDeviceToHost);
cout << "Vector Max using GPU :"<<gpu_res<<" \n";
//-------------------------------------------------------------------
// Free memory on device
hipFree(d_a);
} | .text
.file "operations_on_Vector.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z10vector_sumSt6vectorIfSaIfEERfi # -- Begin function _Z10vector_sumSt6vectorIfSaIfEERfi
.p2align 4, 0x90
.type _Z10vector_sumSt6vectorIfSaIfEERfi,@function
_Z10vector_sumSt6vectorIfSaIfEERfi: # @_Z10vector_sumSt6vectorIfSaIfEERfi
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB0_3
# %bb.1: # %.lr.ph
movss (%rsi), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq (%rdi), %rax
movl %edx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
addss (%rax,%rdx,4), %xmm0
movss %xmm0, (%rsi)
incq %rdx
cmpq %rdx, %rcx
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z10vector_sumSt6vectorIfSaIfEERfi, .Lfunc_end0-_Z10vector_sumSt6vectorIfSaIfEERfi
.cfi_endproc
# -- End function
.globl _Z10vector_minSt6vectorIfSaIfEERfi # -- Begin function _Z10vector_minSt6vectorIfSaIfEERfi
.p2align 4, 0x90
.type _Z10vector_minSt6vectorIfSaIfEERfi,@function
_Z10vector_minSt6vectorIfSaIfEERfi: # @_Z10vector_minSt6vectorIfSaIfEERfi
.cfi_startproc
# %bb.0:
movl $1325400064, (%rsi) # imm = 0x4F000000
testl %edx, %edx
jle .LBB1_3
# %bb.1: # %.lr.ph
movq (%rdi), %rax
movss (%rsi), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl %edx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
minss (%rax,%rdx,4), %xmm0
movss %xmm0, (%rsi)
incq %rdx
cmpq %rdx, %rcx
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z10vector_minSt6vectorIfSaIfEERfi, .Lfunc_end1-_Z10vector_minSt6vectorIfSaIfEERfi
.cfi_endproc
# -- End function
.globl _Z10vector_maxSt6vectorIfSaIfEERfi # -- Begin function _Z10vector_maxSt6vectorIfSaIfEERfi
.p2align 4, 0x90
.type _Z10vector_maxSt6vectorIfSaIfEERfi,@function
_Z10vector_maxSt6vectorIfSaIfEERfi: # @_Z10vector_maxSt6vectorIfSaIfEERfi
.cfi_startproc
# %bb.0:
movl $-822083584, (%rsi) # imm = 0xCF000000
testl %edx, %edx
jle .LBB2_3
# %bb.1: # %.lr.ph
movq (%rdi), %rax
movss (%rsi), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl %edx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_2: # =>This Inner Loop Header: Depth=1
movss (%rax,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
maxss %xmm0, %xmm1
movss %xmm1, (%rsi)
incq %rdx
movaps %xmm1, %xmm0
cmpq %rdx, %rcx
jne .LBB2_2
.LBB2_3: # %._crit_edge
retq
.Lfunc_end2:
.size _Z10vector_maxSt6vectorIfSaIfEERfi, .Lfunc_end2-_Z10vector_maxSt6vectorIfSaIfEERfi
.cfi_endproc
# -- End function
.globl _Z9vector_sdSt6vectorIfSaIfEEfRdi # -- Begin function _Z9vector_sdSt6vectorIfSaIfEEfRdi
.p2align 4, 0x90
.type _Z9vector_sdSt6vectorIfSaIfEEfRdi,@function
_Z9vector_sdSt6vectorIfSaIfEEfRdi: # @_Z9vector_sdSt6vectorIfSaIfEEfRdi
.cfi_startproc
# %bb.0:
cvtsi2sd %edx, %xmm1
testl %edx, %edx
jle .LBB3_1
# %bb.3: # %.lr.ph
cvtss2sd %xmm0, %xmm2
divsd %xmm1, %xmm2
movq (%rdi), %rax
movl %edx, %ecx
xorps %xmm0, %xmm0
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_4: # =>This Inner Loop Header: Depth=1
movss (%rax,%rdx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
cvtss2sd %xmm3, %xmm3
subsd %xmm2, %xmm3
mulsd %xmm3, %xmm3
addsd %xmm3, %xmm0
incq %rdx
cmpq %rdx, %rcx
jne .LBB3_4
jmp .LBB3_2
.LBB3_1:
xorps %xmm0, %xmm0
.LBB3_2: # %._crit_edge
divsd %xmm1, %xmm0
movsd %xmm0, (%rsi)
retq
.Lfunc_end3:
.size _Z9vector_sdSt6vectorIfSaIfEEfRdi, .Lfunc_end3-_Z9vector_sdSt6vectorIfSaIfEEfRdi
.cfi_endproc
# -- End function
.globl _Z30__device_stub__cuda_vector_sumPfi # -- Begin function _Z30__device_stub__cuda_vector_sumPfi
.p2align 4, 0x90
.type _Z30__device_stub__cuda_vector_sumPfi,@function
_Z30__device_stub__cuda_vector_sumPfi: # @_Z30__device_stub__cuda_vector_sumPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15cuda_vector_sumPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z30__device_stub__cuda_vector_sumPfi, .Lfunc_end4-_Z30__device_stub__cuda_vector_sumPfi
.cfi_endproc
# -- End function
.globl _Z30__device_stub__cuda_vector_minPfi # -- Begin function _Z30__device_stub__cuda_vector_minPfi
.p2align 4, 0x90
.type _Z30__device_stub__cuda_vector_minPfi,@function
_Z30__device_stub__cuda_vector_minPfi: # @_Z30__device_stub__cuda_vector_minPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15cuda_vector_minPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end5:
.size _Z30__device_stub__cuda_vector_minPfi, .Lfunc_end5-_Z30__device_stub__cuda_vector_minPfi
.cfi_endproc
# -- End function
.globl _Z30__device_stub__cuda_vector_maxPfi # -- Begin function _Z30__device_stub__cuda_vector_maxPfi
.p2align 4, 0x90
.type _Z30__device_stub__cuda_vector_maxPfi,@function
_Z30__device_stub__cuda_vector_maxPfi: # @_Z30__device_stub__cuda_vector_maxPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15cuda_vector_maxPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end6:
.size _Z30__device_stub__cuda_vector_maxPfi, .Lfunc_end6-_Z30__device_stub__cuda_vector_maxPfi
.cfi_endproc
# -- End function
.globl _Z30__device_stub__cuda_update_arrPfd # -- Begin function _Z30__device_stub__cuda_update_arrPfd
.p2align 4, 0x90
.type _Z30__device_stub__cuda_update_arrPfd,@function
_Z30__device_stub__cuda_update_arrPfd: # @_Z30__device_stub__cuda_update_arrPfd
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movsd %xmm0, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15cuda_update_arrPfd, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end7:
.size _Z30__device_stub__cuda_update_arrPfd, .Lfunc_end7-_Z30__device_stub__cuda_update_arrPfd
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI8_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI8_1:
.long 0x42c80000 # float 100
.LCPI8_3:
.long 0x4f000000 # float 2.14748365E+9
.LCPI8_4:
.long 0xcf000000 # float -2.14748365E+9
.LCPI8_5:
.long 0x3a000000 # float 4.8828125E-4
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI8_2:
.quad 0x3f40000000000000 # double 4.8828125E-4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt6vectorIfSaIfEEC2EmRKS0_.exit
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
.cfi_escape 0x2e, 0x00
movl $8192, %edi # imm = 0x2000
callq _Znwm
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
xorl %r14d, %r14d
movl $8192, %edx # imm = 0x2000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.cfi_escape 0x2e, 0x00
xorl %edi, %edi
callq time
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB8_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI8_0(%rip), %xmm0
mulss .LCPI8_1(%rip), %xmm0
movss %xmm0, (%rbx,%r14)
addq $4, %r14
cmpq $8192, %r14 # imm = 0x2000
jne .LBB8_1
# %bb.2: # %_ZSt8generateIN9__gnu_cxx17__normal_iteratorIPfSt6vectorIfSaIfEEEEZ4mainEUlvE_EvT_S8_T0_.exit.preheader.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB8_3: # %_ZSt8generateIN9__gnu_cxx17__normal_iteratorIPfSt6vectorIfSaIfEEEEZ4mainEUlvE_EvT_S8_T0_.exit.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp1:
# %bb.4: # %_ZNSolsEf.exit
# in Loop: Header=BB8_3 Depth=1
.Ltmp2:
.cfi_escape 0x2e, 0x00
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp3:
# %bb.5: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB8_3 Depth=1
addq $4, %r14
cmpq $8192, %r14 # imm = 0x2000
jne .LBB8_3
# %bb.6:
movb $10, 32(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB8_8
# %bb.7:
.Ltmp5:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rsi
movl $_ZSt4cout, %edi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp6:
jmp .LBB8_9
.LBB8_8:
.Ltmp7:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
.Ltmp8:
.LBB8_9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
movl $0, 12(%rsp)
.Ltmp10:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp11:
# %bb.10: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit69
movb $10, 32(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB8_14
# %bb.11:
.Ltmp12:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rsi
movl $_ZSt4cout, %edi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp13:
jmp .LBB8_15
.LBB8_14:
.Ltmp14:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
.Ltmp15:
.LBB8_15: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit74
.Ltmp16:
.cfi_escape 0x2e, 0x00
movl $8192, %edi # imm = 0x2000
callq _Znwm
.Ltmp17:
# %bb.16: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.i
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $8192, %edx # imm = 0x2000
movq %rax, %rdi
movq %rbx, %rsi
callq memcpy@PLT
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB8_17: # =>This Inner Loop Header: Depth=1
addss (%r14,%rax,4), %xmm0
incq %rax
cmpq $2048, %rax # imm = 0x800
jne .LBB8_17
# %bb.18: # %_Z10vector_sumSt6vectorIfSaIfEERfi.exit
movss %xmm0, 24(%rsp) # 4-byte Spill
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.Ltmp18:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp19:
# %bb.19: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit80
movss 24(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp20:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movsd %xmm0, 24(%rsp) # 8-byte Spill
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp21:
# %bb.20: # %_ZNSolsEf.exit82
.Ltmp22:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp23:
# %bb.21: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit84
.Ltmp24:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp25:
# %bb.22: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit86
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI8_2(%rip), %xmm0
.Ltmp26:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movsd %xmm0, 24(%rsp) # 8-byte Spill
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp27:
# %bb.23: # %_ZNSolsEd.exit
.Ltmp28:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp29:
# %bb.24: # %_ZNSt16allocator_traitsISaIfEE8allocateERS0_m.exit.i.i.i.i91
.Ltmp30:
.cfi_escape 0x2e, 0x00
movl $8192, %edi # imm = 0x2000
callq _Znwm
.Ltmp31:
# %bb.25: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.i92
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $8192, %edx # imm = 0x2000
movq %rax, %rdi
movq %rbx, %rsi
callq memcpy@PLT
xorpd %xmm2, %xmm2
xorl %eax, %eax
movsd 24(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB8_26: # =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
subsd %xmm1, %xmm0
mulsd %xmm0, %xmm0
addsd %xmm0, %xmm2
incq %rax
cmpq $2048, %rax # imm = 0x800
jne .LBB8_26
# %bb.27: # %_Z9vector_sdSt6vectorIfSaIfEEfRdi.exit
movsd %xmm2, 24(%rsp) # 8-byte Spill
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.Ltmp32:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $37, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp33:
# %bb.28: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit106
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI8_2(%rip), %xmm0
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rcx
movl $-261, %edx # imm = 0xFEFB
andl _ZSt4cout+24(%rcx), %edx
orl $4, %edx
movl %edx, _ZSt4cout+24(%rcx)
movq -24(%rax), %rax
movq $2, _ZSt4cout+8(%rax)
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB8_30
# %bb.29:
sqrtsd %xmm0, %xmm0
jmp .LBB8_31
.LBB8_30: # %call.sqrt
.cfi_escape 0x2e, 0x00
callq sqrt
.LBB8_31: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit106.split
.Ltmp34:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp35:
# %bb.32: # %_ZNSolsEd.exit109
.Ltmp36:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp37:
# %bb.33: # %_ZNSt16allocator_traitsISaIfEE8allocateERS0_m.exit.i.i.i.i113
.Ltmp38:
.cfi_escape 0x2e, 0x00
movl $8192, %edi # imm = 0x2000
callq _Znwm
.Ltmp39:
# %bb.34: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.i114
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $8192, %edx # imm = 0x2000
movq %rax, %rdi
movq %rbx, %rsi
callq memcpy@PLT
movss .LCPI8_3(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %eax, %eax
.p2align 4, 0x90
.LBB8_35: # =>This Inner Loop Header: Depth=1
minss (%r14,%rax,4), %xmm0
incq %rax
cmpq $2048, %rax # imm = 0x800
jne .LBB8_35
# %bb.36: # %_Z10vector_minSt6vectorIfSaIfEERfi.exit
movss %xmm0, 24(%rsp) # 4-byte Spill
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.Ltmp40:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp41:
# %bb.37: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit129
movss 24(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp42:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp43:
# %bb.38: # %_ZNSolsEf.exit131
.Ltmp44:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp45:
# %bb.39: # %_ZNSt16allocator_traitsISaIfEE8allocateERS0_m.exit.i.i.i.i135
.Ltmp46:
.cfi_escape 0x2e, 0x00
movl $8192, %edi # imm = 0x2000
callq _Znwm
.Ltmp47:
# %bb.40: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.i136
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $8192, %edx # imm = 0x2000
movq %rax, %rdi
movq %rbx, %rsi
callq memcpy@PLT
movss .LCPI8_4(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorl %eax, %eax
.p2align 4, 0x90
.LBB8_41: # =>This Inner Loop Header: Depth=1
movaps %xmm1, %xmm0
movss (%r14,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
maxss %xmm0, %xmm1
incq %rax
cmpq $2048, %rax # imm = 0x800
jne .LBB8_41
# %bb.42: # %_Z10vector_maxSt6vectorIfSaIfEERfi.exit
movss %xmm1, 24(%rsp) # 4-byte Spill
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.Ltmp48:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp49:
# %bb.43: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit151
movss 24(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp50:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp51:
# %bb.44: # %_ZNSolsEf.exit153
.Ltmp52:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp53:
# %bb.45: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit155
.Ltmp54:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp55:
# %bb.46: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit157
movb $10, 32(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB8_48
# %bb.47:
.Ltmp56:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rsi
movl $_ZSt4cout, %edi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp57:
jmp .LBB8_49
.LBB8_48:
.Ltmp58:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
.Ltmp59:
.LBB8_49: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit162
.Ltmp61:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
.Ltmp62:
# %bb.50: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit
movq 16(%rsp), %rdi
.Ltmp63:
.cfi_escape 0x2e, 0x00
movl $8192, %edx # imm = 0x2000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp64:
# %bb.51:
.Ltmp65:
.cfi_escape 0x2e, 0x00
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $4294968320, %rdx # imm = 0x100000400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp66:
# %bb.52:
testl %eax, %eax
jne .LBB8_55
# %bb.53:
movq 16(%rsp), %rax
movq %rax, 112(%rsp)
movl $2048, 56(%rsp) # imm = 0x800
leaq 112(%rsp), %rax
movq %rax, 32(%rsp)
leaq 56(%rsp), %rax
movq %rax, 40(%rsp)
.Ltmp67:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp68:
# %bb.54: # %.noexc164
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
.Ltmp69:
.cfi_escape 0x2e, 0x10
leaq 32(%rsp), %r9
movl $_Z15cuda_vector_sumPfi, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp70:
.LBB8_55:
movq 16(%rsp), %rsi
.Ltmp71:
.cfi_escape 0x2e, 0x00
leaq 12(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
.Ltmp72:
# %bb.56:
.Ltmp73:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp74:
# %bb.57: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit171
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp75:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp76:
# %bb.58: # %_ZNSolsEf.exit173
.Ltmp77:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp78:
# %bb.59: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit175
.Ltmp79:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp80:
# %bb.60: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit177
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
mulsd .LCPI8_2(%rip), %xmm0
.Ltmp81:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp82:
# %bb.61: # %_ZNSolsEd.exit179
.Ltmp83:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp84:
# %bb.62: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit181
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 24(%rsp) # 4-byte Spill
movq 16(%rsp), %rdi
.Ltmp86:
.cfi_escape 0x2e, 0x00
movl $8192, %edx # imm = 0x2000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp87:
# %bb.63:
.Ltmp88:
.cfi_escape 0x2e, 0x00
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $4294969344, %rdx # imm = 0x100000800
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp89:
# %bb.64:
testl %eax, %eax
jne .LBB8_67
# %bb.65:
movss 24(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
mulsd .LCPI8_2(%rip), %xmm0
movq 16(%rsp), %rax
movq %rax, 112(%rsp)
movsd %xmm0, 72(%rsp)
leaq 112(%rsp), %rax
movq %rax, 32(%rsp)
leaq 72(%rsp), %rax
movq %rax, 40(%rsp)
.Ltmp90:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp91:
# %bb.66: # %.noexc188
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
.Ltmp92:
.cfi_escape 0x2e, 0x10
leaq 32(%rsp), %r9
movl $_Z15cuda_update_arrPfd, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp93:
.LBB8_67:
.Ltmp94:
.cfi_escape 0x2e, 0x00
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $4294968320, %rdx # imm = 0x100000400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp95:
# %bb.68:
testl %eax, %eax
jne .LBB8_71
# %bb.69:
movq 16(%rsp), %rax
movq %rax, 112(%rsp)
movl $2048, 56(%rsp) # imm = 0x800
leaq 112(%rsp), %rax
movq %rax, 32(%rsp)
leaq 56(%rsp), %rax
movq %rax, 40(%rsp)
.Ltmp96:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp97:
# %bb.70: # %.noexc196
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
.Ltmp98:
.cfi_escape 0x2e, 0x10
leaq 32(%rsp), %r9
movl $_Z15cuda_vector_sumPfi, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp99:
.LBB8_71:
movq 16(%rsp), %rsi
.Ltmp100:
.cfi_escape 0x2e, 0x00
leaq 12(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
.Ltmp101:
# %bb.72:
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss .LCPI8_5(%rip), %xmm0
movss %xmm0, 12(%rsp)
.Ltmp102:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
movl $37, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp103:
# %bb.73: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit200
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rcx
movl $-261, %edx # imm = 0xFEFB
andl _ZSt4cout+24(%rcx), %edx
orl $4, %edx
movl %edx, _ZSt4cout+24(%rcx)
movq -24(%rax), %rax
movq $2, _ZSt4cout+8(%rax)
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
ucomiss %xmm1, %xmm0
jb .LBB8_77
# %bb.74:
sqrtss %xmm0, %xmm0
jmp .LBB8_78
.LBB8_77: # %call.sqrt334
.cfi_escape 0x2e, 0x00
callq sqrtf
.LBB8_78: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit200.split
cvtss2sd %xmm0, %xmm0
.Ltmp104:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp105:
# %bb.79: # %_ZNSolsEf.exit204
.Ltmp106:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp107:
# %bb.80: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit206
movq 16(%rsp), %rdi
.Ltmp108:
.cfi_escape 0x2e, 0x00
movl $8192, %edx # imm = 0x2000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp109:
# %bb.81:
movl $1325400064, 12(%rsp) # imm = 0x4F000000
.Ltmp110:
.cfi_escape 0x2e, 0x00
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $4294968320, %rdx # imm = 0x100000400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp111:
# %bb.82:
testl %eax, %eax
jne .LBB8_85
# %bb.83:
movq 16(%rsp), %rax
movq %rax, 112(%rsp)
movl $2048, 56(%rsp) # imm = 0x800
leaq 112(%rsp), %rax
movq %rax, 32(%rsp)
leaq 56(%rsp), %rax
movq %rax, 40(%rsp)
.Ltmp112:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp113:
# %bb.84: # %.noexc213
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
.Ltmp114:
.cfi_escape 0x2e, 0x10
leaq 32(%rsp), %r9
movl $_Z15cuda_vector_minPfi, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp115:
.LBB8_85:
movq 16(%rsp), %rsi
.Ltmp116:
.cfi_escape 0x2e, 0x00
leaq 12(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
.Ltmp117:
# %bb.86:
.Ltmp118:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.12, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp119:
# %bb.87: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit216
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp120:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp121:
# %bb.88: # %_ZNSolsEf.exit218
.Ltmp122:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp123:
# %bb.89: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit220
movq 16(%rsp), %rdi
.Ltmp124:
.cfi_escape 0x2e, 0x00
movl $8192, %edx # imm = 0x2000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp125:
# %bb.90:
movl $-822083584, 12(%rsp) # imm = 0xCF000000
.Ltmp126:
.cfi_escape 0x2e, 0x00
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $4294968320, %rdx # imm = 0x100000400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp127:
# %bb.91:
testl %eax, %eax
jne .LBB8_94
# %bb.92:
movq 16(%rsp), %rax
movq %rax, 112(%rsp)
movl $2048, 56(%rsp) # imm = 0x800
leaq 112(%rsp), %rax
movq %rax, 32(%rsp)
leaq 56(%rsp), %rax
movq %rax, 40(%rsp)
.Ltmp128:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp129:
# %bb.93: # %.noexc227
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
.Ltmp130:
.cfi_escape 0x2e, 0x10
leaq 32(%rsp), %r9
movl $_Z15cuda_vector_maxPfi, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp131:
.LBB8_94:
movq 16(%rsp), %rsi
.Ltmp132:
.cfi_escape 0x2e, 0x00
leaq 12(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
.Ltmp133:
# %bb.95:
.Ltmp134:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.13, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp135:
# %bb.96: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit230
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp136:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp137:
# %bb.97: # %_ZNSolsEf.exit232
.Ltmp138:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp139:
# %bb.98: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit234
movq 16(%rsp), %rdi
.Ltmp140:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp141:
# %bb.99: # %_ZNSt6vectorIfSaIfEED2Ev.exit236
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB8_12:
.cfi_def_cfa_offset 144
.Ltmp9:
jmp .LBB8_101
.LBB8_100:
.Ltmp85:
jmp .LBB8_101
.LBB8_76:
.Ltmp142:
jmp .LBB8_101
.LBB8_75:
.Ltmp60:
jmp .LBB8_101
.LBB8_13:
.Ltmp4:
.LBB8_101: # %_ZNSt6vectorIfSaIfEED2Ev.exit238
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end8:
.size main, .Lfunc_end8-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table8:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp8-.Ltmp5 # Call between .Ltmp5 and .Ltmp8
.uleb128 .Ltmp9-.Lfunc_begin0 # jumps to .Ltmp9
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp17-.Ltmp10 # Call between .Ltmp10 and .Ltmp17
.uleb128 .Ltmp60-.Lfunc_begin0 # jumps to .Ltmp60
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp18-.Ltmp17 # Call between .Ltmp17 and .Ltmp18
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp31-.Ltmp18 # Call between .Ltmp18 and .Ltmp31
.uleb128 .Ltmp60-.Lfunc_begin0 # jumps to .Ltmp60
.byte 0 # On action: cleanup
.uleb128 .Ltmp31-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp32-.Ltmp31 # Call between .Ltmp31 and .Ltmp32
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp32-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp39-.Ltmp32 # Call between .Ltmp32 and .Ltmp39
.uleb128 .Ltmp60-.Lfunc_begin0 # jumps to .Ltmp60
.byte 0 # On action: cleanup
.uleb128 .Ltmp39-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp40-.Ltmp39 # Call between .Ltmp39 and .Ltmp40
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp40-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp47-.Ltmp40 # Call between .Ltmp40 and .Ltmp47
.uleb128 .Ltmp60-.Lfunc_begin0 # jumps to .Ltmp60
.byte 0 # On action: cleanup
.uleb128 .Ltmp47-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp48-.Ltmp47 # Call between .Ltmp47 and .Ltmp48
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp48-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp59-.Ltmp48 # Call between .Ltmp48 and .Ltmp59
.uleb128 .Ltmp60-.Lfunc_begin0 # jumps to .Ltmp60
.byte 0 # On action: cleanup
.uleb128 .Ltmp61-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp84-.Ltmp61 # Call between .Ltmp61 and .Ltmp84
.uleb128 .Ltmp85-.Lfunc_begin0 # jumps to .Ltmp85
.byte 0 # On action: cleanup
.uleb128 .Ltmp86-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp141-.Ltmp86 # Call between .Ltmp86 and .Ltmp141
.uleb128 .Ltmp142-.Lfunc_begin0 # jumps to .Ltmp142
.byte 0 # On action: cleanup
.uleb128 .Ltmp141-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Lfunc_end8-.Ltmp141 # Call between .Ltmp141 and .Lfunc_end8
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15cuda_vector_sumPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15cuda_vector_minPfi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15cuda_vector_maxPfi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15cuda_update_arrPfd, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15cuda_vector_sumPfi,@object # @_Z15cuda_vector_sumPfi
.section .rodata,"a",@progbits
.globl _Z15cuda_vector_sumPfi
.p2align 3, 0x0
_Z15cuda_vector_sumPfi:
.quad _Z30__device_stub__cuda_vector_sumPfi
.size _Z15cuda_vector_sumPfi, 8
.type _Z15cuda_vector_minPfi,@object # @_Z15cuda_vector_minPfi
.globl _Z15cuda_vector_minPfi
.p2align 3, 0x0
_Z15cuda_vector_minPfi:
.quad _Z30__device_stub__cuda_vector_minPfi
.size _Z15cuda_vector_minPfi, 8
.type _Z15cuda_vector_maxPfi,@object # @_Z15cuda_vector_maxPfi
.globl _Z15cuda_vector_maxPfi
.p2align 3, 0x0
_Z15cuda_vector_maxPfi:
.quad _Z30__device_stub__cuda_vector_maxPfi
.size _Z15cuda_vector_maxPfi, 8
.type _Z15cuda_update_arrPfd,@object # @_Z15cuda_update_arrPfd
.globl _Z15cuda_update_arrPfd
.p2align 3, 0x0
_Z15cuda_update_arrPfd:
.quad _Z30__device_stub__cuda_update_arrPfd
.size _Z15cuda_update_arrPfd, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CPU: "
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Vector Sum using CPU :"
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " \n"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Vector Average using CPU :"
.size .L.str.4, 27
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Vector Standard Deviation using CPU :"
.size .L.str.5, 38
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Vector Min using CPU :"
.size .L.str.6, 23
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Vector Max using CPU :"
.size .L.str.7, 23
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "GPU: "
.size .L.str.8, 6
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Vector Sum using GPU :"
.size .L.str.9, 23
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Vector Average using GPU :"
.size .L.str.10, 27
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Vector Standard Deviation using GPU :"
.size .L.str.11, 38
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Vector Min using GPU :"
.size .L.str.12, 23
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Vector Max using GPU :"
.size .L.str.13, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15cuda_vector_sumPfi"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15cuda_vector_minPfi"
.size .L__unnamed_2, 23
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z15cuda_vector_maxPfi"
.size .L__unnamed_3, 23
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z15cuda_update_arrPfd"
.size .L__unnamed_4, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__cuda_vector_sumPfi
.addrsig_sym _Z30__device_stub__cuda_vector_minPfi
.addrsig_sym _Z30__device_stub__cuda_vector_maxPfi
.addrsig_sym _Z30__device_stub__cuda_update_arrPfd
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z15cuda_vector_sumPfi
.addrsig_sym _Z15cuda_vector_minPfi
.addrsig_sym _Z15cuda_vector_maxPfi
.addrsig_sym _Z15cuda_update_arrPfd
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15cuda_update_arrPfd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0203 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0060*/ F2F.F64.F32 R4, R0 ; /* 0x0000000000047310 */
/* 0x004e240000201800 */
/*0070*/ DADD R4, R4, -c[0x0][0x168] ; /* 0x80005a0004047629 */
/* 0x001e0c0000000000 */
/*0080*/ DMUL R4, R4, R4 ; /* 0x0000000404047228 */
/* 0x001e140000000000 */
/*0090*/ F2F.F32.F64 R5, R4 ; /* 0x0000000400057310 */
/* 0x001e240000301000 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15cuda_vector_maxPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0050*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fe200000001ff */
/*0060*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0080*/ ISETP.GT.AND P0, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x001fe2000bf04270 */
/*0090*/ BSSY B0, 0x190 ; /* 0x000000f000007945 */
/* 0x000fd80003800000 */
/*00a0*/ @P0 BRA 0x180 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD R0, R7, R6, RZ ; /* 0x0000000607007224 */
/* 0x000fe400078e02ff */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*00d0*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fca00000006ff */
/*00e0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0205 */
/*00f0*/ LDG.E R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IMAD.IADD R0, R0, 0x1, R7 ; /* 0x0000000100007824 */
/* 0x000fca00078e0207 */
/*0110*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0120*/ @!P0 IMAD.WIDE R2, R7, 0x4, R4 ; /* 0x0000000407028825 */
/* 0x000fe200078e0204 */
/*0130*/ @P0 FMNMX R11, R9, 1.175494350822287508e-38, !PT ; /* 0x00800000090b0809 */
/* 0x004fca0007800000 */
/*0140*/ @P0 STG.E [R4.64], R11 ; /* 0x0000000b04000986 */
/* 0x0001e8000c101906 */
/*0150*/ @!P0 LDG.E R2, [R2.64] ; /* 0x0000000602028981 */
/* 0x000ea4000c1e1900 */
/*0160*/ @!P0 FMNMX R9, R9, R2, !PT ; /* 0x0000000209098209 */
/* 0x004fca0007800000 */
/*0170*/ @!P0 STG.E [R4.64], R9 ; /* 0x0000000904008986 */
/* 0x0001e4000c101906 */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0190*/ SHF.L.U32 R7, R7, 0x1, RZ ; /* 0x0000000107077819 */
/* 0x000fe200000006ff */
/*01a0*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fc6000f8f083f */
/*01b0*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fe20003f06270 */
/*01c0*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fd80008011404 */
/*01d0*/ @!P0 BRA 0x80 ; /* 0xfffffea000008947 */
/* 0x000fea000383ffff */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15cuda_vector_minPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0050*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fe200000001ff */
/*0060*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0080*/ ISETP.GT.AND P0, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x001fe2000bf04270 */
/*0090*/ BSSY B0, 0x190 ; /* 0x000000f000007945 */
/* 0x000fd80003800000 */
/*00a0*/ @P0 BRA 0x180 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD R0, R7, R6, RZ ; /* 0x0000000607007224 */
/* 0x000fe400078e02ff */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*00d0*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fca00000006ff */
/*00e0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0205 */
/*00f0*/ LDG.E R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IMAD.IADD R0, R0, 0x1, R7 ; /* 0x0000000100007824 */
/* 0x000fca00078e0207 */
/*0110*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0120*/ @!P0 IMAD.WIDE R2, R7, 0x4, R4 ; /* 0x0000000407028825 */
/* 0x000fe200078e0204 */
/*0130*/ @P0 FMNMX R11, R9, 3.40282346638528859812e+38, PT ; /* 0x7f7fffff090b0809 */
/* 0x004fca0003800000 */
/*0140*/ @P0 STG.E [R4.64], R11 ; /* 0x0000000b04000986 */
/* 0x0001e8000c101906 */
/*0150*/ @!P0 LDG.E R2, [R2.64] ; /* 0x0000000602028981 */
/* 0x000ea4000c1e1900 */
/*0160*/ @!P0 FMNMX R9, R9, R2, PT ; /* 0x0000000209098209 */
/* 0x004fca0003800000 */
/*0170*/ @!P0 STG.E [R4.64], R9 ; /* 0x0000000904008986 */
/* 0x0001e4000c101906 */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0190*/ SHF.L.U32 R7, R7, 0x1, RZ ; /* 0x0000000107077819 */
/* 0x000fe200000006ff */
/*01a0*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fc6000f8f083f */
/*01b0*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fe20003f06270 */
/*01c0*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fd80008011404 */
/*01d0*/ @!P0 BRA 0x80 ; /* 0xfffffea000008947 */
/* 0x000fea000383ffff */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15cuda_vector_sumPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R0, c[0x0][0x168] ; /* 0x00005a0000007a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0050*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe200078e00ff */
/*0060*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0080*/ ISETP.GT.AND P0, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x001fe2000bf04270 */
/*0090*/ BSSY B0, 0x190 ; /* 0x000000f000007945 */
/* 0x000fd80003800000 */
/*00a0*/ @P0 BRA 0x180 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD R0, R7, R6, RZ ; /* 0x0000000607007224 */
/* 0x000fc800078e02ff */
/*00d0*/ IMAD.SHL.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007824 */
/* 0x000fca00078e00ff */
/*00e0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0205 */
/*00f0*/ LDG.E R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IADD3 R0, R0, R7, RZ ; /* 0x0000000700007210 */
/* 0x000fc80007ffe0ff */
/*0110*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0120*/ @!P0 IMAD.WIDE R2, R7, 0x4, R4 ; /* 0x0000000407028825 */
/* 0x000fc800078e0204 */
/*0130*/ @P0 FADD R11, RZ, R9 ; /* 0x00000009ff0b0221 */
/* 0x004fca0000000000 */
/*0140*/ @P0 STG.E [R4.64], R11 ; /* 0x0000000b04000986 */
/* 0x0001e8000c101906 */
/*0150*/ @!P0 LDG.E R2, [R2.64] ; /* 0x0000000602028981 */
/* 0x000ea4000c1e1900 */
/*0160*/ @!P0 FADD R9, R9, R2 ; /* 0x0000000209098221 */
/* 0x004fca0000000000 */
/*0170*/ @!P0 STG.E [R4.64], R9 ; /* 0x0000000904008986 */
/* 0x0001e4000c101906 */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0190*/ IMAD.SHL.U32 R7, R7, 0x2, RZ ; /* 0x0000000207077824 */
/* 0x000fe200078e00ff */
/*01a0*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fc8000f8f083f */
/*01b0*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fe20003f06270 */
/*01c0*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fd80008011404 */
/*01d0*/ @!P0 BRA 0x80 ; /* 0xfffffea000008947 */
/* 0x000fea000383ffff */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15cuda_vector_sumPfi
.globl _Z15cuda_vector_sumPfi
.p2align 8
.type _Z15cuda_vector_sumPfi,@function
_Z15cuda_vector_sumPfi:
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 2
s_cbranch_scc1 .LBB0_7
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_mov_b32 s4, 1
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v7, v1
global_store_b32 v[3:4], v1, off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s5
s_lshl_b32 s4, s4, 1
s_lshr_b32 s3, s3, 1
s_cmp_ge_i32 s4, s2
s_cbranch_scc1 .LBB0_7
.LBB0_4:
s_mov_b32 s5, exec_lo
v_cmpx_ge_u32_e64 s3, v0
s_cbranch_execz .LBB0_3
v_mul_lo_u32 v1, s4, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 1, v1
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v5, s4, v1
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_load_b32 v7, v[3:4], off
v_cmpx_gt_i32_e64 s2, v5
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
global_load_b32 v1, v[5:6], off
s_branch .LBB0_2
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15cuda_vector_sumPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 7
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15cuda_vector_sumPfi, .Lfunc_end0-_Z15cuda_vector_sumPfi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15cuda_vector_minPfi
.globl _Z15cuda_vector_minPfi
.p2align 8
.type _Z15cuda_vector_minPfi,@function
_Z15cuda_vector_minPfi:
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 2
s_cbranch_scc1 .LBB1_7
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_mov_b32 s4, 1
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_4
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s6
s_waitcnt vmcnt(0)
v_max_f32_e32 v1, v1, v1
v_max_f32_e32 v5, v7, v7
s_delay_alu instid0(VALU_DEP_1)
v_min_f32_e32 v1, v5, v1
global_store_b32 v[3:4], v1, off
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s5
s_lshl_b32 s4, s4, 1
s_lshr_b32 s3, s3, 1
s_cmp_ge_i32 s4, s2
s_cbranch_scc1 .LBB1_7
.LBB1_4:
s_mov_b32 s5, exec_lo
v_cmpx_ge_u32_e64 s3, v0
s_cbranch_execz .LBB1_3
v_mul_lo_u32 v1, s4, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 1, v1
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v5, s4, v1
v_mov_b32_e32 v1, 0x7f7fffff
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_load_b32 v7, v[3:4], off
v_cmpx_gt_i32_e64 s2, v5
s_cbranch_execz .LBB1_2
v_mov_b32_e32 v6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
global_load_b32 v1, v[5:6], off
s_branch .LBB1_2
.LBB1_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15cuda_vector_minPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 7
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15cuda_vector_minPfi, .Lfunc_end1-_Z15cuda_vector_minPfi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15cuda_vector_maxPfi
.globl _Z15cuda_vector_maxPfi
.p2align 8
.type _Z15cuda_vector_maxPfi,@function
_Z15cuda_vector_maxPfi:
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 2
s_cbranch_scc1 .LBB2_7
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_mov_b32 s4, 1
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_set_inst_prefetch_distance 0x1
s_branch .LBB2_4
.p2align 6
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s6
s_waitcnt vmcnt(0)
v_max_f32_e32 v1, v1, v1
v_max_f32_e32 v5, v7, v7
s_delay_alu instid0(VALU_DEP_1)
v_max_f32_e32 v1, v5, v1
global_store_b32 v[3:4], v1, off
.LBB2_3:
s_or_b32 exec_lo, exec_lo, s5
s_lshl_b32 s4, s4, 1
s_lshr_b32 s3, s3, 1
s_cmp_ge_i32 s4, s2
s_cbranch_scc1 .LBB2_7
.LBB2_4:
s_mov_b32 s5, exec_lo
v_cmpx_ge_u32_e64 s3, v0
s_cbranch_execz .LBB2_3
v_mul_lo_u32 v1, s4, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 1, v1
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v5, s4, v1
v_mov_b32_e32 v1, 0x800000
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_load_b32 v7, v[3:4], off
v_cmpx_gt_i32_e64 s2, v5
s_cbranch_execz .LBB2_2
v_mov_b32_e32 v6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
global_load_b32 v1, v[5:6], off
s_branch .LBB2_2
.LBB2_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15cuda_vector_maxPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 7
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z15cuda_vector_maxPfi, .Lfunc_end2-_Z15cuda_vector_maxPfi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15cuda_update_arrPfd
.globl _Z15cuda_update_arrPfd
.p2align 8
.type _Z15cuda_update_arrPfd,@function
_Z15cuda_update_arrPfd:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v0, v2, s[0:1]
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[0:1], v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], -s[2:3]
v_mul_f64 v[0:1], v[0:1], v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v0, v[0:1]
global_store_b32 v2, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15cuda_update_arrPfd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z15cuda_update_arrPfd, .Lfunc_end3-_Z15cuda_update_arrPfd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15cuda_vector_sumPfi
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: _Z15cuda_vector_sumPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15cuda_vector_minPfi
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: _Z15cuda_vector_minPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15cuda_vector_maxPfi
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: _Z15cuda_vector_maxPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15cuda_update_arrPfd
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z15cuda_update_arrPfd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
/*wave kernel*/
__global__ void sin_dist(float *wa)
{
/*calculate 2d arrray index from thread and block IDs*/
const int j = threadIdx.y+(blockIdx.y*gridDim.y);
const int i = threadIdx.x+(blockIdx.x*gridDim.x);
/*calculate mapping to 1d array from 2d indicies*/
const int lID = i+(j*blockDim.y*gridDim.y);
/*define the wave sources*/
float pa[] = {100,150};
float pb[] = {200,150};
/*calculate value at location*/
float adist = sqrt( ((i-pa[0])*(i-pa[0]))+((j-pa[1])*(j-pa[1])) );
float bdist = sqrt( ((i-pb[0])*(i-pb[0]))+((j-pb[1])*(j-pb[1])) );
/*save to array*/
wa[lID] = (sin(adist)+sin(bdist))/2;
}
/*Main function (ofc)*/
int main(int argc, char** argv)
{
/*allocate memory for "normal" array*/
float *wav_array = (float*)malloc(sizeof(float)*900*900);
/*allocate memory on the GPU*/
float *gpu_wav_array;
cudaMalloc(&gpu_wav_array, 900*900*sizeof(float));
/*define block size*/
dim3 block_size;
block_size.x = 30;
block_size.y = 30;
block_size.z = 1;
/*define grid dimensions*/
dim3 grid_size;
grid_size.x = 30;
grid_size.y = 30;
/*Launch the kernels*/
sin_dist<<<block_size, grid_size>>>(gpu_wav_array);
/*Copy the data back from the GPU*/
cudaMemcpy(wav_array, gpu_wav_array, 900*900*sizeof(float), cudaMemcpyDeviceToHost);
return 0;
} | code for sm_80
Function : _Z8sin_distPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc600078e00ff */
/*0010*/ S2R R8, SR_CTAID.Y ; /* 0x0000000000087919 */
/* 0x000e220000002600 */
/*0020*/ BSSY B0, 0x1d0 ; /* 0x000001a000007945 */
/* 0x000fe20003800000 */
/*0030*/ IADD3 R1, R1, -0x20, RZ ; /* 0xffffffe001017810 */
/* 0x000fe40007ffe0ff */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0050*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e680000002500 */
/*0060*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0070*/ IMAD R8, R8, c[0x0][0x10], R3 ; /* 0x0000040008087a24 */
/* 0x001fc800078e0203 */
/*0080*/ I2F R2, R8 ; /* 0x0000000800027306 */
/* 0x000e220000201400 */
/*0090*/ IMAD R9, R9, c[0x0][0xc], R0 ; /* 0x0000030009097a24 */
/* 0x002fce00078e0200 */
/*00a0*/ I2F R0, R9 ; /* 0x0000000900007306 */
/* 0x000e620000201400 */
/*00b0*/ FADD R3, R2, -150 ; /* 0xc316000002037421 */
/* 0x001fc80000000000 */
/*00c0*/ FMUL R5, R3, R3 ; /* 0x0000000303057220 */
/* 0x000fe40000400000 */
/*00d0*/ FADD R2, R0, -100 ; /* 0xc2c8000000027421 */
/* 0x002fc80000000000 */
/*00e0*/ FFMA R2, R2, R2, R5 ; /* 0x0000000202027223 */
/* 0x000fc80000000005 */
/*00f0*/ MUFU.RSQ R3, R2 ; /* 0x0000000200037308 */
/* 0x0000620000001400 */
/*0100*/ IADD3 R4, R2, -0xd000000, RZ ; /* 0xf300000002047810 */
/* 0x000fc80007ffe0ff */
/*0110*/ ISETP.GT.U32.AND P0, PT, R4, 0x727fffff, PT ; /* 0x727fffff0400780c */
/* 0x000fda0003f04070 */
/*0120*/ @!P0 BRA 0x180 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0130*/ IMAD.MOV.U32 R12, RZ, RZ, R2 ; /* 0x000000ffff0c7224 */
/* 0x003fe200078e0002 */
/*0140*/ MOV R13, 0x160 ; /* 0x00000160000d7802 */
/* 0x000fe40000000f00 */
/*0150*/ CALL.REL.NOINC 0xe40 ; /* 0x00000ce000007944 */
/* 0x000fea0003c00000 */
/*0160*/ IMAD.MOV.U32 R11, RZ, RZ, R10 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e000a */
/*0170*/ BRA 0x1c0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0180*/ FMUL.FTZ R11, R2, R3 ; /* 0x00000003020b7220 */
/* 0x003fe40000410000 */
/*0190*/ FMUL.FTZ R3, R3, 0.5 ; /* 0x3f00000003037820 */
/* 0x000fe40000410000 */
/*01a0*/ FFMA R2, -R11, R11, R2 ; /* 0x0000000b0b027223 */
/* 0x000fc80000000102 */
/*01b0*/ FFMA R11, R2, R3, R11 ; /* 0x00000003020b7223 */
/* 0x000fe4000000000b */
/*01c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01d0*/ FADD R0, R0, -200 ; /* 0xc348000000007421 */
/* 0x000fe20000000000 */
/*01e0*/ BSSY B0, 0x2f0 ; /* 0x0000010000007945 */
/* 0x000fe60003800000 */
/*01f0*/ FFMA R0, R0, R0, R5 ; /* 0x0000000000007223 */
/* 0x000fc80000000005 */
/*0200*/ MUFU.RSQ R3, R0 ; /* 0x0000000000037308 */
/* 0x0000620000001400 */
/*0210*/ IADD3 R2, R0, -0xd000000, RZ ; /* 0xf300000000027810 */
/* 0x000fc80007ffe0ff */
/*0220*/ ISETP.GT.U32.AND P0, PT, R2, 0x727fffff, PT ; /* 0x727fffff0200780c */
/* 0x000fda0003f04070 */
/*0230*/ @!P0 BRA 0x2a0 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0240*/ BSSY B1, 0x290 ; /* 0x0000004000017945 */
/* 0x003fe20003800000 */
/*0250*/ IMAD.MOV.U32 R12, RZ, RZ, R0 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0000 */
/*0260*/ MOV R13, 0x280 ; /* 0x00000280000d7802 */
/* 0x000fe40000000f00 */
/*0270*/ CALL.REL.NOINC 0xe40 ; /* 0x00000bc000007944 */
/* 0x000fea0003c00000 */
/*0280*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x2e0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*02a0*/ FMUL.FTZ R5, R0, R3 ; /* 0x0000000300057220 */
/* 0x003fe40000410000 */
/*02b0*/ FMUL.FTZ R3, R3, 0.5 ; /* 0x3f00000003037820 */
/* 0x000fe40000410000 */
/*02c0*/ FFMA R0, -R5, R5, R0 ; /* 0x0000000505007223 */
/* 0x000fc80000000100 */
/*02d0*/ FFMA R10, R0, R3, R5 ; /* 0x00000003000a7223 */
/* 0x000fe40000000005 */
/*02e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02f0*/ FMUL R0, R11.reuse, 0.63661974668502807617 ; /* 0x3f22f9830b007820 */
/* 0x040fe20000400000 */
/*0300*/ FSETP.GE.AND P0, PT, |R11|, 105615, PT ; /* 0x47ce47800b00780b */
/* 0x000fe20003f06200 */
/*0310*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0320*/ BSSY B0, 0x760 ; /* 0x0000043000007945 */
/* 0x000fe20003800000 */
/*0330*/ F2I.NTZ R6, R0 ; /* 0x0000000000067305 */
/* 0x000e300000203100 */
/*0340*/ I2F R2, R6 ; /* 0x0000000600027306 */
/* 0x001e240000201400 */
/*0350*/ FFMA R3, R2, -1.5707962512969970703, R11 ; /* 0xbfc90fda02037823 */
/* 0x001fc8000000000b */
/*0360*/ FFMA R3, R2, -7.5497894158615963534e-08, R3 ; /* 0xb3a2216802037823 */
/* 0x000fc80000000003 */
/*0370*/ FFMA R7, R2, -5.3903029534742383927e-15, R3 ; /* 0xa7c234c502077823 */
/* 0x000fe20000000003 */
/*0380*/ @!P0 BRA 0x750 ; /* 0x000003c000008947 */
/* 0x000fea0003800000 */
/*0390*/ FSETP.NEU.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fda0003f0d200 */
/*03a0*/ @!P0 BRA 0x730 ; /* 0x0000038000008947 */
/* 0x000fea0003800000 */
/*03b0*/ IMAD.SHL.U32 R2, R11, 0x100, RZ ; /* 0x000001000b027824 */
/* 0x000fe200078e00ff */
/*03c0*/ MOV R0, R1 ; /* 0x0000000100007202 */
/* 0x000fe20000000f00 */
/*03d0*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*03e0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*03f0*/ LOP3.LUT R15, R2, 0x80000000, RZ, 0xfc, !PT ; /* 0x80000000020f7812 */
/* 0x000fe200078efcff */
/*0400*/ ULDC.64 UR8, c[0x4][0x0] ; /* 0x0100000000087ab9 */
/* 0x000fe40000000a00 */
/*0410*/ IMAD.U32 R4, RZ, RZ, UR8 ; /* 0x00000008ff047e24 */
/* 0x000fe4000f8e00ff */
/*0420*/ IMAD.U32 R5, RZ, RZ, UR9 ; /* 0x00000009ff057e24 */
/* 0x000fca000f8e00ff */
/*0430*/ LDG.E.CONSTANT R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e9900 */
/*0440*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*0450*/ UIADD3 UR8, UP0, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fc6000ff1e03f */
/*0460*/ ISETP.NE.AND P0, PT, R7, 0x6, PT ; /* 0x000000060700780c */
/* 0x000fe20003f05270 */
/*0470*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0480*/ IMAD.WIDE.U32 R2, R2, R15, RZ ; /* 0x0000000f02027225 */
/* 0x004fca00078e00ff */
/*0490*/ IADD3 R13, P1, R2, R6, RZ ; /* 0x00000006020d7210 */
/* 0x000fc80007f3e0ff */
/*04a0*/ IADD3.X R6, R3, UR4, RZ, P1, !PT ; /* 0x0000000403067c10 */
/* 0x000fe20008ffe4ff */
/*04b0*/ STL [R0], R13 ; /* 0x0000000d00007387 */
/* 0x0001e40000100800 */
/*04c0*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x001fe20007ffe0ff */
/*04d0*/ @P0 BRA 0x410 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*04e0*/ SHF.R.U32.HI R0, RZ, 0x17, R11 ; /* 0x00000017ff007819 */
/* 0x000fe2000001160b */
/*04f0*/ STL [R1+0x18], R6 ; /* 0x0000180601007387 */
/* 0x0001e60000100800 */
/*0500*/ LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00007812 */
/* 0x000fc800078ec0ff */
/*0510*/ IADD3 R0, R0, -0x80, RZ ; /* 0xffffff8000007810 */
/* 0x000fc80007ffe0ff */
/*0520*/ LOP3.LUT P0, R7, R0, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f00077812 */
/* 0x000fe4000780c0ff */
/*0530*/ SHF.R.U32.HI R0, RZ, 0x5, R0 ; /* 0x00000005ff007819 */
/* 0x000fc80000011600 */
/*0540*/ IADD3 R2, -R0.reuse, 0x4, RZ ; /* 0x0000000400027810 */
/* 0x040fe40007ffe1ff */
/*0550*/ IADD3 R0, -R0, 0x6, RZ ; /* 0x0000000600007810 */
/* 0x000fca0007ffe1ff */
/*0560*/ @P0 IMAD R13, R2, 0x4, R1.reuse ; /* 0x00000004020d0824 */
/* 0x100fe400078e0201 */
/*0570*/ IMAD R12, R0, 0x4, R1 ; /* 0x00000004000c7824 */
/* 0x000fc600078e0201 */
/*0580*/ @P0 LDL R5, [R13] ; /* 0x000000000d050983 */
/* 0x000ea80000100800 */
/*0590*/ LDL R0, [R12] ; /* 0x000000000c007983 */
/* 0x000ee80000100800 */
/*05a0*/ LDL R3, [R12+-0x4] ; /* 0xfffffc000c037983 */
/* 0x000f220000100800 */
/*05b0*/ @P0 IADD3 R2, -R7, 0x20, RZ ; /* 0x0000002007020810 */
/* 0x000fc80007ffe1ff */
/*05c0*/ @P0 SHF.R.U32.HI R4, RZ, R2.reuse, R5 ; /* 0x00000002ff040219 */
/* 0x084fe40000011605 */
/*05d0*/ @P0 SHF.L.U32 R5, R0, R7.reuse, RZ ; /* 0x0000000700050219 */
/* 0x088fe400000006ff */
/*05e0*/ @P0 SHF.L.U32 R7, R3, R7, RZ ; /* 0x0000000703070219 */
/* 0x010fe400000006ff */
/*05f0*/ @P0 SHF.R.U32.HI R2, RZ, R2, R3 ; /* 0x00000002ff020219 */
/* 0x000fc60000011603 */
/*0600*/ @P0 IMAD.IADD R3, R4, 0x1, R7 ; /* 0x0000000104030824 */
/* 0x000fe200078e0207 */
/*0610*/ @P0 IADD3 R0, R2, R5, RZ ; /* 0x0000000502000210 */
/* 0x000fe40007ffe0ff */
/*0620*/ LOP3.LUT P0, R11, R11, 0x80000000, RZ, 0xc0, !PT ; /* 0x800000000b0b7812 */
/* 0x000fe2000780c0ff */
/*0630*/ IMAD.SHL.U32 R4, R3.reuse, 0x4, RZ ; /* 0x0000000403047824 */
/* 0x040fe200078e00ff */
/*0640*/ SHF.L.U32.HI R5, R3, 0x2, R0 ; /* 0x0000000203057819 */
/* 0x000fc80000010600 */
/*0650*/ SHF.R.U32.HI R7, RZ, 0x1f, R5 ; /* 0x0000001fff077819 */
/* 0x000fc80000011605 */
/*0660*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f25270 */
/*0670*/ LEA.HI R6, R0, R7, RZ, 0x2 ; /* 0x0000000700067211 */
/* 0x001fca00078f10ff */
/*0680*/ IMAD.MOV R0, RZ, RZ, -R6 ; /* 0x000000ffff007224 */
/* 0x000fc800078e0a06 */
/*0690*/ @P0 IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff060224 */
/* 0x000fe400078e0000 */
/*06a0*/ @P1 LOP3.LUT R5, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff051212 */
/* 0x000fe400078e33ff */
/*06b0*/ @P1 LOP3.LUT R4, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff041212 */
/* 0x000fe400078e33ff */
/*06c0*/ @P1 LOP3.LUT R11, R11, 0x80000000, RZ, 0x3c, !PT ; /* 0x800000000b0b1812 */
/* 0x000fe400078e3cff */
/*06d0*/ I2F.F64.S64 R2, R4 ; /* 0x0000000400027312 */
/* 0x000e240000301c00 */
/*06e0*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f25270 */
/*06f0*/ DMUL R2, R2, c[0x2][0x0] ; /* 0x0080000002027a28 */
/* 0x001e140000000000 */
/*0700*/ F2F.F32.F64 R2, R2 ; /* 0x0000000200027310 */
/* 0x001e240000301000 */
/*0710*/ FSEL R7, R2, -R2, !P1 ; /* 0x8000000202077208 */
/* 0x001fe20004800000 */
/*0720*/ BRA 0x750 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0730*/ FMUL R7, RZ, R11 ; /* 0x0000000bff077220 */
/* 0x000fe20000400000 */
/*0740*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fe40000000f00 */
/*0750*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0760*/ FMUL R0, R10, 0.63661974668502807617 ; /* 0x3f22f9830a007820 */
/* 0x000fe20000400000 */
/*0770*/ LOP3.LUT P1, RZ, R6.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000106ff7812 */
/* 0x040fe2000782c0ff */
/*0780*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3c0885e4 ; /* 0x3c0885e4ff0b7424 */
/* 0x000fe200078e00ff */
/*0790*/ LOP3.LUT P0, RZ, R6, 0x2, RZ, 0xc0, !PT ; /* 0x0000000206ff7812 */
/* 0x000fe2000780c0ff */
/*07a0*/ FMUL R13, R7.reuse, R7 ; /* 0x00000007070d7220 */
/* 0x040fe20000400000 */
/*07b0*/ FSEL R7, R7, 1, !P1 ; /* 0x3f80000007077808 */
/* 0x000fe20004800000 */
/*07c0*/ F2I.NTZ R0, R0 ; /* 0x0000000000007305 */
/* 0x000e220000203100 */
/*07d0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x3e2aaaa8 ; /* 0x3e2aaaa8ff0c7424 */
/* 0x000fe200078e00ff */
/*07e0*/ FSEL R3, R11, 0.041666727513074874878, !P1 ; /* 0x3d2aaabb0b037808 */
/* 0x000fe20004800000 */
/*07f0*/ IMAD.MOV.U32 R2, RZ, RZ, -0x46b2bead ; /* 0xb94d4153ff027424 */
/* 0x000fe200078e00ff */
/*0800*/ BSSY B0, 0xcc0 ; /* 0x000004b000007945 */
/* 0x000fe40003800000 */
/*0810*/ FSEL R5, -R12, -0.4999999701976776123, !P1 ; /* 0xbeffffff0c057808 */
/* 0x000fc40004800100 */
/*0820*/ @P1 IMAD.MOV.U32 R4, RZ, RZ, 0x37cbac00 ; /* 0x37cbac00ff041424 */
/* 0x000fc800078e00ff */
/*0830*/ @P1 FFMA R2, R13.reuse, R4, -0.0013887860113754868507 ; /* 0xbab607ed0d021423 */
/* 0x040fe20000000004 */
/*0840*/ FSETP.GE.AND P1, PT, |R10|, 105615, PT ; /* 0x47ce47800a00780b */
/* 0x000fe20003f26200 */
/*0850*/ I2F R15, R0 ; /* 0x00000000000f7306 */
/* 0x001e240000201400 */
/*0860*/ FFMA R2, R13, R2, R3 ; /* 0x000000020d027223 */
/* 0x000fc80000000003 */
/*0870*/ FFMA R2, R13, R2, R5 ; /* 0x000000020d027223 */
/* 0x000fe40000000005 */
/*0880*/ FFMA R13, R7, R13, RZ ; /* 0x0000000d070d7223 */
/* 0x000fc800000000ff */
/*0890*/ FFMA R13, R2, R13, R7 ; /* 0x0000000d020d7223 */
/* 0x000fc80000000007 */
/*08a0*/ @P0 FFMA R13, R13, -1, RZ ; /* 0xbf8000000d0d0823 */
/* 0x000fe400000000ff */
/*08b0*/ FFMA R4, R15, -1.5707962512969970703, R10 ; /* 0xbfc90fda0f047823 */
/* 0x001fc8000000000a */
/*08c0*/ FFMA R4, R15, -7.5497894158615963534e-08, R4 ; /* 0xb3a221680f047823 */
/* 0x000fc80000000004 */
/*08d0*/ FFMA R15, R15, -5.3903029534742383927e-15, R4 ; /* 0xa7c234c50f0f7823 */
/* 0x000fe20000000004 */
/*08e0*/ @!P1 BRA 0xcb0 ; /* 0x000003c000009947 */
/* 0x000fea0003800000 */
/*08f0*/ FSETP.NEU.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fda0003f0d200 */
/*0900*/ @!P0 BRA 0xc90 ; /* 0x0000038000008947 */
/* 0x000fea0003800000 */
/*0910*/ SHF.R.U32.HI R0, RZ, 0x17, R10 ; /* 0x00000017ff007819 */
/* 0x000fe2000001160a */
/*0920*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0930*/ SHF.L.U32 R3, R10, 0x8, RZ ; /* 0x000000080a037819 */
/* 0x000fe200000006ff */
/*0940*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0950*/ LOP3.LUT R2, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00027812 */
/* 0x000fe200078ec0ff */
/*0960*/ IMAD.MOV.U32 R0, RZ, RZ, R1 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0001 */
/*0970*/ LOP3.LUT R17, R3, 0x80000000, RZ, 0xfc, !PT ; /* 0x8000000003117812 */
/* 0x000fe200078efcff */
/*0980*/ ULDC.64 UR8, c[0x4][0x0] ; /* 0x0100000000087ab9 */
/* 0x000fe20000000a00 */
/*0990*/ IADD3 R14, R2, -0x80, RZ ; /* 0xffffff80020e7810 */
/* 0x000fc80007ffe0ff */
/*09a0*/ SHF.R.U32.HI R16, RZ, 0x5, R14 ; /* 0x00000005ff107819 */
/* 0x000fe4000001160e */
/*09b0*/ IMAD.U32 R4, RZ, RZ, UR8 ; /* 0x00000008ff047e24 */
/* 0x000fe4000f8e00ff */
/*09c0*/ IMAD.U32 R5, RZ, RZ, UR9 ; /* 0x00000009ff057e24 */
/* 0x000fca000f8e00ff */
/*09d0*/ LDG.E.CONSTANT R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e9900 */
/*09e0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*09f0*/ UIADD3 UR8, UP0, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fc6000ff1e03f */
/*0a00*/ ISETP.NE.AND P0, PT, R7, 0x6, PT ; /* 0x000000060700780c */
/* 0x000fe20003f05270 */
/*0a10*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0a20*/ IMAD.WIDE.U32 R2, R2, R17, RZ ; /* 0x0000001102027225 */
/* 0x004fca00078e00ff */
/*0a30*/ IADD3 R15, P1, R2, R6, RZ ; /* 0x00000006020f7210 */
/* 0x000fc80007f3e0ff */
/*0a40*/ IADD3.X R6, R3, UR4, RZ, P1, !PT ; /* 0x0000000403067c10 */
/* 0x000fe20008ffe4ff */
/*0a50*/ STL [R0], R15 ; /* 0x0000000f00007387 */
/* 0x0001e40000100800 */
/*0a60*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x001fe20007ffe0ff */
/*0a70*/ @P0 BRA 0x9b0 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*0a80*/ LOP3.LUT P0, R7, R14, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f0e077812 */
/* 0x000fe2000780c0ff */
/*0a90*/ STL [R1+0x18], R6 ; /* 0x0000180601007387 */
/* 0x0001e20000100800 */
/*0aa0*/ IADD3 R2, -R16.reuse, 0x4, RZ ; /* 0x0000000410027810 */
/* 0x040fe40007ffe1ff */
/*0ab0*/ IADD3 R0, -R16, 0x6, RZ ; /* 0x0000000610007810 */
/* 0x000fc80007ffe1ff */
/*0ac0*/ LEA R14, R0, R1, 0x2 ; /* 0x00000001000e7211 */
/* 0x000fca00078e10ff */
/*0ad0*/ @P0 IMAD R15, R2, 0x4, R1 ; /* 0x00000004020f0824 */
/* 0x000fe200078e0201 */
/*0ae0*/ LDL R0, [R14] ; /* 0x000000000e007983 */
/* 0x000ea80000100800 */
/*0af0*/ @P0 LDL R5, [R15] ; /* 0x000000000f050983 */
/* 0x000ee80000100800 */
/*0b00*/ LDL R3, [R14+-0x4] ; /* 0xfffffc000e037983 */
/* 0x000f220000100800 */
/*0b10*/ @P0 IADD3 R2, -R7, 0x20, RZ ; /* 0x0000002007020810 */
/* 0x000fc80007ffe1ff */
/*0b20*/ @P0 SHF.R.U32.HI R4, RZ, R2.reuse, R5 ; /* 0x00000002ff040219 */
/* 0x088fe40000011605 */
/*0b30*/ @P0 SHF.L.U32 R5, R0, R7.reuse, RZ ; /* 0x0000000700050219 */
/* 0x084fe400000006ff */
/*0b40*/ @P0 SHF.R.U32.HI R2, RZ, R2, R3 ; /* 0x00000002ff020219 */
/* 0x010fe40000011603 */
/*0b50*/ @P0 SHF.L.U32 R7, R3, R7, RZ ; /* 0x0000000703070219 */
/* 0x000fc600000006ff */
/*0b60*/ @P0 IMAD.IADD R0, R2, 0x1, R5 ; /* 0x0000000102000824 */
/* 0x000fe400078e0205 */
/*0b70*/ @P0 IMAD.IADD R3, R4, 0x1, R7 ; /* 0x0000000104030824 */
/* 0x000fca00078e0207 */
/*0b80*/ SHF.L.U32.HI R5, R3, 0x2, R0 ; /* 0x0000000203057819 */
/* 0x000fc80000010600 */
/*0b90*/ SHF.R.U32.HI R7, RZ, 0x1f, R5 ; /* 0x0000001fff077819 */
/* 0x000fc80000011605 */
/*0ba0*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f25270 */
/*0bb0*/ IMAD.SHL.U32 R4, R3, 0x4, RZ ; /* 0x0000000403047824 */
/* 0x000fd800078e00ff */
/*0bc0*/ @P1 LOP3.LUT R5, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff051212 */
/* 0x000fe400078e33ff */
/*0bd0*/ @P1 LOP3.LUT R4, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff041212 */
/* 0x000fc800078e33ff */
/*0be0*/ I2F.F64.S64 R2, R4 ; /* 0x0000000400027312 */
/* 0x000e620000301c00 */
/*0bf0*/ LOP3.LUT P0, R10, R10, 0x80000000, RZ, 0xc0, !PT ; /* 0x800000000a0a7812 */
/* 0x000fe2000780c0ff */
/*0c00*/ DMUL R2, R2, c[0x2][0x0] ; /* 0x0080000002027a28 */
/* 0x002e620000000000 */
/*0c10*/ LEA.HI R0, R0, R7, RZ, 0x2 ; /* 0x0000000700007211 */
/* 0x000fd200078f10ff */
/*0c20*/ F2F.F32.F64 R2, R2 ; /* 0x0000000200027310 */
/* 0x002e620000301000 */
/*0c30*/ @P1 LOP3.LUT R10, R10, 0x80000000, RZ, 0x3c, !PT ; /* 0x800000000a0a1812 */
/* 0x000fe200078e3cff */
/*0c40*/ IMAD.MOV R6, RZ, RZ, -R0 ; /* 0x000000ffff067224 */
/* 0x001fc600078e0a00 */
/*0c50*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f25270 */
/*0c60*/ @P0 MOV R0, R6 ; /* 0x0000000600000202 */
/* 0x000fe40000000f00 */
/*0c70*/ FSEL R15, R2, -R2, !P1 ; /* 0x80000002020f7208 */
/* 0x002fe20004800000 */
/*0c80*/ BRA 0xcb0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0c90*/ FMUL R15, RZ, R10 ; /* 0x0000000aff0f7220 */
/* 0x000fe40000400000 */
/*0ca0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*0cb0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0cc0*/ LOP3.LUT P1, RZ, R0.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100ff7812 */
/* 0x040fe2000782c0ff */
/*0cd0*/ FMUL R4, R15, R15 ; /* 0x0000000f0f047220 */
/* 0x000fe20000400000 */
/*0ce0*/ LOP3.LUT P0, RZ, R0, 0x2, RZ, 0xc0, !PT ; /* 0x0000000200ff7812 */
/* 0x000fe2000780c0ff */
/*0cf0*/ IMAD.MOV.U32 R2, RZ, RZ, -0x46b2bead ; /* 0xb94d4153ff027424 */
/* 0x000fe200078e00ff */
/*0d00*/ FSEL R11, R11, 0.041666727513074874878, !P1 ; /* 0x3d2aaabb0b0b7808 */
/* 0x000fe20004800000 */
/*0d10*/ ULDC UR4, c[0x0][0x10] ; /* 0x0000040000047ab9 */
/* 0x000fe20000000800 */
/*0d20*/ FSEL R15, R15, 1, !P1 ; /* 0x3f8000000f0f7808 */
/* 0x000fe20004800000 */
/*0d30*/ ULDC UR5, c[0x0][0x4] ; /* 0x0000010000057ab9 */
/* 0x000fe20000000800 */
/*0d40*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*0d50*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fc4000f8e023f */
/*0d60*/ FFMA R5, R15, R4, RZ ; /* 0x000000040f057223 */
/* 0x000fe400000000ff */
/*0d70*/ @P1 IMAD.MOV.U32 R3, RZ, RZ, 0x37cbac00 ; /* 0x37cbac00ff031424 */
/* 0x000fc800078e00ff */
/*0d80*/ @P1 FFMA R2, R4, R3, -0.0013887860113754868507 ; /* 0xbab607ed04021423 */
/* 0x000fe20000000003 */
/*0d90*/ FSEL R3, -R12, -0.4999999701976776123, !P1 ; /* 0xbeffffff0c037808 */
/* 0x000fc60004800100 */
/*0da0*/ FFMA R2, R4, R2, R11 ; /* 0x0000000204027223 */
/* 0x000fc8000000000b */
/*0db0*/ FFMA R2, R4, R2, R3 ; /* 0x0000000204027223 */
/* 0x000fe40000000003 */
/*0dc0*/ IMAD R3, R8, UR4, R9 ; /* 0x0000000408037c24 */
/* 0x000fe4000f8e0209 */
/*0dd0*/ FFMA R2, R2, R5, R15 ; /* 0x0000000502027223 */
/* 0x000fc8000000000f */
/*0de0*/ @P0 FFMA R2, R2, -1, RZ ; /* 0xbf80000002020823 */
/* 0x000fc800000000ff */
/*0df0*/ FADD R13, R2, R13 ; /* 0x0000000d020d7221 */
/* 0x000fe40000000000 */
/*0e00*/ IMAD.WIDE R2, R3, R0, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc800078e0200 */
/*0e10*/ FMUL R13, R13, 0.5 ; /* 0x3f0000000d0d7820 */
/* 0x000fca0000400000 */
/*0e20*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe2000c101906 */
/*0e30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e40*/ LOP3.LUT P0, RZ, R12, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fda000780c0ff */
/*0e50*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff028224 */
/* 0x000fe200078e000c */
/*0e60*/ @!P0 BRA 0xf70 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0e70*/ FSETP.GEU.FTZ.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720b */
/* 0x000fda0003f1e000 */
/*0e80*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff028424 */
/* 0x000fe200078e00ff */
/*0e90*/ @!P0 BRA 0xf70 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0ea0*/ FSETP.GTU.FTZ.AND P0, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fda0003f1c200 */
/*0eb0*/ @P0 FADD.FTZ R2, R12, 1 ; /* 0x3f8000000c020421 */
/* 0x000fe20000010000 */
/*0ec0*/ @P0 BRA 0xf70 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0ed0*/ FSETP.NEU.FTZ.AND P0, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fda0003f1d200 */
/*0ee0*/ @P0 FFMA R3, R12, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000c030823 */
/* 0x000fc800000000ff */
/*0ef0*/ @P0 MUFU.RSQ R2, R3 ; /* 0x0000000300020308 */
/* 0x000e240000001400 */
/*0f00*/ @P0 FMUL.FTZ R4, R3, R2 ; /* 0x0000000203040220 */
/* 0x001fe40000410000 */
/*0f10*/ @P0 FMUL.FTZ R10, R2, 0.5 ; /* 0x3f000000020a0820 */
/* 0x000fe40000410000 */
/*0f20*/ @P0 FADD.FTZ R6, -R4.reuse, -RZ ; /* 0x800000ff04060221 */
/* 0x040fe40000010100 */
/*0f30*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff028224 */
/* 0x000fe400078e000c */
/*0f40*/ @P0 FFMA R7, R4, R6, R3 ; /* 0x0000000604070223 */
/* 0x000fc80000000003 */
/*0f50*/ @P0 FFMA R7, R7, R10, R4 ; /* 0x0000000a07070223 */
/* 0x000fc80000000004 */
/*0f60*/ @P0 FMUL.FTZ R2, R7, 2.3283064365386962891e-10 ; /* 0x2f80000007020820 */
/* 0x000fca0000410000 */
/*0f70*/ MOV R10, R2 ; /* 0x00000002000a7202 */
/* 0x000fe20000000f00 */
/*0f80*/ IMAD.MOV.U32 R2, RZ, RZ, R13 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000d */
/*0f90*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0fa0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff05002007950 */
/* 0x000fea0003c3ffff */
/*0fb0*/ BRA 0xfb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
/*wave kernel*/
__global__ void sin_dist(float *wa)
{
/*calculate 2d arrray index from thread and block IDs*/
const int j = threadIdx.y+(blockIdx.y*gridDim.y);
const int i = threadIdx.x+(blockIdx.x*gridDim.x);
/*calculate mapping to 1d array from 2d indicies*/
const int lID = i+(j*blockDim.y*gridDim.y);
/*define the wave sources*/
float pa[] = {100,150};
float pb[] = {200,150};
/*calculate value at location*/
float adist = sqrt( ((i-pa[0])*(i-pa[0]))+((j-pa[1])*(j-pa[1])) );
float bdist = sqrt( ((i-pb[0])*(i-pb[0]))+((j-pb[1])*(j-pb[1])) );
/*save to array*/
wa[lID] = (sin(adist)+sin(bdist))/2;
}
/*Main function (ofc)*/
int main(int argc, char** argv)
{
/*allocate memory for "normal" array*/
float *wav_array = (float*)malloc(sizeof(float)*900*900);
/*allocate memory on the GPU*/
float *gpu_wav_array;
cudaMalloc(&gpu_wav_array, 900*900*sizeof(float));
/*define block size*/
dim3 block_size;
block_size.x = 30;
block_size.y = 30;
block_size.z = 1;
/*define grid dimensions*/
dim3 grid_size;
grid_size.x = 30;
grid_size.y = 30;
/*Launch the kernels*/
sin_dist<<<block_size, grid_size>>>(gpu_wav_array);
/*Copy the data back from the GPU*/
cudaMemcpy(wav_array, gpu_wav_array, 900*900*sizeof(float), cudaMemcpyDeviceToHost);
return 0;
} | .file "tmpxft_000d45d9_00000000-6_waves_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z8sin_distPfPf
.type _Z27__device_stub__Z8sin_distPfPf, @function
_Z27__device_stub__Z8sin_distPfPf:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8sin_distPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z8sin_distPfPf, .-_Z27__device_stub__Z8sin_distPfPf
.globl _Z8sin_distPf
.type _Z8sin_distPf, @function
_Z8sin_distPf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z8sin_distPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8sin_distPf, .-_Z8sin_distPf
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $3240000, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $3240000, %esi
call cudaMalloc@PLT
movl $30, 16(%rsp)
movl $30, 20(%rsp)
movl $30, 28(%rsp)
movl $30, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movl $3240000, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z27__device_stub__Z8sin_distPfPf
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8sin_distPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8sin_distPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
/*wave kernel*/
__global__ void sin_dist(float *wa)
{
/*calculate 2d arrray index from thread and block IDs*/
const int j = threadIdx.y+(blockIdx.y*gridDim.y);
const int i = threadIdx.x+(blockIdx.x*gridDim.x);
/*calculate mapping to 1d array from 2d indicies*/
const int lID = i+(j*blockDim.y*gridDim.y);
/*define the wave sources*/
float pa[] = {100,150};
float pb[] = {200,150};
/*calculate value at location*/
float adist = sqrt( ((i-pa[0])*(i-pa[0]))+((j-pa[1])*(j-pa[1])) );
float bdist = sqrt( ((i-pb[0])*(i-pb[0]))+((j-pb[1])*(j-pb[1])) );
/*save to array*/
wa[lID] = (sin(adist)+sin(bdist))/2;
}
/*Main function (ofc)*/
int main(int argc, char** argv)
{
/*allocate memory for "normal" array*/
float *wav_array = (float*)malloc(sizeof(float)*900*900);
/*allocate memory on the GPU*/
float *gpu_wav_array;
cudaMalloc(&gpu_wav_array, 900*900*sizeof(float));
/*define block size*/
dim3 block_size;
block_size.x = 30;
block_size.y = 30;
block_size.z = 1;
/*define grid dimensions*/
dim3 grid_size;
grid_size.x = 30;
grid_size.y = 30;
/*Launch the kernels*/
sin_dist<<<block_size, grid_size>>>(gpu_wav_array);
/*Copy the data back from the GPU*/
cudaMemcpy(wav_array, gpu_wav_array, 900*900*sizeof(float), cudaMemcpyDeviceToHost);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
/*wave kernel*/
__global__ void sin_dist(float *wa)
{
/*calculate 2d arrray index from thread and block IDs*/
const int j = threadIdx.y+(blockIdx.y*gridDim.y);
const int i = threadIdx.x+(blockIdx.x*gridDim.x);
/*calculate mapping to 1d array from 2d indicies*/
const int lID = i+(j*blockDim.y*gridDim.y);
/*define the wave sources*/
float pa[] = {100,150};
float pb[] = {200,150};
/*calculate value at location*/
float adist = sqrt( ((i-pa[0])*(i-pa[0]))+((j-pa[1])*(j-pa[1])) );
float bdist = sqrt( ((i-pb[0])*(i-pb[0]))+((j-pb[1])*(j-pb[1])) );
/*save to array*/
wa[lID] = (sin(adist)+sin(bdist))/2;
}
/*Main function (ofc)*/
int main(int argc, char** argv)
{
/*allocate memory for "normal" array*/
float *wav_array = (float*)malloc(sizeof(float)*900*900);
/*allocate memory on the GPU*/
float *gpu_wav_array;
hipMalloc(&gpu_wav_array, 900*900*sizeof(float));
/*define block size*/
dim3 block_size;
block_size.x = 30;
block_size.y = 30;
block_size.z = 1;
/*define grid dimensions*/
dim3 grid_size;
grid_size.x = 30;
grid_size.y = 30;
/*Launch the kernels*/
sin_dist<<<block_size, grid_size>>>(gpu_wav_array);
/*Copy the data back from the GPU*/
hipMemcpy(wav_array, gpu_wav_array, 900*900*sizeof(float), hipMemcpyDeviceToHost);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
/*wave kernel*/
__global__ void sin_dist(float *wa)
{
/*calculate 2d arrray index from thread and block IDs*/
const int j = threadIdx.y+(blockIdx.y*gridDim.y);
const int i = threadIdx.x+(blockIdx.x*gridDim.x);
/*calculate mapping to 1d array from 2d indicies*/
const int lID = i+(j*blockDim.y*gridDim.y);
/*define the wave sources*/
float pa[] = {100,150};
float pb[] = {200,150};
/*calculate value at location*/
float adist = sqrt( ((i-pa[0])*(i-pa[0]))+((j-pa[1])*(j-pa[1])) );
float bdist = sqrt( ((i-pb[0])*(i-pb[0]))+((j-pb[1])*(j-pb[1])) );
/*save to array*/
wa[lID] = (sin(adist)+sin(bdist))/2;
}
/*Main function (ofc)*/
int main(int argc, char** argv)
{
/*allocate memory for "normal" array*/
float *wav_array = (float*)malloc(sizeof(float)*900*900);
/*allocate memory on the GPU*/
float *gpu_wav_array;
hipMalloc(&gpu_wav_array, 900*900*sizeof(float));
/*define block size*/
dim3 block_size;
block_size.x = 30;
block_size.y = 30;
block_size.z = 1;
/*define grid dimensions*/
dim3 grid_size;
grid_size.x = 30;
grid_size.y = 30;
/*Launch the kernels*/
sin_dist<<<block_size, grid_size>>>(gpu_wav_array);
/*Copy the data back from the GPU*/
hipMemcpy(wav_array, gpu_wav_array, 900*900*sizeof(float), hipMemcpyDeviceToHost);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8sin_distPf
.globl _Z8sin_distPf
.p2align 8
.type _Z8sin_distPf,@function
_Z8sin_distPf:
s_load_b64 s[4:5], s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s5, s15, v[1:2]
v_mad_u64_u32 v[0:1], null, s4, s14, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v1, v2
v_cvt_f32_i32_e32 v7, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v1, 0xc3160000, v1
v_dual_add_f32 v3, 0xc2c80000, v7 :: v_dual_mul_f32 v6, v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v1, v3, v3, v6
v_mul_f32_e32 v3, 0x4f800000, v1
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v3, vcc_lo
v_sqrt_f32_e32 v3, v1
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v4, -1, v3
v_add_nc_u32_e32 v5, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v8, -v4, v3, v1
v_fma_f32 v9, -v5, v3, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v8
v_cndmask_b32_e64 v3, v3, v4, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s2, 0, v9
v_cndmask_b32_e64 v3, v3, v5, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, 0x37800000, v3
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v1, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v3, v1, vcc_lo
v_and_b32_e32 v3, 0x7fffffff, v1
v_cmpx_ngt_f32_e64 0x48000000, |v1|
s_xor_b32 s4, exec_lo, s3
s_cbranch_execz .LBB0_2
s_mov_b32 s2, 0x7fffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_or_b32 v17, v3, s2, 0x800000
v_mad_u64_u32 v[4:5], null, v17, 0xfe5163ab, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v8, v5
v_lshrrev_b32_e32 v5, 23, v3
v_mad_u64_u32 v[10:11], null, v17, 0x3c439041, v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, 0xffffff88, v5
v_cmp_lt_u32_e32 vcc_lo, 63, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mov_b32_e32 v8, v11
v_cndmask_b32_e64 v15, 0, 0xffffffc0, vcc_lo
v_mad_u64_u32 v[11:12], null, v17, 0xdb629599, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v8, v12 :: v_dual_add_nc_u32 v5, v15, v5
v_cmp_lt_u32_e64 s2, 31, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v4, v11, v4, vcc_lo
v_mad_u64_u32 v[12:13], null, v17, 0xf534ddc0, v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v16, 0, 0xffffffe0, s2
v_dual_mov_b32 v8, v13 :: v_dual_add_nc_u32 v5, v16, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s3, 31, v5
v_mad_u64_u32 v[13:14], null, v17, 0xfc2757d1, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v8, v14
v_mad_u64_u32 v[14:15], null, v17, 0x4e441529, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v8, v15
v_mad_u64_u32 v[15:16], null, v17, 0xa2f9836e, v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v9, v14, v12, vcc_lo
v_cndmask_b32_e64 v8, 0, 0xffffffe0, s3
v_add_nc_u32_e32 v5, v8, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v15, v15, v13 :: v_dual_cndmask_b32 v14, v16, v14
v_dual_cndmask_b32 v13, v13, v11 :: v_dual_cndmask_b32 v8, v12, v10
v_cmp_eq_u32_e32 vcc_lo, 0, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v10, v15, v9, s2
v_cndmask_b32_e64 v12, v14, v15, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v9, v9, v13, s2
v_sub_nc_u32_e32 v14, 32, v5
v_cndmask_b32_e64 v12, v12, v10, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v10, v10, v9, s3
v_alignbit_b32 v15, v12, v10, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, v15, v12, vcc_lo
v_cndmask_b32_e64 v13, v13, v8, s2
v_cndmask_b32_e64 v4, v8, v4, s2
v_cndmask_b32_e64 v9, v9, v13, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v4, v13, v4, s3
v_alignbit_b32 v11, v10, v9, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_alignbit_b32 v13, v9, v4, v14
v_dual_cndmask_b32 v8, v11, v10 :: v_dual_cndmask_b32 v9, v13, v9
v_bfe_u32 v10, v5, 29, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v11, v5, v8, 30
v_alignbit_b32 v8, v8, v9, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v12, 0, v10
v_alignbit_b32 v4, v9, v4, 30
v_xor_b32_e32 v11, v11, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v8, v8, v12
v_xor_b32_e32 v4, v4, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v13, v11
v_min_u32_e32 v13, 32, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v9, 31, v13
v_lshlrev_b32_e32 v15, 23, v13
v_alignbit_b32 v11, v11, v8, v9
v_alignbit_b32 v4, v8, v4, v9
v_lshrrev_b32_e32 v9, 29, v5
v_lshrrev_b32_e32 v5, 30, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v8, v11, v4, 9
v_lshlrev_b32_e32 v9, 31, v9
v_lshrrev_b32_e32 v11, 9, v11
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v5, v10, v5
v_clz_i32_u32_e32 v12, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v14, 0.5, v9
v_min_u32_e32 v12, 32, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v14, v14, v15
v_sub_nc_u32_e32 v16, 31, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v4, v8, v4, v16
v_or_b32_e32 v8, v11, v14
v_add_lshl_u32 v11, v12, v13, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v4, 9, v4
v_mul_f32_e32 v12, 0x3fc90fda, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v4, v11
v_fma_f32 v11, v8, 0x3fc90fda, -v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 0x33000000, v4
v_fmamk_f32 v8, v8, 0x33a22168, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v4, v4, v9
v_fmac_f32_e32 v8, 0x3fc90fda, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v4, v12, v8
.LBB0_2:
s_and_not1_saveexec_b32 s2, s4
v_mul_f32_e64 v4, 0x3f22f983, |v1|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v5, v4
v_fma_f32 v4, v5, 0xbfc90fda, |v1|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v4, v5, 0xb3a22168, v4
v_fmamk_f32 v4, v5, 0xa7c234c4, v4
v_cvt_i32_f32_e32 v5, v5
s_or_b32 exec_lo, exec_lo, s2
v_add_f32_e32 v7, 0xc3480000, v7
s_load_b32 s4, s[0:1], 0x14
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v7, v7
v_mul_f32_e32 v7, 0x4f800000, v6
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v6, v6, v7, vcc_lo
v_sqrt_f32_e32 v7, v6
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v8, -1, v7
v_add_nc_u32_e32 v9, 1, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v10, -v8, v7, v6
v_fma_f32 v11, -v9, v7, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v10
v_cndmask_b32_e64 v7, v7, v8, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s2, 0, v11
v_cndmask_b32_e64 v7, v7, v9, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, 0x37800000, v7
v_cndmask_b32_e32 v7, v7, v8, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v6, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v6, v7, v6, vcc_lo
v_and_b32_e32 v7, 0x7fffffff, v6
v_cmpx_ngt_f32_e64 0x48000000, |v6|
s_xor_b32 s6, exec_lo, s3
s_cbranch_execz .LBB0_6
s_mov_b32 s2, 0x7fffff
v_mov_b32_e32 v10, 0
v_and_or_b32 v18, v7, s2, 0x800000
v_lshrrev_b32_e32 v15, 23, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[8:9], null, v18, 0xfe5163ab, 0
v_add_nc_u32_e32 v16, 0xffffff88, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 63, v16
v_mad_u64_u32 v[11:12], null, v18, 0x3c439041, v[9:10]
v_cndmask_b32_e64 v17, 0, 0xffffffc0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v9, v12
v_add_nc_u32_e32 v17, v17, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[12:13], null, v18, 0xdb629599, v[9:10]
v_cmp_lt_u32_e64 s2, 31, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v19, 0, 0xffffffe0, s2
v_dual_mov_b32 v9, v13 :: v_dual_cndmask_b32 v8, v12, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v19, v19, v17
v_mad_u64_u32 v[13:14], null, v18, 0xf534ddc0, v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s3, 31, v19
v_mov_b32_e32 v9, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v11, v13, v11, vcc_lo
v_mad_u64_u32 v[14:15], null, v18, 0xfc2757d1, v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v8, v11, v8, s2
v_mov_b32_e32 v9, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[15:16], null, v18, 0x4e441529, v[9:10]
v_mov_b32_e32 v9, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[16:17], null, v18, 0xa2f9836e, v[9:10]
v_cndmask_b32_e64 v9, 0, 0xffffffe0, s3
v_dual_cndmask_b32 v10, v15, v13 :: v_dual_add_nc_u32 v9, v9, v19
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v16, v16, v14 :: v_dual_cndmask_b32 v15, v17, v15
v_cndmask_b32_e32 v14, v14, v12, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v13, v16, v10, s2
v_cndmask_b32_e64 v15, v15, v16, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v10, v10, v14, s2
v_sub_nc_u32_e32 v16, 32, v9
v_cndmask_b32_e64 v14, v14, v11, s2
v_cndmask_b32_e64 v15, v15, v13, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v13, v13, v10, s3
v_cndmask_b32_e64 v10, v10, v14, s3
v_cndmask_b32_e64 v8, v14, v8, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v17, v15, v13, v16
v_alignbit_b32 v12, v13, v10, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v9, v17, v15, vcc_lo
v_alignbit_b32 v15, v10, v8, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v11, v12, v13, vcc_lo
v_bfe_u32 v12, v9, 29, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v10, v15, v10, vcc_lo
v_alignbit_b32 v13, v9, v11, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v14, 0, v12
v_alignbit_b32 v11, v11, v10, 30
v_alignbit_b32 v8, v10, v8, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v13, v13, v14
v_xor_b32_e32 v10, v11, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v8, v8, v14
v_clz_i32_u32_e32 v15, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v15, 32, v15
v_sub_nc_u32_e32 v11, 31, v15
v_lshlrev_b32_e32 v17, 23, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_alignbit_b32 v13, v13, v10, v11
v_alignbit_b32 v8, v10, v8, v11
v_lshrrev_b32_e32 v11, 29, v9
v_alignbit_b32 v10, v13, v8, 9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v11, 31, v11
v_lshrrev_b32_e32 v13, 9, v13
v_clz_i32_u32_e32 v14, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v16, 0.5, v11
v_min_u32_e32 v14, 32, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v16, v16, v17
v_sub_nc_u32_e32 v18, 31, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v8, v10, v8, v18
v_or_b32_e32 v10, v13, v16
v_add_lshl_u32 v13, v14, v15, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v8, 9, v8
v_mul_f32_e32 v14, 0x3fc90fda, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v8, v8, v13
v_fma_f32 v13, v10, 0x3fc90fda, -v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v8, 0x33000000, v8
v_fmamk_f32 v10, v10, 0x33a22168, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v8, v8, v11
v_fmac_f32_e32 v10, 0x3fc90fda, v8
v_lshrrev_b32_e32 v9, 30, v9
s_delay_alu instid0(VALU_DEP_1)
v_dual_add_f32 v8, v14, v10 :: v_dual_add_nc_u32 v9, v12, v9
.LBB0_6:
s_or_saveexec_b32 s3, s6
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s4, 16
s_xor_b32 exec_lo, exec_lo, s3
v_mul_f32_e64 v8, 0x3f22f983, |v6|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v9, v8
v_fma_f32 v8, v9, 0xbfc90fda, |v6|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v8, v9, 0xb3a22168, v8
v_fmamk_f32 v8, v9, 0xa7c234c4, v8
v_cvt_i32_f32_e32 v9, v9
s_or_b32 exec_lo, exec_lo, s3
s_mov_b32 s3, 0xb94c1982
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_mul_f32_e32 v11, v8, v8
v_mul_f32_e32 v10, v4, v4
s_mov_b32 s4, 0x37d75334
v_xor_b32_e32 v3, v3, v1
v_dual_fmaak_f32 v15, s3, v11, 0x3c0881c4 :: v_dual_lshlrev_b32 v14, 30, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fmaak_f32 v12, s3, v10, 0x3c0881c4
v_dual_fmaak_f32 v13, s4, v10, 0xbab64f3b :: v_dual_fmaak_f32 v16, s4, v11, 0xbab64f3b
v_and_b32_e32 v5, 1, v5
v_dual_fmaak_f32 v15, v11, v15, 0xbe2aaa9d :: v_dual_fmaak_f32 v12, v10, v12, 0xbe2aaa9d
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_fmaak_f32 v13, v10, v13, 0x3d2aabf7 :: v_dual_fmaak_f32 v16, v11, v16, 0x3d2aabf7
v_cmp_eq_u32_e32 vcc_lo, 0, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_dual_mul_f32 v15, v11, v15 :: v_dual_and_b32 v14, 0x80000000, v14
v_mul_f32_e32 v12, v10, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_fmaak_f32 v13, v10, v13, 0xbf000004
s_and_b32 s2, 0xffff, s2
v_xor_b32_e32 v7, v7, v6
s_load_b64 s[0:1], s[0:1], 0x0
v_fma_f32 v10, v10, v13, 1.0
v_mul_lo_u32 v13, v2, s5
v_and_b32_e32 v2, 1, v9
v_dual_fmac_f32 v4, v4, v12 :: v_dual_lshlrev_b32 v9, 30, v9
v_fmaak_f32 v12, v11, v16, 0xbf000004
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v10, v4, vcc_lo
v_fma_f32 v11, v11, v12, 1.0
v_cmp_eq_u32_e32 vcc_lo, 0, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_xor3_b32 v4, v3, v14, v4
v_fmac_f32_e32 v8, v8, v15
v_mad_u64_u32 v[2:3], null, v13, s2, v[0:1]
v_dual_cndmask_b32 v5, v11, v8 :: v_dual_and_b32 v8, 0x80000000, v9
v_cmp_class_f32_e64 vcc_lo, v1, 0x1f8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v3, 31, v2
v_xor3_b32 v0, v7, v8, v5
v_cndmask_b32_e32 v1, 0x7fc00000, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v6, 0x1f8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
v_add_f32_e32 v4, v1, v0
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v2, 0.5, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8sin_distPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8sin_distPf, .Lfunc_end0-_Z8sin_distPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8sin_distPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8sin_distPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
/*wave kernel*/
__global__ void sin_dist(float *wa)
{
/*calculate 2d arrray index from thread and block IDs*/
const int j = threadIdx.y+(blockIdx.y*gridDim.y);
const int i = threadIdx.x+(blockIdx.x*gridDim.x);
/*calculate mapping to 1d array from 2d indicies*/
const int lID = i+(j*blockDim.y*gridDim.y);
/*define the wave sources*/
float pa[] = {100,150};
float pb[] = {200,150};
/*calculate value at location*/
float adist = sqrt( ((i-pa[0])*(i-pa[0]))+((j-pa[1])*(j-pa[1])) );
float bdist = sqrt( ((i-pb[0])*(i-pb[0]))+((j-pb[1])*(j-pb[1])) );
/*save to array*/
wa[lID] = (sin(adist)+sin(bdist))/2;
}
/*Main function (ofc)*/
int main(int argc, char** argv)
{
/*allocate memory for "normal" array*/
float *wav_array = (float*)malloc(sizeof(float)*900*900);
/*allocate memory on the GPU*/
float *gpu_wav_array;
hipMalloc(&gpu_wav_array, 900*900*sizeof(float));
/*define block size*/
dim3 block_size;
block_size.x = 30;
block_size.y = 30;
block_size.z = 1;
/*define grid dimensions*/
dim3 grid_size;
grid_size.x = 30;
grid_size.y = 30;
/*Launch the kernels*/
sin_dist<<<block_size, grid_size>>>(gpu_wav_array);
/*Copy the data back from the GPU*/
hipMemcpy(wav_array, gpu_wav_array, 900*900*sizeof(float), hipMemcpyDeviceToHost);
return 0;
} | .text
.file "waves_cuda.hip"
.globl _Z23__device_stub__sin_distPf # -- Begin function _Z23__device_stub__sin_distPf
.p2align 4, 0x90
.type _Z23__device_stub__sin_distPf,@function
_Z23__device_stub__sin_distPf: # @_Z23__device_stub__sin_distPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z8sin_distPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z23__device_stub__sin_distPf, .Lfunc_end0-_Z23__device_stub__sin_distPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
movl $3240000, %edi # imm = 0x317040
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $3240000, %esi # imm = 0x317040
callq hipMalloc
movabsq $128849018910, %rdi # imm = 0x1E0000001E
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z8sin_distPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movl $3240000, %edx # imm = 0x317040
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8sin_distPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8sin_distPf,@object # @_Z8sin_distPf
.section .rodata,"a",@progbits
.globl _Z8sin_distPf
.p2align 3, 0x0
_Z8sin_distPf:
.quad _Z23__device_stub__sin_distPf
.size _Z8sin_distPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8sin_distPf"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__sin_distPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8sin_distPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d45d9_00000000-6_waves_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z8sin_distPfPf
.type _Z27__device_stub__Z8sin_distPfPf, @function
_Z27__device_stub__Z8sin_distPfPf:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8sin_distPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z8sin_distPfPf, .-_Z27__device_stub__Z8sin_distPfPf
.globl _Z8sin_distPf
.type _Z8sin_distPf, @function
_Z8sin_distPf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z8sin_distPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8sin_distPf, .-_Z8sin_distPf
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $3240000, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $3240000, %esi
call cudaMalloc@PLT
movl $30, 16(%rsp)
movl $30, 20(%rsp)
movl $30, 28(%rsp)
movl $30, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movl $3240000, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z27__device_stub__Z8sin_distPfPf
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8sin_distPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8sin_distPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "waves_cuda.hip"
.globl _Z23__device_stub__sin_distPf # -- Begin function _Z23__device_stub__sin_distPf
.p2align 4, 0x90
.type _Z23__device_stub__sin_distPf,@function
_Z23__device_stub__sin_distPf: # @_Z23__device_stub__sin_distPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z8sin_distPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z23__device_stub__sin_distPf, .Lfunc_end0-_Z23__device_stub__sin_distPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
movl $3240000, %edi # imm = 0x317040
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $3240000, %esi # imm = 0x317040
callq hipMalloc
movabsq $128849018910, %rdi # imm = 0x1E0000001E
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z8sin_distPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movl $3240000, %edx # imm = 0x317040
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8sin_distPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8sin_distPf,@object # @_Z8sin_distPf
.section .rodata,"a",@progbits
.globl _Z8sin_distPf
.p2align 3, 0x0
_Z8sin_distPf:
.quad _Z23__device_stub__sin_distPf
.size _Z8sin_distPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8sin_distPf"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__sin_distPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8sin_distPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kern_ResetSinkBuffer(float* sink, float* source, float* div, float* label, float ik, float iCC, int size)
{
int idx = CUDASTDOFFSET;
float value = (1.0f-ik)*sink[idx] + ik*(source[idx] - div[idx] + label[idx] * iCC);
if( idx < size )
{
sink[idx] = value;
}
} | code for sm_80
Function : _Z20kern_ResetSinkBufferPfS_S_S_ffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Z ; /* 0x0000000000007919 */
/* 0x000e220000002700 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0050*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0x10], R3 ; /* 0x0000040000007a24 */
/* 0x001fe200078e0203 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc600000001ff */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fc800078e0207 */
/*00a0*/ IMAD.WIDE R6, R0, R3, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0203 */
/*00b0*/ IMAD.WIDE R4, R0.reuse, R3.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0203 */
/*00c0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ IMAD.WIDE R8, R0.reuse, R3.reuse, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x0c0fe400078e0203 */
/*00e0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee2000c1e1900 */
/*0100*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0110*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000f22000c1e1900 */
/*0120*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x188], PT ; /* 0x0000620000007a0c */
/* 0x000fe40003f06270 */
/*0130*/ MOV R12, c[0x0][0x180] ; /* 0x00006000000c7a02 */
/* 0x000fe20000000f00 */
/*0140*/ FADD R11, -R6, R5 ; /* 0x00000005060b7221 */
/* 0x004fc80000000100 */
/*0150*/ FFMA R0, R8, c[0x0][0x184], R11 ; /* 0x0000610008007a23 */
/* 0x008fe4000000000b */
/*0160*/ FADD R11, -R12, 1 ; /* 0x3f8000000c0b7421 */
/* 0x000fe40000000100 */
/*0170*/ FMUL R0, R0, c[0x0][0x180] ; /* 0x0000600000007a20 */
/* 0x000fc80000400000 */
/*0180*/ FFMA R11, R10, R11, R0 ; /* 0x0000000b0a0b7223 */
/* 0x010fe20000000000 */
/*0190*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fec0003800000 */
/*01a0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kern_ResetSinkBuffer(float* sink, float* source, float* div, float* label, float ik, float iCC, int size)
{
int idx = CUDASTDOFFSET;
float value = (1.0f-ik)*sink[idx] + ik*(source[idx] - div[idx] + label[idx] * iCC);
if( idx < size )
{
sink[idx] = value;
}
} | .file "tmpxft_00136cd0_00000000-6_kern_ResetSinkBuffer.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z20kern_ResetSinkBufferPfS_S_S_ffiPfS_S_S_ffi
.type _Z49__device_stub__Z20kern_ResetSinkBufferPfS_S_S_ffiPfS_S_S_ffi, @function
_Z49__device_stub__Z20kern_ResetSinkBufferPfS_S_S_ffiPfS_S_S_ffi:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20kern_ResetSinkBufferPfS_S_S_ffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z20kern_ResetSinkBufferPfS_S_S_ffiPfS_S_S_ffi, .-_Z49__device_stub__Z20kern_ResetSinkBufferPfS_S_S_ffiPfS_S_S_ffi
.globl _Z20kern_ResetSinkBufferPfS_S_S_ffi
.type _Z20kern_ResetSinkBufferPfS_S_S_ffi, @function
_Z20kern_ResetSinkBufferPfS_S_S_ffi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z20kern_ResetSinkBufferPfS_S_S_ffiPfS_S_S_ffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20kern_ResetSinkBufferPfS_S_S_ffi, .-_Z20kern_ResetSinkBufferPfS_S_S_ffi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20kern_ResetSinkBufferPfS_S_S_ffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20kern_ResetSinkBufferPfS_S_S_ffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kern_ResetSinkBuffer(float* sink, float* source, float* div, float* label, float ik, float iCC, int size)
{
int idx = CUDASTDOFFSET;
float value = (1.0f-ik)*sink[idx] + ik*(source[idx] - div[idx] + label[idx] * iCC);
if( idx < size )
{
sink[idx] = value;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kern_ResetSinkBuffer(float* sink, float* source, float* div, float* label, float ik, float iCC, int size)
{
int idx = CUDASTDOFFSET;
float value = (1.0f-ik)*sink[idx] + ik*(source[idx] - div[idx] + label[idx] * iCC);
if( idx < size )
{
sink[idx] = value;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kern_ResetSinkBuffer(float* sink, float* source, float* div, float* label, float ik, float iCC, int size)
{
int idx = CUDASTDOFFSET;
float value = (1.0f-ik)*sink[idx] + ik*(source[idx] - div[idx] + label[idx] * iCC);
if( idx < size )
{
sink[idx] = value;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20kern_ResetSinkBufferPfS_S_S_ffi
.globl _Z20kern_ResetSinkBufferPfS_S_S_ffi
.p2align 8
.type _Z20kern_ResetSinkBufferPfS_S_S_ffi,@function
_Z20kern_ResetSinkBufferPfS_S_S_ffi:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x30
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s5, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s14
s_mul_i32 s2, s3, s2
s_and_b32 s3, s4, 0xffff
s_add_i32 s2, s2, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_2
s_load_b256 s[4:11], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v1, vcc_lo
global_load_b32 v6, v[2:3], off
global_load_b32 v4, v[4:5], off
v_add_co_u32 v2, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(2)
v_sub_f32_e32 v4, v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v4, s1, v2
v_sub_f32_e64 v2, 1.0, s0
v_mul_f32_e32 v4, s0, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v4, v2, v3
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20kern_ResetSinkBufferPfS_S_S_ffi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20kern_ResetSinkBufferPfS_S_S_ffi, .Lfunc_end0-_Z20kern_ResetSinkBufferPfS_S_S_ffi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20kern_ResetSinkBufferPfS_S_S_ffi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20kern_ResetSinkBufferPfS_S_S_ffi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kern_ResetSinkBuffer(float* sink, float* source, float* div, float* label, float ik, float iCC, int size)
{
int idx = CUDASTDOFFSET;
float value = (1.0f-ik)*sink[idx] + ik*(source[idx] - div[idx] + label[idx] * iCC);
if( idx < size )
{
sink[idx] = value;
}
} | .text
.file "kern_ResetSinkBuffer.hip"
.globl _Z35__device_stub__kern_ResetSinkBufferPfS_S_S_ffi # -- Begin function _Z35__device_stub__kern_ResetSinkBufferPfS_S_S_ffi
.p2align 4, 0x90
.type _Z35__device_stub__kern_ResetSinkBufferPfS_S_S_ffi,@function
_Z35__device_stub__kern_ResetSinkBufferPfS_S_S_ffi: # @_Z35__device_stub__kern_ResetSinkBufferPfS_S_S_ffi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20kern_ResetSinkBufferPfS_S_S_ffi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z35__device_stub__kern_ResetSinkBufferPfS_S_S_ffi, .Lfunc_end0-_Z35__device_stub__kern_ResetSinkBufferPfS_S_S_ffi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20kern_ResetSinkBufferPfS_S_S_ffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20kern_ResetSinkBufferPfS_S_S_ffi,@object # @_Z20kern_ResetSinkBufferPfS_S_S_ffi
.section .rodata,"a",@progbits
.globl _Z20kern_ResetSinkBufferPfS_S_S_ffi
.p2align 3, 0x0
_Z20kern_ResetSinkBufferPfS_S_S_ffi:
.quad _Z35__device_stub__kern_ResetSinkBufferPfS_S_S_ffi
.size _Z20kern_ResetSinkBufferPfS_S_S_ffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20kern_ResetSinkBufferPfS_S_S_ffi"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__kern_ResetSinkBufferPfS_S_S_ffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20kern_ResetSinkBufferPfS_S_S_ffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20kern_ResetSinkBufferPfS_S_S_ffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Z ; /* 0x0000000000007919 */
/* 0x000e220000002700 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0050*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0x10], R3 ; /* 0x0000040000007a24 */
/* 0x001fe200078e0203 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc600000001ff */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fc800078e0207 */
/*00a0*/ IMAD.WIDE R6, R0, R3, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0203 */
/*00b0*/ IMAD.WIDE R4, R0.reuse, R3.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0203 */
/*00c0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ IMAD.WIDE R8, R0.reuse, R3.reuse, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x0c0fe400078e0203 */
/*00e0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee2000c1e1900 */
/*0100*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0110*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000f22000c1e1900 */
/*0120*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x188], PT ; /* 0x0000620000007a0c */
/* 0x000fe40003f06270 */
/*0130*/ MOV R12, c[0x0][0x180] ; /* 0x00006000000c7a02 */
/* 0x000fe20000000f00 */
/*0140*/ FADD R11, -R6, R5 ; /* 0x00000005060b7221 */
/* 0x004fc80000000100 */
/*0150*/ FFMA R0, R8, c[0x0][0x184], R11 ; /* 0x0000610008007a23 */
/* 0x008fe4000000000b */
/*0160*/ FADD R11, -R12, 1 ; /* 0x3f8000000c0b7421 */
/* 0x000fe40000000100 */
/*0170*/ FMUL R0, R0, c[0x0][0x180] ; /* 0x0000600000007a20 */
/* 0x000fc80000400000 */
/*0180*/ FFMA R11, R10, R11, R0 ; /* 0x0000000b0a0b7223 */
/* 0x010fe20000000000 */
/*0190*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fec0003800000 */
/*01a0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20kern_ResetSinkBufferPfS_S_S_ffi
.globl _Z20kern_ResetSinkBufferPfS_S_S_ffi
.p2align 8
.type _Z20kern_ResetSinkBufferPfS_S_S_ffi,@function
_Z20kern_ResetSinkBufferPfS_S_S_ffi:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x30
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s5, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s14
s_mul_i32 s2, s3, s2
s_and_b32 s3, s4, 0xffff
s_add_i32 s2, s2, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_2
s_load_b256 s[4:11], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v1, vcc_lo
global_load_b32 v6, v[2:3], off
global_load_b32 v4, v[4:5], off
v_add_co_u32 v2, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(2)
v_sub_f32_e32 v4, v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v4, s1, v2
v_sub_f32_e64 v2, 1.0, s0
v_mul_f32_e32 v4, s0, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v4, v2, v3
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20kern_ResetSinkBufferPfS_S_S_ffi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20kern_ResetSinkBufferPfS_S_S_ffi, .Lfunc_end0-_Z20kern_ResetSinkBufferPfS_S_S_ffi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20kern_ResetSinkBufferPfS_S_S_ffi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20kern_ResetSinkBufferPfS_S_S_ffi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00136cd0_00000000-6_kern_ResetSinkBuffer.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z20kern_ResetSinkBufferPfS_S_S_ffiPfS_S_S_ffi
.type _Z49__device_stub__Z20kern_ResetSinkBufferPfS_S_S_ffiPfS_S_S_ffi, @function
_Z49__device_stub__Z20kern_ResetSinkBufferPfS_S_S_ffiPfS_S_S_ffi:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20kern_ResetSinkBufferPfS_S_S_ffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z20kern_ResetSinkBufferPfS_S_S_ffiPfS_S_S_ffi, .-_Z49__device_stub__Z20kern_ResetSinkBufferPfS_S_S_ffiPfS_S_S_ffi
.globl _Z20kern_ResetSinkBufferPfS_S_S_ffi
.type _Z20kern_ResetSinkBufferPfS_S_S_ffi, @function
_Z20kern_ResetSinkBufferPfS_S_S_ffi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z20kern_ResetSinkBufferPfS_S_S_ffiPfS_S_S_ffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20kern_ResetSinkBufferPfS_S_S_ffi, .-_Z20kern_ResetSinkBufferPfS_S_S_ffi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20kern_ResetSinkBufferPfS_S_S_ffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20kern_ResetSinkBufferPfS_S_S_ffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kern_ResetSinkBuffer.hip"
.globl _Z35__device_stub__kern_ResetSinkBufferPfS_S_S_ffi # -- Begin function _Z35__device_stub__kern_ResetSinkBufferPfS_S_S_ffi
.p2align 4, 0x90
.type _Z35__device_stub__kern_ResetSinkBufferPfS_S_S_ffi,@function
_Z35__device_stub__kern_ResetSinkBufferPfS_S_S_ffi: # @_Z35__device_stub__kern_ResetSinkBufferPfS_S_S_ffi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20kern_ResetSinkBufferPfS_S_S_ffi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z35__device_stub__kern_ResetSinkBufferPfS_S_S_ffi, .Lfunc_end0-_Z35__device_stub__kern_ResetSinkBufferPfS_S_S_ffi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20kern_ResetSinkBufferPfS_S_S_ffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20kern_ResetSinkBufferPfS_S_S_ffi,@object # @_Z20kern_ResetSinkBufferPfS_S_S_ffi
.section .rodata,"a",@progbits
.globl _Z20kern_ResetSinkBufferPfS_S_S_ffi
.p2align 3, 0x0
_Z20kern_ResetSinkBufferPfS_S_S_ffi:
.quad _Z35__device_stub__kern_ResetSinkBufferPfS_S_S_ffi
.size _Z20kern_ResetSinkBufferPfS_S_S_ffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20kern_ResetSinkBufferPfS_S_S_ffi"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__kern_ResetSinkBufferPfS_S_S_ffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20kern_ResetSinkBufferPfS_S_S_ffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
static void HandleError( cudaError_t err, const char *file, int line ) {
if (err != cudaSuccess) {
::printf( "%s in %s at line %d\n", cudaGetErrorString( err ), file, line );
::exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
#define N 100000
#define cudaCheckErrors(msg) \
do { \
cudaError_t __err = cudaGetLastError(); \
if (__err != cudaSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n",msg, cudaGetErrorString(__err), __FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
__global__ void add( int *a, int *b, int *c ) {
int tid = blockIdx.x; // this thread handles the data at its thread id
if (tid < N)
c[tid] = a[tid] + b[tid];
}
extern "C" void Cuda_Main_Test1(){
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
// allocate the memory on the GPU
HANDLE_ERROR( cudaMalloc( (void**)&dev_a, N * sizeof(int) ) );
HANDLE_ERROR( cudaMalloc( (void**)&dev_b, N * sizeof(int) ) );
HANDLE_ERROR( cudaMalloc( (void**)&dev_c, N * sizeof(int) ) );
// cudaCheckErrors("cudamalloc fail");
// fill the arrays 'a' and 'b' on the CPU
for (int i=0; i<N; i++) {
a[i] = i;
b[i] = i;
c[i] = 0;
}
// copy the arrays 'a' and 'b' to the GPU
HANDLE_ERROR( cudaMemcpy( dev_a, a, N * sizeof(int), cudaMemcpyHostToDevice ) );
//HANDLE_ERROR( cudaMemcpy( dev_b, b, N * sizeof(int), cudaMemcpyHostToDevice ) );
cudaError_t status = cudaMemcpy(dev_b, b, N * sizeof(int), cudaMemcpyHostToDevice);
// cudaCheckErrors("cuda memcpy fail");
//sleep(1);
add<<<N,1>>>(dev_a,dev_b,dev_c);
// sleep(1);
// copy the array 'c' back from the GPU to the CPU
HANDLE_ERROR( cudaMemcpy( c, dev_c, N * sizeof(int), cudaMemcpyDeviceToHost ) );
// if (status == cudaSuccess) {
// printf( "0 CUDA Error: %s \n", cudaGetErrorString( status ) );
// }
// if (status != cudaSuccess) {
// printf( "1 CUDA Error: %s \n", cudaGetErrorString( status ) );
// // cout << "CUDA Error: " << cudaGetErrorString( cuerr ) << endl
// }
// cudaCheckErrors("cudamemcpy or cuda kernel fail");
// sleep(1);
// display the results
for (int i=0; i<N; i++) {
// printf( "%d + %d = %d\n", a[i], b[i], c[i] );
printf( "%d%c ", c[i],((i%8==7)?'\n':' '));
}
printf( "Start CPU add \n ");
for (int i=0; i<N; i++) {
c[i]=a[i]+b[i];
//printf( "%d%c ", c[i],((i%8==7)?'\n':' '));
}
printf( "Stop CPU add \n ");
// free the memory allocated on the GPU
HANDLE_ERROR( cudaFree( dev_a ) );
HANDLE_ERROR( cudaFree( dev_b ) );
HANDLE_ERROR( cudaFree( dev_c ) );
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x1869f, PT ; /* 0x0001869f0600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
static void HandleError( cudaError_t err, const char *file, int line ) {
if (err != cudaSuccess) {
::printf( "%s in %s at line %d\n", cudaGetErrorString( err ), file, line );
::exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
#define N 100000
#define cudaCheckErrors(msg) \
do { \
cudaError_t __err = cudaGetLastError(); \
if (__err != cudaSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n",msg, cudaGetErrorString(__err), __FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
__global__ void add( int *a, int *b, int *c ) {
int tid = blockIdx.x; // this thread handles the data at its thread id
if (tid < N)
c[tid] = a[tid] + b[tid];
}
extern "C" void Cuda_Main_Test1(){
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
// allocate the memory on the GPU
HANDLE_ERROR( cudaMalloc( (void**)&dev_a, N * sizeof(int) ) );
HANDLE_ERROR( cudaMalloc( (void**)&dev_b, N * sizeof(int) ) );
HANDLE_ERROR( cudaMalloc( (void**)&dev_c, N * sizeof(int) ) );
// cudaCheckErrors("cudamalloc fail");
// fill the arrays 'a' and 'b' on the CPU
for (int i=0; i<N; i++) {
a[i] = i;
b[i] = i;
c[i] = 0;
}
// copy the arrays 'a' and 'b' to the GPU
HANDLE_ERROR( cudaMemcpy( dev_a, a, N * sizeof(int), cudaMemcpyHostToDevice ) );
//HANDLE_ERROR( cudaMemcpy( dev_b, b, N * sizeof(int), cudaMemcpyHostToDevice ) );
cudaError_t status = cudaMemcpy(dev_b, b, N * sizeof(int), cudaMemcpyHostToDevice);
// cudaCheckErrors("cuda memcpy fail");
//sleep(1);
add<<<N,1>>>(dev_a,dev_b,dev_c);
// sleep(1);
// copy the array 'c' back from the GPU to the CPU
HANDLE_ERROR( cudaMemcpy( c, dev_c, N * sizeof(int), cudaMemcpyDeviceToHost ) );
// if (status == cudaSuccess) {
// printf( "0 CUDA Error: %s \n", cudaGetErrorString( status ) );
// }
// if (status != cudaSuccess) {
// printf( "1 CUDA Error: %s \n", cudaGetErrorString( status ) );
// // cout << "CUDA Error: " << cudaGetErrorString( cuerr ) << endl
// }
// cudaCheckErrors("cudamemcpy or cuda kernel fail");
// sleep(1);
// display the results
for (int i=0; i<N; i++) {
// printf( "%d + %d = %d\n", a[i], b[i], c[i] );
printf( "%d%c ", c[i],((i%8==7)?'\n':' '));
}
printf( "Start CPU add \n ");
for (int i=0; i<N; i++) {
c[i]=a[i]+b[i];
//printf( "%d%c ", c[i],((i%8==7)?'\n':' '));
}
printf( "Stop CPU add \n ");
// free the memory allocated on the GPU
HANDLE_ERROR( cudaFree( dev_a ) );
HANDLE_ERROR( cudaFree( dev_b ) );
HANDLE_ERROR( cudaFree( dev_c ) );
} | .file "tmpxft_001a53e9_00000000-6_cuda.cudafe1.cpp"
.text
#APP
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s in %s at line %d\n"
#NO_APP
.text
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB2057:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _ZL11HandleError9cudaErrorPKci, .-_ZL11HandleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/ArefyevDenis/ArefyevDenis/master/cuda_sub_dir/cuda_one/cuda.cu"
.section .rodata.str1.1
.LC2:
.string "%d%c "
.LC3:
.string "Start CPU add \n "
.LC4:
.string "Stop CPU add \n "
.text
.globl Cuda_Main_Test1
.type Cuda_Main_Test1, @function
Cuda_Main_Test1:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
leaq -1196032(%rsp), %r11
.cfi_def_cfa 11, 1196056
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $4040, %rsp
.cfi_def_cfa_offset 1200096
movq %fs:40, %rax
movq %rax, 1200056(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $400000, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $36, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 8(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $37, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 16(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $38, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %eax
.L18:
movl %eax, 48(%rsp,%rax,4)
movl %eax, 400048(%rsp,%rax,4)
movl $0, 800048(%rsp,%rax,4)
addq $1, %rax
cmpq $100000, %rax
jne .L18
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $400000, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $48, %edx
leaq .LC1(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 400048(%rsp), %rsi
movl $1, %ecx
movl $400000, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $100000, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L19:
leaq 800048(%rsp), %rdi
movl $2, %ecx
movl $400000, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
movl $57, %edx
leaq .LC1(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L21:
movl %ebx, %edx
sarl $31, %edx
shrl $29, %edx
leal (%rdx,%rbx), %eax
andl $7, %eax
subl %edx, %eax
cmpl $7, %eax
movl $32, %ecx
movl $10, %eax
cmove %eax, %ecx
movl 800048(%rsp,%rbx,4), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $100000, %rbx
jne .L21
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L22:
movl 400048(%rsp,%rax), %edx
addl 48(%rsp,%rax), %edx
movl %edx, 800048(%rsp,%rax)
addq $4, %rax
cmpq $400000, %rax
jne .L22
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $80, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $81, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $82, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movq 1200056(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $1200072, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L19
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size Cuda_Main_Test1, .-Cuda_Main_Test1
.section .rodata.str1.1
.LC5:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
static void HandleError( cudaError_t err, const char *file, int line ) {
if (err != cudaSuccess) {
::printf( "%s in %s at line %d\n", cudaGetErrorString( err ), file, line );
::exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
#define N 100000
#define cudaCheckErrors(msg) \
do { \
cudaError_t __err = cudaGetLastError(); \
if (__err != cudaSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n",msg, cudaGetErrorString(__err), __FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
__global__ void add( int *a, int *b, int *c ) {
int tid = blockIdx.x; // this thread handles the data at its thread id
if (tid < N)
c[tid] = a[tid] + b[tid];
}
extern "C" void Cuda_Main_Test1(){
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
// allocate the memory on the GPU
HANDLE_ERROR( cudaMalloc( (void**)&dev_a, N * sizeof(int) ) );
HANDLE_ERROR( cudaMalloc( (void**)&dev_b, N * sizeof(int) ) );
HANDLE_ERROR( cudaMalloc( (void**)&dev_c, N * sizeof(int) ) );
// cudaCheckErrors("cudamalloc fail");
// fill the arrays 'a' and 'b' on the CPU
for (int i=0; i<N; i++) {
a[i] = i;
b[i] = i;
c[i] = 0;
}
// copy the arrays 'a' and 'b' to the GPU
HANDLE_ERROR( cudaMemcpy( dev_a, a, N * sizeof(int), cudaMemcpyHostToDevice ) );
//HANDLE_ERROR( cudaMemcpy( dev_b, b, N * sizeof(int), cudaMemcpyHostToDevice ) );
cudaError_t status = cudaMemcpy(dev_b, b, N * sizeof(int), cudaMemcpyHostToDevice);
// cudaCheckErrors("cuda memcpy fail");
//sleep(1);
add<<<N,1>>>(dev_a,dev_b,dev_c);
// sleep(1);
// copy the array 'c' back from the GPU to the CPU
HANDLE_ERROR( cudaMemcpy( c, dev_c, N * sizeof(int), cudaMemcpyDeviceToHost ) );
// if (status == cudaSuccess) {
// printf( "0 CUDA Error: %s \n", cudaGetErrorString( status ) );
// }
// if (status != cudaSuccess) {
// printf( "1 CUDA Error: %s \n", cudaGetErrorString( status ) );
// // cout << "CUDA Error: " << cudaGetErrorString( cuerr ) << endl
// }
// cudaCheckErrors("cudamemcpy or cuda kernel fail");
// sleep(1);
// display the results
for (int i=0; i<N; i++) {
// printf( "%d + %d = %d\n", a[i], b[i], c[i] );
printf( "%d%c ", c[i],((i%8==7)?'\n':' '));
}
printf( "Start CPU add \n ");
for (int i=0; i<N; i++) {
c[i]=a[i]+b[i];
//printf( "%d%c ", c[i],((i%8==7)?'\n':' '));
}
printf( "Stop CPU add \n ");
// free the memory allocated on the GPU
HANDLE_ERROR( cudaFree( dev_a ) );
HANDLE_ERROR( cudaFree( dev_b ) );
HANDLE_ERROR( cudaFree( dev_c ) );
} | #include <hip/hip_runtime.h>
#include <stdio.h>
static void HandleError( hipError_t err, const char *file, int line ) {
if (err != hipSuccess) {
::printf( "%s in %s at line %d\n", hipGetErrorString( err ), file, line );
::exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
#define N 100000
#define cudaCheckErrors(msg) \
do { \
hipError_t __err = hipGetLastError(); \
if (__err != hipSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n",msg, hipGetErrorString(__err), __FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
__global__ void add( int *a, int *b, int *c ) {
int tid = blockIdx.x; // this thread handles the data at its thread id
if (tid < N)
c[tid] = a[tid] + b[tid];
}
extern "C" void Cuda_Main_Test1(){
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
// allocate the memory on the GPU
HANDLE_ERROR( hipMalloc( (void**)&dev_a, N * sizeof(int) ) );
HANDLE_ERROR( hipMalloc( (void**)&dev_b, N * sizeof(int) ) );
HANDLE_ERROR( hipMalloc( (void**)&dev_c, N * sizeof(int) ) );
// cudaCheckErrors("cudamalloc fail");
// fill the arrays 'a' and 'b' on the CPU
for (int i=0; i<N; i++) {
a[i] = i;
b[i] = i;
c[i] = 0;
}
// copy the arrays 'a' and 'b' to the GPU
HANDLE_ERROR( hipMemcpy( dev_a, a, N * sizeof(int), hipMemcpyHostToDevice ) );
//HANDLE_ERROR( cudaMemcpy( dev_b, b, N * sizeof(int), cudaMemcpyHostToDevice ) );
hipError_t status = hipMemcpy(dev_b, b, N * sizeof(int), hipMemcpyHostToDevice);
// cudaCheckErrors("cuda memcpy fail");
//sleep(1);
add<<<N,1>>>(dev_a,dev_b,dev_c);
// sleep(1);
// copy the array 'c' back from the GPU to the CPU
HANDLE_ERROR( hipMemcpy( c, dev_c, N * sizeof(int), hipMemcpyDeviceToHost ) );
// if (status == cudaSuccess) {
// printf( "0 CUDA Error: %s \n", cudaGetErrorString( status ) );
// }
// if (status != cudaSuccess) {
// printf( "1 CUDA Error: %s \n", cudaGetErrorString( status ) );
// // cout << "CUDA Error: " << cudaGetErrorString( cuerr ) << endl
// }
// cudaCheckErrors("cudamemcpy or cuda kernel fail");
// sleep(1);
// display the results
for (int i=0; i<N; i++) {
// printf( "%d + %d = %d\n", a[i], b[i], c[i] );
printf( "%d%c ", c[i],((i%8==7)?'\n':' '));
}
printf( "Start CPU add \n ");
for (int i=0; i<N; i++) {
c[i]=a[i]+b[i];
//printf( "%d%c ", c[i],((i%8==7)?'\n':' '));
}
printf( "Stop CPU add \n ");
// free the memory allocated on the GPU
HANDLE_ERROR( hipFree( dev_a ) );
HANDLE_ERROR( hipFree( dev_b ) );
HANDLE_ERROR( hipFree( dev_c ) );
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
static void HandleError( hipError_t err, const char *file, int line ) {
if (err != hipSuccess) {
::printf( "%s in %s at line %d\n", hipGetErrorString( err ), file, line );
::exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
#define N 100000
#define cudaCheckErrors(msg) \
do { \
hipError_t __err = hipGetLastError(); \
if (__err != hipSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n",msg, hipGetErrorString(__err), __FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
__global__ void add( int *a, int *b, int *c ) {
int tid = blockIdx.x; // this thread handles the data at its thread id
if (tid < N)
c[tid] = a[tid] + b[tid];
}
extern "C" void Cuda_Main_Test1(){
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
// allocate the memory on the GPU
HANDLE_ERROR( hipMalloc( (void**)&dev_a, N * sizeof(int) ) );
HANDLE_ERROR( hipMalloc( (void**)&dev_b, N * sizeof(int) ) );
HANDLE_ERROR( hipMalloc( (void**)&dev_c, N * sizeof(int) ) );
// cudaCheckErrors("cudamalloc fail");
// fill the arrays 'a' and 'b' on the CPU
for (int i=0; i<N; i++) {
a[i] = i;
b[i] = i;
c[i] = 0;
}
// copy the arrays 'a' and 'b' to the GPU
HANDLE_ERROR( hipMemcpy( dev_a, a, N * sizeof(int), hipMemcpyHostToDevice ) );
//HANDLE_ERROR( cudaMemcpy( dev_b, b, N * sizeof(int), cudaMemcpyHostToDevice ) );
hipError_t status = hipMemcpy(dev_b, b, N * sizeof(int), hipMemcpyHostToDevice);
// cudaCheckErrors("cuda memcpy fail");
//sleep(1);
add<<<N,1>>>(dev_a,dev_b,dev_c);
// sleep(1);
// copy the array 'c' back from the GPU to the CPU
HANDLE_ERROR( hipMemcpy( c, dev_c, N * sizeof(int), hipMemcpyDeviceToHost ) );
// if (status == cudaSuccess) {
// printf( "0 CUDA Error: %s \n", cudaGetErrorString( status ) );
// }
// if (status != cudaSuccess) {
// printf( "1 CUDA Error: %s \n", cudaGetErrorString( status ) );
// // cout << "CUDA Error: " << cudaGetErrorString( cuerr ) << endl
// }
// cudaCheckErrors("cudamemcpy or cuda kernel fail");
// sleep(1);
// display the results
for (int i=0; i<N; i++) {
// printf( "%d + %d = %d\n", a[i], b[i], c[i] );
printf( "%d%c ", c[i],((i%8==7)?'\n':' '));
}
printf( "Start CPU add \n ");
for (int i=0; i<N; i++) {
c[i]=a[i]+b[i];
//printf( "%d%c ", c[i],((i%8==7)?'\n':' '));
}
printf( "Stop CPU add \n ");
// free the memory allocated on the GPU
HANDLE_ERROR( hipFree( dev_a ) );
HANDLE_ERROR( hipFree( dev_b ) );
HANDLE_ERROR( hipFree( dev_c ) );
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_cmp_gt_i32 s15, 0x1869f
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
static void HandleError( hipError_t err, const char *file, int line ) {
if (err != hipSuccess) {
::printf( "%s in %s at line %d\n", hipGetErrorString( err ), file, line );
::exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
#define N 100000
#define cudaCheckErrors(msg) \
do { \
hipError_t __err = hipGetLastError(); \
if (__err != hipSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n",msg, hipGetErrorString(__err), __FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
__global__ void add( int *a, int *b, int *c ) {
int tid = blockIdx.x; // this thread handles the data at its thread id
if (tid < N)
c[tid] = a[tid] + b[tid];
}
extern "C" void Cuda_Main_Test1(){
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
// allocate the memory on the GPU
HANDLE_ERROR( hipMalloc( (void**)&dev_a, N * sizeof(int) ) );
HANDLE_ERROR( hipMalloc( (void**)&dev_b, N * sizeof(int) ) );
HANDLE_ERROR( hipMalloc( (void**)&dev_c, N * sizeof(int) ) );
// cudaCheckErrors("cudamalloc fail");
// fill the arrays 'a' and 'b' on the CPU
for (int i=0; i<N; i++) {
a[i] = i;
b[i] = i;
c[i] = 0;
}
// copy the arrays 'a' and 'b' to the GPU
HANDLE_ERROR( hipMemcpy( dev_a, a, N * sizeof(int), hipMemcpyHostToDevice ) );
//HANDLE_ERROR( cudaMemcpy( dev_b, b, N * sizeof(int), cudaMemcpyHostToDevice ) );
hipError_t status = hipMemcpy(dev_b, b, N * sizeof(int), hipMemcpyHostToDevice);
// cudaCheckErrors("cuda memcpy fail");
//sleep(1);
add<<<N,1>>>(dev_a,dev_b,dev_c);
// sleep(1);
// copy the array 'c' back from the GPU to the CPU
HANDLE_ERROR( hipMemcpy( c, dev_c, N * sizeof(int), hipMemcpyDeviceToHost ) );
// if (status == cudaSuccess) {
// printf( "0 CUDA Error: %s \n", cudaGetErrorString( status ) );
// }
// if (status != cudaSuccess) {
// printf( "1 CUDA Error: %s \n", cudaGetErrorString( status ) );
// // cout << "CUDA Error: " << cudaGetErrorString( cuerr ) << endl
// }
// cudaCheckErrors("cudamemcpy or cuda kernel fail");
// sleep(1);
// display the results
for (int i=0; i<N; i++) {
// printf( "%d + %d = %d\n", a[i], b[i], c[i] );
printf( "%d%c ", c[i],((i%8==7)?'\n':' '));
}
printf( "Start CPU add \n ");
for (int i=0; i<N; i++) {
c[i]=a[i]+b[i];
//printf( "%d%c ", c[i],((i%8==7)?'\n':' '));
}
printf( "Stop CPU add \n ");
// free the memory allocated on the GPU
HANDLE_ERROR( hipFree( dev_a ) );
HANDLE_ERROR( hipFree( dev_b ) );
HANDLE_ERROR( hipFree( dev_c ) );
} | .text
.file "cuda.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl Cuda_Main_Test1 # -- Begin function Cuda_Main_Test1
.p2align 4, 0x90
.type Cuda_Main_Test1,@function
Cuda_Main_Test1: # @Cuda_Main_Test1
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1200136, %rsp # imm = 0x125008
.cfi_def_cfa_offset 1200160
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_ZL11HandleError10hipError_tPKci.exit
leaq 8(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_ZL11HandleError10hipError_tPKci.exit21
movq %rsp, %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
testl %eax, %eax
jne .LBB1_24
# %bb.6: # %_ZL11HandleError10hipError_tPKci.exit23.preheader
leaq 128(%rsp), %rdi
xorl %ebx, %ebx
movl $400000, %edx # imm = 0x61A80
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_7: # %_ZL11HandleError10hipError_tPKci.exit23
# =>This Inner Loop Header: Depth=1
movl %ebx, 800128(%rsp,%rbx,4)
movl %ebx, 400128(%rsp,%rbx,4)
incq %rbx
cmpq $100000, %rbx # imm = 0x186A0
jne .LBB1_7
# %bb.8:
movq 16(%rsp), %rdi
leaq 800128(%rsp), %rsi
movl $400000, %edx # imm = 0x61A80
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_9
# %bb.10: # %_ZL11HandleError10hipError_tPKci.exit25
movq 8(%rsp), %rdi
leaq 400128(%rsp), %rsi
movl $400000, %edx # imm = 0x61A80
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 99999(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_12
# %bb.11:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_12:
movq (%rsp), %rsi
leaq 128(%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_25
# %bb.13: # %_ZL11HandleError10hipError_tPKci.exit27.preheader
movl $10, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_14: # %_ZL11HandleError10hipError_tPKci.exit27
# =>This Inner Loop Header: Depth=1
movl 128(%rsp,%r14,4), %esi
movl %r14d, %eax
notl %eax
testb $7, %al
movl $32, %edx
cmovel %ebx, %edx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $100000, %r14 # imm = 0x186A0
jne .LBB1_14
# %bb.15:
xorl %ebx, %ebx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB1_16: # =>This Inner Loop Header: Depth=1
movl 400128(%rsp,%rbx,4), %eax
addl 800128(%rsp,%rbx,4), %eax
movl %eax, 128(%rsp,%rbx,4)
incq %rbx
cmpq $100000, %rbx # imm = 0x186A0
jne .LBB1_16
# %bb.17:
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_18
# %bb.19: # %_ZL11HandleError10hipError_tPKci.exit29
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_20
# %bb.21: # %_ZL11HandleError10hipError_tPKci.exit31
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_22
# %bb.23: # %_ZL11HandleError10hipError_tPKci.exit33
addq $1200136, %rsp # imm = 0x125008
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 1200160
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $38, %ecx
jmp .LBB1_2
.LBB1_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $39, %ecx
jmp .LBB1_2
.LBB1_24:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $40, %ecx
jmp .LBB1_2
.LBB1_9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $50, %ecx
jmp .LBB1_2
.LBB1_25:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $59, %ecx
jmp .LBB1_2
.LBB1_18:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $82, %ecx
jmp .LBB1_2
.LBB1_20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $83, %ecx
jmp .LBB1_2
.LBB1_22:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $84, %ecx
.LBB1_2:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size Cuda_Main_Test1, .Lfunc_end1-Cuda_Main_Test1
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/ArefyevDenis/ArefyevDenis/master/cuda_sub_dir/cuda_one/cuda.hip"
.size .L.str, 121
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d%c "
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Start CPU add \n "
.size .L.str.2, 17
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Stop CPU add \n "
.size .L.str.3, 16
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%s in %s at line %d\n"
.size .L.str.4, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x1869f, PT ; /* 0x0001869f0600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_cmp_gt_i32 s15, 0x1869f
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a53e9_00000000-6_cuda.cudafe1.cpp"
.text
#APP
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s in %s at line %d\n"
#NO_APP
.text
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB2057:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _ZL11HandleError9cudaErrorPKci, .-_ZL11HandleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/ArefyevDenis/ArefyevDenis/master/cuda_sub_dir/cuda_one/cuda.cu"
.section .rodata.str1.1
.LC2:
.string "%d%c "
.LC3:
.string "Start CPU add \n "
.LC4:
.string "Stop CPU add \n "
.text
.globl Cuda_Main_Test1
.type Cuda_Main_Test1, @function
Cuda_Main_Test1:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
leaq -1196032(%rsp), %r11
.cfi_def_cfa 11, 1196056
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $4040, %rsp
.cfi_def_cfa_offset 1200096
movq %fs:40, %rax
movq %rax, 1200056(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $400000, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $36, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 8(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $37, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 16(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $38, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %eax
.L18:
movl %eax, 48(%rsp,%rax,4)
movl %eax, 400048(%rsp,%rax,4)
movl $0, 800048(%rsp,%rax,4)
addq $1, %rax
cmpq $100000, %rax
jne .L18
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $400000, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $48, %edx
leaq .LC1(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 400048(%rsp), %rsi
movl $1, %ecx
movl $400000, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $100000, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L19:
leaq 800048(%rsp), %rdi
movl $2, %ecx
movl $400000, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
movl $57, %edx
leaq .LC1(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L21:
movl %ebx, %edx
sarl $31, %edx
shrl $29, %edx
leal (%rdx,%rbx), %eax
andl $7, %eax
subl %edx, %eax
cmpl $7, %eax
movl $32, %ecx
movl $10, %eax
cmove %eax, %ecx
movl 800048(%rsp,%rbx,4), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $100000, %rbx
jne .L21
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L22:
movl 400048(%rsp,%rax), %edx
addl 48(%rsp,%rax), %edx
movl %edx, 800048(%rsp,%rax)
addq $4, %rax
cmpq $400000, %rax
jne .L22
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $80, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $81, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $82, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movq 1200056(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $1200072, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L19
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size Cuda_Main_Test1, .-Cuda_Main_Test1
.section .rodata.str1.1
.LC5:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl Cuda_Main_Test1 # -- Begin function Cuda_Main_Test1
.p2align 4, 0x90
.type Cuda_Main_Test1,@function
Cuda_Main_Test1: # @Cuda_Main_Test1
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1200136, %rsp # imm = 0x125008
.cfi_def_cfa_offset 1200160
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_ZL11HandleError10hipError_tPKci.exit
leaq 8(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_ZL11HandleError10hipError_tPKci.exit21
movq %rsp, %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
testl %eax, %eax
jne .LBB1_24
# %bb.6: # %_ZL11HandleError10hipError_tPKci.exit23.preheader
leaq 128(%rsp), %rdi
xorl %ebx, %ebx
movl $400000, %edx # imm = 0x61A80
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_7: # %_ZL11HandleError10hipError_tPKci.exit23
# =>This Inner Loop Header: Depth=1
movl %ebx, 800128(%rsp,%rbx,4)
movl %ebx, 400128(%rsp,%rbx,4)
incq %rbx
cmpq $100000, %rbx # imm = 0x186A0
jne .LBB1_7
# %bb.8:
movq 16(%rsp), %rdi
leaq 800128(%rsp), %rsi
movl $400000, %edx # imm = 0x61A80
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_9
# %bb.10: # %_ZL11HandleError10hipError_tPKci.exit25
movq 8(%rsp), %rdi
leaq 400128(%rsp), %rsi
movl $400000, %edx # imm = 0x61A80
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 99999(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_12
# %bb.11:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_12:
movq (%rsp), %rsi
leaq 128(%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_25
# %bb.13: # %_ZL11HandleError10hipError_tPKci.exit27.preheader
movl $10, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_14: # %_ZL11HandleError10hipError_tPKci.exit27
# =>This Inner Loop Header: Depth=1
movl 128(%rsp,%r14,4), %esi
movl %r14d, %eax
notl %eax
testb $7, %al
movl $32, %edx
cmovel %ebx, %edx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $100000, %r14 # imm = 0x186A0
jne .LBB1_14
# %bb.15:
xorl %ebx, %ebx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB1_16: # =>This Inner Loop Header: Depth=1
movl 400128(%rsp,%rbx,4), %eax
addl 800128(%rsp,%rbx,4), %eax
movl %eax, 128(%rsp,%rbx,4)
incq %rbx
cmpq $100000, %rbx # imm = 0x186A0
jne .LBB1_16
# %bb.17:
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_18
# %bb.19: # %_ZL11HandleError10hipError_tPKci.exit29
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_20
# %bb.21: # %_ZL11HandleError10hipError_tPKci.exit31
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_22
# %bb.23: # %_ZL11HandleError10hipError_tPKci.exit33
addq $1200136, %rsp # imm = 0x125008
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 1200160
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $38, %ecx
jmp .LBB1_2
.LBB1_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $39, %ecx
jmp .LBB1_2
.LBB1_24:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $40, %ecx
jmp .LBB1_2
.LBB1_9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $50, %ecx
jmp .LBB1_2
.LBB1_25:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $59, %ecx
jmp .LBB1_2
.LBB1_18:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $82, %ecx
jmp .LBB1_2
.LBB1_20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $83, %ecx
jmp .LBB1_2
.LBB1_22:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $84, %ecx
.LBB1_2:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size Cuda_Main_Test1, .Lfunc_end1-Cuda_Main_Test1
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/ArefyevDenis/ArefyevDenis/master/cuda_sub_dir/cuda_one/cuda.hip"
.size .L.str, 121
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d%c "
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Start CPU add \n "
.size .L.str.2, 17
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Stop CPU add \n "
.size .L.str.3, 16
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%s in %s at line %d\n"
.size .L.str.4, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <math.h>
#define CUDA_CALL(c) \
do { \
cudaError_t res = c; \
if (res != cudaSuccess) { \
fprintf(stderr, "error at line %d: %s \n", __LINE__, cudaGetErrorString(res)); \
exit(EXIT_FAILURE); \
} \
} while (0)
// Problem dimension
#define STENCIL_SIZE (16 * 1024 * 1024)
#define RADIUS (3)
#define NUM_CHANNELS (4)
#define BLOCK_SIZE (32)
// Given the pixel index and channel, return the position of the
// element in the 1D array.
static __device__ __host__ int getIndex(int index, int channel)
{
return index * NUM_CHANNELS + channel;
}
static __constant__ int weight[RADIUS * 2 + 1] = {
1, 2, 3, 4, 3, 2, 1
};
static __constant__ int denominator = 16;
__global__ void stencilKernel(unsigned char *in,
int numPixels,
unsigned char *out)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int radius, channel;
int outLocal[NUM_CHANNELS] = { 0 };
if (i < RADIUS) {
return;
}
if (i >= numPixels - RADIUS) {
return;
}
for (radius = -RADIUS; radius <= RADIUS; ++radius) {
for (channel = 0; channel < NUM_CHANNELS; ++channel) {
outLocal[channel] += (int)in[getIndex(i + radius, channel)] * weight[RADIUS + radius];
}
}
for (channel = 0; channel < NUM_CHANNELS; ++channel) {
out[getIndex(i, channel)] = (unsigned char)(outLocal[channel] / denominator);
}
}
static void stencilGpu(unsigned char *in,
int numPixels,
unsigned char *out)
{
unsigned char *inGPU;
unsigned char *outGPU;
size_t arraySize;
arraySize = numPixels * NUM_CHANNELS * sizeof(unsigned char);
CUDA_CALL(cudaMalloc(&inGPU, arraySize));
CUDA_CALL(cudaMalloc(&outGPU, arraySize));
CUDA_CALL(cudaMemcpy(inGPU, in, arraySize, cudaMemcpyHostToDevice));
stencilKernel<<<ceil((float)numPixels / BLOCK_SIZE), BLOCK_SIZE>>>(inGPU, numPixels, outGPU);
CUDA_CALL(cudaGetLastError());
CUDA_CALL(cudaDeviceSynchronize());
CUDA_CALL(cudaMemcpy(out, outGPU, arraySize, cudaMemcpyDeviceToHost));
CUDA_CALL(cudaFree(inGPU));
CUDA_CALL(cudaFree(outGPU));
}
int main()
{
unsigned char *in;
unsigned char *outGPU;
size_t arraySize = STENCIL_SIZE * NUM_CHANNELS * sizeof(unsigned char);
in = (unsigned char *)malloc(arraySize);
outGPU = (unsigned char *)malloc(arraySize);
if (in == NULL || outGPU == NULL) {
fprintf(stderr, "Allocation failed\n");
exit(EXIT_FAILURE);
}
stencilGpu(in, STENCIL_SIZE, outGPU);
free(in);
free(outGPU);
return 0;
} | code for sm_80
Function : _Z13stencilKernelPhiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR4, -0x3, URZ ; /* 0xfffffffd04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x000fc8000bf06270 */
/*0070*/ ISETP.LT.OR P0, PT, R6, 0x3, P0 ; /* 0x000000030600780c */
/* 0x000fda0000701670 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IMAD.SHL.U32 R6, R6, 0x4, RZ ; /* 0x0000000406067824 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00b0*/ IADD3 R0, R6, -0xc, RZ ; /* 0xfffffff406007810 */
/* 0x000fc80007ffe0ff */
/*00c0*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f1e0ff */
/*00d0*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f0eff */
/*00e0*/ LDG.E.U8 R13, [R2.64+0x4] ; /* 0x00000404020d7981 */
/* 0x000ea8000c1e1100 */
/*00f0*/ LDG.E.U8 R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x000ee8000c1e1100 */
/*0100*/ LDG.E.U8 R18, [R2.64+0x7] ; /* 0x0000070402127981 */
/* 0x000f28000c1e1100 */
/*0110*/ LDG.E.U8 R16, [R2.64+0x6] ; /* 0x0000060402107981 */
/* 0x000f68000c1e1100 */
/*0120*/ LDG.E.U8 R14, [R2.64+0x5] ; /* 0x00000504020e7981 */
/* 0x000f68000c1e1100 */
/*0130*/ LDG.E.U8 R9, [R2.64+0x2] ; /* 0x0000020402097981 */
/* 0x000f68000c1e1100 */
/*0140*/ LDG.E.U8 R28, [R2.64+0x1] ; /* 0x00000104021c7981 */
/* 0x000f68000c1e1100 */
/*0150*/ LDG.E.U8 R17, [R2.64+0x8] ; /* 0x0000080402117981 */
/* 0x000f68000c1e1100 */
/*0160*/ LDG.E.U8 R0, [R2.64+0x3] ; /* 0x0000030402007981 */
/* 0x000f68000c1e1100 */
/*0170*/ LDG.E.U8 R5, [R2.64+0x9] ; /* 0x0000090402057981 */
/* 0x000f62000c1e1100 */
/*0180*/ SHF.R.S32.HI R8, RZ, 0x1f, R6 ; /* 0x0000001fff087819 */
/* 0x000fc40000011406 */
/*0190*/ IADD3 R10, P0, R6, c[0x0][0x160], RZ ; /* 0x00005800060a7a10 */
/* 0x000fe20007f1e0ff */
/*01a0*/ LDG.E.U8 R4, [R2.64+0xa] ; /* 0x00000a0402047981 */
/* 0x000f66000c1e1100 */
/*01b0*/ IADD3.X R11, R8, c[0x0][0x164], RZ, P0, !PT ; /* 0x00005900080b7a10 */
/* 0x000fe200007fe4ff */
/*01c0*/ LDG.E.U8 R24, [R2.64+0x10] ; /* 0x0000100402187981 */
/* 0x000f68000c1e1100 */
/*01d0*/ LDG.E.U8 R26, [R10.64] ; /* 0x000000040a1a7981 */
/* 0x000168000c1e1100 */
/*01e0*/ LDG.E.U8 R23, [R10.64+0x1] ; /* 0x000001040a177981 */
/* 0x000168000c1e1100 */
/*01f0*/ LDG.E.U8 R7, [R2.64+0xb] ; /* 0x00000b0402077981 */
/* 0x000f68000c1e1100 */
/*0200*/ LDG.E.U8 R21, [R2.64+0x14] ; /* 0x0000140402157981 */
/* 0x000f68000c1e1100 */
/*0210*/ LDG.E.U8 R19, [R2.64+0x11] ; /* 0x0000110402137981 */
/* 0x000f68000c1e1100 */
/*0220*/ LDG.E.U8 R22, [R10.64+0x2] ; /* 0x000002040a167981 */
/* 0x000168000c1e1100 */
/*0230*/ LDG.E.U8 R20, [R10.64+0x3] ; /* 0x000003040a147981 */
/* 0x000168000c1e1100 */
/*0240*/ LDG.E.U8 R27, [R2.64+0x1b] ; /* 0x00001b04021b7981 */
/* 0x000368000c1e1100 */
/*0250*/ LDG.E.U8 R10, [R2.64+0x16] ; /* 0x00001604020a7981 */
/* 0x001368000c1e1100 */
/*0260*/ LDG.E.U8 R11, [R2.64+0x1a] ; /* 0x00001a04020b7981 */
/* 0x000362000c1e1100 */
/*0270*/ IMAD R13, R13, c[0x3][0x4], RZ ; /* 0x00c001000d0d7a24 */
/* 0x004fc800078e02ff */
/*0280*/ IMAD R12, R12, c[0x3][0x0], R13 ; /* 0x00c000000c0c7a24 */
/* 0x008fe400078e020d */
/*0290*/ IMAD R13, R18, c[0x3][0x4], RZ ; /* 0x00c00100120d7a24 */
/* 0x010fe400078e02ff */
/*02a0*/ LDG.E.U8 R18, [R2.64+0x18] ; /* 0x0000180402127981 */
/* 0x0002a2000c1e1100 */
/*02b0*/ IMAD R16, R16, c[0x3][0x4], RZ ; /* 0x00c0010010107a24 */
/* 0x020fe400078e02ff */
/*02c0*/ IMAD R15, R14, c[0x3][0x4], RZ ; /* 0x00c001000e0f7a24 */
/* 0x000fe400078e02ff */
/*02d0*/ LDG.E.U8 R14, [R2.64+0x15] ; /* 0x00001504020e7981 */
/* 0x0002e2000c1e1100 */
/*02e0*/ IMAD R9, R9, c[0x3][0x0], R16 ; /* 0x00c0000009097a24 */
/* 0x000fc600078e0210 */
/*02f0*/ LDG.E.U8 R16, [R2.64+0x12] ; /* 0x0000120402107981 */
/* 0x000322000c1e1100 */
/*0300*/ IMAD R28, R28, c[0x3][0x0], R15 ; /* 0x00c000001c1c7a24 */
/* 0x000fc600078e020f */
/*0310*/ LDG.E.U8 R15, [R2.64+0x13] ; /* 0x00001304020f7981 */
/* 0x000362000c1e1100 */
/*0320*/ IMAD R17, R17, c[0x3][0x8], R12 ; /* 0x00c0020011117a24 */
/* 0x000fc600078e020c */
/*0330*/ LDG.E.U8 R12, [R2.64+0x19] ; /* 0x00001904020c7981 */
/* 0x000362000c1e1100 */
/*0340*/ IMAD R0, R0, c[0x3][0x0], R13 ; /* 0x00c0000000007a24 */
/* 0x000fc600078e020d */
/*0350*/ LDG.E.U8 R13, [R2.64+0x17] ; /* 0x00001704020d7981 */
/* 0x000362000c1e1100 */
/*0360*/ IABS R25, c[0x3][0x1c] ; /* 0x00c0070000197a13 */
/* 0x000fc80000000000 */
/*0370*/ I2F.RP R29, R25 ; /* 0x00000019001d7306 */
/* 0x000e220000209400 */
/*0380*/ IMAD R28, R5, c[0x3][0x8], R28 ; /* 0x00c00200051c7a24 */
/* 0x000fce00078e021c */
/*0390*/ MUFU.RCP R29, R29 ; /* 0x0000001d001d7308 */
/* 0x001e240000001000 */
/*03a0*/ IADD3 R5, R29, 0xffffffe, RZ ; /* 0x0ffffffe1d057810 */
/* 0x001fcc0007ffe0ff */
/*03b0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e22000021f000 */
/*03c0*/ IMAD R17, R26, c[0x3][0xc], R17 ; /* 0x00c003001a117a24 */
/* 0x000fe400078e0211 */
/*03d0*/ IMAD R9, R4, c[0x3][0x8], R9 ; /* 0x00c0020004097a24 */
/* 0x000fe400078e0209 */
/*03e0*/ IMAD R24, R24, c[0x3][0x10], R17 ; /* 0x00c0040018187a24 */
/* 0x000fe400078e0211 */
/*03f0*/ IMAD R7, R7, c[0x3][0x8], R0 ; /* 0x00c0020007077a24 */
/* 0x000fe400078e0200 */
/*0400*/ IMAD R28, R23, c[0x3][0xc], R28 ; /* 0x00c00300171c7a24 */
/* 0x000fe400078e021c */
/*0410*/ IMAD R21, R21, c[0x3][0x14], R24 ; /* 0x00c0050015157a24 */
/* 0x000fe200078e0218 */
/*0420*/ IADD3 R4, RZ, -R5, RZ ; /* 0x80000005ff047210 */
/* 0x001fe20007ffe0ff */
/*0430*/ IMAD R19, R19, c[0x3][0x10], R28 ; /* 0x00c0040013137a24 */
/* 0x000fc800078e021c */
/*0440*/ IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0004 */
/*0450*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe400078e00ff */
/*0460*/ IMAD R3, R0, R25, RZ ; /* 0x0000001900037224 */
/* 0x002fe400078e02ff */
/*0470*/ IMAD R9, R22, c[0x3][0xc], R9 ; /* 0x00c0030016097a24 */
/* 0x000fe400078e0209 */
/*0480*/ IMAD R20, R20, c[0x3][0xc], R7 ; /* 0x00c0030014147a24 */
/* 0x000fe400078e0207 */
/*0490*/ IMAD.HI.U32 R4, R5, R3, R4 ; /* 0x0000000305047227 */
/* 0x000fc800078e0004 */
/*04a0*/ IMAD R18, R18, c[0x3][0x18], R21 ; /* 0x00c0060012127a24 */
/* 0x004fca00078e0215 */
/*04b0*/ IABS R2, R18 ; /* 0x0000001200027213 */
/* 0x000fe20000000000 */
/*04c0*/ IMAD R19, R14, c[0x3][0x14], R19 ; /* 0x00c005000e137a24 */
/* 0x008fe400078e0213 */
/*04d0*/ IMAD R9, R16, c[0x3][0x10], R9 ; /* 0x00c0040010097a24 */
/* 0x010fe400078e0209 */
/*04e0*/ IMAD R20, R15, c[0x3][0x10], R20 ; /* 0x00c004000f147a24 */
/* 0x020fe400078e0214 */
/*04f0*/ IMAD R12, R12, c[0x3][0x18], R19 ; /* 0x00c006000c0c7a24 */
/* 0x000fe400078e0213 */
/*0500*/ IMAD R10, R10, c[0x3][0x14], R9 ; /* 0x00c005000a0a7a24 */
/* 0x000fe400078e0209 */
/*0510*/ IMAD.HI.U32 R3, R4, R2, RZ ; /* 0x0000000204037227 */
/* 0x000fe200078e00ff */
/*0520*/ IABS R14, R12 ; /* 0x0000000c000e7213 */
/* 0x000fc60000000000 */
/*0530*/ IMAD R20, R13, c[0x3][0x14], R20 ; /* 0x00c005000d147a24 */
/* 0x000fe400078e0214 */
/*0540*/ IMAD R11, R11, c[0x3][0x18], R10 ; /* 0x00c006000b0b7a24 */
/* 0x000fe200078e020a */
/*0550*/ IADD3 R10, -R3, RZ, RZ ; /* 0x000000ff030a7210 */
/* 0x000fe20007ffe1ff */
/*0560*/ IMAD R27, R27, c[0x3][0x18], R20 ; /* 0x00c006001b1b7a24 */
/* 0x000fe400078e0214 */
/*0570*/ IMAD.HI.U32 R0, R4, R14, RZ ; /* 0x0000000e04007227 */
/* 0x000fe200078e00ff */
/*0580*/ IABS R16, R11 ; /* 0x0000000b00107213 */
/* 0x000fe40000000000 */
/*0590*/ IABS R20, R27 ; /* 0x0000001b00147213 */
/* 0x000fe20000000000 */
/*05a0*/ IMAD R10, R25, R10, R2 ; /* 0x0000000a190a7224 */
/* 0x000fc400078e0202 */
/*05b0*/ IMAD.MOV R5, RZ, RZ, -R0 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0a00 */
/*05c0*/ IMAD.HI.U32 R2, R4, R16, RZ ; /* 0x0000001004027227 */
/* 0x000fe200078e00ff */
/*05d0*/ ISETP.GT.U32.AND P2, PT, R25, R10, PT ; /* 0x0000000a1900720c */
/* 0x000fc60003f44070 */
/*05e0*/ IMAD.HI.U32 R4, R4, R20, RZ ; /* 0x0000001404047227 */
/* 0x000fc800078e00ff */
/*05f0*/ IMAD R14, R25, R5, R14 ; /* 0x00000005190e7224 */
/* 0x000fe200078e020e */
/*0600*/ IADD3 R9, -R4, RZ, RZ ; /* 0x000000ff04097210 */
/* 0x000fe20007ffe1ff */
/*0610*/ IMAD.MOV R7, RZ, RZ, -R2 ; /* 0x000000ffff077224 */
/* 0x000fc600078e0a02 */
/*0620*/ ISETP.GT.U32.AND P0, PT, R25.reuse, R14, PT ; /* 0x0000000e1900720c */
/* 0x040fe20003f04070 */
/*0630*/ IMAD R16, R25.reuse, R7, R16 ; /* 0x0000000719107224 */
/* 0x040fe400078e0210 */
/*0640*/ IMAD R20, R25.reuse, R9, R20 ; /* 0x0000000919147224 */
/* 0x040fe400078e0214 */
/*0650*/ @!P2 IMAD.IADD R10, R10, 0x1, -R25 ; /* 0x000000010a0aa824 */
/* 0x000fe200078e0a19 */
/*0660*/ ISETP.GT.U32.AND P5, PT, R25.reuse, R16, PT ; /* 0x000000101900720c */
/* 0x040fe40003fa4070 */
/*0670*/ ISETP.GT.U32.AND P1, PT, R25, R20, PT ; /* 0x000000141900720c */
/* 0x000fe40003f24070 */
/*0680*/ ISETP.GE.U32.AND P6, PT, R10, R25, PT ; /* 0x000000190a00720c */
/* 0x000fc60003fc6070 */
/*0690*/ @!P0 IMAD.IADD R14, R14, 0x1, -R25 ; /* 0x000000010e0e8824 */
/* 0x000fe200078e0a19 */
/*06a0*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fc80007ffe0ff */
/*06b0*/ ISETP.GE.U32.AND P4, PT, R14, R25.reuse, PT ; /* 0x000000190e00720c */
/* 0x080fe40003f86070 */
/*06c0*/ @!P5 IADD3 R16, R16, -R25.reuse, RZ ; /* 0x800000191010d210 */
/* 0x080fe20007ffe0ff */
/*06d0*/ @!P1 IMAD.IADD R20, R20, 0x1, -R25 ; /* 0x0000000114149824 */
/* 0x000fe200078e0a19 */
/*06e0*/ LOP3.LUT R18, R18, c[0x3][0x1c], RZ, 0x3c, !PT ; /* 0x00c0070012127a12 */
/* 0x000fe400078e3cff */
/*06f0*/ ISETP.GE.U32.AND P2, PT, R16, R25, PT ; /* 0x000000191000720c */
/* 0x000fe40003f46070 */
/*0700*/ @P6 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103036810 */
/* 0x000fe40007ffe0ff */
/*0710*/ IADD3 R6, P6, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a10 */
/* 0x000fc40007fde0ff */
/*0720*/ @!P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100008810 */
/* 0x000fe40007ffe0ff */
/*0730*/ LOP3.LUT R11, R11, c[0x3][0x1c], RZ, 0x3c, !PT ; /* 0x00c007000b0b7a12 */
/* 0x000fe400078e3cff */
/*0740*/ LOP3.LUT R12, R12, c[0x3][0x1c], RZ, 0x3c, !PT ; /* 0x00c007000c0c7a12 */
/* 0x000fe400078e3cff */
/*0750*/ ISETP.GE.U32.AND P0, PT, R20, R25, PT ; /* 0x000000191400720c */
/* 0x000fe40003f06070 */
/*0760*/ LOP3.LUT R27, R27, c[0x3][0x1c], RZ, 0x3c, !PT ; /* 0x00c007001b1b7a12 */
/* 0x000fe400078e3cff */
/*0770*/ @!P5 IADD3 R2, R2, 0x1, RZ ; /* 0x000000010202d810 */
/* 0x000fc40007ffe0ff */
/*0780*/ ISETP.GE.AND P3, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fe40003f66270 */
/*0790*/ IADD3.X R7, R8, c[0x0][0x174], RZ, P6, !PT ; /* 0x00005d0008077a10 */
/* 0x000fe400037fe4ff */
/*07a0*/ @P4 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100004810 */
/* 0x000fe40007ffe0ff */
/*07b0*/ ISETP.GE.AND P5, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003fa6270 */
/*07c0*/ ISETP.GE.AND P6, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003fc6270 */
/*07d0*/ ISETP.GE.AND P4, PT, R27, RZ, PT ; /* 0x000000ff1b00720c */
/* 0x000fc40003f86270 */
/*07e0*/ @!P1 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104049810 */
/* 0x000fe40007ffe0ff */
/*07f0*/ @P2 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102022810 */
/* 0x000fe40007ffe0ff */
/*0800*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fe20007ffe0ff */
/*0810*/ @!P3 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff03b224 */
/* 0x000fe200078e0a03 */
/*0820*/ ISETP.NE.AND P1, PT, RZ, c[0x3][0x1c], PT ; /* 0x00c00700ff007a0c */
/* 0x000fe20003f25270 */
/*0830*/ @!P5 IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff02d224 */
/* 0x000fe200078e0a02 */
/*0840*/ LOP3.LUT R8, RZ, c[0x3][0x1c], RZ, 0x33, !PT ; /* 0x00c00700ff087a12 */
/* 0x000fe400078e33ff */
/*0850*/ @!P6 IADD3 R0, -R0, RZ, RZ ; /* 0x000000ff0000e210 */
/* 0x000fc40007ffe1ff */
/*0860*/ @!P4 IADD3 R4, -R4, RZ, RZ ; /* 0x000000ff0404c210 */
/* 0x000fe40007ffe1ff */
/*0870*/ SEL R3, R8.reuse, R3, !P1 ; /* 0x0000000308037207 */
/* 0x040fe40004800000 */
/*0880*/ SEL R5, R8.reuse, R0, !P1 ; /* 0x0000000008057207 */
/* 0x040fe40004800000 */
/*0890*/ SEL R9, R8.reuse, R2, !P1 ; /* 0x0000000208097207 */
/* 0x040fe40004800000 */
/*08a0*/ SEL R11, R8, R4, !P1 ; /* 0x00000004080b7207 */
/* 0x000fe20004800000 */
/*08b0*/ STG.E.U8 [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x000fe8000c101104 */
/*08c0*/ STG.E.U8 [R6.64+0x1], R5 ; /* 0x0000010506007986 */
/* 0x000fe8000c101104 */
/*08d0*/ STG.E.U8 [R6.64+0x2], R9 ; /* 0x0000020906007986 */
/* 0x000fe8000c101104 */
/*08e0*/ STG.E.U8 [R6.64+0x3], R11 ; /* 0x0000030b06007986 */
/* 0x000fe2000c101104 */
/*08f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0900*/ BRA 0x900; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <math.h>
#define CUDA_CALL(c) \
do { \
cudaError_t res = c; \
if (res != cudaSuccess) { \
fprintf(stderr, "error at line %d: %s \n", __LINE__, cudaGetErrorString(res)); \
exit(EXIT_FAILURE); \
} \
} while (0)
// Problem dimension
#define STENCIL_SIZE (16 * 1024 * 1024)
#define RADIUS (3)
#define NUM_CHANNELS (4)
#define BLOCK_SIZE (32)
// Given the pixel index and channel, return the position of the
// element in the 1D array.
static __device__ __host__ int getIndex(int index, int channel)
{
return index * NUM_CHANNELS + channel;
}
static __constant__ int weight[RADIUS * 2 + 1] = {
1, 2, 3, 4, 3, 2, 1
};
static __constant__ int denominator = 16;
__global__ void stencilKernel(unsigned char *in,
int numPixels,
unsigned char *out)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int radius, channel;
int outLocal[NUM_CHANNELS] = { 0 };
if (i < RADIUS) {
return;
}
if (i >= numPixels - RADIUS) {
return;
}
for (radius = -RADIUS; radius <= RADIUS; ++radius) {
for (channel = 0; channel < NUM_CHANNELS; ++channel) {
outLocal[channel] += (int)in[getIndex(i + radius, channel)] * weight[RADIUS + radius];
}
}
for (channel = 0; channel < NUM_CHANNELS; ++channel) {
out[getIndex(i, channel)] = (unsigned char)(outLocal[channel] / denominator);
}
}
static void stencilGpu(unsigned char *in,
int numPixels,
unsigned char *out)
{
unsigned char *inGPU;
unsigned char *outGPU;
size_t arraySize;
arraySize = numPixels * NUM_CHANNELS * sizeof(unsigned char);
CUDA_CALL(cudaMalloc(&inGPU, arraySize));
CUDA_CALL(cudaMalloc(&outGPU, arraySize));
CUDA_CALL(cudaMemcpy(inGPU, in, arraySize, cudaMemcpyHostToDevice));
stencilKernel<<<ceil((float)numPixels / BLOCK_SIZE), BLOCK_SIZE>>>(inGPU, numPixels, outGPU);
CUDA_CALL(cudaGetLastError());
CUDA_CALL(cudaDeviceSynchronize());
CUDA_CALL(cudaMemcpy(out, outGPU, arraySize, cudaMemcpyDeviceToHost));
CUDA_CALL(cudaFree(inGPU));
CUDA_CALL(cudaFree(outGPU));
}
int main()
{
unsigned char *in;
unsigned char *outGPU;
size_t arraySize = STENCIL_SIZE * NUM_CHANNELS * sizeof(unsigned char);
in = (unsigned char *)malloc(arraySize);
outGPU = (unsigned char *)malloc(arraySize);
if (in == NULL || outGPU == NULL) {
fprintf(stderr, "Allocation failed\n");
exit(EXIT_FAILURE);
}
stencilGpu(in, STENCIL_SIZE, outGPU);
free(in);
free(outGPU);
return 0;
} | .file "tmpxft_000e6bd9_00000000-6_stencil0_orig.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z13stencilKernelPhiS_PhiS_
.type _Z36__device_stub__Z13stencilKernelPhiS_PhiS_, @function
_Z36__device_stub__Z13stencilKernelPhiS_PhiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13stencilKernelPhiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z36__device_stub__Z13stencilKernelPhiS_PhiS_, .-_Z36__device_stub__Z13stencilKernelPhiS_PhiS_
.globl _Z13stencilKernelPhiS_
.type _Z13stencilKernelPhiS_, @function
_Z13stencilKernelPhiS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13stencilKernelPhiS_PhiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13stencilKernelPhiS_, .-_Z13stencilKernelPhiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Allocation failed\n"
.LC1:
.string "error at line %d: %s \n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbx
movl $67108864, %edi
call malloc@PLT
testq %rbx, %rbx
je .L24
movq %rax, %rbp
testq %rax, %rax
je .L24
movq %rsp, %rdi
movl $67108864, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L26
leaq 8(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L27
movl $1, %ecx
movl $67108864, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L28
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $524288, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L17:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L30
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L31
movl $2, %ecx
movl $67108864, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L32
movq (%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L33
movq 8(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L34
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L26:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $69, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L27:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $70, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L28:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $72, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L29:
movq 8(%rsp), %rdx
movl $16777216, %esi
movq (%rsp), %rdi
call _Z36__device_stub__Z13stencilKernelPhiS_PhiS_
jmp .L17
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $75, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $76, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $78, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $80, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $81, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z13stencilKernelPhiS_"
.LC3:
.string "weight"
.LC4:
.string "denominator"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13stencilKernelPhiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $28, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6weight(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11denominator(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL11denominator
.comm _ZL11denominator,4,4
.local _ZL6weight
.comm _ZL6weight,28,16
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <math.h>
#define CUDA_CALL(c) \
do { \
cudaError_t res = c; \
if (res != cudaSuccess) { \
fprintf(stderr, "error at line %d: %s \n", __LINE__, cudaGetErrorString(res)); \
exit(EXIT_FAILURE); \
} \
} while (0)
// Problem dimension
#define STENCIL_SIZE (16 * 1024 * 1024)
#define RADIUS (3)
#define NUM_CHANNELS (4)
#define BLOCK_SIZE (32)
// Given the pixel index and channel, return the position of the
// element in the 1D array.
static __device__ __host__ int getIndex(int index, int channel)
{
return index * NUM_CHANNELS + channel;
}
static __constant__ int weight[RADIUS * 2 + 1] = {
1, 2, 3, 4, 3, 2, 1
};
static __constant__ int denominator = 16;
__global__ void stencilKernel(unsigned char *in,
int numPixels,
unsigned char *out)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int radius, channel;
int outLocal[NUM_CHANNELS] = { 0 };
if (i < RADIUS) {
return;
}
if (i >= numPixels - RADIUS) {
return;
}
for (radius = -RADIUS; radius <= RADIUS; ++radius) {
for (channel = 0; channel < NUM_CHANNELS; ++channel) {
outLocal[channel] += (int)in[getIndex(i + radius, channel)] * weight[RADIUS + radius];
}
}
for (channel = 0; channel < NUM_CHANNELS; ++channel) {
out[getIndex(i, channel)] = (unsigned char)(outLocal[channel] / denominator);
}
}
static void stencilGpu(unsigned char *in,
int numPixels,
unsigned char *out)
{
unsigned char *inGPU;
unsigned char *outGPU;
size_t arraySize;
arraySize = numPixels * NUM_CHANNELS * sizeof(unsigned char);
CUDA_CALL(cudaMalloc(&inGPU, arraySize));
CUDA_CALL(cudaMalloc(&outGPU, arraySize));
CUDA_CALL(cudaMemcpy(inGPU, in, arraySize, cudaMemcpyHostToDevice));
stencilKernel<<<ceil((float)numPixels / BLOCK_SIZE), BLOCK_SIZE>>>(inGPU, numPixels, outGPU);
CUDA_CALL(cudaGetLastError());
CUDA_CALL(cudaDeviceSynchronize());
CUDA_CALL(cudaMemcpy(out, outGPU, arraySize, cudaMemcpyDeviceToHost));
CUDA_CALL(cudaFree(inGPU));
CUDA_CALL(cudaFree(outGPU));
}
int main()
{
unsigned char *in;
unsigned char *outGPU;
size_t arraySize = STENCIL_SIZE * NUM_CHANNELS * sizeof(unsigned char);
in = (unsigned char *)malloc(arraySize);
outGPU = (unsigned char *)malloc(arraySize);
if (in == NULL || outGPU == NULL) {
fprintf(stderr, "Allocation failed\n");
exit(EXIT_FAILURE);
}
stencilGpu(in, STENCIL_SIZE, outGPU);
free(in);
free(outGPU);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#define CUDA_CALL(c) \
do { \
hipError_t res = c; \
if (res != hipSuccess) { \
fprintf(stderr, "error at line %d: %s \n", __LINE__, hipGetErrorString(res)); \
exit(EXIT_FAILURE); \
} \
} while (0)
// Problem dimension
#define STENCIL_SIZE (16 * 1024 * 1024)
#define RADIUS (3)
#define NUM_CHANNELS (4)
#define BLOCK_SIZE (32)
// Given the pixel index and channel, return the position of the
// element in the 1D array.
static __device__ __host__ int getIndex(int index, int channel)
{
return index * NUM_CHANNELS + channel;
}
static __constant__ int weight[RADIUS * 2 + 1] = {
1, 2, 3, 4, 3, 2, 1
};
static __constant__ int denominator = 16;
__global__ void stencilKernel(unsigned char *in,
int numPixels,
unsigned char *out)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int radius, channel;
int outLocal[NUM_CHANNELS] = { 0 };
if (i < RADIUS) {
return;
}
if (i >= numPixels - RADIUS) {
return;
}
for (radius = -RADIUS; radius <= RADIUS; ++radius) {
for (channel = 0; channel < NUM_CHANNELS; ++channel) {
outLocal[channel] += (int)in[getIndex(i + radius, channel)] * weight[RADIUS + radius];
}
}
for (channel = 0; channel < NUM_CHANNELS; ++channel) {
out[getIndex(i, channel)] = (unsigned char)(outLocal[channel] / denominator);
}
}
static void stencilGpu(unsigned char *in,
int numPixels,
unsigned char *out)
{
unsigned char *inGPU;
unsigned char *outGPU;
size_t arraySize;
arraySize = numPixels * NUM_CHANNELS * sizeof(unsigned char);
CUDA_CALL(hipMalloc(&inGPU, arraySize));
CUDA_CALL(hipMalloc(&outGPU, arraySize));
CUDA_CALL(hipMemcpy(inGPU, in, arraySize, hipMemcpyHostToDevice));
stencilKernel<<<ceil((float)numPixels / BLOCK_SIZE), BLOCK_SIZE>>>(inGPU, numPixels, outGPU);
CUDA_CALL(hipGetLastError());
CUDA_CALL(hipDeviceSynchronize());
CUDA_CALL(hipMemcpy(out, outGPU, arraySize, hipMemcpyDeviceToHost));
CUDA_CALL(hipFree(inGPU));
CUDA_CALL(hipFree(outGPU));
}
int main()
{
unsigned char *in;
unsigned char *outGPU;
size_t arraySize = STENCIL_SIZE * NUM_CHANNELS * sizeof(unsigned char);
in = (unsigned char *)malloc(arraySize);
outGPU = (unsigned char *)malloc(arraySize);
if (in == NULL || outGPU == NULL) {
fprintf(stderr, "Allocation failed\n");
exit(EXIT_FAILURE);
}
stencilGpu(in, STENCIL_SIZE, outGPU);
free(in);
free(outGPU);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#define CUDA_CALL(c) \
do { \
hipError_t res = c; \
if (res != hipSuccess) { \
fprintf(stderr, "error at line %d: %s \n", __LINE__, hipGetErrorString(res)); \
exit(EXIT_FAILURE); \
} \
} while (0)
// Problem dimension
#define STENCIL_SIZE (16 * 1024 * 1024)
#define RADIUS (3)
#define NUM_CHANNELS (4)
#define BLOCK_SIZE (32)
// Given the pixel index and channel, return the position of the
// element in the 1D array.
static __device__ __host__ int getIndex(int index, int channel)
{
return index * NUM_CHANNELS + channel;
}
static __constant__ int weight[RADIUS * 2 + 1] = {
1, 2, 3, 4, 3, 2, 1
};
static __constant__ int denominator = 16;
__global__ void stencilKernel(unsigned char *in,
int numPixels,
unsigned char *out)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int radius, channel;
int outLocal[NUM_CHANNELS] = { 0 };
if (i < RADIUS) {
return;
}
if (i >= numPixels - RADIUS) {
return;
}
for (radius = -RADIUS; radius <= RADIUS; ++radius) {
for (channel = 0; channel < NUM_CHANNELS; ++channel) {
outLocal[channel] += (int)in[getIndex(i + radius, channel)] * weight[RADIUS + radius];
}
}
for (channel = 0; channel < NUM_CHANNELS; ++channel) {
out[getIndex(i, channel)] = (unsigned char)(outLocal[channel] / denominator);
}
}
static void stencilGpu(unsigned char *in,
int numPixels,
unsigned char *out)
{
unsigned char *inGPU;
unsigned char *outGPU;
size_t arraySize;
arraySize = numPixels * NUM_CHANNELS * sizeof(unsigned char);
CUDA_CALL(hipMalloc(&inGPU, arraySize));
CUDA_CALL(hipMalloc(&outGPU, arraySize));
CUDA_CALL(hipMemcpy(inGPU, in, arraySize, hipMemcpyHostToDevice));
stencilKernel<<<ceil((float)numPixels / BLOCK_SIZE), BLOCK_SIZE>>>(inGPU, numPixels, outGPU);
CUDA_CALL(hipGetLastError());
CUDA_CALL(hipDeviceSynchronize());
CUDA_CALL(hipMemcpy(out, outGPU, arraySize, hipMemcpyDeviceToHost));
CUDA_CALL(hipFree(inGPU));
CUDA_CALL(hipFree(outGPU));
}
int main()
{
unsigned char *in;
unsigned char *outGPU;
size_t arraySize = STENCIL_SIZE * NUM_CHANNELS * sizeof(unsigned char);
in = (unsigned char *)malloc(arraySize);
outGPU = (unsigned char *)malloc(arraySize);
if (in == NULL || outGPU == NULL) {
fprintf(stderr, "Allocation failed\n");
exit(EXIT_FAILURE);
}
stencilGpu(in, STENCIL_SIZE, outGPU);
free(in);
free(outGPU);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13stencilKernelPhiS_
.globl _Z13stencilKernelPhiS_
.p2align 8
.type _Z13stencilKernelPhiS_,@function
_Z13stencilKernelPhiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x8
s_mov_b32 s6, -3
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_add_i32 s3, s3, -3
s_mul_i32 s15, s15, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, s15, v0
v_cmp_lt_i32_e32 vcc_lo, 2, v4
v_cmp_gt_i32_e64 s2, s3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_7
s_load_b64 s[8:9], s[0:1], 0x0
s_mov_b32 s12, 0
v_lshl_add_u32 v5, v4, 2, -12
s_mov_b32 s13, s12
s_mov_b32 s14, s12
s_mov_b32 s15, s12
v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
.LBB0_2:
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, _ZL6weight@rel32@lo+16
s_addc_u32 s3, s3, _ZL6weight@rel32@hi+24
s_ashr_i32 s7, s6, 31
v_ashrrev_i32_e32 v7, 31, v5
s_lshl_b64 s[4:5], s[6:7], 2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s8, v5
s_add_u32 s2, s4, s2
s_addc_u32 s3, s5, s3
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
s_load_b32 s5, s[2:3], 0x0
s_mov_b64 s[10:11], 0
.p2align 6
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v6, s10
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v7, vcc_lo
s_cmp_eq_u32 s10, 1
s_cselect_b32 vcc_lo, -1, 0
global_load_u8 v11, v[8:9], off
v_cndmask_b32_e32 v8, v0, v1, vcc_lo
s_cmp_eq_u32 s10, 2
s_cselect_b32 s2, -1, 0
s_cmp_eq_u32 s10, 3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v8, v8, v2, s2
s_cselect_b32 s3, -1, 0
s_cmp_eq_u32 s10, 0
s_cselect_b32 s4, -1, 0
v_cndmask_b32_e64 v8, v8, v3, s3
s_add_u32 s10, s10, 1
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s10, 4
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mad_u64_u32 v[9:10], null, s5, v11, v[8:9]
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v9, s3
v_cndmask_b32_e64 v2, v2, v9, s2
v_cndmask_b32_e32 v1, v1, v9, vcc_lo
v_cndmask_b32_e64 v0, v0, v9, s4
s_cbranch_scc1 .LBB0_3
v_add_nc_u32_e32 v5, 4, v5
s_add_i32 s6, s6, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s6, 4
s_cbranch_scc0 .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v4, 2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_mov_b64 s[0:1], 0
.p2align 6
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s0, 1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s0, 2
v_cndmask_b32_e32 v6, v0, v1, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s0, 3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v6, v6, v2, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
v_cndmask_b32_e32 v6, v6, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshrrev_b32_e32 v7, 28, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v8, v6, v7
v_add_co_u32 v6, vcc_lo, v4, s0
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
v_lshrrev_b32_e32 v8, 4, v8
s_add_u32 s0, s0, 1
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s0, 4
global_store_b8 v[6:7], v8, off
s_cbranch_scc1 .LBB0_6
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13stencilKernelPhiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13stencilKernelPhiS_, .Lfunc_end0-_Z13stencilKernelPhiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type _ZL6weight,@object
.section .rodata,"a",@progbits
.p2align 4, 0x0
_ZL6weight:
.long 1
.long 2
.long 3
.long 4
.long 3
.long 2
.long 1
.size _ZL6weight, 28
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13stencilKernelPhiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13stencilKernelPhiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#define CUDA_CALL(c) \
do { \
hipError_t res = c; \
if (res != hipSuccess) { \
fprintf(stderr, "error at line %d: %s \n", __LINE__, hipGetErrorString(res)); \
exit(EXIT_FAILURE); \
} \
} while (0)
// Problem dimension
#define STENCIL_SIZE (16 * 1024 * 1024)
#define RADIUS (3)
#define NUM_CHANNELS (4)
#define BLOCK_SIZE (32)
// Given the pixel index and channel, return the position of the
// element in the 1D array.
static __device__ __host__ int getIndex(int index, int channel)
{
return index * NUM_CHANNELS + channel;
}
static __constant__ int weight[RADIUS * 2 + 1] = {
1, 2, 3, 4, 3, 2, 1
};
static __constant__ int denominator = 16;
__global__ void stencilKernel(unsigned char *in,
int numPixels,
unsigned char *out)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int radius, channel;
int outLocal[NUM_CHANNELS] = { 0 };
if (i < RADIUS) {
return;
}
if (i >= numPixels - RADIUS) {
return;
}
for (radius = -RADIUS; radius <= RADIUS; ++radius) {
for (channel = 0; channel < NUM_CHANNELS; ++channel) {
outLocal[channel] += (int)in[getIndex(i + radius, channel)] * weight[RADIUS + radius];
}
}
for (channel = 0; channel < NUM_CHANNELS; ++channel) {
out[getIndex(i, channel)] = (unsigned char)(outLocal[channel] / denominator);
}
}
static void stencilGpu(unsigned char *in,
int numPixels,
unsigned char *out)
{
unsigned char *inGPU;
unsigned char *outGPU;
size_t arraySize;
arraySize = numPixels * NUM_CHANNELS * sizeof(unsigned char);
CUDA_CALL(hipMalloc(&inGPU, arraySize));
CUDA_CALL(hipMalloc(&outGPU, arraySize));
CUDA_CALL(hipMemcpy(inGPU, in, arraySize, hipMemcpyHostToDevice));
stencilKernel<<<ceil((float)numPixels / BLOCK_SIZE), BLOCK_SIZE>>>(inGPU, numPixels, outGPU);
CUDA_CALL(hipGetLastError());
CUDA_CALL(hipDeviceSynchronize());
CUDA_CALL(hipMemcpy(out, outGPU, arraySize, hipMemcpyDeviceToHost));
CUDA_CALL(hipFree(inGPU));
CUDA_CALL(hipFree(outGPU));
}
int main()
{
unsigned char *in;
unsigned char *outGPU;
size_t arraySize = STENCIL_SIZE * NUM_CHANNELS * sizeof(unsigned char);
in = (unsigned char *)malloc(arraySize);
outGPU = (unsigned char *)malloc(arraySize);
if (in == NULL || outGPU == NULL) {
fprintf(stderr, "Allocation failed\n");
exit(EXIT_FAILURE);
}
stencilGpu(in, STENCIL_SIZE, outGPU);
free(in);
free(outGPU);
return 0;
} | .text
.file "stencil0_orig.hip"
.globl _Z28__device_stub__stencilKernelPhiS_ # -- Begin function _Z28__device_stub__stencilKernelPhiS_
.p2align 4, 0x90
.type _Z28__device_stub__stencilKernelPhiS_,@function
_Z28__device_stub__stencilKernelPhiS_: # @_Z28__device_stub__stencilKernelPhiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13stencilKernelPhiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__stencilKernelPhiS_, .Lfunc_end0-_Z28__device_stub__stencilKernelPhiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %rbx
movl $67108864, %edi # imm = 0x4000000
callq malloc
testq %rbx, %rbx
je .LBB1_22
# %bb.1:
movq %rax, %r14
testq %rax, %rax
je .LBB1_22
# %bb.2:
leaq 16(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
testl %eax, %eax
jne .LBB1_3
# %bb.5:
leaq 8(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.7:
movq 16(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_8
# %bb.9:
movabsq $4294967328, %rdx # imm = 0x100000020
leaq 524256(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movl $16777216, 28(%rsp) # imm = 0x1000000
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13stencilKernelPhiS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_11:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_12
# %bb.13:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_14
# %bb.15:
movq 8(%rsp), %rsi
movl $67108864, %edx # imm = 0x4000000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_16
# %bb.17:
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_18
# %bb.19:
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_20
# %bb.21: # %_ZL10stencilGpuPhiS_.exit
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_22:
.cfi_def_cfa_offset 144
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $18, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB1_3:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movq %rbx, %rdi
movl $71, %edx
jmp .LBB1_4
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movq %rbx, %rdi
movl $72, %edx
jmp .LBB1_4
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movq %rbx, %rdi
movl $74, %edx
jmp .LBB1_4
.LBB1_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movq %rbx, %rdi
movl $77, %edx
jmp .LBB1_4
.LBB1_14:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movq %rbx, %rdi
movl $78, %edx
jmp .LBB1_4
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movq %rbx, %rdi
movl $80, %edx
jmp .LBB1_4
.LBB1_18:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movq %rbx, %rdi
movl $82, %edx
jmp .LBB1_4
.LBB1_20:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movq %rbx, %rdi
movl $83, %edx
.LBB1_4:
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13stencilKernelPhiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13stencilKernelPhiS_,@object # @_Z13stencilKernelPhiS_
.section .rodata,"a",@progbits
.globl _Z13stencilKernelPhiS_
.p2align 3, 0x0
_Z13stencilKernelPhiS_:
.quad _Z28__device_stub__stencilKernelPhiS_
.size _Z13stencilKernelPhiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Allocation failed\n"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "error at line %d: %s \n"
.size .L.str.1, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13stencilKernelPhiS_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__stencilKernelPhiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13stencilKernelPhiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13stencilKernelPhiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR4, -0x3, URZ ; /* 0xfffffffd04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x000fc8000bf06270 */
/*0070*/ ISETP.LT.OR P0, PT, R6, 0x3, P0 ; /* 0x000000030600780c */
/* 0x000fda0000701670 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IMAD.SHL.U32 R6, R6, 0x4, RZ ; /* 0x0000000406067824 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00b0*/ IADD3 R0, R6, -0xc, RZ ; /* 0xfffffff406007810 */
/* 0x000fc80007ffe0ff */
/*00c0*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f1e0ff */
/*00d0*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f0eff */
/*00e0*/ LDG.E.U8 R13, [R2.64+0x4] ; /* 0x00000404020d7981 */
/* 0x000ea8000c1e1100 */
/*00f0*/ LDG.E.U8 R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x000ee8000c1e1100 */
/*0100*/ LDG.E.U8 R18, [R2.64+0x7] ; /* 0x0000070402127981 */
/* 0x000f28000c1e1100 */
/*0110*/ LDG.E.U8 R16, [R2.64+0x6] ; /* 0x0000060402107981 */
/* 0x000f68000c1e1100 */
/*0120*/ LDG.E.U8 R14, [R2.64+0x5] ; /* 0x00000504020e7981 */
/* 0x000f68000c1e1100 */
/*0130*/ LDG.E.U8 R9, [R2.64+0x2] ; /* 0x0000020402097981 */
/* 0x000f68000c1e1100 */
/*0140*/ LDG.E.U8 R28, [R2.64+0x1] ; /* 0x00000104021c7981 */
/* 0x000f68000c1e1100 */
/*0150*/ LDG.E.U8 R17, [R2.64+0x8] ; /* 0x0000080402117981 */
/* 0x000f68000c1e1100 */
/*0160*/ LDG.E.U8 R0, [R2.64+0x3] ; /* 0x0000030402007981 */
/* 0x000f68000c1e1100 */
/*0170*/ LDG.E.U8 R5, [R2.64+0x9] ; /* 0x0000090402057981 */
/* 0x000f62000c1e1100 */
/*0180*/ SHF.R.S32.HI R8, RZ, 0x1f, R6 ; /* 0x0000001fff087819 */
/* 0x000fc40000011406 */
/*0190*/ IADD3 R10, P0, R6, c[0x0][0x160], RZ ; /* 0x00005800060a7a10 */
/* 0x000fe20007f1e0ff */
/*01a0*/ LDG.E.U8 R4, [R2.64+0xa] ; /* 0x00000a0402047981 */
/* 0x000f66000c1e1100 */
/*01b0*/ IADD3.X R11, R8, c[0x0][0x164], RZ, P0, !PT ; /* 0x00005900080b7a10 */
/* 0x000fe200007fe4ff */
/*01c0*/ LDG.E.U8 R24, [R2.64+0x10] ; /* 0x0000100402187981 */
/* 0x000f68000c1e1100 */
/*01d0*/ LDG.E.U8 R26, [R10.64] ; /* 0x000000040a1a7981 */
/* 0x000168000c1e1100 */
/*01e0*/ LDG.E.U8 R23, [R10.64+0x1] ; /* 0x000001040a177981 */
/* 0x000168000c1e1100 */
/*01f0*/ LDG.E.U8 R7, [R2.64+0xb] ; /* 0x00000b0402077981 */
/* 0x000f68000c1e1100 */
/*0200*/ LDG.E.U8 R21, [R2.64+0x14] ; /* 0x0000140402157981 */
/* 0x000f68000c1e1100 */
/*0210*/ LDG.E.U8 R19, [R2.64+0x11] ; /* 0x0000110402137981 */
/* 0x000f68000c1e1100 */
/*0220*/ LDG.E.U8 R22, [R10.64+0x2] ; /* 0x000002040a167981 */
/* 0x000168000c1e1100 */
/*0230*/ LDG.E.U8 R20, [R10.64+0x3] ; /* 0x000003040a147981 */
/* 0x000168000c1e1100 */
/*0240*/ LDG.E.U8 R27, [R2.64+0x1b] ; /* 0x00001b04021b7981 */
/* 0x000368000c1e1100 */
/*0250*/ LDG.E.U8 R10, [R2.64+0x16] ; /* 0x00001604020a7981 */
/* 0x001368000c1e1100 */
/*0260*/ LDG.E.U8 R11, [R2.64+0x1a] ; /* 0x00001a04020b7981 */
/* 0x000362000c1e1100 */
/*0270*/ IMAD R13, R13, c[0x3][0x4], RZ ; /* 0x00c001000d0d7a24 */
/* 0x004fc800078e02ff */
/*0280*/ IMAD R12, R12, c[0x3][0x0], R13 ; /* 0x00c000000c0c7a24 */
/* 0x008fe400078e020d */
/*0290*/ IMAD R13, R18, c[0x3][0x4], RZ ; /* 0x00c00100120d7a24 */
/* 0x010fe400078e02ff */
/*02a0*/ LDG.E.U8 R18, [R2.64+0x18] ; /* 0x0000180402127981 */
/* 0x0002a2000c1e1100 */
/*02b0*/ IMAD R16, R16, c[0x3][0x4], RZ ; /* 0x00c0010010107a24 */
/* 0x020fe400078e02ff */
/*02c0*/ IMAD R15, R14, c[0x3][0x4], RZ ; /* 0x00c001000e0f7a24 */
/* 0x000fe400078e02ff */
/*02d0*/ LDG.E.U8 R14, [R2.64+0x15] ; /* 0x00001504020e7981 */
/* 0x0002e2000c1e1100 */
/*02e0*/ IMAD R9, R9, c[0x3][0x0], R16 ; /* 0x00c0000009097a24 */
/* 0x000fc600078e0210 */
/*02f0*/ LDG.E.U8 R16, [R2.64+0x12] ; /* 0x0000120402107981 */
/* 0x000322000c1e1100 */
/*0300*/ IMAD R28, R28, c[0x3][0x0], R15 ; /* 0x00c000001c1c7a24 */
/* 0x000fc600078e020f */
/*0310*/ LDG.E.U8 R15, [R2.64+0x13] ; /* 0x00001304020f7981 */
/* 0x000362000c1e1100 */
/*0320*/ IMAD R17, R17, c[0x3][0x8], R12 ; /* 0x00c0020011117a24 */
/* 0x000fc600078e020c */
/*0330*/ LDG.E.U8 R12, [R2.64+0x19] ; /* 0x00001904020c7981 */
/* 0x000362000c1e1100 */
/*0340*/ IMAD R0, R0, c[0x3][0x0], R13 ; /* 0x00c0000000007a24 */
/* 0x000fc600078e020d */
/*0350*/ LDG.E.U8 R13, [R2.64+0x17] ; /* 0x00001704020d7981 */
/* 0x000362000c1e1100 */
/*0360*/ IABS R25, c[0x3][0x1c] ; /* 0x00c0070000197a13 */
/* 0x000fc80000000000 */
/*0370*/ I2F.RP R29, R25 ; /* 0x00000019001d7306 */
/* 0x000e220000209400 */
/*0380*/ IMAD R28, R5, c[0x3][0x8], R28 ; /* 0x00c00200051c7a24 */
/* 0x000fce00078e021c */
/*0390*/ MUFU.RCP R29, R29 ; /* 0x0000001d001d7308 */
/* 0x001e240000001000 */
/*03a0*/ IADD3 R5, R29, 0xffffffe, RZ ; /* 0x0ffffffe1d057810 */
/* 0x001fcc0007ffe0ff */
/*03b0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e22000021f000 */
/*03c0*/ IMAD R17, R26, c[0x3][0xc], R17 ; /* 0x00c003001a117a24 */
/* 0x000fe400078e0211 */
/*03d0*/ IMAD R9, R4, c[0x3][0x8], R9 ; /* 0x00c0020004097a24 */
/* 0x000fe400078e0209 */
/*03e0*/ IMAD R24, R24, c[0x3][0x10], R17 ; /* 0x00c0040018187a24 */
/* 0x000fe400078e0211 */
/*03f0*/ IMAD R7, R7, c[0x3][0x8], R0 ; /* 0x00c0020007077a24 */
/* 0x000fe400078e0200 */
/*0400*/ IMAD R28, R23, c[0x3][0xc], R28 ; /* 0x00c00300171c7a24 */
/* 0x000fe400078e021c */
/*0410*/ IMAD R21, R21, c[0x3][0x14], R24 ; /* 0x00c0050015157a24 */
/* 0x000fe200078e0218 */
/*0420*/ IADD3 R4, RZ, -R5, RZ ; /* 0x80000005ff047210 */
/* 0x001fe20007ffe0ff */
/*0430*/ IMAD R19, R19, c[0x3][0x10], R28 ; /* 0x00c0040013137a24 */
/* 0x000fc800078e021c */
/*0440*/ IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0004 */
/*0450*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe400078e00ff */
/*0460*/ IMAD R3, R0, R25, RZ ; /* 0x0000001900037224 */
/* 0x002fe400078e02ff */
/*0470*/ IMAD R9, R22, c[0x3][0xc], R9 ; /* 0x00c0030016097a24 */
/* 0x000fe400078e0209 */
/*0480*/ IMAD R20, R20, c[0x3][0xc], R7 ; /* 0x00c0030014147a24 */
/* 0x000fe400078e0207 */
/*0490*/ IMAD.HI.U32 R4, R5, R3, R4 ; /* 0x0000000305047227 */
/* 0x000fc800078e0004 */
/*04a0*/ IMAD R18, R18, c[0x3][0x18], R21 ; /* 0x00c0060012127a24 */
/* 0x004fca00078e0215 */
/*04b0*/ IABS R2, R18 ; /* 0x0000001200027213 */
/* 0x000fe20000000000 */
/*04c0*/ IMAD R19, R14, c[0x3][0x14], R19 ; /* 0x00c005000e137a24 */
/* 0x008fe400078e0213 */
/*04d0*/ IMAD R9, R16, c[0x3][0x10], R9 ; /* 0x00c0040010097a24 */
/* 0x010fe400078e0209 */
/*04e0*/ IMAD R20, R15, c[0x3][0x10], R20 ; /* 0x00c004000f147a24 */
/* 0x020fe400078e0214 */
/*04f0*/ IMAD R12, R12, c[0x3][0x18], R19 ; /* 0x00c006000c0c7a24 */
/* 0x000fe400078e0213 */
/*0500*/ IMAD R10, R10, c[0x3][0x14], R9 ; /* 0x00c005000a0a7a24 */
/* 0x000fe400078e0209 */
/*0510*/ IMAD.HI.U32 R3, R4, R2, RZ ; /* 0x0000000204037227 */
/* 0x000fe200078e00ff */
/*0520*/ IABS R14, R12 ; /* 0x0000000c000e7213 */
/* 0x000fc60000000000 */
/*0530*/ IMAD R20, R13, c[0x3][0x14], R20 ; /* 0x00c005000d147a24 */
/* 0x000fe400078e0214 */
/*0540*/ IMAD R11, R11, c[0x3][0x18], R10 ; /* 0x00c006000b0b7a24 */
/* 0x000fe200078e020a */
/*0550*/ IADD3 R10, -R3, RZ, RZ ; /* 0x000000ff030a7210 */
/* 0x000fe20007ffe1ff */
/*0560*/ IMAD R27, R27, c[0x3][0x18], R20 ; /* 0x00c006001b1b7a24 */
/* 0x000fe400078e0214 */
/*0570*/ IMAD.HI.U32 R0, R4, R14, RZ ; /* 0x0000000e04007227 */
/* 0x000fe200078e00ff */
/*0580*/ IABS R16, R11 ; /* 0x0000000b00107213 */
/* 0x000fe40000000000 */
/*0590*/ IABS R20, R27 ; /* 0x0000001b00147213 */
/* 0x000fe20000000000 */
/*05a0*/ IMAD R10, R25, R10, R2 ; /* 0x0000000a190a7224 */
/* 0x000fc400078e0202 */
/*05b0*/ IMAD.MOV R5, RZ, RZ, -R0 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0a00 */
/*05c0*/ IMAD.HI.U32 R2, R4, R16, RZ ; /* 0x0000001004027227 */
/* 0x000fe200078e00ff */
/*05d0*/ ISETP.GT.U32.AND P2, PT, R25, R10, PT ; /* 0x0000000a1900720c */
/* 0x000fc60003f44070 */
/*05e0*/ IMAD.HI.U32 R4, R4, R20, RZ ; /* 0x0000001404047227 */
/* 0x000fc800078e00ff */
/*05f0*/ IMAD R14, R25, R5, R14 ; /* 0x00000005190e7224 */
/* 0x000fe200078e020e */
/*0600*/ IADD3 R9, -R4, RZ, RZ ; /* 0x000000ff04097210 */
/* 0x000fe20007ffe1ff */
/*0610*/ IMAD.MOV R7, RZ, RZ, -R2 ; /* 0x000000ffff077224 */
/* 0x000fc600078e0a02 */
/*0620*/ ISETP.GT.U32.AND P0, PT, R25.reuse, R14, PT ; /* 0x0000000e1900720c */
/* 0x040fe20003f04070 */
/*0630*/ IMAD R16, R25.reuse, R7, R16 ; /* 0x0000000719107224 */
/* 0x040fe400078e0210 */
/*0640*/ IMAD R20, R25.reuse, R9, R20 ; /* 0x0000000919147224 */
/* 0x040fe400078e0214 */
/*0650*/ @!P2 IMAD.IADD R10, R10, 0x1, -R25 ; /* 0x000000010a0aa824 */
/* 0x000fe200078e0a19 */
/*0660*/ ISETP.GT.U32.AND P5, PT, R25.reuse, R16, PT ; /* 0x000000101900720c */
/* 0x040fe40003fa4070 */
/*0670*/ ISETP.GT.U32.AND P1, PT, R25, R20, PT ; /* 0x000000141900720c */
/* 0x000fe40003f24070 */
/*0680*/ ISETP.GE.U32.AND P6, PT, R10, R25, PT ; /* 0x000000190a00720c */
/* 0x000fc60003fc6070 */
/*0690*/ @!P0 IMAD.IADD R14, R14, 0x1, -R25 ; /* 0x000000010e0e8824 */
/* 0x000fe200078e0a19 */
/*06a0*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fc80007ffe0ff */
/*06b0*/ ISETP.GE.U32.AND P4, PT, R14, R25.reuse, PT ; /* 0x000000190e00720c */
/* 0x080fe40003f86070 */
/*06c0*/ @!P5 IADD3 R16, R16, -R25.reuse, RZ ; /* 0x800000191010d210 */
/* 0x080fe20007ffe0ff */
/*06d0*/ @!P1 IMAD.IADD R20, R20, 0x1, -R25 ; /* 0x0000000114149824 */
/* 0x000fe200078e0a19 */
/*06e0*/ LOP3.LUT R18, R18, c[0x3][0x1c], RZ, 0x3c, !PT ; /* 0x00c0070012127a12 */
/* 0x000fe400078e3cff */
/*06f0*/ ISETP.GE.U32.AND P2, PT, R16, R25, PT ; /* 0x000000191000720c */
/* 0x000fe40003f46070 */
/*0700*/ @P6 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103036810 */
/* 0x000fe40007ffe0ff */
/*0710*/ IADD3 R6, P6, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a10 */
/* 0x000fc40007fde0ff */
/*0720*/ @!P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100008810 */
/* 0x000fe40007ffe0ff */
/*0730*/ LOP3.LUT R11, R11, c[0x3][0x1c], RZ, 0x3c, !PT ; /* 0x00c007000b0b7a12 */
/* 0x000fe400078e3cff */
/*0740*/ LOP3.LUT R12, R12, c[0x3][0x1c], RZ, 0x3c, !PT ; /* 0x00c007000c0c7a12 */
/* 0x000fe400078e3cff */
/*0750*/ ISETP.GE.U32.AND P0, PT, R20, R25, PT ; /* 0x000000191400720c */
/* 0x000fe40003f06070 */
/*0760*/ LOP3.LUT R27, R27, c[0x3][0x1c], RZ, 0x3c, !PT ; /* 0x00c007001b1b7a12 */
/* 0x000fe400078e3cff */
/*0770*/ @!P5 IADD3 R2, R2, 0x1, RZ ; /* 0x000000010202d810 */
/* 0x000fc40007ffe0ff */
/*0780*/ ISETP.GE.AND P3, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fe40003f66270 */
/*0790*/ IADD3.X R7, R8, c[0x0][0x174], RZ, P6, !PT ; /* 0x00005d0008077a10 */
/* 0x000fe400037fe4ff */
/*07a0*/ @P4 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100004810 */
/* 0x000fe40007ffe0ff */
/*07b0*/ ISETP.GE.AND P5, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003fa6270 */
/*07c0*/ ISETP.GE.AND P6, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003fc6270 */
/*07d0*/ ISETP.GE.AND P4, PT, R27, RZ, PT ; /* 0x000000ff1b00720c */
/* 0x000fc40003f86270 */
/*07e0*/ @!P1 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104049810 */
/* 0x000fe40007ffe0ff */
/*07f0*/ @P2 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102022810 */
/* 0x000fe40007ffe0ff */
/*0800*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fe20007ffe0ff */
/*0810*/ @!P3 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff03b224 */
/* 0x000fe200078e0a03 */
/*0820*/ ISETP.NE.AND P1, PT, RZ, c[0x3][0x1c], PT ; /* 0x00c00700ff007a0c */
/* 0x000fe20003f25270 */
/*0830*/ @!P5 IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff02d224 */
/* 0x000fe200078e0a02 */
/*0840*/ LOP3.LUT R8, RZ, c[0x3][0x1c], RZ, 0x33, !PT ; /* 0x00c00700ff087a12 */
/* 0x000fe400078e33ff */
/*0850*/ @!P6 IADD3 R0, -R0, RZ, RZ ; /* 0x000000ff0000e210 */
/* 0x000fc40007ffe1ff */
/*0860*/ @!P4 IADD3 R4, -R4, RZ, RZ ; /* 0x000000ff0404c210 */
/* 0x000fe40007ffe1ff */
/*0870*/ SEL R3, R8.reuse, R3, !P1 ; /* 0x0000000308037207 */
/* 0x040fe40004800000 */
/*0880*/ SEL R5, R8.reuse, R0, !P1 ; /* 0x0000000008057207 */
/* 0x040fe40004800000 */
/*0890*/ SEL R9, R8.reuse, R2, !P1 ; /* 0x0000000208097207 */
/* 0x040fe40004800000 */
/*08a0*/ SEL R11, R8, R4, !P1 ; /* 0x00000004080b7207 */
/* 0x000fe20004800000 */
/*08b0*/ STG.E.U8 [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x000fe8000c101104 */
/*08c0*/ STG.E.U8 [R6.64+0x1], R5 ; /* 0x0000010506007986 */
/* 0x000fe8000c101104 */
/*08d0*/ STG.E.U8 [R6.64+0x2], R9 ; /* 0x0000020906007986 */
/* 0x000fe8000c101104 */
/*08e0*/ STG.E.U8 [R6.64+0x3], R11 ; /* 0x0000030b06007986 */
/* 0x000fe2000c101104 */
/*08f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0900*/ BRA 0x900; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13stencilKernelPhiS_
.globl _Z13stencilKernelPhiS_
.p2align 8
.type _Z13stencilKernelPhiS_,@function
_Z13stencilKernelPhiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x8
s_mov_b32 s6, -3
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_add_i32 s3, s3, -3
s_mul_i32 s15, s15, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, s15, v0
v_cmp_lt_i32_e32 vcc_lo, 2, v4
v_cmp_gt_i32_e64 s2, s3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_7
s_load_b64 s[8:9], s[0:1], 0x0
s_mov_b32 s12, 0
v_lshl_add_u32 v5, v4, 2, -12
s_mov_b32 s13, s12
s_mov_b32 s14, s12
s_mov_b32 s15, s12
v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
.LBB0_2:
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, _ZL6weight@rel32@lo+16
s_addc_u32 s3, s3, _ZL6weight@rel32@hi+24
s_ashr_i32 s7, s6, 31
v_ashrrev_i32_e32 v7, 31, v5
s_lshl_b64 s[4:5], s[6:7], 2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s8, v5
s_add_u32 s2, s4, s2
s_addc_u32 s3, s5, s3
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
s_load_b32 s5, s[2:3], 0x0
s_mov_b64 s[10:11], 0
.p2align 6
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v6, s10
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v7, vcc_lo
s_cmp_eq_u32 s10, 1
s_cselect_b32 vcc_lo, -1, 0
global_load_u8 v11, v[8:9], off
v_cndmask_b32_e32 v8, v0, v1, vcc_lo
s_cmp_eq_u32 s10, 2
s_cselect_b32 s2, -1, 0
s_cmp_eq_u32 s10, 3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v8, v8, v2, s2
s_cselect_b32 s3, -1, 0
s_cmp_eq_u32 s10, 0
s_cselect_b32 s4, -1, 0
v_cndmask_b32_e64 v8, v8, v3, s3
s_add_u32 s10, s10, 1
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s10, 4
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mad_u64_u32 v[9:10], null, s5, v11, v[8:9]
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v9, s3
v_cndmask_b32_e64 v2, v2, v9, s2
v_cndmask_b32_e32 v1, v1, v9, vcc_lo
v_cndmask_b32_e64 v0, v0, v9, s4
s_cbranch_scc1 .LBB0_3
v_add_nc_u32_e32 v5, 4, v5
s_add_i32 s6, s6, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s6, 4
s_cbranch_scc0 .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v4, 2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_mov_b64 s[0:1], 0
.p2align 6
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s0, 1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s0, 2
v_cndmask_b32_e32 v6, v0, v1, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s0, 3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v6, v6, v2, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
v_cndmask_b32_e32 v6, v6, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshrrev_b32_e32 v7, 28, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v8, v6, v7
v_add_co_u32 v6, vcc_lo, v4, s0
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
v_lshrrev_b32_e32 v8, 4, v8
s_add_u32 s0, s0, 1
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s0, 4
global_store_b8 v[6:7], v8, off
s_cbranch_scc1 .LBB0_6
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13stencilKernelPhiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13stencilKernelPhiS_, .Lfunc_end0-_Z13stencilKernelPhiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type _ZL6weight,@object
.section .rodata,"a",@progbits
.p2align 4, 0x0
_ZL6weight:
.long 1
.long 2
.long 3
.long 4
.long 3
.long 2
.long 1
.size _ZL6weight, 28
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13stencilKernelPhiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13stencilKernelPhiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e6bd9_00000000-6_stencil0_orig.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z13stencilKernelPhiS_PhiS_
.type _Z36__device_stub__Z13stencilKernelPhiS_PhiS_, @function
_Z36__device_stub__Z13stencilKernelPhiS_PhiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13stencilKernelPhiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z36__device_stub__Z13stencilKernelPhiS_PhiS_, .-_Z36__device_stub__Z13stencilKernelPhiS_PhiS_
.globl _Z13stencilKernelPhiS_
.type _Z13stencilKernelPhiS_, @function
_Z13stencilKernelPhiS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13stencilKernelPhiS_PhiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13stencilKernelPhiS_, .-_Z13stencilKernelPhiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Allocation failed\n"
.LC1:
.string "error at line %d: %s \n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbx
movl $67108864, %edi
call malloc@PLT
testq %rbx, %rbx
je .L24
movq %rax, %rbp
testq %rax, %rax
je .L24
movq %rsp, %rdi
movl $67108864, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L26
leaq 8(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L27
movl $1, %ecx
movl $67108864, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L28
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $524288, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L17:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L30
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L31
movl $2, %ecx
movl $67108864, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L32
movq (%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L33
movq 8(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L34
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L26:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $69, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L27:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $70, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L28:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $72, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L29:
movq 8(%rsp), %rdx
movl $16777216, %esi
movq (%rsp), %rdi
call _Z36__device_stub__Z13stencilKernelPhiS_PhiS_
jmp .L17
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $75, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $76, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $78, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $80, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $81, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z13stencilKernelPhiS_"
.LC3:
.string "weight"
.LC4:
.string "denominator"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13stencilKernelPhiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $28, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6weight(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11denominator(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL11denominator
.comm _ZL11denominator,4,4
.local _ZL6weight
.comm _ZL6weight,28,16
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "stencil0_orig.hip"
.globl _Z28__device_stub__stencilKernelPhiS_ # -- Begin function _Z28__device_stub__stencilKernelPhiS_
.p2align 4, 0x90
.type _Z28__device_stub__stencilKernelPhiS_,@function
_Z28__device_stub__stencilKernelPhiS_: # @_Z28__device_stub__stencilKernelPhiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13stencilKernelPhiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__stencilKernelPhiS_, .Lfunc_end0-_Z28__device_stub__stencilKernelPhiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %rbx
movl $67108864, %edi # imm = 0x4000000
callq malloc
testq %rbx, %rbx
je .LBB1_22
# %bb.1:
movq %rax, %r14
testq %rax, %rax
je .LBB1_22
# %bb.2:
leaq 16(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
testl %eax, %eax
jne .LBB1_3
# %bb.5:
leaq 8(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.7:
movq 16(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_8
# %bb.9:
movabsq $4294967328, %rdx # imm = 0x100000020
leaq 524256(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movl $16777216, 28(%rsp) # imm = 0x1000000
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13stencilKernelPhiS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_11:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_12
# %bb.13:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_14
# %bb.15:
movq 8(%rsp), %rsi
movl $67108864, %edx # imm = 0x4000000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_16
# %bb.17:
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_18
# %bb.19:
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_20
# %bb.21: # %_ZL10stencilGpuPhiS_.exit
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_22:
.cfi_def_cfa_offset 144
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $18, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB1_3:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movq %rbx, %rdi
movl $71, %edx
jmp .LBB1_4
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movq %rbx, %rdi
movl $72, %edx
jmp .LBB1_4
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movq %rbx, %rdi
movl $74, %edx
jmp .LBB1_4
.LBB1_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movq %rbx, %rdi
movl $77, %edx
jmp .LBB1_4
.LBB1_14:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movq %rbx, %rdi
movl $78, %edx
jmp .LBB1_4
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movq %rbx, %rdi
movl $80, %edx
jmp .LBB1_4
.LBB1_18:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movq %rbx, %rdi
movl $82, %edx
jmp .LBB1_4
.LBB1_20:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movq %rbx, %rdi
movl $83, %edx
.LBB1_4:
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13stencilKernelPhiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13stencilKernelPhiS_,@object # @_Z13stencilKernelPhiS_
.section .rodata,"a",@progbits
.globl _Z13stencilKernelPhiS_
.p2align 3, 0x0
_Z13stencilKernelPhiS_:
.quad _Z28__device_stub__stencilKernelPhiS_
.size _Z13stencilKernelPhiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Allocation failed\n"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "error at line %d: %s \n"
.size .L.str.1, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13stencilKernelPhiS_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__stencilKernelPhiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13stencilKernelPhiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void multMatriz(float *da, float *db, float *dc, int num){
float sum=0;
for (unsigned int k = 0; k<num; k++)
sum += da[threadIdx.y * num + k] * db[k * num + threadIdx.x];
dc[threadIdx.y*num + threadIdx.x] = (float) sum;
}
#define n 32
#define SIZE n*n*sizeof(float)
int main(){
int N=32;
float *A, *B, *C;
float *da, *db, *dc;
int m;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
dim3 dimGrid(1, 1);
dim3 dimBlock(N, N);
A=(float *)malloc(SIZE);
B=(float *)malloc(SIZE);
C=(float *)malloc(SIZE);
for(m=0;m<N*N;m++){
A[m]=(float)m+1;
B[m]=(float)m+2;
C[m]=(float)0;
}
cudaMalloc((void**)&da, SIZE);
cudaMalloc((void**)&db, SIZE);
cudaMalloc((void**)&dc, SIZE);
cudaMemcpy(da,A, SIZE, cudaMemcpyHostToDevice);
cudaMemcpy(db,B, SIZE, cudaMemcpyHostToDevice);
cudaMemcpy(dc,C, SIZE, cudaMemcpyHostToDevice);
cudaEventRecord(start, 0);
multMatriz<<<dimGrid , dimBlock >>>(da,db,dc,N);
//cudaThreadSynchronize();
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaMemcpy(C,dc, SIZE, cudaMemcpyDeviceToHost);
for(m=0;m<N*N;m++){
printf("%08.0f",A[m]);
printf("%c",( (m%N)<(N-1) ) ? '\t':'\n');
}
printf("\n\n");
for(m=0;m<N*N;m++){
printf("%08.0f",B[m]);
printf("%c",( (m%N)<(N-1) ) ? '\t':'\n');
}
printf("\n\n");
for(m=0;m<N*N;m++){
printf("%08.0f",C[m]);
printf("%c",( (m%N)<(N-1) ) ? '\t':'\n');
}
printf("\n\n");
float elapsedTime;
cudaEventElapsedTime(&elapsedTime,start,stop);
printf("Tiempo %4.6f milseg\n\n",elapsedTime);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaFree(da);
cudaFree(db);
cudaFree(dc);
free(A);
free(B);
free(C);
return 0;
} | code for sm_80
Function : _Z10multMatrizPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f05270 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*0040*/ @!P0 BRA 0x500 ; /* 0x000004b000008947 */
/* 0x000fea0003800000 */
/*0050*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff117624 */
/* 0x000fe200078e00ff */
/*0060*/ S2R R18, SR_TID.X ; /* 0x0000000000127919 */
/* 0x000e620000002100 */
/*0070*/ HFMA2.MMA R23, -RZ, RZ, 0, 0 ; /* 0x00000000ff177435 */
/* 0x000fe200000001ff */
/*0080*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe400078e00ff */
/*0090*/ IADD3 R2, R17.reuse, -0x1, RZ ; /* 0xffffffff11027810 */
/* 0x040fe40007ffe0ff */
/*00a0*/ LOP3.LUT R16, R17, 0x3, RZ, 0xc0, !PT ; /* 0x0000000311107812 */
/* 0x000fe400078ec0ff */
/*00b0*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*00c0*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fd60003f05270 */
/*00d0*/ @!P1 BRA 0x370 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*00e0*/ IMAD R21, R0, R17, 0x3 ; /* 0x0000000300157424 */
/* 0x001fe200078e0211 */
/*00f0*/ IADD3 R28, R18, c[0x0][0x178], RZ ; /* 0x00005e00121c7a10 */
/* 0x002fe20007ffe0ff */
/*0100*/ IMAD R22, R17.reuse, 0x3, R18.reuse ; /* 0x0000000311167824 */
/* 0x140fe200078e0212 */
/*0110*/ LEA R20, R17, R18, 0x1 ; /* 0x0000001211147211 */
/* 0x000fe200078e08ff */
/*0120*/ IMAD.MOV.U32 R23, RZ, RZ, RZ ; /* 0x000000ffff177224 */
/* 0x000fe200078e00ff */
/*0130*/ IADD3 R26, R16, -c[0x0][0x178], RZ ; /* 0x80005e00101a7a10 */
/* 0x000fe20007ffe0ff */
/*0140*/ IMAD.MOV.U32 R24, RZ, RZ, R18 ; /* 0x000000ffff187224 */
/* 0x000fe200078e0012 */
/*0150*/ MOV R19, RZ ; /* 0x000000ff00137202 */
/* 0x000fe40000000f00 */
/*0160*/ MOV R13, 0x4 ; /* 0x00000004000d7802 */
/* 0x000fe40000000f00 */
/*0170*/ IADD3 R2, R21.reuse, -0x3, RZ ; /* 0xfffffffd15027810 */
/* 0x040fe40007ffe0ff */
/*0180*/ IADD3 R4, R21.reuse, -0x2, RZ ; /* 0xfffffffe15047810 */
/* 0x040fe20007ffe0ff */
/*0190*/ IMAD.WIDE.U32 R14, R24, R13, c[0x0][0x168] ; /* 0x00005a00180e7625 */
/* 0x000fe200078e000d */
/*01a0*/ IADD3 R8, R21, -0x1, RZ ; /* 0xffffffff15087810 */
/* 0x000fc60007ffe0ff */
/*01b0*/ IMAD.WIDE.U32 R2, R2, R13.reuse, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x080fe400078e000d */
/*01c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1900 */
/*01d0*/ IMAD.WIDE.U32 R4, R4, R13.reuse, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x080fe400078e000d */
/*01e0*/ LDG.E R25, [R2.64] ; /* 0x0000000402197981 */
/* 0x0000a4000c1e1900 */
/*01f0*/ IMAD.WIDE.U32 R6, R28, R13.reuse, c[0x0][0x168] ; /* 0x00005a001c067625 */
/* 0x080fe400078e000d */
/*0200*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee8000c1e1900 */
/*0210*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee2000c1e1900 */
/*0220*/ IMAD.WIDE.U32 R8, R8, R13, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fc800078e000d */
/*0230*/ IMAD.WIDE.U32 R2, R20, R13.reuse, c[0x0][0x168] ; /* 0x00005a0014027625 */
/* 0x081fe400078e000d */
/*0240*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f24000c1e1900 */
/*0250*/ IMAD.WIDE.U32 R10, R21, R13.reuse, c[0x0][0x160] ; /* 0x00005800150a7625 */
/* 0x080fe400078e000d */
/*0260*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000f24000c1e1900 */
/*0270*/ IMAD.WIDE.U32 R12, R22, R13, c[0x0][0x168] ; /* 0x00005a00160c7625 */
/* 0x000fe400078e000d */
/*0280*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f68000c1e1900 */
/*0290*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f62000c1e1900 */
/*02a0*/ IADD3 R19, R19, 0x4, RZ ; /* 0x0000000413137810 */
/* 0x000fe20007ffe0ff */
/*02b0*/ IMAD R20, R17.reuse, 0x4, R20 ; /* 0x0000000411147824 */
/* 0x040fe200078e0214 */
/*02c0*/ LEA R28, R17, R28, 0x2 ; /* 0x0000001c111c7211 */
/* 0x000fc400078e10ff */
/*02d0*/ LEA R24, R17, R24, 0x2 ; /* 0x0000001811187211 */
/* 0x000fe400078e10ff */
/*02e0*/ IADD3 R21, R21, 0x4, RZ ; /* 0x0000000415157810 */
/* 0x000fe40007ffe0ff */
/*02f0*/ LEA R22, R17, R22, 0x2 ; /* 0x0000001611167211 */
/* 0x000fe200078e10ff */
/*0300*/ FFMA R14, R14, R25, R23 ; /* 0x000000190e0e7223 */
/* 0x004fc80000000017 */
/*0310*/ FFMA R5, R7, R4, R14 ; /* 0x0000000407057223 */
/* 0x008fe4000000000e */
/*0320*/ IMAD.IADD R4, R26, 0x1, R19 ; /* 0x000000011a047824 */
/* 0x000fca00078e0213 */
/*0330*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f25270 */
/*0340*/ FFMA R5, R2, R8, R5 ; /* 0x0000000802057223 */
/* 0x010fc80000000005 */
/*0350*/ FFMA R23, R12, R10, R5 ; /* 0x0000000a0c177223 */
/* 0x020fd00000000005 */
/*0360*/ @P1 BRA 0x160 ; /* 0xfffffdf000001947 */
/* 0x000fea000383ffff */
/*0370*/ @!P0 BRA 0x510 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0380*/ IMAD R18, R19, c[0x0][0x178], R18 ; /* 0x00005e0013127a24 */
/* 0x002fe400078e0212 */
/*0390*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fe400078e00ff */
/*03a0*/ IMAD R19, R0, c[0x0][0x178], R19 ; /* 0x00005e0000137a24 */
/* 0x001fe400078e0213 */
/*03b0*/ IMAD.WIDE.U32 R4, R18, R6, c[0x0][0x168] ; /* 0x00005a0012047625 */
/* 0x000fc800078e0006 */
/*03c0*/ IMAD.WIDE.U32 R2, R19, R6, c[0x0][0x160] ; /* 0x0000580013027625 */
/* 0x000fe400078e0006 */
/*03d0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*03e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*03f0*/ IADD3 R16, R16, -0x1, RZ ; /* 0xffffffff10107810 */
/* 0x000fc80007ffe0ff */
/*0400*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f05270 */
/*0410*/ FFMA R23, R4, R2, R23 ; /* 0x0000000204177223 */
/* 0x004fd80000000017 */
/*0420*/ @!P0 BRA 0x510 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0430*/ IADD3 R18, R18, c[0x0][0x178], RZ ; /* 0x00005e0012127a10 */
/* 0x000fe40007ffe0ff */
/*0440*/ IADD3 R19, R19, 0x1, RZ ; /* 0x0000000113137810 */
/* 0x000fca0007ffe0ff */
/*0450*/ IMAD.WIDE.U32 R2, R19, R6, c[0x0][0x160] ; /* 0x0000580013027625 */
/* 0x000fc800078e0006 */
/*0460*/ IMAD.WIDE.U32 R4, R18, R6, c[0x0][0x168] ; /* 0x00005a0012047625 */
/* 0x000fe400078e0006 */
/*0470*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0480*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0490*/ IADD3 R16, R16, -0x1, RZ ; /* 0xffffffff10107810 */
/* 0x000fe40007ffe0ff */
/*04a0*/ IADD3 R18, R18, c[0x0][0x178], RZ ; /* 0x00005e0012127a10 */
/* 0x000fe40007ffe0ff */
/*04b0*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fc40003f05270 */
/*04c0*/ IADD3 R19, R19, 0x1, RZ ; /* 0x0000000113137810 */
/* 0x000fe20007ffe0ff */
/*04d0*/ FFMA R23, R4, R2, R23 ; /* 0x0000000204177223 */
/* 0x004fd40000000017 */
/*04e0*/ @P0 BRA 0x450 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*04f0*/ BRA 0x510 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0500*/ HFMA2.MMA R23, -RZ, RZ, 0, 0 ; /* 0x00000000ff177435 */
/* 0x000fe400000001ff */
/*0510*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0520*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fe20000000f00 */
/*0530*/ IMAD R2, R0, c[0x0][0x178], R3 ; /* 0x00005e0000027a24 */
/* 0x005fc800078e0203 */
/*0540*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0005 */
/*0550*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x000fe2000c101904 */
/*0560*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0570*/ BRA 0x570; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void multMatriz(float *da, float *db, float *dc, int num){
float sum=0;
for (unsigned int k = 0; k<num; k++)
sum += da[threadIdx.y * num + k] * db[k * num + threadIdx.x];
dc[threadIdx.y*num + threadIdx.x] = (float) sum;
}
#define n 32
#define SIZE n*n*sizeof(float)
int main(){
int N=32;
float *A, *B, *C;
float *da, *db, *dc;
int m;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
dim3 dimGrid(1, 1);
dim3 dimBlock(N, N);
A=(float *)malloc(SIZE);
B=(float *)malloc(SIZE);
C=(float *)malloc(SIZE);
for(m=0;m<N*N;m++){
A[m]=(float)m+1;
B[m]=(float)m+2;
C[m]=(float)0;
}
cudaMalloc((void**)&da, SIZE);
cudaMalloc((void**)&db, SIZE);
cudaMalloc((void**)&dc, SIZE);
cudaMemcpy(da,A, SIZE, cudaMemcpyHostToDevice);
cudaMemcpy(db,B, SIZE, cudaMemcpyHostToDevice);
cudaMemcpy(dc,C, SIZE, cudaMemcpyHostToDevice);
cudaEventRecord(start, 0);
multMatriz<<<dimGrid , dimBlock >>>(da,db,dc,N);
//cudaThreadSynchronize();
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaMemcpy(C,dc, SIZE, cudaMemcpyDeviceToHost);
for(m=0;m<N*N;m++){
printf("%08.0f",A[m]);
printf("%c",( (m%N)<(N-1) ) ? '\t':'\n');
}
printf("\n\n");
for(m=0;m<N*N;m++){
printf("%08.0f",B[m]);
printf("%c",( (m%N)<(N-1) ) ? '\t':'\n');
}
printf("\n\n");
for(m=0;m<N*N;m++){
printf("%08.0f",C[m]);
printf("%c",( (m%N)<(N-1) ) ? '\t':'\n');
}
printf("\n\n");
float elapsedTime;
cudaEventElapsedTime(&elapsedTime,start,stop);
printf("Tiempo %4.6f milseg\n\n",elapsedTime);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaFree(da);
cudaFree(db);
cudaFree(dc);
free(A);
free(B);
free(C);
return 0;
} | .file "tmpxft_000b7dc1_00000000-6_multMatricesSolucion.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10multMatrizPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10multMatrizPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10multMatrizPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10multMatrizPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z10multMatrizPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10multMatrizPfS_S_iPfS_S_i
.globl _Z10multMatrizPfS_S_i
.type _Z10multMatrizPfS_S_i, @function
_Z10multMatrizPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10multMatrizPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10multMatrizPfS_S_i, .-_Z10multMatrizPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "%08.0f"
.LC4:
.string "%c"
.LC5:
.string "\n\n"
.LC6:
.string "Tiempo %4.6f milseg\n\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $32, 60(%rsp)
movl $32, 64(%rsp)
movl $1, 68(%rsp)
movl $4096, %edi
call malloc@PLT
movq %rax, %r13
movl $4096, %edi
call malloc@PLT
movq %rax, %r12
movl $4096, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
movss .LC0(%rip), %xmm3
movss .LC1(%rip), %xmm2
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movaps %xmm0, %xmm1
addss %xmm3, %xmm1
movss %xmm1, 0(%r13,%rax,4)
addss %xmm2, %xmm0
movss %xmm0, (%r12,%rax,4)
movl $0x00000000, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $1024, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4096, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L13:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $2, %ecx
movl $4096, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC3(%rip), %r15
leaq .LC4(%rip), %r14
.L15:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %r15, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %ebx, %edx
sarl $31, %edx
shrl $27, %edx
leal (%rdx,%rbx), %eax
andl $31, %eax
subl %edx, %eax
cmpl $30, %eax
setg %dl
movzbl %dl, %edx
addl $9, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $1024, %rbx
jne .L15
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC3(%rip), %r15
leaq .LC4(%rip), %r14
.L17:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %r15, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %ebx, %edx
sarl $31, %edx
shrl $27, %edx
leal (%rdx,%rbx), %eax
andl $31, %eax
subl %edx, %eax
cmpl $30, %eax
setg %dl
movzbl %dl, %edx
addl $9, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $1024, %rbx
jne .L17
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC3(%rip), %r15
leaq .LC4(%rip), %r14
.L19:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r15, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %ebx, %edx
sarl $31, %edx
shrl $27, %edx
leal (%rdx,%rbx), %eax
andl $31, %eax
subl %edx, %eax
cmpl $30, %eax
setg %dl
movzbl %dl, %edx
addl $9, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $1024, %rbx
jne .L19
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movl $32, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z10multMatrizPfS_S_iPfS_S_i
jmp .L13
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z10multMatrizPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z10multMatrizPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void multMatriz(float *da, float *db, float *dc, int num){
float sum=0;
for (unsigned int k = 0; k<num; k++)
sum += da[threadIdx.y * num + k] * db[k * num + threadIdx.x];
dc[threadIdx.y*num + threadIdx.x] = (float) sum;
}
#define n 32
#define SIZE n*n*sizeof(float)
int main(){
int N=32;
float *A, *B, *C;
float *da, *db, *dc;
int m;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
dim3 dimGrid(1, 1);
dim3 dimBlock(N, N);
A=(float *)malloc(SIZE);
B=(float *)malloc(SIZE);
C=(float *)malloc(SIZE);
for(m=0;m<N*N;m++){
A[m]=(float)m+1;
B[m]=(float)m+2;
C[m]=(float)0;
}
cudaMalloc((void**)&da, SIZE);
cudaMalloc((void**)&db, SIZE);
cudaMalloc((void**)&dc, SIZE);
cudaMemcpy(da,A, SIZE, cudaMemcpyHostToDevice);
cudaMemcpy(db,B, SIZE, cudaMemcpyHostToDevice);
cudaMemcpy(dc,C, SIZE, cudaMemcpyHostToDevice);
cudaEventRecord(start, 0);
multMatriz<<<dimGrid , dimBlock >>>(da,db,dc,N);
//cudaThreadSynchronize();
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaMemcpy(C,dc, SIZE, cudaMemcpyDeviceToHost);
for(m=0;m<N*N;m++){
printf("%08.0f",A[m]);
printf("%c",( (m%N)<(N-1) ) ? '\t':'\n');
}
printf("\n\n");
for(m=0;m<N*N;m++){
printf("%08.0f",B[m]);
printf("%c",( (m%N)<(N-1) ) ? '\t':'\n');
}
printf("\n\n");
for(m=0;m<N*N;m++){
printf("%08.0f",C[m]);
printf("%c",( (m%N)<(N-1) ) ? '\t':'\n');
}
printf("\n\n");
float elapsedTime;
cudaEventElapsedTime(&elapsedTime,start,stop);
printf("Tiempo %4.6f milseg\n\n",elapsedTime);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaFree(da);
cudaFree(db);
cudaFree(dc);
free(A);
free(B);
free(C);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void multMatriz(float *da, float *db, float *dc, int num){
float sum=0;
for (unsigned int k = 0; k<num; k++)
sum += da[threadIdx.y * num + k] * db[k * num + threadIdx.x];
dc[threadIdx.y*num + threadIdx.x] = (float) sum;
}
#define n 32
#define SIZE n*n*sizeof(float)
int main(){
int N=32;
float *A, *B, *C;
float *da, *db, *dc;
int m;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
dim3 dimGrid(1, 1);
dim3 dimBlock(N, N);
A=(float *)malloc(SIZE);
B=(float *)malloc(SIZE);
C=(float *)malloc(SIZE);
for(m=0;m<N*N;m++){
A[m]=(float)m+1;
B[m]=(float)m+2;
C[m]=(float)0;
}
hipMalloc((void**)&da, SIZE);
hipMalloc((void**)&db, SIZE);
hipMalloc((void**)&dc, SIZE);
hipMemcpy(da,A, SIZE, hipMemcpyHostToDevice);
hipMemcpy(db,B, SIZE, hipMemcpyHostToDevice);
hipMemcpy(dc,C, SIZE, hipMemcpyHostToDevice);
hipEventRecord(start, 0);
multMatriz<<<dimGrid , dimBlock >>>(da,db,dc,N);
//cudaThreadSynchronize();
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipMemcpy(C,dc, SIZE, hipMemcpyDeviceToHost);
for(m=0;m<N*N;m++){
printf("%08.0f",A[m]);
printf("%c",( (m%N)<(N-1) ) ? '\t':'\n');
}
printf("\n\n");
for(m=0;m<N*N;m++){
printf("%08.0f",B[m]);
printf("%c",( (m%N)<(N-1) ) ? '\t':'\n');
}
printf("\n\n");
for(m=0;m<N*N;m++){
printf("%08.0f",C[m]);
printf("%c",( (m%N)<(N-1) ) ? '\t':'\n');
}
printf("\n\n");
float elapsedTime;
hipEventElapsedTime(&elapsedTime,start,stop);
printf("Tiempo %4.6f milseg\n\n",elapsedTime);
hipEventDestroy(start);
hipEventDestroy(stop);
hipFree(da);
hipFree(db);
hipFree(dc);
free(A);
free(B);
free(C);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void multMatriz(float *da, float *db, float *dc, int num){
float sum=0;
for (unsigned int k = 0; k<num; k++)
sum += da[threadIdx.y * num + k] * db[k * num + threadIdx.x];
dc[threadIdx.y*num + threadIdx.x] = (float) sum;
}
#define n 32
#define SIZE n*n*sizeof(float)
int main(){
int N=32;
float *A, *B, *C;
float *da, *db, *dc;
int m;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
dim3 dimGrid(1, 1);
dim3 dimBlock(N, N);
A=(float *)malloc(SIZE);
B=(float *)malloc(SIZE);
C=(float *)malloc(SIZE);
for(m=0;m<N*N;m++){
A[m]=(float)m+1;
B[m]=(float)m+2;
C[m]=(float)0;
}
hipMalloc((void**)&da, SIZE);
hipMalloc((void**)&db, SIZE);
hipMalloc((void**)&dc, SIZE);
hipMemcpy(da,A, SIZE, hipMemcpyHostToDevice);
hipMemcpy(db,B, SIZE, hipMemcpyHostToDevice);
hipMemcpy(dc,C, SIZE, hipMemcpyHostToDevice);
hipEventRecord(start, 0);
multMatriz<<<dimGrid , dimBlock >>>(da,db,dc,N);
//cudaThreadSynchronize();
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipMemcpy(C,dc, SIZE, hipMemcpyDeviceToHost);
for(m=0;m<N*N;m++){
printf("%08.0f",A[m]);
printf("%c",( (m%N)<(N-1) ) ? '\t':'\n');
}
printf("\n\n");
for(m=0;m<N*N;m++){
printf("%08.0f",B[m]);
printf("%c",( (m%N)<(N-1) ) ? '\t':'\n');
}
printf("\n\n");
for(m=0;m<N*N;m++){
printf("%08.0f",C[m]);
printf("%c",( (m%N)<(N-1) ) ? '\t':'\n');
}
printf("\n\n");
float elapsedTime;
hipEventElapsedTime(&elapsedTime,start,stop);
printf("Tiempo %4.6f milseg\n\n",elapsedTime);
hipEventDestroy(start);
hipEventDestroy(stop);
hipFree(da);
hipFree(db);
hipFree(dc);
free(A);
free(B);
free(C);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10multMatrizPfS_S_i
.globl _Z10multMatrizPfS_S_i
.p2align 8
.type _Z10multMatrizPfS_S_i,@function
_Z10multMatrizPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v5, v0, 10, 10
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v7, v5, s2
v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
v_mov_b32_e32 v4, 0
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v2, v4 :: v_dual_add_nc_u32 v3, s3, v7
s_add_i32 s3, s3, 1
s_cmp_eq_u32 s2, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[8:9], 2, v[3:4]
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v8, v[8:9], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_dual_fmac_f32 v6, v8, v2 :: v_dual_add_nc_u32 v1, s2, v1
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
v_and_b32_e32 v0, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v5, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10multMatrizPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10multMatrizPfS_S_i, .Lfunc_end0-_Z10multMatrizPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10multMatrizPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z10multMatrizPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void multMatriz(float *da, float *db, float *dc, int num){
float sum=0;
for (unsigned int k = 0; k<num; k++)
sum += da[threadIdx.y * num + k] * db[k * num + threadIdx.x];
dc[threadIdx.y*num + threadIdx.x] = (float) sum;
}
#define n 32
#define SIZE n*n*sizeof(float)
int main(){
int N=32;
float *A, *B, *C;
float *da, *db, *dc;
int m;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
dim3 dimGrid(1, 1);
dim3 dimBlock(N, N);
A=(float *)malloc(SIZE);
B=(float *)malloc(SIZE);
C=(float *)malloc(SIZE);
for(m=0;m<N*N;m++){
A[m]=(float)m+1;
B[m]=(float)m+2;
C[m]=(float)0;
}
hipMalloc((void**)&da, SIZE);
hipMalloc((void**)&db, SIZE);
hipMalloc((void**)&dc, SIZE);
hipMemcpy(da,A, SIZE, hipMemcpyHostToDevice);
hipMemcpy(db,B, SIZE, hipMemcpyHostToDevice);
hipMemcpy(dc,C, SIZE, hipMemcpyHostToDevice);
hipEventRecord(start, 0);
multMatriz<<<dimGrid , dimBlock >>>(da,db,dc,N);
//cudaThreadSynchronize();
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipMemcpy(C,dc, SIZE, hipMemcpyDeviceToHost);
for(m=0;m<N*N;m++){
printf("%08.0f",A[m]);
printf("%c",( (m%N)<(N-1) ) ? '\t':'\n');
}
printf("\n\n");
for(m=0;m<N*N;m++){
printf("%08.0f",B[m]);
printf("%c",( (m%N)<(N-1) ) ? '\t':'\n');
}
printf("\n\n");
for(m=0;m<N*N;m++){
printf("%08.0f",C[m]);
printf("%c",( (m%N)<(N-1) ) ? '\t':'\n');
}
printf("\n\n");
float elapsedTime;
hipEventElapsedTime(&elapsedTime,start,stop);
printf("Tiempo %4.6f milseg\n\n",elapsedTime);
hipEventDestroy(start);
hipEventDestroy(stop);
hipFree(da);
hipFree(db);
hipFree(dc);
free(A);
free(B);
free(C);
return 0;
} | .text
.file "multMatricesSolucion.hip"
.globl _Z25__device_stub__multMatrizPfS_S_i # -- Begin function _Z25__device_stub__multMatrizPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__multMatrizPfS_S_i,@function
_Z25__device_stub__multMatrizPfS_S_i: # @_Z25__device_stub__multMatrizPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10multMatrizPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__multMatrizPfS_S_i, .Lfunc_end0-_Z25__device_stub__multMatrizPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3f800000 # float 1
.LCPI1_1:
.long 0x40000000 # float 2
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $168, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
movl $4096, %edx # imm = 0x1000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm2, %xmm2
cvtsi2ss %r12d, %xmm2
movaps %xmm2, %xmm3
addss %xmm0, %xmm3
movss %xmm3, (%rbx,%r12,4)
addss %xmm1, %xmm2
movss %xmm2, (%r14,%r12,4)
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_1
# %bb.2:
leaq 40(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 40(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $32, 52(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 52(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z10multMatrizPfS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl %r12d, %eax
notl %eax
andl $31, %eax
cmpl $1, %eax
movl $0, %edi
adcl $9, %edi
callq putchar@PLT
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_5
# %bb.6:
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl %r12d, %eax
notl %eax
andl $31, %eax
cmpl $1, %eax
movl $0, %edi
adcl $9, %edi
callq putchar@PLT
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_7
# %bb.8:
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_9: # =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl %r12d, %eax
notl %eax
andl $31, %eax
cmpl $1, %eax
movl $0, %edi
adcl $9, %edi
callq putchar@PLT
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_9
# %bb.10:
movl $.Lstr.2, %edi
callq puts@PLT
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10multMatrizPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10multMatrizPfS_S_i,@object # @_Z10multMatrizPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10multMatrizPfS_S_i
.p2align 3, 0x0
_Z10multMatrizPfS_S_i:
.quad _Z25__device_stub__multMatrizPfS_S_i
.size _Z10multMatrizPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%08.0f"
.size .L.str, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Tiempo %4.6f milseg\n\n"
.size .L.str.3, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10multMatrizPfS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.2,@object # @str.2
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.2:
.asciz "\n"
.size .Lstr.2, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__multMatrizPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10multMatrizPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10multMatrizPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f05270 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*0040*/ @!P0 BRA 0x500 ; /* 0x000004b000008947 */
/* 0x000fea0003800000 */
/*0050*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff117624 */
/* 0x000fe200078e00ff */
/*0060*/ S2R R18, SR_TID.X ; /* 0x0000000000127919 */
/* 0x000e620000002100 */
/*0070*/ HFMA2.MMA R23, -RZ, RZ, 0, 0 ; /* 0x00000000ff177435 */
/* 0x000fe200000001ff */
/*0080*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe400078e00ff */
/*0090*/ IADD3 R2, R17.reuse, -0x1, RZ ; /* 0xffffffff11027810 */
/* 0x040fe40007ffe0ff */
/*00a0*/ LOP3.LUT R16, R17, 0x3, RZ, 0xc0, !PT ; /* 0x0000000311107812 */
/* 0x000fe400078ec0ff */
/*00b0*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*00c0*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fd60003f05270 */
/*00d0*/ @!P1 BRA 0x370 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*00e0*/ IMAD R21, R0, R17, 0x3 ; /* 0x0000000300157424 */
/* 0x001fe200078e0211 */
/*00f0*/ IADD3 R28, R18, c[0x0][0x178], RZ ; /* 0x00005e00121c7a10 */
/* 0x002fe20007ffe0ff */
/*0100*/ IMAD R22, R17.reuse, 0x3, R18.reuse ; /* 0x0000000311167824 */
/* 0x140fe200078e0212 */
/*0110*/ LEA R20, R17, R18, 0x1 ; /* 0x0000001211147211 */
/* 0x000fe200078e08ff */
/*0120*/ IMAD.MOV.U32 R23, RZ, RZ, RZ ; /* 0x000000ffff177224 */
/* 0x000fe200078e00ff */
/*0130*/ IADD3 R26, R16, -c[0x0][0x178], RZ ; /* 0x80005e00101a7a10 */
/* 0x000fe20007ffe0ff */
/*0140*/ IMAD.MOV.U32 R24, RZ, RZ, R18 ; /* 0x000000ffff187224 */
/* 0x000fe200078e0012 */
/*0150*/ MOV R19, RZ ; /* 0x000000ff00137202 */
/* 0x000fe40000000f00 */
/*0160*/ MOV R13, 0x4 ; /* 0x00000004000d7802 */
/* 0x000fe40000000f00 */
/*0170*/ IADD3 R2, R21.reuse, -0x3, RZ ; /* 0xfffffffd15027810 */
/* 0x040fe40007ffe0ff */
/*0180*/ IADD3 R4, R21.reuse, -0x2, RZ ; /* 0xfffffffe15047810 */
/* 0x040fe20007ffe0ff */
/*0190*/ IMAD.WIDE.U32 R14, R24, R13, c[0x0][0x168] ; /* 0x00005a00180e7625 */
/* 0x000fe200078e000d */
/*01a0*/ IADD3 R8, R21, -0x1, RZ ; /* 0xffffffff15087810 */
/* 0x000fc60007ffe0ff */
/*01b0*/ IMAD.WIDE.U32 R2, R2, R13.reuse, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x080fe400078e000d */
/*01c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1900 */
/*01d0*/ IMAD.WIDE.U32 R4, R4, R13.reuse, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x080fe400078e000d */
/*01e0*/ LDG.E R25, [R2.64] ; /* 0x0000000402197981 */
/* 0x0000a4000c1e1900 */
/*01f0*/ IMAD.WIDE.U32 R6, R28, R13.reuse, c[0x0][0x168] ; /* 0x00005a001c067625 */
/* 0x080fe400078e000d */
/*0200*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee8000c1e1900 */
/*0210*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee2000c1e1900 */
/*0220*/ IMAD.WIDE.U32 R8, R8, R13, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fc800078e000d */
/*0230*/ IMAD.WIDE.U32 R2, R20, R13.reuse, c[0x0][0x168] ; /* 0x00005a0014027625 */
/* 0x081fe400078e000d */
/*0240*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f24000c1e1900 */
/*0250*/ IMAD.WIDE.U32 R10, R21, R13.reuse, c[0x0][0x160] ; /* 0x00005800150a7625 */
/* 0x080fe400078e000d */
/*0260*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000f24000c1e1900 */
/*0270*/ IMAD.WIDE.U32 R12, R22, R13, c[0x0][0x168] ; /* 0x00005a00160c7625 */
/* 0x000fe400078e000d */
/*0280*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f68000c1e1900 */
/*0290*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f62000c1e1900 */
/*02a0*/ IADD3 R19, R19, 0x4, RZ ; /* 0x0000000413137810 */
/* 0x000fe20007ffe0ff */
/*02b0*/ IMAD R20, R17.reuse, 0x4, R20 ; /* 0x0000000411147824 */
/* 0x040fe200078e0214 */
/*02c0*/ LEA R28, R17, R28, 0x2 ; /* 0x0000001c111c7211 */
/* 0x000fc400078e10ff */
/*02d0*/ LEA R24, R17, R24, 0x2 ; /* 0x0000001811187211 */
/* 0x000fe400078e10ff */
/*02e0*/ IADD3 R21, R21, 0x4, RZ ; /* 0x0000000415157810 */
/* 0x000fe40007ffe0ff */
/*02f0*/ LEA R22, R17, R22, 0x2 ; /* 0x0000001611167211 */
/* 0x000fe200078e10ff */
/*0300*/ FFMA R14, R14, R25, R23 ; /* 0x000000190e0e7223 */
/* 0x004fc80000000017 */
/*0310*/ FFMA R5, R7, R4, R14 ; /* 0x0000000407057223 */
/* 0x008fe4000000000e */
/*0320*/ IMAD.IADD R4, R26, 0x1, R19 ; /* 0x000000011a047824 */
/* 0x000fca00078e0213 */
/*0330*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f25270 */
/*0340*/ FFMA R5, R2, R8, R5 ; /* 0x0000000802057223 */
/* 0x010fc80000000005 */
/*0350*/ FFMA R23, R12, R10, R5 ; /* 0x0000000a0c177223 */
/* 0x020fd00000000005 */
/*0360*/ @P1 BRA 0x160 ; /* 0xfffffdf000001947 */
/* 0x000fea000383ffff */
/*0370*/ @!P0 BRA 0x510 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0380*/ IMAD R18, R19, c[0x0][0x178], R18 ; /* 0x00005e0013127a24 */
/* 0x002fe400078e0212 */
/*0390*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fe400078e00ff */
/*03a0*/ IMAD R19, R0, c[0x0][0x178], R19 ; /* 0x00005e0000137a24 */
/* 0x001fe400078e0213 */
/*03b0*/ IMAD.WIDE.U32 R4, R18, R6, c[0x0][0x168] ; /* 0x00005a0012047625 */
/* 0x000fc800078e0006 */
/*03c0*/ IMAD.WIDE.U32 R2, R19, R6, c[0x0][0x160] ; /* 0x0000580013027625 */
/* 0x000fe400078e0006 */
/*03d0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*03e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*03f0*/ IADD3 R16, R16, -0x1, RZ ; /* 0xffffffff10107810 */
/* 0x000fc80007ffe0ff */
/*0400*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f05270 */
/*0410*/ FFMA R23, R4, R2, R23 ; /* 0x0000000204177223 */
/* 0x004fd80000000017 */
/*0420*/ @!P0 BRA 0x510 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0430*/ IADD3 R18, R18, c[0x0][0x178], RZ ; /* 0x00005e0012127a10 */
/* 0x000fe40007ffe0ff */
/*0440*/ IADD3 R19, R19, 0x1, RZ ; /* 0x0000000113137810 */
/* 0x000fca0007ffe0ff */
/*0450*/ IMAD.WIDE.U32 R2, R19, R6, c[0x0][0x160] ; /* 0x0000580013027625 */
/* 0x000fc800078e0006 */
/*0460*/ IMAD.WIDE.U32 R4, R18, R6, c[0x0][0x168] ; /* 0x00005a0012047625 */
/* 0x000fe400078e0006 */
/*0470*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0480*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0490*/ IADD3 R16, R16, -0x1, RZ ; /* 0xffffffff10107810 */
/* 0x000fe40007ffe0ff */
/*04a0*/ IADD3 R18, R18, c[0x0][0x178], RZ ; /* 0x00005e0012127a10 */
/* 0x000fe40007ffe0ff */
/*04b0*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fc40003f05270 */
/*04c0*/ IADD3 R19, R19, 0x1, RZ ; /* 0x0000000113137810 */
/* 0x000fe20007ffe0ff */
/*04d0*/ FFMA R23, R4, R2, R23 ; /* 0x0000000204177223 */
/* 0x004fd40000000017 */
/*04e0*/ @P0 BRA 0x450 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*04f0*/ BRA 0x510 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0500*/ HFMA2.MMA R23, -RZ, RZ, 0, 0 ; /* 0x00000000ff177435 */
/* 0x000fe400000001ff */
/*0510*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0520*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fe20000000f00 */
/*0530*/ IMAD R2, R0, c[0x0][0x178], R3 ; /* 0x00005e0000027a24 */
/* 0x005fc800078e0203 */
/*0540*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0005 */
/*0550*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x000fe2000c101904 */
/*0560*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0570*/ BRA 0x570; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10multMatrizPfS_S_i
.globl _Z10multMatrizPfS_S_i
.p2align 8
.type _Z10multMatrizPfS_S_i,@function
_Z10multMatrizPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v5, v0, 10, 10
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v7, v5, s2
v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
v_mov_b32_e32 v4, 0
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v2, v4 :: v_dual_add_nc_u32 v3, s3, v7
s_add_i32 s3, s3, 1
s_cmp_eq_u32 s2, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[8:9], 2, v[3:4]
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v8, v[8:9], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_dual_fmac_f32 v6, v8, v2 :: v_dual_add_nc_u32 v1, s2, v1
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
v_and_b32_e32 v0, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v5, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10multMatrizPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10multMatrizPfS_S_i, .Lfunc_end0-_Z10multMatrizPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10multMatrizPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z10multMatrizPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b7dc1_00000000-6_multMatricesSolucion.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10multMatrizPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10multMatrizPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10multMatrizPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10multMatrizPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z10multMatrizPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10multMatrizPfS_S_iPfS_S_i
.globl _Z10multMatrizPfS_S_i
.type _Z10multMatrizPfS_S_i, @function
_Z10multMatrizPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10multMatrizPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10multMatrizPfS_S_i, .-_Z10multMatrizPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "%08.0f"
.LC4:
.string "%c"
.LC5:
.string "\n\n"
.LC6:
.string "Tiempo %4.6f milseg\n\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $32, 60(%rsp)
movl $32, 64(%rsp)
movl $1, 68(%rsp)
movl $4096, %edi
call malloc@PLT
movq %rax, %r13
movl $4096, %edi
call malloc@PLT
movq %rax, %r12
movl $4096, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
movss .LC0(%rip), %xmm3
movss .LC1(%rip), %xmm2
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movaps %xmm0, %xmm1
addss %xmm3, %xmm1
movss %xmm1, 0(%r13,%rax,4)
addss %xmm2, %xmm0
movss %xmm0, (%r12,%rax,4)
movl $0x00000000, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $1024, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4096, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L13:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $2, %ecx
movl $4096, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC3(%rip), %r15
leaq .LC4(%rip), %r14
.L15:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %r15, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %ebx, %edx
sarl $31, %edx
shrl $27, %edx
leal (%rdx,%rbx), %eax
andl $31, %eax
subl %edx, %eax
cmpl $30, %eax
setg %dl
movzbl %dl, %edx
addl $9, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $1024, %rbx
jne .L15
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC3(%rip), %r15
leaq .LC4(%rip), %r14
.L17:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %r15, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %ebx, %edx
sarl $31, %edx
shrl $27, %edx
leal (%rdx,%rbx), %eax
andl $31, %eax
subl %edx, %eax
cmpl $30, %eax
setg %dl
movzbl %dl, %edx
addl $9, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $1024, %rbx
jne .L17
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC3(%rip), %r15
leaq .LC4(%rip), %r14
.L19:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r15, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %ebx, %edx
sarl $31, %edx
shrl $27, %edx
leal (%rdx,%rbx), %eax
andl $31, %eax
subl %edx, %eax
cmpl $30, %eax
setg %dl
movzbl %dl, %edx
addl $9, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $1024, %rbx
jne .L19
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movl $32, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z10multMatrizPfS_S_iPfS_S_i
jmp .L13
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z10multMatrizPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z10multMatrizPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "multMatricesSolucion.hip"
.globl _Z25__device_stub__multMatrizPfS_S_i # -- Begin function _Z25__device_stub__multMatrizPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__multMatrizPfS_S_i,@function
_Z25__device_stub__multMatrizPfS_S_i: # @_Z25__device_stub__multMatrizPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10multMatrizPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__multMatrizPfS_S_i, .Lfunc_end0-_Z25__device_stub__multMatrizPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3f800000 # float 1
.LCPI1_1:
.long 0x40000000 # float 2
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $168, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
movl $4096, %edx # imm = 0x1000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm2, %xmm2
cvtsi2ss %r12d, %xmm2
movaps %xmm2, %xmm3
addss %xmm0, %xmm3
movss %xmm3, (%rbx,%r12,4)
addss %xmm1, %xmm2
movss %xmm2, (%r14,%r12,4)
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_1
# %bb.2:
leaq 40(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 40(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $32, 52(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 52(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z10multMatrizPfS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl %r12d, %eax
notl %eax
andl $31, %eax
cmpl $1, %eax
movl $0, %edi
adcl $9, %edi
callq putchar@PLT
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_5
# %bb.6:
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl %r12d, %eax
notl %eax
andl $31, %eax
cmpl $1, %eax
movl $0, %edi
adcl $9, %edi
callq putchar@PLT
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_7
# %bb.8:
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_9: # =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl %r12d, %eax
notl %eax
andl $31, %eax
cmpl $1, %eax
movl $0, %edi
adcl $9, %edi
callq putchar@PLT
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_9
# %bb.10:
movl $.Lstr.2, %edi
callq puts@PLT
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10multMatrizPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10multMatrizPfS_S_i,@object # @_Z10multMatrizPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10multMatrizPfS_S_i
.p2align 3, 0x0
_Z10multMatrizPfS_S_i:
.quad _Z25__device_stub__multMatrizPfS_S_i
.size _Z10multMatrizPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%08.0f"
.size .L.str, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Tiempo %4.6f milseg\n\n"
.size .L.str.3, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10multMatrizPfS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.2,@object # @str.2
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.2:
.asciz "\n"
.size .Lstr.2, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__multMatrizPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10multMatrizPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //transform length
#define TLEN 128
#define TILE_DIM 16
#define HEIGHT 8 //1, 2, 4, 8
#define NEG_2PI_BY_TLEN -0.04908738521f //-2*PI/128
#define STRIDE_STAGE_1 0x00000040 //64
#define STRIDE_STAGE_2 0x00000020 //32
#define STRIDE_STAGE_3 0x00000010 //16
#define STRIDE_STAGE_4 0x00000008 //08
#define STRIDE_STAGE_5 0x00000004 //04
#define STRIDE_STAGE_6 0x00000002 //02
#define STRIDE_STAGE_7 0x00000001 //01
#define M12 0x60
#define M34 0x18
#define M35 0x14
#define M46 0x0a
#define M246 0x2a
#define M135 0x54
#define M357 0x15
#define M56 0x06
#define M5 0x04
__device__ int bitreverse(int tid)
{
int revtid = tid;
revtid = ((0xf0f0f0f0 & revtid) >> 4) | ((0x0f0f0f0f & revtid) << 4);
revtid = ((0xcccccccc & revtid) >> 2) | ((0x33333333 & revtid) << 2);
revtid = ((0xaaaaaaaa & revtid) >> 2) | ((0x55555555 & revtid));
return revtid;
}
__global__ void FFT1D(float *real, float *img)
{
float rVal[HEIGHT], iVal[HEIGHT];
//assuming that thread block size is 128
__shared__ float shReal[HEIGHT][TLEN];
__shared__ float shImg[HEIGHT][TLEN];
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
rVal[I] = real[((blockIdx.x*HEIGHT) + I)*blockDim.x + threadIdx.x];
iVal[I] = img[((blockIdx.x*HEIGHT) + I)*blockDim.x + threadIdx.x];
}
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][threadIdx.x] = rVal[I];
shImg[I][threadIdx.x] = iVal[I];
}
__syncthreads();
if((threadIdx.x & STRIDE_STAGE_1) == STRIDE_STAGE_1)
{
rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_1] - rVal[0];
iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_1] - iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_1] - rVal[1];
iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_1] - iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_1] - rVal[2];
iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_1] - iVal[2];
rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_1] - rVal[3];
iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_1] - iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_1] - rVal[4];
iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_1] - iVal[4];
rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_1] - rVal[5];
iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_1] - iVal[5];
rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_1] - rVal[6];
iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_1] - iVal[6];
rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_1] - rVal[7];
iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_1] - iVal[7];
#endif
}
else
{
rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_1] + rVal[0];
iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_1] + iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_1] + rVal[1];
iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_1] + iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_1] + rVal[2];
iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_1] + iVal[2];
rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_1] + rVal[3];
iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_1] + iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_1] + rVal[4];
iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_1] + iVal[4];
rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_1] + rVal[5];
iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_1] + iVal[5];
rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_1] + rVal[6];
iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_1] + iVal[6];
rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_1] + rVal[7];
iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_1] + iVal[7];
#endif
}
if((threadIdx.x & STRIDE_STAGE_2) == STRIDE_STAGE_2)
{
//calculate Q twiddle factor
float Q = (float)((threadIdx.x & STRIDE_STAGE_1)>>1);
Q = Q*NEG_2PI_BY_TLEN;
float c, s, T;
__sincosf(Q, &s, &c);
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
T = rVal[I];
rVal[I] = rVal[I]*c - iVal[I]*s;
iVal[I] = T*s + iVal[I]*c;
}
}
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][threadIdx.x] = rVal[I];
shImg[I][threadIdx.x] = iVal[I];
}
__syncthreads();
//stage 2
if((threadIdx.x & STRIDE_STAGE_2) == STRIDE_STAGE_2)
{
rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_2] - rVal[0];
iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_2] - iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_2] - rVal[1];
iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_2] - iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_2] - rVal[2];
iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_2] - iVal[2];
rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_2] - rVal[3];
iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_2] - iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_2] - rVal[4];
iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_2] - iVal[4];
rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_2] - rVal[5];
iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_2] - iVal[5];
rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_2] - rVal[6];
iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_2] - iVal[6];
rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_2] - rVal[7];
iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_2] - iVal[7];
#endif
}
else
{
rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_2] + rVal[0];
iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_2] + iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_2] + rVal[1];
iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_2] + iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_2] + rVal[2];
iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_2] + iVal[2];
rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_2] + rVal[3];
iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_2] + iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_2] + rVal[4];
iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_2] + iVal[4];
rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_2] + rVal[5];
iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_2] + iVal[5];
rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_2] + rVal[6];
iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_2] + iVal[6];
rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_2] + rVal[7];
iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_2] + iVal[7];
#endif
}
//end of stage 2
//multiply with twiddle for beginning of stage 3
//STRIDE_STAGE_3 16
if((threadIdx.x & STRIDE_STAGE_3) == STRIDE_STAGE_3)
{
//calculate Q twiddle factor
float Q = (float)((threadIdx.x & STRIDE_STAGE_2) | ((threadIdx.x & STRIDE_STAGE_1)>>2));
Q = Q*NEG_2PI_BY_TLEN;
float c, s, T;
__sincosf(Q, &s, &c);
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
T = rVal[I];
rVal[I] = rVal[I]*c - iVal[I]*s;
iVal[I] = T*s + iVal[I]*c;
}
}
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][threadIdx.x] = rVal[I];
shImg[I][threadIdx.x] = iVal[I];
}
__syncthreads();
//stage3
if((threadIdx.x & STRIDE_STAGE_3) == STRIDE_STAGE_3)
{
rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_3] - rVal[0];
iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_3] - iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_3] - rVal[1];
iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_3] - iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_3] - rVal[2];
iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_3] - iVal[2];
rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_3] - rVal[3];
iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_3] - iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_3] - rVal[4];
iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_3] - iVal[4];
rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_3] - rVal[5];
iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_3] - iVal[5];
rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_3] - rVal[6];
iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_3] - iVal[6];
rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_3] - rVal[7];
iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_3] - iVal[7];
#endif
}
else
{
rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_3] + rVal[0];
iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_3] + iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_3] + rVal[1];
iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_3] + iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_3] + rVal[2];
iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_3] + iVal[2];
rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_3] + rVal[3];
iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_3] + iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_3] + rVal[4];
iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_3] + iVal[4];
rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_3] + rVal[5];
iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_3] + iVal[5];
rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_3] + rVal[6];
iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_3] + iVal[6];
rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_3] + rVal[7];
iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_3] + iVal[7];
#endif
}
//end of stage 3
//multiply with twiddle for beginning of stage 4
//STRIDE_STAGE_4 8
if((threadIdx.x & STRIDE_STAGE_4) == STRIDE_STAGE_4)
{
//calculate Q twiddle factor
float Q = (float)(((threadIdx.x & STRIDE_STAGE_1)>>3) |
((threadIdx.x & STRIDE_STAGE_2)>>1) | ((threadIdx.x & STRIDE_STAGE_3)<<1));
Q = Q*NEG_2PI_BY_TLEN;
float c, s, T;
__sincosf(Q, &s, &c);
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
T = rVal[I];
rVal[I] = rVal[I]*c - iVal[I]*s;
iVal[I] = T*s + iVal[I]*c;
}
}
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][threadIdx.x] = rVal[I];
shImg[I][threadIdx.x] = iVal[I];
}
__syncthreads();
//stage 4
if((threadIdx.x & STRIDE_STAGE_4) == STRIDE_STAGE_4)
{
rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_4] - rVal[0];
iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_4] - iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_4] - rVal[1];
iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_4] - iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_4] - rVal[2];
iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_4] - iVal[2];
rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_4] - rVal[3];
iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_4] - iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_4] - rVal[4];
iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_4] - iVal[4];
rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_4] - rVal[5];
iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_4] - iVal[5];
rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_4] - rVal[6];
iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_4] - iVal[6];
rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_4] - rVal[7];
iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_4] - iVal[7];
#endif
}
else
{
rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_4] + rVal[0];
iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_4] + iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_4] + rVal[1];
iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_4] + iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_4] + rVal[2];
iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_4] + iVal[2];
rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_4] + rVal[3];
iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_4] + iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_4] + rVal[4];
iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_4] + iVal[4];
rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_4] + rVal[5];
iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_4] + iVal[5];
rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_4] + rVal[6];
iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_4] + iVal[6];
rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_4] + rVal[7];
iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_4] + iVal[7];
#endif
}
//end of stage 4
//multiply with twiddle for beginning of stage 5
//STRIDE_STAGE_5 4
if((threadIdx.x & STRIDE_STAGE_5) == STRIDE_STAGE_5)
{
//calculate Q twiddle factor
int q = ((threadIdx.x & M12)>>4) | (threadIdx.x & M34);
q = (q & M35) | ((q & M46)<<2);
float Q = q*NEG_2PI_BY_TLEN;
float c, s, T;
__sincosf(Q, &s, &c);
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
T = rVal[I];
rVal[I] = rVal[I]*c - iVal[I]*s;
iVal[I] = T*s + iVal[I]*c;
}
}
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][threadIdx.x] = rVal[I];
shImg[I][threadIdx.x] = iVal[I];
}
__syncthreads();
//stage 5
if((threadIdx.x & STRIDE_STAGE_5) == STRIDE_STAGE_5)
{
rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_5] - rVal[0];
iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_5] - iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_5] - rVal[1];
iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_5] - iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_5] - rVal[2];
iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_5] - iVal[2];
rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_5] - rVal[3];
iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_5] - iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_5] - rVal[4];
iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_5] - iVal[4];
rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_5] - rVal[5];
iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_5] - iVal[5];
rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_5] - rVal[6];
iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_5] - iVal[6];
rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_5] - rVal[7];
iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_5] - iVal[7];
#endif
}
else
{
rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_5] + rVal[0];
iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_5] + iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_5] + rVal[1];
iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_5] + iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_5] + rVal[2];
iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_5] + iVal[2];
rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_5] + rVal[3];
iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_5] + iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_5] + rVal[4];
iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_5] + iVal[4];
rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_5] + rVal[5];
iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_5] + iVal[5];
rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_5] + rVal[6];
iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_5] + iVal[6];
rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_5] + rVal[7];
iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_5] + iVal[7];
#endif
}
//end of stage 5
//multiply with twiddle for beginning of stage 6
//STRIDE_STAGE_6 2
if((threadIdx.x & STRIDE_STAGE_6) == STRIDE_STAGE_6)
{
//calculate Q twiddle factor
int q = ((threadIdx.x & M12)>>5) | ((threadIdx.x & M34)>>1) |
((threadIdx.x & M5)<<3);
q = (q & M246) | ((q & M357)<<2);
float Q = q*NEG_2PI_BY_TLEN;
float c, s, T;
__sincosf(Q, &s, &c);
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
T = rVal[I];
rVal[I] = rVal[I]*c - iVal[I]*s;
iVal[I] = T*s + iVal[I]*c;
}
}
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][threadIdx.x] = rVal[I];
shImg[I][threadIdx.x] = iVal[I];
}
__syncthreads();
//stage 6
if((threadIdx.x & STRIDE_STAGE_6) == STRIDE_STAGE_6)
{
rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_6] - rVal[0];
iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_6] - iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_6] - rVal[1];
iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_6] - iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_6] - rVal[2];
iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_6] - iVal[2];
rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_6] - rVal[3];
iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_6] - iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_6] - rVal[4];
iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_6] - iVal[4];
rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_6] - rVal[5];
iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_6] - iVal[5];
rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_6] - rVal[6];
iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_6] - iVal[6];
rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_6] - rVal[7];
iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_6] - iVal[7];
#endif
}
else
{
rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_6] + rVal[0];
iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_6] + iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_6] + rVal[1];
iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_6] + iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_6] + rVal[2];
iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_6] + iVal[2];
rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_6] + rVal[3];
iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_6] + iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_6] + rVal[4];
iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_6] + iVal[4];
rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_6] + rVal[5];
iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_6] + iVal[5];
rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_6] + rVal[6];
iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_6] + iVal[6];
rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_6] + rVal[7];
iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_6] + iVal[7];
#endif
}
//end of stage 6
//multiply with twiddle for beginning of stage 7
//STRIDE_STAGE_7 1
if((threadIdx.x & STRIDE_STAGE_7) == STRIDE_STAGE_7)
{
//calculate Q twiddle factor
int q = ((threadIdx.x & M12)>>4) | (threadIdx.x & M34) |
((threadIdx.x & M56)<<4);
q = ((q & M135)>>2) | (q & M246);
float Q = q*NEG_2PI_BY_TLEN;
float c, s, T;
__sincosf(Q, &s, &c);
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
T = rVal[I];
rVal[I] = rVal[I]*c - iVal[I]*s;
iVal[I] = T*s + iVal[I]*c;
}
}
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][threadIdx.x] = rVal[I];
shImg[I][threadIdx.x] = iVal[I];
}
__syncthreads();
//stage 7
if((threadIdx.x & STRIDE_STAGE_7) == STRIDE_STAGE_7)
{
rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_7] - rVal[0];
iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_7] - iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_7] - rVal[1];
iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_7] - iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_7] - rVal[2];
iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_7] - iVal[2];
rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_7] - rVal[3];
iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_7] - iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_7] - rVal[4];
iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_7] - iVal[4];
rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_7] - rVal[5];
iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_7] - iVal[5];
rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_7] - rVal[6];
iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_7] - iVal[6];
rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_7] - rVal[7];
iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_7] - iVal[7];
#endif
}
else
{
rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_7] + rVal[0];
iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_7] + iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_7] + rVal[1];
iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_7] + iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_7] + rVal[2];
iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_7] + iVal[2];
rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_7] + rVal[3];
iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_7] + iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_7] + rVal[4];
iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_7] + iVal[4];
rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_7] + rVal[5];
iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_7] + iVal[5];
rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_7] + rVal[6];
iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_7] + iVal[6];
rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_7] + rVal[7];
iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_7] + iVal[7];
#endif
}
int revtid = bitreverse(threadIdx.x);
/*
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][revtid] = rVal[I];
shImg[I][revtid] = iVal[I];
}
*/
shReal[0][revtid] = rVal[0];
shImg[0][revtid] = iVal[0];
#if HEIGHT > 1
shReal[1][revtid] = rVal[1];
shImg[1][revtid] = iVal[1];
#endif
#if HEIGHT > 2
shReal[2][revtid] = rVal[2];
shImg[2][revtid] = iVal[2];
shReal[3][revtid] = rVal[3];
shImg[3][revtid] = iVal[3];
#endif
#if HEIGHT > 4
shReal[4][revtid] = rVal[4];
shImg[4][revtid] = iVal[4];
shReal[5][revtid] = rVal[5];
shImg[5][revtid] = iVal[5];
shReal[6][revtid] = rVal[6];
shImg[6][revtid] = iVal[6];
shReal[7][revtid] = rVal[7];
shImg[7][revtid] = iVal[7];
#endif
__syncthreads();
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
real[((blockIdx.x*HEIGHT) + I)*blockDim.x + threadIdx.x] = shReal[I][threadIdx.x];
img[((blockIdx.x*HEIGHT) + I)*blockDim.x + threadIdx.x] = shImg[I][threadIdx.x];
}
}
__global__ void transposeDiagonal_xy(float *odatar, float *odatai, float *idatar, float *idatai, int width)
{
__shared__ float tile[TILE_DIM][TILE_DIM+1];
int blockIdx_x, blockIdx_y;
// do diagonal reordering
blockIdx_y = blockIdx.x;
blockIdx_x = (blockIdx.x+blockIdx.y)%gridDim.x;
// from here on the code is same as previous kernel except blockIdx_x replaces blockIdx.x
// and similarly for y
int xIndex = blockIdx_x * TILE_DIM + threadIdx.x;
int yIndex = blockIdx_y * TILE_DIM + threadIdx.y;
int index_in = xIndex + (yIndex + blockIdx.z*width)*width;
xIndex = blockIdx_y * TILE_DIM + threadIdx.x;
yIndex = blockIdx_x * TILE_DIM + threadIdx.y;
int index_out = xIndex + (yIndex + blockIdx.z*width)*width;
tile[threadIdx.y][threadIdx.x] = idatar[index_in];
__syncthreads();
odatar[index_out] = tile[threadIdx.x][threadIdx.y];
__syncthreads();
tile[threadIdx.y][threadIdx.x] = idatai[index_in];
__syncthreads();
odatai[index_out] = tile[threadIdx.x][threadIdx.y];
}
__global__ void transposeDiagonal_xz(float *odatar, float *odatai, float *idatar, float *idatai, int width)
{
__shared__ float tile[TILE_DIM][TILE_DIM+1];
int blockIdx_x, blockIdx_z;
// do diagonal reordering
blockIdx_z = blockIdx.x;
blockIdx_x = (blockIdx.x+blockIdx.z)%gridDim.x;
// from here on the code is same as previous kernel except blockIdx_x replaces blockIdx.x
// and similarly for y
int xIndex = blockIdx_x * TILE_DIM + threadIdx.x;
int zIndex = blockIdx_z * TILE_DIM + threadIdx.z;
int index_in = xIndex + (blockIdx.y + zIndex*width)*width;
xIndex = blockIdx_z * TILE_DIM + threadIdx.x;
zIndex = blockIdx_x * TILE_DIM + threadIdx.z;
int index_out = xIndex + (blockIdx.y + zIndex*width)*width;
tile[threadIdx.z][threadIdx.x] = idatar[index_in];
__syncthreads();
odatar[index_out] = tile[threadIdx.x][threadIdx.z];
__syncthreads();
tile[threadIdx.z][threadIdx.x] = idatai[index_in];
__syncthreads();
odatai[index_out] = tile[threadIdx.x][threadIdx.z];
}
__global__ void transposeDiagonal_xy(float *odata, float *idata, int width)
{
__shared__ float tile[TILE_DIM][TILE_DIM+1];
int blockIdx_x, blockIdx_y;
// do diagonal reordering
blockIdx_y = blockIdx.x;
blockIdx_x = (blockIdx.x+blockIdx.y)%gridDim.x;
// from here on the code is same as previous kernel except blockIdx_x replaces blockIdx.x
// and similarly for y
int xIndex = blockIdx_x * TILE_DIM + threadIdx.x;
int yIndex = blockIdx_y * TILE_DIM + threadIdx.y;
int index_in = xIndex + (yIndex + blockIdx.z*width)*width;
xIndex = blockIdx_y * TILE_DIM + threadIdx.x;
yIndex = blockIdx_x * TILE_DIM + threadIdx.y;
int index_out = xIndex + (yIndex + blockIdx.z*width)*width;
tile[threadIdx.y][threadIdx.x] = idata[index_in];
__syncthreads();
odata[index_out] = tile[threadIdx.x][threadIdx.y];
}
__global__ void transposeDiagonal_xz(float *odata, float *idata, int width)
{
__shared__ float tile[TILE_DIM][TILE_DIM+1];
int blockIdx_x, blockIdx_z;
// do diagonal reordering
blockIdx_z = blockIdx.x;
blockIdx_x = (blockIdx.x+blockIdx.z)%gridDim.x;
// from here on the code is same as previous kernel except blockIdx_x replaces blockIdx.x
// and similarly for y
int xIndex = blockIdx_x * TILE_DIM + threadIdx.x;
int zIndex = blockIdx_z * TILE_DIM + threadIdx.z;
int index_in = xIndex + (blockIdx.y + zIndex*width)*width;
xIndex = blockIdx_z * TILE_DIM + threadIdx.x;
zIndex = blockIdx_x * TILE_DIM + threadIdx.z;
int index_out = xIndex + (blockIdx.y + zIndex*width)*width;
tile[threadIdx.z][threadIdx.x] = idata[index_in];
__syncthreads();
odata[index_out] = tile[threadIdx.x][threadIdx.z];
} | .file "tmpxft_0005351b_00000000-6_fft.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10bitreversei
.type _Z10bitreversei, @function
_Z10bitreversei:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z10bitreversei, .-_Z10bitreversei
.globl _Z26__device_stub__Z5FFT1DPfS_PfS_
.type _Z26__device_stub__Z5FFT1DPfS_PfS_, @function
_Z26__device_stub__Z5FFT1DPfS_PfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5FFT1DPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z26__device_stub__Z5FFT1DPfS_PfS_, .-_Z26__device_stub__Z5FFT1DPfS_PfS_
.globl _Z5FFT1DPfS_
.type _Z5FFT1DPfS_, @function
_Z5FFT1DPfS_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z5FFT1DPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z5FFT1DPfS_, .-_Z5FFT1DPfS_
.globl _Z47__device_stub__Z20transposeDiagonal_xyPfS_S_S_iPfS_S_S_i
.type _Z47__device_stub__Z20transposeDiagonal_xyPfS_S_S_iPfS_S_S_i, @function
_Z47__device_stub__Z20transposeDiagonal_xyPfS_S_S_iPfS_S_S_i:
.LFB2054:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20transposeDiagonal_xyPfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z47__device_stub__Z20transposeDiagonal_xyPfS_S_S_iPfS_S_S_i, .-_Z47__device_stub__Z20transposeDiagonal_xyPfS_S_S_iPfS_S_S_i
.globl _Z20transposeDiagonal_xyPfS_S_S_i
.type _Z20transposeDiagonal_xyPfS_S_S_i, @function
_Z20transposeDiagonal_xyPfS_S_S_i:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z20transposeDiagonal_xyPfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z20transposeDiagonal_xyPfS_S_S_i, .-_Z20transposeDiagonal_xyPfS_S_S_i
.globl _Z47__device_stub__Z20transposeDiagonal_xzPfS_S_S_iPfS_S_S_i
.type _Z47__device_stub__Z20transposeDiagonal_xzPfS_S_S_iPfS_S_S_i, @function
_Z47__device_stub__Z20transposeDiagonal_xzPfS_S_S_iPfS_S_S_i:
.LFB2056:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20transposeDiagonal_xzPfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _Z47__device_stub__Z20transposeDiagonal_xzPfS_S_S_iPfS_S_S_i, .-_Z47__device_stub__Z20transposeDiagonal_xzPfS_S_S_iPfS_S_S_i
.globl _Z20transposeDiagonal_xzPfS_S_S_i
.type _Z20transposeDiagonal_xzPfS_S_S_i, @function
_Z20transposeDiagonal_xzPfS_S_S_i:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z20transposeDiagonal_xzPfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z20transposeDiagonal_xzPfS_S_S_i, .-_Z20transposeDiagonal_xzPfS_S_S_i
.globl _Z43__device_stub__Z20transposeDiagonal_xyPfS_iPfS_i
.type _Z43__device_stub__Z20transposeDiagonal_xyPfS_iPfS_i, @function
_Z43__device_stub__Z20transposeDiagonal_xyPfS_iPfS_i:
.LFB2058:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20transposeDiagonal_xyPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z43__device_stub__Z20transposeDiagonal_xyPfS_iPfS_i, .-_Z43__device_stub__Z20transposeDiagonal_xyPfS_iPfS_i
.globl _Z20transposeDiagonal_xyPfS_i
.type _Z20transposeDiagonal_xyPfS_i, @function
_Z20transposeDiagonal_xyPfS_i:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z20transposeDiagonal_xyPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z20transposeDiagonal_xyPfS_i, .-_Z20transposeDiagonal_xyPfS_i
.globl _Z43__device_stub__Z20transposeDiagonal_xzPfS_iPfS_i
.type _Z43__device_stub__Z20transposeDiagonal_xzPfS_iPfS_i, @function
_Z43__device_stub__Z20transposeDiagonal_xzPfS_iPfS_i:
.LFB2060:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20transposeDiagonal_xzPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z43__device_stub__Z20transposeDiagonal_xzPfS_iPfS_i, .-_Z43__device_stub__Z20transposeDiagonal_xzPfS_iPfS_i
.globl _Z20transposeDiagonal_xzPfS_i
.type _Z20transposeDiagonal_xzPfS_i, @function
_Z20transposeDiagonal_xzPfS_i:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z20transposeDiagonal_xzPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z20transposeDiagonal_xzPfS_i, .-_Z20transposeDiagonal_xzPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z20transposeDiagonal_xzPfS_i"
.LC1:
.string "_Z20transposeDiagonal_xyPfS_i"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z20transposeDiagonal_xzPfS_S_S_i"
.align 8
.LC3:
.string "_Z20transposeDiagonal_xyPfS_S_S_i"
.section .rodata.str1.1
.LC4:
.string "_Z5FFT1DPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2063:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20transposeDiagonal_xzPfS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z20transposeDiagonal_xyPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z20transposeDiagonal_xzPfS_S_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z20transposeDiagonal_xyPfS_S_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z5FFT1DPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //transform length
#define TLEN 128
#define TILE_DIM 16
#define HEIGHT 8 //1, 2, 4, 8
#define NEG_2PI_BY_TLEN -0.04908738521f //-2*PI/128
#define STRIDE_STAGE_1 0x00000040 //64
#define STRIDE_STAGE_2 0x00000020 //32
#define STRIDE_STAGE_3 0x00000010 //16
#define STRIDE_STAGE_4 0x00000008 //08
#define STRIDE_STAGE_5 0x00000004 //04
#define STRIDE_STAGE_6 0x00000002 //02
#define STRIDE_STAGE_7 0x00000001 //01
#define M12 0x60
#define M34 0x18
#define M35 0x14
#define M46 0x0a
#define M246 0x2a
#define M135 0x54
#define M357 0x15
#define M56 0x06
#define M5 0x04
__device__ int bitreverse(int tid)
{
int revtid = tid;
revtid = ((0xf0f0f0f0 & revtid) >> 4) | ((0x0f0f0f0f & revtid) << 4);
revtid = ((0xcccccccc & revtid) >> 2) | ((0x33333333 & revtid) << 2);
revtid = ((0xaaaaaaaa & revtid) >> 2) | ((0x55555555 & revtid));
return revtid;
}
__global__ void FFT1D(float *real, float *img)
{
float rVal[HEIGHT], iVal[HEIGHT];
//assuming that thread block size is 128
__shared__ float shReal[HEIGHT][TLEN];
__shared__ float shImg[HEIGHT][TLEN];
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
rVal[I] = real[((blockIdx.x*HEIGHT) + I)*blockDim.x + threadIdx.x];
iVal[I] = img[((blockIdx.x*HEIGHT) + I)*blockDim.x + threadIdx.x];
}
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][threadIdx.x] = rVal[I];
shImg[I][threadIdx.x] = iVal[I];
}
__syncthreads();
if((threadIdx.x & STRIDE_STAGE_1) == STRIDE_STAGE_1)
{
rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_1] - rVal[0];
iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_1] - iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_1] - rVal[1];
iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_1] - iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_1] - rVal[2];
iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_1] - iVal[2];
rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_1] - rVal[3];
iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_1] - iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_1] - rVal[4];
iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_1] - iVal[4];
rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_1] - rVal[5];
iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_1] - iVal[5];
rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_1] - rVal[6];
iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_1] - iVal[6];
rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_1] - rVal[7];
iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_1] - iVal[7];
#endif
}
else
{
rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_1] + rVal[0];
iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_1] + iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_1] + rVal[1];
iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_1] + iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_1] + rVal[2];
iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_1] + iVal[2];
rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_1] + rVal[3];
iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_1] + iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_1] + rVal[4];
iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_1] + iVal[4];
rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_1] + rVal[5];
iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_1] + iVal[5];
rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_1] + rVal[6];
iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_1] + iVal[6];
rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_1] + rVal[7];
iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_1] + iVal[7];
#endif
}
if((threadIdx.x & STRIDE_STAGE_2) == STRIDE_STAGE_2)
{
//calculate Q twiddle factor
float Q = (float)((threadIdx.x & STRIDE_STAGE_1)>>1);
Q = Q*NEG_2PI_BY_TLEN;
float c, s, T;
__sincosf(Q, &s, &c);
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
T = rVal[I];
rVal[I] = rVal[I]*c - iVal[I]*s;
iVal[I] = T*s + iVal[I]*c;
}
}
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][threadIdx.x] = rVal[I];
shImg[I][threadIdx.x] = iVal[I];
}
__syncthreads();
//stage 2
if((threadIdx.x & STRIDE_STAGE_2) == STRIDE_STAGE_2)
{
rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_2] - rVal[0];
iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_2] - iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_2] - rVal[1];
iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_2] - iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_2] - rVal[2];
iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_2] - iVal[2];
rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_2] - rVal[3];
iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_2] - iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_2] - rVal[4];
iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_2] - iVal[4];
rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_2] - rVal[5];
iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_2] - iVal[5];
rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_2] - rVal[6];
iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_2] - iVal[6];
rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_2] - rVal[7];
iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_2] - iVal[7];
#endif
}
else
{
rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_2] + rVal[0];
iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_2] + iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_2] + rVal[1];
iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_2] + iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_2] + rVal[2];
iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_2] + iVal[2];
rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_2] + rVal[3];
iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_2] + iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_2] + rVal[4];
iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_2] + iVal[4];
rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_2] + rVal[5];
iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_2] + iVal[5];
rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_2] + rVal[6];
iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_2] + iVal[6];
rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_2] + rVal[7];
iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_2] + iVal[7];
#endif
}
//end of stage 2
//multiply with twiddle for beginning of stage 3
//STRIDE_STAGE_3 16
if((threadIdx.x & STRIDE_STAGE_3) == STRIDE_STAGE_3)
{
//calculate Q twiddle factor
float Q = (float)((threadIdx.x & STRIDE_STAGE_2) | ((threadIdx.x & STRIDE_STAGE_1)>>2));
Q = Q*NEG_2PI_BY_TLEN;
float c, s, T;
__sincosf(Q, &s, &c);
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
T = rVal[I];
rVal[I] = rVal[I]*c - iVal[I]*s;
iVal[I] = T*s + iVal[I]*c;
}
}
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][threadIdx.x] = rVal[I];
shImg[I][threadIdx.x] = iVal[I];
}
__syncthreads();
//stage3
if((threadIdx.x & STRIDE_STAGE_3) == STRIDE_STAGE_3)
{
rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_3] - rVal[0];
iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_3] - iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_3] - rVal[1];
iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_3] - iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_3] - rVal[2];
iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_3] - iVal[2];
rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_3] - rVal[3];
iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_3] - iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_3] - rVal[4];
iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_3] - iVal[4];
rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_3] - rVal[5];
iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_3] - iVal[5];
rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_3] - rVal[6];
iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_3] - iVal[6];
rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_3] - rVal[7];
iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_3] - iVal[7];
#endif
}
else
{
rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_3] + rVal[0];
iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_3] + iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_3] + rVal[1];
iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_3] + iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_3] + rVal[2];
iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_3] + iVal[2];
rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_3] + rVal[3];
iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_3] + iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_3] + rVal[4];
iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_3] + iVal[4];
rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_3] + rVal[5];
iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_3] + iVal[5];
rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_3] + rVal[6];
iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_3] + iVal[6];
rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_3] + rVal[7];
iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_3] + iVal[7];
#endif
}
//end of stage 3
//multiply with twiddle for beginning of stage 4
//STRIDE_STAGE_4 8
if((threadIdx.x & STRIDE_STAGE_4) == STRIDE_STAGE_4)
{
//calculate Q twiddle factor
float Q = (float)(((threadIdx.x & STRIDE_STAGE_1)>>3) |
((threadIdx.x & STRIDE_STAGE_2)>>1) | ((threadIdx.x & STRIDE_STAGE_3)<<1));
Q = Q*NEG_2PI_BY_TLEN;
float c, s, T;
__sincosf(Q, &s, &c);
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
T = rVal[I];
rVal[I] = rVal[I]*c - iVal[I]*s;
iVal[I] = T*s + iVal[I]*c;
}
}
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][threadIdx.x] = rVal[I];
shImg[I][threadIdx.x] = iVal[I];
}
__syncthreads();
//stage 4
if((threadIdx.x & STRIDE_STAGE_4) == STRIDE_STAGE_4)
{
rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_4] - rVal[0];
iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_4] - iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_4] - rVal[1];
iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_4] - iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_4] - rVal[2];
iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_4] - iVal[2];
rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_4] - rVal[3];
iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_4] - iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_4] - rVal[4];
iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_4] - iVal[4];
rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_4] - rVal[5];
iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_4] - iVal[5];
rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_4] - rVal[6];
iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_4] - iVal[6];
rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_4] - rVal[7];
iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_4] - iVal[7];
#endif
}
else
{
rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_4] + rVal[0];
iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_4] + iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_4] + rVal[1];
iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_4] + iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_4] + rVal[2];
iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_4] + iVal[2];
rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_4] + rVal[3];
iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_4] + iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_4] + rVal[4];
iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_4] + iVal[4];
rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_4] + rVal[5];
iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_4] + iVal[5];
rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_4] + rVal[6];
iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_4] + iVal[6];
rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_4] + rVal[7];
iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_4] + iVal[7];
#endif
}
//end of stage 4
//multiply with twiddle for beginning of stage 5
//STRIDE_STAGE_5 4
if((threadIdx.x & STRIDE_STAGE_5) == STRIDE_STAGE_5)
{
//calculate Q twiddle factor
int q = ((threadIdx.x & M12)>>4) | (threadIdx.x & M34);
q = (q & M35) | ((q & M46)<<2);
float Q = q*NEG_2PI_BY_TLEN;
float c, s, T;
__sincosf(Q, &s, &c);
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
T = rVal[I];
rVal[I] = rVal[I]*c - iVal[I]*s;
iVal[I] = T*s + iVal[I]*c;
}
}
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][threadIdx.x] = rVal[I];
shImg[I][threadIdx.x] = iVal[I];
}
__syncthreads();
//stage 5
if((threadIdx.x & STRIDE_STAGE_5) == STRIDE_STAGE_5)
{
rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_5] - rVal[0];
iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_5] - iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_5] - rVal[1];
iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_5] - iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_5] - rVal[2];
iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_5] - iVal[2];
rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_5] - rVal[3];
iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_5] - iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_5] - rVal[4];
iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_5] - iVal[4];
rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_5] - rVal[5];
iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_5] - iVal[5];
rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_5] - rVal[6];
iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_5] - iVal[6];
rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_5] - rVal[7];
iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_5] - iVal[7];
#endif
}
else
{
rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_5] + rVal[0];
iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_5] + iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_5] + rVal[1];
iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_5] + iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_5] + rVal[2];
iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_5] + iVal[2];
rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_5] + rVal[3];
iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_5] + iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_5] + rVal[4];
iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_5] + iVal[4];
rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_5] + rVal[5];
iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_5] + iVal[5];
rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_5] + rVal[6];
iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_5] + iVal[6];
rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_5] + rVal[7];
iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_5] + iVal[7];
#endif
}
//end of stage 5
//multiply with twiddle for beginning of stage 6
//STRIDE_STAGE_6 2
if((threadIdx.x & STRIDE_STAGE_6) == STRIDE_STAGE_6)
{
//calculate Q twiddle factor
int q = ((threadIdx.x & M12)>>5) | ((threadIdx.x & M34)>>1) |
((threadIdx.x & M5)<<3);
q = (q & M246) | ((q & M357)<<2);
float Q = q*NEG_2PI_BY_TLEN;
float c, s, T;
__sincosf(Q, &s, &c);
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
T = rVal[I];
rVal[I] = rVal[I]*c - iVal[I]*s;
iVal[I] = T*s + iVal[I]*c;
}
}
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][threadIdx.x] = rVal[I];
shImg[I][threadIdx.x] = iVal[I];
}
__syncthreads();
//stage 6
if((threadIdx.x & STRIDE_STAGE_6) == STRIDE_STAGE_6)
{
rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_6] - rVal[0];
iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_6] - iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_6] - rVal[1];
iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_6] - iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_6] - rVal[2];
iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_6] - iVal[2];
rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_6] - rVal[3];
iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_6] - iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_6] - rVal[4];
iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_6] - iVal[4];
rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_6] - rVal[5];
iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_6] - iVal[5];
rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_6] - rVal[6];
iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_6] - iVal[6];
rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_6] - rVal[7];
iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_6] - iVal[7];
#endif
}
else
{
rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_6] + rVal[0];
iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_6] + iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_6] + rVal[1];
iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_6] + iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_6] + rVal[2];
iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_6] + iVal[2];
rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_6] + rVal[3];
iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_6] + iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_6] + rVal[4];
iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_6] + iVal[4];
rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_6] + rVal[5];
iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_6] + iVal[5];
rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_6] + rVal[6];
iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_6] + iVal[6];
rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_6] + rVal[7];
iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_6] + iVal[7];
#endif
}
//end of stage 6
//multiply with twiddle for beginning of stage 7
//STRIDE_STAGE_7 1
if((threadIdx.x & STRIDE_STAGE_7) == STRIDE_STAGE_7)
{
//calculate Q twiddle factor
int q = ((threadIdx.x & M12)>>4) | (threadIdx.x & M34) |
((threadIdx.x & M56)<<4);
q = ((q & M135)>>2) | (q & M246);
float Q = q*NEG_2PI_BY_TLEN;
float c, s, T;
__sincosf(Q, &s, &c);
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
T = rVal[I];
rVal[I] = rVal[I]*c - iVal[I]*s;
iVal[I] = T*s + iVal[I]*c;
}
}
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][threadIdx.x] = rVal[I];
shImg[I][threadIdx.x] = iVal[I];
}
__syncthreads();
//stage 7
if((threadIdx.x & STRIDE_STAGE_7) == STRIDE_STAGE_7)
{
rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_7] - rVal[0];
iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_7] - iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_7] - rVal[1];
iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_7] - iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_7] - rVal[2];
iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_7] - iVal[2];
rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_7] - rVal[3];
iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_7] - iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_7] - rVal[4];
iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_7] - iVal[4];
rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_7] - rVal[5];
iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_7] - iVal[5];
rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_7] - rVal[6];
iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_7] - iVal[6];
rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_7] - rVal[7];
iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_7] - iVal[7];
#endif
}
else
{
rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_7] + rVal[0];
iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_7] + iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_7] + rVal[1];
iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_7] + iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_7] + rVal[2];
iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_7] + iVal[2];
rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_7] + rVal[3];
iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_7] + iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_7] + rVal[4];
iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_7] + iVal[4];
rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_7] + rVal[5];
iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_7] + iVal[5];
rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_7] + rVal[6];
iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_7] + iVal[6];
rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_7] + rVal[7];
iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_7] + iVal[7];
#endif
}
int revtid = bitreverse(threadIdx.x);
/*
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][revtid] = rVal[I];
shImg[I][revtid] = iVal[I];
}
*/
shReal[0][revtid] = rVal[0];
shImg[0][revtid] = iVal[0];
#if HEIGHT > 1
shReal[1][revtid] = rVal[1];
shImg[1][revtid] = iVal[1];
#endif
#if HEIGHT > 2
shReal[2][revtid] = rVal[2];
shImg[2][revtid] = iVal[2];
shReal[3][revtid] = rVal[3];
shImg[3][revtid] = iVal[3];
#endif
#if HEIGHT > 4
shReal[4][revtid] = rVal[4];
shImg[4][revtid] = iVal[4];
shReal[5][revtid] = rVal[5];
shImg[5][revtid] = iVal[5];
shReal[6][revtid] = rVal[6];
shImg[6][revtid] = iVal[6];
shReal[7][revtid] = rVal[7];
shImg[7][revtid] = iVal[7];
#endif
__syncthreads();
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
real[((blockIdx.x*HEIGHT) + I)*blockDim.x + threadIdx.x] = shReal[I][threadIdx.x];
img[((blockIdx.x*HEIGHT) + I)*blockDim.x + threadIdx.x] = shImg[I][threadIdx.x];
}
}
__global__ void transposeDiagonal_xy(float *odatar, float *odatai, float *idatar, float *idatai, int width)
{
__shared__ float tile[TILE_DIM][TILE_DIM+1];
int blockIdx_x, blockIdx_y;
// do diagonal reordering
blockIdx_y = blockIdx.x;
blockIdx_x = (blockIdx.x+blockIdx.y)%gridDim.x;
// from here on the code is same as previous kernel except blockIdx_x replaces blockIdx.x
// and similarly for y
int xIndex = blockIdx_x * TILE_DIM + threadIdx.x;
int yIndex = blockIdx_y * TILE_DIM + threadIdx.y;
int index_in = xIndex + (yIndex + blockIdx.z*width)*width;
xIndex = blockIdx_y * TILE_DIM + threadIdx.x;
yIndex = blockIdx_x * TILE_DIM + threadIdx.y;
int index_out = xIndex + (yIndex + blockIdx.z*width)*width;
tile[threadIdx.y][threadIdx.x] = idatar[index_in];
__syncthreads();
odatar[index_out] = tile[threadIdx.x][threadIdx.y];
__syncthreads();
tile[threadIdx.y][threadIdx.x] = idatai[index_in];
__syncthreads();
odatai[index_out] = tile[threadIdx.x][threadIdx.y];
}
__global__ void transposeDiagonal_xz(float *odatar, float *odatai, float *idatar, float *idatai, int width)
{
__shared__ float tile[TILE_DIM][TILE_DIM+1];
int blockIdx_x, blockIdx_z;
// do diagonal reordering
blockIdx_z = blockIdx.x;
blockIdx_x = (blockIdx.x+blockIdx.z)%gridDim.x;
// from here on the code is same as previous kernel except blockIdx_x replaces blockIdx.x
// and similarly for y
int xIndex = blockIdx_x * TILE_DIM + threadIdx.x;
int zIndex = blockIdx_z * TILE_DIM + threadIdx.z;
int index_in = xIndex + (blockIdx.y + zIndex*width)*width;
xIndex = blockIdx_z * TILE_DIM + threadIdx.x;
zIndex = blockIdx_x * TILE_DIM + threadIdx.z;
int index_out = xIndex + (blockIdx.y + zIndex*width)*width;
tile[threadIdx.z][threadIdx.x] = idatar[index_in];
__syncthreads();
odatar[index_out] = tile[threadIdx.x][threadIdx.z];
__syncthreads();
tile[threadIdx.z][threadIdx.x] = idatai[index_in];
__syncthreads();
odatai[index_out] = tile[threadIdx.x][threadIdx.z];
}
__global__ void transposeDiagonal_xy(float *odata, float *idata, int width)
{
__shared__ float tile[TILE_DIM][TILE_DIM+1];
int blockIdx_x, blockIdx_y;
// do diagonal reordering
blockIdx_y = blockIdx.x;
blockIdx_x = (blockIdx.x+blockIdx.y)%gridDim.x;
// from here on the code is same as previous kernel except blockIdx_x replaces blockIdx.x
// and similarly for y
int xIndex = blockIdx_x * TILE_DIM + threadIdx.x;
int yIndex = blockIdx_y * TILE_DIM + threadIdx.y;
int index_in = xIndex + (yIndex + blockIdx.z*width)*width;
xIndex = blockIdx_y * TILE_DIM + threadIdx.x;
yIndex = blockIdx_x * TILE_DIM + threadIdx.y;
int index_out = xIndex + (yIndex + blockIdx.z*width)*width;
tile[threadIdx.y][threadIdx.x] = idata[index_in];
__syncthreads();
odata[index_out] = tile[threadIdx.x][threadIdx.y];
}
__global__ void transposeDiagonal_xz(float *odata, float *idata, int width)
{
__shared__ float tile[TILE_DIM][TILE_DIM+1];
int blockIdx_x, blockIdx_z;
// do diagonal reordering
blockIdx_z = blockIdx.x;
blockIdx_x = (blockIdx.x+blockIdx.z)%gridDim.x;
// from here on the code is same as previous kernel except blockIdx_x replaces blockIdx.x
// and similarly for y
int xIndex = blockIdx_x * TILE_DIM + threadIdx.x;
int zIndex = blockIdx_z * TILE_DIM + threadIdx.z;
int index_in = xIndex + (blockIdx.y + zIndex*width)*width;
xIndex = blockIdx_z * TILE_DIM + threadIdx.x;
zIndex = blockIdx_x * TILE_DIM + threadIdx.z;
int index_out = xIndex + (blockIdx.y + zIndex*width)*width;
tile[threadIdx.z][threadIdx.x] = idata[index_in];
__syncthreads();
odata[index_out] = tile[threadIdx.x][threadIdx.z];
} | #include <hip/hip_runtime.h>
//transform length
#define TLEN 128
#define TILE_DIM 16
#define HEIGHT 8 //1, 2, 4, 8
#define NEG_2PI_BY_TLEN -0.04908738521f //-2*PI/128
#define STRIDE_STAGE_1 0x00000040 //64
#define STRIDE_STAGE_2 0x00000020 //32
#define STRIDE_STAGE_3 0x00000010 //16
#define STRIDE_STAGE_4 0x00000008 //08
#define STRIDE_STAGE_5 0x00000004 //04
#define STRIDE_STAGE_6 0x00000002 //02
#define STRIDE_STAGE_7 0x00000001 //01
#define M12 0x60
#define M34 0x18
#define M35 0x14
#define M46 0x0a
#define M246 0x2a
#define M135 0x54
#define M357 0x15
#define M56 0x06
#define M5 0x04
__device__ int bitreverse(int tid)
{
int revtid = tid;
revtid = ((0xf0f0f0f0 & revtid) >> 4) | ((0x0f0f0f0f & revtid) << 4);
revtid = ((0xcccccccc & revtid) >> 2) | ((0x33333333 & revtid) << 2);
revtid = ((0xaaaaaaaa & revtid) >> 2) | ((0x55555555 & revtid));
return revtid;
}
__global__ void FFT1D(float *real, float *img)
{
float rVal[HEIGHT], iVal[HEIGHT];
//assuming that thread block size is 128
__shared__ float shReal[HEIGHT][TLEN];
__shared__ float shImg[HEIGHT][TLEN];
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
rVal[I] = real[((blockIdx.x*HEIGHT) + I)*blockDim.x + threadIdx.x];
iVal[I] = img[((blockIdx.x*HEIGHT) + I)*blockDim.x + threadIdx.x];
}
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][threadIdx.x] = rVal[I];
shImg[I][threadIdx.x] = iVal[I];
}
__syncthreads();
if((threadIdx.x & STRIDE_STAGE_1) == STRIDE_STAGE_1)
{
rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_1] - rVal[0];
iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_1] - iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_1] - rVal[1];
iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_1] - iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_1] - rVal[2];
iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_1] - iVal[2];
rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_1] - rVal[3];
iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_1] - iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_1] - rVal[4];
iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_1] - iVal[4];
rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_1] - rVal[5];
iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_1] - iVal[5];
rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_1] - rVal[6];
iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_1] - iVal[6];
rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_1] - rVal[7];
iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_1] - iVal[7];
#endif
}
else
{
rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_1] + rVal[0];
iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_1] + iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_1] + rVal[1];
iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_1] + iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_1] + rVal[2];
iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_1] + iVal[2];
rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_1] + rVal[3];
iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_1] + iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_1] + rVal[4];
iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_1] + iVal[4];
rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_1] + rVal[5];
iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_1] + iVal[5];
rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_1] + rVal[6];
iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_1] + iVal[6];
rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_1] + rVal[7];
iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_1] + iVal[7];
#endif
}
if((threadIdx.x & STRIDE_STAGE_2) == STRIDE_STAGE_2)
{
//calculate Q twiddle factor
float Q = (float)((threadIdx.x & STRIDE_STAGE_1)>>1);
Q = Q*NEG_2PI_BY_TLEN;
float c, s, T;
__sincosf(Q, &s, &c);
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
T = rVal[I];
rVal[I] = rVal[I]*c - iVal[I]*s;
iVal[I] = T*s + iVal[I]*c;
}
}
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][threadIdx.x] = rVal[I];
shImg[I][threadIdx.x] = iVal[I];
}
__syncthreads();
//stage 2
if((threadIdx.x & STRIDE_STAGE_2) == STRIDE_STAGE_2)
{
rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_2] - rVal[0];
iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_2] - iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_2] - rVal[1];
iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_2] - iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_2] - rVal[2];
iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_2] - iVal[2];
rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_2] - rVal[3];
iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_2] - iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_2] - rVal[4];
iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_2] - iVal[4];
rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_2] - rVal[5];
iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_2] - iVal[5];
rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_2] - rVal[6];
iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_2] - iVal[6];
rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_2] - rVal[7];
iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_2] - iVal[7];
#endif
}
else
{
rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_2] + rVal[0];
iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_2] + iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_2] + rVal[1];
iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_2] + iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_2] + rVal[2];
iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_2] + iVal[2];
rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_2] + rVal[3];
iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_2] + iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_2] + rVal[4];
iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_2] + iVal[4];
rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_2] + rVal[5];
iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_2] + iVal[5];
rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_2] + rVal[6];
iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_2] + iVal[6];
rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_2] + rVal[7];
iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_2] + iVal[7];
#endif
}
//end of stage 2
//multiply with twiddle for beginning of stage 3
//STRIDE_STAGE_3 16
if((threadIdx.x & STRIDE_STAGE_3) == STRIDE_STAGE_3)
{
//calculate Q twiddle factor
float Q = (float)((threadIdx.x & STRIDE_STAGE_2) | ((threadIdx.x & STRIDE_STAGE_1)>>2));
Q = Q*NEG_2PI_BY_TLEN;
float c, s, T;
__sincosf(Q, &s, &c);
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
T = rVal[I];
rVal[I] = rVal[I]*c - iVal[I]*s;
iVal[I] = T*s + iVal[I]*c;
}
}
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][threadIdx.x] = rVal[I];
shImg[I][threadIdx.x] = iVal[I];
}
__syncthreads();
//stage3
if((threadIdx.x & STRIDE_STAGE_3) == STRIDE_STAGE_3)
{
rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_3] - rVal[0];
iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_3] - iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_3] - rVal[1];
iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_3] - iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_3] - rVal[2];
iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_3] - iVal[2];
rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_3] - rVal[3];
iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_3] - iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_3] - rVal[4];
iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_3] - iVal[4];
rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_3] - rVal[5];
iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_3] - iVal[5];
rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_3] - rVal[6];
iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_3] - iVal[6];
rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_3] - rVal[7];
iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_3] - iVal[7];
#endif
}
else
{
rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_3] + rVal[0];
iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_3] + iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_3] + rVal[1];
iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_3] + iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_3] + rVal[2];
iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_3] + iVal[2];
rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_3] + rVal[3];
iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_3] + iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_3] + rVal[4];
iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_3] + iVal[4];
rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_3] + rVal[5];
iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_3] + iVal[5];
rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_3] + rVal[6];
iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_3] + iVal[6];
rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_3] + rVal[7];
iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_3] + iVal[7];
#endif
}
//end of stage 3
//multiply with twiddle for beginning of stage 4
//STRIDE_STAGE_4 8
if((threadIdx.x & STRIDE_STAGE_4) == STRIDE_STAGE_4)
{
//calculate Q twiddle factor
float Q = (float)(((threadIdx.x & STRIDE_STAGE_1)>>3) |
((threadIdx.x & STRIDE_STAGE_2)>>1) | ((threadIdx.x & STRIDE_STAGE_3)<<1));
Q = Q*NEG_2PI_BY_TLEN;
float c, s, T;
__sincosf(Q, &s, &c);
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
T = rVal[I];
rVal[I] = rVal[I]*c - iVal[I]*s;
iVal[I] = T*s + iVal[I]*c;
}
}
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][threadIdx.x] = rVal[I];
shImg[I][threadIdx.x] = iVal[I];
}
__syncthreads();
//stage 4
if((threadIdx.x & STRIDE_STAGE_4) == STRIDE_STAGE_4)
{
rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_4] - rVal[0];
iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_4] - iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_4] - rVal[1];
iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_4] - iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_4] - rVal[2];
iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_4] - iVal[2];
rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_4] - rVal[3];
iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_4] - iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_4] - rVal[4];
iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_4] - iVal[4];
rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_4] - rVal[5];
iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_4] - iVal[5];
rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_4] - rVal[6];
iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_4] - iVal[6];
rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_4] - rVal[7];
iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_4] - iVal[7];
#endif
}
else
{
rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_4] + rVal[0];
iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_4] + iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_4] + rVal[1];
iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_4] + iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_4] + rVal[2];
iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_4] + iVal[2];
rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_4] + rVal[3];
iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_4] + iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_4] + rVal[4];
iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_4] + iVal[4];
rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_4] + rVal[5];
iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_4] + iVal[5];
rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_4] + rVal[6];
iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_4] + iVal[6];
rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_4] + rVal[7];
iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_4] + iVal[7];
#endif
}
//end of stage 4
//multiply with twiddle for beginning of stage 5
//STRIDE_STAGE_5 4
if((threadIdx.x & STRIDE_STAGE_5) == STRIDE_STAGE_5)
{
//calculate Q twiddle factor
int q = ((threadIdx.x & M12)>>4) | (threadIdx.x & M34);
q = (q & M35) | ((q & M46)<<2);
float Q = q*NEG_2PI_BY_TLEN;
float c, s, T;
__sincosf(Q, &s, &c);
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
T = rVal[I];
rVal[I] = rVal[I]*c - iVal[I]*s;
iVal[I] = T*s + iVal[I]*c;
}
}
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][threadIdx.x] = rVal[I];
shImg[I][threadIdx.x] = iVal[I];
}
__syncthreads();
//stage 5
if((threadIdx.x & STRIDE_STAGE_5) == STRIDE_STAGE_5)
{
rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_5] - rVal[0];
iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_5] - iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_5] - rVal[1];
iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_5] - iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_5] - rVal[2];
iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_5] - iVal[2];
rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_5] - rVal[3];
iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_5] - iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_5] - rVal[4];
iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_5] - iVal[4];
rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_5] - rVal[5];
iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_5] - iVal[5];
rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_5] - rVal[6];
iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_5] - iVal[6];
rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_5] - rVal[7];
iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_5] - iVal[7];
#endif
}
else
{
rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_5] + rVal[0];
iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_5] + iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_5] + rVal[1];
iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_5] + iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_5] + rVal[2];
iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_5] + iVal[2];
rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_5] + rVal[3];
iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_5] + iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_5] + rVal[4];
iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_5] + iVal[4];
rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_5] + rVal[5];
iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_5] + iVal[5];
rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_5] + rVal[6];
iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_5] + iVal[6];
rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_5] + rVal[7];
iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_5] + iVal[7];
#endif
}
//end of stage 5
//multiply with twiddle for beginning of stage 6
//STRIDE_STAGE_6 2
if((threadIdx.x & STRIDE_STAGE_6) == STRIDE_STAGE_6)
{
//calculate Q twiddle factor
int q = ((threadIdx.x & M12)>>5) | ((threadIdx.x & M34)>>1) |
((threadIdx.x & M5)<<3);
q = (q & M246) | ((q & M357)<<2);
float Q = q*NEG_2PI_BY_TLEN;
float c, s, T;
__sincosf(Q, &s, &c);
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
T = rVal[I];
rVal[I] = rVal[I]*c - iVal[I]*s;
iVal[I] = T*s + iVal[I]*c;
}
}
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][threadIdx.x] = rVal[I];
shImg[I][threadIdx.x] = iVal[I];
}
__syncthreads();
//stage 6
if((threadIdx.x & STRIDE_STAGE_6) == STRIDE_STAGE_6)
{
rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_6] - rVal[0];
iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_6] - iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_6] - rVal[1];
iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_6] - iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_6] - rVal[2];
iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_6] - iVal[2];
rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_6] - rVal[3];
iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_6] - iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_6] - rVal[4];
iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_6] - iVal[4];
rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_6] - rVal[5];
iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_6] - iVal[5];
rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_6] - rVal[6];
iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_6] - iVal[6];
rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_6] - rVal[7];
iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_6] - iVal[7];
#endif
}
else
{
rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_6] + rVal[0];
iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_6] + iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_6] + rVal[1];
iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_6] + iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_6] + rVal[2];
iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_6] + iVal[2];
rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_6] + rVal[3];
iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_6] + iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_6] + rVal[4];
iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_6] + iVal[4];
rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_6] + rVal[5];
iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_6] + iVal[5];
rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_6] + rVal[6];
iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_6] + iVal[6];
rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_6] + rVal[7];
iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_6] + iVal[7];
#endif
}
//end of stage 6
//multiply with twiddle for beginning of stage 7
//STRIDE_STAGE_7 1
if((threadIdx.x & STRIDE_STAGE_7) == STRIDE_STAGE_7)
{
//calculate Q twiddle factor
int q = ((threadIdx.x & M12)>>4) | (threadIdx.x & M34) |
((threadIdx.x & M56)<<4);
q = ((q & M135)>>2) | (q & M246);
float Q = q*NEG_2PI_BY_TLEN;
float c, s, T;
__sincosf(Q, &s, &c);
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
T = rVal[I];
rVal[I] = rVal[I]*c - iVal[I]*s;
iVal[I] = T*s + iVal[I]*c;
}
}
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][threadIdx.x] = rVal[I];
shImg[I][threadIdx.x] = iVal[I];
}
__syncthreads();
//stage 7
if((threadIdx.x & STRIDE_STAGE_7) == STRIDE_STAGE_7)
{
rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_7] - rVal[0];
iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_7] - iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_7] - rVal[1];
iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_7] - iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_7] - rVal[2];
iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_7] - iVal[2];
rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_7] - rVal[3];
iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_7] - iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_7] - rVal[4];
iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_7] - iVal[4];
rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_7] - rVal[5];
iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_7] - iVal[5];
rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_7] - rVal[6];
iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_7] - iVal[6];
rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_7] - rVal[7];
iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_7] - iVal[7];
#endif
}
else
{
rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_7] + rVal[0];
iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_7] + iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_7] + rVal[1];
iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_7] + iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_7] + rVal[2];
iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_7] + iVal[2];
rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_7] + rVal[3];
iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_7] + iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_7] + rVal[4];
iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_7] + iVal[4];
rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_7] + rVal[5];
iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_7] + iVal[5];
rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_7] + rVal[6];
iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_7] + iVal[6];
rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_7] + rVal[7];
iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_7] + iVal[7];
#endif
}
int revtid = bitreverse(threadIdx.x);
/*
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][revtid] = rVal[I];
shImg[I][revtid] = iVal[I];
}
*/
shReal[0][revtid] = rVal[0];
shImg[0][revtid] = iVal[0];
#if HEIGHT > 1
shReal[1][revtid] = rVal[1];
shImg[1][revtid] = iVal[1];
#endif
#if HEIGHT > 2
shReal[2][revtid] = rVal[2];
shImg[2][revtid] = iVal[2];
shReal[3][revtid] = rVal[3];
shImg[3][revtid] = iVal[3];
#endif
#if HEIGHT > 4
shReal[4][revtid] = rVal[4];
shImg[4][revtid] = iVal[4];
shReal[5][revtid] = rVal[5];
shImg[5][revtid] = iVal[5];
shReal[6][revtid] = rVal[6];
shImg[6][revtid] = iVal[6];
shReal[7][revtid] = rVal[7];
shImg[7][revtid] = iVal[7];
#endif
__syncthreads();
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
real[((blockIdx.x*HEIGHT) + I)*blockDim.x + threadIdx.x] = shReal[I][threadIdx.x];
img[((blockIdx.x*HEIGHT) + I)*blockDim.x + threadIdx.x] = shImg[I][threadIdx.x];
}
}
__global__ void transposeDiagonal_xy(float *odatar, float *odatai, float *idatar, float *idatai, int width)
{
__shared__ float tile[TILE_DIM][TILE_DIM+1];
int blockIdx_x, blockIdx_y;
// do diagonal reordering
blockIdx_y = blockIdx.x;
blockIdx_x = (blockIdx.x+blockIdx.y)%gridDim.x;
// from here on the code is same as previous kernel except blockIdx_x replaces blockIdx.x
// and similarly for y
int xIndex = blockIdx_x * TILE_DIM + threadIdx.x;
int yIndex = blockIdx_y * TILE_DIM + threadIdx.y;
int index_in = xIndex + (yIndex + blockIdx.z*width)*width;
xIndex = blockIdx_y * TILE_DIM + threadIdx.x;
yIndex = blockIdx_x * TILE_DIM + threadIdx.y;
int index_out = xIndex + (yIndex + blockIdx.z*width)*width;
tile[threadIdx.y][threadIdx.x] = idatar[index_in];
__syncthreads();
odatar[index_out] = tile[threadIdx.x][threadIdx.y];
__syncthreads();
tile[threadIdx.y][threadIdx.x] = idatai[index_in];
__syncthreads();
odatai[index_out] = tile[threadIdx.x][threadIdx.y];
}
__global__ void transposeDiagonal_xz(float *odatar, float *odatai, float *idatar, float *idatai, int width)
{
__shared__ float tile[TILE_DIM][TILE_DIM+1];
int blockIdx_x, blockIdx_z;
// do diagonal reordering
blockIdx_z = blockIdx.x;
blockIdx_x = (blockIdx.x+blockIdx.z)%gridDim.x;
// from here on the code is same as previous kernel except blockIdx_x replaces blockIdx.x
// and similarly for y
int xIndex = blockIdx_x * TILE_DIM + threadIdx.x;
int zIndex = blockIdx_z * TILE_DIM + threadIdx.z;
int index_in = xIndex + (blockIdx.y + zIndex*width)*width;
xIndex = blockIdx_z * TILE_DIM + threadIdx.x;
zIndex = blockIdx_x * TILE_DIM + threadIdx.z;
int index_out = xIndex + (blockIdx.y + zIndex*width)*width;
tile[threadIdx.z][threadIdx.x] = idatar[index_in];
__syncthreads();
odatar[index_out] = tile[threadIdx.x][threadIdx.z];
__syncthreads();
tile[threadIdx.z][threadIdx.x] = idatai[index_in];
__syncthreads();
odatai[index_out] = tile[threadIdx.x][threadIdx.z];
}
__global__ void transposeDiagonal_xy(float *odata, float *idata, int width)
{
__shared__ float tile[TILE_DIM][TILE_DIM+1];
int blockIdx_x, blockIdx_y;
// do diagonal reordering
blockIdx_y = blockIdx.x;
blockIdx_x = (blockIdx.x+blockIdx.y)%gridDim.x;
// from here on the code is same as previous kernel except blockIdx_x replaces blockIdx.x
// and similarly for y
int xIndex = blockIdx_x * TILE_DIM + threadIdx.x;
int yIndex = blockIdx_y * TILE_DIM + threadIdx.y;
int index_in = xIndex + (yIndex + blockIdx.z*width)*width;
xIndex = blockIdx_y * TILE_DIM + threadIdx.x;
yIndex = blockIdx_x * TILE_DIM + threadIdx.y;
int index_out = xIndex + (yIndex + blockIdx.z*width)*width;
tile[threadIdx.y][threadIdx.x] = idata[index_in];
__syncthreads();
odata[index_out] = tile[threadIdx.x][threadIdx.y];
}
__global__ void transposeDiagonal_xz(float *odata, float *idata, int width)
{
__shared__ float tile[TILE_DIM][TILE_DIM+1];
int blockIdx_x, blockIdx_z;
// do diagonal reordering
blockIdx_z = blockIdx.x;
blockIdx_x = (blockIdx.x+blockIdx.z)%gridDim.x;
// from here on the code is same as previous kernel except blockIdx_x replaces blockIdx.x
// and similarly for y
int xIndex = blockIdx_x * TILE_DIM + threadIdx.x;
int zIndex = blockIdx_z * TILE_DIM + threadIdx.z;
int index_in = xIndex + (blockIdx.y + zIndex*width)*width;
xIndex = blockIdx_z * TILE_DIM + threadIdx.x;
zIndex = blockIdx_x * TILE_DIM + threadIdx.z;
int index_out = xIndex + (blockIdx.y + zIndex*width)*width;
tile[threadIdx.z][threadIdx.x] = idata[index_in];
__syncthreads();
odata[index_out] = tile[threadIdx.x][threadIdx.z];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//transform length
#define TLEN 128
#define TILE_DIM 16
#define HEIGHT 8 //1, 2, 4, 8
#define NEG_2PI_BY_TLEN -0.04908738521f //-2*PI/128
#define STRIDE_STAGE_1 0x00000040 //64
#define STRIDE_STAGE_2 0x00000020 //32
#define STRIDE_STAGE_3 0x00000010 //16
#define STRIDE_STAGE_4 0x00000008 //08
#define STRIDE_STAGE_5 0x00000004 //04
#define STRIDE_STAGE_6 0x00000002 //02
#define STRIDE_STAGE_7 0x00000001 //01
#define M12 0x60
#define M34 0x18
#define M35 0x14
#define M46 0x0a
#define M246 0x2a
#define M135 0x54
#define M357 0x15
#define M56 0x06
#define M5 0x04
__device__ int bitreverse(int tid)
{
int revtid = tid;
revtid = ((0xf0f0f0f0 & revtid) >> 4) | ((0x0f0f0f0f & revtid) << 4);
revtid = ((0xcccccccc & revtid) >> 2) | ((0x33333333 & revtid) << 2);
revtid = ((0xaaaaaaaa & revtid) >> 2) | ((0x55555555 & revtid));
return revtid;
}
__global__ void FFT1D(float *real, float *img)
{
float rVal[HEIGHT], iVal[HEIGHT];
//assuming that thread block size is 128
__shared__ float shReal[HEIGHT][TLEN];
__shared__ float shImg[HEIGHT][TLEN];
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
rVal[I] = real[((blockIdx.x*HEIGHT) + I)*blockDim.x + threadIdx.x];
iVal[I] = img[((blockIdx.x*HEIGHT) + I)*blockDim.x + threadIdx.x];
}
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][threadIdx.x] = rVal[I];
shImg[I][threadIdx.x] = iVal[I];
}
__syncthreads();
if((threadIdx.x & STRIDE_STAGE_1) == STRIDE_STAGE_1)
{
rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_1] - rVal[0];
iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_1] - iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_1] - rVal[1];
iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_1] - iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_1] - rVal[2];
iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_1] - iVal[2];
rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_1] - rVal[3];
iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_1] - iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_1] - rVal[4];
iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_1] - iVal[4];
rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_1] - rVal[5];
iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_1] - iVal[5];
rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_1] - rVal[6];
iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_1] - iVal[6];
rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_1] - rVal[7];
iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_1] - iVal[7];
#endif
}
else
{
rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_1] + rVal[0];
iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_1] + iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_1] + rVal[1];
iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_1] + iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_1] + rVal[2];
iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_1] + iVal[2];
rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_1] + rVal[3];
iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_1] + iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_1] + rVal[4];
iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_1] + iVal[4];
rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_1] + rVal[5];
iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_1] + iVal[5];
rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_1] + rVal[6];
iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_1] + iVal[6];
rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_1] + rVal[7];
iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_1] + iVal[7];
#endif
}
if((threadIdx.x & STRIDE_STAGE_2) == STRIDE_STAGE_2)
{
//calculate Q twiddle factor
float Q = (float)((threadIdx.x & STRIDE_STAGE_1)>>1);
Q = Q*NEG_2PI_BY_TLEN;
float c, s, T;
__sincosf(Q, &s, &c);
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
T = rVal[I];
rVal[I] = rVal[I]*c - iVal[I]*s;
iVal[I] = T*s + iVal[I]*c;
}
}
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][threadIdx.x] = rVal[I];
shImg[I][threadIdx.x] = iVal[I];
}
__syncthreads();
//stage 2
if((threadIdx.x & STRIDE_STAGE_2) == STRIDE_STAGE_2)
{
rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_2] - rVal[0];
iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_2] - iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_2] - rVal[1];
iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_2] - iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_2] - rVal[2];
iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_2] - iVal[2];
rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_2] - rVal[3];
iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_2] - iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_2] - rVal[4];
iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_2] - iVal[4];
rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_2] - rVal[5];
iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_2] - iVal[5];
rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_2] - rVal[6];
iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_2] - iVal[6];
rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_2] - rVal[7];
iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_2] - iVal[7];
#endif
}
else
{
rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_2] + rVal[0];
iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_2] + iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_2] + rVal[1];
iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_2] + iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_2] + rVal[2];
iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_2] + iVal[2];
rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_2] + rVal[3];
iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_2] + iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_2] + rVal[4];
iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_2] + iVal[4];
rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_2] + rVal[5];
iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_2] + iVal[5];
rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_2] + rVal[6];
iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_2] + iVal[6];
rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_2] + rVal[7];
iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_2] + iVal[7];
#endif
}
//end of stage 2
//multiply with twiddle for beginning of stage 3
//STRIDE_STAGE_3 16
if((threadIdx.x & STRIDE_STAGE_3) == STRIDE_STAGE_3)
{
//calculate Q twiddle factor
float Q = (float)((threadIdx.x & STRIDE_STAGE_2) | ((threadIdx.x & STRIDE_STAGE_1)>>2));
Q = Q*NEG_2PI_BY_TLEN;
float c, s, T;
__sincosf(Q, &s, &c);
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
T = rVal[I];
rVal[I] = rVal[I]*c - iVal[I]*s;
iVal[I] = T*s + iVal[I]*c;
}
}
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][threadIdx.x] = rVal[I];
shImg[I][threadIdx.x] = iVal[I];
}
__syncthreads();
//stage3
if((threadIdx.x & STRIDE_STAGE_3) == STRIDE_STAGE_3)
{
rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_3] - rVal[0];
iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_3] - iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_3] - rVal[1];
iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_3] - iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_3] - rVal[2];
iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_3] - iVal[2];
rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_3] - rVal[3];
iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_3] - iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_3] - rVal[4];
iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_3] - iVal[4];
rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_3] - rVal[5];
iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_3] - iVal[5];
rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_3] - rVal[6];
iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_3] - iVal[6];
rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_3] - rVal[7];
iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_3] - iVal[7];
#endif
}
else
{
rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_3] + rVal[0];
iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_3] + iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_3] + rVal[1];
iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_3] + iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_3] + rVal[2];
iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_3] + iVal[2];
rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_3] + rVal[3];
iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_3] + iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_3] + rVal[4];
iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_3] + iVal[4];
rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_3] + rVal[5];
iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_3] + iVal[5];
rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_3] + rVal[6];
iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_3] + iVal[6];
rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_3] + rVal[7];
iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_3] + iVal[7];
#endif
}
//end of stage 3
//multiply with twiddle for beginning of stage 4
//STRIDE_STAGE_4 8
if((threadIdx.x & STRIDE_STAGE_4) == STRIDE_STAGE_4)
{
//calculate Q twiddle factor
float Q = (float)(((threadIdx.x & STRIDE_STAGE_1)>>3) |
((threadIdx.x & STRIDE_STAGE_2)>>1) | ((threadIdx.x & STRIDE_STAGE_3)<<1));
Q = Q*NEG_2PI_BY_TLEN;
float c, s, T;
__sincosf(Q, &s, &c);
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
T = rVal[I];
rVal[I] = rVal[I]*c - iVal[I]*s;
iVal[I] = T*s + iVal[I]*c;
}
}
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][threadIdx.x] = rVal[I];
shImg[I][threadIdx.x] = iVal[I];
}
__syncthreads();
//stage 4
if((threadIdx.x & STRIDE_STAGE_4) == STRIDE_STAGE_4)
{
rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_4] - rVal[0];
iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_4] - iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_4] - rVal[1];
iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_4] - iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_4] - rVal[2];
iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_4] - iVal[2];
rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_4] - rVal[3];
iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_4] - iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_4] - rVal[4];
iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_4] - iVal[4];
rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_4] - rVal[5];
iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_4] - iVal[5];
rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_4] - rVal[6];
iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_4] - iVal[6];
rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_4] - rVal[7];
iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_4] - iVal[7];
#endif
}
else
{
rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_4] + rVal[0];
iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_4] + iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_4] + rVal[1];
iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_4] + iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_4] + rVal[2];
iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_4] + iVal[2];
rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_4] + rVal[3];
iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_4] + iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_4] + rVal[4];
iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_4] + iVal[4];
rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_4] + rVal[5];
iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_4] + iVal[5];
rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_4] + rVal[6];
iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_4] + iVal[6];
rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_4] + rVal[7];
iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_4] + iVal[7];
#endif
}
//end of stage 4
//multiply with twiddle for beginning of stage 5
//STRIDE_STAGE_5 4
if((threadIdx.x & STRIDE_STAGE_5) == STRIDE_STAGE_5)
{
//calculate Q twiddle factor
int q = ((threadIdx.x & M12)>>4) | (threadIdx.x & M34);
q = (q & M35) | ((q & M46)<<2);
float Q = q*NEG_2PI_BY_TLEN;
float c, s, T;
__sincosf(Q, &s, &c);
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
T = rVal[I];
rVal[I] = rVal[I]*c - iVal[I]*s;
iVal[I] = T*s + iVal[I]*c;
}
}
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][threadIdx.x] = rVal[I];
shImg[I][threadIdx.x] = iVal[I];
}
__syncthreads();
//stage 5
if((threadIdx.x & STRIDE_STAGE_5) == STRIDE_STAGE_5)
{
rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_5] - rVal[0];
iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_5] - iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_5] - rVal[1];
iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_5] - iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_5] - rVal[2];
iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_5] - iVal[2];
rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_5] - rVal[3];
iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_5] - iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_5] - rVal[4];
iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_5] - iVal[4];
rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_5] - rVal[5];
iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_5] - iVal[5];
rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_5] - rVal[6];
iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_5] - iVal[6];
rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_5] - rVal[7];
iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_5] - iVal[7];
#endif
}
else
{
rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_5] + rVal[0];
iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_5] + iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_5] + rVal[1];
iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_5] + iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_5] + rVal[2];
iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_5] + iVal[2];
rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_5] + rVal[3];
iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_5] + iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_5] + rVal[4];
iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_5] + iVal[4];
rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_5] + rVal[5];
iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_5] + iVal[5];
rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_5] + rVal[6];
iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_5] + iVal[6];
rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_5] + rVal[7];
iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_5] + iVal[7];
#endif
}
//end of stage 5
//multiply with twiddle for beginning of stage 6
//STRIDE_STAGE_6 2
if((threadIdx.x & STRIDE_STAGE_6) == STRIDE_STAGE_6)
{
//calculate Q twiddle factor
int q = ((threadIdx.x & M12)>>5) | ((threadIdx.x & M34)>>1) |
((threadIdx.x & M5)<<3);
q = (q & M246) | ((q & M357)<<2);
float Q = q*NEG_2PI_BY_TLEN;
float c, s, T;
__sincosf(Q, &s, &c);
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
T = rVal[I];
rVal[I] = rVal[I]*c - iVal[I]*s;
iVal[I] = T*s + iVal[I]*c;
}
}
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][threadIdx.x] = rVal[I];
shImg[I][threadIdx.x] = iVal[I];
}
__syncthreads();
//stage 6
if((threadIdx.x & STRIDE_STAGE_6) == STRIDE_STAGE_6)
{
rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_6] - rVal[0];
iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_6] - iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_6] - rVal[1];
iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_6] - iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_6] - rVal[2];
iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_6] - iVal[2];
rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_6] - rVal[3];
iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_6] - iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_6] - rVal[4];
iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_6] - iVal[4];
rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_6] - rVal[5];
iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_6] - iVal[5];
rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_6] - rVal[6];
iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_6] - iVal[6];
rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_6] - rVal[7];
iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_6] - iVal[7];
#endif
}
else
{
rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_6] + rVal[0];
iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_6] + iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_6] + rVal[1];
iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_6] + iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_6] + rVal[2];
iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_6] + iVal[2];
rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_6] + rVal[3];
iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_6] + iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_6] + rVal[4];
iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_6] + iVal[4];
rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_6] + rVal[5];
iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_6] + iVal[5];
rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_6] + rVal[6];
iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_6] + iVal[6];
rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_6] + rVal[7];
iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_6] + iVal[7];
#endif
}
//end of stage 6
//multiply with twiddle for beginning of stage 7
//STRIDE_STAGE_7 1
if((threadIdx.x & STRIDE_STAGE_7) == STRIDE_STAGE_7)
{
//calculate Q twiddle factor
int q = ((threadIdx.x & M12)>>4) | (threadIdx.x & M34) |
((threadIdx.x & M56)<<4);
q = ((q & M135)>>2) | (q & M246);
float Q = q*NEG_2PI_BY_TLEN;
float c, s, T;
__sincosf(Q, &s, &c);
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
T = rVal[I];
rVal[I] = rVal[I]*c - iVal[I]*s;
iVal[I] = T*s + iVal[I]*c;
}
}
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][threadIdx.x] = rVal[I];
shImg[I][threadIdx.x] = iVal[I];
}
__syncthreads();
//stage 7
if((threadIdx.x & STRIDE_STAGE_7) == STRIDE_STAGE_7)
{
rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_7] - rVal[0];
iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_7] - iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_7] - rVal[1];
iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_7] - iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_7] - rVal[2];
iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_7] - iVal[2];
rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_7] - rVal[3];
iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_7] - iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_7] - rVal[4];
iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_7] - iVal[4];
rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_7] - rVal[5];
iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_7] - iVal[5];
rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_7] - rVal[6];
iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_7] - iVal[6];
rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_7] - rVal[7];
iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_7] - iVal[7];
#endif
}
else
{
rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_7] + rVal[0];
iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_7] + iVal[0];
#if HEIGHT > 1
rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_7] + rVal[1];
iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_7] + iVal[1];
#endif
#if HEIGHT > 2
rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_7] + rVal[2];
iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_7] + iVal[2];
rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_7] + rVal[3];
iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_7] + iVal[3];
#endif
#if HEIGHT > 4
rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_7] + rVal[4];
iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_7] + iVal[4];
rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_7] + rVal[5];
iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_7] + iVal[5];
rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_7] + rVal[6];
iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_7] + iVal[6];
rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_7] + rVal[7];
iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_7] + iVal[7];
#endif
}
int revtid = bitreverse(threadIdx.x);
/*
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
shReal[I][revtid] = rVal[I];
shImg[I][revtid] = iVal[I];
}
*/
shReal[0][revtid] = rVal[0];
shImg[0][revtid] = iVal[0];
#if HEIGHT > 1
shReal[1][revtid] = rVal[1];
shImg[1][revtid] = iVal[1];
#endif
#if HEIGHT > 2
shReal[2][revtid] = rVal[2];
shImg[2][revtid] = iVal[2];
shReal[3][revtid] = rVal[3];
shImg[3][revtid] = iVal[3];
#endif
#if HEIGHT > 4
shReal[4][revtid] = rVal[4];
shImg[4][revtid] = iVal[4];
shReal[5][revtid] = rVal[5];
shImg[5][revtid] = iVal[5];
shReal[6][revtid] = rVal[6];
shImg[6][revtid] = iVal[6];
shReal[7][revtid] = rVal[7];
shImg[7][revtid] = iVal[7];
#endif
__syncthreads();
#pragma unroll
for(int I = 0; I < HEIGHT; I++)
{
real[((blockIdx.x*HEIGHT) + I)*blockDim.x + threadIdx.x] = shReal[I][threadIdx.x];
img[((blockIdx.x*HEIGHT) + I)*blockDim.x + threadIdx.x] = shImg[I][threadIdx.x];
}
}
__global__ void transposeDiagonal_xy(float *odatar, float *odatai, float *idatar, float *idatai, int width)
{
__shared__ float tile[TILE_DIM][TILE_DIM+1];
int blockIdx_x, blockIdx_y;
// do diagonal reordering
blockIdx_y = blockIdx.x;
blockIdx_x = (blockIdx.x+blockIdx.y)%gridDim.x;
// from here on the code is same as previous kernel except blockIdx_x replaces blockIdx.x
// and similarly for y
int xIndex = blockIdx_x * TILE_DIM + threadIdx.x;
int yIndex = blockIdx_y * TILE_DIM + threadIdx.y;
int index_in = xIndex + (yIndex + blockIdx.z*width)*width;
xIndex = blockIdx_y * TILE_DIM + threadIdx.x;
yIndex = blockIdx_x * TILE_DIM + threadIdx.y;
int index_out = xIndex + (yIndex + blockIdx.z*width)*width;
tile[threadIdx.y][threadIdx.x] = idatar[index_in];
__syncthreads();
odatar[index_out] = tile[threadIdx.x][threadIdx.y];
__syncthreads();
tile[threadIdx.y][threadIdx.x] = idatai[index_in];
__syncthreads();
odatai[index_out] = tile[threadIdx.x][threadIdx.y];
}
__global__ void transposeDiagonal_xz(float *odatar, float *odatai, float *idatar, float *idatai, int width)
{
__shared__ float tile[TILE_DIM][TILE_DIM+1];
int blockIdx_x, blockIdx_z;
// do diagonal reordering
blockIdx_z = blockIdx.x;
blockIdx_x = (blockIdx.x+blockIdx.z)%gridDim.x;
// from here on the code is same as previous kernel except blockIdx_x replaces blockIdx.x
// and similarly for y
int xIndex = blockIdx_x * TILE_DIM + threadIdx.x;
int zIndex = blockIdx_z * TILE_DIM + threadIdx.z;
int index_in = xIndex + (blockIdx.y + zIndex*width)*width;
xIndex = blockIdx_z * TILE_DIM + threadIdx.x;
zIndex = blockIdx_x * TILE_DIM + threadIdx.z;
int index_out = xIndex + (blockIdx.y + zIndex*width)*width;
tile[threadIdx.z][threadIdx.x] = idatar[index_in];
__syncthreads();
odatar[index_out] = tile[threadIdx.x][threadIdx.z];
__syncthreads();
tile[threadIdx.z][threadIdx.x] = idatai[index_in];
__syncthreads();
odatai[index_out] = tile[threadIdx.x][threadIdx.z];
}
__global__ void transposeDiagonal_xy(float *odata, float *idata, int width)
{
__shared__ float tile[TILE_DIM][TILE_DIM+1];
int blockIdx_x, blockIdx_y;
// do diagonal reordering
blockIdx_y = blockIdx.x;
blockIdx_x = (blockIdx.x+blockIdx.y)%gridDim.x;
// from here on the code is same as previous kernel except blockIdx_x replaces blockIdx.x
// and similarly for y
int xIndex = blockIdx_x * TILE_DIM + threadIdx.x;
int yIndex = blockIdx_y * TILE_DIM + threadIdx.y;
int index_in = xIndex + (yIndex + blockIdx.z*width)*width;
xIndex = blockIdx_y * TILE_DIM + threadIdx.x;
yIndex = blockIdx_x * TILE_DIM + threadIdx.y;
int index_out = xIndex + (yIndex + blockIdx.z*width)*width;
tile[threadIdx.y][threadIdx.x] = idata[index_in];
__syncthreads();
odata[index_out] = tile[threadIdx.x][threadIdx.y];
}
__global__ void transposeDiagonal_xz(float *odata, float *idata, int width)
{
__shared__ float tile[TILE_DIM][TILE_DIM+1];
int blockIdx_x, blockIdx_z;
// do diagonal reordering
blockIdx_z = blockIdx.x;
blockIdx_x = (blockIdx.x+blockIdx.z)%gridDim.x;
// from here on the code is same as previous kernel except blockIdx_x replaces blockIdx.x
// and similarly for y
int xIndex = blockIdx_x * TILE_DIM + threadIdx.x;
int zIndex = blockIdx_z * TILE_DIM + threadIdx.z;
int index_in = xIndex + (blockIdx.y + zIndex*width)*width;
xIndex = blockIdx_z * TILE_DIM + threadIdx.x;
zIndex = blockIdx_x * TILE_DIM + threadIdx.z;
int index_out = xIndex + (blockIdx.y + zIndex*width)*width;
tile[threadIdx.z][threadIdx.x] = idata[index_in];
__syncthreads();
odata[index_out] = tile[threadIdx.x][threadIdx.z];
} | .text
.file "fft.hip"
.globl _Z20__device_stub__FFT1DPfS_ # -- Begin function _Z20__device_stub__FFT1DPfS_
.p2align 4, 0x90
.type _Z20__device_stub__FFT1DPfS_,@function
_Z20__device_stub__FFT1DPfS_: # @_Z20__device_stub__FFT1DPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5FFT1DPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z20__device_stub__FFT1DPfS_, .Lfunc_end0-_Z20__device_stub__FFT1DPfS_
.cfi_endproc
# -- End function
.globl _Z35__device_stub__transposeDiagonal_xyPfS_S_S_i # -- Begin function _Z35__device_stub__transposeDiagonal_xyPfS_S_S_i
.p2align 4, 0x90
.type _Z35__device_stub__transposeDiagonal_xyPfS_S_S_i,@function
_Z35__device_stub__transposeDiagonal_xyPfS_S_S_i: # @_Z35__device_stub__transposeDiagonal_xyPfS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20transposeDiagonal_xyPfS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z35__device_stub__transposeDiagonal_xyPfS_S_S_i, .Lfunc_end1-_Z35__device_stub__transposeDiagonal_xyPfS_S_S_i
.cfi_endproc
# -- End function
.globl _Z35__device_stub__transposeDiagonal_xzPfS_S_S_i # -- Begin function _Z35__device_stub__transposeDiagonal_xzPfS_S_S_i
.p2align 4, 0x90
.type _Z35__device_stub__transposeDiagonal_xzPfS_S_S_i,@function
_Z35__device_stub__transposeDiagonal_xzPfS_S_S_i: # @_Z35__device_stub__transposeDiagonal_xzPfS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20transposeDiagonal_xzPfS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end2:
.size _Z35__device_stub__transposeDiagonal_xzPfS_S_S_i, .Lfunc_end2-_Z35__device_stub__transposeDiagonal_xzPfS_S_S_i
.cfi_endproc
# -- End function
.globl _Z35__device_stub__transposeDiagonal_xyPfS_i # -- Begin function _Z35__device_stub__transposeDiagonal_xyPfS_i
.p2align 4, 0x90
.type _Z35__device_stub__transposeDiagonal_xyPfS_i,@function
_Z35__device_stub__transposeDiagonal_xyPfS_i: # @_Z35__device_stub__transposeDiagonal_xyPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20transposeDiagonal_xyPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z35__device_stub__transposeDiagonal_xyPfS_i, .Lfunc_end3-_Z35__device_stub__transposeDiagonal_xyPfS_i
.cfi_endproc
# -- End function
.globl _Z35__device_stub__transposeDiagonal_xzPfS_i # -- Begin function _Z35__device_stub__transposeDiagonal_xzPfS_i
.p2align 4, 0x90
.type _Z35__device_stub__transposeDiagonal_xzPfS_i,@function
_Z35__device_stub__transposeDiagonal_xzPfS_i: # @_Z35__device_stub__transposeDiagonal_xzPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20transposeDiagonal_xzPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z35__device_stub__transposeDiagonal_xzPfS_i, .Lfunc_end4-_Z35__device_stub__transposeDiagonal_xzPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5FFT1DPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20transposeDiagonal_xyPfS_S_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20transposeDiagonal_xzPfS_S_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20transposeDiagonal_xyPfS_i, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20transposeDiagonal_xzPfS_i, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5FFT1DPfS_,@object # @_Z5FFT1DPfS_
.section .rodata,"a",@progbits
.globl _Z5FFT1DPfS_
.p2align 3, 0x0
_Z5FFT1DPfS_:
.quad _Z20__device_stub__FFT1DPfS_
.size _Z5FFT1DPfS_, 8
.type _Z20transposeDiagonal_xyPfS_S_S_i,@object # @_Z20transposeDiagonal_xyPfS_S_S_i
.globl _Z20transposeDiagonal_xyPfS_S_S_i
.p2align 3, 0x0
_Z20transposeDiagonal_xyPfS_S_S_i:
.quad _Z35__device_stub__transposeDiagonal_xyPfS_S_S_i
.size _Z20transposeDiagonal_xyPfS_S_S_i, 8
.type _Z20transposeDiagonal_xzPfS_S_S_i,@object # @_Z20transposeDiagonal_xzPfS_S_S_i
.globl _Z20transposeDiagonal_xzPfS_S_S_i
.p2align 3, 0x0
_Z20transposeDiagonal_xzPfS_S_S_i:
.quad _Z35__device_stub__transposeDiagonal_xzPfS_S_S_i
.size _Z20transposeDiagonal_xzPfS_S_S_i, 8
.type _Z20transposeDiagonal_xyPfS_i,@object # @_Z20transposeDiagonal_xyPfS_i
.globl _Z20transposeDiagonal_xyPfS_i
.p2align 3, 0x0
_Z20transposeDiagonal_xyPfS_i:
.quad _Z35__device_stub__transposeDiagonal_xyPfS_i
.size _Z20transposeDiagonal_xyPfS_i, 8
.type _Z20transposeDiagonal_xzPfS_i,@object # @_Z20transposeDiagonal_xzPfS_i
.globl _Z20transposeDiagonal_xzPfS_i
.p2align 3, 0x0
_Z20transposeDiagonal_xzPfS_i:
.quad _Z35__device_stub__transposeDiagonal_xzPfS_i
.size _Z20transposeDiagonal_xzPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5FFT1DPfS_"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z20transposeDiagonal_xyPfS_S_S_i"
.size .L__unnamed_2, 34
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z20transposeDiagonal_xzPfS_S_S_i"
.size .L__unnamed_3, 34
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z20transposeDiagonal_xyPfS_i"
.size .L__unnamed_4, 30
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z20transposeDiagonal_xzPfS_i"
.size .L__unnamed_5, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__FFT1DPfS_
.addrsig_sym _Z35__device_stub__transposeDiagonal_xyPfS_S_S_i
.addrsig_sym _Z35__device_stub__transposeDiagonal_xzPfS_S_S_i
.addrsig_sym _Z35__device_stub__transposeDiagonal_xyPfS_i
.addrsig_sym _Z35__device_stub__transposeDiagonal_xzPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5FFT1DPfS_
.addrsig_sym _Z20transposeDiagonal_xyPfS_S_S_i
.addrsig_sym _Z20transposeDiagonal_xzPfS_S_S_i
.addrsig_sym _Z20transposeDiagonal_xyPfS_i
.addrsig_sym _Z20transposeDiagonal_xzPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005351b_00000000-6_fft.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10bitreversei
.type _Z10bitreversei, @function
_Z10bitreversei:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z10bitreversei, .-_Z10bitreversei
.globl _Z26__device_stub__Z5FFT1DPfS_PfS_
.type _Z26__device_stub__Z5FFT1DPfS_PfS_, @function
_Z26__device_stub__Z5FFT1DPfS_PfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5FFT1DPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z26__device_stub__Z5FFT1DPfS_PfS_, .-_Z26__device_stub__Z5FFT1DPfS_PfS_
.globl _Z5FFT1DPfS_
.type _Z5FFT1DPfS_, @function
_Z5FFT1DPfS_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z5FFT1DPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z5FFT1DPfS_, .-_Z5FFT1DPfS_
.globl _Z47__device_stub__Z20transposeDiagonal_xyPfS_S_S_iPfS_S_S_i
.type _Z47__device_stub__Z20transposeDiagonal_xyPfS_S_S_iPfS_S_S_i, @function
_Z47__device_stub__Z20transposeDiagonal_xyPfS_S_S_iPfS_S_S_i:
.LFB2054:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20transposeDiagonal_xyPfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z47__device_stub__Z20transposeDiagonal_xyPfS_S_S_iPfS_S_S_i, .-_Z47__device_stub__Z20transposeDiagonal_xyPfS_S_S_iPfS_S_S_i
.globl _Z20transposeDiagonal_xyPfS_S_S_i
.type _Z20transposeDiagonal_xyPfS_S_S_i, @function
_Z20transposeDiagonal_xyPfS_S_S_i:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z20transposeDiagonal_xyPfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z20transposeDiagonal_xyPfS_S_S_i, .-_Z20transposeDiagonal_xyPfS_S_S_i
.globl _Z47__device_stub__Z20transposeDiagonal_xzPfS_S_S_iPfS_S_S_i
.type _Z47__device_stub__Z20transposeDiagonal_xzPfS_S_S_iPfS_S_S_i, @function
_Z47__device_stub__Z20transposeDiagonal_xzPfS_S_S_iPfS_S_S_i:
.LFB2056:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20transposeDiagonal_xzPfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _Z47__device_stub__Z20transposeDiagonal_xzPfS_S_S_iPfS_S_S_i, .-_Z47__device_stub__Z20transposeDiagonal_xzPfS_S_S_iPfS_S_S_i
.globl _Z20transposeDiagonal_xzPfS_S_S_i
.type _Z20transposeDiagonal_xzPfS_S_S_i, @function
_Z20transposeDiagonal_xzPfS_S_S_i:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z20transposeDiagonal_xzPfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z20transposeDiagonal_xzPfS_S_S_i, .-_Z20transposeDiagonal_xzPfS_S_S_i
.globl _Z43__device_stub__Z20transposeDiagonal_xyPfS_iPfS_i
.type _Z43__device_stub__Z20transposeDiagonal_xyPfS_iPfS_i, @function
_Z43__device_stub__Z20transposeDiagonal_xyPfS_iPfS_i:
.LFB2058:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20transposeDiagonal_xyPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z43__device_stub__Z20transposeDiagonal_xyPfS_iPfS_i, .-_Z43__device_stub__Z20transposeDiagonal_xyPfS_iPfS_i
.globl _Z20transposeDiagonal_xyPfS_i
.type _Z20transposeDiagonal_xyPfS_i, @function
_Z20transposeDiagonal_xyPfS_i:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z20transposeDiagonal_xyPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z20transposeDiagonal_xyPfS_i, .-_Z20transposeDiagonal_xyPfS_i
.globl _Z43__device_stub__Z20transposeDiagonal_xzPfS_iPfS_i
.type _Z43__device_stub__Z20transposeDiagonal_xzPfS_iPfS_i, @function
_Z43__device_stub__Z20transposeDiagonal_xzPfS_iPfS_i:
.LFB2060:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20transposeDiagonal_xzPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z43__device_stub__Z20transposeDiagonal_xzPfS_iPfS_i, .-_Z43__device_stub__Z20transposeDiagonal_xzPfS_iPfS_i
.globl _Z20transposeDiagonal_xzPfS_i
.type _Z20transposeDiagonal_xzPfS_i, @function
_Z20transposeDiagonal_xzPfS_i:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z20transposeDiagonal_xzPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z20transposeDiagonal_xzPfS_i, .-_Z20transposeDiagonal_xzPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z20transposeDiagonal_xzPfS_i"
.LC1:
.string "_Z20transposeDiagonal_xyPfS_i"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z20transposeDiagonal_xzPfS_S_S_i"
.align 8
.LC3:
.string "_Z20transposeDiagonal_xyPfS_S_S_i"
.section .rodata.str1.1
.LC4:
.string "_Z5FFT1DPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2063:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20transposeDiagonal_xzPfS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z20transposeDiagonal_xyPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z20transposeDiagonal_xzPfS_S_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z20transposeDiagonal_xyPfS_S_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z5FFT1DPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "fft.hip"
.globl _Z20__device_stub__FFT1DPfS_ # -- Begin function _Z20__device_stub__FFT1DPfS_
.p2align 4, 0x90
.type _Z20__device_stub__FFT1DPfS_,@function
_Z20__device_stub__FFT1DPfS_: # @_Z20__device_stub__FFT1DPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5FFT1DPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z20__device_stub__FFT1DPfS_, .Lfunc_end0-_Z20__device_stub__FFT1DPfS_
.cfi_endproc
# -- End function
.globl _Z35__device_stub__transposeDiagonal_xyPfS_S_S_i # -- Begin function _Z35__device_stub__transposeDiagonal_xyPfS_S_S_i
.p2align 4, 0x90
.type _Z35__device_stub__transposeDiagonal_xyPfS_S_S_i,@function
_Z35__device_stub__transposeDiagonal_xyPfS_S_S_i: # @_Z35__device_stub__transposeDiagonal_xyPfS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20transposeDiagonal_xyPfS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z35__device_stub__transposeDiagonal_xyPfS_S_S_i, .Lfunc_end1-_Z35__device_stub__transposeDiagonal_xyPfS_S_S_i
.cfi_endproc
# -- End function
.globl _Z35__device_stub__transposeDiagonal_xzPfS_S_S_i # -- Begin function _Z35__device_stub__transposeDiagonal_xzPfS_S_S_i
.p2align 4, 0x90
.type _Z35__device_stub__transposeDiagonal_xzPfS_S_S_i,@function
_Z35__device_stub__transposeDiagonal_xzPfS_S_S_i: # @_Z35__device_stub__transposeDiagonal_xzPfS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20transposeDiagonal_xzPfS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end2:
.size _Z35__device_stub__transposeDiagonal_xzPfS_S_S_i, .Lfunc_end2-_Z35__device_stub__transposeDiagonal_xzPfS_S_S_i
.cfi_endproc
# -- End function
.globl _Z35__device_stub__transposeDiagonal_xyPfS_i # -- Begin function _Z35__device_stub__transposeDiagonal_xyPfS_i
.p2align 4, 0x90
.type _Z35__device_stub__transposeDiagonal_xyPfS_i,@function
_Z35__device_stub__transposeDiagonal_xyPfS_i: # @_Z35__device_stub__transposeDiagonal_xyPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20transposeDiagonal_xyPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z35__device_stub__transposeDiagonal_xyPfS_i, .Lfunc_end3-_Z35__device_stub__transposeDiagonal_xyPfS_i
.cfi_endproc
# -- End function
.globl _Z35__device_stub__transposeDiagonal_xzPfS_i # -- Begin function _Z35__device_stub__transposeDiagonal_xzPfS_i
.p2align 4, 0x90
.type _Z35__device_stub__transposeDiagonal_xzPfS_i,@function
_Z35__device_stub__transposeDiagonal_xzPfS_i: # @_Z35__device_stub__transposeDiagonal_xzPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20transposeDiagonal_xzPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z35__device_stub__transposeDiagonal_xzPfS_i, .Lfunc_end4-_Z35__device_stub__transposeDiagonal_xzPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5FFT1DPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20transposeDiagonal_xyPfS_S_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20transposeDiagonal_xzPfS_S_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20transposeDiagonal_xyPfS_i, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20transposeDiagonal_xzPfS_i, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5FFT1DPfS_,@object # @_Z5FFT1DPfS_
.section .rodata,"a",@progbits
.globl _Z5FFT1DPfS_
.p2align 3, 0x0
_Z5FFT1DPfS_:
.quad _Z20__device_stub__FFT1DPfS_
.size _Z5FFT1DPfS_, 8
.type _Z20transposeDiagonal_xyPfS_S_S_i,@object # @_Z20transposeDiagonal_xyPfS_S_S_i
.globl _Z20transposeDiagonal_xyPfS_S_S_i
.p2align 3, 0x0
_Z20transposeDiagonal_xyPfS_S_S_i:
.quad _Z35__device_stub__transposeDiagonal_xyPfS_S_S_i
.size _Z20transposeDiagonal_xyPfS_S_S_i, 8
.type _Z20transposeDiagonal_xzPfS_S_S_i,@object # @_Z20transposeDiagonal_xzPfS_S_S_i
.globl _Z20transposeDiagonal_xzPfS_S_S_i
.p2align 3, 0x0
_Z20transposeDiagonal_xzPfS_S_S_i:
.quad _Z35__device_stub__transposeDiagonal_xzPfS_S_S_i
.size _Z20transposeDiagonal_xzPfS_S_S_i, 8
.type _Z20transposeDiagonal_xyPfS_i,@object # @_Z20transposeDiagonal_xyPfS_i
.globl _Z20transposeDiagonal_xyPfS_i
.p2align 3, 0x0
_Z20transposeDiagonal_xyPfS_i:
.quad _Z35__device_stub__transposeDiagonal_xyPfS_i
.size _Z20transposeDiagonal_xyPfS_i, 8
.type _Z20transposeDiagonal_xzPfS_i,@object # @_Z20transposeDiagonal_xzPfS_i
.globl _Z20transposeDiagonal_xzPfS_i
.p2align 3, 0x0
_Z20transposeDiagonal_xzPfS_i:
.quad _Z35__device_stub__transposeDiagonal_xzPfS_i
.size _Z20transposeDiagonal_xzPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5FFT1DPfS_"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z20transposeDiagonal_xyPfS_S_S_i"
.size .L__unnamed_2, 34
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z20transposeDiagonal_xzPfS_S_S_i"
.size .L__unnamed_3, 34
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z20transposeDiagonal_xyPfS_i"
.size .L__unnamed_4, 30
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z20transposeDiagonal_xzPfS_i"
.size .L__unnamed_5, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__FFT1DPfS_
.addrsig_sym _Z35__device_stub__transposeDiagonal_xyPfS_S_S_i
.addrsig_sym _Z35__device_stub__transposeDiagonal_xzPfS_S_S_i
.addrsig_sym _Z35__device_stub__transposeDiagonal_xyPfS_i
.addrsig_sym _Z35__device_stub__transposeDiagonal_xzPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5FFT1DPfS_
.addrsig_sym _Z20transposeDiagonal_xyPfS_S_S_i
.addrsig_sym _Z20transposeDiagonal_xzPfS_S_S_i
.addrsig_sym _Z20transposeDiagonal_xyPfS_i
.addrsig_sym _Z20transposeDiagonal_xzPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void twiddleImgKernel(float *wi, float *w, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int i, index;
if (idx < N) {
if (idx == 0) {
for (i = 0; i < N; i++)
wi[idx * N + i] = 0;
} else {
wi[idx * N + 0] = 0;
for (i = 1; i < N; i++) {
index = (idx * i) % N;
wi[idx * N + i] = (-1) * w[index * 2 + 1];
}
}
}
} | code for sm_80
Function : _Z16twiddleImgKernelPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0070*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fd80000000a00 */
/*0080*/ @!P0 BRA 0xa50 ; /* 0x000009c000008947 */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD R7, R0, c[0x0][0x170], RZ ; /* 0x00005c0000077a24 */
/* 0x000fe200078e02ff */
/*00c0*/ ISETP.GE.AND P0, PT, R4, 0x2, PT ; /* 0x000000020400780c */
/* 0x000fc60003f06270 */
/*00d0*/ IMAD.WIDE R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fca00078e0202 */
/*00e0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001ea000c101908 */
/*00f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R5, R4.reuse, -0x1, RZ ; /* 0xffffffff04057810 */
/* 0x040fe20007ffe0ff */
/*0110*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe200078e00ff */
/*0120*/ IADD3 R4, R4, -0x2, RZ ; /* 0xfffffffe04047810 */
/* 0x000fe40007ffe0ff */
/*0130*/ LOP3.LUT R6, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305067812 */
/* 0x000fe400078ec0ff */
/*0140*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fc40003f26070 */
/*0150*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fd60003f05270 */
/*0160*/ @!P1 BRA 0x790 ; /* 0x0000062000009947 */
/* 0x000fea0003800000 */
/*0170*/ IABS R10, c[0x0][0x170] ; /* 0x00005c00000a7a13 */
/* 0x000fe20000000000 */
/*0180*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e00ff */
/*0190*/ IMAD.IADD R8, R5, 0x1, -R6 ; /* 0x0000000105087824 */
/* 0x000fe200078e0a06 */
/*01a0*/ I2F.RP R4, R10 ; /* 0x0000000a00047306 */
/* 0x000e620000209400 */
/*01b0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fce00078e00ff */
/*01c0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e640000001000 */
/*01d0*/ IADD3 R15, R4, 0xffffffe, RZ ; /* 0x0ffffffe040f7810 */
/* 0x002fcc0007ffe0ff */
/*01e0*/ F2I.FTZ.U32.TRUNC.NTZ R15, R15 ; /* 0x0000000f000f7305 */
/* 0x000e64000021f000 */
/*01f0*/ IMAD.MOV R11, RZ, RZ, -R15 ; /* 0x000000ffff0b7224 */
/* 0x002fc800078e0a0f */
/*0200*/ IMAD R11, R11, R10, RZ ; /* 0x0000000a0b0b7224 */
/* 0x000fc800078e02ff */
/*0210*/ IMAD.HI.U32 R14, R15, R11, R14 ; /* 0x0000000b0f0e7227 */
/* 0x000fc800078e000e */
/*0220*/ IMAD R19, R0, R9, RZ ; /* 0x0000000900137224 */
/* 0x002fe200078e02ff */
/*0230*/ IABS R11, c[0x0][0x170] ; /* 0x00005c00000b7a13 */
/* 0x000fe20000000000 */
/*0240*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe200078e00ff */
/*0250*/ LOP3.LUT R12, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff0c7a12 */
/* 0x000fe400078e33ff */
/*0260*/ IABS R4, R19 ; /* 0x0000001300047213 */
/* 0x000fe40000000000 */
/*0270*/ ISETP.GE.AND P2, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fc60003f46270 */
/*0280*/ IMAD.HI.U32 R14, R14, R4, RZ ; /* 0x000000040e0e7227 */
/* 0x000fc800078e00ff */
/*0290*/ IMAD.MOV R14, RZ, RZ, -R14 ; /* 0x000000ffff0e7224 */
/* 0x000fc800078e0a0e */
/*02a0*/ IMAD R4, R11, R14, R4 ; /* 0x0000000e0b047224 */
/* 0x000fca00078e0204 */
/*02b0*/ ISETP.GT.U32.AND P1, PT, R10, R4, PT ; /* 0x000000040a00720c */
/* 0x000fda0003f24070 */
/*02c0*/ @!P1 IMAD.IADD R4, R4, 0x1, -R11 ; /* 0x0000000104049824 */
/* 0x000fca00078e0a0b */
/*02d0*/ ISETP.GT.U32.AND P1, PT, R10, R4, PT ; /* 0x000000040a00720c */
/* 0x000fda0003f24070 */
/*02e0*/ @!P1 IMAD.IADD R4, R4, 0x1, -R11 ; /* 0x0000000104049824 */
/* 0x000fe200078e0a0b */
/*02f0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fc80003f25270 */
/*0300*/ @!P2 IADD3 R4, -R4, RZ, RZ ; /* 0x000000ff0404a210 */
/* 0x000fc80007ffe1ff */
/*0310*/ SEL R4, R12, R4, !P1 ; /* 0x000000040c047207 */
/* 0x000fc80004800000 */
/*0320*/ LEA R4, R4, 0x1, 0x1 ; /* 0x0000000104047811 */
/* 0x000fca00078e08ff */
/*0330*/ IMAD.WIDE R14, R4, R13, c[0x0][0x168] ; /* 0x00005a00040e7625 */
/* 0x000fcc00078e020d */
/*0340*/ LDG.E R15, [R14.64] ; /* 0x000000080e0f7981 */
/* 0x0002a2000c1e1900 */
/*0350*/ I2F.RP R10, R11 ; /* 0x0000000b000a7306 */
/* 0x000ee20000209400 */
/*0360*/ IMAD.IADD R19, R0, 0x1, R19 ; /* 0x0000000100137824 */
/* 0x000fca00078e0213 */
/*0370*/ IABS R18, R19 ; /* 0x0000001300127213 */
/* 0x000fe40000000000 */
/*0380*/ ISETP.GE.AND P3, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fe20003f66270 */
/*0390*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x008ee40000001000 */
/*03a0*/ IADD3 R16, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a107810 */
/* 0x008fe20007ffe0ff */
/*03b0*/ IMAD.MOV.U32 R10, RZ, RZ, R11 ; /* 0x000000ffff0a7224 */
/* 0x000fca00078e000b */
/*03c0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R16 ; /* 0x0000001000057305 */
/* 0x000ee4000021f000 */
/*03d0*/ IMAD.MOV R4, RZ, RZ, -R5 ; /* 0x000000ffff047224 */
/* 0x008fc800078e0a05 */
/*03e0*/ IMAD R17, R4, R11, RZ ; /* 0x0000000b04117224 */
/* 0x000fe400078e02ff */
/*03f0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc800078e00ff */
/*0400*/ IMAD.HI.U32 R14, R5, R17, R4 ; /* 0x00000011050e7227 */
/* 0x002fc800078e0004 */
/*0410*/ IMAD.MOV.U32 R5, RZ, RZ, R18 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0012 */
/*0420*/ IMAD.HI.U32 R4, R14, R5, RZ ; /* 0x000000050e047227 */
/* 0x000fc800078e00ff */
/*0430*/ IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a04 */
/*0440*/ IMAD R4, R11, R4, R5 ; /* 0x000000040b047224 */
/* 0x000fca00078e0205 */
/*0450*/ ISETP.GT.U32.AND P2, PT, R10, R4, PT ; /* 0x000000040a00720c */
/* 0x000fda0003f44070 */
/*0460*/ @!P2 IMAD.IADD R4, R4, 0x1, -R11 ; /* 0x000000010404a824 */
/* 0x000fca00078e0a0b */
/*0470*/ ISETP.GT.U32.AND P2, PT, R10, R4, PT ; /* 0x000000040a00720c */
/* 0x000fda0003f44070 */
/*0480*/ @!P2 IMAD.IADD R4, R4, 0x1, -R11 ; /* 0x000000010404a824 */
/* 0x000fca00078e0a0b */
/*0490*/ @!P3 IADD3 R4, -R4, RZ, RZ ; /* 0x000000ff0404b210 */
/* 0x000fc80007ffe1ff */
/*04a0*/ SEL R4, R12, R4, !P1 ; /* 0x000000040c047207 */
/* 0x000fc80004800000 */
/*04b0*/ LEA R16, R4, 0x1, 0x1 ; /* 0x0000000104107811 */
/* 0x000fe200078e08ff */
/*04c0*/ IMAD.WIDE R4, R9, 0x4, R2 ; /* 0x0000000409047825 */
/* 0x000fc800078e0202 */
/*04d0*/ IMAD.WIDE R16, R16, R13, c[0x0][0x168] ; /* 0x00005a0010107625 */
/* 0x000fc800078e020d */
/*04e0*/ FADD R21, -R15, -RZ ; /* 0x800000ff0f157221 */
/* 0x004fca0000000100 */
/*04f0*/ STG.E [R4.64], R21 ; /* 0x0000001504007986 */
/* 0x0003e8000c101908 */
/*0500*/ LDG.E R16, [R16.64] ; /* 0x0000000810107981 */
/* 0x000ea2000c1e1900 */
/*0510*/ IMAD.IADD R23, R0, 0x1, R19 ; /* 0x0000000100177824 */
/* 0x000fca00078e0213 */
/*0520*/ IABS R18, R23 ; /* 0x0000001700127213 */
/* 0x000fe40000000000 */
/*0530*/ ISETP.GE.AND P3, PT, R23, RZ, PT ; /* 0x000000ff1700720c */
/* 0x000fc60003f66270 */
/*0540*/ IMAD.HI.U32 R15, R14, R18, RZ ; /* 0x000000120e0f7227 */
/* 0x000fc800078e00ff */
/*0550*/ IMAD.MOV R15, RZ, RZ, -R15 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e0a0f */
/*0560*/ IMAD R15, R11, R15, R18 ; /* 0x0000000f0b0f7224 */
/* 0x000fca00078e0212 */
/*0570*/ ISETP.GT.U32.AND P2, PT, R10, R15, PT ; /* 0x0000000f0a00720c */
/* 0x000fda0003f44070 */
/*0580*/ @!P2 IMAD.IADD R15, R15, 0x1, -R11 ; /* 0x000000010f0fa824 */
/* 0x000fca00078e0a0b */
/*0590*/ ISETP.GT.U32.AND P2, PT, R10, R15, PT ; /* 0x0000000f0a00720c */
/* 0x000fda0003f44070 */
/*05a0*/ @!P2 IMAD.IADD R15, R15, 0x1, -R11 ; /* 0x000000010f0fa824 */
/* 0x000fc800078e0a0b */
/*05b0*/ @!P3 IMAD.MOV R15, RZ, RZ, -R15 ; /* 0x000000ffff0fb224 */
/* 0x000fca00078e0a0f */
/*05c0*/ SEL R15, R12, R15, !P1 ; /* 0x0000000f0c0f7207 */
/* 0x000fc80004800000 */
/*05d0*/ LEA R18, R15, 0x1, 0x1 ; /* 0x000000010f127811 */
/* 0x000fe200078e08ff */
/*05e0*/ FADD R19, -R16, -RZ ; /* 0x800000ff10137221 */
/* 0x004fc80000000100 */
/*05f0*/ IMAD.WIDE R16, R18, R13, c[0x0][0x168] ; /* 0x00005a0012107625 */
/* 0x000fe200078e020d */
/*0600*/ STG.E [R4.64+0x4], R19 ; /* 0x0000041304007986 */
/* 0x0003ea000c101908 */
/*0610*/ LDG.E R16, [R16.64] ; /* 0x0000000810107981 */
/* 0x000ea2000c1e1900 */
/*0620*/ IMAD.IADD R15, R0, 0x1, R23 ; /* 0x00000001000f7824 */
/* 0x000fca00078e0217 */
/*0630*/ IABS R20, R15 ; /* 0x0000000f00147213 */
/* 0x000fe40000000000 */
/*0640*/ ISETP.GE.AND P3, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fc60003f66270 */
/*0650*/ IMAD.HI.U32 R18, R14, R20, RZ ; /* 0x000000140e127227 */
/* 0x000fc800078e00ff */
/*0660*/ IMAD.MOV R18, RZ, RZ, -R18 ; /* 0x000000ffff127224 */
/* 0x000fc800078e0a12 */
/*0670*/ IMAD R18, R11, R18, R20 ; /* 0x000000120b127224 */
/* 0x000fca00078e0214 */
/*0680*/ ISETP.GT.U32.AND P2, PT, R10, R18, PT ; /* 0x000000120a00720c */
/* 0x000fda0003f44070 */
/*0690*/ @!P2 IMAD.IADD R18, R18, 0x1, -R11 ; /* 0x000000011212a824 */
/* 0x000fca00078e0a0b */
/*06a0*/ ISETP.GT.U32.AND P2, PT, R10, R18, PT ; /* 0x000000120a00720c */
/* 0x000fda0003f44070 */
/*06b0*/ @!P2 IMAD.IADD R18, R18, 0x1, -R11 ; /* 0x000000011212a824 */
/* 0x000fca00078e0a0b */
/*06c0*/ @!P3 IADD3 R18, -R18, RZ, RZ ; /* 0x000000ff1212b210 */
/* 0x000fc80007ffe1ff */
/*06d0*/ SEL R12, R12, R18, !P1 ; /* 0x000000120c0c7207 */
/* 0x000fc80004800000 */
/*06e0*/ LEA R12, R12, 0x1, 0x1 ; /* 0x000000010c0c7811 */
/* 0x000fca00078e08ff */
/*06f0*/ IMAD.WIDE R12, R12, R13, c[0x0][0x168] ; /* 0x00005a000c0c7625 */
/* 0x000fc800078e020d */
/*0700*/ FADD R11, -R16, -RZ ; /* 0x800000ff100b7221 */
/* 0x004fca0000000100 */
/*0710*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x0003e8000c101908 */
/*0720*/ LDG.E R12, [R12.64] ; /* 0x000000080c0c7981 */
/* 0x000ea2000c1e1900 */
/*0730*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe40007ffe0ff */
/*0740*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe40007ffe0ff */
/*0750*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f25270 */
/*0760*/ FADD R15, -R12, -RZ ; /* 0x800000ff0c0f7221 */
/* 0x004fca0000000100 */
/*0770*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0003ee000c101908 */
/*0780*/ @P1 BRA 0x220 ; /* 0xfffffa9000001947 */
/* 0x000fea000383ffff */
/*0790*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*07a0*/ IABS R2, c[0x0][0x170] ; /* 0x00005c0000027a13 */
/* 0x001fe40000000000 */
/*07b0*/ SHF.R.S32.HI R4, RZ, 0x1f, R9 ; /* 0x0000001fff047819 */
/* 0x002fe40000011409 */
/*07c0*/ I2F.RP R3, R2 ; /* 0x0000000200037306 */
/* 0x000e220000209400 */
/*07d0*/ IADD3 R5, P0, R7, R9.reuse, RZ ; /* 0x0000000907057210 */
/* 0x080fe20007f1e0ff */
/*07e0*/ IMAD R9, R0, R9, RZ ; /* 0x0000000900097224 */
/* 0x000fc600078e02ff */
/*07f0*/ LEA.HI.X.SX32 R8, R7, R4, 0x1, P0 ; /* 0x0000000407087211 */
/* 0x000fe400000f0eff */
/*0800*/ LEA R4, P0, R5, c[0x0][0x160], 0x2 ; /* 0x0000580005047a11 */
/* 0x000fc800078010ff */
/*0810*/ LEA.HI.X R5, R5, c[0x0][0x164], R8, 0x2, P0 ; /* 0x0000590005057a11 */
/* 0x000fe200000f1408 */
/*0820*/ MUFU.RCP R3, R3 ; /* 0x0000000300037308 */
/* 0x001e240000001000 */
/*0830*/ IADD3 R10, R3, 0xffffffe, RZ ; /* 0x0ffffffe030a7810 */
/* 0x001fcc0007ffe0ff */
/*0840*/ F2I.FTZ.U32.TRUNC.NTZ R11, R10 ; /* 0x0000000a000b7305 */
/* 0x000064000021f000 */
/*0850*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e00ff */
/*0860*/ IMAD.MOV R13, RZ, RZ, -R11 ; /* 0x000000ffff0d7224 */
/* 0x002fc800078e0a0b */
/*0870*/ IMAD R7, R13, R2, RZ ; /* 0x000000020d077224 */
/* 0x000fc800078e02ff */
/*0880*/ IMAD.HI.U32 R12, R11, R7, R10 ; /* 0x000000070b0c7227 */
/* 0x000fc800078e000a */
/*0890*/ IABS R7, R9 ; /* 0x0000000900077213 */
/* 0x000fe20000000000 */
/*08a0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*08b0*/ IABS R10, c[0x0][0x170] ; /* 0x00005c00000a7a13 */
/* 0x000fe40000000000 */
/*08c0*/ ISETP.GE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f26270 */
/*08d0*/ IMAD.HI.U32 R3, R12, R7, RZ ; /* 0x000000070c037227 */
/* 0x000fe200078e00ff */
/*08e0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fc60003f45270 */
/*08f0*/ IMAD.MOV R8, RZ, RZ, -R3 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0a03 */
/*0900*/ IMAD R3, R10, R8, R7 ; /* 0x000000080a037224 */
/* 0x000fca00078e0207 */
/*0910*/ ISETP.GT.U32.AND P0, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fda0003f04070 */
/*0920*/ @!P0 IMAD.IADD R3, R3, 0x1, -R10 ; /* 0x0000000103038824 */
/* 0x000fca00078e0a0a */
/*0930*/ ISETP.GT.U32.AND P0, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fda0003f04070 */
/*0940*/ @!P0 IMAD.IADD R3, R3, 0x1, -R10 ; /* 0x0000000103038824 */
/* 0x000fc800078e0a0a */
/*0950*/ @!P1 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0a03 */
/*0960*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff03aa12 */
/* 0x000fc800078e33ff */
/*0970*/ LEA R10, R3, 0x1, 0x1 ; /* 0x00000001030a7811 */
/* 0x000fca00078e08ff */
/*0980*/ IMAD.WIDE R10, R10, R11, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x000fcc00078e020b */
/*0990*/ LDG.E R10, [R10.64] ; /* 0x000000080a0a7981 */
/* 0x000ea2000c1e1900 */
/*09a0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*09b0*/ IADD3 R3, P1, R4, 0x4, RZ ; /* 0x0000000404037810 */
/* 0x000fe40007f3e0ff */
/*09c0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc60003f05270 */
/*09d0*/ IMAD.X R7, RZ, RZ, R5, P1 ; /* 0x000000ffff077224 */
/* 0x000fe400008e0605 */
/*09e0*/ FADD R13, -R10, -RZ ; /* 0x800000ff0a0d7221 */
/* 0x004fca0000000100 */
/*09f0*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0001e6000c101908 */
/*0a00*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0a10*/ IADD3 R9, R0, R9, RZ ; /* 0x0000000900097210 */
/* 0x000fe20007ffe0ff */
/*0a20*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0003 */
/*0a30*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0007 */
/*0a40*/ BRA 0x890 ; /* 0xfffffe4000007947 */
/* 0x000fea000383ffff */
/*0a50*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff007624 */
/* 0x000fca00078e00ff */
/*0a60*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0a70*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0a80*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0a90*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0aa0*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe400078ec0ff */
/*0ab0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0ac0*/ @!P0 BRA 0xee0 ; /* 0x0000041000008947 */
/* 0x000fea0003800000 */
/*0ad0*/ IADD3 R4, -R0, c[0x0][0x170], RZ ; /* 0x00005c0000047a10 */
/* 0x000fe20007ffe1ff */
/*0ae0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0af0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe400078e00ff */
/*0b00*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f04270 */
/*0b10*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fd800078e00ff */
/*0b20*/ @!P0 BRA 0xe20 ; /* 0x000002f000008947 */
/* 0x000fea0003800000 */
/*0b30*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*0b40*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0b50*/ @!P1 BRA 0xcf0 ; /* 0x0000019000009947 */
/* 0x000fea0003800000 */
/*0b60*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0b70*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fe20007ffe0ff */
/*0b80*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*0b90*/ IADD3 R5, P2, R2, 0x40, RZ ; /* 0x0000004002057810 */
/* 0x000fe20007f5e0ff */
/*0ba0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101908 */
/*0bb0*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fc60003f24270 */
/*0bc0*/ IMAD.X R6, RZ, RZ, R3, P2 ; /* 0x000000ffff067224 */
/* 0x000fe200010e0603 */
/*0bd0*/ STG.E [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe8000c101908 */
/*0be0*/ STG.E [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x000fe8000c101908 */
/*0bf0*/ STG.E [R2.64+0xc], RZ ; /* 0x00000cff02007986 */
/* 0x000fe8000c101908 */
/*0c00*/ STG.E [R2.64+0x10], RZ ; /* 0x000010ff02007986 */
/* 0x000fe8000c101908 */
/*0c10*/ STG.E [R2.64+0x14], RZ ; /* 0x000014ff02007986 */
/* 0x000fe8000c101908 */
/*0c20*/ STG.E [R2.64+0x18], RZ ; /* 0x000018ff02007986 */
/* 0x000fe8000c101908 */
/*0c30*/ STG.E [R2.64+0x1c], RZ ; /* 0x00001cff02007986 */
/* 0x000fe8000c101908 */
/*0c40*/ STG.E [R2.64+0x20], RZ ; /* 0x000020ff02007986 */
/* 0x000fe8000c101908 */
/*0c50*/ STG.E [R2.64+0x24], RZ ; /* 0x000024ff02007986 */
/* 0x000fe8000c101908 */
/*0c60*/ STG.E [R2.64+0x28], RZ ; /* 0x000028ff02007986 */
/* 0x000fe8000c101908 */
/*0c70*/ STG.E [R2.64+0x2c], RZ ; /* 0x00002cff02007986 */
/* 0x000fe8000c101908 */
/*0c80*/ STG.E [R2.64+0x30], RZ ; /* 0x000030ff02007986 */
/* 0x000fe8000c101908 */
/*0c90*/ STG.E [R2.64+0x34], RZ ; /* 0x000034ff02007986 */
/* 0x000fe8000c101908 */
/*0ca0*/ STG.E [R2.64+0x38], RZ ; /* 0x000038ff02007986 */
/* 0x000fe8000c101908 */
/*0cb0*/ STG.E [R2.64+0x3c], RZ ; /* 0x00003cff02007986 */
/* 0x0001e4000c101908 */
/*0cc0*/ IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0005 */
/*0cd0*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0006 */
/*0ce0*/ @P1 BRA 0xb70 ; /* 0xfffffe8000001947 */
/* 0x000fea000383ffff */
/*0cf0*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*0d00*/ @!P1 BRA 0xe00 ; /* 0x000000f000009947 */
/* 0x000fea0003800000 */
/*0d10*/ IADD3 R5, P1, R2, 0x20, RZ ; /* 0x0000002002057810 */
/* 0x000fe20007f3e0ff */
/*0d20*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101908 */
/*0d30*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0d40*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0d50*/ IADD3.X R6, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff067210 */
/* 0x000fe20000ffe4ff */
/*0d60*/ STG.E [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe2000c101908 */
/*0d70*/ IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804047810 */
/* 0x000fc60007ffe0ff */
/*0d80*/ STG.E [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x000fe8000c101908 */
/*0d90*/ STG.E [R2.64+0xc], RZ ; /* 0x00000cff02007986 */
/* 0x000fe8000c101908 */
/*0da0*/ STG.E [R2.64+0x10], RZ ; /* 0x000010ff02007986 */
/* 0x000fe8000c101908 */
/*0db0*/ STG.E [R2.64+0x14], RZ ; /* 0x000014ff02007986 */
/* 0x000fe8000c101908 */
/*0dc0*/ STG.E [R2.64+0x18], RZ ; /* 0x000018ff02007986 */
/* 0x000fe8000c101908 */
/*0dd0*/ STG.E [R2.64+0x1c], RZ ; /* 0x00001cff02007986 */
/* 0x0001e4000c101908 */
/*0de0*/ IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0005 */
/*0df0*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0006 */
/*0e00*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705670 */
/*0e10*/ @!P0 BRA 0xee0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0e20*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe20007ffe0ff */
/*0e30*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0e40*/ IADD3 R5, P1, R2, 0x10, RZ ; /* 0x0000001002057810 */
/* 0x000fe20007f3e0ff */
/*0e50*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101908 */
/*0e60*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0e70*/ IMAD.X R6, RZ, RZ, R3, P1 ; /* 0x000000ffff067224 */
/* 0x000fe200008e0603 */
/*0e80*/ STG.E [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe8000c101908 */
/*0e90*/ STG.E [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x000fe8000c101908 */
/*0ea0*/ STG.E [R2.64+0xc], RZ ; /* 0x00000cff02007986 */
/* 0x0001e4000c101908 */
/*0eb0*/ IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0005 */
/*0ec0*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0006 */
/*0ed0*/ @P0 BRA 0xe20 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0ee0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0ef0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0f00*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe40000000000 */
/*0f10*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*0f20*/ UIMAD.WIDE UR4, UR4, UR5, UR6 ; /* 0x00000005040472a5 */
/* 0x000fcc000f8e0206 */
/*0f30*/ IMAD.U32 R2, RZ, RZ, UR4 ; /* 0x00000004ff027e24 */
/* 0x000fe2000f8e00ff */
/*0f40*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0f50*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x000fe2000f8e00ff */
/*0f60*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000ff1e03f */
/*0f70*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0f80*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101908 */
/*0f90*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fd400087fe43f */
/*0fa0*/ @P0 BRA 0xf30 ; /* 0xffffff8000000947 */
/* 0x001fea000383ffff */
/*0fb0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0fc0*/ BRA 0xfc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void twiddleImgKernel(float *wi, float *w, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int i, index;
if (idx < N) {
if (idx == 0) {
for (i = 0; i < N; i++)
wi[idx * N + i] = 0;
} else {
wi[idx * N + 0] = 0;
for (i = 1; i < N; i++) {
index = (idx * i) % N;
wi[idx * N + i] = (-1) * w[index * 2 + 1];
}
}
}
} | .file "tmpxft_0002e504_00000000-6_twiddleImgKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z16twiddleImgKernelPfS_iPfS_i
.type _Z39__device_stub__Z16twiddleImgKernelPfS_iPfS_i, @function
_Z39__device_stub__Z16twiddleImgKernelPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16twiddleImgKernelPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z16twiddleImgKernelPfS_iPfS_i, .-_Z39__device_stub__Z16twiddleImgKernelPfS_iPfS_i
.globl _Z16twiddleImgKernelPfS_i
.type _Z16twiddleImgKernelPfS_i, @function
_Z16twiddleImgKernelPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16twiddleImgKernelPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16twiddleImgKernelPfS_i, .-_Z16twiddleImgKernelPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16twiddleImgKernelPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16twiddleImgKernelPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void twiddleImgKernel(float *wi, float *w, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int i, index;
if (idx < N) {
if (idx == 0) {
for (i = 0; i < N; i++)
wi[idx * N + i] = 0;
} else {
wi[idx * N + 0] = 0;
for (i = 1; i < N; i++) {
index = (idx * i) % N;
wi[idx * N + i] = (-1) * w[index * 2 + 1];
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void twiddleImgKernel(float *wi, float *w, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int i, index;
if (idx < N) {
if (idx == 0) {
for (i = 0; i < N; i++)
wi[idx * N + i] = 0;
} else {
wi[idx * N + 0] = 0;
for (i = 1; i < N; i++) {
index = (idx * i) % N;
wi[idx * N + i] = (-1) * w[index * 2 + 1];
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void twiddleImgKernel(float *wi, float *w, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int i, index;
if (idx < N) {
if (idx == 0) {
for (i = 0; i < N; i++)
wi[idx * N + i] = 0;
} else {
wi[idx * N + 0] = 0;
for (i = 1; i < N; i++) {
index = (idx * i) % N;
wi[idx * N + i] = (-1) * w[index * 2 + 1];
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16twiddleImgKernelPfS_i
.globl _Z16twiddleImgKernelPfS_i
.p2align 8
.type _Z16twiddleImgKernelPfS_i,@function
_Z16twiddleImgKernelPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_9
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s5, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_5
v_mul_lo_u32 v2, v1, s4
v_mov_b32_e32 v0, 0
s_cmp_lt_i32 s4, 2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_store_b32 v[3:4], v0, off
s_cbranch_scc1 .LBB0_5
s_ashr_i32 s6, s4, 31
s_load_b64 s[0:1], s[0:1], 0x8
s_add_i32 s7, s4, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s6, s7, s6
v_cvt_f32_u32_e32 v0, s6
s_sub_i32 s7, 0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s7, v0
s_mov_b32 s7, 1
v_mul_hi_u32 v3, v0, v3
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v3, v1 :: v_dual_add_nc_u32 v0, v0, v3
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_add_nc_u32_e32 v5, v3, v4
v_add_nc_u32_e32 v3, v3, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v5, v5, v4
v_mul_hi_u32 v6, v5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, v6, s6
v_sub_nc_u32_e32 v5, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s6, v5
v_cmp_le_u32_e32 vcc_lo, s6, v5
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s6, v5
v_cmp_le_u32_e32 vcc_lo, s6, v5
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v5, v5, v4
v_sub_nc_u32_e32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_or_b32 v4, v4, 1, 1
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b32 v6, v[4:5], off
v_add_nc_u32_e32 v4, s7, v2
s_add_i32 s7, s7, 1
s_cmp_lg_u32 s4, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_waitcnt vmcnt(0)
v_xor_b32_e32 v6, 0x80000000, v6
global_store_b32 v[4:5], v6, off
s_cbranch_scc1 .LBB0_4
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_and_not1_saveexec_b32 s0, s5
s_cbranch_execz .LBB0_9
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_9
v_mov_b32_e32 v0, 0
.LBB0_8:
s_add_i32 s4, s4, -1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v0, s[2:3]
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s4, 0
s_cbranch_scc0 .LBB0_8
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16twiddleImgKernelPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16twiddleImgKernelPfS_i, .Lfunc_end0-_Z16twiddleImgKernelPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16twiddleImgKernelPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16twiddleImgKernelPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void twiddleImgKernel(float *wi, float *w, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int i, index;
if (idx < N) {
if (idx == 0) {
for (i = 0; i < N; i++)
wi[idx * N + i] = 0;
} else {
wi[idx * N + 0] = 0;
for (i = 1; i < N; i++) {
index = (idx * i) % N;
wi[idx * N + i] = (-1) * w[index * 2 + 1];
}
}
}
} | .text
.file "twiddleImgKernel.hip"
.globl _Z31__device_stub__twiddleImgKernelPfS_i # -- Begin function _Z31__device_stub__twiddleImgKernelPfS_i
.p2align 4, 0x90
.type _Z31__device_stub__twiddleImgKernelPfS_i,@function
_Z31__device_stub__twiddleImgKernelPfS_i: # @_Z31__device_stub__twiddleImgKernelPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16twiddleImgKernelPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z31__device_stub__twiddleImgKernelPfS_i, .Lfunc_end0-_Z31__device_stub__twiddleImgKernelPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16twiddleImgKernelPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16twiddleImgKernelPfS_i,@object # @_Z16twiddleImgKernelPfS_i
.section .rodata,"a",@progbits
.globl _Z16twiddleImgKernelPfS_i
.p2align 3, 0x0
_Z16twiddleImgKernelPfS_i:
.quad _Z31__device_stub__twiddleImgKernelPfS_i
.size _Z16twiddleImgKernelPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16twiddleImgKernelPfS_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__twiddleImgKernelPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16twiddleImgKernelPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16twiddleImgKernelPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0070*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fd80000000a00 */
/*0080*/ @!P0 BRA 0xa50 ; /* 0x000009c000008947 */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD R7, R0, c[0x0][0x170], RZ ; /* 0x00005c0000077a24 */
/* 0x000fe200078e02ff */
/*00c0*/ ISETP.GE.AND P0, PT, R4, 0x2, PT ; /* 0x000000020400780c */
/* 0x000fc60003f06270 */
/*00d0*/ IMAD.WIDE R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fca00078e0202 */
/*00e0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001ea000c101908 */
/*00f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R5, R4.reuse, -0x1, RZ ; /* 0xffffffff04057810 */
/* 0x040fe20007ffe0ff */
/*0110*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe200078e00ff */
/*0120*/ IADD3 R4, R4, -0x2, RZ ; /* 0xfffffffe04047810 */
/* 0x000fe40007ffe0ff */
/*0130*/ LOP3.LUT R6, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305067812 */
/* 0x000fe400078ec0ff */
/*0140*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fc40003f26070 */
/*0150*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fd60003f05270 */
/*0160*/ @!P1 BRA 0x790 ; /* 0x0000062000009947 */
/* 0x000fea0003800000 */
/*0170*/ IABS R10, c[0x0][0x170] ; /* 0x00005c00000a7a13 */
/* 0x000fe20000000000 */
/*0180*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e00ff */
/*0190*/ IMAD.IADD R8, R5, 0x1, -R6 ; /* 0x0000000105087824 */
/* 0x000fe200078e0a06 */
/*01a0*/ I2F.RP R4, R10 ; /* 0x0000000a00047306 */
/* 0x000e620000209400 */
/*01b0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fce00078e00ff */
/*01c0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e640000001000 */
/*01d0*/ IADD3 R15, R4, 0xffffffe, RZ ; /* 0x0ffffffe040f7810 */
/* 0x002fcc0007ffe0ff */
/*01e0*/ F2I.FTZ.U32.TRUNC.NTZ R15, R15 ; /* 0x0000000f000f7305 */
/* 0x000e64000021f000 */
/*01f0*/ IMAD.MOV R11, RZ, RZ, -R15 ; /* 0x000000ffff0b7224 */
/* 0x002fc800078e0a0f */
/*0200*/ IMAD R11, R11, R10, RZ ; /* 0x0000000a0b0b7224 */
/* 0x000fc800078e02ff */
/*0210*/ IMAD.HI.U32 R14, R15, R11, R14 ; /* 0x0000000b0f0e7227 */
/* 0x000fc800078e000e */
/*0220*/ IMAD R19, R0, R9, RZ ; /* 0x0000000900137224 */
/* 0x002fe200078e02ff */
/*0230*/ IABS R11, c[0x0][0x170] ; /* 0x00005c00000b7a13 */
/* 0x000fe20000000000 */
/*0240*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe200078e00ff */
/*0250*/ LOP3.LUT R12, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff0c7a12 */
/* 0x000fe400078e33ff */
/*0260*/ IABS R4, R19 ; /* 0x0000001300047213 */
/* 0x000fe40000000000 */
/*0270*/ ISETP.GE.AND P2, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fc60003f46270 */
/*0280*/ IMAD.HI.U32 R14, R14, R4, RZ ; /* 0x000000040e0e7227 */
/* 0x000fc800078e00ff */
/*0290*/ IMAD.MOV R14, RZ, RZ, -R14 ; /* 0x000000ffff0e7224 */
/* 0x000fc800078e0a0e */
/*02a0*/ IMAD R4, R11, R14, R4 ; /* 0x0000000e0b047224 */
/* 0x000fca00078e0204 */
/*02b0*/ ISETP.GT.U32.AND P1, PT, R10, R4, PT ; /* 0x000000040a00720c */
/* 0x000fda0003f24070 */
/*02c0*/ @!P1 IMAD.IADD R4, R4, 0x1, -R11 ; /* 0x0000000104049824 */
/* 0x000fca00078e0a0b */
/*02d0*/ ISETP.GT.U32.AND P1, PT, R10, R4, PT ; /* 0x000000040a00720c */
/* 0x000fda0003f24070 */
/*02e0*/ @!P1 IMAD.IADD R4, R4, 0x1, -R11 ; /* 0x0000000104049824 */
/* 0x000fe200078e0a0b */
/*02f0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fc80003f25270 */
/*0300*/ @!P2 IADD3 R4, -R4, RZ, RZ ; /* 0x000000ff0404a210 */
/* 0x000fc80007ffe1ff */
/*0310*/ SEL R4, R12, R4, !P1 ; /* 0x000000040c047207 */
/* 0x000fc80004800000 */
/*0320*/ LEA R4, R4, 0x1, 0x1 ; /* 0x0000000104047811 */
/* 0x000fca00078e08ff */
/*0330*/ IMAD.WIDE R14, R4, R13, c[0x0][0x168] ; /* 0x00005a00040e7625 */
/* 0x000fcc00078e020d */
/*0340*/ LDG.E R15, [R14.64] ; /* 0x000000080e0f7981 */
/* 0x0002a2000c1e1900 */
/*0350*/ I2F.RP R10, R11 ; /* 0x0000000b000a7306 */
/* 0x000ee20000209400 */
/*0360*/ IMAD.IADD R19, R0, 0x1, R19 ; /* 0x0000000100137824 */
/* 0x000fca00078e0213 */
/*0370*/ IABS R18, R19 ; /* 0x0000001300127213 */
/* 0x000fe40000000000 */
/*0380*/ ISETP.GE.AND P3, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fe20003f66270 */
/*0390*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x008ee40000001000 */
/*03a0*/ IADD3 R16, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a107810 */
/* 0x008fe20007ffe0ff */
/*03b0*/ IMAD.MOV.U32 R10, RZ, RZ, R11 ; /* 0x000000ffff0a7224 */
/* 0x000fca00078e000b */
/*03c0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R16 ; /* 0x0000001000057305 */
/* 0x000ee4000021f000 */
/*03d0*/ IMAD.MOV R4, RZ, RZ, -R5 ; /* 0x000000ffff047224 */
/* 0x008fc800078e0a05 */
/*03e0*/ IMAD R17, R4, R11, RZ ; /* 0x0000000b04117224 */
/* 0x000fe400078e02ff */
/*03f0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc800078e00ff */
/*0400*/ IMAD.HI.U32 R14, R5, R17, R4 ; /* 0x00000011050e7227 */
/* 0x002fc800078e0004 */
/*0410*/ IMAD.MOV.U32 R5, RZ, RZ, R18 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0012 */
/*0420*/ IMAD.HI.U32 R4, R14, R5, RZ ; /* 0x000000050e047227 */
/* 0x000fc800078e00ff */
/*0430*/ IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a04 */
/*0440*/ IMAD R4, R11, R4, R5 ; /* 0x000000040b047224 */
/* 0x000fca00078e0205 */
/*0450*/ ISETP.GT.U32.AND P2, PT, R10, R4, PT ; /* 0x000000040a00720c */
/* 0x000fda0003f44070 */
/*0460*/ @!P2 IMAD.IADD R4, R4, 0x1, -R11 ; /* 0x000000010404a824 */
/* 0x000fca00078e0a0b */
/*0470*/ ISETP.GT.U32.AND P2, PT, R10, R4, PT ; /* 0x000000040a00720c */
/* 0x000fda0003f44070 */
/*0480*/ @!P2 IMAD.IADD R4, R4, 0x1, -R11 ; /* 0x000000010404a824 */
/* 0x000fca00078e0a0b */
/*0490*/ @!P3 IADD3 R4, -R4, RZ, RZ ; /* 0x000000ff0404b210 */
/* 0x000fc80007ffe1ff */
/*04a0*/ SEL R4, R12, R4, !P1 ; /* 0x000000040c047207 */
/* 0x000fc80004800000 */
/*04b0*/ LEA R16, R4, 0x1, 0x1 ; /* 0x0000000104107811 */
/* 0x000fe200078e08ff */
/*04c0*/ IMAD.WIDE R4, R9, 0x4, R2 ; /* 0x0000000409047825 */
/* 0x000fc800078e0202 */
/*04d0*/ IMAD.WIDE R16, R16, R13, c[0x0][0x168] ; /* 0x00005a0010107625 */
/* 0x000fc800078e020d */
/*04e0*/ FADD R21, -R15, -RZ ; /* 0x800000ff0f157221 */
/* 0x004fca0000000100 */
/*04f0*/ STG.E [R4.64], R21 ; /* 0x0000001504007986 */
/* 0x0003e8000c101908 */
/*0500*/ LDG.E R16, [R16.64] ; /* 0x0000000810107981 */
/* 0x000ea2000c1e1900 */
/*0510*/ IMAD.IADD R23, R0, 0x1, R19 ; /* 0x0000000100177824 */
/* 0x000fca00078e0213 */
/*0520*/ IABS R18, R23 ; /* 0x0000001700127213 */
/* 0x000fe40000000000 */
/*0530*/ ISETP.GE.AND P3, PT, R23, RZ, PT ; /* 0x000000ff1700720c */
/* 0x000fc60003f66270 */
/*0540*/ IMAD.HI.U32 R15, R14, R18, RZ ; /* 0x000000120e0f7227 */
/* 0x000fc800078e00ff */
/*0550*/ IMAD.MOV R15, RZ, RZ, -R15 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e0a0f */
/*0560*/ IMAD R15, R11, R15, R18 ; /* 0x0000000f0b0f7224 */
/* 0x000fca00078e0212 */
/*0570*/ ISETP.GT.U32.AND P2, PT, R10, R15, PT ; /* 0x0000000f0a00720c */
/* 0x000fda0003f44070 */
/*0580*/ @!P2 IMAD.IADD R15, R15, 0x1, -R11 ; /* 0x000000010f0fa824 */
/* 0x000fca00078e0a0b */
/*0590*/ ISETP.GT.U32.AND P2, PT, R10, R15, PT ; /* 0x0000000f0a00720c */
/* 0x000fda0003f44070 */
/*05a0*/ @!P2 IMAD.IADD R15, R15, 0x1, -R11 ; /* 0x000000010f0fa824 */
/* 0x000fc800078e0a0b */
/*05b0*/ @!P3 IMAD.MOV R15, RZ, RZ, -R15 ; /* 0x000000ffff0fb224 */
/* 0x000fca00078e0a0f */
/*05c0*/ SEL R15, R12, R15, !P1 ; /* 0x0000000f0c0f7207 */
/* 0x000fc80004800000 */
/*05d0*/ LEA R18, R15, 0x1, 0x1 ; /* 0x000000010f127811 */
/* 0x000fe200078e08ff */
/*05e0*/ FADD R19, -R16, -RZ ; /* 0x800000ff10137221 */
/* 0x004fc80000000100 */
/*05f0*/ IMAD.WIDE R16, R18, R13, c[0x0][0x168] ; /* 0x00005a0012107625 */
/* 0x000fe200078e020d */
/*0600*/ STG.E [R4.64+0x4], R19 ; /* 0x0000041304007986 */
/* 0x0003ea000c101908 */
/*0610*/ LDG.E R16, [R16.64] ; /* 0x0000000810107981 */
/* 0x000ea2000c1e1900 */
/*0620*/ IMAD.IADD R15, R0, 0x1, R23 ; /* 0x00000001000f7824 */
/* 0x000fca00078e0217 */
/*0630*/ IABS R20, R15 ; /* 0x0000000f00147213 */
/* 0x000fe40000000000 */
/*0640*/ ISETP.GE.AND P3, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fc60003f66270 */
/*0650*/ IMAD.HI.U32 R18, R14, R20, RZ ; /* 0x000000140e127227 */
/* 0x000fc800078e00ff */
/*0660*/ IMAD.MOV R18, RZ, RZ, -R18 ; /* 0x000000ffff127224 */
/* 0x000fc800078e0a12 */
/*0670*/ IMAD R18, R11, R18, R20 ; /* 0x000000120b127224 */
/* 0x000fca00078e0214 */
/*0680*/ ISETP.GT.U32.AND P2, PT, R10, R18, PT ; /* 0x000000120a00720c */
/* 0x000fda0003f44070 */
/*0690*/ @!P2 IMAD.IADD R18, R18, 0x1, -R11 ; /* 0x000000011212a824 */
/* 0x000fca00078e0a0b */
/*06a0*/ ISETP.GT.U32.AND P2, PT, R10, R18, PT ; /* 0x000000120a00720c */
/* 0x000fda0003f44070 */
/*06b0*/ @!P2 IMAD.IADD R18, R18, 0x1, -R11 ; /* 0x000000011212a824 */
/* 0x000fca00078e0a0b */
/*06c0*/ @!P3 IADD3 R18, -R18, RZ, RZ ; /* 0x000000ff1212b210 */
/* 0x000fc80007ffe1ff */
/*06d0*/ SEL R12, R12, R18, !P1 ; /* 0x000000120c0c7207 */
/* 0x000fc80004800000 */
/*06e0*/ LEA R12, R12, 0x1, 0x1 ; /* 0x000000010c0c7811 */
/* 0x000fca00078e08ff */
/*06f0*/ IMAD.WIDE R12, R12, R13, c[0x0][0x168] ; /* 0x00005a000c0c7625 */
/* 0x000fc800078e020d */
/*0700*/ FADD R11, -R16, -RZ ; /* 0x800000ff100b7221 */
/* 0x004fca0000000100 */
/*0710*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x0003e8000c101908 */
/*0720*/ LDG.E R12, [R12.64] ; /* 0x000000080c0c7981 */
/* 0x000ea2000c1e1900 */
/*0730*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe40007ffe0ff */
/*0740*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe40007ffe0ff */
/*0750*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f25270 */
/*0760*/ FADD R15, -R12, -RZ ; /* 0x800000ff0c0f7221 */
/* 0x004fca0000000100 */
/*0770*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0003ee000c101908 */
/*0780*/ @P1 BRA 0x220 ; /* 0xfffffa9000001947 */
/* 0x000fea000383ffff */
/*0790*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*07a0*/ IABS R2, c[0x0][0x170] ; /* 0x00005c0000027a13 */
/* 0x001fe40000000000 */
/*07b0*/ SHF.R.S32.HI R4, RZ, 0x1f, R9 ; /* 0x0000001fff047819 */
/* 0x002fe40000011409 */
/*07c0*/ I2F.RP R3, R2 ; /* 0x0000000200037306 */
/* 0x000e220000209400 */
/*07d0*/ IADD3 R5, P0, R7, R9.reuse, RZ ; /* 0x0000000907057210 */
/* 0x080fe20007f1e0ff */
/*07e0*/ IMAD R9, R0, R9, RZ ; /* 0x0000000900097224 */
/* 0x000fc600078e02ff */
/*07f0*/ LEA.HI.X.SX32 R8, R7, R4, 0x1, P0 ; /* 0x0000000407087211 */
/* 0x000fe400000f0eff */
/*0800*/ LEA R4, P0, R5, c[0x0][0x160], 0x2 ; /* 0x0000580005047a11 */
/* 0x000fc800078010ff */
/*0810*/ LEA.HI.X R5, R5, c[0x0][0x164], R8, 0x2, P0 ; /* 0x0000590005057a11 */
/* 0x000fe200000f1408 */
/*0820*/ MUFU.RCP R3, R3 ; /* 0x0000000300037308 */
/* 0x001e240000001000 */
/*0830*/ IADD3 R10, R3, 0xffffffe, RZ ; /* 0x0ffffffe030a7810 */
/* 0x001fcc0007ffe0ff */
/*0840*/ F2I.FTZ.U32.TRUNC.NTZ R11, R10 ; /* 0x0000000a000b7305 */
/* 0x000064000021f000 */
/*0850*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e00ff */
/*0860*/ IMAD.MOV R13, RZ, RZ, -R11 ; /* 0x000000ffff0d7224 */
/* 0x002fc800078e0a0b */
/*0870*/ IMAD R7, R13, R2, RZ ; /* 0x000000020d077224 */
/* 0x000fc800078e02ff */
/*0880*/ IMAD.HI.U32 R12, R11, R7, R10 ; /* 0x000000070b0c7227 */
/* 0x000fc800078e000a */
/*0890*/ IABS R7, R9 ; /* 0x0000000900077213 */
/* 0x000fe20000000000 */
/*08a0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*08b0*/ IABS R10, c[0x0][0x170] ; /* 0x00005c00000a7a13 */
/* 0x000fe40000000000 */
/*08c0*/ ISETP.GE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f26270 */
/*08d0*/ IMAD.HI.U32 R3, R12, R7, RZ ; /* 0x000000070c037227 */
/* 0x000fe200078e00ff */
/*08e0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fc60003f45270 */
/*08f0*/ IMAD.MOV R8, RZ, RZ, -R3 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0a03 */
/*0900*/ IMAD R3, R10, R8, R7 ; /* 0x000000080a037224 */
/* 0x000fca00078e0207 */
/*0910*/ ISETP.GT.U32.AND P0, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fda0003f04070 */
/*0920*/ @!P0 IMAD.IADD R3, R3, 0x1, -R10 ; /* 0x0000000103038824 */
/* 0x000fca00078e0a0a */
/*0930*/ ISETP.GT.U32.AND P0, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fda0003f04070 */
/*0940*/ @!P0 IMAD.IADD R3, R3, 0x1, -R10 ; /* 0x0000000103038824 */
/* 0x000fc800078e0a0a */
/*0950*/ @!P1 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0a03 */
/*0960*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff03aa12 */
/* 0x000fc800078e33ff */
/*0970*/ LEA R10, R3, 0x1, 0x1 ; /* 0x00000001030a7811 */
/* 0x000fca00078e08ff */
/*0980*/ IMAD.WIDE R10, R10, R11, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x000fcc00078e020b */
/*0990*/ LDG.E R10, [R10.64] ; /* 0x000000080a0a7981 */
/* 0x000ea2000c1e1900 */
/*09a0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*09b0*/ IADD3 R3, P1, R4, 0x4, RZ ; /* 0x0000000404037810 */
/* 0x000fe40007f3e0ff */
/*09c0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc60003f05270 */
/*09d0*/ IMAD.X R7, RZ, RZ, R5, P1 ; /* 0x000000ffff077224 */
/* 0x000fe400008e0605 */
/*09e0*/ FADD R13, -R10, -RZ ; /* 0x800000ff0a0d7221 */
/* 0x004fca0000000100 */
/*09f0*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0001e6000c101908 */
/*0a00*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0a10*/ IADD3 R9, R0, R9, RZ ; /* 0x0000000900097210 */
/* 0x000fe20007ffe0ff */
/*0a20*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0003 */
/*0a30*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0007 */
/*0a40*/ BRA 0x890 ; /* 0xfffffe4000007947 */
/* 0x000fea000383ffff */
/*0a50*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff007624 */
/* 0x000fca00078e00ff */
/*0a60*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0a70*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0a80*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0a90*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0aa0*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe400078ec0ff */
/*0ab0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0ac0*/ @!P0 BRA 0xee0 ; /* 0x0000041000008947 */
/* 0x000fea0003800000 */
/*0ad0*/ IADD3 R4, -R0, c[0x0][0x170], RZ ; /* 0x00005c0000047a10 */
/* 0x000fe20007ffe1ff */
/*0ae0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0af0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe400078e00ff */
/*0b00*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f04270 */
/*0b10*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fd800078e00ff */
/*0b20*/ @!P0 BRA 0xe20 ; /* 0x000002f000008947 */
/* 0x000fea0003800000 */
/*0b30*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*0b40*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0b50*/ @!P1 BRA 0xcf0 ; /* 0x0000019000009947 */
/* 0x000fea0003800000 */
/*0b60*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0b70*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fe20007ffe0ff */
/*0b80*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*0b90*/ IADD3 R5, P2, R2, 0x40, RZ ; /* 0x0000004002057810 */
/* 0x000fe20007f5e0ff */
/*0ba0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101908 */
/*0bb0*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fc60003f24270 */
/*0bc0*/ IMAD.X R6, RZ, RZ, R3, P2 ; /* 0x000000ffff067224 */
/* 0x000fe200010e0603 */
/*0bd0*/ STG.E [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe8000c101908 */
/*0be0*/ STG.E [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x000fe8000c101908 */
/*0bf0*/ STG.E [R2.64+0xc], RZ ; /* 0x00000cff02007986 */
/* 0x000fe8000c101908 */
/*0c00*/ STG.E [R2.64+0x10], RZ ; /* 0x000010ff02007986 */
/* 0x000fe8000c101908 */
/*0c10*/ STG.E [R2.64+0x14], RZ ; /* 0x000014ff02007986 */
/* 0x000fe8000c101908 */
/*0c20*/ STG.E [R2.64+0x18], RZ ; /* 0x000018ff02007986 */
/* 0x000fe8000c101908 */
/*0c30*/ STG.E [R2.64+0x1c], RZ ; /* 0x00001cff02007986 */
/* 0x000fe8000c101908 */
/*0c40*/ STG.E [R2.64+0x20], RZ ; /* 0x000020ff02007986 */
/* 0x000fe8000c101908 */
/*0c50*/ STG.E [R2.64+0x24], RZ ; /* 0x000024ff02007986 */
/* 0x000fe8000c101908 */
/*0c60*/ STG.E [R2.64+0x28], RZ ; /* 0x000028ff02007986 */
/* 0x000fe8000c101908 */
/*0c70*/ STG.E [R2.64+0x2c], RZ ; /* 0x00002cff02007986 */
/* 0x000fe8000c101908 */
/*0c80*/ STG.E [R2.64+0x30], RZ ; /* 0x000030ff02007986 */
/* 0x000fe8000c101908 */
/*0c90*/ STG.E [R2.64+0x34], RZ ; /* 0x000034ff02007986 */
/* 0x000fe8000c101908 */
/*0ca0*/ STG.E [R2.64+0x38], RZ ; /* 0x000038ff02007986 */
/* 0x000fe8000c101908 */
/*0cb0*/ STG.E [R2.64+0x3c], RZ ; /* 0x00003cff02007986 */
/* 0x0001e4000c101908 */
/*0cc0*/ IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0005 */
/*0cd0*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0006 */
/*0ce0*/ @P1 BRA 0xb70 ; /* 0xfffffe8000001947 */
/* 0x000fea000383ffff */
/*0cf0*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*0d00*/ @!P1 BRA 0xe00 ; /* 0x000000f000009947 */
/* 0x000fea0003800000 */
/*0d10*/ IADD3 R5, P1, R2, 0x20, RZ ; /* 0x0000002002057810 */
/* 0x000fe20007f3e0ff */
/*0d20*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101908 */
/*0d30*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0d40*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0d50*/ IADD3.X R6, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff067210 */
/* 0x000fe20000ffe4ff */
/*0d60*/ STG.E [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe2000c101908 */
/*0d70*/ IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804047810 */
/* 0x000fc60007ffe0ff */
/*0d80*/ STG.E [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x000fe8000c101908 */
/*0d90*/ STG.E [R2.64+0xc], RZ ; /* 0x00000cff02007986 */
/* 0x000fe8000c101908 */
/*0da0*/ STG.E [R2.64+0x10], RZ ; /* 0x000010ff02007986 */
/* 0x000fe8000c101908 */
/*0db0*/ STG.E [R2.64+0x14], RZ ; /* 0x000014ff02007986 */
/* 0x000fe8000c101908 */
/*0dc0*/ STG.E [R2.64+0x18], RZ ; /* 0x000018ff02007986 */
/* 0x000fe8000c101908 */
/*0dd0*/ STG.E [R2.64+0x1c], RZ ; /* 0x00001cff02007986 */
/* 0x0001e4000c101908 */
/*0de0*/ IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0005 */
/*0df0*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0006 */
/*0e00*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705670 */
/*0e10*/ @!P0 BRA 0xee0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0e20*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe20007ffe0ff */
/*0e30*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0e40*/ IADD3 R5, P1, R2, 0x10, RZ ; /* 0x0000001002057810 */
/* 0x000fe20007f3e0ff */
/*0e50*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101908 */
/*0e60*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0e70*/ IMAD.X R6, RZ, RZ, R3, P1 ; /* 0x000000ffff067224 */
/* 0x000fe200008e0603 */
/*0e80*/ STG.E [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe8000c101908 */
/*0e90*/ STG.E [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x000fe8000c101908 */
/*0ea0*/ STG.E [R2.64+0xc], RZ ; /* 0x00000cff02007986 */
/* 0x0001e4000c101908 */
/*0eb0*/ IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0005 */
/*0ec0*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0006 */
/*0ed0*/ @P0 BRA 0xe20 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0ee0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0ef0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0f00*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe40000000000 */
/*0f10*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*0f20*/ UIMAD.WIDE UR4, UR4, UR5, UR6 ; /* 0x00000005040472a5 */
/* 0x000fcc000f8e0206 */
/*0f30*/ IMAD.U32 R2, RZ, RZ, UR4 ; /* 0x00000004ff027e24 */
/* 0x000fe2000f8e00ff */
/*0f40*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0f50*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x000fe2000f8e00ff */
/*0f60*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000ff1e03f */
/*0f70*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0f80*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101908 */
/*0f90*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fd400087fe43f */
/*0fa0*/ @P0 BRA 0xf30 ; /* 0xffffff8000000947 */
/* 0x001fea000383ffff */
/*0fb0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0fc0*/ BRA 0xfc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16twiddleImgKernelPfS_i
.globl _Z16twiddleImgKernelPfS_i
.p2align 8
.type _Z16twiddleImgKernelPfS_i,@function
_Z16twiddleImgKernelPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_9
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s5, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_5
v_mul_lo_u32 v2, v1, s4
v_mov_b32_e32 v0, 0
s_cmp_lt_i32 s4, 2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_store_b32 v[3:4], v0, off
s_cbranch_scc1 .LBB0_5
s_ashr_i32 s6, s4, 31
s_load_b64 s[0:1], s[0:1], 0x8
s_add_i32 s7, s4, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s6, s7, s6
v_cvt_f32_u32_e32 v0, s6
s_sub_i32 s7, 0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s7, v0
s_mov_b32 s7, 1
v_mul_hi_u32 v3, v0, v3
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v3, v1 :: v_dual_add_nc_u32 v0, v0, v3
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_add_nc_u32_e32 v5, v3, v4
v_add_nc_u32_e32 v3, v3, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v5, v5, v4
v_mul_hi_u32 v6, v5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, v6, s6
v_sub_nc_u32_e32 v5, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s6, v5
v_cmp_le_u32_e32 vcc_lo, s6, v5
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s6, v5
v_cmp_le_u32_e32 vcc_lo, s6, v5
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v5, v5, v4
v_sub_nc_u32_e32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_or_b32 v4, v4, 1, 1
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b32 v6, v[4:5], off
v_add_nc_u32_e32 v4, s7, v2
s_add_i32 s7, s7, 1
s_cmp_lg_u32 s4, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_waitcnt vmcnt(0)
v_xor_b32_e32 v6, 0x80000000, v6
global_store_b32 v[4:5], v6, off
s_cbranch_scc1 .LBB0_4
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_and_not1_saveexec_b32 s0, s5
s_cbranch_execz .LBB0_9
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_9
v_mov_b32_e32 v0, 0
.LBB0_8:
s_add_i32 s4, s4, -1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v0, s[2:3]
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s4, 0
s_cbranch_scc0 .LBB0_8
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16twiddleImgKernelPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16twiddleImgKernelPfS_i, .Lfunc_end0-_Z16twiddleImgKernelPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16twiddleImgKernelPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16twiddleImgKernelPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002e504_00000000-6_twiddleImgKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z16twiddleImgKernelPfS_iPfS_i
.type _Z39__device_stub__Z16twiddleImgKernelPfS_iPfS_i, @function
_Z39__device_stub__Z16twiddleImgKernelPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16twiddleImgKernelPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z16twiddleImgKernelPfS_iPfS_i, .-_Z39__device_stub__Z16twiddleImgKernelPfS_iPfS_i
.globl _Z16twiddleImgKernelPfS_i
.type _Z16twiddleImgKernelPfS_i, @function
_Z16twiddleImgKernelPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16twiddleImgKernelPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16twiddleImgKernelPfS_i, .-_Z16twiddleImgKernelPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16twiddleImgKernelPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16twiddleImgKernelPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "twiddleImgKernel.hip"
.globl _Z31__device_stub__twiddleImgKernelPfS_i # -- Begin function _Z31__device_stub__twiddleImgKernelPfS_i
.p2align 4, 0x90
.type _Z31__device_stub__twiddleImgKernelPfS_i,@function
_Z31__device_stub__twiddleImgKernelPfS_i: # @_Z31__device_stub__twiddleImgKernelPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16twiddleImgKernelPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z31__device_stub__twiddleImgKernelPfS_i, .Lfunc_end0-_Z31__device_stub__twiddleImgKernelPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16twiddleImgKernelPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16twiddleImgKernelPfS_i,@object # @_Z16twiddleImgKernelPfS_i
.section .rodata,"a",@progbits
.globl _Z16twiddleImgKernelPfS_i
.p2align 3, 0x0
_Z16twiddleImgKernelPfS_i:
.quad _Z31__device_stub__twiddleImgKernelPfS_i
.size _Z16twiddleImgKernelPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16twiddleImgKernelPfS_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__twiddleImgKernelPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16twiddleImgKernelPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void donothing()
{
/* Do nothing! */
return;
} | code for sm_80
Function : _Z9donothingv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void donothing()
{
/* Do nothing! */
return;
} | .file "tmpxft_0011a19d_00000000-6_donothing.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z9donothingvv
.type _Z27__device_stub__Z9donothingvv, @function
_Z27__device_stub__Z9donothingvv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z9donothingv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z9donothingvv, .-_Z27__device_stub__Z9donothingvv
.globl _Z9donothingv
.type _Z9donothingv, @function
_Z9donothingv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z9donothingvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9donothingv, .-_Z9donothingv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9donothingv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9donothingv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void donothing()
{
/* Do nothing! */
return;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void donothing()
{
/* Do nothing! */
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void donothing()
{
/* Do nothing! */
return;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9donothingv
.globl _Z9donothingv
.p2align 8
.type _Z9donothingv,@function
_Z9donothingv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9donothingv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9donothingv, .Lfunc_end0-_Z9donothingv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9donothingv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z9donothingv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void donothing()
{
/* Do nothing! */
return;
} | .text
.file "donothing.hip"
.globl _Z24__device_stub__donothingv # -- Begin function _Z24__device_stub__donothingv
.p2align 4, 0x90
.type _Z24__device_stub__donothingv,@function
_Z24__device_stub__donothingv: # @_Z24__device_stub__donothingv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9donothingv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z24__device_stub__donothingv, .Lfunc_end0-_Z24__device_stub__donothingv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9donothingv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9donothingv,@object # @_Z9donothingv
.section .rodata,"a",@progbits
.globl _Z9donothingv
.p2align 3, 0x0
_Z9donothingv:
.quad _Z24__device_stub__donothingv
.size _Z9donothingv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9donothingv"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__donothingv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9donothingv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9donothingv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9donothingv
.globl _Z9donothingv
.p2align 8
.type _Z9donothingv,@function
_Z9donothingv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9donothingv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9donothingv, .Lfunc_end0-_Z9donothingv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9donothingv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z9donothingv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011a19d_00000000-6_donothing.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z9donothingvv
.type _Z27__device_stub__Z9donothingvv, @function
_Z27__device_stub__Z9donothingvv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z9donothingv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z9donothingvv, .-_Z27__device_stub__Z9donothingvv
.globl _Z9donothingv
.type _Z9donothingv, @function
_Z9donothingv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z9donothingvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9donothingv, .-_Z9donothingv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9donothingv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9donothingv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "donothing.hip"
.globl _Z24__device_stub__donothingv # -- Begin function _Z24__device_stub__donothingv
.p2align 4, 0x90
.type _Z24__device_stub__donothingv,@function
_Z24__device_stub__donothingv: # @_Z24__device_stub__donothingv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9donothingv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z24__device_stub__donothingv, .Lfunc_end0-_Z24__device_stub__donothingv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9donothingv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9donothingv,@object # @_Z9donothingv
.section .rodata,"a",@progbits
.globl _Z9donothingv
.p2align 3, 0x0
_Z9donothingv:
.quad _Z24__device_stub__donothingv
.size _Z9donothingv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9donothingv"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__donothingv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9donothingv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <fstream>
#include <string>
#include <stdio.h>
#include <stdlib.h>
using namespace std;
#include <iterator>
#include <algorithm>
#include <random>
#include <math.h>
// Cada thread deberia calcular la carga de 1 punto
__global__ void calcular_carga(float* iones_x, float* iones_y, float* cargas, int cantidad) {
int tId = threadIdx.x + blockIdx.x * blockDim.x;
if(tId < 8192*8192) {
float x = tId%8192;
float y = tId/8192;
float carga = 0;
float distancia;
float x_2, y_2;
for (int i = 0; i < cantidad; i++) {
x_2 = (x - iones_x[i]) * (x - iones_x[i]);
y_2 = (y - iones_y[i]) * (y - iones_y[i]);
distancia = sqrt(x_2 + y_2);
carga += distancia != 0 ? 1.0 / distancia : 1;
}
cargas[tId] = carga;
}
}
// cada thread calcula la menor carga en su fila y la guarda
__global__ void calcular_carga_fila(float* iones_x, float* iones_y, float* cargas, float*cargas_menores, int cantidad) {
int tId = threadIdx.x + blockIdx.x * blockDim.x;
if(tId < 8192) {
float Q_menor = cargas[tId*8192];
float y = tId;
float x;
for (int i = tId*8192; i < tId*8192+8192; i++) {
if(cargas[i] <Q_menor){
Q_menor = cargas[i];
x = i%8192;
}
}
cargas_menores[tId*3] = Q_menor;
cargas_menores[tId*3+1] = x;
cargas_menores[tId*3+2] = y;
}
}
// Calculamos entre todas la menor y ponemos la carga ahí
__global__ void posicionar_ion(float* iones_x, float* iones_y, float*cargas_menores, int cantidad) {
int tId = threadIdx.x + blockIdx.x * blockDim.x;
if(tId < 1) {
float Q_menor = cargas_menores[0];
float x = cargas_menores[1];
float y = cargas_menores[2];
for (int i = 0; i < 8192*3; i+=3) {
if(cargas_menores[i] < Q_menor){
Q_menor = cargas_menores[i];
x = cargas_menores[i+1];
y = cargas_menores[i+2];
}
// printf("%f %f %f %f\n", cargas_menores[i], Q_menor, cargas_menores[i+1], cargas_menores[i+2]);
}
iones_x[cantidad] = x;
iones_y[cantidad] = y;
}
}
int main(int argc, char const *argv[])
{
float *gpu_cargas, *cargas_menores, *gpu_iones_x, *gpu_iones_y, *iones_x, *iones_y;
cudaEvent_t ct1, ct2;
float dt;
int cantidad;
iones_x = new float[6000];
iones_y = new float[6000];
int block_size = 256;
int grid_size = (int) ceil( (float) 8192*8192 / block_size);
int grid_size_b = (int) ceil( (float) 8192 / block_size);
int grid_size_c = (int) ceil( (float) 1 / block_size);
FILE *in = fopen("dataset", "r");
for (int i = 0; i < 5000; i++)
{
fscanf(in, "%f %f", &iones_x[i], &iones_y[i]);
}
cudaMalloc(&gpu_iones_x, sizeof(float) * 6000);
cudaMalloc(&gpu_iones_y, sizeof(float) * 6000);
cudaMalloc(&gpu_cargas, sizeof(float) * 8192 * 8192);
cudaMalloc(&cargas_menores, sizeof(float) * 8192*3);
cudaMemcpy(gpu_iones_x, iones_x ,sizeof(float) * 6000, cudaMemcpyHostToDevice);
cudaMemcpy(gpu_iones_y, iones_y ,sizeof(float) * 6000, cudaMemcpyHostToDevice);
cudaEventCreate(&ct1);
cudaEventCreate(&ct2);
cudaEventRecord(ct1);
for (cantidad = 5000; cantidad < 5010; cantidad++)
{
calcular_carga<<<grid_size, block_size>>>(gpu_iones_x, gpu_iones_y, gpu_cargas, cantidad);
cudaDeviceSynchronize();
calcular_carga_fila<<<grid_size_b, block_size>>>(gpu_iones_x, gpu_iones_y, gpu_cargas, cargas_menores, cantidad);
cudaDeviceSynchronize();
posicionar_ion<<<grid_size_c, block_size>>>(gpu_iones_x, gpu_iones_y, cargas_menores, cantidad);
cudaDeviceSynchronize();
cudaMemcpy(iones_x, gpu_iones_x,sizeof(float) * 6000, cudaMemcpyDeviceToHost);
cudaMemcpy(iones_y, gpu_iones_y,sizeof(float) * 6000, cudaMemcpyDeviceToHost);
cout << iones_x[cantidad] << " " << iones_y[cantidad] << endl;
}
cudaEventRecord(ct2);
cudaEventSynchronize(ct2);
cudaEventElapsedTime(&dt, ct1, ct2);
cout << "Tiempo: " << dt << "[ms]" << '\n';
cudaFree(gpu_iones_x);
cudaFree(gpu_iones_y);
cudaFree(gpu_cargas);
cudaFree(cargas_menores);
cudaFree(gpu_iones_x);
cudaFree(gpu_iones_y);
delete iones_x;
delete iones_y;
return 0;
} | .file "tmpxft_000a30c7_00000000-6_kernel1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB5122:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5122:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z14calcular_cargaPfS_S_iPfS_S_i
.type _Z39__device_stub__Z14calcular_cargaPfS_S_iPfS_S_i, @function
_Z39__device_stub__Z14calcular_cargaPfS_S_iPfS_S_i:
.LFB5144:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14calcular_cargaPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5144:
.size _Z39__device_stub__Z14calcular_cargaPfS_S_iPfS_S_i, .-_Z39__device_stub__Z14calcular_cargaPfS_S_iPfS_S_i
.globl _Z14calcular_cargaPfS_S_i
.type _Z14calcular_cargaPfS_S_i, @function
_Z14calcular_cargaPfS_S_i:
.LFB5145:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14calcular_cargaPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5145:
.size _Z14calcular_cargaPfS_S_i, .-_Z14calcular_cargaPfS_S_i
.globl _Z46__device_stub__Z19calcular_carga_filaPfS_S_S_iPfS_S_S_i
.type _Z46__device_stub__Z19calcular_carga_filaPfS_S_S_iPfS_S_S_i, @function
_Z46__device_stub__Z19calcular_carga_filaPfS_S_S_iPfS_S_S_i:
.LFB5146:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19calcular_carga_filaPfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5146:
.size _Z46__device_stub__Z19calcular_carga_filaPfS_S_S_iPfS_S_S_i, .-_Z46__device_stub__Z19calcular_carga_filaPfS_S_S_iPfS_S_S_i
.globl _Z19calcular_carga_filaPfS_S_S_i
.type _Z19calcular_carga_filaPfS_S_S_i, @function
_Z19calcular_carga_filaPfS_S_S_i:
.LFB5147:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z19calcular_carga_filaPfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5147:
.size _Z19calcular_carga_filaPfS_S_S_i, .-_Z19calcular_carga_filaPfS_S_S_i
.globl _Z39__device_stub__Z14posicionar_ionPfS_S_iPfS_S_i
.type _Z39__device_stub__Z14posicionar_ionPfS_S_iPfS_S_i, @function
_Z39__device_stub__Z14posicionar_ionPfS_S_iPfS_S_i:
.LFB5148:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14posicionar_ionPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5148:
.size _Z39__device_stub__Z14posicionar_ionPfS_S_iPfS_S_i, .-_Z39__device_stub__Z14posicionar_ionPfS_S_iPfS_S_i
.globl _Z14posicionar_ionPfS_S_i
.type _Z14posicionar_ionPfS_S_i, @function
_Z14posicionar_ionPfS_S_i:
.LFB5149:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14posicionar_ionPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5149:
.size _Z14posicionar_ionPfS_S_i, .-_Z14posicionar_ionPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "dataset"
.LC2:
.string "%f %f"
.LC3:
.string " "
.LC4:
.string "Tiempo: "
.LC5:
.string "[ms]"
.text
.globl main
.type main, @function
main:
.LFB5119:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $24000, %edi
call _Znam@PLT
movq %rax, %r15
movl $24000, %edi
call _Znam@PLT
movq %rax, %rbp
movq %rax, 8(%rsp)
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movq %r15, %rbx
leaq 20000(%r15), %r14
leaq .LC2(%rip), %r13
.L28:
movq %rbp, %rcx
movq %rbx, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $4, %rbx
addq $4, %rbp
cmpq %r14, %rbx
jne .L28
leaq 32(%rsp), %rdi
movl $24000, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $24000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $268435456, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $98304, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $24000, %edx
movq %r15, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $24000, %edx
movq 8(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $5000, %ebx
leaq _ZSt4cout(%rip), %r13
leaq .LC3(%rip), %r14
jmp .L36
.L43:
movl %ebx, %ecx
movq 16(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z39__device_stub__Z14calcular_cargaPfS_S_iPfS_S_i
jmp .L29
.L44:
movl %ebp, %r8d
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z46__device_stub__Z19calcular_carga_filaPfS_S_S_iPfS_S_S_i
jmp .L30
.L45:
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z39__device_stub__Z14posicionar_ionPfS_S_iPfS_S_i
jmp .L31
.L46:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L41
call _ZSt16__throw_bad_castv@PLT
.L41:
call __stack_chk_fail@PLT
.L34:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L35:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbx
cmpq $5010, %rbx
je .L42
.L36:
movl %ebx, %ebp
movl $256, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $262144, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L29:
call cudaDeviceSynchronize@PLT
movl $256, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $32, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L44
.L30:
call cudaDeviceSynchronize@PLT
movl $256, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L31:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $24000, %edx
movq 32(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $24000, %edx
movq 40(%rsp), %rsi
movq 8(%rsp), %r12
movq %r12, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L46
cmpb $0, 56(%r12)
je .L34
movzbl 67(%r12), %esi
jmp .L35
.L42:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 76(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 76(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movl $4, %esi
movq %r15, %rdi
call _ZdlPvm@PLT
movl $4, %esi
movq 8(%rsp), %rdi
call _ZdlPvm@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L47
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5119:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z14posicionar_ionPfS_S_i"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "_Z19calcular_carga_filaPfS_S_S_i"
.section .rodata.str1.1
.LC8:
.string "_Z14calcular_cargaPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB5151:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z14posicionar_ionPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z19calcular_carga_filaPfS_S_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z14calcular_cargaPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5151:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <fstream>
#include <string>
#include <stdio.h>
#include <stdlib.h>
using namespace std;
#include <iterator>
#include <algorithm>
#include <random>
#include <math.h>
// Cada thread deberia calcular la carga de 1 punto
__global__ void calcular_carga(float* iones_x, float* iones_y, float* cargas, int cantidad) {
int tId = threadIdx.x + blockIdx.x * blockDim.x;
if(tId < 8192*8192) {
float x = tId%8192;
float y = tId/8192;
float carga = 0;
float distancia;
float x_2, y_2;
for (int i = 0; i < cantidad; i++) {
x_2 = (x - iones_x[i]) * (x - iones_x[i]);
y_2 = (y - iones_y[i]) * (y - iones_y[i]);
distancia = sqrt(x_2 + y_2);
carga += distancia != 0 ? 1.0 / distancia : 1;
}
cargas[tId] = carga;
}
}
// cada thread calcula la menor carga en su fila y la guarda
__global__ void calcular_carga_fila(float* iones_x, float* iones_y, float* cargas, float*cargas_menores, int cantidad) {
int tId = threadIdx.x + blockIdx.x * blockDim.x;
if(tId < 8192) {
float Q_menor = cargas[tId*8192];
float y = tId;
float x;
for (int i = tId*8192; i < tId*8192+8192; i++) {
if(cargas[i] <Q_menor){
Q_menor = cargas[i];
x = i%8192;
}
}
cargas_menores[tId*3] = Q_menor;
cargas_menores[tId*3+1] = x;
cargas_menores[tId*3+2] = y;
}
}
// Calculamos entre todas la menor y ponemos la carga ahí
__global__ void posicionar_ion(float* iones_x, float* iones_y, float*cargas_menores, int cantidad) {
int tId = threadIdx.x + blockIdx.x * blockDim.x;
if(tId < 1) {
float Q_menor = cargas_menores[0];
float x = cargas_menores[1];
float y = cargas_menores[2];
for (int i = 0; i < 8192*3; i+=3) {
if(cargas_menores[i] < Q_menor){
Q_menor = cargas_menores[i];
x = cargas_menores[i+1];
y = cargas_menores[i+2];
}
// printf("%f %f %f %f\n", cargas_menores[i], Q_menor, cargas_menores[i+1], cargas_menores[i+2]);
}
iones_x[cantidad] = x;
iones_y[cantidad] = y;
}
}
int main(int argc, char const *argv[])
{
float *gpu_cargas, *cargas_menores, *gpu_iones_x, *gpu_iones_y, *iones_x, *iones_y;
cudaEvent_t ct1, ct2;
float dt;
int cantidad;
iones_x = new float[6000];
iones_y = new float[6000];
int block_size = 256;
int grid_size = (int) ceil( (float) 8192*8192 / block_size);
int grid_size_b = (int) ceil( (float) 8192 / block_size);
int grid_size_c = (int) ceil( (float) 1 / block_size);
FILE *in = fopen("dataset", "r");
for (int i = 0; i < 5000; i++)
{
fscanf(in, "%f %f", &iones_x[i], &iones_y[i]);
}
cudaMalloc(&gpu_iones_x, sizeof(float) * 6000);
cudaMalloc(&gpu_iones_y, sizeof(float) * 6000);
cudaMalloc(&gpu_cargas, sizeof(float) * 8192 * 8192);
cudaMalloc(&cargas_menores, sizeof(float) * 8192*3);
cudaMemcpy(gpu_iones_x, iones_x ,sizeof(float) * 6000, cudaMemcpyHostToDevice);
cudaMemcpy(gpu_iones_y, iones_y ,sizeof(float) * 6000, cudaMemcpyHostToDevice);
cudaEventCreate(&ct1);
cudaEventCreate(&ct2);
cudaEventRecord(ct1);
for (cantidad = 5000; cantidad < 5010; cantidad++)
{
calcular_carga<<<grid_size, block_size>>>(gpu_iones_x, gpu_iones_y, gpu_cargas, cantidad);
cudaDeviceSynchronize();
calcular_carga_fila<<<grid_size_b, block_size>>>(gpu_iones_x, gpu_iones_y, gpu_cargas, cargas_menores, cantidad);
cudaDeviceSynchronize();
posicionar_ion<<<grid_size_c, block_size>>>(gpu_iones_x, gpu_iones_y, cargas_menores, cantidad);
cudaDeviceSynchronize();
cudaMemcpy(iones_x, gpu_iones_x,sizeof(float) * 6000, cudaMemcpyDeviceToHost);
cudaMemcpy(iones_y, gpu_iones_y,sizeof(float) * 6000, cudaMemcpyDeviceToHost);
cout << iones_x[cantidad] << " " << iones_y[cantidad] << endl;
}
cudaEventRecord(ct2);
cudaEventSynchronize(ct2);
cudaEventElapsedTime(&dt, ct1, ct2);
cout << "Tiempo: " << dt << "[ms]" << '\n';
cudaFree(gpu_iones_x);
cudaFree(gpu_iones_y);
cudaFree(gpu_cargas);
cudaFree(cargas_menores);
cudaFree(gpu_iones_x);
cudaFree(gpu_iones_y);
delete iones_x;
delete iones_y;
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <string>
#include <stdio.h>
#include <stdlib.h>
using namespace std;
#include <iterator>
#include <algorithm>
#include <random>
#include <math.h>
// Cada thread deberia calcular la carga de 1 punto
__global__ void calcular_carga(float* iones_x, float* iones_y, float* cargas, int cantidad) {
int tId = threadIdx.x + blockIdx.x * blockDim.x;
if(tId < 8192*8192) {
float x = tId%8192;
float y = tId/8192;
float carga = 0;
float distancia;
float x_2, y_2;
for (int i = 0; i < cantidad; i++) {
x_2 = (x - iones_x[i]) * (x - iones_x[i]);
y_2 = (y - iones_y[i]) * (y - iones_y[i]);
distancia = sqrt(x_2 + y_2);
carga += distancia != 0 ? 1.0 / distancia : 1;
}
cargas[tId] = carga;
}
}
// cada thread calcula la menor carga en su fila y la guarda
__global__ void calcular_carga_fila(float* iones_x, float* iones_y, float* cargas, float*cargas_menores, int cantidad) {
int tId = threadIdx.x + blockIdx.x * blockDim.x;
if(tId < 8192) {
float Q_menor = cargas[tId*8192];
float y = tId;
float x;
for (int i = tId*8192; i < tId*8192+8192; i++) {
if(cargas[i] <Q_menor){
Q_menor = cargas[i];
x = i%8192;
}
}
cargas_menores[tId*3] = Q_menor;
cargas_menores[tId*3+1] = x;
cargas_menores[tId*3+2] = y;
}
}
// Calculamos entre todas la menor y ponemos la carga ahí
__global__ void posicionar_ion(float* iones_x, float* iones_y, float*cargas_menores, int cantidad) {
int tId = threadIdx.x + blockIdx.x * blockDim.x;
if(tId < 1) {
float Q_menor = cargas_menores[0];
float x = cargas_menores[1];
float y = cargas_menores[2];
for (int i = 0; i < 8192*3; i+=3) {
if(cargas_menores[i] < Q_menor){
Q_menor = cargas_menores[i];
x = cargas_menores[i+1];
y = cargas_menores[i+2];
}
// printf("%f %f %f %f\n", cargas_menores[i], Q_menor, cargas_menores[i+1], cargas_menores[i+2]);
}
iones_x[cantidad] = x;
iones_y[cantidad] = y;
}
}
int main(int argc, char const *argv[])
{
float *gpu_cargas, *cargas_menores, *gpu_iones_x, *gpu_iones_y, *iones_x, *iones_y;
hipEvent_t ct1, ct2;
float dt;
int cantidad;
iones_x = new float[6000];
iones_y = new float[6000];
int block_size = 256;
int grid_size = (int) ceil( (float) 8192*8192 / block_size);
int grid_size_b = (int) ceil( (float) 8192 / block_size);
int grid_size_c = (int) ceil( (float) 1 / block_size);
FILE *in = fopen("dataset", "r");
for (int i = 0; i < 5000; i++)
{
fscanf(in, "%f %f", &iones_x[i], &iones_y[i]);
}
hipMalloc(&gpu_iones_x, sizeof(float) * 6000);
hipMalloc(&gpu_iones_y, sizeof(float) * 6000);
hipMalloc(&gpu_cargas, sizeof(float) * 8192 * 8192);
hipMalloc(&cargas_menores, sizeof(float) * 8192*3);
hipMemcpy(gpu_iones_x, iones_x ,sizeof(float) * 6000, hipMemcpyHostToDevice);
hipMemcpy(gpu_iones_y, iones_y ,sizeof(float) * 6000, hipMemcpyHostToDevice);
hipEventCreate(&ct1);
hipEventCreate(&ct2);
hipEventRecord(ct1);
for (cantidad = 5000; cantidad < 5010; cantidad++)
{
calcular_carga<<<grid_size, block_size>>>(gpu_iones_x, gpu_iones_y, gpu_cargas, cantidad);
hipDeviceSynchronize();
calcular_carga_fila<<<grid_size_b, block_size>>>(gpu_iones_x, gpu_iones_y, gpu_cargas, cargas_menores, cantidad);
hipDeviceSynchronize();
posicionar_ion<<<grid_size_c, block_size>>>(gpu_iones_x, gpu_iones_y, cargas_menores, cantidad);
hipDeviceSynchronize();
hipMemcpy(iones_x, gpu_iones_x,sizeof(float) * 6000, hipMemcpyDeviceToHost);
hipMemcpy(iones_y, gpu_iones_y,sizeof(float) * 6000, hipMemcpyDeviceToHost);
cout << iones_x[cantidad] << " " << iones_y[cantidad] << endl;
}
hipEventRecord(ct2);
hipEventSynchronize(ct2);
hipEventElapsedTime(&dt, ct1, ct2);
cout << "Tiempo: " << dt << "[ms]" << '\n';
hipFree(gpu_iones_x);
hipFree(gpu_iones_y);
hipFree(gpu_cargas);
hipFree(cargas_menores);
hipFree(gpu_iones_x);
hipFree(gpu_iones_y);
delete iones_x;
delete iones_y;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <string>
#include <stdio.h>
#include <stdlib.h>
using namespace std;
#include <iterator>
#include <algorithm>
#include <random>
#include <math.h>
// Cada thread deberia calcular la carga de 1 punto
__global__ void calcular_carga(float* iones_x, float* iones_y, float* cargas, int cantidad) {
int tId = threadIdx.x + blockIdx.x * blockDim.x;
if(tId < 8192*8192) {
float x = tId%8192;
float y = tId/8192;
float carga = 0;
float distancia;
float x_2, y_2;
for (int i = 0; i < cantidad; i++) {
x_2 = (x - iones_x[i]) * (x - iones_x[i]);
y_2 = (y - iones_y[i]) * (y - iones_y[i]);
distancia = sqrt(x_2 + y_2);
carga += distancia != 0 ? 1.0 / distancia : 1;
}
cargas[tId] = carga;
}
}
// cada thread calcula la menor carga en su fila y la guarda
__global__ void calcular_carga_fila(float* iones_x, float* iones_y, float* cargas, float*cargas_menores, int cantidad) {
int tId = threadIdx.x + blockIdx.x * blockDim.x;
if(tId < 8192) {
float Q_menor = cargas[tId*8192];
float y = tId;
float x;
for (int i = tId*8192; i < tId*8192+8192; i++) {
if(cargas[i] <Q_menor){
Q_menor = cargas[i];
x = i%8192;
}
}
cargas_menores[tId*3] = Q_menor;
cargas_menores[tId*3+1] = x;
cargas_menores[tId*3+2] = y;
}
}
// Calculamos entre todas la menor y ponemos la carga ahí
__global__ void posicionar_ion(float* iones_x, float* iones_y, float*cargas_menores, int cantidad) {
int tId = threadIdx.x + blockIdx.x * blockDim.x;
if(tId < 1) {
float Q_menor = cargas_menores[0];
float x = cargas_menores[1];
float y = cargas_menores[2];
for (int i = 0; i < 8192*3; i+=3) {
if(cargas_menores[i] < Q_menor){
Q_menor = cargas_menores[i];
x = cargas_menores[i+1];
y = cargas_menores[i+2];
}
// printf("%f %f %f %f\n", cargas_menores[i], Q_menor, cargas_menores[i+1], cargas_menores[i+2]);
}
iones_x[cantidad] = x;
iones_y[cantidad] = y;
}
}
int main(int argc, char const *argv[])
{
float *gpu_cargas, *cargas_menores, *gpu_iones_x, *gpu_iones_y, *iones_x, *iones_y;
hipEvent_t ct1, ct2;
float dt;
int cantidad;
iones_x = new float[6000];
iones_y = new float[6000];
int block_size = 256;
int grid_size = (int) ceil( (float) 8192*8192 / block_size);
int grid_size_b = (int) ceil( (float) 8192 / block_size);
int grid_size_c = (int) ceil( (float) 1 / block_size);
FILE *in = fopen("dataset", "r");
for (int i = 0; i < 5000; i++)
{
fscanf(in, "%f %f", &iones_x[i], &iones_y[i]);
}
hipMalloc(&gpu_iones_x, sizeof(float) * 6000);
hipMalloc(&gpu_iones_y, sizeof(float) * 6000);
hipMalloc(&gpu_cargas, sizeof(float) * 8192 * 8192);
hipMalloc(&cargas_menores, sizeof(float) * 8192*3);
hipMemcpy(gpu_iones_x, iones_x ,sizeof(float) * 6000, hipMemcpyHostToDevice);
hipMemcpy(gpu_iones_y, iones_y ,sizeof(float) * 6000, hipMemcpyHostToDevice);
hipEventCreate(&ct1);
hipEventCreate(&ct2);
hipEventRecord(ct1);
for (cantidad = 5000; cantidad < 5010; cantidad++)
{
calcular_carga<<<grid_size, block_size>>>(gpu_iones_x, gpu_iones_y, gpu_cargas, cantidad);
hipDeviceSynchronize();
calcular_carga_fila<<<grid_size_b, block_size>>>(gpu_iones_x, gpu_iones_y, gpu_cargas, cargas_menores, cantidad);
hipDeviceSynchronize();
posicionar_ion<<<grid_size_c, block_size>>>(gpu_iones_x, gpu_iones_y, cargas_menores, cantidad);
hipDeviceSynchronize();
hipMemcpy(iones_x, gpu_iones_x,sizeof(float) * 6000, hipMemcpyDeviceToHost);
hipMemcpy(iones_y, gpu_iones_y,sizeof(float) * 6000, hipMemcpyDeviceToHost);
cout << iones_x[cantidad] << " " << iones_y[cantidad] << endl;
}
hipEventRecord(ct2);
hipEventSynchronize(ct2);
hipEventElapsedTime(&dt, ct1, ct2);
cout << "Tiempo: " << dt << "[ms]" << '\n';
hipFree(gpu_iones_x);
hipFree(gpu_iones_y);
hipFree(gpu_cargas);
hipFree(cargas_menores);
hipFree(gpu_iones_x);
hipFree(gpu_iones_y);
delete iones_x;
delete iones_y;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14calcular_cargaPfS_S_i
.globl _Z14calcular_cargaPfS_S_i
.p2align 8
.type _Z14calcular_cargaPfS_S_i,@function
_Z14calcular_cargaPfS_S_i:
s_load_b32 s2, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x4000000, v1
s_cbranch_execz .LBB0_8
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_6
v_ashrrev_i32_e32 v0, 31, v1
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v0, 19, v0
v_add_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v0, 13, v0
v_mul_i32_i24_e32 v2, 0x2000, v0
v_cvt_f32_i32_e32 v4, v0
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v1, v2
v_cvt_f32_i32_e32 v5, v2
s_branch .LBB0_4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
v_cvt_f64_f32_e32 v[6:7], v0
s_add_i32 s3, s3, -1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[6:7]
v_cvt_f32_f64_e32 v0, v[2:3]
s_cbranch_scc1 .LBB0_7
.LBB0_4:
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[6:7], 0x0
s_load_b32 s8, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_dual_subrev_f32 v2, s2, v4 :: v_dual_subrev_f32 v3, s8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, v2, v2
v_fmac_f32_e32 v2, v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v3, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v6, -1, v3
v_add_nc_u32_e32 v7, 1, v3
v_fma_f32 v8, -v6, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v9, -v7, v3, v2
v_cmp_ge_f32_e64 s2, 0, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, v3, v6, s2
v_cmp_lt_f32_e64 s2, 0, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v7, s2
s_mov_b32 s2, exec_lo
v_mul_f32_e32 v6, 0x37800000, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
v_cndmask_b32_e32 v6, v3, v2, vcc_lo
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0x3ff00000
s_delay_alu instid0(VALU_DEP_3)
v_cmpx_neq_f32_e32 0, v6
s_cbranch_execz .LBB0_3
v_cvt_f64_f32_e32 v[2:3], v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[6:7], null, v[2:3], v[2:3], 1.0
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_div_scale_f64 v[10:11], vcc_lo, 1.0, v[2:3], 1.0
v_mul_f64 v[12:13], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f64 v[2:3], v[6:7], v[2:3], 1.0
s_branch .LBB0_3
.LBB0_6:
v_mov_b32_e32 v0, 0
.LBB0_7:
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14calcular_cargaPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14calcular_cargaPfS_S_i, .Lfunc_end0-_Z14calcular_cargaPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z19calcular_carga_filaPfS_S_S_i
.globl _Z19calcular_carga_filaPfS_S_S_i
.p2align 8
.type _Z19calcular_carga_filaPfS_S_S_i,@function
_Z19calcular_carga_filaPfS_S_S_i:
s_load_b32 s2, s[0:1], 0x34
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
v_cmpx_gt_i32_e32 0x2000, v3
s_cbranch_execz .LBB1_6
s_load_b64 s[4:5], s[0:1], 0x10
v_lshlrev_b32_e32 v1, 13, v3
v_lshlrev_b32_e32 v0, 13, v0
s_mul_i32 s15, s15, s2
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_lshl_add_u32 v0, s15, 13, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v2, vcc_lo
global_load_b32 v1, v[4:5], off
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s3
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s2, 0x2000
s_cbranch_scc1 .LBB1_5
.LBB1_3:
global_load_b32 v6, v[4:5], off
s_mov_b32 s3, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 v6, v1
s_cbranch_execz .LBB1_2
v_add_nc_u32_e32 v1, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshrrev_b32_e32 v2, 19, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v1, v2
v_and_b32_e32 v2, 0xffffe000, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v1, v2
v_cvt_f32_i32_e32 v2, v1
v_mov_b32_e32 v1, v6
s_branch .LBB1_2
.LBB1_5:
s_load_b64 s[0:1], s[0:1], 0x18
v_lshl_add_u32 v4, v3, 1, v3
v_cvt_f32_i32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_store_b96 v[4:5], v[1:3], off
.LBB1_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19calcular_carga_filaPfS_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z19calcular_carga_filaPfS_S_S_i, .Lfunc_end1-_Z19calcular_carga_filaPfS_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14posicionar_ionPfS_S_i
.globl _Z14posicionar_ionPfS_S_i
.p2align 8
.type _Z14posicionar_ionPfS_S_i,@function
_Z14posicionar_ionPfS_S_i:
s_load_b32 s2, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 1, v1
s_cbranch_execz .LBB2_6
s_load_b64 s[4:5], s[0:1], 0x10
s_mov_b32 s8, -3
s_waitcnt lgkmcnt(0)
s_clause 0x1
s_load_b64 s[6:7], s[4:5], 0x0
s_load_b32 s3, s[4:5], 0x8
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_waitcnt lgkmcnt(0)
s_mov_b32 s2, s7
s_branch .LBB2_3
.p2align 6
.LBB2_2:
s_add_i32 s8, s8, 3
s_add_u32 s4, s4, 12
s_addc_u32 s5, s5, 0
s_cmpk_gt_u32 s8, 0x5ffc
s_cbranch_scc1 .LBB2_5
.LBB2_3:
s_add_u32 s10, s4, -4
s_addc_u32 s11, s5, -1
s_load_b32 s7, s[10:11], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_nlt_f32_e64 s9, s7, s6
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz .LBB2_2
s_load_b64 s[2:3], s[4:5], 0x0
s_mov_b32 s6, s7
s_branch .LBB2_2
.LBB2_5:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
v_mov_b32_e32 v2, s3
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[8:9], 2
s_add_u32 s2, s4, s0
s_addc_u32 s3, s5, s1
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_clause 0x1
global_store_b32 v0, v1, s[2:3]
global_store_b32 v0, v2, s[0:1]
.LBB2_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14posicionar_ionPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z14posicionar_ionPfS_S_i, .Lfunc_end2-_Z14posicionar_ionPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14calcular_cargaPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14calcular_cargaPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19calcular_carga_filaPfS_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19calcular_carga_filaPfS_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14posicionar_ionPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14posicionar_ionPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <string>
#include <stdio.h>
#include <stdlib.h>
using namespace std;
#include <iterator>
#include <algorithm>
#include <random>
#include <math.h>
// Cada thread deberia calcular la carga de 1 punto
__global__ void calcular_carga(float* iones_x, float* iones_y, float* cargas, int cantidad) {
int tId = threadIdx.x + blockIdx.x * blockDim.x;
if(tId < 8192*8192) {
float x = tId%8192;
float y = tId/8192;
float carga = 0;
float distancia;
float x_2, y_2;
for (int i = 0; i < cantidad; i++) {
x_2 = (x - iones_x[i]) * (x - iones_x[i]);
y_2 = (y - iones_y[i]) * (y - iones_y[i]);
distancia = sqrt(x_2 + y_2);
carga += distancia != 0 ? 1.0 / distancia : 1;
}
cargas[tId] = carga;
}
}
// cada thread calcula la menor carga en su fila y la guarda
__global__ void calcular_carga_fila(float* iones_x, float* iones_y, float* cargas, float*cargas_menores, int cantidad) {
int tId = threadIdx.x + blockIdx.x * blockDim.x;
if(tId < 8192) {
float Q_menor = cargas[tId*8192];
float y = tId;
float x;
for (int i = tId*8192; i < tId*8192+8192; i++) {
if(cargas[i] <Q_menor){
Q_menor = cargas[i];
x = i%8192;
}
}
cargas_menores[tId*3] = Q_menor;
cargas_menores[tId*3+1] = x;
cargas_menores[tId*3+2] = y;
}
}
// Calculamos entre todas la menor y ponemos la carga ahí
__global__ void posicionar_ion(float* iones_x, float* iones_y, float*cargas_menores, int cantidad) {
int tId = threadIdx.x + blockIdx.x * blockDim.x;
if(tId < 1) {
float Q_menor = cargas_menores[0];
float x = cargas_menores[1];
float y = cargas_menores[2];
for (int i = 0; i < 8192*3; i+=3) {
if(cargas_menores[i] < Q_menor){
Q_menor = cargas_menores[i];
x = cargas_menores[i+1];
y = cargas_menores[i+2];
}
// printf("%f %f %f %f\n", cargas_menores[i], Q_menor, cargas_menores[i+1], cargas_menores[i+2]);
}
iones_x[cantidad] = x;
iones_y[cantidad] = y;
}
}
int main(int argc, char const *argv[])
{
float *gpu_cargas, *cargas_menores, *gpu_iones_x, *gpu_iones_y, *iones_x, *iones_y;
hipEvent_t ct1, ct2;
float dt;
int cantidad;
iones_x = new float[6000];
iones_y = new float[6000];
int block_size = 256;
int grid_size = (int) ceil( (float) 8192*8192 / block_size);
int grid_size_b = (int) ceil( (float) 8192 / block_size);
int grid_size_c = (int) ceil( (float) 1 / block_size);
FILE *in = fopen("dataset", "r");
for (int i = 0; i < 5000; i++)
{
fscanf(in, "%f %f", &iones_x[i], &iones_y[i]);
}
hipMalloc(&gpu_iones_x, sizeof(float) * 6000);
hipMalloc(&gpu_iones_y, sizeof(float) * 6000);
hipMalloc(&gpu_cargas, sizeof(float) * 8192 * 8192);
hipMalloc(&cargas_menores, sizeof(float) * 8192*3);
hipMemcpy(gpu_iones_x, iones_x ,sizeof(float) * 6000, hipMemcpyHostToDevice);
hipMemcpy(gpu_iones_y, iones_y ,sizeof(float) * 6000, hipMemcpyHostToDevice);
hipEventCreate(&ct1);
hipEventCreate(&ct2);
hipEventRecord(ct1);
for (cantidad = 5000; cantidad < 5010; cantidad++)
{
calcular_carga<<<grid_size, block_size>>>(gpu_iones_x, gpu_iones_y, gpu_cargas, cantidad);
hipDeviceSynchronize();
calcular_carga_fila<<<grid_size_b, block_size>>>(gpu_iones_x, gpu_iones_y, gpu_cargas, cargas_menores, cantidad);
hipDeviceSynchronize();
posicionar_ion<<<grid_size_c, block_size>>>(gpu_iones_x, gpu_iones_y, cargas_menores, cantidad);
hipDeviceSynchronize();
hipMemcpy(iones_x, gpu_iones_x,sizeof(float) * 6000, hipMemcpyDeviceToHost);
hipMemcpy(iones_y, gpu_iones_y,sizeof(float) * 6000, hipMemcpyDeviceToHost);
cout << iones_x[cantidad] << " " << iones_y[cantidad] << endl;
}
hipEventRecord(ct2);
hipEventSynchronize(ct2);
hipEventElapsedTime(&dt, ct1, ct2);
cout << "Tiempo: " << dt << "[ms]" << '\n';
hipFree(gpu_iones_x);
hipFree(gpu_iones_y);
hipFree(gpu_cargas);
hipFree(cargas_menores);
hipFree(gpu_iones_x);
hipFree(gpu_iones_y);
delete iones_x;
delete iones_y;
return 0;
} | .text
.file "kernel1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__calcular_cargaPfS_S_i # -- Begin function _Z29__device_stub__calcular_cargaPfS_S_i
.p2align 4, 0x90
.type _Z29__device_stub__calcular_cargaPfS_S_i,@function
_Z29__device_stub__calcular_cargaPfS_S_i: # @_Z29__device_stub__calcular_cargaPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14calcular_cargaPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__calcular_cargaPfS_S_i, .Lfunc_end0-_Z29__device_stub__calcular_cargaPfS_S_i
.cfi_endproc
# -- End function
.globl _Z34__device_stub__calcular_carga_filaPfS_S_S_i # -- Begin function _Z34__device_stub__calcular_carga_filaPfS_S_S_i
.p2align 4, 0x90
.type _Z34__device_stub__calcular_carga_filaPfS_S_S_i,@function
_Z34__device_stub__calcular_carga_filaPfS_S_S_i: # @_Z34__device_stub__calcular_carga_filaPfS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19calcular_carga_filaPfS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z34__device_stub__calcular_carga_filaPfS_S_S_i, .Lfunc_end1-_Z34__device_stub__calcular_carga_filaPfS_S_S_i
.cfi_endproc
# -- End function
.globl _Z29__device_stub__posicionar_ionPfS_S_i # -- Begin function _Z29__device_stub__posicionar_ionPfS_S_i
.p2align 4, 0x90
.type _Z29__device_stub__posicionar_ionPfS_S_i,@function
_Z29__device_stub__posicionar_ionPfS_S_i: # @_Z29__device_stub__posicionar_ionPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14posicionar_ionPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z29__device_stub__posicionar_ionPfS_S_i, .Lfunc_end2-_Z29__device_stub__posicionar_ionPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $24000, %edi # imm = 0x5DC0
callq _Znam
movq %rax, %rbx
movl $24000, %edi # imm = 0x5DC0
callq _Znam
movq %rax, %r14
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
leaq (%rbx,%r12), %rdx
leaq (%r14,%r12), %rcx
movl $.L.str.2, %esi
movq %r15, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r12
cmpq $20000, %r12 # imm = 0x4E20
jne .LBB3_1
# %bb.2:
movabsq $4294967552, %r15 # imm = 0x100000100
leaq 8(%rsp), %rdi
movl $24000, %esi # imm = 0x5DC0
callq hipMalloc
movq %rsp, %rdi
movl $24000, %esi # imm = 0x5DC0
callq hipMalloc
leaq 112(%rsp), %rdi
movl $268435456, %esi # imm = 0x10000000
callq hipMalloc
leaq 104(%rsp), %rdi
movl $98304, %esi # imm = 0x18000
callq hipMalloc
movq 8(%rsp), %rdi
movl $24000, %edx # imm = 0x5DC0
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $24000, %edx # imm = 0x5DC0
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 168(%rsp), %rdi
callq hipEventCreate
leaq 96(%rsp), %rdi
callq hipEventCreate
movq 168(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $5000, %ebp # imm = 0x1388
leaq 261888(%r15), %rax
movq %rax, 192(%rsp) # 8-byte Spill
leaq -224(%r15), %rax
movq %rax, 184(%rsp) # 8-byte Spill
leaq -255(%r15), %rax
movq %rax, 176(%rsp) # 8-byte Spill
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_12: # in Loop: Header=BB3_3 Depth=1
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB3_3 Depth=1
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %rbp
cmpq $5010, %rbp # imm = 0x1392
je .LBB3_14
.LBB3_3: # =>This Inner Loop Header: Depth=1
movq 192(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_5
# %bb.4: # in Loop: Header=BB3_3 Depth=1
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq 112(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ebp, 32(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z14calcular_cargaPfS_S_i, %edi
leaq 128(%rsp), %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_5: # in Loop: Header=BB3_3 Depth=1
callq hipDeviceSynchronize
movq 184(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_7
# %bb.6: # in Loop: Header=BB3_3 Depth=1
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq 112(%rsp), %rdx
movq 104(%rsp), %rsi
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rsi, 48(%rsp)
movl %ebp, 124(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 124(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z19calcular_carga_filaPfS_S_S_i, %edi
leaq 128(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_7: # in Loop: Header=BB3_3 Depth=1
callq hipDeviceSynchronize
movq 176(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_9
# %bb.8: # in Loop: Header=BB3_3 Depth=1
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq 104(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ebp, 32(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z14posicionar_ionPfS_S_i, %edi
leaq 128(%rsp), %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_9: # in Loop: Header=BB3_3 Depth=1
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $24000, %edx # imm = 0x5DC0
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rsi
movl $24000, %edx # imm = 0x5DC0
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movss (%rbx,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r14,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB3_18
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB3_3 Depth=1
cmpb $0, 56(%r13)
je .LBB3_12
# %bb.11: # in Loop: Header=BB3_3 Depth=1
movzbl 67(%r13), %eax
jmp .LBB3_13
.LBB3_14:
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 96(%rsp), %rdi
callq hipEventSynchronize
movq 168(%rsp), %rsi
movq 96(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.5, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movb $10, 16(%rsp)
movq (%r15), %rax
movq -24(%rax), %rax
cmpq $0, 16(%r15,%rax)
je .LBB3_16
# %bb.15:
leaq 16(%rsp), %rsi
movl $1, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB3_17
.LBB3_16:
movq %r15, %rdi
movl $10, %esi
callq _ZNSo3putEc
.LBB3_17: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq 112(%rsp), %rdi
callq hipFree
movq 104(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdlPv
movq %r14, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_18:
.cfi_def_cfa_offset 256
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14calcular_cargaPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19calcular_carga_filaPfS_S_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14posicionar_ionPfS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14calcular_cargaPfS_S_i,@object # @_Z14calcular_cargaPfS_S_i
.section .rodata,"a",@progbits
.globl _Z14calcular_cargaPfS_S_i
.p2align 3, 0x0
_Z14calcular_cargaPfS_S_i:
.quad _Z29__device_stub__calcular_cargaPfS_S_i
.size _Z14calcular_cargaPfS_S_i, 8
.type _Z19calcular_carga_filaPfS_S_S_i,@object # @_Z19calcular_carga_filaPfS_S_S_i
.globl _Z19calcular_carga_filaPfS_S_S_i
.p2align 3, 0x0
_Z19calcular_carga_filaPfS_S_S_i:
.quad _Z34__device_stub__calcular_carga_filaPfS_S_S_i
.size _Z19calcular_carga_filaPfS_S_S_i, 8
.type _Z14posicionar_ionPfS_S_i,@object # @_Z14posicionar_ionPfS_S_i
.globl _Z14posicionar_ionPfS_S_i
.p2align 3, 0x0
_Z14posicionar_ionPfS_S_i:
.quad _Z29__device_stub__posicionar_ionPfS_S_i
.size _Z14posicionar_ionPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "dataset"
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%f %f"
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " "
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Tiempo: "
.size .L.str.4, 9
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "[ms]"
.size .L.str.5, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14calcular_cargaPfS_S_i"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z19calcular_carga_filaPfS_S_S_i"
.size .L__unnamed_2, 33
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z14posicionar_ionPfS_S_i"
.size .L__unnamed_3, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__calcular_cargaPfS_S_i
.addrsig_sym _Z34__device_stub__calcular_carga_filaPfS_S_S_i
.addrsig_sym _Z29__device_stub__posicionar_ionPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14calcular_cargaPfS_S_i
.addrsig_sym _Z19calcular_carga_filaPfS_S_S_i
.addrsig_sym _Z14posicionar_ionPfS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a30c7_00000000-6_kernel1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB5122:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5122:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z14calcular_cargaPfS_S_iPfS_S_i
.type _Z39__device_stub__Z14calcular_cargaPfS_S_iPfS_S_i, @function
_Z39__device_stub__Z14calcular_cargaPfS_S_iPfS_S_i:
.LFB5144:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14calcular_cargaPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5144:
.size _Z39__device_stub__Z14calcular_cargaPfS_S_iPfS_S_i, .-_Z39__device_stub__Z14calcular_cargaPfS_S_iPfS_S_i
.globl _Z14calcular_cargaPfS_S_i
.type _Z14calcular_cargaPfS_S_i, @function
_Z14calcular_cargaPfS_S_i:
.LFB5145:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14calcular_cargaPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5145:
.size _Z14calcular_cargaPfS_S_i, .-_Z14calcular_cargaPfS_S_i
.globl _Z46__device_stub__Z19calcular_carga_filaPfS_S_S_iPfS_S_S_i
.type _Z46__device_stub__Z19calcular_carga_filaPfS_S_S_iPfS_S_S_i, @function
_Z46__device_stub__Z19calcular_carga_filaPfS_S_S_iPfS_S_S_i:
.LFB5146:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19calcular_carga_filaPfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5146:
.size _Z46__device_stub__Z19calcular_carga_filaPfS_S_S_iPfS_S_S_i, .-_Z46__device_stub__Z19calcular_carga_filaPfS_S_S_iPfS_S_S_i
.globl _Z19calcular_carga_filaPfS_S_S_i
.type _Z19calcular_carga_filaPfS_S_S_i, @function
_Z19calcular_carga_filaPfS_S_S_i:
.LFB5147:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z19calcular_carga_filaPfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5147:
.size _Z19calcular_carga_filaPfS_S_S_i, .-_Z19calcular_carga_filaPfS_S_S_i
.globl _Z39__device_stub__Z14posicionar_ionPfS_S_iPfS_S_i
.type _Z39__device_stub__Z14posicionar_ionPfS_S_iPfS_S_i, @function
_Z39__device_stub__Z14posicionar_ionPfS_S_iPfS_S_i:
.LFB5148:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14posicionar_ionPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5148:
.size _Z39__device_stub__Z14posicionar_ionPfS_S_iPfS_S_i, .-_Z39__device_stub__Z14posicionar_ionPfS_S_iPfS_S_i
.globl _Z14posicionar_ionPfS_S_i
.type _Z14posicionar_ionPfS_S_i, @function
_Z14posicionar_ionPfS_S_i:
.LFB5149:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14posicionar_ionPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5149:
.size _Z14posicionar_ionPfS_S_i, .-_Z14posicionar_ionPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "dataset"
.LC2:
.string "%f %f"
.LC3:
.string " "
.LC4:
.string "Tiempo: "
.LC5:
.string "[ms]"
.text
.globl main
.type main, @function
main:
.LFB5119:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $24000, %edi
call _Znam@PLT
movq %rax, %r15
movl $24000, %edi
call _Znam@PLT
movq %rax, %rbp
movq %rax, 8(%rsp)
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movq %r15, %rbx
leaq 20000(%r15), %r14
leaq .LC2(%rip), %r13
.L28:
movq %rbp, %rcx
movq %rbx, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $4, %rbx
addq $4, %rbp
cmpq %r14, %rbx
jne .L28
leaq 32(%rsp), %rdi
movl $24000, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $24000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $268435456, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $98304, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $24000, %edx
movq %r15, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $24000, %edx
movq 8(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $5000, %ebx
leaq _ZSt4cout(%rip), %r13
leaq .LC3(%rip), %r14
jmp .L36
.L43:
movl %ebx, %ecx
movq 16(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z39__device_stub__Z14calcular_cargaPfS_S_iPfS_S_i
jmp .L29
.L44:
movl %ebp, %r8d
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z46__device_stub__Z19calcular_carga_filaPfS_S_S_iPfS_S_S_i
jmp .L30
.L45:
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z39__device_stub__Z14posicionar_ionPfS_S_iPfS_S_i
jmp .L31
.L46:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L41
call _ZSt16__throw_bad_castv@PLT
.L41:
call __stack_chk_fail@PLT
.L34:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L35:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbx
cmpq $5010, %rbx
je .L42
.L36:
movl %ebx, %ebp
movl $256, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $262144, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L29:
call cudaDeviceSynchronize@PLT
movl $256, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $32, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L44
.L30:
call cudaDeviceSynchronize@PLT
movl $256, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L31:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $24000, %edx
movq 32(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $24000, %edx
movq 40(%rsp), %rsi
movq 8(%rsp), %r12
movq %r12, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L46
cmpb $0, 56(%r12)
je .L34
movzbl 67(%r12), %esi
jmp .L35
.L42:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 76(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 76(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movl $4, %esi
movq %r15, %rdi
call _ZdlPvm@PLT
movl $4, %esi
movq 8(%rsp), %rdi
call _ZdlPvm@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L47
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5119:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z14posicionar_ionPfS_S_i"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "_Z19calcular_carga_filaPfS_S_S_i"
.section .rodata.str1.1
.LC8:
.string "_Z14calcular_cargaPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB5151:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z14posicionar_ionPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z19calcular_carga_filaPfS_S_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z14calcular_cargaPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5151:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__calcular_cargaPfS_S_i # -- Begin function _Z29__device_stub__calcular_cargaPfS_S_i
.p2align 4, 0x90
.type _Z29__device_stub__calcular_cargaPfS_S_i,@function
_Z29__device_stub__calcular_cargaPfS_S_i: # @_Z29__device_stub__calcular_cargaPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14calcular_cargaPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__calcular_cargaPfS_S_i, .Lfunc_end0-_Z29__device_stub__calcular_cargaPfS_S_i
.cfi_endproc
# -- End function
.globl _Z34__device_stub__calcular_carga_filaPfS_S_S_i # -- Begin function _Z34__device_stub__calcular_carga_filaPfS_S_S_i
.p2align 4, 0x90
.type _Z34__device_stub__calcular_carga_filaPfS_S_S_i,@function
_Z34__device_stub__calcular_carga_filaPfS_S_S_i: # @_Z34__device_stub__calcular_carga_filaPfS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19calcular_carga_filaPfS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z34__device_stub__calcular_carga_filaPfS_S_S_i, .Lfunc_end1-_Z34__device_stub__calcular_carga_filaPfS_S_S_i
.cfi_endproc
# -- End function
.globl _Z29__device_stub__posicionar_ionPfS_S_i # -- Begin function _Z29__device_stub__posicionar_ionPfS_S_i
.p2align 4, 0x90
.type _Z29__device_stub__posicionar_ionPfS_S_i,@function
_Z29__device_stub__posicionar_ionPfS_S_i: # @_Z29__device_stub__posicionar_ionPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14posicionar_ionPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z29__device_stub__posicionar_ionPfS_S_i, .Lfunc_end2-_Z29__device_stub__posicionar_ionPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $24000, %edi # imm = 0x5DC0
callq _Znam
movq %rax, %rbx
movl $24000, %edi # imm = 0x5DC0
callq _Znam
movq %rax, %r14
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
leaq (%rbx,%r12), %rdx
leaq (%r14,%r12), %rcx
movl $.L.str.2, %esi
movq %r15, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r12
cmpq $20000, %r12 # imm = 0x4E20
jne .LBB3_1
# %bb.2:
movabsq $4294967552, %r15 # imm = 0x100000100
leaq 8(%rsp), %rdi
movl $24000, %esi # imm = 0x5DC0
callq hipMalloc
movq %rsp, %rdi
movl $24000, %esi # imm = 0x5DC0
callq hipMalloc
leaq 112(%rsp), %rdi
movl $268435456, %esi # imm = 0x10000000
callq hipMalloc
leaq 104(%rsp), %rdi
movl $98304, %esi # imm = 0x18000
callq hipMalloc
movq 8(%rsp), %rdi
movl $24000, %edx # imm = 0x5DC0
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $24000, %edx # imm = 0x5DC0
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 168(%rsp), %rdi
callq hipEventCreate
leaq 96(%rsp), %rdi
callq hipEventCreate
movq 168(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $5000, %ebp # imm = 0x1388
leaq 261888(%r15), %rax
movq %rax, 192(%rsp) # 8-byte Spill
leaq -224(%r15), %rax
movq %rax, 184(%rsp) # 8-byte Spill
leaq -255(%r15), %rax
movq %rax, 176(%rsp) # 8-byte Spill
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_12: # in Loop: Header=BB3_3 Depth=1
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB3_3 Depth=1
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %rbp
cmpq $5010, %rbp # imm = 0x1392
je .LBB3_14
.LBB3_3: # =>This Inner Loop Header: Depth=1
movq 192(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_5
# %bb.4: # in Loop: Header=BB3_3 Depth=1
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq 112(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ebp, 32(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z14calcular_cargaPfS_S_i, %edi
leaq 128(%rsp), %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_5: # in Loop: Header=BB3_3 Depth=1
callq hipDeviceSynchronize
movq 184(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_7
# %bb.6: # in Loop: Header=BB3_3 Depth=1
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq 112(%rsp), %rdx
movq 104(%rsp), %rsi
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rsi, 48(%rsp)
movl %ebp, 124(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 124(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z19calcular_carga_filaPfS_S_S_i, %edi
leaq 128(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_7: # in Loop: Header=BB3_3 Depth=1
callq hipDeviceSynchronize
movq 176(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_9
# %bb.8: # in Loop: Header=BB3_3 Depth=1
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq 104(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ebp, 32(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z14posicionar_ionPfS_S_i, %edi
leaq 128(%rsp), %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_9: # in Loop: Header=BB3_3 Depth=1
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $24000, %edx # imm = 0x5DC0
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rsi
movl $24000, %edx # imm = 0x5DC0
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movss (%rbx,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r14,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB3_18
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB3_3 Depth=1
cmpb $0, 56(%r13)
je .LBB3_12
# %bb.11: # in Loop: Header=BB3_3 Depth=1
movzbl 67(%r13), %eax
jmp .LBB3_13
.LBB3_14:
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 96(%rsp), %rdi
callq hipEventSynchronize
movq 168(%rsp), %rsi
movq 96(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.5, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movb $10, 16(%rsp)
movq (%r15), %rax
movq -24(%rax), %rax
cmpq $0, 16(%r15,%rax)
je .LBB3_16
# %bb.15:
leaq 16(%rsp), %rsi
movl $1, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB3_17
.LBB3_16:
movq %r15, %rdi
movl $10, %esi
callq _ZNSo3putEc
.LBB3_17: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq 112(%rsp), %rdi
callq hipFree
movq 104(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdlPv
movq %r14, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_18:
.cfi_def_cfa_offset 256
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14calcular_cargaPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19calcular_carga_filaPfS_S_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14posicionar_ionPfS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14calcular_cargaPfS_S_i,@object # @_Z14calcular_cargaPfS_S_i
.section .rodata,"a",@progbits
.globl _Z14calcular_cargaPfS_S_i
.p2align 3, 0x0
_Z14calcular_cargaPfS_S_i:
.quad _Z29__device_stub__calcular_cargaPfS_S_i
.size _Z14calcular_cargaPfS_S_i, 8
.type _Z19calcular_carga_filaPfS_S_S_i,@object # @_Z19calcular_carga_filaPfS_S_S_i
.globl _Z19calcular_carga_filaPfS_S_S_i
.p2align 3, 0x0
_Z19calcular_carga_filaPfS_S_S_i:
.quad _Z34__device_stub__calcular_carga_filaPfS_S_S_i
.size _Z19calcular_carga_filaPfS_S_S_i, 8
.type _Z14posicionar_ionPfS_S_i,@object # @_Z14posicionar_ionPfS_S_i
.globl _Z14posicionar_ionPfS_S_i
.p2align 3, 0x0
_Z14posicionar_ionPfS_S_i:
.quad _Z29__device_stub__posicionar_ionPfS_S_i
.size _Z14posicionar_ionPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "dataset"
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%f %f"
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " "
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Tiempo: "
.size .L.str.4, 9
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "[ms]"
.size .L.str.5, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14calcular_cargaPfS_S_i"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z19calcular_carga_filaPfS_S_S_i"
.size .L__unnamed_2, 33
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z14posicionar_ionPfS_S_i"
.size .L__unnamed_3, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__calcular_cargaPfS_S_i
.addrsig_sym _Z34__device_stub__calcular_carga_filaPfS_S_S_i
.addrsig_sym _Z29__device_stub__posicionar_ionPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14calcular_cargaPfS_S_i
.addrsig_sym _Z19calcular_carga_filaPfS_S_S_i
.addrsig_sym _Z14posicionar_ionPfS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* William Dreese + Steven Gschwind
* t-SNE C baseline for mini project
*
* Proper import path before compilation:
* export PATH=${PATH}:/usr/local/cuda-9.1/bin
*/
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <cuda.h>
#include <sys/time.h>
#include <time.h>
typedef unsigned long long ull;
unsigned long long dD, dP;
float perp, l_r, momemtum;
int iters;
int *image_labels;
static FILE *FILE_POINTER = NULL;
static int EOF_FLAG = 0;
void setFilePointer(char *file_name);
float *getChunkedValues();
void closeFile();
int parseNextLine(float *data_points);
float getNextValue();
struct sol {
float x,y;
};
void pf(int i){
printf("here %d\n",i);
}
static double get_walltime() {
struct timeval tp;
gettimeofday(&tp, NULL);
return ((double) (tp.tv_sec) + 1e-6 * tp.tv_usec);
}
void setFilePointer(char *file_name) {
FILE_POINTER = fopen(file_name, "r");
if (FILE_POINTER == NULL) {
printf("Error opening file\n");
exit(1);
}
EOF_FLAG = 0;
}
void getChunkedValues(float *data) {
image_labels = (int *)malloc(dD * sizeof(int));
// int throwaway = parseNextLine(data);
// Set image_labels and data values, image_labels will be used for cluster graph
int count;
for (count = 0; count < dD; count ++) {
image_labels[count] = parseNextLine(&data[count * dP]);
}
}
void closeFile() {
fclose(FILE_POINTER);
free(image_labels);
FILE_POINTER = NULL;
}
int parseNextLine(float *data_points) {
if (FILE_POINTER == NULL) {
printf("No file found, call setFilePointer(char *file_name) before runnning\n");
exit(1);
}
// Get label value for image creation
int value = getNextValue();
if (EOF_FLAG > 0) {
return -1; // Finished parsing the file
}
int count = 0;
while (count < dP) {
data_points[count] = getNextValue();
count += 1;
}
return value;
}
// Returns next value from csv file
float getNextValue() {
char value[4] = {0,0,0,0}; // value is between 0 and 256
int pos = 0;
char current;
while (1) {
current = fgetc(FILE_POINTER);
if (current == ',') {
break;
}
else if (current == EOF) {
EOF_FLAG = 1;
break;
}
else if (current == '\n') {
break;
}
value[pos] = current;
pos += 1;
}
return atof(value);
}
void displayHelp() {
printf("\nHELP\nThe program must be run in the format './tsne {filename.csv} {#rows} {#cols} {command} {command_input}....'\n");
printf("The filename.csv, #rows and #cols inputs are necessary. \n#cols should be the number of data points, not including the label column\n");
printf("\nBelow are a set of optional commands:\n");
printf("\tCommand\t\tValue Type\tMeaning\t\n");
printf("\t-----------------------------------------\n");
printf("\t-perp\t\tfloat\t\tSet the perplexity value\n");
printf("\t-learning_rate\tfloat\t\tSet the learning rate\n");
printf("\t-momentum\tfloat\t\tSet the momentum\n");
printf("\t-iters\t\tint\t\tSet the number of iterations\n\n");
printf("For simplicities sake, the commands that we have used to run our test was:\n");
printf("\t./tsne fashion-mnist_test.csv 10000 784\n");
printf("We modified the optional input as necessary\n");
}
void parseCommandLineArguments(int argc, char **argv) {
if (argc < 2) {
printf("Illegal number of arguments supplied. Displaying help (-h)\n");
displayHelp();
exit(1);
}
if (strcmp(argv[1], "-h") == 0) {
displayHelp();
exit(0);
} else {
setFilePointer(argv[1]);
}
if (argc % 2 != 0 || argc < 4) {
printf("Illegal number of arguments supplied. Displaying help (-h)\n");
displayHelp();
exit(1);
}
// Set columns and width
dD = atoi(argv[2]);
dP = atoi(argv[3]);
// Set each of the optional commandline arguments
int i;
float arg_value;
for (i = 4; i < argc; i += 2) {
arg_value = atof(argv[i+1]);
if (strcmp(argv[i], "-perp") == 0) {
perp = arg_value;
} else if (strcmp(argv[i], "-learning_rate") == 0) {
l_r = arg_value;
} else if (strcmp(argv[i], "-momentum") == 0) {
momemtum = arg_value;
} else if (strcmp(argv[i], "-iters") == 0) {
iters = arg_value;
} else {
printf("Command (%s) not found\n", argv[i]);
}
}
printf("Arguments:\n");
printf("Perplexity: %g\n", perp);
printf("Learning_rate: %g\n", l_r);
printf("Momentum: %g\n", momemtum);
printf("Iterations: %d\n", iters);
}
//find euclidean distance for two data points with arbitrary dimensions
float euclidean_dist(float *xi, float *xj){
int i;
float total = 0;
for (i = 0; i < dP; i++) total += (xi[i]-xj[i])*(xi[i]-xj[i]);
return sqrt(total);
}
//compute true similarity scores between data points
void compute_pij(float *data, float *pij_grid){
unsigned long long i, j, k;
float total_prob, val;
for (i = 0; i < dD; i++){
total_prob = 0;
for (j = 0; j < dD; j++){
val = 0;
if (i == j) pij_grid[i*dD+j] = 0;
else {
for (k = 0; k < dP; k++) val += (data[i*dP+k]-data[j*dP+k])*(data[i*dP+k]-data[j*dP+k]);
val = expf((0.0-sqrt(val))/(2.0*perp*perp));
total_prob += val;
pij_grid[i*dD+j] = val;
}
}
for (j = 0; j < dD; j++) pij_grid[i*dD+j] /= total_prob;
}
}
/*
//compute true similarity scores between data points
void compute_pij_hbeta(float *data, float *pij_grid){
unsigned long long i, j, k, tries;
float total_prob, val, beta, bmax, bmin, dp, hval;
float tol = 0.00001;
float logp = logf(perp);
float *dist_temp = (float *)malloc(dD*sizeof(float));
for (i = 0; i < dD; i++){
total_prob = 0;
beta = 1.0;
bmax = 10000.0;
bmin = -10000.0;
for (j = 0; j < dD; j++){
val = 0;
if (i == j) {
pij_grid[i*dD+j] = 0;
dist_temp[j] = 0.0;
}
else {
for (k = 0; k < dP; k++) val += (data[i*dP+k]-data[j*dP+k])*(data[i*dP+k]-data[j*dP+k]);
dist_temp[j] = sqrt(val);
}
}
tries = 0;
do {
if (tries != 0){
if ((hval-logp) > 0.0){
bmin = beta;
if (bmax == 10000 || bmax == -10000) beta *= 2.0;
else beta = (beta + bmax) / 2.0;
}
else {
bmax = beta;
if (bmin == 10000 || bmin == -10000) beta /= 2.0;
else beta = (beta + bmin) / 2.0;
}
}
tries++;
dp = 0;
for (j = 0; j < dD; j++){
val = expf((0.0-dist_temp[j])*beta);
total_prob += val;
pij_grid[i*dD+j] = val;
dp += val*dist_temp[j];
}
hval = logf(total_prob) + ( beta * dp / total_prob);
for (j = 0; j < dD; j++) pij_grid[i*dD+j] /= total_prob;
} while (abs(hval-logp) > tol && tries < 50);
}
free(dist_temp);
}
*/
//pre-processing of pij rid, saves time and increases visual accuracy
void symmetric_pij(float *pij_grid){
int i, j;
float val;
for (i = 0; i < dD; i++){
for (j = i+1; j < dD; j++){
val = (pij_grid[i*dD+j] + pij_grid[j*dD+i]) / (float)(2*dD);
pij_grid[i*dD+j] = val;
pij_grid[j*dD+i] = val;
}
}
}
//each potential solution is randomized 0 < x,y < 1
void random_solutions(sol *sols){
int i;
for (i = 0; i < dD; i++){
sols[i].x = (float)rand() / (float)RAND_MAX;
sols[i].y = (float)rand() / (float)RAND_MAX;
}
}
//calculate euclidean distance between two 2D points
float sol_ed(sol i, sol j){
return sqrt(((i.x-j.x)*(i.x-j.x))+((i.y-j.y)*(i.y-j.y)));
}
//calculate low-dimensionality similarity grid
void compute_qij(sol *sols, float *qij_grid){
unsigned long long i, j;
float total, val;
for (i = 0; i < dD; i++){
total = 0;
for (j = 0; j < dD; j++){
if (i == j) qij_grid[i*dD+j] = 0;
else {
val = 1.0 / (1.0+sol_ed(sols[i], sols[j]));
total += val;
qij_grid[i*dD+j] = val;
}
}
for (j = 0; j < dD; j++) qij_grid[i*dD+j] /= total;
// TODO: subtract so k!=i
}
}
//calculates and applies gradients to each solution
void compute_gradients(sol *sols, float *pij_grid, float *qij_grid, sol *prev_sols){
ull i, j;
float gradX, gradY, prevX, prevY, pq, ed;
for (i = 0; i < dD; i++){
gradX = 0; gradY = 0;
for (j = 0; j < dD; j++){
pq = (pij_grid[i*dD+j] - qij_grid[i*dD+j]);
ed = 1.0 / (1.0 + sol_ed(sols[i],sols[j]));
gradX += pq * (sols[i].x - sols[j].x) * ed;
gradY += pq * (sols[i].y - sols[j].y) * ed;
}
gradX *= 4; gradY *= 4;
prevX = sols[i].x; prevY = sols[i].y;
sols[i].x += l_r*gradX + momemtum*(sols[i].x - prev_sols[i].x);
sols[i].y += l_r*gradY + momemtum*(sols[i].y - prev_sols[i].y);
prev_sols[i].x = prevX; prev_sols[i].y = prevY;
}
}
//honestly, the exact same as baseline compute_pij, except each row is sent to it's own thread
__global__ void compute_pij_kernel_A(float *data, float *pij, ull dD, ull dP, float perp, ull offset){
ull k;
ull i = (ull) (blockIdx.x * blockDim.x + threadIdx.x);
ull j = (ull) (offset * blockDim.y + threadIdx.y);
float dist = 0;
float val;
if (i < dD && j < dD){
for (k = 0; k < dP; k++) dist += (data[i*dP+k]-data[j*dP+k])*(data[i*dP+k]-data[j*dP+k]);
val = expf((0.0-sqrt(dist))/(2.0*perp*perp));
pij[i*dD+j] = val;
if (i == j) pij[i*dD+j] = 0.0;
}
}
//compute total per row, divide each element
__global__ void compute_pij_kernel_B(float *pij, ull dD){
ull i = (ull) (blockIdx.x * blockDim.x + threadIdx.x);
ull j;
float total = 0;
if (i < dD){
for (j = 0; j < dD; j++) total += pij[i*dD+j];
for (j = 0; j < dD; j++) pij[i*dD+j] /= total;
}
}
//balances pij for increased accuracy
__global__ void symettric_pij_kernel(float *pij, ull dD){
ull i = (ull) blockIdx.x * blockDim.x + threadIdx.x;
ull j = (ull) blockIdx.y * blockDim.y + threadIdx.y;
float val;
if (i < dD && j < dD && i < j){
val = (pij[i*dD+j]+pij[j*dD+i]) / (float)(2*dD);
pij[i*dD+j] = val;
pij[j*dD+i] = val;
}
}
//access function for compute_pij_kernel
void cuda_compute_pij(float *data, float *pij){
int ys = ceil((float)dD / 32.0);
dim3 threads1D(1024);
dim3 blocks1D(ceil((float)dD / 1024.0));
dim3 threads2D(32,32);
dim3 blocks2D(ys, 1);
dim3 blocks2Da(ys, ys);
for (ull y = 0; y < ys; y++){
compute_pij_kernel_A<<<blocks2D, threads2D>>>(data, pij, dD, dP, perp, y);
}
cudaFree(data);
compute_pij_kernel_B<<<blocks1D, threads1D>>>(pij, dD);
symettric_pij_kernel<<<blocks2Da, threads2D>>>(pij, dD);
}
__global__ void compute_qij_kernel(sol *sols, float *qij, ull dD){
ull i = (ull) blockIdx.x * blockDim.x + threadIdx.x;
ull j;
float total, val, dist;
if (i < dD){
total = 0;
for (j = 0; j < dD; j++){
if (i == j) qij[i*dD+j] = 0;
else {
dist = (sols[i].x - sols[j].x)*(sols[i].x-sols[j].x) + (sols[i].y - sols[j].y)*(sols[i].y-sols[j].y);
val = 1.0 / (1.0+sqrt(dist));
total += val;
qij[i*dD+j] = val;
}
}
for (j = 0; j < dD; j++) qij[i*dD+j] /= total;
}
}
//access function to compute_qij_kernel
void cuda_compute_qij(sol *sols, float *qij){
dim3 threads(1024);
dim3 blocks(ceil((float)dD / 1024.0));
compute_qij_kernel<<<blocks, threads>>>(sols, qij, dD);
}
__global__ void compute_gradients_kernel(sol *sols, float *pij, float *qij, sol *prev, ull dD, float momemtum, float l_r){
ull i = (ull) (blockIdx.x * blockDim.x + threadIdx.x);
ull j;
float gradX, gradY, prevX, prevY, pq, ed;
if (i < dD){
gradX = 0; gradY = 0;
for (j = 0; j < dD; j++){
pq = (pij[i*dD+j] - qij[i*dD+j]);
ed = (sols[i].x - sols[j].x)*(sols[i].x-sols[j].x) + (sols[i].y - sols[j].y)*(sols[i].y-sols[j].y);
ed = 1.0 / (1.0 + sqrt(ed));
gradX += pq * (sols[i].x - sols[j].x) * ed;
gradY += pq * (sols[i].y - sols[j].y) * ed;
}
gradX *= 4; gradY *= 4;
prevX = sols[i].x; prevY = sols[i].y;
sols[i].x += l_r*gradX + momemtum*(sols[i].x - prev[i].x);
sols[i].y += l_r*gradY + momemtum*(sols[i].y - prev[i].y);
prev[i].x = prevX; prev[i].y = prevY;
}
}
void cuda_compute_gradients(sol *sols, float *pij, float *qij, sol *prev){
dim3 threads(1024);
dim3 blocks(ceil((float)dD / 1024.0));
compute_gradients_kernel<<<blocks, threads>>>(sols, pij, qij, prev, dD, momemtum, l_r);
cudaThreadSynchronize();
}
void cEcheck(cudaError_t cE, const char *type){
if (cE != cudaSuccess){
printf("Error while %s memory.\n",type);
printf( cudaGetErrorString( cudaGetLastError()));
exit(1);
}
}
void tsne_cuda(float *data, sol *sols, int iters){
int t;
//same mallocs as baseline below
sol *prev_sols = (sol *) malloc(dD*sizeof(sol));
for (t = 0; t < dD; t++){ prev_sols[t].x = 0.0; prev_sols[t].y = 0.0; }
random_solutions(sols);
//corresponding matrixes that live on device
float *data_d, *pij_grid_d, *qij_grid_d;
sol *sols_d, *prev_sols_d;
cEcheck( cudaMalloc((void **)&data_d, dD*dP*sizeof(float)), "allocating" );
cEcheck( cudaMalloc((void **)&pij_grid_d, dD*dD*sizeof(float)), "allocating" );
cEcheck( cudaMemcpy(data_d, data, dD*dP*sizeof(float), cudaMemcpyHostToDevice), "transferring" );
cuda_compute_pij(data_d, pij_grid_d); //also frees data
printf("Making pij (CUDA)\n");
cEcheck( cudaMalloc((void **)&qij_grid_d, dD*dD*sizeof(float)), "allocating" );
cEcheck( cudaMalloc((void **)&sols_d, dD*sizeof(sol)), "allocating" );
cEcheck( cudaMalloc((void **)&prev_sols_d, dD*sizeof(sol)), "allocating" );
cEcheck( cudaMemcpy(sols_d, sols, dD*sizeof(sol), cudaMemcpyHostToDevice), "transferring" );
cEcheck( cudaMemcpy(prev_sols_d, prev_sols, dD*sizeof(sol), cudaMemcpyHostToDevice), "transferring" );;
for (t = 0; t < iters; t++){
cuda_compute_qij(sols_d, qij_grid_d);
cuda_compute_gradients(sols_d, pij_grid_d, qij_grid_d, prev_sols_d);
if (t == 250) momemtum = 0.8;
}
cEcheck( cudaMemcpy(sols, sols_d, dD*sizeof(sol), cudaMemcpyDeviceToHost), "transferring" );
pf(66);
cudaFree(pij_grid_d);
cudaFree(qij_grid_d);
cudaFree(sols_d);
cudaFree(prev_sols_d);
free(prev_sols);
}
//the main function
void tsne_baseline(float *data, sol *sols, int iters){
int t;
//malloc grids, init prev_sol
float *pij_grid = (float *)malloc(dD*dD*sizeof(float));
float *qij_grid = (float *)malloc(dD*dD*sizeof(float));
sol *prev_sols = (sol *) malloc(dD*sizeof(sol));
for (t = 0; t < dD; t++){
prev_sols[t].x = 0.0;
prev_sols[t].y = 0.0;
}
//prepare for loop
compute_pij(data, pij_grid);
symmetric_pij(pij_grid);
random_solutions(sols);
//slowly move each x/y closer to it's true value
for (t = 0; t<iters; t++){
compute_qij(sols, qij_grid);
compute_gradients(sols, pij_grid, qij_grid, prev_sols);
}
//free memory
free(pij_grid);
free(qij_grid);
free(prev_sols);
}
void normalizeSols(sol *solArray, int data_length) {
// Normalize x values;
float min, max;
min = solArray[0].x;
max = solArray[0].x;
for (int i = 0; i < data_length; i++) {
min = min > solArray[i].x ? solArray[i].x : min;
max = max < solArray[i].x ? solArray[i].x : max;
}
float diff = max - min;
for(int i = 0; i < data_length; i++) {
solArray[i].x = (solArray[i].x - min) / diff;
}
// Normalize y values;
min = solArray[0].y;
max = solArray[0].y;
for (int i = 0; i < data_length; i++) {
min = min > solArray[i].y ? solArray[i].y : min;
max = max < solArray[i].y ? solArray[i].y : max;
}
diff = max - min;
for(int i = 0; i < data_length; i++) {
solArray[i].y = (solArray[i].y - min) / diff;
}
}
void outputSols(sol *solArray, int data_length) {
FILE *fp = fopen("output.txt", "w");
for (int t = 0; t < data_length; t++) fprintf(fp,"%d, %f, %f\n",image_labels[t], solArray[t].x, solArray[t].y);
fclose(fp);
}
int main(int argc, char **argv){
if (argc == 1) {
printf("File name not supplied as argument, quitting\n");
exit(1);
}
cudaDeviceProp pp;
cudaGetDeviceProperties(&pp, 0);
//printf("%zu\n",pp.warpSize);
//default values
dD = 10000;
dP = 784;
perp = 25.0;
l_r = 100.0; //look up Jacob’s 1988 ALR papr
momemtum = 0.5; //change to 0.8 after 250 iters
iters = 1000;
parseCommandLineArguments(argc, argv);
sol *sols = (sol *)malloc(dD*sizeof(sol));
sol *solsCUDA = (sol *)malloc(dD*sizeof(sol));
float *data = (float *)malloc(dD*dP*sizeof(float));
getChunkedValues(data);
double ss, se, ce;
ss = get_walltime();
tsne_baseline(data, sols, iters);
se = get_walltime();
tsne_cuda(data, solsCUDA, iters);
ce = get_walltime();
printf("times: \n\tbaseline: %f\n\tcuda: %f\n",se-ss,ce-se);
normalizeSols(solsCUDA, dD);
outputSols(solsCUDA, dD);
closeFile();
free(data);
free(sols);
free(solsCUDA);
return 0;
} | /* William Dreese + Steven Gschwind
* t-SNE C baseline for mini project
*
* Proper import path before compilation:
* export PATH=${PATH}:/usr/local/cuda-9.1/bin
*/
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#include <time.h>
typedef unsigned long long ull;
unsigned long long dD, dP;
float perp, l_r, momemtum;
int iters;
int *image_labels;
static FILE *FILE_POINTER = NULL;
static int EOF_FLAG = 0;
void setFilePointer(char *file_name);
float *getChunkedValues();
void closeFile();
int parseNextLine(float *data_points);
float getNextValue();
struct sol {
float x,y;
};
void pf(int i){
printf("here %d\n",i);
}
static double get_walltime() {
struct timeval tp;
gettimeofday(&tp, NULL);
return ((double) (tp.tv_sec) + 1e-6 * tp.tv_usec);
}
void setFilePointer(char *file_name) {
FILE_POINTER = fopen(file_name, "r");
if (FILE_POINTER == NULL) {
printf("Error opening file\n");
exit(1);
}
EOF_FLAG = 0;
}
void getChunkedValues(float *data) {
image_labels = (int *)malloc(dD * sizeof(int));
// int throwaway = parseNextLine(data);
// Set image_labels and data values, image_labels will be used for cluster graph
int count;
for (count = 0; count < dD; count ++) {
image_labels[count] = parseNextLine(&data[count * dP]);
}
}
void closeFile() {
fclose(FILE_POINTER);
free(image_labels);
FILE_POINTER = NULL;
}
int parseNextLine(float *data_points) {
if (FILE_POINTER == NULL) {
printf("No file found, call setFilePointer(char *file_name) before runnning\n");
exit(1);
}
// Get label value for image creation
int value = getNextValue();
if (EOF_FLAG > 0) {
return -1; // Finished parsing the file
}
int count = 0;
while (count < dP) {
data_points[count] = getNextValue();
count += 1;
}
return value;
}
// Returns next value from csv file
float getNextValue() {
char value[4] = {0,0,0,0}; // value is between 0 and 256
int pos = 0;
char current;
while (1) {
current = fgetc(FILE_POINTER);
if (current == ',') {
break;
}
else if (current == EOF) {
EOF_FLAG = 1;
break;
}
else if (current == '\n') {
break;
}
value[pos] = current;
pos += 1;
}
return atof(value);
}
void displayHelp() {
printf("\nHELP\nThe program must be run in the format './tsne {filename.csv} {#rows} {#cols} {command} {command_input}....'\n");
printf("The filename.csv, #rows and #cols inputs are necessary. \n#cols should be the number of data points, not including the label column\n");
printf("\nBelow are a set of optional commands:\n");
printf("\tCommand\t\tValue Type\tMeaning\t\n");
printf("\t-----------------------------------------\n");
printf("\t-perp\t\tfloat\t\tSet the perplexity value\n");
printf("\t-learning_rate\tfloat\t\tSet the learning rate\n");
printf("\t-momentum\tfloat\t\tSet the momentum\n");
printf("\t-iters\t\tint\t\tSet the number of iterations\n\n");
printf("For simplicities sake, the commands that we have used to run our test was:\n");
printf("\t./tsne fashion-mnist_test.csv 10000 784\n");
printf("We modified the optional input as necessary\n");
}
void parseCommandLineArguments(int argc, char **argv) {
if (argc < 2) {
printf("Illegal number of arguments supplied. Displaying help (-h)\n");
displayHelp();
exit(1);
}
if (strcmp(argv[1], "-h") == 0) {
displayHelp();
exit(0);
} else {
setFilePointer(argv[1]);
}
if (argc % 2 != 0 || argc < 4) {
printf("Illegal number of arguments supplied. Displaying help (-h)\n");
displayHelp();
exit(1);
}
// Set columns and width
dD = atoi(argv[2]);
dP = atoi(argv[3]);
// Set each of the optional commandline arguments
int i;
float arg_value;
for (i = 4; i < argc; i += 2) {
arg_value = atof(argv[i+1]);
if (strcmp(argv[i], "-perp") == 0) {
perp = arg_value;
} else if (strcmp(argv[i], "-learning_rate") == 0) {
l_r = arg_value;
} else if (strcmp(argv[i], "-momentum") == 0) {
momemtum = arg_value;
} else if (strcmp(argv[i], "-iters") == 0) {
iters = arg_value;
} else {
printf("Command (%s) not found\n", argv[i]);
}
}
printf("Arguments:\n");
printf("Perplexity: %g\n", perp);
printf("Learning_rate: %g\n", l_r);
printf("Momentum: %g\n", momemtum);
printf("Iterations: %d\n", iters);
}
//find euclidean distance for two data points with arbitrary dimensions
float euclidean_dist(float *xi, float *xj){
int i;
float total = 0;
for (i = 0; i < dP; i++) total += (xi[i]-xj[i])*(xi[i]-xj[i]);
return sqrt(total);
}
//compute true similarity scores between data points
void compute_pij(float *data, float *pij_grid){
unsigned long long i, j, k;
float total_prob, val;
for (i = 0; i < dD; i++){
total_prob = 0;
for (j = 0; j < dD; j++){
val = 0;
if (i == j) pij_grid[i*dD+j] = 0;
else {
for (k = 0; k < dP; k++) val += (data[i*dP+k]-data[j*dP+k])*(data[i*dP+k]-data[j*dP+k]);
val = expf((0.0-sqrt(val))/(2.0*perp*perp));
total_prob += val;
pij_grid[i*dD+j] = val;
}
}
for (j = 0; j < dD; j++) pij_grid[i*dD+j] /= total_prob;
}
}
/*
//compute true similarity scores between data points
void compute_pij_hbeta(float *data, float *pij_grid){
unsigned long long i, j, k, tries;
float total_prob, val, beta, bmax, bmin, dp, hval;
float tol = 0.00001;
float logp = logf(perp);
float *dist_temp = (float *)malloc(dD*sizeof(float));
for (i = 0; i < dD; i++){
total_prob = 0;
beta = 1.0;
bmax = 10000.0;
bmin = -10000.0;
for (j = 0; j < dD; j++){
val = 0;
if (i == j) {
pij_grid[i*dD+j] = 0;
dist_temp[j] = 0.0;
}
else {
for (k = 0; k < dP; k++) val += (data[i*dP+k]-data[j*dP+k])*(data[i*dP+k]-data[j*dP+k]);
dist_temp[j] = sqrt(val);
}
}
tries = 0;
do {
if (tries != 0){
if ((hval-logp) > 0.0){
bmin = beta;
if (bmax == 10000 || bmax == -10000) beta *= 2.0;
else beta = (beta + bmax) / 2.0;
}
else {
bmax = beta;
if (bmin == 10000 || bmin == -10000) beta /= 2.0;
else beta = (beta + bmin) / 2.0;
}
}
tries++;
dp = 0;
for (j = 0; j < dD; j++){
val = expf((0.0-dist_temp[j])*beta);
total_prob += val;
pij_grid[i*dD+j] = val;
dp += val*dist_temp[j];
}
hval = logf(total_prob) + ( beta * dp / total_prob);
for (j = 0; j < dD; j++) pij_grid[i*dD+j] /= total_prob;
} while (abs(hval-logp) > tol && tries < 50);
}
free(dist_temp);
}
*/
//pre-processing of pij rid, saves time and increases visual accuracy
void symmetric_pij(float *pij_grid){
int i, j;
float val;
for (i = 0; i < dD; i++){
for (j = i+1; j < dD; j++){
val = (pij_grid[i*dD+j] + pij_grid[j*dD+i]) / (float)(2*dD);
pij_grid[i*dD+j] = val;
pij_grid[j*dD+i] = val;
}
}
}
//each potential solution is randomized 0 < x,y < 1
void random_solutions(sol *sols){
int i;
for (i = 0; i < dD; i++){
sols[i].x = (float)rand() / (float)RAND_MAX;
sols[i].y = (float)rand() / (float)RAND_MAX;
}
}
//calculate euclidean distance between two 2D points
float sol_ed(sol i, sol j){
return sqrt(((i.x-j.x)*(i.x-j.x))+((i.y-j.y)*(i.y-j.y)));
}
//calculate low-dimensionality similarity grid
void compute_qij(sol *sols, float *qij_grid){
unsigned long long i, j;
float total, val;
for (i = 0; i < dD; i++){
total = 0;
for (j = 0; j < dD; j++){
if (i == j) qij_grid[i*dD+j] = 0;
else {
val = 1.0 / (1.0+sol_ed(sols[i], sols[j]));
total += val;
qij_grid[i*dD+j] = val;
}
}
for (j = 0; j < dD; j++) qij_grid[i*dD+j] /= total;
// TODO: subtract so k!=i
}
}
//calculates and applies gradients to each solution
void compute_gradients(sol *sols, float *pij_grid, float *qij_grid, sol *prev_sols){
ull i, j;
float gradX, gradY, prevX, prevY, pq, ed;
for (i = 0; i < dD; i++){
gradX = 0; gradY = 0;
for (j = 0; j < dD; j++){
pq = (pij_grid[i*dD+j] - qij_grid[i*dD+j]);
ed = 1.0 / (1.0 + sol_ed(sols[i],sols[j]));
gradX += pq * (sols[i].x - sols[j].x) * ed;
gradY += pq * (sols[i].y - sols[j].y) * ed;
}
gradX *= 4; gradY *= 4;
prevX = sols[i].x; prevY = sols[i].y;
sols[i].x += l_r*gradX + momemtum*(sols[i].x - prev_sols[i].x);
sols[i].y += l_r*gradY + momemtum*(sols[i].y - prev_sols[i].y);
prev_sols[i].x = prevX; prev_sols[i].y = prevY;
}
}
//honestly, the exact same as baseline compute_pij, except each row is sent to it's own thread
__global__ void compute_pij_kernel_A(float *data, float *pij, ull dD, ull dP, float perp, ull offset){
ull k;
ull i = (ull) (blockIdx.x * blockDim.x + threadIdx.x);
ull j = (ull) (offset * blockDim.y + threadIdx.y);
float dist = 0;
float val;
if (i < dD && j < dD){
for (k = 0; k < dP; k++) dist += (data[i*dP+k]-data[j*dP+k])*(data[i*dP+k]-data[j*dP+k]);
val = expf((0.0-sqrt(dist))/(2.0*perp*perp));
pij[i*dD+j] = val;
if (i == j) pij[i*dD+j] = 0.0;
}
}
//compute total per row, divide each element
__global__ void compute_pij_kernel_B(float *pij, ull dD){
ull i = (ull) (blockIdx.x * blockDim.x + threadIdx.x);
ull j;
float total = 0;
if (i < dD){
for (j = 0; j < dD; j++) total += pij[i*dD+j];
for (j = 0; j < dD; j++) pij[i*dD+j] /= total;
}
}
//balances pij for increased accuracy
__global__ void symettric_pij_kernel(float *pij, ull dD){
ull i = (ull) blockIdx.x * blockDim.x + threadIdx.x;
ull j = (ull) blockIdx.y * blockDim.y + threadIdx.y;
float val;
if (i < dD && j < dD && i < j){
val = (pij[i*dD+j]+pij[j*dD+i]) / (float)(2*dD);
pij[i*dD+j] = val;
pij[j*dD+i] = val;
}
}
//access function for compute_pij_kernel
void cuda_compute_pij(float *data, float *pij){
int ys = ceil((float)dD / 32.0);
dim3 threads1D(1024);
dim3 blocks1D(ceil((float)dD / 1024.0));
dim3 threads2D(32,32);
dim3 blocks2D(ys, 1);
dim3 blocks2Da(ys, ys);
for (ull y = 0; y < ys; y++){
compute_pij_kernel_A<<<blocks2D, threads2D>>>(data, pij, dD, dP, perp, y);
}
hipFree(data);
compute_pij_kernel_B<<<blocks1D, threads1D>>>(pij, dD);
symettric_pij_kernel<<<blocks2Da, threads2D>>>(pij, dD);
}
__global__ void compute_qij_kernel(sol *sols, float *qij, ull dD){
ull i = (ull) blockIdx.x * blockDim.x + threadIdx.x;
ull j;
float total, val, dist;
if (i < dD){
total = 0;
for (j = 0; j < dD; j++){
if (i == j) qij[i*dD+j] = 0;
else {
dist = (sols[i].x - sols[j].x)*(sols[i].x-sols[j].x) + (sols[i].y - sols[j].y)*(sols[i].y-sols[j].y);
val = 1.0 / (1.0+sqrt(dist));
total += val;
qij[i*dD+j] = val;
}
}
for (j = 0; j < dD; j++) qij[i*dD+j] /= total;
}
}
//access function to compute_qij_kernel
void cuda_compute_qij(sol *sols, float *qij){
dim3 threads(1024);
dim3 blocks(ceil((float)dD / 1024.0));
compute_qij_kernel<<<blocks, threads>>>(sols, qij, dD);
}
__global__ void compute_gradients_kernel(sol *sols, float *pij, float *qij, sol *prev, ull dD, float momemtum, float l_r){
ull i = (ull) (blockIdx.x * blockDim.x + threadIdx.x);
ull j;
float gradX, gradY, prevX, prevY, pq, ed;
if (i < dD){
gradX = 0; gradY = 0;
for (j = 0; j < dD; j++){
pq = (pij[i*dD+j] - qij[i*dD+j]);
ed = (sols[i].x - sols[j].x)*(sols[i].x-sols[j].x) + (sols[i].y - sols[j].y)*(sols[i].y-sols[j].y);
ed = 1.0 / (1.0 + sqrt(ed));
gradX += pq * (sols[i].x - sols[j].x) * ed;
gradY += pq * (sols[i].y - sols[j].y) * ed;
}
gradX *= 4; gradY *= 4;
prevX = sols[i].x; prevY = sols[i].y;
sols[i].x += l_r*gradX + momemtum*(sols[i].x - prev[i].x);
sols[i].y += l_r*gradY + momemtum*(sols[i].y - prev[i].y);
prev[i].x = prevX; prev[i].y = prevY;
}
}
void cuda_compute_gradients(sol *sols, float *pij, float *qij, sol *prev){
dim3 threads(1024);
dim3 blocks(ceil((float)dD / 1024.0));
compute_gradients_kernel<<<blocks, threads>>>(sols, pij, qij, prev, dD, momemtum, l_r);
hipDeviceSynchronize();
}
void cEcheck(hipError_t cE, const char *type){
if (cE != hipSuccess){
printf("Error while %s memory.\n",type);
printf( hipGetErrorString( hipGetLastError()));
exit(1);
}
}
void tsne_cuda(float *data, sol *sols, int iters){
int t;
//same mallocs as baseline below
sol *prev_sols = (sol *) malloc(dD*sizeof(sol));
for (t = 0; t < dD; t++){ prev_sols[t].x = 0.0; prev_sols[t].y = 0.0; }
random_solutions(sols);
//corresponding matrixes that live on device
float *data_d, *pij_grid_d, *qij_grid_d;
sol *sols_d, *prev_sols_d;
cEcheck( hipMalloc((void **)&data_d, dD*dP*sizeof(float)), "allocating" );
cEcheck( hipMalloc((void **)&pij_grid_d, dD*dD*sizeof(float)), "allocating" );
cEcheck( hipMemcpy(data_d, data, dD*dP*sizeof(float), hipMemcpyHostToDevice), "transferring" );
cuda_compute_pij(data_d, pij_grid_d); //also frees data
printf("Making pij (CUDA)\n");
cEcheck( hipMalloc((void **)&qij_grid_d, dD*dD*sizeof(float)), "allocating" );
cEcheck( hipMalloc((void **)&sols_d, dD*sizeof(sol)), "allocating" );
cEcheck( hipMalloc((void **)&prev_sols_d, dD*sizeof(sol)), "allocating" );
cEcheck( hipMemcpy(sols_d, sols, dD*sizeof(sol), hipMemcpyHostToDevice), "transferring" );
cEcheck( hipMemcpy(prev_sols_d, prev_sols, dD*sizeof(sol), hipMemcpyHostToDevice), "transferring" );;
for (t = 0; t < iters; t++){
cuda_compute_qij(sols_d, qij_grid_d);
cuda_compute_gradients(sols_d, pij_grid_d, qij_grid_d, prev_sols_d);
if (t == 250) momemtum = 0.8;
}
cEcheck( hipMemcpy(sols, sols_d, dD*sizeof(sol), hipMemcpyDeviceToHost), "transferring" );
pf(66);
hipFree(pij_grid_d);
hipFree(qij_grid_d);
hipFree(sols_d);
hipFree(prev_sols_d);
free(prev_sols);
}
//the main function
void tsne_baseline(float *data, sol *sols, int iters){
int t;
//malloc grids, init prev_sol
float *pij_grid = (float *)malloc(dD*dD*sizeof(float));
float *qij_grid = (float *)malloc(dD*dD*sizeof(float));
sol *prev_sols = (sol *) malloc(dD*sizeof(sol));
for (t = 0; t < dD; t++){
prev_sols[t].x = 0.0;
prev_sols[t].y = 0.0;
}
//prepare for loop
compute_pij(data, pij_grid);
symmetric_pij(pij_grid);
random_solutions(sols);
//slowly move each x/y closer to it's true value
for (t = 0; t<iters; t++){
compute_qij(sols, qij_grid);
compute_gradients(sols, pij_grid, qij_grid, prev_sols);
}
//free memory
free(pij_grid);
free(qij_grid);
free(prev_sols);
}
void normalizeSols(sol *solArray, int data_length) {
// Normalize x values;
float min, max;
min = solArray[0].x;
max = solArray[0].x;
for (int i = 0; i < data_length; i++) {
min = min > solArray[i].x ? solArray[i].x : min;
max = max < solArray[i].x ? solArray[i].x : max;
}
float diff = max - min;
for(int i = 0; i < data_length; i++) {
solArray[i].x = (solArray[i].x - min) / diff;
}
// Normalize y values;
min = solArray[0].y;
max = solArray[0].y;
for (int i = 0; i < data_length; i++) {
min = min > solArray[i].y ? solArray[i].y : min;
max = max < solArray[i].y ? solArray[i].y : max;
}
diff = max - min;
for(int i = 0; i < data_length; i++) {
solArray[i].y = (solArray[i].y - min) / diff;
}
}
void outputSols(sol *solArray, int data_length) {
FILE *fp = fopen("output.txt", "w");
for (int t = 0; t < data_length; t++) fprintf(fp,"%d, %f, %f\n",image_labels[t], solArray[t].x, solArray[t].y);
fclose(fp);
}
int main(int argc, char **argv){
if (argc == 1) {
printf("File name not supplied as argument, quitting\n");
exit(1);
}
hipDeviceProp_t pp;
hipGetDeviceProperties(&pp, 0);
//printf("%zu\n",pp.warpSize);
//default values
dD = 10000;
dP = 784;
perp = 25.0;
l_r = 100.0; //look up Jacob’s 1988 ALR papr
momemtum = 0.5; //change to 0.8 after 250 iters
iters = 1000;
parseCommandLineArguments(argc, argv);
sol *sols = (sol *)malloc(dD*sizeof(sol));
sol *solsCUDA = (sol *)malloc(dD*sizeof(sol));
float *data = (float *)malloc(dD*dP*sizeof(float));
getChunkedValues(data);
double ss, se, ce;
ss = get_walltime();
tsne_baseline(data, sols, iters);
se = get_walltime();
tsne_cuda(data, solsCUDA, iters);
ce = get_walltime();
printf("times: \n\tbaseline: %f\n\tcuda: %f\n",se-ss,ce-se);
normalizeSols(solsCUDA, dD);
outputSols(solsCUDA, dD);
closeFile();
free(data);
free(sols);
free(solsCUDA);
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void STREAM_Scale(float *a, float *b, float scale, size_t len)
{
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < len) {
b[idx] = scale* a[idx];
idx += blockDim.x * gridDim.x;
}
} | code for sm_80
Function : _Z12STREAM_ScalePfS_fm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff067624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.SHL.U32 R4, R0.reuse, 0x4, RZ ; /* 0x0000000400047824 */
/* 0x041fe200078e00ff */
/*00b0*/ SHF.L.U64.HI R5, R0, 0x2, R9 ; /* 0x0000000200057819 */
/* 0x000fc80000010209 */
/*00c0*/ IADD3 R2, P0, R4, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x000fc80007f1e0ff */
/*00d0*/ IADD3.X R3, R5, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590005037a10 */
/* 0x000fca00007fe4ff */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IADD3 R4, P0, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fe20007f1e0ff */
/*0100*/ IMAD R11, R6, c[0x0][0xc], RZ ; /* 0x00000300060b7a24 */
/* 0x000fc600078e02ff */
/*0110*/ IADD3.X R5, R5, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0005057a10 */
/* 0x000fe400007fe4ff */
/*0120*/ IADD3 R0, P0, R11, R0, RZ ; /* 0x000000000b007210 */
/* 0x000fca0007f1e0ff */
/*0130*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0150*/ ISETP.GE.U32.AND.EX P0, PT, R9, c[0x0][0x17c], PT, P0 ; /* 0x00005f0009007a0c */
/* 0x000fe20003f06100 */
/*0160*/ FMUL R7, R2, c[0x0][0x170] ; /* 0x00005c0002077a20 */
/* 0x004fca0000400000 */
/*0170*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ee000c101904 */
/*0180*/ @!P0 BRA 0xa0 ; /* 0xffffff1000008947 */
/* 0x000fea000383ffff */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void STREAM_Scale(float *a, float *b, float scale, size_t len)
{
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < len) {
b[idx] = scale* a[idx];
idx += blockDim.x * gridDim.x;
}
} | .file "tmpxft_00023049_00000000-6_STREAM_Scale.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z12STREAM_ScalePfS_fmPfS_fm
.type _Z36__device_stub__Z12STREAM_ScalePfS_fmPfS_fm, @function
_Z36__device_stub__Z12STREAM_ScalePfS_fmPfS_fm:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12STREAM_ScalePfS_fm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z12STREAM_ScalePfS_fmPfS_fm, .-_Z36__device_stub__Z12STREAM_ScalePfS_fmPfS_fm
.globl _Z12STREAM_ScalePfS_fm
.type _Z12STREAM_ScalePfS_fm, @function
_Z12STREAM_ScalePfS_fm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12STREAM_ScalePfS_fmPfS_fm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12STREAM_ScalePfS_fm, .-_Z12STREAM_ScalePfS_fm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12STREAM_ScalePfS_fm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12STREAM_ScalePfS_fm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void STREAM_Scale(float *a, float *b, float scale, size_t len)
{
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < len) {
b[idx] = scale* a[idx];
idx += blockDim.x * gridDim.x;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void STREAM_Scale(float *a, float *b, float scale, size_t len)
{
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < len) {
b[idx] = scale* a[idx];
idx += blockDim.x * gridDim.x;
}
} |
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