system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void STREAM_Scale(float *a, float *b, float scale, size_t len)
{
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < len) {
b[idx] = scale* a[idx];
idx += blockDim.x * gridDim.x;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12STREAM_ScalePfS_fm
.globl _Z12STREAM_ScalePfS_fm
.p2align 8
.type _Z12STREAM_ScalePfS_fm,@function
_Z12STREAM_ScalePfS_fm:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s10, s[4:5], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s1, s[0:1], 0x10
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s9, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mov_b32 s12, s9
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s10, s8
s_lshl_b64 s[10:11], s[8:9], 2
.p2align 6
.LBB0_2:
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s8
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
global_load_b32 v0, v[5:6], off
v_add_co_u32 v5, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
v_add_co_u32 v3, s0, v3, s10
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s11, v4, s0
s_or_b32 s12, vcc_lo, s12
s_waitcnt vmcnt(0)
v_mul_f32_e32 v0, s1, v0
global_store_b32 v[5:6], v0, off
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12STREAM_ScalePfS_fm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12STREAM_ScalePfS_fm, .Lfunc_end0-_Z12STREAM_ScalePfS_fm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12STREAM_ScalePfS_fm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12STREAM_ScalePfS_fm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void STREAM_Scale(float *a, float *b, float scale, size_t len)
{
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < len) {
b[idx] = scale* a[idx];
idx += blockDim.x * gridDim.x;
}
} | .text
.file "STREAM_Scale.hip"
.globl _Z27__device_stub__STREAM_ScalePfS_fm # -- Begin function _Z27__device_stub__STREAM_ScalePfS_fm
.p2align 4, 0x90
.type _Z27__device_stub__STREAM_ScalePfS_fm,@function
_Z27__device_stub__STREAM_ScalePfS_fm: # @_Z27__device_stub__STREAM_ScalePfS_fm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 4(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12STREAM_ScalePfS_fm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__STREAM_ScalePfS_fm, .Lfunc_end0-_Z27__device_stub__STREAM_ScalePfS_fm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12STREAM_ScalePfS_fm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12STREAM_ScalePfS_fm,@object # @_Z12STREAM_ScalePfS_fm
.section .rodata,"a",@progbits
.globl _Z12STREAM_ScalePfS_fm
.p2align 3, 0x0
_Z12STREAM_ScalePfS_fm:
.quad _Z27__device_stub__STREAM_ScalePfS_fm
.size _Z12STREAM_ScalePfS_fm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12STREAM_ScalePfS_fm"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__STREAM_ScalePfS_fm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12STREAM_ScalePfS_fm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12STREAM_ScalePfS_fm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff067624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.SHL.U32 R4, R0.reuse, 0x4, RZ ; /* 0x0000000400047824 */
/* 0x041fe200078e00ff */
/*00b0*/ SHF.L.U64.HI R5, R0, 0x2, R9 ; /* 0x0000000200057819 */
/* 0x000fc80000010209 */
/*00c0*/ IADD3 R2, P0, R4, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x000fc80007f1e0ff */
/*00d0*/ IADD3.X R3, R5, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590005037a10 */
/* 0x000fca00007fe4ff */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IADD3 R4, P0, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fe20007f1e0ff */
/*0100*/ IMAD R11, R6, c[0x0][0xc], RZ ; /* 0x00000300060b7a24 */
/* 0x000fc600078e02ff */
/*0110*/ IADD3.X R5, R5, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0005057a10 */
/* 0x000fe400007fe4ff */
/*0120*/ IADD3 R0, P0, R11, R0, RZ ; /* 0x000000000b007210 */
/* 0x000fca0007f1e0ff */
/*0130*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0150*/ ISETP.GE.U32.AND.EX P0, PT, R9, c[0x0][0x17c], PT, P0 ; /* 0x00005f0009007a0c */
/* 0x000fe20003f06100 */
/*0160*/ FMUL R7, R2, c[0x0][0x170] ; /* 0x00005c0002077a20 */
/* 0x004fca0000400000 */
/*0170*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ee000c101904 */
/*0180*/ @!P0 BRA 0xa0 ; /* 0xffffff1000008947 */
/* 0x000fea000383ffff */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12STREAM_ScalePfS_fm
.globl _Z12STREAM_ScalePfS_fm
.p2align 8
.type _Z12STREAM_ScalePfS_fm,@function
_Z12STREAM_ScalePfS_fm:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s10, s[4:5], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s1, s[0:1], 0x10
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s9, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mov_b32 s12, s9
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s10, s8
s_lshl_b64 s[10:11], s[8:9], 2
.p2align 6
.LBB0_2:
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s8
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
global_load_b32 v0, v[5:6], off
v_add_co_u32 v5, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
v_add_co_u32 v3, s0, v3, s10
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s11, v4, s0
s_or_b32 s12, vcc_lo, s12
s_waitcnt vmcnt(0)
v_mul_f32_e32 v0, s1, v0
global_store_b32 v[5:6], v0, off
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12STREAM_ScalePfS_fm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12STREAM_ScalePfS_fm, .Lfunc_end0-_Z12STREAM_ScalePfS_fm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12STREAM_ScalePfS_fm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12STREAM_ScalePfS_fm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00023049_00000000-6_STREAM_Scale.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z12STREAM_ScalePfS_fmPfS_fm
.type _Z36__device_stub__Z12STREAM_ScalePfS_fmPfS_fm, @function
_Z36__device_stub__Z12STREAM_ScalePfS_fmPfS_fm:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12STREAM_ScalePfS_fm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z12STREAM_ScalePfS_fmPfS_fm, .-_Z36__device_stub__Z12STREAM_ScalePfS_fmPfS_fm
.globl _Z12STREAM_ScalePfS_fm
.type _Z12STREAM_ScalePfS_fm, @function
_Z12STREAM_ScalePfS_fm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12STREAM_ScalePfS_fmPfS_fm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12STREAM_ScalePfS_fm, .-_Z12STREAM_ScalePfS_fm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12STREAM_ScalePfS_fm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12STREAM_ScalePfS_fm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "STREAM_Scale.hip"
.globl _Z27__device_stub__STREAM_ScalePfS_fm # -- Begin function _Z27__device_stub__STREAM_ScalePfS_fm
.p2align 4, 0x90
.type _Z27__device_stub__STREAM_ScalePfS_fm,@function
_Z27__device_stub__STREAM_ScalePfS_fm: # @_Z27__device_stub__STREAM_ScalePfS_fm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 4(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12STREAM_ScalePfS_fm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__STREAM_ScalePfS_fm, .Lfunc_end0-_Z27__device_stub__STREAM_ScalePfS_fm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12STREAM_ScalePfS_fm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12STREAM_ScalePfS_fm,@object # @_Z12STREAM_ScalePfS_fm
.section .rodata,"a",@progbits
.globl _Z12STREAM_ScalePfS_fm
.p2align 3, 0x0
_Z12STREAM_ScalePfS_fm:
.quad _Z27__device_stub__STREAM_ScalePfS_fm
.size _Z12STREAM_ScalePfS_fm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12STREAM_ScalePfS_fm"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__STREAM_ScalePfS_fm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12STREAM_ScalePfS_fm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void matAdd(double *a_D, double *c_D)
{
int t_rank;
t_rank = threadIdx.y*blockDim.x + threadIdx.x;
c_D[t_rank] = t_rank+1;
}
int main(int argc, char **argv)
{
int i, j;
int size, block_size = 8, grid_size = 1;
double *c_H, *c_D, *a_H, *a_D;
size = block_size*block_size*sizeof(double);
a_H = (double *)malloc(size);
c_H = (double *)malloc(size);
cudaMalloc((void **)&a_D, size);
cudaMalloc((void **)&c_D, size);
for (i=0; i<block_size; i++)
for (j=0; j<block_size; j++)
a_H[(i*block_size)+j]=(i*block_size)+j;
for(i = 0; i < block_size; i++, printf("\n"))
for (j=0; j < block_size; j++)
//printf("matric[%d][%d] is %f\n", i, j, c_H[(i*block_size)+j]);
printf(" %4.1f", a_H[(i*block_size)+j]);
printf("\n");
cudaMemcpy(a_D, a_H, size, cudaMemcpyHostToDevice);
dim3 Block(block_size, block_size);
dim3 Grid(grid_size, grid_size);
matAdd<<<Grid, Block>>>(a_D, c_D);
cudaMemcpy(c_H, c_D, size, cudaMemcpyDeviceToHost);
for(i = 0; i < block_size; i++, printf("\n"))
for (j=0; j < block_size; j++)
//printf("matric[%d][%d] is %f\n", i, j, c_H[(i*block_size)+j]);
printf(" %4.1f", c_H[(i*block_size)+j]);
free(a_H);
free(c_H);
cudaFree(a_D);
cudaFree(c_D);
return 0;
} | code for sm_80
Function : _Z6matAddPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002200 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IADD3 R2, R4.reuse, 0x1, RZ ; /* 0x0000000104027810 */
/* 0x040fe20007ffe0ff */
/*0070*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*0080*/ I2F.F64 R2, R2 ; /* 0x0000000200027312 */
/* 0x000e240000201c00 */
/*0090*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x001fe2000c101b04 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void matAdd(double *a_D, double *c_D)
{
int t_rank;
t_rank = threadIdx.y*blockDim.x + threadIdx.x;
c_D[t_rank] = t_rank+1;
}
int main(int argc, char **argv)
{
int i, j;
int size, block_size = 8, grid_size = 1;
double *c_H, *c_D, *a_H, *a_D;
size = block_size*block_size*sizeof(double);
a_H = (double *)malloc(size);
c_H = (double *)malloc(size);
cudaMalloc((void **)&a_D, size);
cudaMalloc((void **)&c_D, size);
for (i=0; i<block_size; i++)
for (j=0; j<block_size; j++)
a_H[(i*block_size)+j]=(i*block_size)+j;
for(i = 0; i < block_size; i++, printf("\n"))
for (j=0; j < block_size; j++)
//printf("matric[%d][%d] is %f\n", i, j, c_H[(i*block_size)+j]);
printf(" %4.1f", a_H[(i*block_size)+j]);
printf("\n");
cudaMemcpy(a_D, a_H, size, cudaMemcpyHostToDevice);
dim3 Block(block_size, block_size);
dim3 Grid(grid_size, grid_size);
matAdd<<<Grid, Block>>>(a_D, c_D);
cudaMemcpy(c_H, c_D, size, cudaMemcpyDeviceToHost);
for(i = 0; i < block_size; i++, printf("\n"))
for (j=0; j < block_size; j++)
//printf("matric[%d][%d] is %f\n", i, j, c_H[(i*block_size)+j]);
printf(" %4.1f", c_H[(i*block_size)+j]);
free(a_H);
free(c_H);
cudaFree(a_D);
cudaFree(c_D);
return 0;
} | .file "tmpxft_00111b95_00000000-6_matrixAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6matAddPdS_PdS_
.type _Z27__device_stub__Z6matAddPdS_PdS_, @function
_Z27__device_stub__Z6matAddPdS_PdS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6matAddPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z6matAddPdS_PdS_, .-_Z27__device_stub__Z6matAddPdS_PdS_
.globl _Z6matAddPdS_
.type _Z6matAddPdS_, @function
_Z6matAddPdS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6matAddPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6matAddPdS_, .-_Z6matAddPdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " %4.1f"
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $512, %edi
call malloc@PLT
movq %rax, %r13
movl $512, %edi
call malloc@PLT
movq %rax, 8(%rsp)
leaq 24(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 512(%r13), %rdi
movq %r13, %rcx
movl $0, %esi
.L12:
movl $0, %eax
.L13:
leal (%rsi,%rax), %edx
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
movsd %xmm0, (%rcx,%rax,8)
addq $1, %rax
cmpq $8, %rax
jne .L13
addl $8, %esi
addq $64, %rcx
cmpq %rdi, %rcx
jne .L12
leaq 64(%r13), %rbp
leaq 576(%r13), %r15
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r14
.L14:
leaq -64(%rbp), %rbx
.L15:
movsd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L15
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $64, %rbp
cmpq %r15, %rbp
jne .L14
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $512, %edx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $8, 32(%rsp)
movl $8, 36(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L17:
movl $2, %ecx
movl $512, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 64(%rbx), %rbp
leaq 576(%rbx), %r15
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r14
.L18:
leaq -64(%rbp), %rbx
.L19:
movsd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L19
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $64, %rbp
cmpq %r15, %rbp
jne .L18
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z27__device_stub__Z6matAddPdS_PdS_
jmp .L17
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6matAddPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matAddPdS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void matAdd(double *a_D, double *c_D)
{
int t_rank;
t_rank = threadIdx.y*blockDim.x + threadIdx.x;
c_D[t_rank] = t_rank+1;
}
int main(int argc, char **argv)
{
int i, j;
int size, block_size = 8, grid_size = 1;
double *c_H, *c_D, *a_H, *a_D;
size = block_size*block_size*sizeof(double);
a_H = (double *)malloc(size);
c_H = (double *)malloc(size);
cudaMalloc((void **)&a_D, size);
cudaMalloc((void **)&c_D, size);
for (i=0; i<block_size; i++)
for (j=0; j<block_size; j++)
a_H[(i*block_size)+j]=(i*block_size)+j;
for(i = 0; i < block_size; i++, printf("\n"))
for (j=0; j < block_size; j++)
//printf("matric[%d][%d] is %f\n", i, j, c_H[(i*block_size)+j]);
printf(" %4.1f", a_H[(i*block_size)+j]);
printf("\n");
cudaMemcpy(a_D, a_H, size, cudaMemcpyHostToDevice);
dim3 Block(block_size, block_size);
dim3 Grid(grid_size, grid_size);
matAdd<<<Grid, Block>>>(a_D, c_D);
cudaMemcpy(c_H, c_D, size, cudaMemcpyDeviceToHost);
for(i = 0; i < block_size; i++, printf("\n"))
for (j=0; j < block_size; j++)
//printf("matric[%d][%d] is %f\n", i, j, c_H[(i*block_size)+j]);
printf(" %4.1f", c_H[(i*block_size)+j]);
free(a_H);
free(c_H);
cudaFree(a_D);
cudaFree(c_D);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void matAdd(double *a_D, double *c_D)
{
int t_rank;
t_rank = threadIdx.y*blockDim.x + threadIdx.x;
c_D[t_rank] = t_rank+1;
}
int main(int argc, char **argv)
{
int i, j;
int size, block_size = 8, grid_size = 1;
double *c_H, *c_D, *a_H, *a_D;
size = block_size*block_size*sizeof(double);
a_H = (double *)malloc(size);
c_H = (double *)malloc(size);
hipMalloc((void **)&a_D, size);
hipMalloc((void **)&c_D, size);
for (i=0; i<block_size; i++)
for (j=0; j<block_size; j++)
a_H[(i*block_size)+j]=(i*block_size)+j;
for(i = 0; i < block_size; i++, printf("\n"))
for (j=0; j < block_size; j++)
//printf("matric[%d][%d] is %f\n", i, j, c_H[(i*block_size)+j]);
printf(" %4.1f", a_H[(i*block_size)+j]);
printf("\n");
hipMemcpy(a_D, a_H, size, hipMemcpyHostToDevice);
dim3 Block(block_size, block_size);
dim3 Grid(grid_size, grid_size);
matAdd<<<Grid, Block>>>(a_D, c_D);
hipMemcpy(c_H, c_D, size, hipMemcpyDeviceToHost);
for(i = 0; i < block_size; i++, printf("\n"))
for (j=0; j < block_size; j++)
//printf("matric[%d][%d] is %f\n", i, j, c_H[(i*block_size)+j]);
printf(" %4.1f", c_H[(i*block_size)+j]);
free(a_H);
free(c_H);
hipFree(a_D);
hipFree(c_D);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void matAdd(double *a_D, double *c_D)
{
int t_rank;
t_rank = threadIdx.y*blockDim.x + threadIdx.x;
c_D[t_rank] = t_rank+1;
}
int main(int argc, char **argv)
{
int i, j;
int size, block_size = 8, grid_size = 1;
double *c_H, *c_D, *a_H, *a_D;
size = block_size*block_size*sizeof(double);
a_H = (double *)malloc(size);
c_H = (double *)malloc(size);
hipMalloc((void **)&a_D, size);
hipMalloc((void **)&c_D, size);
for (i=0; i<block_size; i++)
for (j=0; j<block_size; j++)
a_H[(i*block_size)+j]=(i*block_size)+j;
for(i = 0; i < block_size; i++, printf("\n"))
for (j=0; j < block_size; j++)
//printf("matric[%d][%d] is %f\n", i, j, c_H[(i*block_size)+j]);
printf(" %4.1f", a_H[(i*block_size)+j]);
printf("\n");
hipMemcpy(a_D, a_H, size, hipMemcpyHostToDevice);
dim3 Block(block_size, block_size);
dim3 Grid(grid_size, grid_size);
matAdd<<<Grid, Block>>>(a_D, c_D);
hipMemcpy(c_H, c_D, size, hipMemcpyDeviceToHost);
for(i = 0; i < block_size; i++, printf("\n"))
for (j=0; j < block_size; j++)
//printf("matric[%d][%d] is %f\n", i, j, c_H[(i*block_size)+j]);
printf(" %4.1f", c_H[(i*block_size)+j]);
free(a_H);
free(c_H);
hipFree(a_D);
hipFree(c_D);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matAddPdS_
.globl _Z6matAddPdS_
.p2align 8
.type _Z6matAddPdS_,@function
_Z6matAddPdS_:
s_load_b32 s2, s[0:1], 0x1c
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u32_u24 v2, v0, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, 1, v2
v_lshlrev_b32_e32 v2, 3, v2
v_cvt_f64_i32_e32 v[0:1], v0
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matAddPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 3
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matAddPdS_, .Lfunc_end0-_Z6matAddPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matAddPdS_
.private_segment_fixed_size: 0
.sgpr_count: 3
.sgpr_spill_count: 0
.symbol: _Z6matAddPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void matAdd(double *a_D, double *c_D)
{
int t_rank;
t_rank = threadIdx.y*blockDim.x + threadIdx.x;
c_D[t_rank] = t_rank+1;
}
int main(int argc, char **argv)
{
int i, j;
int size, block_size = 8, grid_size = 1;
double *c_H, *c_D, *a_H, *a_D;
size = block_size*block_size*sizeof(double);
a_H = (double *)malloc(size);
c_H = (double *)malloc(size);
hipMalloc((void **)&a_D, size);
hipMalloc((void **)&c_D, size);
for (i=0; i<block_size; i++)
for (j=0; j<block_size; j++)
a_H[(i*block_size)+j]=(i*block_size)+j;
for(i = 0; i < block_size; i++, printf("\n"))
for (j=0; j < block_size; j++)
//printf("matric[%d][%d] is %f\n", i, j, c_H[(i*block_size)+j]);
printf(" %4.1f", a_H[(i*block_size)+j]);
printf("\n");
hipMemcpy(a_D, a_H, size, hipMemcpyHostToDevice);
dim3 Block(block_size, block_size);
dim3 Grid(grid_size, grid_size);
matAdd<<<Grid, Block>>>(a_D, c_D);
hipMemcpy(c_H, c_D, size, hipMemcpyDeviceToHost);
for(i = 0; i < block_size; i++, printf("\n"))
for (j=0; j < block_size; j++)
//printf("matric[%d][%d] is %f\n", i, j, c_H[(i*block_size)+j]);
printf(" %4.1f", c_H[(i*block_size)+j]);
free(a_H);
free(c_H);
hipFree(a_D);
hipFree(c_D);
return 0;
} | .text
.file "matrixAdd.hip"
.globl _Z21__device_stub__matAddPdS_ # -- Begin function _Z21__device_stub__matAddPdS_
.p2align 4, 0x90
.type _Z21__device_stub__matAddPdS_,@function
_Z21__device_stub__matAddPdS_: # @_Z21__device_stub__matAddPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6matAddPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__matAddPdS_, .Lfunc_end0-_Z21__device_stub__matAddPdS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $96, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $512, %edi # imm = 0x200
callq malloc
movq %rax, %rbx
movl $512, %edi # imm = 0x200
callq malloc
movq %rax, %r14
movq %rsp, %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
leaq 8(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # %.preheader63
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
movl $8, %edx
movq %rax, %rsi
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtsi2sd %esi, %xmm0
movsd %xmm0, (%rbx,%rsi,8)
incq %rsi
decq %rdx
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rcx
addq $8, %rax
cmpq $8, %rcx
jne .LBB1_1
# %bb.4: # %.preheader61.preheader
xorl %r15d, %r15d
movq %rbx, %r12
.p2align 4, 0x90
.LBB1_5: # %.preheader61
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r12,%r13,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r13
cmpq $8, %r13
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
incq %r15
movl $10, %edi
callq putchar@PLT
addq $64, %r12
cmpq $8, %r15
jne .LBB1_5
# %bb.8:
movl $10, %edi
callq putchar@PLT
movq (%rsp), %rdi
movl $512, %edx # imm = 0x200
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $34359738376, %rdx # imm = 0x800000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6matAddPdS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
movq 8(%rsp), %rsi
movl $512, %edx # imm = 0x200
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
movq %r14, %r12
.p2align 4, 0x90
.LBB1_11: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_12: # Parent Loop BB1_11 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r12,%r13,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r13
cmpq $8, %r13
jne .LBB1_12
# %bb.13: # in Loop: Header=BB1_11 Depth=1
incq %r15
movl $10, %edi
callq putchar@PLT
addq $64, %r12
cmpq $8, %r15
jne .LBB1_11
# %bb.14:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matAddPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matAddPdS_,@object # @_Z6matAddPdS_
.section .rodata,"a",@progbits
.globl _Z6matAddPdS_
.p2align 3, 0x0
_Z6matAddPdS_:
.quad _Z21__device_stub__matAddPdS_
.size _Z6matAddPdS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " %4.1f"
.size .L.str, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6matAddPdS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matAddPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matAddPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6matAddPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002200 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IADD3 R2, R4.reuse, 0x1, RZ ; /* 0x0000000104027810 */
/* 0x040fe20007ffe0ff */
/*0070*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*0080*/ I2F.F64 R2, R2 ; /* 0x0000000200027312 */
/* 0x000e240000201c00 */
/*0090*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x001fe2000c101b04 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matAddPdS_
.globl _Z6matAddPdS_
.p2align 8
.type _Z6matAddPdS_,@function
_Z6matAddPdS_:
s_load_b32 s2, s[0:1], 0x1c
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u32_u24 v2, v0, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, 1, v2
v_lshlrev_b32_e32 v2, 3, v2
v_cvt_f64_i32_e32 v[0:1], v0
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matAddPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 3
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matAddPdS_, .Lfunc_end0-_Z6matAddPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matAddPdS_
.private_segment_fixed_size: 0
.sgpr_count: 3
.sgpr_spill_count: 0
.symbol: _Z6matAddPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00111b95_00000000-6_matrixAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6matAddPdS_PdS_
.type _Z27__device_stub__Z6matAddPdS_PdS_, @function
_Z27__device_stub__Z6matAddPdS_PdS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6matAddPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z6matAddPdS_PdS_, .-_Z27__device_stub__Z6matAddPdS_PdS_
.globl _Z6matAddPdS_
.type _Z6matAddPdS_, @function
_Z6matAddPdS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6matAddPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6matAddPdS_, .-_Z6matAddPdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " %4.1f"
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $512, %edi
call malloc@PLT
movq %rax, %r13
movl $512, %edi
call malloc@PLT
movq %rax, 8(%rsp)
leaq 24(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 512(%r13), %rdi
movq %r13, %rcx
movl $0, %esi
.L12:
movl $0, %eax
.L13:
leal (%rsi,%rax), %edx
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
movsd %xmm0, (%rcx,%rax,8)
addq $1, %rax
cmpq $8, %rax
jne .L13
addl $8, %esi
addq $64, %rcx
cmpq %rdi, %rcx
jne .L12
leaq 64(%r13), %rbp
leaq 576(%r13), %r15
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r14
.L14:
leaq -64(%rbp), %rbx
.L15:
movsd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L15
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $64, %rbp
cmpq %r15, %rbp
jne .L14
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $512, %edx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $8, 32(%rsp)
movl $8, 36(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L17:
movl $2, %ecx
movl $512, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 64(%rbx), %rbp
leaq 576(%rbx), %r15
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r14
.L18:
leaq -64(%rbp), %rbx
.L19:
movsd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L19
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $64, %rbp
cmpq %r15, %rbp
jne .L18
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z27__device_stub__Z6matAddPdS_PdS_
jmp .L17
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6matAddPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matAddPdS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixAdd.hip"
.globl _Z21__device_stub__matAddPdS_ # -- Begin function _Z21__device_stub__matAddPdS_
.p2align 4, 0x90
.type _Z21__device_stub__matAddPdS_,@function
_Z21__device_stub__matAddPdS_: # @_Z21__device_stub__matAddPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6matAddPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__matAddPdS_, .Lfunc_end0-_Z21__device_stub__matAddPdS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $96, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $512, %edi # imm = 0x200
callq malloc
movq %rax, %rbx
movl $512, %edi # imm = 0x200
callq malloc
movq %rax, %r14
movq %rsp, %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
leaq 8(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # %.preheader63
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
movl $8, %edx
movq %rax, %rsi
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtsi2sd %esi, %xmm0
movsd %xmm0, (%rbx,%rsi,8)
incq %rsi
decq %rdx
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rcx
addq $8, %rax
cmpq $8, %rcx
jne .LBB1_1
# %bb.4: # %.preheader61.preheader
xorl %r15d, %r15d
movq %rbx, %r12
.p2align 4, 0x90
.LBB1_5: # %.preheader61
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r12,%r13,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r13
cmpq $8, %r13
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
incq %r15
movl $10, %edi
callq putchar@PLT
addq $64, %r12
cmpq $8, %r15
jne .LBB1_5
# %bb.8:
movl $10, %edi
callq putchar@PLT
movq (%rsp), %rdi
movl $512, %edx # imm = 0x200
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $34359738376, %rdx # imm = 0x800000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6matAddPdS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
movq 8(%rsp), %rsi
movl $512, %edx # imm = 0x200
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
movq %r14, %r12
.p2align 4, 0x90
.LBB1_11: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_12: # Parent Loop BB1_11 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r12,%r13,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r13
cmpq $8, %r13
jne .LBB1_12
# %bb.13: # in Loop: Header=BB1_11 Depth=1
incq %r15
movl $10, %edi
callq putchar@PLT
addq $64, %r12
cmpq $8, %r15
jne .LBB1_11
# %bb.14:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matAddPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matAddPdS_,@object # @_Z6matAddPdS_
.section .rodata,"a",@progbits
.globl _Z6matAddPdS_
.p2align 3, 0x0
_Z6matAddPdS_:
.quad _Z21__device_stub__matAddPdS_
.size _Z6matAddPdS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " %4.1f"
.size .L.str, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6matAddPdS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matAddPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matAddPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <iomanip>
#include <ctime>
#include <cstdlib>
#include <cstdio>
#include <cmath>
#include "cuda_runtime.h"
using namespace std;
#define TPB 1024
#define min(a,b) ((a < b) ? a : b)
__global__
void scat_part_sum(double * array, double * array_psums) {
// Distributes the values from array_psums (array of partial sums) to every element
// in the array. Every thread in a block gets the same partial sum added to it
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
//__syncthreads();
array[tid] += array_psums[blockIdx.x];
//__syncthreads();
}
__global__
void upsweep (double * array, double * array_aggr1, int size) {
// Performs an upsweep
int bid = blockIdx.x * blockDim.x;
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
int min_size = min(size, TPB);
__syncthreads();
// Merge elements like a binary tree
for (int step = 2; step <= min_size ; step *= 2) {
if (tid % step == (step - 1) && (tid - (step / 2) >= bid)) {
array[tid] += array[tid - (step / 2)];
}
__syncthreads();
}
__syncthreads();
// Aggregates the sum of each block to another array for to calculate partial tums
if (array_aggr1 != NULL) {
if (threadIdx.x == (TPB - 1)) {
if (tid < size) {
array_aggr1[blockIdx.x] = array[tid];
}
else {
array_aggr1[blockIdx.x] = array[size - 1];
}
}
__syncthreads();
}
}
__global__
void excl_downsweep (double * array, int size) {
int bsize = blockIdx.x * blockDim.x;
int next_block = (blockIdx.x + 1) * blockDim.x;
int tid = bsize + threadIdx.x;
int tmp;
int min_size = min(size, TPB);
// Performs an exlusive down sweep. After the inclusive down sweep, each block
// will have elements 0, 0 + a_1 , 0 + a_1 + a_2, ... , 0 + a_1 + a_2 + ... + a_1023
if (tid % TPB == 0) { array[min(size, next_block) - 1] = 0; }
__syncthreads();
for (int step = min_size; step > 0; step /= 2) {
if (tid % step == (step - 1) && (tid - (step / 2) >= bsize)) {
tmp = array[tid];
array[tid] += array[tid - (step / 2)];
array[tid - (step / 2)] = tmp;
}
__syncthreads();
}
}
__global__
void incl_downsweep (double * array) {
int next_bid = (blockIdx.x + 1) * blockDim.x;
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
__syncthreads();
// Performs an inclusive down sweep. After the inclusive down sweep, each block
// will have elements a_1, a_1 + a_2, ... , a_1 + a_2 + ... + a_1024
for (int step = TPB / 2; step > 1; step /= 2) {
if (tid % step == (step - 1) && (tid + (step / 2) < next_bid)) {
array[tid + (step / 2)] += array[tid];
}
__syncthreads();
}
}
void sum(double* a, double* b, const int n) {
//Given an array a[0...n-1], you need to compute b[0...n-1],
//where b[i] = (i+1)*a[0] + i*a[1] + ... + 2*a[i-1] + a[i]
//Note that b is NOT initialized with 0, be careful!
//Write your CUDA code starting from here
//Add any functions (e.g., device function) you want within this file
int size = n;
int size_div1 = int(ceil(double(size) / double(TPB)));
int size_div2 = int(ceil(double(size_div1) / double(TPB)));
int nblocks = int(ceil(double(size) / double(TPB)));
int nblocks_div1 = int(ceil(double(nblocks) / double(TPB)));
int nblocks_div2 = int(ceil(double(nblocks_div1) / double(TPB)));
double *d_x, *d_x1, *d_x2;
cudaMalloc(&d_x, size * sizeof(double));
cudaMalloc(&d_x1, size_div1 * sizeof(double));
cudaMalloc(&d_x2, size_div2 * sizeof(double));
cudaMemcpy(d_x, a, size * sizeof(double), cudaMemcpyHostToDevice);
//cudaMemcpy(d_x1, x1, size_div1 * sizeof(double), cudaMemcpyHostToDevice);
//cudaMemcpy(d_x2, x2, size_div2 * sizeof(double), cudaMemcpyHostToDevice);
for (int pf_step = 1; pf_step < 3; pf_step++) {
// cout << "Up-Sweep\n" << endl;
upsweep <<<nblocks, TPB>>> (d_x, d_x1, size);
cudaDeviceSynchronize();
// cout << "Up-Sweep 2\n" << endl;
upsweep <<<nblocks_div1, TPB>>> (d_x1, d_x2, size_div1);
cudaDeviceSynchronize();
// cout << "Up-Sweep 3\n" << endl;
upsweep <<<nblocks_div1, TPB>>> (d_x2, NULL, size_div2);
cudaDeviceSynchronize();
// cout << "Down-Sweep 3\n" << endl;
excl_downsweep <<<nblocks_div2, TPB>>> (d_x2, size_div2);
cudaDeviceSynchronize();
// cout << "Down-Sweep 2\n" << endl;
excl_downsweep <<<nblocks_div1, TPB>>> (d_x1, size_div1);
cudaDeviceSynchronize();
// cout << "Down-Sweep\n" << endl;
incl_downsweep <<<nblocks, TPB>>> (d_x);
cudaDeviceSynchronize();
// cout << "Scatter Partial Sums 2\n" << endl;
scat_part_sum <<<nblocks_div1, TPB>>> (d_x1, d_x2);
cudaDeviceSynchronize();
// cout << "Scatter Partial Sums 1\n" << endl;
scat_part_sum <<<nblocks, TPB>>> (d_x, d_x1);
cudaDeviceSynchronize();
cudaMemcpy(b, d_x, size * sizeof(double), cudaMemcpyDeviceToHost);
}
}
int main(int argc, const char * argv[]) {
if (argc != 2) {
printf("The argument is wrong! Execute your program with only input file name!\n");
return 1;
}
int n = 1 << 24;
//Dummy code for creating a random input vectors
//Convenient for the text purpose
//Please comment out when you submit your code!!!!!!!!!
/* FILE *fpw = fopen(argv[1], "w");
if (fpw == NULL) {
printf("The file can not be created!\n");
return 1;
}
//int n = 1 << 24;
fprintf(fpw, "%d\n", n);
srand(time(NULL));
for (int i=0; i<n; i++)
fprintf(fpw, "%lg\n", ((double)(rand() % n))/100);
fclose(fpw);
printf("Finished writing\n");
*/
//Read input from input file specified by user
FILE* fpr = fopen(argv[1], "r");
if (fpr == NULL) {
printf("The file can not be opened or does not exist!\n");
return 1;
}
//int n;
fscanf(fpr, "%d\n", &n);
printf("%d\n", n);
double* a = (double*)malloc(n*sizeof(double));
double* b = (double*)malloc(n*sizeof(double));
for (int i=0; i<n; i++) {
fscanf(fpr, "%lg\n", &a[i]);
}
fclose(fpr);
//Main function
sum(a, b, n);
//Write b into output file
FILE* fpo = fopen("output.txt","w");
if (fpo == NULL) {
printf("The file can not be created!\n");
return 1;
}
fprintf(fpo, "%d\n", n);
for (int i=0; i<n; i++)
fprintf(fpo, "%lg\n", b[i]);
fclose(fpo);
free(a);
free(b);
printf("Done...\n");
return 0;
} | code for sm_80
Function : _Z14incl_downsweepPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0040*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0050*/ IMAD R0, R4.reuse, c[0x0][0x0], R3 ; /* 0x0000000004007a24 */
/* 0x041fe200078e0203 */
/*0060*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fc80007ffe0ff */
/*0070*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fe20000011400 */
/*0080*/ IMAD R4, R4, c[0x0][0x0], RZ ; /* 0x0000000004047a24 */
/* 0x000fe200078e02ff */
/*0090*/ IADD3 R7, R0, 0x100, RZ ; /* 0x0000010000077810 */
/* 0x000fe40007ffe0ff */
/*00a0*/ LEA.HI R2, R5, R0, RZ, 0x9 ; /* 0x0000000005027211 */
/* 0x000fe400078f48ff */
/*00b0*/ ISETP.GE.AND P1, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fe40003f26270 */
/*00c0*/ LOP3.LUT R3, R2, 0xfffffe00, RZ, 0xc0, !PT ; /* 0xfffffe0002037812 */
/* 0x000fca00078ec0ff */
/*00d0*/ IMAD.IADD R3, R0, 0x1, -R3 ; /* 0x0000000100037824 */
/* 0x000fca00078e0a03 */
/*00e0*/ ISETP.NE.OR P1, PT, R3, 0x1ff, P1 ; /* 0x000001ff0300780c */
/* 0x000fe20000f25670 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fd000078e0203 */
/*0110*/ @!P1 LDG.E.64 R6, [R2.64] ; /* 0x0000000402069981 */
/* 0x000ea8000c1e1b00 */
/*0120*/ @!P1 LDG.E.64 R8, [R2.64+0x800] ; /* 0x0008000402089981 */
/* 0x000ea2000c1e1b00 */
/*0130*/ LEA.HI R10, R5, R0, RZ, 0x8 ; /* 0x00000000050a7211 */
/* 0x000fe400078f40ff */
/*0140*/ IADD3 R13, R0, 0x80, RZ ; /* 0x00000080000d7810 */
/* 0x000fe40007ffe0ff */
/*0150*/ LOP3.LUT R11, R10, 0xffffff00, RZ, 0xc0, !PT ; /* 0xffffff000a0b7812 */
/* 0x000fe400078ec0ff */
/*0160*/ ISETP.GE.AND P0, PT, R13, R4, PT ; /* 0x000000040d00720c */
/* 0x000fc60003f06270 */
/*0170*/ IMAD.IADD R11, R0, 0x1, -R11 ; /* 0x00000001000b7824 */
/* 0x000fca00078e0a0b */
/*0180*/ ISETP.NE.OR P0, PT, R11, 0xff, P0 ; /* 0x000000ff0b00780c */
/* 0x000fe20000705670 */
/*0190*/ @!P1 DADD R6, R6, R8 ; /* 0x0000000006069229 */
/* 0x004e0e0000000008 */
/*01a0*/ @!P1 STG.E.64 [R2.64+0x800], R6 ; /* 0x0008000602009986 */
/* 0x0011e8000c101b04 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01c0*/ @!P0 LDG.E.64 R8, [R2.64] ; /* 0x0000000402088981 */
/* 0x000ea8000c1e1b00 */
/*01d0*/ @!P0 LDG.E.64 R10, [R2.64+0x400] ; /* 0x00040004020a8981 */
/* 0x000ea2000c1e1b00 */
/*01e0*/ LEA.HI R12, R5, R0, RZ, 0x7 ; /* 0x00000000050c7211 */
/* 0x000fc400078f38ff */
/*01f0*/ IADD3 R15, R0, 0x40, RZ ; /* 0x00000040000f7810 */
/* 0x000fe40007ffe0ff */
/*0200*/ LOP3.LUT R13, R12, 0xffffff80, RZ, 0xc0, !PT ; /* 0xffffff800c0d7812 */
/* 0x000fe400078ec0ff */
/*0210*/ ISETP.GE.AND P1, PT, R15, R4, PT ; /* 0x000000040f00720c */
/* 0x000fc60003f26270 */
/*0220*/ IMAD.IADD R13, R0, 0x1, -R13 ; /* 0x00000001000d7824 */
/* 0x000fca00078e0a0d */
/*0230*/ ISETP.NE.OR P1, PT, R13, 0x7f, P1 ; /* 0x0000007f0d00780c */
/* 0x000fe20000f25670 */
/*0240*/ @!P0 DADD R8, R8, R10 ; /* 0x0000000008088229 */
/* 0x004e4e000000000a */
/*0250*/ @!P0 STG.E.64 [R2.64+0x400], R8 ; /* 0x0004000802008986 */
/* 0x0023e8000c101b04 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0270*/ @!P1 LDG.E.64 R6, [R2.64] ; /* 0x0000000402069981 */
/* 0x001ea8000c1e1b00 */
/*0280*/ @!P1 LDG.E.64 R10, [R2.64+0x200] ; /* 0x00020004020a9981 */
/* 0x000ea2000c1e1b00 */
/*0290*/ LEA.HI R12, R5, R0, RZ, 0x6 ; /* 0x00000000050c7211 */
/* 0x000fc400078f30ff */
/*02a0*/ IADD3 R15, R0, 0x20, RZ ; /* 0x00000020000f7810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ LOP3.LUT R13, R12, 0xffffffc0, RZ, 0xc0, !PT ; /* 0xffffffc00c0d7812 */
/* 0x000fe400078ec0ff */
/*02c0*/ ISETP.GE.AND P0, PT, R15, R4, PT ; /* 0x000000040f00720c */
/* 0x000fc60003f06270 */
/*02d0*/ IMAD.IADD R13, R0, 0x1, -R13 ; /* 0x00000001000d7824 */
/* 0x000fca00078e0a0d */
/*02e0*/ ISETP.NE.OR P0, PT, R13, 0x3f, P0 ; /* 0x0000003f0d00780c */
/* 0x000fe20000705670 */
/*02f0*/ @!P1 DADD R6, R6, R10 ; /* 0x0000000006069229 */
/* 0x004e0e000000000a */
/*0300*/ @!P1 STG.E.64 [R2.64+0x200], R6 ; /* 0x0002000602009986 */
/* 0x0011e8000c101b04 */
/*0310*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0320*/ @!P0 LDG.E.64 R8, [R2.64] ; /* 0x0000000402088981 */
/* 0x002ea8000c1e1b00 */
/*0330*/ @!P0 LDG.E.64 R10, [R2.64+0x100] ; /* 0x00010004020a8981 */
/* 0x000ea2000c1e1b00 */
/*0340*/ LEA.HI R12, R5, R0, RZ, 0x5 ; /* 0x00000000050c7211 */
/* 0x000fc400078f28ff */
/*0350*/ IADD3 R15, R0, 0x10, RZ ; /* 0x00000010000f7810 */
/* 0x000fe40007ffe0ff */
/*0360*/ LOP3.LUT R13, R12, 0xffffffe0, RZ, 0xc0, !PT ; /* 0xffffffe00c0d7812 */
/* 0x000fe400078ec0ff */
/*0370*/ ISETP.GE.AND P1, PT, R15, R4, PT ; /* 0x000000040f00720c */
/* 0x000fc60003f26270 */
/*0380*/ IMAD.IADD R13, R0, 0x1, -R13 ; /* 0x00000001000d7824 */
/* 0x000fca00078e0a0d */
/*0390*/ ISETP.NE.OR P1, PT, R13, 0x1f, P1 ; /* 0x0000001f0d00780c */
/* 0x000fe20000f25670 */
/*03a0*/ @!P0 DADD R8, R8, R10 ; /* 0x0000000008088229 */
/* 0x004e4e000000000a */
/*03b0*/ @!P0 STG.E.64 [R2.64+0x100], R8 ; /* 0x0001000802008986 */
/* 0x0023e8000c101b04 */
/*03c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03d0*/ @!P1 LDG.E.64 R6, [R2.64] ; /* 0x0000000402069981 */
/* 0x001ea8000c1e1b00 */
/*03e0*/ @!P1 LDG.E.64 R10, [R2.64+0x80] ; /* 0x00008004020a9981 */
/* 0x000ea2000c1e1b00 */
/*03f0*/ LEA.HI R12, R5, R0, RZ, 0x4 ; /* 0x00000000050c7211 */
/* 0x000fc400078f20ff */
/*0400*/ IADD3 R15, R0, 0x8, RZ ; /* 0x00000008000f7810 */
/* 0x000fe40007ffe0ff */
/*0410*/ LOP3.LUT R13, R12, 0xfffffff0, RZ, 0xc0, !PT ; /* 0xfffffff00c0d7812 */
/* 0x000fe400078ec0ff */
/*0420*/ ISETP.GE.AND P0, PT, R15, R4, PT ; /* 0x000000040f00720c */
/* 0x000fc60003f06270 */
/*0430*/ IMAD.IADD R13, R0, 0x1, -R13 ; /* 0x00000001000d7824 */
/* 0x000fca00078e0a0d */
/*0440*/ ISETP.NE.OR P0, PT, R13, 0xf, P0 ; /* 0x0000000f0d00780c */
/* 0x000fe20000705670 */
/*0450*/ @!P1 DADD R6, R6, R10 ; /* 0x0000000006069229 */
/* 0x004e0e000000000a */
/*0460*/ @!P1 STG.E.64 [R2.64+0x80], R6 ; /* 0x0000800602009986 */
/* 0x0011e8000c101b04 */
/*0470*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0480*/ @!P0 LDG.E.64 R8, [R2.64] ; /* 0x0000000402088981 */
/* 0x002ea8000c1e1b00 */
/*0490*/ @!P0 LDG.E.64 R10, [R2.64+0x40] ; /* 0x00004004020a8981 */
/* 0x000ea2000c1e1b00 */
/*04a0*/ LEA.HI R12, R5, R0, RZ, 0x3 ; /* 0x00000000050c7211 */
/* 0x000fc400078f18ff */
/*04b0*/ IADD3 R15, R0, 0x4, RZ ; /* 0x00000004000f7810 */
/* 0x000fe40007ffe0ff */
/*04c0*/ LOP3.LUT R13, R12, 0xfffffff8, RZ, 0xc0, !PT ; /* 0xfffffff80c0d7812 */
/* 0x000fe400078ec0ff */
/*04d0*/ ISETP.GE.AND P1, PT, R15, R4, PT ; /* 0x000000040f00720c */
/* 0x000fc60003f26270 */
/*04e0*/ IMAD.IADD R13, R0, 0x1, -R13 ; /* 0x00000001000d7824 */
/* 0x000fca00078e0a0d */
/*04f0*/ ISETP.NE.OR P1, PT, R13, 0x7, P1 ; /* 0x000000070d00780c */
/* 0x000fe20000f25670 */
/*0500*/ @!P0 DADD R8, R8, R10 ; /* 0x0000000008088229 */
/* 0x004e4e000000000a */
/*0510*/ @!P0 STG.E.64 [R2.64+0x40], R8 ; /* 0x0000400802008986 */
/* 0x0023e8000c101b04 */
/*0520*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0530*/ @!P1 LDG.E.64 R6, [R2.64] ; /* 0x0000000402069981 */
/* 0x001ea8000c1e1b00 */
/*0540*/ @!P1 LDG.E.64 R10, [R2.64+0x20] ; /* 0x00002004020a9981 */
/* 0x000ea2000c1e1b00 */
/*0550*/ LEA.HI R5, R5, R0, RZ, 0x2 ; /* 0x0000000005057211 */
/* 0x000fc400078f10ff */
/*0560*/ IADD3 R13, R0, 0x2, RZ ; /* 0x00000002000d7810 */
/* 0x000fe40007ffe0ff */
/*0570*/ LOP3.LUT R5, R5, 0xfffffffc, RZ, 0xc0, !PT ; /* 0xfffffffc05057812 */
/* 0x000fe400078ec0ff */
/*0580*/ ISETP.GE.AND P0, PT, R13, R4, PT ; /* 0x000000040d00720c */
/* 0x000fc60003f06270 */
/*0590*/ IMAD.IADD R5, R0, 0x1, -R5 ; /* 0x0000000100057824 */
/* 0x000fca00078e0a05 */
/*05a0*/ ISETP.NE.OR P0, PT, R5, 0x3, P0 ; /* 0x000000030500780c */
/* 0x000fe20000705670 */
/*05b0*/ @!P1 DADD R6, R6, R10 ; /* 0x0000000006069229 */
/* 0x004e0e000000000a */
/*05c0*/ @!P1 STG.E.64 [R2.64+0x20], R6 ; /* 0x0000200602009986 */
/* 0x0011e8000c101b04 */
/*05d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05e0*/ @!P0 LDG.E.64 R8, [R2.64] ; /* 0x0000000402088981 */
/* 0x002ea8000c1e1b00 */
/*05f0*/ @!P0 LDG.E.64 R10, [R2.64+0x10] ; /* 0x00001004020a8981 */
/* 0x000ea2000c1e1b00 */
/*0600*/ LEA.HI R5, R0.reuse, R0, RZ, 0x1 ; /* 0x0000000000057211 */
/* 0x040fe200078f08ff */
/*0610*/ BSSY B0, 0x700 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0620*/ IADD3 R13, R0, 0x1, RZ ; /* 0x00000001000d7810 */
/* 0x000fc40007ffe0ff */
/*0630*/ LOP3.LUT R5, R5, 0xfffffffe, RZ, 0xc0, !PT ; /* 0xfffffffe05057812 */
/* 0x000fe400078ec0ff */
/*0640*/ ISETP.GE.AND P1, PT, R13, R4, PT ; /* 0x000000040d00720c */
/* 0x000fc60003f26270 */
/*0650*/ IMAD.IADD R5, R0, 0x1, -R5 ; /* 0x0000000100057824 */
/* 0x000fca00078e0a05 */
/*0660*/ ISETP.NE.OR P1, PT, R5, 0x1, P1 ; /* 0x000000010500780c */
/* 0x000fe20000f25670 */
/*0670*/ @!P0 DADD R8, R8, R10 ; /* 0x0000000008088229 */
/* 0x004e4e000000000a */
/*0680*/ @!P0 STG.E.64 [R2.64+0x10], R8 ; /* 0x0000100802008986 */
/* 0x0021e8000c101b04 */
/*0690*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06a0*/ @P1 BRA 0x6f0 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*06b0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1b00 */
/*06c0*/ LDG.E.64 R6, [R2.64+0x8] ; /* 0x0000080402067981 */
/* 0x001ea4000c1e1b00 */
/*06d0*/ DADD R4, R4, R6 ; /* 0x0000000004047229 */
/* 0x004e0e0000000006 */
/*06e0*/ STG.E.64 [R2.64+0x8], R4 ; /* 0x0000080402007986 */
/* 0x0011e8000c101b04 */
/*06f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0700*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0710*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0720*/ BRA 0x720; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z14excl_downsweepPdi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff057624 */
/* 0x000fe400078e00ff */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e660000002100 */
/*0050*/ ISETP.GE.AND P1, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe20003f26270 */
/*0060*/ IMAD R4, R4, c[0x0][0x0], RZ ; /* 0x0000000004047a24 */
/* 0x001fc800078e02ff */
/*0070*/ IMAD.IADD R0, R4, 0x1, R3 ; /* 0x0000000104007824 */
/* 0x002fca00078e0203 */
/*0080*/ LOP3.LUT P0, RZ, R0, 0x3ff, RZ, 0xc0, !PT ; /* 0x000003ff00ff7812 */
/* 0x000fda000780c0ff */
/*0090*/ @!P0 IADD3 R2, R4, c[0x0][0x0], RZ ; /* 0x0000000004028a10 */
/* 0x000fe20007ffe0ff */
/*00a0*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff038424 */
/* 0x000fc600078e00ff */
/*00b0*/ @!P0 IMNMX R2, R2, c[0x0][0x168], PT ; /* 0x00005a0002028a17 */
/* 0x000fc80003800200 */
/*00c0*/ @!P0 IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02028810 */
/* 0x000fca0007ffe0ff */
/*00d0*/ @!P0 IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002028625 */
/* 0x000fca00078e0203 */
/*00e0*/ @!P0 STG.E.64 [R2.64], RZ ; /* 0x000000ff02008986 */
/* 0x0001e8000c101b04 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0100*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0110*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x001fe200078e00ff */
/*0120*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fc40000000000 */
/*0130*/ IMNMX R5, R5, 0x400, PT ; /* 0x0000040005057817 */
/* 0x000fe20003800200 */
/*0140*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0203 */
/*0150*/ IABS R10, R5.reuse ; /* 0x00000005000a7213 */
/* 0x082fe20000000000 */
/*0160*/ BSSY B0, 0x3d0 ; /* 0x0000026000007945 */
/* 0x000fe20003800000 */
/*0170*/ IABS R12, R5 ; /* 0x00000005000c7213 */
/* 0x000fe40000000000 */
/*0180*/ I2F.RP R7, R10 ; /* 0x0000000a00077306 */
/* 0x000e220000209400 */
/*0190*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f46270 */
/*01a0*/ IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0c7224 */
/* 0x000fca00078e0a0c */
/*01b0*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e240000001000 */
/*01c0*/ IADD3 R8, R7, 0xffffffe, RZ ; /* 0x0ffffffe07087810 */
/* 0x001fe40007ffe0ff */
/*01d0*/ IABS R7, R0 ; /* 0x0000000000077213 */
/* 0x000fc80000000000 */
/*01e0*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000064000021f000 */
/*01f0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fe400078e00ff */
/*0200*/ IMAD.MOV R11, RZ, RZ, -R9 ; /* 0x000000ffff0b7224 */
/* 0x002fc800078e0a09 */
/*0210*/ IMAD R11, R11, R10, RZ ; /* 0x0000000a0b0b7224 */
/* 0x000fc800078e02ff */
/*0220*/ IMAD.HI.U32 R9, R9, R11, R8 ; /* 0x0000000b09097227 */
/* 0x000fe200078e0008 */
/*0230*/ IADD3 R8, R5, -0x1, RZ ; /* 0xffffffff05087810 */
/* 0x000fca0007ffe0ff */
/*0240*/ IMAD.HI.U32 R9, R9, R6, RZ ; /* 0x0000000609097227 */
/* 0x000fc800078e00ff */
/*0250*/ IMAD R9, R9, R12, R7 ; /* 0x0000000c09097224 */
/* 0x000fca00078e0207 */
/*0260*/ ISETP.GT.U32.AND P0, PT, R10, R9, PT ; /* 0x000000090a00720c */
/* 0x000fda0003f04070 */
/*0270*/ @!P0 IMAD.IADD R9, R9, 0x1, -R10 ; /* 0x0000000109098824 */
/* 0x000fe200078e0a0a */
/*0280*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc80003f05270 */
/*0290*/ ISETP.GT.U32.AND P1, PT, R10, R9, PT ; /* 0x000000090a00720c */
/* 0x000fda0003f24070 */
/*02a0*/ @!P1 IMAD.IADD R9, R9, 0x1, -R10 ; /* 0x0000000109099824 */
/* 0x000fc800078e0a0a */
/*02b0*/ @!P2 IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff09a224 */
/* 0x000fe200078e0a09 */
/*02c0*/ @!P0 LOP3.LUT R9, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff098212 */
/* 0x000fc800078e33ff */
/*02d0*/ ISETP.NE.AND P0, PT, R9, R8, PT ; /* 0x000000080900720c */
/* 0x000fda0003f05270 */
/*02e0*/ @P0 BRA 0x3c0 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*02f0*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fca0000011605 */
/*0300*/ IMAD.IADD R7, R0, 0x1, -R7 ; /* 0x0000000100077824 */
/* 0x000fca00078e0a07 */
/*0310*/ ISETP.GE.AND P0, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fda0003f06270 */
/*0320*/ @!P0 BRA 0x3c0 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*0330*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1b00 */
/*0340*/ IMAD.MOV.U32 R10, RZ, RZ, 0x8 ; /* 0x00000008ff0a7424 */
/* 0x000fc800078e00ff */
/*0350*/ IMAD.WIDE R10, R7, R10, c[0x0][0x160] ; /* 0x00005800070a7625 */
/* 0x000fca00078e020a */
/*0360*/ LDG.E.64 R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ee2000c1e1b00 */
/*0370*/ F2I.F64.TRUNC R14, R8 ; /* 0x00000008000e7311 */
/* 0x004e22000030d100 */
/*0380*/ DADD R12, R8, R12 ; /* 0x00000000080c7229 */
/* 0x008e4e000000000c */
/*0390*/ I2F.F64 R14, R14 ; /* 0x0000000e000e7312 */
/* 0x001e220000201c00 */
/*03a0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0023e8000c101b04 */
/*03b0*/ STG.E.64 [R10.64], R14 ; /* 0x0000000e0a007986 */
/* 0x0013e4000c101b04 */
/*03c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03d0*/ SHF.R.U32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff057819 */
/* 0x000fe20000011605 */
/*03e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*03f0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0400*/ @P0 BRA 0x150 ; /* 0xfffffd4000000947 */
/* 0x000fea000383ffff */
/*0410*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0420*/ BRA 0x420; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7upsweepPdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e640000002100 */
/*0060*/ IMNMX R5, R5, 0x400, PT ; /* 0x0000040005057817 */
/* 0x000fe40003800200 */
/*0070*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe40000010000 */
/*0080*/ ISETP.GE.AND P0, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x000fe20003f06270 */
/*0090*/ IMAD R7, R0, c[0x0][0x0], RZ ; /* 0x0000000000077a24 */
/* 0x001fc800078e02ff */
/*00a0*/ IMAD.IADD R6, R7, 0x1, R4 ; /* 0x0000000107067824 */
/* 0x002fc800078e0204 */
/*00b0*/ IMAD.WIDE R2, R6, R3, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0203 */
/*00c0*/ @!P0 BRA 0x390 ; /* 0x000002c000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IABS R9, R6 ; /* 0x0000000600097213 */
/* 0x000fe20000000000 */
/*00e0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x2 ; /* 0x00000002ff087424 */
/* 0x000fca00078e00ff */
/*00f0*/ IABS R13, R8.reuse ; /* 0x00000008000d7213 */
/* 0x081fe20000000000 */
/*0100*/ BSSY B0, 0x350 ; /* 0x0000024000007945 */
/* 0x000fe20003800000 */
/*0110*/ IABS R16, R8 ; /* 0x0000000800107213 */
/* 0x000fe40000000000 */
/*0120*/ I2F.RP R12, R13 ; /* 0x0000000d000c7306 */
/* 0x000e220000209400 */
/*0130*/ ISETP.GE.AND P2, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fce0003f46270 */
/*0140*/ MUFU.RCP R12, R12 ; /* 0x0000000c000c7308 */
/* 0x001e240000001000 */
/*0150*/ IADD3 R10, R12, 0xffffffe, RZ ; /* 0x0ffffffe0c0a7810 */
/* 0x001fe40007ffe0ff */
/*0160*/ IABS R12, R6 ; /* 0x00000006000c7213 */
/* 0x000fc80000000000 */
/*0170*/ F2I.FTZ.U32.TRUNC.NTZ R11, R10 ; /* 0x0000000a000b7305 */
/* 0x000064000021f000 */
/*0180*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e00ff */
/*0190*/ IMAD.MOV R14, RZ, RZ, -R11 ; /* 0x000000ffff0e7224 */
/* 0x002fc800078e0a0b */
/*01a0*/ IMAD R15, R14, R13, RZ ; /* 0x0000000d0e0f7224 */
/* 0x000fc800078e02ff */
/*01b0*/ IMAD.HI.U32 R14, R11, R15, R10 ; /* 0x0000000f0b0e7227 */
/* 0x000fc800078e000a */
/*01c0*/ IMAD.MOV R11, RZ, RZ, -R16 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0a10 */
/*01d0*/ IMAD.HI.U32 R14, R14, R9, RZ ; /* 0x000000090e0e7227 */
/* 0x000fc800078e00ff */
/*01e0*/ IMAD R14, R14, R11, R12 ; /* 0x0000000b0e0e7224 */
/* 0x000fe200078e020c */
/*01f0*/ IADD3 R11, R8, -0x1, RZ ; /* 0xffffffff080b7810 */
/* 0x000fc80007ffe0ff */
/*0200*/ ISETP.GT.U32.AND P0, PT, R13, R14, PT ; /* 0x0000000e0d00720c */
/* 0x000fda0003f04070 */
/*0210*/ @!P0 IADD3 R14, R14, -R13, RZ ; /* 0x8000000d0e0e8210 */
/* 0x000fe40007ffe0ff */
/*0220*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*0230*/ ISETP.GT.U32.AND P1, PT, R13, R14, PT ; /* 0x0000000e0d00720c */
/* 0x000fda0003f24070 */
/*0240*/ @!P1 IMAD.IADD R14, R14, 0x1, -R13 ; /* 0x000000010e0e9824 */
/* 0x000fc800078e0a0d */
/*0250*/ @!P2 IMAD.MOV R14, RZ, RZ, -R14 ; /* 0x000000ffff0ea224 */
/* 0x000fe200078e0a0e */
/*0260*/ @!P0 LOP3.LUT R14, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff0e8212 */
/* 0x000fc800078e33ff */
/*0270*/ ISETP.NE.AND P0, PT, R14, R11, PT ; /* 0x0000000b0e00720c */
/* 0x000fda0003f05270 */
/*0280*/ @P0 BRA 0x340 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0290*/ LEA.HI R10, R8, R8, RZ, 0x1 ; /* 0x00000008080a7211 */
/* 0x000fc800078f08ff */
/*02a0*/ SHF.R.S32.HI R11, RZ, 0x1, R10 ; /* 0x00000001ff0b7819 */
/* 0x000fca000001140a */
/*02b0*/ IMAD.IADD R10, R6, 0x1, -R11 ; /* 0x00000001060a7824 */
/* 0x000fca00078e0a0b */
/*02c0*/ ISETP.GE.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fda0003f06270 */
/*02d0*/ @!P0 BRA 0x340 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*02e0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b7424 */
/* 0x000fe200078e00ff */
/*02f0*/ LDG.E.64 R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x000ea6000c1e1b00 */
/*0300*/ IMAD.WIDE R10, R10, R11, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fcc00078e020b */
/*0310*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea4000c1e1b00 */
/*0320*/ DADD R12, R12, R10 ; /* 0x000000000c0c7229 */
/* 0x004e0e000000000a */
/*0330*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0340*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0350*/ SHF.L.U32 R8, R8, 0x1, RZ ; /* 0x0000000108087819 */
/* 0x000fe200000006ff */
/*0360*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0370*/ ISETP.GT.AND P0, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f04270 */
/*0380*/ @!P0 BRA 0xf0 ; /* 0xfffffd6000008947 */
/* 0x000fea000383ffff */
/*0390*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03a0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fc80003f05070 */
/*03b0*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x16c], PT, P0 ; /* 0x00005b00ff007a0c */
/* 0x000fda0003f05300 */
/*03c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*03d0*/ ISETP.NE.AND P0, PT, R4, 0x3ff, PT ; /* 0x000003ff0400780c */
/* 0x000fe20003f05270 */
/*03e0*/ BSSY B0, 0x4b0 ; /* 0x000000c000007945 */
/* 0x000fd80003800000 */
/*03f0*/ @P0 BRA 0x4a0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0400*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fe20003f06270 */
/*0410*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fd800078e00ff */
/*0420*/ @P0 IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff060624 */
/* 0x000fca00078e00ff */
/*0430*/ @P0 IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06060810 */
/* 0x000fca0007ffe0ff */
/*0440*/ @P0 IMAD.WIDE R6, R6, R5, c[0x0][0x160] ; /* 0x0000580006060625 */
/* 0x000fcc00078e0205 */
/*0450*/ @P0 LDG.E.64 R6, [R6.64] ; /* 0x0000000406060981 */
/* 0x000ea2000c1e1b00 */
/*0460*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0005 */
/*0470*/ @P0 STG.E.64 [R4.64], R6 ; /* 0x0000000604000986 */
/* 0x0043e8000c101b04 */
/*0480*/ @!P0 LDG.E.64 R2, [R2.64] ; /* 0x0000000402028981 */
/* 0x001ea8000c1e1b00 */
/*0490*/ @!P0 STG.E.64 [R4.64], R2 ; /* 0x0000000204008986 */
/* 0x0043e4000c101b04 */
/*04a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04d0*/ BRA 0x4d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13scat_part_sumPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R2, c[0x0][0x0], R3 ; /* 0x0000000002047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0005 */
/*0070*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0205 */
/*0080*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0090*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1b00 */
/*00a0*/ DADD R6, R2, R6 ; /* 0x0000000002067229 */
/* 0x004e0e0000000006 */
/*00b0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x001fe2000c101b04 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <iomanip>
#include <ctime>
#include <cstdlib>
#include <cstdio>
#include <cmath>
#include "cuda_runtime.h"
using namespace std;
#define TPB 1024
#define min(a,b) ((a < b) ? a : b)
__global__
void scat_part_sum(double * array, double * array_psums) {
// Distributes the values from array_psums (array of partial sums) to every element
// in the array. Every thread in a block gets the same partial sum added to it
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
//__syncthreads();
array[tid] += array_psums[blockIdx.x];
//__syncthreads();
}
__global__
void upsweep (double * array, double * array_aggr1, int size) {
// Performs an upsweep
int bid = blockIdx.x * blockDim.x;
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
int min_size = min(size, TPB);
__syncthreads();
// Merge elements like a binary tree
for (int step = 2; step <= min_size ; step *= 2) {
if (tid % step == (step - 1) && (tid - (step / 2) >= bid)) {
array[tid] += array[tid - (step / 2)];
}
__syncthreads();
}
__syncthreads();
// Aggregates the sum of each block to another array for to calculate partial tums
if (array_aggr1 != NULL) {
if (threadIdx.x == (TPB - 1)) {
if (tid < size) {
array_aggr1[blockIdx.x] = array[tid];
}
else {
array_aggr1[blockIdx.x] = array[size - 1];
}
}
__syncthreads();
}
}
__global__
void excl_downsweep (double * array, int size) {
int bsize = blockIdx.x * blockDim.x;
int next_block = (blockIdx.x + 1) * blockDim.x;
int tid = bsize + threadIdx.x;
int tmp;
int min_size = min(size, TPB);
// Performs an exlusive down sweep. After the inclusive down sweep, each block
// will have elements 0, 0 + a_1 , 0 + a_1 + a_2, ... , 0 + a_1 + a_2 + ... + a_1023
if (tid % TPB == 0) { array[min(size, next_block) - 1] = 0; }
__syncthreads();
for (int step = min_size; step > 0; step /= 2) {
if (tid % step == (step - 1) && (tid - (step / 2) >= bsize)) {
tmp = array[tid];
array[tid] += array[tid - (step / 2)];
array[tid - (step / 2)] = tmp;
}
__syncthreads();
}
}
__global__
void incl_downsweep (double * array) {
int next_bid = (blockIdx.x + 1) * blockDim.x;
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
__syncthreads();
// Performs an inclusive down sweep. After the inclusive down sweep, each block
// will have elements a_1, a_1 + a_2, ... , a_1 + a_2 + ... + a_1024
for (int step = TPB / 2; step > 1; step /= 2) {
if (tid % step == (step - 1) && (tid + (step / 2) < next_bid)) {
array[tid + (step / 2)] += array[tid];
}
__syncthreads();
}
}
void sum(double* a, double* b, const int n) {
//Given an array a[0...n-1], you need to compute b[0...n-1],
//where b[i] = (i+1)*a[0] + i*a[1] + ... + 2*a[i-1] + a[i]
//Note that b is NOT initialized with 0, be careful!
//Write your CUDA code starting from here
//Add any functions (e.g., device function) you want within this file
int size = n;
int size_div1 = int(ceil(double(size) / double(TPB)));
int size_div2 = int(ceil(double(size_div1) / double(TPB)));
int nblocks = int(ceil(double(size) / double(TPB)));
int nblocks_div1 = int(ceil(double(nblocks) / double(TPB)));
int nblocks_div2 = int(ceil(double(nblocks_div1) / double(TPB)));
double *d_x, *d_x1, *d_x2;
cudaMalloc(&d_x, size * sizeof(double));
cudaMalloc(&d_x1, size_div1 * sizeof(double));
cudaMalloc(&d_x2, size_div2 * sizeof(double));
cudaMemcpy(d_x, a, size * sizeof(double), cudaMemcpyHostToDevice);
//cudaMemcpy(d_x1, x1, size_div1 * sizeof(double), cudaMemcpyHostToDevice);
//cudaMemcpy(d_x2, x2, size_div2 * sizeof(double), cudaMemcpyHostToDevice);
for (int pf_step = 1; pf_step < 3; pf_step++) {
// cout << "Up-Sweep\n" << endl;
upsweep <<<nblocks, TPB>>> (d_x, d_x1, size);
cudaDeviceSynchronize();
// cout << "Up-Sweep 2\n" << endl;
upsweep <<<nblocks_div1, TPB>>> (d_x1, d_x2, size_div1);
cudaDeviceSynchronize();
// cout << "Up-Sweep 3\n" << endl;
upsweep <<<nblocks_div1, TPB>>> (d_x2, NULL, size_div2);
cudaDeviceSynchronize();
// cout << "Down-Sweep 3\n" << endl;
excl_downsweep <<<nblocks_div2, TPB>>> (d_x2, size_div2);
cudaDeviceSynchronize();
// cout << "Down-Sweep 2\n" << endl;
excl_downsweep <<<nblocks_div1, TPB>>> (d_x1, size_div1);
cudaDeviceSynchronize();
// cout << "Down-Sweep\n" << endl;
incl_downsweep <<<nblocks, TPB>>> (d_x);
cudaDeviceSynchronize();
// cout << "Scatter Partial Sums 2\n" << endl;
scat_part_sum <<<nblocks_div1, TPB>>> (d_x1, d_x2);
cudaDeviceSynchronize();
// cout << "Scatter Partial Sums 1\n" << endl;
scat_part_sum <<<nblocks, TPB>>> (d_x, d_x1);
cudaDeviceSynchronize();
cudaMemcpy(b, d_x, size * sizeof(double), cudaMemcpyDeviceToHost);
}
}
int main(int argc, const char * argv[]) {
if (argc != 2) {
printf("The argument is wrong! Execute your program with only input file name!\n");
return 1;
}
int n = 1 << 24;
//Dummy code for creating a random input vectors
//Convenient for the text purpose
//Please comment out when you submit your code!!!!!!!!!
/* FILE *fpw = fopen(argv[1], "w");
if (fpw == NULL) {
printf("The file can not be created!\n");
return 1;
}
//int n = 1 << 24;
fprintf(fpw, "%d\n", n);
srand(time(NULL));
for (int i=0; i<n; i++)
fprintf(fpw, "%lg\n", ((double)(rand() % n))/100);
fclose(fpw);
printf("Finished writing\n");
*/
//Read input from input file specified by user
FILE* fpr = fopen(argv[1], "r");
if (fpr == NULL) {
printf("The file can not be opened or does not exist!\n");
return 1;
}
//int n;
fscanf(fpr, "%d\n", &n);
printf("%d\n", n);
double* a = (double*)malloc(n*sizeof(double));
double* b = (double*)malloc(n*sizeof(double));
for (int i=0; i<n; i++) {
fscanf(fpr, "%lg\n", &a[i]);
}
fclose(fpr);
//Main function
sum(a, b, n);
//Write b into output file
FILE* fpo = fopen("output.txt","w");
if (fpo == NULL) {
printf("The file can not be created!\n");
return 1;
}
fprintf(fpo, "%d\n", n);
for (int i=0; i<n; i++)
fprintf(fpo, "%lg\n", b[i]);
fclose(fpo);
free(a);
free(b);
printf("Done...\n");
return 0;
} | .file "tmpxft_00053efb_00000000-6_prefix_sum.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3953:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3953:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z13scat_part_sumPdS_PdS_
.type _Z35__device_stub__Z13scat_part_sumPdS_PdS_, @function
_Z35__device_stub__Z13scat_part_sumPdS_PdS_:
.LFB3975:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13scat_part_sumPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3975:
.size _Z35__device_stub__Z13scat_part_sumPdS_PdS_, .-_Z35__device_stub__Z13scat_part_sumPdS_PdS_
.globl _Z13scat_part_sumPdS_
.type _Z13scat_part_sumPdS_, @function
_Z13scat_part_sumPdS_:
.LFB3976:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13scat_part_sumPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3976:
.size _Z13scat_part_sumPdS_, .-_Z13scat_part_sumPdS_
.globl _Z29__device_stub__Z7upsweepPdS_iPdS_i
.type _Z29__device_stub__Z7upsweepPdS_iPdS_i, @function
_Z29__device_stub__Z7upsweepPdS_iPdS_i:
.LFB3977:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7upsweepPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3977:
.size _Z29__device_stub__Z7upsweepPdS_iPdS_i, .-_Z29__device_stub__Z7upsweepPdS_iPdS_i
.globl _Z7upsweepPdS_i
.type _Z7upsweepPdS_i, @function
_Z7upsweepPdS_i:
.LFB3978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7upsweepPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3978:
.size _Z7upsweepPdS_i, .-_Z7upsweepPdS_i
.globl _Z35__device_stub__Z14excl_downsweepPdiPdi
.type _Z35__device_stub__Z14excl_downsweepPdiPdi, @function
_Z35__device_stub__Z14excl_downsweepPdiPdi:
.LFB3979:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14excl_downsweepPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3979:
.size _Z35__device_stub__Z14excl_downsweepPdiPdi, .-_Z35__device_stub__Z14excl_downsweepPdiPdi
.globl _Z14excl_downsweepPdi
.type _Z14excl_downsweepPdi, @function
_Z14excl_downsweepPdi:
.LFB3980:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z14excl_downsweepPdiPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3980:
.size _Z14excl_downsweepPdi, .-_Z14excl_downsweepPdi
.globl _Z34__device_stub__Z14incl_downsweepPdPd
.type _Z34__device_stub__Z14incl_downsweepPdPd, @function
_Z34__device_stub__Z14incl_downsweepPdPd:
.LFB3981:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14incl_downsweepPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3981:
.size _Z34__device_stub__Z14incl_downsweepPdPd, .-_Z34__device_stub__Z14incl_downsweepPdPd
.globl _Z14incl_downsweepPd
.type _Z14incl_downsweepPd, @function
_Z14incl_downsweepPd:
.LFB3982:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z14incl_downsweepPdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3982:
.size _Z14incl_downsweepPd, .-_Z14incl_downsweepPd
.globl _Z3sumPdS_i
.type _Z3sumPdS_i, @function
_Z3sumPdS_i:
.LFB3949:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %r12
movq %rsi, 8(%rsp)
movl %edx, %r14d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L36
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L36:
cvttsd2sil %xmm3, %ebp
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L37
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L37:
cvttsd2sil %xmm3, %ebx
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L38
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L38:
cvttsd2sil %xmm3, %r15d
movslq %r14d, %r13
salq $3, %r13
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movslq %ebp, %rsi
salq $3, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movslq %ebx, %rsi
salq $3, %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %r12d
.L47:
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %ebp, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L39:
call cudaDeviceSynchronize@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %ebx, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L40:
call cudaDeviceSynchronize@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %ebx, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L41:
call cudaDeviceSynchronize@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %r15d, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L42:
call cudaDeviceSynchronize@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %ebx, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L43:
call cudaDeviceSynchronize@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %ebp, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L56
.L44:
call cudaDeviceSynchronize@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %ebx, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L57
.L45:
call cudaDeviceSynchronize@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %ebp, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L58
.L46:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
subl $1, %r12d
jne .L47
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L59
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
movl %r14d, %edx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z29__device_stub__Z7upsweepPdS_iPdS_i
jmp .L39
.L52:
movl %ebp, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z29__device_stub__Z7upsweepPdS_iPdS_i
jmp .L40
.L53:
movl %ebx, %edx
movl $0, %esi
movq 40(%rsp), %rdi
call _Z29__device_stub__Z7upsweepPdS_iPdS_i
jmp .L41
.L54:
movl %ebx, %esi
movq 40(%rsp), %rdi
call _Z35__device_stub__Z14excl_downsweepPdiPdi
jmp .L42
.L55:
movl %ebp, %esi
movq 32(%rsp), %rdi
call _Z35__device_stub__Z14excl_downsweepPdiPdi
jmp .L43
.L56:
movq 24(%rsp), %rdi
call _Z34__device_stub__Z14incl_downsweepPdPd
jmp .L44
.L57:
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z35__device_stub__Z13scat_part_sumPdS_PdS_
jmp .L45
.L58:
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z35__device_stub__Z13scat_part_sumPdS_PdS_
jmp .L46
.L59:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3949:
.size _Z3sumPdS_i, .-_Z3sumPdS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "The argument is wrong! Execute your program with only input file name!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "r"
.section .rodata.str1.8
.align 8
.LC7:
.string "The file can not be opened or does not exist!\n"
.section .rodata.str1.1
.LC8:
.string "%d\n"
.LC9:
.string "%lg\n"
.LC10:
.string "w"
.LC11:
.string "output.txt"
.LC12:
.string "The file can not be created!\n"
.LC13:
.string "Done...\n"
.text
.globl main
.type main, @function
main:
.LFB3950:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L61
leaq .LC5(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %eax
.L60:
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L73
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
movl $16777216, 4(%rsp)
movq 8(%rsi), %rdi
leaq .LC6(%rip), %rsi
call fopen@PLT
movq %rax, %r12
testq %rax, %rax
je .L74
leaq 4(%rsp), %rdx
leaq .LC8(%rip), %rbx
movq %rbx, %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 4(%rsp), %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 4(%rsp), %ebp
movslq %ebp, %rbx
salq $3, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
testl %ebp, %ebp
jle .L64
movq %r14, %rbp
movl $0, %ebx
leaq .LC9(%rip), %r15
.L65:
movq %rbp, %rdx
movq %r15, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebx
addq $8, %rbp
cmpl %ebx, 4(%rsp)
jg .L65
.L64:
movq %r12, %rdi
call fclose@PLT
movl 4(%rsp), %edx
movq %r13, %rsi
movq %r14, %rdi
call _Z3sumPdS_i
leaq .LC10(%rip), %rsi
leaq .LC11(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
testq %rax, %rax
je .L75
movl 4(%rsp), %ecx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
cmpl $0, 4(%rsp)
jle .L67
movl $0, %ebx
leaq .LC9(%rip), %r12
.L68:
movsd 0(%r13,%rbx,8), %xmm0
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpl %ebx, 4(%rsp)
jg .L68
.L67:
movq %rbp, %rdi
call fclose@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L60
.L74:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L60
.L75:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L60
.L73:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3950:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z14incl_downsweepPd"
.LC15:
.string "_Z14excl_downsweepPdi"
.LC16:
.string "_Z7upsweepPdS_i"
.LC17:
.string "_Z13scat_part_sumPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3984:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z14incl_downsweepPd(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z14excl_downsweepPdi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z7upsweepPdS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z13scat_part_sumPdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3984:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1062207488
.align 8
.LC1:
.long 0
.long 1127219200
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC4:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <iomanip>
#include <ctime>
#include <cstdlib>
#include <cstdio>
#include <cmath>
#include "cuda_runtime.h"
using namespace std;
#define TPB 1024
#define min(a,b) ((a < b) ? a : b)
__global__
void scat_part_sum(double * array, double * array_psums) {
// Distributes the values from array_psums (array of partial sums) to every element
// in the array. Every thread in a block gets the same partial sum added to it
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
//__syncthreads();
array[tid] += array_psums[blockIdx.x];
//__syncthreads();
}
__global__
void upsweep (double * array, double * array_aggr1, int size) {
// Performs an upsweep
int bid = blockIdx.x * blockDim.x;
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
int min_size = min(size, TPB);
__syncthreads();
// Merge elements like a binary tree
for (int step = 2; step <= min_size ; step *= 2) {
if (tid % step == (step - 1) && (tid - (step / 2) >= bid)) {
array[tid] += array[tid - (step / 2)];
}
__syncthreads();
}
__syncthreads();
// Aggregates the sum of each block to another array for to calculate partial tums
if (array_aggr1 != NULL) {
if (threadIdx.x == (TPB - 1)) {
if (tid < size) {
array_aggr1[blockIdx.x] = array[tid];
}
else {
array_aggr1[blockIdx.x] = array[size - 1];
}
}
__syncthreads();
}
}
__global__
void excl_downsweep (double * array, int size) {
int bsize = blockIdx.x * blockDim.x;
int next_block = (blockIdx.x + 1) * blockDim.x;
int tid = bsize + threadIdx.x;
int tmp;
int min_size = min(size, TPB);
// Performs an exlusive down sweep. After the inclusive down sweep, each block
// will have elements 0, 0 + a_1 , 0 + a_1 + a_2, ... , 0 + a_1 + a_2 + ... + a_1023
if (tid % TPB == 0) { array[min(size, next_block) - 1] = 0; }
__syncthreads();
for (int step = min_size; step > 0; step /= 2) {
if (tid % step == (step - 1) && (tid - (step / 2) >= bsize)) {
tmp = array[tid];
array[tid] += array[tid - (step / 2)];
array[tid - (step / 2)] = tmp;
}
__syncthreads();
}
}
__global__
void incl_downsweep (double * array) {
int next_bid = (blockIdx.x + 1) * blockDim.x;
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
__syncthreads();
// Performs an inclusive down sweep. After the inclusive down sweep, each block
// will have elements a_1, a_1 + a_2, ... , a_1 + a_2 + ... + a_1024
for (int step = TPB / 2; step > 1; step /= 2) {
if (tid % step == (step - 1) && (tid + (step / 2) < next_bid)) {
array[tid + (step / 2)] += array[tid];
}
__syncthreads();
}
}
void sum(double* a, double* b, const int n) {
//Given an array a[0...n-1], you need to compute b[0...n-1],
//where b[i] = (i+1)*a[0] + i*a[1] + ... + 2*a[i-1] + a[i]
//Note that b is NOT initialized with 0, be careful!
//Write your CUDA code starting from here
//Add any functions (e.g., device function) you want within this file
int size = n;
int size_div1 = int(ceil(double(size) / double(TPB)));
int size_div2 = int(ceil(double(size_div1) / double(TPB)));
int nblocks = int(ceil(double(size) / double(TPB)));
int nblocks_div1 = int(ceil(double(nblocks) / double(TPB)));
int nblocks_div2 = int(ceil(double(nblocks_div1) / double(TPB)));
double *d_x, *d_x1, *d_x2;
cudaMalloc(&d_x, size * sizeof(double));
cudaMalloc(&d_x1, size_div1 * sizeof(double));
cudaMalloc(&d_x2, size_div2 * sizeof(double));
cudaMemcpy(d_x, a, size * sizeof(double), cudaMemcpyHostToDevice);
//cudaMemcpy(d_x1, x1, size_div1 * sizeof(double), cudaMemcpyHostToDevice);
//cudaMemcpy(d_x2, x2, size_div2 * sizeof(double), cudaMemcpyHostToDevice);
for (int pf_step = 1; pf_step < 3; pf_step++) {
// cout << "Up-Sweep\n" << endl;
upsweep <<<nblocks, TPB>>> (d_x, d_x1, size);
cudaDeviceSynchronize();
// cout << "Up-Sweep 2\n" << endl;
upsweep <<<nblocks_div1, TPB>>> (d_x1, d_x2, size_div1);
cudaDeviceSynchronize();
// cout << "Up-Sweep 3\n" << endl;
upsweep <<<nblocks_div1, TPB>>> (d_x2, NULL, size_div2);
cudaDeviceSynchronize();
// cout << "Down-Sweep 3\n" << endl;
excl_downsweep <<<nblocks_div2, TPB>>> (d_x2, size_div2);
cudaDeviceSynchronize();
// cout << "Down-Sweep 2\n" << endl;
excl_downsweep <<<nblocks_div1, TPB>>> (d_x1, size_div1);
cudaDeviceSynchronize();
// cout << "Down-Sweep\n" << endl;
incl_downsweep <<<nblocks, TPB>>> (d_x);
cudaDeviceSynchronize();
// cout << "Scatter Partial Sums 2\n" << endl;
scat_part_sum <<<nblocks_div1, TPB>>> (d_x1, d_x2);
cudaDeviceSynchronize();
// cout << "Scatter Partial Sums 1\n" << endl;
scat_part_sum <<<nblocks, TPB>>> (d_x, d_x1);
cudaDeviceSynchronize();
cudaMemcpy(b, d_x, size * sizeof(double), cudaMemcpyDeviceToHost);
}
}
int main(int argc, const char * argv[]) {
if (argc != 2) {
printf("The argument is wrong! Execute your program with only input file name!\n");
return 1;
}
int n = 1 << 24;
//Dummy code for creating a random input vectors
//Convenient for the text purpose
//Please comment out when you submit your code!!!!!!!!!
/* FILE *fpw = fopen(argv[1], "w");
if (fpw == NULL) {
printf("The file can not be created!\n");
return 1;
}
//int n = 1 << 24;
fprintf(fpw, "%d\n", n);
srand(time(NULL));
for (int i=0; i<n; i++)
fprintf(fpw, "%lg\n", ((double)(rand() % n))/100);
fclose(fpw);
printf("Finished writing\n");
*/
//Read input from input file specified by user
FILE* fpr = fopen(argv[1], "r");
if (fpr == NULL) {
printf("The file can not be opened or does not exist!\n");
return 1;
}
//int n;
fscanf(fpr, "%d\n", &n);
printf("%d\n", n);
double* a = (double*)malloc(n*sizeof(double));
double* b = (double*)malloc(n*sizeof(double));
for (int i=0; i<n; i++) {
fscanf(fpr, "%lg\n", &a[i]);
}
fclose(fpr);
//Main function
sum(a, b, n);
//Write b into output file
FILE* fpo = fopen("output.txt","w");
if (fpo == NULL) {
printf("The file can not be created!\n");
return 1;
}
fprintf(fpo, "%d\n", n);
for (int i=0; i<n; i++)
fprintf(fpo, "%lg\n", b[i]);
fclose(fpo);
free(a);
free(b);
printf("Done...\n");
return 0;
} | #include <iostream>
#include <iomanip>
#include <ctime>
#include <cstdlib>
#include <cstdio>
#include <cmath>
#include "hip/hip_runtime.h"
using namespace std;
#define TPB 1024
#define min(a,b) ((a < b) ? a : b)
__global__
void scat_part_sum(double * array, double * array_psums) {
// Distributes the values from array_psums (array of partial sums) to every element
// in the array. Every thread in a block gets the same partial sum added to it
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
//__syncthreads();
array[tid] += array_psums[blockIdx.x];
//__syncthreads();
}
__global__
void upsweep (double * array, double * array_aggr1, int size) {
// Performs an upsweep
int bid = blockIdx.x * blockDim.x;
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
int min_size = min(size, TPB);
__syncthreads();
// Merge elements like a binary tree
for (int step = 2; step <= min_size ; step *= 2) {
if (tid % step == (step - 1) && (tid - (step / 2) >= bid)) {
array[tid] += array[tid - (step / 2)];
}
__syncthreads();
}
__syncthreads();
// Aggregates the sum of each block to another array for to calculate partial tums
if (array_aggr1 != NULL) {
if (threadIdx.x == (TPB - 1)) {
if (tid < size) {
array_aggr1[blockIdx.x] = array[tid];
}
else {
array_aggr1[blockIdx.x] = array[size - 1];
}
}
__syncthreads();
}
}
__global__
void excl_downsweep (double * array, int size) {
int bsize = blockIdx.x * blockDim.x;
int next_block = (blockIdx.x + 1) * blockDim.x;
int tid = bsize + threadIdx.x;
int tmp;
int min_size = min(size, TPB);
// Performs an exlusive down sweep. After the inclusive down sweep, each block
// will have elements 0, 0 + a_1 , 0 + a_1 + a_2, ... , 0 + a_1 + a_2 + ... + a_1023
if (tid % TPB == 0) { array[min(size, next_block) - 1] = 0; }
__syncthreads();
for (int step = min_size; step > 0; step /= 2) {
if (tid % step == (step - 1) && (tid - (step / 2) >= bsize)) {
tmp = array[tid];
array[tid] += array[tid - (step / 2)];
array[tid - (step / 2)] = tmp;
}
__syncthreads();
}
}
__global__
void incl_downsweep (double * array) {
int next_bid = (blockIdx.x + 1) * blockDim.x;
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
__syncthreads();
// Performs an inclusive down sweep. After the inclusive down sweep, each block
// will have elements a_1, a_1 + a_2, ... , a_1 + a_2 + ... + a_1024
for (int step = TPB / 2; step > 1; step /= 2) {
if (tid % step == (step - 1) && (tid + (step / 2) < next_bid)) {
array[tid + (step / 2)] += array[tid];
}
__syncthreads();
}
}
void sum(double* a, double* b, const int n) {
//Given an array a[0...n-1], you need to compute b[0...n-1],
//where b[i] = (i+1)*a[0] + i*a[1] + ... + 2*a[i-1] + a[i]
//Note that b is NOT initialized with 0, be careful!
//Write your CUDA code starting from here
//Add any functions (e.g., device function) you want within this file
int size = n;
int size_div1 = int(ceil(double(size) / double(TPB)));
int size_div2 = int(ceil(double(size_div1) / double(TPB)));
int nblocks = int(ceil(double(size) / double(TPB)));
int nblocks_div1 = int(ceil(double(nblocks) / double(TPB)));
int nblocks_div2 = int(ceil(double(nblocks_div1) / double(TPB)));
double *d_x, *d_x1, *d_x2;
hipMalloc(&d_x, size * sizeof(double));
hipMalloc(&d_x1, size_div1 * sizeof(double));
hipMalloc(&d_x2, size_div2 * sizeof(double));
hipMemcpy(d_x, a, size * sizeof(double), hipMemcpyHostToDevice);
//cudaMemcpy(d_x1, x1, size_div1 * sizeof(double), cudaMemcpyHostToDevice);
//cudaMemcpy(d_x2, x2, size_div2 * sizeof(double), cudaMemcpyHostToDevice);
for (int pf_step = 1; pf_step < 3; pf_step++) {
// cout << "Up-Sweep\n" << endl;
upsweep <<<nblocks, TPB>>> (d_x, d_x1, size);
hipDeviceSynchronize();
// cout << "Up-Sweep 2\n" << endl;
upsweep <<<nblocks_div1, TPB>>> (d_x1, d_x2, size_div1);
hipDeviceSynchronize();
// cout << "Up-Sweep 3\n" << endl;
upsweep <<<nblocks_div1, TPB>>> (d_x2, NULL, size_div2);
hipDeviceSynchronize();
// cout << "Down-Sweep 3\n" << endl;
excl_downsweep <<<nblocks_div2, TPB>>> (d_x2, size_div2);
hipDeviceSynchronize();
// cout << "Down-Sweep 2\n" << endl;
excl_downsweep <<<nblocks_div1, TPB>>> (d_x1, size_div1);
hipDeviceSynchronize();
// cout << "Down-Sweep\n" << endl;
incl_downsweep <<<nblocks, TPB>>> (d_x);
hipDeviceSynchronize();
// cout << "Scatter Partial Sums 2\n" << endl;
scat_part_sum <<<nblocks_div1, TPB>>> (d_x1, d_x2);
hipDeviceSynchronize();
// cout << "Scatter Partial Sums 1\n" << endl;
scat_part_sum <<<nblocks, TPB>>> (d_x, d_x1);
hipDeviceSynchronize();
hipMemcpy(b, d_x, size * sizeof(double), hipMemcpyDeviceToHost);
}
}
int main(int argc, const char * argv[]) {
if (argc != 2) {
printf("The argument is wrong! Execute your program with only input file name!\n");
return 1;
}
int n = 1 << 24;
//Dummy code for creating a random input vectors
//Convenient for the text purpose
//Please comment out when you submit your code!!!!!!!!!
/* FILE *fpw = fopen(argv[1], "w");
if (fpw == NULL) {
printf("The file can not be created!\n");
return 1;
}
//int n = 1 << 24;
fprintf(fpw, "%d\n", n);
srand(time(NULL));
for (int i=0; i<n; i++)
fprintf(fpw, "%lg\n", ((double)(rand() % n))/100);
fclose(fpw);
printf("Finished writing\n");
*/
//Read input from input file specified by user
FILE* fpr = fopen(argv[1], "r");
if (fpr == NULL) {
printf("The file can not be opened or does not exist!\n");
return 1;
}
//int n;
fscanf(fpr, "%d\n", &n);
printf("%d\n", n);
double* a = (double*)malloc(n*sizeof(double));
double* b = (double*)malloc(n*sizeof(double));
for (int i=0; i<n; i++) {
fscanf(fpr, "%lg\n", &a[i]);
}
fclose(fpr);
//Main function
sum(a, b, n);
//Write b into output file
FILE* fpo = fopen("output.txt","w");
if (fpo == NULL) {
printf("The file can not be created!\n");
return 1;
}
fprintf(fpo, "%d\n", n);
for (int i=0; i<n; i++)
fprintf(fpo, "%lg\n", b[i]);
fclose(fpo);
free(a);
free(b);
printf("Done...\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <iomanip>
#include <ctime>
#include <cstdlib>
#include <cstdio>
#include <cmath>
#include "hip/hip_runtime.h"
using namespace std;
#define TPB 1024
#define min(a,b) ((a < b) ? a : b)
__global__
void scat_part_sum(double * array, double * array_psums) {
// Distributes the values from array_psums (array of partial sums) to every element
// in the array. Every thread in a block gets the same partial sum added to it
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
//__syncthreads();
array[tid] += array_psums[blockIdx.x];
//__syncthreads();
}
__global__
void upsweep (double * array, double * array_aggr1, int size) {
// Performs an upsweep
int bid = blockIdx.x * blockDim.x;
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
int min_size = min(size, TPB);
__syncthreads();
// Merge elements like a binary tree
for (int step = 2; step <= min_size ; step *= 2) {
if (tid % step == (step - 1) && (tid - (step / 2) >= bid)) {
array[tid] += array[tid - (step / 2)];
}
__syncthreads();
}
__syncthreads();
// Aggregates the sum of each block to another array for to calculate partial tums
if (array_aggr1 != NULL) {
if (threadIdx.x == (TPB - 1)) {
if (tid < size) {
array_aggr1[blockIdx.x] = array[tid];
}
else {
array_aggr1[blockIdx.x] = array[size - 1];
}
}
__syncthreads();
}
}
__global__
void excl_downsweep (double * array, int size) {
int bsize = blockIdx.x * blockDim.x;
int next_block = (blockIdx.x + 1) * blockDim.x;
int tid = bsize + threadIdx.x;
int tmp;
int min_size = min(size, TPB);
// Performs an exlusive down sweep. After the inclusive down sweep, each block
// will have elements 0, 0 + a_1 , 0 + a_1 + a_2, ... , 0 + a_1 + a_2 + ... + a_1023
if (tid % TPB == 0) { array[min(size, next_block) - 1] = 0; }
__syncthreads();
for (int step = min_size; step > 0; step /= 2) {
if (tid % step == (step - 1) && (tid - (step / 2) >= bsize)) {
tmp = array[tid];
array[tid] += array[tid - (step / 2)];
array[tid - (step / 2)] = tmp;
}
__syncthreads();
}
}
__global__
void incl_downsweep (double * array) {
int next_bid = (blockIdx.x + 1) * blockDim.x;
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
__syncthreads();
// Performs an inclusive down sweep. After the inclusive down sweep, each block
// will have elements a_1, a_1 + a_2, ... , a_1 + a_2 + ... + a_1024
for (int step = TPB / 2; step > 1; step /= 2) {
if (tid % step == (step - 1) && (tid + (step / 2) < next_bid)) {
array[tid + (step / 2)] += array[tid];
}
__syncthreads();
}
}
void sum(double* a, double* b, const int n) {
//Given an array a[0...n-1], you need to compute b[0...n-1],
//where b[i] = (i+1)*a[0] + i*a[1] + ... + 2*a[i-1] + a[i]
//Note that b is NOT initialized with 0, be careful!
//Write your CUDA code starting from here
//Add any functions (e.g., device function) you want within this file
int size = n;
int size_div1 = int(ceil(double(size) / double(TPB)));
int size_div2 = int(ceil(double(size_div1) / double(TPB)));
int nblocks = int(ceil(double(size) / double(TPB)));
int nblocks_div1 = int(ceil(double(nblocks) / double(TPB)));
int nblocks_div2 = int(ceil(double(nblocks_div1) / double(TPB)));
double *d_x, *d_x1, *d_x2;
hipMalloc(&d_x, size * sizeof(double));
hipMalloc(&d_x1, size_div1 * sizeof(double));
hipMalloc(&d_x2, size_div2 * sizeof(double));
hipMemcpy(d_x, a, size * sizeof(double), hipMemcpyHostToDevice);
//cudaMemcpy(d_x1, x1, size_div1 * sizeof(double), cudaMemcpyHostToDevice);
//cudaMemcpy(d_x2, x2, size_div2 * sizeof(double), cudaMemcpyHostToDevice);
for (int pf_step = 1; pf_step < 3; pf_step++) {
// cout << "Up-Sweep\n" << endl;
upsweep <<<nblocks, TPB>>> (d_x, d_x1, size);
hipDeviceSynchronize();
// cout << "Up-Sweep 2\n" << endl;
upsweep <<<nblocks_div1, TPB>>> (d_x1, d_x2, size_div1);
hipDeviceSynchronize();
// cout << "Up-Sweep 3\n" << endl;
upsweep <<<nblocks_div1, TPB>>> (d_x2, NULL, size_div2);
hipDeviceSynchronize();
// cout << "Down-Sweep 3\n" << endl;
excl_downsweep <<<nblocks_div2, TPB>>> (d_x2, size_div2);
hipDeviceSynchronize();
// cout << "Down-Sweep 2\n" << endl;
excl_downsweep <<<nblocks_div1, TPB>>> (d_x1, size_div1);
hipDeviceSynchronize();
// cout << "Down-Sweep\n" << endl;
incl_downsweep <<<nblocks, TPB>>> (d_x);
hipDeviceSynchronize();
// cout << "Scatter Partial Sums 2\n" << endl;
scat_part_sum <<<nblocks_div1, TPB>>> (d_x1, d_x2);
hipDeviceSynchronize();
// cout << "Scatter Partial Sums 1\n" << endl;
scat_part_sum <<<nblocks, TPB>>> (d_x, d_x1);
hipDeviceSynchronize();
hipMemcpy(b, d_x, size * sizeof(double), hipMemcpyDeviceToHost);
}
}
int main(int argc, const char * argv[]) {
if (argc != 2) {
printf("The argument is wrong! Execute your program with only input file name!\n");
return 1;
}
int n = 1 << 24;
//Dummy code for creating a random input vectors
//Convenient for the text purpose
//Please comment out when you submit your code!!!!!!!!!
/* FILE *fpw = fopen(argv[1], "w");
if (fpw == NULL) {
printf("The file can not be created!\n");
return 1;
}
//int n = 1 << 24;
fprintf(fpw, "%d\n", n);
srand(time(NULL));
for (int i=0; i<n; i++)
fprintf(fpw, "%lg\n", ((double)(rand() % n))/100);
fclose(fpw);
printf("Finished writing\n");
*/
//Read input from input file specified by user
FILE* fpr = fopen(argv[1], "r");
if (fpr == NULL) {
printf("The file can not be opened or does not exist!\n");
return 1;
}
//int n;
fscanf(fpr, "%d\n", &n);
printf("%d\n", n);
double* a = (double*)malloc(n*sizeof(double));
double* b = (double*)malloc(n*sizeof(double));
for (int i=0; i<n; i++) {
fscanf(fpr, "%lg\n", &a[i]);
}
fclose(fpr);
//Main function
sum(a, b, n);
//Write b into output file
FILE* fpo = fopen("output.txt","w");
if (fpo == NULL) {
printf("The file can not be created!\n");
return 1;
}
fprintf(fpo, "%d\n", n);
for (int i=0; i<n; i++)
fprintf(fpo, "%lg\n", b[i]);
fclose(fpo);
free(a);
free(b);
printf("Done...\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13scat_part_sumPdS_
.globl _Z13scat_part_sumPdS_
.p2align 8
.type _Z13scat_part_sumPdS_,@function
_Z13scat_part_sumPdS_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_mov_b32 s5, 0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_lshl_b64 s[0:1], s[4:5], 3
s_add_u32 s0, s2, s0
global_load_b64 v[2:3], v[0:1], off
s_addc_u32 s1, s3, s1
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f64 v[2:3], s[0:1], v[2:3]
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13scat_part_sumPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13scat_part_sumPdS_, .Lfunc_end0-_Z13scat_part_sumPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7upsweepPdS_i
.globl _Z7upsweepPdS_i
.p2align 8
.type _Z7upsweepPdS_i,@function
_Z7upsweepPdS_i:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_mov_b32 s5, 2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s3, s3, 0xffff
s_cmp_lt_i32 s4, 2
s_mul_i32 s3, s15, s3
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v1, s3, v0
s_cbranch_scc1 .LBB1_6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v6, 31, v1
s_min_i32 s8, s4, 0x400
v_lshlrev_b64 v[2:3], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v6
v_xor_b32_e32 v7, v4, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_branch .LBB1_3
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s9
s_lshl_b32 s5, s5, 1
s_waitcnt_vscnt null, 0x0
s_cmp_gt_i32 s5, s8
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_6
.LBB1_3:
s_ashr_i32 s9, s5, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s10, s5, s9
s_xor_b32 s9, s10, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v4, s9
s_sub_i32 s10, 0, s9
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v4, v4
v_mul_lo_u32 v5, s10, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v4, v5
v_add_nc_u32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v7, v4
v_mul_lo_u32 v4, v4, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v7, v4
v_subrev_nc_u32_e32 v5, s9, v4
v_cmp_le_u32_e32 vcc_lo, s9, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_subrev_nc_u32_e32 v5, s9, v4
v_cmp_le_u32_e32 vcc_lo, s9, v4
s_add_i32 s9, s5, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_xor_b32_e32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v4, v6
v_cmp_eq_u32_e32 vcc_lo, s9, v4
s_and_saveexec_b32 s9, vcc_lo
s_cbranch_execz .LBB1_2
s_lshr_b32 s10, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v4, s10, v1
v_cmp_le_i32_e32 vcc_lo, s3, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 3, v[4:5]
v_add_co_u32 v4, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
s_clause 0x1
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[8:9], v[2:3], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[8:9]
global_store_b64 v[2:3], v[4:5], off
s_branch .LBB1_2
.LBB1_6:
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cmp_lg_u64 s[0:1], 0
s_cbranch_scc0 .LBB1_10
s_mov_b32 s8, exec_lo
v_cmpx_eq_u32_e32 0x3ff, v0
s_cbranch_execz .LBB1_9
v_ashrrev_i32_e32 v2, 31, v1
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[4:5], 3
s_add_u32 s3, s6, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[1:2]
s_addc_u32 s5, s7, s11
s_add_u32 s3, s3, -8
s_addc_u32 s5, s5, -1
v_add_co_u32 v0, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v3, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s4, v1
v_dual_cndmask_b32 v1, s5, v2 :: v_dual_mov_b32 v2, 0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cndmask_b32_e32 v0, s3, v0, vcc_lo
s_mov_b32 s3, 0
s_lshl_b64 s[2:3], s[2:3], 3
global_load_b64 v[0:1], v[0:1], off
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
.LBB1_9:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB1_10:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7upsweepPdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7upsweepPdS_i, .Lfunc_end1-_Z7upsweepPdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14excl_downsweepPdi
.globl _Z14excl_downsweepPdi
.p2align 8
.type _Z14excl_downsweepPdi,@function
_Z14excl_downsweepPdi:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s1, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_mov_b32 s4, exec_lo
s_mul_i32 s0, s15, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, s0, v0
v_and_b32_e32 v1, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB2_2
s_add_i32 s6, s15, 1
v_mov_b32_e32 v1, 0
s_mul_i32 s6, s6, s5
v_mov_b32_e32 v3, 0
s_min_i32 s6, s6, s1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v2, v1
s_ashr_i32 s7, s6, 31
s_lshl_b64 s[6:7], s[6:7], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s6, s2, s6
s_addc_u32 s7, s3, s7
global_store_b64 v3, v[1:2], s[6:7] offset:-8
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s4
s_cmp_lt_i32 s1, 1
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB2_8
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v5, 31, v0
s_min_i32 s1, s1, 0x400
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 3, v[0:1]
v_add_nc_u32_e32 v3, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v6, v3, v5
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_branch .LBB2_5
.LBB2_4:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s1, 1
s_cmp_lt_u32 s1, 2
s_mov_b32 s1, s4
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB2_8
.LBB2_5:
s_ashr_i32 s4, s1, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s1, s4
s_xor_b32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v3, s4
s_sub_i32 s5, 0, s4
v_rcp_iflag_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v3, v3
v_mul_lo_u32 v4, s5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v3, v4
v_add_nc_u32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v6, v3
v_mul_lo_u32 v3, v3, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v6, v3
v_subrev_nc_u32_e32 v4, s4, v3
v_cmp_le_u32_e32 vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_subrev_nc_u32_e32 v4, s4, v3
v_cmp_le_u32_e32 vcc_lo, s4, v3
s_add_i32 s4, s1, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_xor_b32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v3, v5
v_cmp_eq_u32_e32 vcc_lo, s4, v3
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB2_4
s_lshr_b32 s5, s1, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v3, s5, v0
v_cmp_le_i32_e32 vcc_lo, s0, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_4
global_load_b64 v[7:8], v[1:2], off
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[3:4]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b64 v[9:10], v[3:4], off
s_waitcnt vmcnt(1)
v_cvt_i32_f64_e32 v11, v[7:8]
s_waitcnt vmcnt(0)
v_add_f64 v[7:8], v[7:8], v[9:10]
s_delay_alu instid0(VALU_DEP_2)
v_cvt_f64_i32_e32 v[9:10], v11
s_clause 0x1
global_store_b64 v[1:2], v[7:8], off
global_store_b64 v[3:4], v[9:10], off
s_branch .LBB2_4
.LBB2_8:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14excl_downsweepPdi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z14excl_downsweepPdi, .Lfunc_end2-_Z14excl_downsweepPdi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14incl_downsweepPd
.globl _Z14incl_downsweepPd
.p2align 8
.type _Z14incl_downsweepPd,@function
_Z14incl_downsweepPd:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x14
s_load_b64 s[2:3], s[0:1], 0x0
s_add_i32 s1, s15, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s0, s4, 0xffff
s_movk_i32 s4, 0x200
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_mul_i32 s1, s1, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v0, 31, v1
v_lshlrev_b64 v[2:3], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v0
v_xor_b32_e32 v6, v4, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_branch .LBB3_2
.LBB3_1:
s_or_b32 exec_lo, exec_lo, s0
s_cmp_lt_u32 s4, 4
s_mov_b32 s4, s5
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB3_4
.LBB3_2:
v_cvt_f32_u32_e32 v4, s4
s_sub_i32 s0, 0, s4
s_lshr_b32 s5, s4, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
v_cvt_u32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, s0, v4
s_add_i32 s0, s4, -1
v_mul_hi_u32 v5, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v4, v5
v_mul_hi_u32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v4, s4
v_sub_nc_u32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v4
v_cmp_le_u32_e32 vcc_lo, s4, v4
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v4
v_cmp_le_u32_e32 vcc_lo, s4, v4
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v4, v4, v0
v_sub_nc_u32_e32 v5, v4, v0
v_add_nc_u32_e32 v4, s5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e32 vcc_lo, s0, v5
v_cmp_gt_i32_e64 s0, s1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s6, vcc_lo, s0
s_and_saveexec_b32 s0, s6
s_cbranch_execz .LBB3_1
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 3, v[4:5]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_clause 0x1
global_load_b64 v[7:8], v[2:3], off
global_load_b64 v[9:10], v[4:5], off
s_waitcnt vmcnt(0)
v_add_f64 v[7:8], v[7:8], v[9:10]
global_store_b64 v[4:5], v[7:8], off
s_branch .LBB3_1
.LBB3_4:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14incl_downsweepPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z14incl_downsweepPd, .Lfunc_end3-_Z14incl_downsweepPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13scat_part_sumPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13scat_part_sumPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7upsweepPdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7upsweepPdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14excl_downsweepPdi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14excl_downsweepPdi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14incl_downsweepPd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14incl_downsweepPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <iomanip>
#include <ctime>
#include <cstdlib>
#include <cstdio>
#include <cmath>
#include "hip/hip_runtime.h"
using namespace std;
#define TPB 1024
#define min(a,b) ((a < b) ? a : b)
__global__
void scat_part_sum(double * array, double * array_psums) {
// Distributes the values from array_psums (array of partial sums) to every element
// in the array. Every thread in a block gets the same partial sum added to it
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
//__syncthreads();
array[tid] += array_psums[blockIdx.x];
//__syncthreads();
}
__global__
void upsweep (double * array, double * array_aggr1, int size) {
// Performs an upsweep
int bid = blockIdx.x * blockDim.x;
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
int min_size = min(size, TPB);
__syncthreads();
// Merge elements like a binary tree
for (int step = 2; step <= min_size ; step *= 2) {
if (tid % step == (step - 1) && (tid - (step / 2) >= bid)) {
array[tid] += array[tid - (step / 2)];
}
__syncthreads();
}
__syncthreads();
// Aggregates the sum of each block to another array for to calculate partial tums
if (array_aggr1 != NULL) {
if (threadIdx.x == (TPB - 1)) {
if (tid < size) {
array_aggr1[blockIdx.x] = array[tid];
}
else {
array_aggr1[blockIdx.x] = array[size - 1];
}
}
__syncthreads();
}
}
__global__
void excl_downsweep (double * array, int size) {
int bsize = blockIdx.x * blockDim.x;
int next_block = (blockIdx.x + 1) * blockDim.x;
int tid = bsize + threadIdx.x;
int tmp;
int min_size = min(size, TPB);
// Performs an exlusive down sweep. After the inclusive down sweep, each block
// will have elements 0, 0 + a_1 , 0 + a_1 + a_2, ... , 0 + a_1 + a_2 + ... + a_1023
if (tid % TPB == 0) { array[min(size, next_block) - 1] = 0; }
__syncthreads();
for (int step = min_size; step > 0; step /= 2) {
if (tid % step == (step - 1) && (tid - (step / 2) >= bsize)) {
tmp = array[tid];
array[tid] += array[tid - (step / 2)];
array[tid - (step / 2)] = tmp;
}
__syncthreads();
}
}
__global__
void incl_downsweep (double * array) {
int next_bid = (blockIdx.x + 1) * blockDim.x;
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
__syncthreads();
// Performs an inclusive down sweep. After the inclusive down sweep, each block
// will have elements a_1, a_1 + a_2, ... , a_1 + a_2 + ... + a_1024
for (int step = TPB / 2; step > 1; step /= 2) {
if (tid % step == (step - 1) && (tid + (step / 2) < next_bid)) {
array[tid + (step / 2)] += array[tid];
}
__syncthreads();
}
}
void sum(double* a, double* b, const int n) {
//Given an array a[0...n-1], you need to compute b[0...n-1],
//where b[i] = (i+1)*a[0] + i*a[1] + ... + 2*a[i-1] + a[i]
//Note that b is NOT initialized with 0, be careful!
//Write your CUDA code starting from here
//Add any functions (e.g., device function) you want within this file
int size = n;
int size_div1 = int(ceil(double(size) / double(TPB)));
int size_div2 = int(ceil(double(size_div1) / double(TPB)));
int nblocks = int(ceil(double(size) / double(TPB)));
int nblocks_div1 = int(ceil(double(nblocks) / double(TPB)));
int nblocks_div2 = int(ceil(double(nblocks_div1) / double(TPB)));
double *d_x, *d_x1, *d_x2;
hipMalloc(&d_x, size * sizeof(double));
hipMalloc(&d_x1, size_div1 * sizeof(double));
hipMalloc(&d_x2, size_div2 * sizeof(double));
hipMemcpy(d_x, a, size * sizeof(double), hipMemcpyHostToDevice);
//cudaMemcpy(d_x1, x1, size_div1 * sizeof(double), cudaMemcpyHostToDevice);
//cudaMemcpy(d_x2, x2, size_div2 * sizeof(double), cudaMemcpyHostToDevice);
for (int pf_step = 1; pf_step < 3; pf_step++) {
// cout << "Up-Sweep\n" << endl;
upsweep <<<nblocks, TPB>>> (d_x, d_x1, size);
hipDeviceSynchronize();
// cout << "Up-Sweep 2\n" << endl;
upsweep <<<nblocks_div1, TPB>>> (d_x1, d_x2, size_div1);
hipDeviceSynchronize();
// cout << "Up-Sweep 3\n" << endl;
upsweep <<<nblocks_div1, TPB>>> (d_x2, NULL, size_div2);
hipDeviceSynchronize();
// cout << "Down-Sweep 3\n" << endl;
excl_downsweep <<<nblocks_div2, TPB>>> (d_x2, size_div2);
hipDeviceSynchronize();
// cout << "Down-Sweep 2\n" << endl;
excl_downsweep <<<nblocks_div1, TPB>>> (d_x1, size_div1);
hipDeviceSynchronize();
// cout << "Down-Sweep\n" << endl;
incl_downsweep <<<nblocks, TPB>>> (d_x);
hipDeviceSynchronize();
// cout << "Scatter Partial Sums 2\n" << endl;
scat_part_sum <<<nblocks_div1, TPB>>> (d_x1, d_x2);
hipDeviceSynchronize();
// cout << "Scatter Partial Sums 1\n" << endl;
scat_part_sum <<<nblocks, TPB>>> (d_x, d_x1);
hipDeviceSynchronize();
hipMemcpy(b, d_x, size * sizeof(double), hipMemcpyDeviceToHost);
}
}
int main(int argc, const char * argv[]) {
if (argc != 2) {
printf("The argument is wrong! Execute your program with only input file name!\n");
return 1;
}
int n = 1 << 24;
//Dummy code for creating a random input vectors
//Convenient for the text purpose
//Please comment out when you submit your code!!!!!!!!!
/* FILE *fpw = fopen(argv[1], "w");
if (fpw == NULL) {
printf("The file can not be created!\n");
return 1;
}
//int n = 1 << 24;
fprintf(fpw, "%d\n", n);
srand(time(NULL));
for (int i=0; i<n; i++)
fprintf(fpw, "%lg\n", ((double)(rand() % n))/100);
fclose(fpw);
printf("Finished writing\n");
*/
//Read input from input file specified by user
FILE* fpr = fopen(argv[1], "r");
if (fpr == NULL) {
printf("The file can not be opened or does not exist!\n");
return 1;
}
//int n;
fscanf(fpr, "%d\n", &n);
printf("%d\n", n);
double* a = (double*)malloc(n*sizeof(double));
double* b = (double*)malloc(n*sizeof(double));
for (int i=0; i<n; i++) {
fscanf(fpr, "%lg\n", &a[i]);
}
fclose(fpr);
//Main function
sum(a, b, n);
//Write b into output file
FILE* fpo = fopen("output.txt","w");
if (fpo == NULL) {
printf("The file can not be created!\n");
return 1;
}
fprintf(fpo, "%d\n", n);
for (int i=0; i<n; i++)
fprintf(fpo, "%lg\n", b[i]);
fclose(fpo);
free(a);
free(b);
printf("Done...\n");
return 0;
} | .text
.file "prefix_sum.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__scat_part_sumPdS_ # -- Begin function _Z28__device_stub__scat_part_sumPdS_
.p2align 4, 0x90
.type _Z28__device_stub__scat_part_sumPdS_,@function
_Z28__device_stub__scat_part_sumPdS_: # @_Z28__device_stub__scat_part_sumPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13scat_part_sumPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__scat_part_sumPdS_, .Lfunc_end0-_Z28__device_stub__scat_part_sumPdS_
.cfi_endproc
# -- End function
.globl _Z22__device_stub__upsweepPdS_i # -- Begin function _Z22__device_stub__upsweepPdS_i
.p2align 4, 0x90
.type _Z22__device_stub__upsweepPdS_i,@function
_Z22__device_stub__upsweepPdS_i: # @_Z22__device_stub__upsweepPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7upsweepPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z22__device_stub__upsweepPdS_i, .Lfunc_end1-_Z22__device_stub__upsweepPdS_i
.cfi_endproc
# -- End function
.globl _Z29__device_stub__excl_downsweepPdi # -- Begin function _Z29__device_stub__excl_downsweepPdi
.p2align 4, 0x90
.type _Z29__device_stub__excl_downsweepPdi,@function
_Z29__device_stub__excl_downsweepPdi: # @_Z29__device_stub__excl_downsweepPdi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14excl_downsweepPdi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z29__device_stub__excl_downsweepPdi, .Lfunc_end2-_Z29__device_stub__excl_downsweepPdi
.cfi_endproc
# -- End function
.globl _Z29__device_stub__incl_downsweepPd # -- Begin function _Z29__device_stub__incl_downsweepPd
.p2align 4, 0x90
.type _Z29__device_stub__incl_downsweepPd,@function
_Z29__device_stub__incl_downsweepPd: # @_Z29__device_stub__incl_downsweepPd
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z14incl_downsweepPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z29__device_stub__incl_downsweepPd, .Lfunc_end3-_Z29__device_stub__incl_downsweepPd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z3sumPdS_i
.LCPI4_0:
.quad 0x3f50000000000000 # double 9.765625E-4
.text
.globl _Z3sumPdS_i
.p2align 4, 0x90
.type _Z3sumPdS_i,@function
_Z3sumPdS_i: # @_Z3sumPdS_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, 176(%rsp) # 8-byte Spill
movq %rdi, %r13
movabsq $4294968320, %r15 # imm = 0x100000400
cvtsi2sd %edx, %xmm0
mulsd .LCPI4_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r12d
cvttpd2dq %xmm0, %xmm0
cvtdq2pd %xmm0, %xmm0
mulsd .LCPI4_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %ebx
cvttpd2dq %xmm0, %xmm0
cvtdq2pd %xmm0, %xmm0
mulsd .LCPI4_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r14d
movl %ebp, 140(%rsp) # 4-byte Spill
movslq %ebp, %rbp
shlq $3, %rbp
leaq 120(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movslq %r12d, %rsi
shlq $3, %rsi
leaq 112(%rsp), %rdi
callq hipMalloc
movslq %ebx, %rsi
shlq $3, %rsi
leaq 128(%rsp), %rdi
callq hipMalloc
movq 120(%rsp), %rdi
movq %r13, %rsi
movq %rbp, 168(%rsp) # 8-byte Spill
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r12, 152(%rsp) # 8-byte Spill
leaq (%r12,%r15), %r13
addq $-1024, %r13 # imm = 0xFC00
movq %rbx, 144(%rsp) # 8-byte Spill
leaq -1024(%rbx,%r15), %rbp
leaq -1024(%r14,%r15), %rax
movq %rax, 160(%rsp) # 8-byte Spill
movl $2, %r14d
leaq 64(%rsp), %rbx
leaq 80(%rsp), %r12
jmp .LBB4_1
.p2align 4, 0x90
.LBB4_17: # in Loop: Header=BB4_1 Depth=1
callq hipDeviceSynchronize
movq 120(%rsp), %rsi
movq 176(%rsp), %rdi # 8-byte Reload
movq 168(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
decl %r14d
je .LBB4_18
.LBB4_1: # =>This Inner Loop Header: Depth=1
movq %r13, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_3
# %bb.2: # in Loop: Header=BB4_1 Depth=1
movq 120(%rsp), %rax
movq 112(%rsp), %rcx
movq %rax, 24(%rsp)
movq %rcx, 16(%rsp)
movl 140(%rsp), %eax # 4-byte Reload
movl %eax, 60(%rsp)
leaq 24(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 60(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rdi
leaq 32(%rsp), %rsi
movq %rbx, %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z7upsweepPdS_i, %edi
movq %r12, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_3: # in Loop: Header=BB4_1 Depth=1
callq hipDeviceSynchronize
movq %rbp, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_5
# %bb.4: # in Loop: Header=BB4_1 Depth=1
movq 112(%rsp), %rax
movq 128(%rsp), %rcx
movq %rax, 24(%rsp)
movq %rcx, 16(%rsp)
movq 152(%rsp), %rax # 8-byte Reload
movl %eax, 60(%rsp)
leaq 24(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 60(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rdi
leaq 32(%rsp), %rsi
movq %rbx, %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z7upsweepPdS_i, %edi
movq %r12, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_5: # in Loop: Header=BB4_1 Depth=1
callq hipDeviceSynchronize
movq %rbp, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_7
# %bb.6: # in Loop: Header=BB4_1 Depth=1
movq 128(%rsp), %rax
movq %rax, 24(%rsp)
movq $0, 16(%rsp)
movq 144(%rsp), %rax # 8-byte Reload
movl %eax, 60(%rsp)
leaq 24(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 60(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rdi
leaq 32(%rsp), %rsi
movq %rbx, %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z7upsweepPdS_i, %edi
movq %r12, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_7: # in Loop: Header=BB4_1 Depth=1
callq hipDeviceSynchronize
movq 160(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_9
# %bb.8: # in Loop: Header=BB4_1 Depth=1
movq 128(%rsp), %rax
movq %rax, 24(%rsp)
movq 144(%rsp), %rax # 8-byte Reload
movl %eax, 48(%rsp)
leaq 24(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rdi
leaq 32(%rsp), %rsi
leaq 16(%rsp), %rdx
movq %rbx, %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z14excl_downsweepPdi, %edi
movq %r12, %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_9: # in Loop: Header=BB4_1 Depth=1
callq hipDeviceSynchronize
movq %rbp, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_11
# %bb.10: # in Loop: Header=BB4_1 Depth=1
movq 112(%rsp), %rax
movq %rax, 24(%rsp)
movq 152(%rsp), %rax # 8-byte Reload
movl %eax, 48(%rsp)
leaq 24(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rdi
leaq 32(%rsp), %rsi
leaq 16(%rsp), %rdx
movq %rbx, %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z14excl_downsweepPdi, %edi
movq %r12, %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_11: # in Loop: Header=BB4_1 Depth=1
callq hipDeviceSynchronize
movq %r13, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_13
# %bb.12: # in Loop: Header=BB4_1 Depth=1
movq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 64(%rsp)
movq %r12, %rdi
movq %rsp, %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
movl $_Z14incl_downsweepPd, %edi
movq %rbx, %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_13: # in Loop: Header=BB4_1 Depth=1
callq hipDeviceSynchronize
movq %rbp, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_15
# %bb.14: # in Loop: Header=BB4_1 Depth=1
movq 112(%rsp), %rax
movq 128(%rsp), %rcx
movq %rax, 24(%rsp)
movq %rcx, 16(%rsp)
leaq 24(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rdi
leaq 32(%rsp), %rsi
movq %rbx, %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z13scat_part_sumPdS_, %edi
movq %r12, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_15: # in Loop: Header=BB4_1 Depth=1
callq hipDeviceSynchronize
movq %r13, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_17
# %bb.16: # in Loop: Header=BB4_1 Depth=1
movq 120(%rsp), %rax
movq 112(%rsp), %rcx
movq %rax, 24(%rsp)
movq %rcx, 16(%rsp)
leaq 24(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rdi
leaq 32(%rsp), %rsi
movq %rbx, %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z13scat_part_sumPdS_, %edi
movq %r12, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_17
.LBB4_18:
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z3sumPdS_i, .Lfunc_end4-_Z3sumPdS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB5_1
# %bb.2:
movl $16777216, 4(%rsp) # imm = 0x1000000
movq 8(%rsi), %rdi
movl $.L.str.1, %esi
callq fopen
movl $1, %ebx
testq %rax, %rax
je .LBB5_3
# %bb.4:
movq %rax, %r12
leaq 4(%rsp), %rdx
movl $.L.str.3, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 4(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movslq 4(%rsp), %r13
leaq (,%r13,8), %r15
movq %r15, %rdi
callq malloc
movq %rax, %r14
movq %r15, %rdi
callq malloc
movq %rax, %r15
testq %r13, %r13
jle .LBB5_7
# %bb.5: # %.lr.ph.preheader
movq %r14, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB5_6: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.4, %esi
movq %r12, %rdi
movq %r13, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %rbp
movslq 4(%rsp), %rax
addq $8, %r13
cmpq %rax, %rbp
jl .LBB5_6
.LBB5_7: # %._crit_edge
movq %r12, %rdi
callq fclose
movl 4(%rsp), %edx
movq %r14, %rdi
movq %r15, %rsi
callq _Z3sumPdS_i
movl $.L.str.5, %edi
movl $.L.str.6, %esi
callq fopen
testq %rax, %rax
je .LBB5_8
# %bb.9:
movq %rax, %r12
movl 4(%rsp), %edx
xorl %ebx, %ebx
movl $.L.str.3, %esi
movq %rax, %rdi
xorl %eax, %eax
callq fprintf
cmpl $0, 4(%rsp)
jle .LBB5_12
# %bb.10: # %.lr.ph32.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB5_11: # %.lr.ph32
# =>This Inner Loop Header: Depth=1
movsd (%r15,%r13,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.4, %esi
movq %r12, %rdi
movb $1, %al
callq fprintf
incq %r13
movslq 4(%rsp), %rax
cmpq %rax, %r13
jl .LBB5_11
.LBB5_12: # %._crit_edge33
movq %r12, %rdi
callq fclose
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movl $.Lstr, %edi
jmp .LBB5_13
.LBB5_1:
movl $.Lstr.3, %edi
callq puts@PLT
movl $1, %ebx
jmp .LBB5_14
.LBB5_3:
movl $.Lstr.2, %edi
jmp .LBB5_13
.LBB5_8:
movl $.Lstr.1, %edi
.LBB5_13:
callq puts@PLT
.LBB5_14:
movl %ebx, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13scat_part_sumPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7upsweepPdS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14excl_downsweepPdi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14incl_downsweepPd, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13scat_part_sumPdS_,@object # @_Z13scat_part_sumPdS_
.section .rodata,"a",@progbits
.globl _Z13scat_part_sumPdS_
.p2align 3, 0x0
_Z13scat_part_sumPdS_:
.quad _Z28__device_stub__scat_part_sumPdS_
.size _Z13scat_part_sumPdS_, 8
.type _Z7upsweepPdS_i,@object # @_Z7upsweepPdS_i
.globl _Z7upsweepPdS_i
.p2align 3, 0x0
_Z7upsweepPdS_i:
.quad _Z22__device_stub__upsweepPdS_i
.size _Z7upsweepPdS_i, 8
.type _Z14excl_downsweepPdi,@object # @_Z14excl_downsweepPdi
.globl _Z14excl_downsweepPdi
.p2align 3, 0x0
_Z14excl_downsweepPdi:
.quad _Z29__device_stub__excl_downsweepPdi
.size _Z14excl_downsweepPdi, 8
.type _Z14incl_downsweepPd,@object # @_Z14incl_downsweepPd
.globl _Z14incl_downsweepPd
.p2align 3, 0x0
_Z14incl_downsweepPd:
.quad _Z29__device_stub__incl_downsweepPd
.size _Z14incl_downsweepPd, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d\n"
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%lg\n"
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "output.txt"
.size .L.str.5, 11
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "w"
.size .L.str.6, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13scat_part_sumPdS_"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7upsweepPdS_i"
.size .L__unnamed_2, 16
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z14excl_downsweepPdi"
.size .L__unnamed_3, 22
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z14incl_downsweepPd"
.size .L__unnamed_4, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Done..."
.size .Lstr, 8
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "The file can not be created!"
.size .Lstr.1, 29
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "The file can not be opened or does not exist!"
.size .Lstr.2, 46
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "The argument is wrong! Execute your program with only input file name!"
.size .Lstr.3, 71
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__scat_part_sumPdS_
.addrsig_sym _Z22__device_stub__upsweepPdS_i
.addrsig_sym _Z29__device_stub__excl_downsweepPdi
.addrsig_sym _Z29__device_stub__incl_downsweepPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13scat_part_sumPdS_
.addrsig_sym _Z7upsweepPdS_i
.addrsig_sym _Z14excl_downsweepPdi
.addrsig_sym _Z14incl_downsweepPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00053efb_00000000-6_prefix_sum.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3953:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3953:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z13scat_part_sumPdS_PdS_
.type _Z35__device_stub__Z13scat_part_sumPdS_PdS_, @function
_Z35__device_stub__Z13scat_part_sumPdS_PdS_:
.LFB3975:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13scat_part_sumPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3975:
.size _Z35__device_stub__Z13scat_part_sumPdS_PdS_, .-_Z35__device_stub__Z13scat_part_sumPdS_PdS_
.globl _Z13scat_part_sumPdS_
.type _Z13scat_part_sumPdS_, @function
_Z13scat_part_sumPdS_:
.LFB3976:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13scat_part_sumPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3976:
.size _Z13scat_part_sumPdS_, .-_Z13scat_part_sumPdS_
.globl _Z29__device_stub__Z7upsweepPdS_iPdS_i
.type _Z29__device_stub__Z7upsweepPdS_iPdS_i, @function
_Z29__device_stub__Z7upsweepPdS_iPdS_i:
.LFB3977:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7upsweepPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3977:
.size _Z29__device_stub__Z7upsweepPdS_iPdS_i, .-_Z29__device_stub__Z7upsweepPdS_iPdS_i
.globl _Z7upsweepPdS_i
.type _Z7upsweepPdS_i, @function
_Z7upsweepPdS_i:
.LFB3978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7upsweepPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3978:
.size _Z7upsweepPdS_i, .-_Z7upsweepPdS_i
.globl _Z35__device_stub__Z14excl_downsweepPdiPdi
.type _Z35__device_stub__Z14excl_downsweepPdiPdi, @function
_Z35__device_stub__Z14excl_downsweepPdiPdi:
.LFB3979:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14excl_downsweepPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3979:
.size _Z35__device_stub__Z14excl_downsweepPdiPdi, .-_Z35__device_stub__Z14excl_downsweepPdiPdi
.globl _Z14excl_downsweepPdi
.type _Z14excl_downsweepPdi, @function
_Z14excl_downsweepPdi:
.LFB3980:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z14excl_downsweepPdiPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3980:
.size _Z14excl_downsweepPdi, .-_Z14excl_downsweepPdi
.globl _Z34__device_stub__Z14incl_downsweepPdPd
.type _Z34__device_stub__Z14incl_downsweepPdPd, @function
_Z34__device_stub__Z14incl_downsweepPdPd:
.LFB3981:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14incl_downsweepPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3981:
.size _Z34__device_stub__Z14incl_downsweepPdPd, .-_Z34__device_stub__Z14incl_downsweepPdPd
.globl _Z14incl_downsweepPd
.type _Z14incl_downsweepPd, @function
_Z14incl_downsweepPd:
.LFB3982:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z14incl_downsweepPdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3982:
.size _Z14incl_downsweepPd, .-_Z14incl_downsweepPd
.globl _Z3sumPdS_i
.type _Z3sumPdS_i, @function
_Z3sumPdS_i:
.LFB3949:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %r12
movq %rsi, 8(%rsp)
movl %edx, %r14d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L36
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L36:
cvttsd2sil %xmm3, %ebp
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L37
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L37:
cvttsd2sil %xmm3, %ebx
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L38
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L38:
cvttsd2sil %xmm3, %r15d
movslq %r14d, %r13
salq $3, %r13
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movslq %ebp, %rsi
salq $3, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movslq %ebx, %rsi
salq $3, %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %r12d
.L47:
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %ebp, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L39:
call cudaDeviceSynchronize@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %ebx, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L40:
call cudaDeviceSynchronize@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %ebx, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L41:
call cudaDeviceSynchronize@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %r15d, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L42:
call cudaDeviceSynchronize@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %ebx, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L43:
call cudaDeviceSynchronize@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %ebp, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L56
.L44:
call cudaDeviceSynchronize@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %ebx, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L57
.L45:
call cudaDeviceSynchronize@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %ebp, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L58
.L46:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
subl $1, %r12d
jne .L47
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L59
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
movl %r14d, %edx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z29__device_stub__Z7upsweepPdS_iPdS_i
jmp .L39
.L52:
movl %ebp, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z29__device_stub__Z7upsweepPdS_iPdS_i
jmp .L40
.L53:
movl %ebx, %edx
movl $0, %esi
movq 40(%rsp), %rdi
call _Z29__device_stub__Z7upsweepPdS_iPdS_i
jmp .L41
.L54:
movl %ebx, %esi
movq 40(%rsp), %rdi
call _Z35__device_stub__Z14excl_downsweepPdiPdi
jmp .L42
.L55:
movl %ebp, %esi
movq 32(%rsp), %rdi
call _Z35__device_stub__Z14excl_downsweepPdiPdi
jmp .L43
.L56:
movq 24(%rsp), %rdi
call _Z34__device_stub__Z14incl_downsweepPdPd
jmp .L44
.L57:
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z35__device_stub__Z13scat_part_sumPdS_PdS_
jmp .L45
.L58:
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z35__device_stub__Z13scat_part_sumPdS_PdS_
jmp .L46
.L59:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3949:
.size _Z3sumPdS_i, .-_Z3sumPdS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "The argument is wrong! Execute your program with only input file name!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "r"
.section .rodata.str1.8
.align 8
.LC7:
.string "The file can not be opened or does not exist!\n"
.section .rodata.str1.1
.LC8:
.string "%d\n"
.LC9:
.string "%lg\n"
.LC10:
.string "w"
.LC11:
.string "output.txt"
.LC12:
.string "The file can not be created!\n"
.LC13:
.string "Done...\n"
.text
.globl main
.type main, @function
main:
.LFB3950:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L61
leaq .LC5(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %eax
.L60:
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L73
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
movl $16777216, 4(%rsp)
movq 8(%rsi), %rdi
leaq .LC6(%rip), %rsi
call fopen@PLT
movq %rax, %r12
testq %rax, %rax
je .L74
leaq 4(%rsp), %rdx
leaq .LC8(%rip), %rbx
movq %rbx, %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 4(%rsp), %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 4(%rsp), %ebp
movslq %ebp, %rbx
salq $3, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
testl %ebp, %ebp
jle .L64
movq %r14, %rbp
movl $0, %ebx
leaq .LC9(%rip), %r15
.L65:
movq %rbp, %rdx
movq %r15, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebx
addq $8, %rbp
cmpl %ebx, 4(%rsp)
jg .L65
.L64:
movq %r12, %rdi
call fclose@PLT
movl 4(%rsp), %edx
movq %r13, %rsi
movq %r14, %rdi
call _Z3sumPdS_i
leaq .LC10(%rip), %rsi
leaq .LC11(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
testq %rax, %rax
je .L75
movl 4(%rsp), %ecx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
cmpl $0, 4(%rsp)
jle .L67
movl $0, %ebx
leaq .LC9(%rip), %r12
.L68:
movsd 0(%r13,%rbx,8), %xmm0
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpl %ebx, 4(%rsp)
jg .L68
.L67:
movq %rbp, %rdi
call fclose@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L60
.L74:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L60
.L75:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L60
.L73:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3950:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z14incl_downsweepPd"
.LC15:
.string "_Z14excl_downsweepPdi"
.LC16:
.string "_Z7upsweepPdS_i"
.LC17:
.string "_Z13scat_part_sumPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3984:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z14incl_downsweepPd(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z14excl_downsweepPdi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z7upsweepPdS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z13scat_part_sumPdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3984:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1062207488
.align 8
.LC1:
.long 0
.long 1127219200
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC4:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "prefix_sum.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__scat_part_sumPdS_ # -- Begin function _Z28__device_stub__scat_part_sumPdS_
.p2align 4, 0x90
.type _Z28__device_stub__scat_part_sumPdS_,@function
_Z28__device_stub__scat_part_sumPdS_: # @_Z28__device_stub__scat_part_sumPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13scat_part_sumPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__scat_part_sumPdS_, .Lfunc_end0-_Z28__device_stub__scat_part_sumPdS_
.cfi_endproc
# -- End function
.globl _Z22__device_stub__upsweepPdS_i # -- Begin function _Z22__device_stub__upsweepPdS_i
.p2align 4, 0x90
.type _Z22__device_stub__upsweepPdS_i,@function
_Z22__device_stub__upsweepPdS_i: # @_Z22__device_stub__upsweepPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7upsweepPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z22__device_stub__upsweepPdS_i, .Lfunc_end1-_Z22__device_stub__upsweepPdS_i
.cfi_endproc
# -- End function
.globl _Z29__device_stub__excl_downsweepPdi # -- Begin function _Z29__device_stub__excl_downsweepPdi
.p2align 4, 0x90
.type _Z29__device_stub__excl_downsweepPdi,@function
_Z29__device_stub__excl_downsweepPdi: # @_Z29__device_stub__excl_downsweepPdi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14excl_downsweepPdi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z29__device_stub__excl_downsweepPdi, .Lfunc_end2-_Z29__device_stub__excl_downsweepPdi
.cfi_endproc
# -- End function
.globl _Z29__device_stub__incl_downsweepPd # -- Begin function _Z29__device_stub__incl_downsweepPd
.p2align 4, 0x90
.type _Z29__device_stub__incl_downsweepPd,@function
_Z29__device_stub__incl_downsweepPd: # @_Z29__device_stub__incl_downsweepPd
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z14incl_downsweepPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z29__device_stub__incl_downsweepPd, .Lfunc_end3-_Z29__device_stub__incl_downsweepPd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z3sumPdS_i
.LCPI4_0:
.quad 0x3f50000000000000 # double 9.765625E-4
.text
.globl _Z3sumPdS_i
.p2align 4, 0x90
.type _Z3sumPdS_i,@function
_Z3sumPdS_i: # @_Z3sumPdS_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, 176(%rsp) # 8-byte Spill
movq %rdi, %r13
movabsq $4294968320, %r15 # imm = 0x100000400
cvtsi2sd %edx, %xmm0
mulsd .LCPI4_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r12d
cvttpd2dq %xmm0, %xmm0
cvtdq2pd %xmm0, %xmm0
mulsd .LCPI4_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %ebx
cvttpd2dq %xmm0, %xmm0
cvtdq2pd %xmm0, %xmm0
mulsd .LCPI4_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r14d
movl %ebp, 140(%rsp) # 4-byte Spill
movslq %ebp, %rbp
shlq $3, %rbp
leaq 120(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movslq %r12d, %rsi
shlq $3, %rsi
leaq 112(%rsp), %rdi
callq hipMalloc
movslq %ebx, %rsi
shlq $3, %rsi
leaq 128(%rsp), %rdi
callq hipMalloc
movq 120(%rsp), %rdi
movq %r13, %rsi
movq %rbp, 168(%rsp) # 8-byte Spill
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r12, 152(%rsp) # 8-byte Spill
leaq (%r12,%r15), %r13
addq $-1024, %r13 # imm = 0xFC00
movq %rbx, 144(%rsp) # 8-byte Spill
leaq -1024(%rbx,%r15), %rbp
leaq -1024(%r14,%r15), %rax
movq %rax, 160(%rsp) # 8-byte Spill
movl $2, %r14d
leaq 64(%rsp), %rbx
leaq 80(%rsp), %r12
jmp .LBB4_1
.p2align 4, 0x90
.LBB4_17: # in Loop: Header=BB4_1 Depth=1
callq hipDeviceSynchronize
movq 120(%rsp), %rsi
movq 176(%rsp), %rdi # 8-byte Reload
movq 168(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
decl %r14d
je .LBB4_18
.LBB4_1: # =>This Inner Loop Header: Depth=1
movq %r13, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_3
# %bb.2: # in Loop: Header=BB4_1 Depth=1
movq 120(%rsp), %rax
movq 112(%rsp), %rcx
movq %rax, 24(%rsp)
movq %rcx, 16(%rsp)
movl 140(%rsp), %eax # 4-byte Reload
movl %eax, 60(%rsp)
leaq 24(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 60(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rdi
leaq 32(%rsp), %rsi
movq %rbx, %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z7upsweepPdS_i, %edi
movq %r12, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_3: # in Loop: Header=BB4_1 Depth=1
callq hipDeviceSynchronize
movq %rbp, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_5
# %bb.4: # in Loop: Header=BB4_1 Depth=1
movq 112(%rsp), %rax
movq 128(%rsp), %rcx
movq %rax, 24(%rsp)
movq %rcx, 16(%rsp)
movq 152(%rsp), %rax # 8-byte Reload
movl %eax, 60(%rsp)
leaq 24(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 60(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rdi
leaq 32(%rsp), %rsi
movq %rbx, %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z7upsweepPdS_i, %edi
movq %r12, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_5: # in Loop: Header=BB4_1 Depth=1
callq hipDeviceSynchronize
movq %rbp, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_7
# %bb.6: # in Loop: Header=BB4_1 Depth=1
movq 128(%rsp), %rax
movq %rax, 24(%rsp)
movq $0, 16(%rsp)
movq 144(%rsp), %rax # 8-byte Reload
movl %eax, 60(%rsp)
leaq 24(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 60(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rdi
leaq 32(%rsp), %rsi
movq %rbx, %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z7upsweepPdS_i, %edi
movq %r12, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_7: # in Loop: Header=BB4_1 Depth=1
callq hipDeviceSynchronize
movq 160(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_9
# %bb.8: # in Loop: Header=BB4_1 Depth=1
movq 128(%rsp), %rax
movq %rax, 24(%rsp)
movq 144(%rsp), %rax # 8-byte Reload
movl %eax, 48(%rsp)
leaq 24(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rdi
leaq 32(%rsp), %rsi
leaq 16(%rsp), %rdx
movq %rbx, %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z14excl_downsweepPdi, %edi
movq %r12, %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_9: # in Loop: Header=BB4_1 Depth=1
callq hipDeviceSynchronize
movq %rbp, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_11
# %bb.10: # in Loop: Header=BB4_1 Depth=1
movq 112(%rsp), %rax
movq %rax, 24(%rsp)
movq 152(%rsp), %rax # 8-byte Reload
movl %eax, 48(%rsp)
leaq 24(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rdi
leaq 32(%rsp), %rsi
leaq 16(%rsp), %rdx
movq %rbx, %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z14excl_downsweepPdi, %edi
movq %r12, %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_11: # in Loop: Header=BB4_1 Depth=1
callq hipDeviceSynchronize
movq %r13, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_13
# %bb.12: # in Loop: Header=BB4_1 Depth=1
movq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 64(%rsp)
movq %r12, %rdi
movq %rsp, %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
movl $_Z14incl_downsweepPd, %edi
movq %rbx, %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_13: # in Loop: Header=BB4_1 Depth=1
callq hipDeviceSynchronize
movq %rbp, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_15
# %bb.14: # in Loop: Header=BB4_1 Depth=1
movq 112(%rsp), %rax
movq 128(%rsp), %rcx
movq %rax, 24(%rsp)
movq %rcx, 16(%rsp)
leaq 24(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rdi
leaq 32(%rsp), %rsi
movq %rbx, %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z13scat_part_sumPdS_, %edi
movq %r12, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_15: # in Loop: Header=BB4_1 Depth=1
callq hipDeviceSynchronize
movq %r13, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_17
# %bb.16: # in Loop: Header=BB4_1 Depth=1
movq 120(%rsp), %rax
movq 112(%rsp), %rcx
movq %rax, 24(%rsp)
movq %rcx, 16(%rsp)
leaq 24(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rdi
leaq 32(%rsp), %rsi
movq %rbx, %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z13scat_part_sumPdS_, %edi
movq %r12, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_17
.LBB4_18:
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z3sumPdS_i, .Lfunc_end4-_Z3sumPdS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB5_1
# %bb.2:
movl $16777216, 4(%rsp) # imm = 0x1000000
movq 8(%rsi), %rdi
movl $.L.str.1, %esi
callq fopen
movl $1, %ebx
testq %rax, %rax
je .LBB5_3
# %bb.4:
movq %rax, %r12
leaq 4(%rsp), %rdx
movl $.L.str.3, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 4(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movslq 4(%rsp), %r13
leaq (,%r13,8), %r15
movq %r15, %rdi
callq malloc
movq %rax, %r14
movq %r15, %rdi
callq malloc
movq %rax, %r15
testq %r13, %r13
jle .LBB5_7
# %bb.5: # %.lr.ph.preheader
movq %r14, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB5_6: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.4, %esi
movq %r12, %rdi
movq %r13, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %rbp
movslq 4(%rsp), %rax
addq $8, %r13
cmpq %rax, %rbp
jl .LBB5_6
.LBB5_7: # %._crit_edge
movq %r12, %rdi
callq fclose
movl 4(%rsp), %edx
movq %r14, %rdi
movq %r15, %rsi
callq _Z3sumPdS_i
movl $.L.str.5, %edi
movl $.L.str.6, %esi
callq fopen
testq %rax, %rax
je .LBB5_8
# %bb.9:
movq %rax, %r12
movl 4(%rsp), %edx
xorl %ebx, %ebx
movl $.L.str.3, %esi
movq %rax, %rdi
xorl %eax, %eax
callq fprintf
cmpl $0, 4(%rsp)
jle .LBB5_12
# %bb.10: # %.lr.ph32.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB5_11: # %.lr.ph32
# =>This Inner Loop Header: Depth=1
movsd (%r15,%r13,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.4, %esi
movq %r12, %rdi
movb $1, %al
callq fprintf
incq %r13
movslq 4(%rsp), %rax
cmpq %rax, %r13
jl .LBB5_11
.LBB5_12: # %._crit_edge33
movq %r12, %rdi
callq fclose
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movl $.Lstr, %edi
jmp .LBB5_13
.LBB5_1:
movl $.Lstr.3, %edi
callq puts@PLT
movl $1, %ebx
jmp .LBB5_14
.LBB5_3:
movl $.Lstr.2, %edi
jmp .LBB5_13
.LBB5_8:
movl $.Lstr.1, %edi
.LBB5_13:
callq puts@PLT
.LBB5_14:
movl %ebx, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13scat_part_sumPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7upsweepPdS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14excl_downsweepPdi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14incl_downsweepPd, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13scat_part_sumPdS_,@object # @_Z13scat_part_sumPdS_
.section .rodata,"a",@progbits
.globl _Z13scat_part_sumPdS_
.p2align 3, 0x0
_Z13scat_part_sumPdS_:
.quad _Z28__device_stub__scat_part_sumPdS_
.size _Z13scat_part_sumPdS_, 8
.type _Z7upsweepPdS_i,@object # @_Z7upsweepPdS_i
.globl _Z7upsweepPdS_i
.p2align 3, 0x0
_Z7upsweepPdS_i:
.quad _Z22__device_stub__upsweepPdS_i
.size _Z7upsweepPdS_i, 8
.type _Z14excl_downsweepPdi,@object # @_Z14excl_downsweepPdi
.globl _Z14excl_downsweepPdi
.p2align 3, 0x0
_Z14excl_downsweepPdi:
.quad _Z29__device_stub__excl_downsweepPdi
.size _Z14excl_downsweepPdi, 8
.type _Z14incl_downsweepPd,@object # @_Z14incl_downsweepPd
.globl _Z14incl_downsweepPd
.p2align 3, 0x0
_Z14incl_downsweepPd:
.quad _Z29__device_stub__incl_downsweepPd
.size _Z14incl_downsweepPd, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d\n"
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%lg\n"
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "output.txt"
.size .L.str.5, 11
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "w"
.size .L.str.6, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13scat_part_sumPdS_"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7upsweepPdS_i"
.size .L__unnamed_2, 16
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z14excl_downsweepPdi"
.size .L__unnamed_3, 22
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z14incl_downsweepPd"
.size .L__unnamed_4, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Done..."
.size .Lstr, 8
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "The file can not be created!"
.size .Lstr.1, 29
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "The file can not be opened or does not exist!"
.size .Lstr.2, 46
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "The argument is wrong! Execute your program with only input file name!"
.size .Lstr.3, 71
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__scat_part_sumPdS_
.addrsig_sym _Z22__device_stub__upsweepPdS_i
.addrsig_sym _Z29__device_stub__excl_downsweepPdi
.addrsig_sym _Z29__device_stub__incl_downsweepPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13scat_part_sumPdS_
.addrsig_sym _Z7upsweepPdS_i
.addrsig_sym _Z14excl_downsweepPdi
.addrsig_sym _Z14incl_downsweepPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Esercizio
// Come il precedente ma 2D
// Dato array 2D di NxM interi e un valore intero x conta quanti sono gli elementi di uguali a x
//
// x e N forniti da linea di comando // TODO
// Variante
// Usare grid 2D // TODO
#include <locale>
#include <stdlib.h>
#include <iostream>
#include <experimental/random>
#include <time.h>
#define N 60 // 3 // Rows
#define M 70 // 4 // Cols
#define THREADS_PER_BLOCK 256
#define MAX_VAL 5 // 50
static void HandleError( cudaError_t err, const char *file, int line) {
if (err != cudaSuccess) {
std::cout << cudaGetErrorString( err ) << " in " << file << " line " << line << std::endl;
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err)(HandleError(err, __FILE__, __LINE__))
void init_vec(int v[N][M]) {
for (int i=0; i<N; i++) {
for (int j=0; j<M; j++) {
v[i][j] = std::experimental::randint(0,MAX_VAL);
//std::cout << "i = " << i << "\tj = " << j << std::endl;
//std::cout << "v[i][j] = "<< v[i][j] << std::endl;
//v[i][j] = 0;
//v[i][j] = i*M + j;
//std::cout << "v[i][j] = "<< v[i][j] << "\n" << std::endl;
}
}
}
void show_vec(int v[N][M]) {
std::cout << "[\n";
for (int i=0; i<N; i++) {
for (int j=0; j<M; j++) {
std::cout << v[i][j] << ", ";
}
std::cout << "\n";
}
std::cout << "]\n" << std::endl;
}
int cpu_count(int v[N][M], const int x) {
int c=0;
for (int i=0; i<N; i++) {
for (int j=0; j<M; j++) {
if (v[i][j] == x)
c++;
}
}
return c;
}
int div_ceil(int numerator, int denominator) {
std::div_t res = std::div(numerator, denominator);
return res.rem ? (res.quot + 1) : res.quot;
}
int compute_num_blocks(const int n, const int m) {
int b = div_ceil(n*m, THREADS_PER_BLOCK);
return b;
}
__device__ int d_g_count = 0;
__global__ void gpu_count(int *d_v, const int x) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid >= N*M)
return;
if (d_v[tid] == x) {
atomicAdd(&d_g_count, 1);
printf("%d\t%d - Increment\n", tid, d_v[tid]);
} else {
printf("%d\t%d\n", tid, d_v[tid]);
}
}
int main( void ) {
size_t vec_size = ((size_t)N*M) * sizeof(int);
//std::cout << "N = " << N << std::endl;
//std::cout << "sizeof(int) = " << sizeof(int) << std::endl;
//std::cout << "size = " << vec_size << std::endl;
int seed = (int)time(NULL);
//std::experimental::reseed(3);
std::experimental::reseed(seed);
std::cout << "seed = " << seed << std::endl;
int x;
x = std::experimental::randint(0,MAX_VAL);
//x = N-1; // x is in the last block
int v[N][M];
//int *v;
//v = (int*)malloc(vec_size);
init_vec(v);
show_vec(v);
int *dev_v;
HANDLE_ERROR(cudaMalloc((void**)&dev_v, vec_size));
HANDLE_ERROR(cudaMemcpy(dev_v, v, vec_size, cudaMemcpyHostToDevice));
int g_count=0;
int b = compute_num_blocks(N,M);
std::cout <<
"\nN = " << N <<
"\nM = " << M <<
"\nN*M = " << N*M <<
"\nthreads = " << THREADS_PER_BLOCK <<
"\nb = " << b <<
"\nb*threads = " << b*THREADS_PER_BLOCK << "\n" <<
std::endl;
gpu_count<<<b, THREADS_PER_BLOCK>>>(dev_v, x);
HANDLE_ERROR(cudaDeviceSynchronize());
HANDLE_ERROR(cudaMemcpyFromSymbol(&g_count, d_g_count, sizeof(int))); // better than cudaMemcpy // Look at ref in README
int c_count = cpu_count(v,x);
std::cout << "\nx = " << x << "\tMAX_VAL = " << MAX_VAL << "\n" << std::endl;
std::cout << "c_count = " << c_count << std::endl;
std::cout << "g_count = " << g_count << std::endl;
if (c_count == g_count)
std::cout << "\nCorrect" << std::endl;
else
std::cout << "\nWRONG!" << std::endl;
cudaFree(&d_g_count);
cudaFree(dev_v);
//free(v);
return 0;
} | code for sm_80
Function : _Z9gpu_countPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GT.AND P0, PT, R2, 0x1067, PT ; /* 0x000010670200780c */
/* 0x000fda0003f04270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE R8, R2, R9, c[0x0][0x160] ; /* 0x0000580002087625 */
/* 0x000fca00078e0209 */
/*00a0*/ LDG.E R3, [R8.64] ; /* 0x0000002408037981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fca0007f3e0ff */
/*00c0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fe200008e06ff */
/*00d0*/ ISETP.NE.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x004fda0003f05270 */
/*00e0*/ @!P0 BRA 0x1d0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*00f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0100*/ STL.64 [R1], R2 ; /* 0x0000000201007387 */
/* 0x0001e20000100a00 */
/*0110*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x18] ; /* 0x01000600ff047624 */
/* 0x000fe400078e00ff */
/*0120*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0000620000000a00 */
/*0130*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x1c] ; /* 0x01000700ff057624 */
/* 0x000fce00078e00ff */
/*0140*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x001fe20000000000 */
/*0150*/ MOV R11, 0x1c0 ; /* 0x000001c0000b7802 */
/* 0x000fe40000000f00 */
/*0160*/ MOV R20, 0x140 ; /* 0x0000014000147802 */
/* 0x000fe40000000f00 */
/*0170*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*0180*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0190*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*01a0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*01b0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x002fea0003c00000 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*01e0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*01f0*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff0a7624 */
/* 0x000fe200078e00ff */
/*0200*/ UFLO.U32 UR5, UR4 ; /* 0x00000004000572bd */
/* 0x000fe200080e0000 */
/*0210*/ POPC R13, UR4 ; /* 0x00000004000d7d09 */
/* 0x000e620008000000 */
/*0220*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff0b7624 */
/* 0x000fc800078e00ff */
/*0230*/ ISETP.EQ.U32.AND P0, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x001fda000bf02070 */
/*0240*/ @P0 RED.E.ADD.STRONG.GPU [R10.64], R13 ; /* 0x0000000d0a00098e */
/* 0x0021e8000c10e1a4 */
/*0250*/ LDG.E R15, [R8.64] ; /* 0x00000024080f7981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD.MOV.U32 R14, RZ, RZ, R2 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0002 */
/*0270*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0280*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*0290*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fc600078e00ff */
/*02a0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e620000000a00 */
/*02b0*/ STL.64 [R1], R14 ; /* 0x0000000e01007387 */
/* 0x0041e60000100a00 */
/*02c0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fe20000000000 */
/*02d0*/ MOV R11, 0x340 ; /* 0x00000340000b7802 */
/* 0x001fe40000000f00 */
/*02e0*/ MOV R20, 0x2c0 ; /* 0x000002c000147802 */
/* 0x000fe40000000f00 */
/*02f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0300*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0310*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0320*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0330*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*0340*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0350*/ BRA 0x350; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Esercizio
// Come il precedente ma 2D
// Dato array 2D di NxM interi e un valore intero x conta quanti sono gli elementi di uguali a x
//
// x e N forniti da linea di comando // TODO
// Variante
// Usare grid 2D // TODO
#include <locale>
#include <stdlib.h>
#include <iostream>
#include <experimental/random>
#include <time.h>
#define N 60 // 3 // Rows
#define M 70 // 4 // Cols
#define THREADS_PER_BLOCK 256
#define MAX_VAL 5 // 50
static void HandleError( cudaError_t err, const char *file, int line) {
if (err != cudaSuccess) {
std::cout << cudaGetErrorString( err ) << " in " << file << " line " << line << std::endl;
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err)(HandleError(err, __FILE__, __LINE__))
void init_vec(int v[N][M]) {
for (int i=0; i<N; i++) {
for (int j=0; j<M; j++) {
v[i][j] = std::experimental::randint(0,MAX_VAL);
//std::cout << "i = " << i << "\tj = " << j << std::endl;
//std::cout << "v[i][j] = "<< v[i][j] << std::endl;
//v[i][j] = 0;
//v[i][j] = i*M + j;
//std::cout << "v[i][j] = "<< v[i][j] << "\n" << std::endl;
}
}
}
void show_vec(int v[N][M]) {
std::cout << "[\n";
for (int i=0; i<N; i++) {
for (int j=0; j<M; j++) {
std::cout << v[i][j] << ", ";
}
std::cout << "\n";
}
std::cout << "]\n" << std::endl;
}
int cpu_count(int v[N][M], const int x) {
int c=0;
for (int i=0; i<N; i++) {
for (int j=0; j<M; j++) {
if (v[i][j] == x)
c++;
}
}
return c;
}
int div_ceil(int numerator, int denominator) {
std::div_t res = std::div(numerator, denominator);
return res.rem ? (res.quot + 1) : res.quot;
}
int compute_num_blocks(const int n, const int m) {
int b = div_ceil(n*m, THREADS_PER_BLOCK);
return b;
}
__device__ int d_g_count = 0;
__global__ void gpu_count(int *d_v, const int x) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid >= N*M)
return;
if (d_v[tid] == x) {
atomicAdd(&d_g_count, 1);
printf("%d\t%d - Increment\n", tid, d_v[tid]);
} else {
printf("%d\t%d\n", tid, d_v[tid]);
}
}
int main( void ) {
size_t vec_size = ((size_t)N*M) * sizeof(int);
//std::cout << "N = " << N << std::endl;
//std::cout << "sizeof(int) = " << sizeof(int) << std::endl;
//std::cout << "size = " << vec_size << std::endl;
int seed = (int)time(NULL);
//std::experimental::reseed(3);
std::experimental::reseed(seed);
std::cout << "seed = " << seed << std::endl;
int x;
x = std::experimental::randint(0,MAX_VAL);
//x = N-1; // x is in the last block
int v[N][M];
//int *v;
//v = (int*)malloc(vec_size);
init_vec(v);
show_vec(v);
int *dev_v;
HANDLE_ERROR(cudaMalloc((void**)&dev_v, vec_size));
HANDLE_ERROR(cudaMemcpy(dev_v, v, vec_size, cudaMemcpyHostToDevice));
int g_count=0;
int b = compute_num_blocks(N,M);
std::cout <<
"\nN = " << N <<
"\nM = " << M <<
"\nN*M = " << N*M <<
"\nthreads = " << THREADS_PER_BLOCK <<
"\nb = " << b <<
"\nb*threads = " << b*THREADS_PER_BLOCK << "\n" <<
std::endl;
gpu_count<<<b, THREADS_PER_BLOCK>>>(dev_v, x);
HANDLE_ERROR(cudaDeviceSynchronize());
HANDLE_ERROR(cudaMemcpyFromSymbol(&g_count, d_g_count, sizeof(int))); // better than cudaMemcpy // Look at ref in README
int c_count = cpu_count(v,x);
std::cout << "\nx = " << x << "\tMAX_VAL = " << MAX_VAL << "\n" << std::endl;
std::cout << "c_count = " << c_count << std::endl;
std::cout << "g_count = " << g_count << std::endl;
if (c_count == g_count)
std::cout << "\nCorrect" << std::endl;
else
std::cout << "\nWRONG!" << std::endl;
cudaFree(&d_g_count);
cudaFree(dev_v);
//free(v);
return 0;
} | .file "tmpxft_000b6f11_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " in "
.LC1:
.string " line "
#NO_APP
.text
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB4944:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbp
movl %edx, %ebx
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE4944:
.size _ZL11HandleError9cudaErrorPKci, .-_ZL11HandleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4953:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4953:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1
.LC2:
.string "[\n"
.LC3:
.string ", "
.LC4:
.string "\n"
.LC5:
.string "]\n"
.text
.globl _Z8show_vecPA70_i
.type _Z8show_vecPA70_i, @function
_Z8show_vecPA70_i:
.LFB4946:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r14
movl $2, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
leaq 280(%r14), %rbp
addq $17080, %r14
leaq _ZSt4cout(%rip), %r12
leaq .LC3(%rip), %r13
leaq .LC4(%rip), %r15
.L10:
leaq -280(%rbp), %rbx
.L11:
movl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $2, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L11
movl $1, %edx
movq %r15, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $280, %rbp
cmpq %rbp, %r14
jne .L10
movl $2, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L18
cmpb $0, 56(%rbx)
je .L14
movzbl 67(%rbx), %eax
.L15:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L14:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L15
.cfi_endproc
.LFE4946:
.size _Z8show_vecPA70_i, .-_Z8show_vecPA70_i
.globl _Z9cpu_countPA70_ii
.type _Z9cpu_countPA70_ii, @function
_Z9cpu_countPA70_ii:
.LFB4947:
.cfi_startproc
endbr64
movq %rdi, %r8
movl %esi, %edi
leaq 280(%r8), %rsi
addq $17080, %r8
movl $0, %edx
.L20:
leaq -280(%rsi), %rax
.L22:
cmpl %edi, (%rax)
sete %cl
movzbl %cl, %ecx
addl %ecx, %edx
addq $4, %rax
cmpq %rsi, %rax
jne .L22
addq $280, %rsi
cmpq %r8, %rsi
jne .L20
movl %edx, %eax
ret
.cfi_endproc
.LFE4947:
.size _Z9cpu_countPA70_ii, .-_Z9cpu_countPA70_ii
.globl _Z8div_ceilii
.type _Z8div_ceilii, @function
_Z8div_ceilii:
.LFB4948:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call div@PLT
movq %rax, %rdx
sarq $32, %rdx
cmpl $1, %edx
sbbl $-1, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4948:
.size _Z8div_ceilii, .-_Z8div_ceilii
.globl _Z18compute_num_blocksii
.type _Z18compute_num_blocksii, @function
_Z18compute_num_blocksii:
.LFB4949:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
imull %esi, %edi
movl $256, %esi
call _Z8div_ceilii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4949:
.size _Z18compute_num_blocksii, .-_Z18compute_num_blocksii
.globl _Z29__device_stub__Z9gpu_countPiiPii
.type _Z29__device_stub__Z9gpu_countPiiPii, @function
_Z29__device_stub__Z9gpu_countPiiPii:
.LFB4975:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9gpu_countPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L30
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4975:
.size _Z29__device_stub__Z9gpu_countPiiPii, .-_Z29__device_stub__Z9gpu_countPiiPii
.globl _Z9gpu_countPii
.type _Z9gpu_countPii, @function
_Z9gpu_countPii:
.LFB4976:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z9gpu_countPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4976:
.size _Z9gpu_countPii, .-_Z9gpu_countPii
.section .rodata.str1.1
.LC6:
.string "_Z9gpu_countPii"
.LC7:
.string "d_g_count"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4978:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z9gpu_countPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9d_g_count(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4978:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag:
.LFB5394:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
subq %rsi, %rdx
movq %rdx, %rbp
movq %rdx, (%rsp)
cmpq $15, %rdx
ja .L47
movq (%rdi), %rdi
cmpq $1, %rdx
jne .L43
movzbl (%rsi), %eax
movb %al, (%rdi)
.L44:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
movq %rsp, %rsi
movl $0, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %rdi
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L42:
movq %rbp, %rdx
movq %r12, %rsi
call memcpy@PLT
jmp .L44
.L43:
testq %rdx, %rdx
je .L44
jmp .L42
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5394:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.section .rodata._ZNSt12experimental15fundamentals_v217_S_randint_engineEv.str1.1,"aMS",@progbits,1
.LC8:
.string "default"
.section .text._ZNSt12experimental15fundamentals_v217_S_randint_engineEv,"axG",@progbits,_ZNSt12experimental15fundamentals_v217_S_randint_engineEv,comdat
.weak _ZNSt12experimental15fundamentals_v217_S_randint_engineEv
.type _ZNSt12experimental15fundamentals_v217_S_randint_engineEv, @function
_ZNSt12experimental15fundamentals_v217_S_randint_engineEv:
.LFB4940:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4940
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $4096, %rsp
.cfi_def_cfa_offset 4112
orq $0, (%rsp)
subq $944, %rsp
.cfi_def_cfa_offset 5056
movq %fs:40, %rax
movq %rax, 5032(%rsp)
xorl %eax, %eax
cmpb $0, %fs:_ZGVZNSt12experimental15fundamentals_v217_S_randint_engineEvE5__eng@tpoff
je .L62
.L50:
movq %fs:0, %rax
addq $_ZZNSt12experimental15fundamentals_v217_S_randint_engineEvE5__eng@tpoff, %rax
movq 5032(%rsp), %rdx
subq %fs:40, %rdx
jne .L63
addq $5040, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L62:
.cfi_restore_state
movq %rsp, %rbx
leaq 16(%rsp), %rax
movq %rax, (%rsp)
leaq 7+.LC8(%rip), %rdx
leaq -7(%rdx), %rsi
movq %rbx, %rdi
.LEHB0:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE0:
leaq 32(%rsp), %rdi
movq %rbx, %rsi
.LEHB1:
call _ZNSt13random_device7_M_initERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@PLT
.LEHE1:
movq (%rsp), %rdi
leaq 16(%rsp), %rax
cmpq %rax, %rdi
je .L51
movq 16(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L51:
leaq 32(%rsp), %rdi
.LEHB2:
call _ZNSt13random_device9_M_getvalEv@PLT
.LEHE2:
movl %eax, %ecx
movabsq $8589934597, %rdx
movq %rcx, %rax
mulq %rdx
movq %rcx, %rax
subq %rdx, %rax
shrq %rax
addq %rax, %rdx
shrq $30, %rdx
movq %rdx, %rax
salq $31, %rax
subq %rdx, %rax
subq %rax, %rcx
movl $1, %eax
cmove %rax, %rcx
movq %rcx, %fs:_ZZNSt12experimental15fundamentals_v217_S_randint_engineEvE5__eng@tpoff
movb $1, %fs:_ZGVZNSt12experimental15fundamentals_v217_S_randint_engineEvE5__eng@tpoff
leaq 32(%rsp), %rdi
call _ZNSt13random_device7_M_finiEv@PLT
jmp .L50
.L59:
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 5032(%rsp), %rax
subq %fs:40, %rax
je .L54
call __stack_chk_fail@PLT
.L54:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L58:
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZNSt13random_device7_M_finiEv@PLT
movq 5032(%rsp), %rax
subq %fs:40, %rax
je .L56
call __stack_chk_fail@PLT
.L56:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L63:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4940:
.globl __gxx_personality_v0
.section .gcc_except_table._ZNSt12experimental15fundamentals_v217_S_randint_engineEv,"aG",@progbits,_ZNSt12experimental15fundamentals_v217_S_randint_engineEv,comdat
.LLSDA4940:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4940-.LLSDACSB4940
.LLSDACSB4940:
.uleb128 .LEHB0-.LFB4940
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4940
.uleb128 .LEHE1-.LEHB1
.uleb128 .L59-.LFB4940
.uleb128 0
.uleb128 .LEHB2-.LFB4940
.uleb128 .LEHE2-.LEHB2
.uleb128 .L58-.LFB4940
.uleb128 0
.uleb128 .LEHB3-.LFB4940
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.uleb128 .LEHB4-.LFB4940
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE4940:
.section .text._ZNSt12experimental15fundamentals_v217_S_randint_engineEv,"axG",@progbits,_ZNSt12experimental15fundamentals_v217_S_randint_engineEv,comdat
.size _ZNSt12experimental15fundamentals_v217_S_randint_engineEv, .-_ZNSt12experimental15fundamentals_v217_S_randint_engineEv
.section .text._ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE,"axG",@progbits,_ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE,comdat
.align 2
.weak _ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE
.type _ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE, @function
_ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE:
.LFB5577:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbx
movq %rdx, %rbp
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movslq 4(%rdx), %r12
movslq (%rdx), %rax
subq %rax, %r12
cmpq $2147483644, %r12
ja .L65
addq $1, %r12
movl $2147483645, %eax
movl $0, %edx
divq %r12
movq %rax, %r8
imulq %rax, %r12
movq (%rsi), %rdx
movabsq $8589934597, %rdi
.L66:
imulq $16807, %rdx, %rsi
movq %rsi, %rax
mulq %rdi
movq %rsi, %rcx
subq %rdx, %rcx
shrq %rcx
addq %rcx, %rdx
shrq $30, %rdx
movq %rdx, %rcx
salq $31, %rcx
subq %rdx, %rcx
subq %rcx, %rsi
movq %rsi, %rdx
leaq -1(%rsi), %rax
cmpq %r12, %rax
jnb .L66
movq %rsi, (%rbx)
movl $0, %edx
divq %r8
.L67:
addl 0(%rbp), %eax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L74
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
movq %rdi, %r13
cmpq $2147483645, %r12
jbe .L68
movq %r12, %rdx
shrq %rdx
movabsq $-9223372028264841207, %rcx
movq %rdx, %rax
mulq %rcx
shrq $29, %rdx
movl %edx, %r14d
movabsq $8589934597, %r15
.L72:
movl $0, (%rsp)
movl %r14d, 4(%rsp)
movq %rsp, %rdx
movq %rbx, %rsi
movq %r13, %rdi
call _ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE
cltq
movq %rax, %rcx
salq $30, %rcx
subq %rax, %rcx
addq %rcx, %rcx
imulq $16807, (%rbx), %rsi
movq %rsi, %rax
mulq %r15
movq %rsi, %rax
subq %rdx, %rax
shrq %rax
addq %rax, %rdx
shrq $30, %rdx
movq %rdx, %rax
salq $31, %rax
subq %rdx, %rax
subq %rax, %rsi
movq %rsi, (%rbx)
leaq -1(%rsi,%rcx), %rax
cmpq %rax, %r12
jb .L72
cmpq %rcx, %rax
jb .L72
jmp .L67
.L68:
imulq $16807, (%rsi), %rcx
movabsq $8589934597, %rdx
movq %rcx, %rax
mulq %rdx
movq %rcx, %rax
subq %rdx, %rax
shrq %rax
addq %rdx, %rax
shrq $30, %rax
movq %rax, %rdx
salq $31, %rdx
subq %rax, %rdx
movq %rcx, %rax
subq %rdx, %rax
movq %rax, (%rsi)
subq $1, %rax
jmp .L67
.L74:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5577:
.size _ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE, .-_ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE
.text
.globl _Z8init_vecPA70_i
.type _Z8init_vecPA70_i, @function
_Z8init_vecPA70_i:
.LFB4945:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r13
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 280(%rdi), %r12
addq $17080, %r13
movq %rsp, %rbp
.L76:
leaq -280(%r12), %rbx
.L77:
movl $0, (%rsp)
movl $5, 4(%rsp)
call _ZNSt12experimental15fundamentals_v217_S_randint_engineEv
movq %rax, %rsi
movq %rbp, %rdx
movq %rbp, %rdi
call _ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE
movl %eax, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L77
addq $280, %r12
cmpq %r13, %r12
jne .L76
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L82
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L82:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4945:
.size _Z8init_vecPA70_i, .-_Z8init_vecPA70_i
.section .rodata.str1.1
.LC9:
.string "seed = "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC10:
.string "/home/ubuntu/Datasets/stackv2/train-structured/Nyriu/Esercizi_Esempi_CUDA/main/l07_s19_atomic2D_my/main.cu"
.section .rodata.str1.1
.LC11:
.string "\nN = "
.LC12:
.string "\nM = "
.LC13:
.string "\nN*M = "
.LC14:
.string "\nthreads = "
.LC15:
.string "\nb = "
.LC16:
.string "\nb*threads = "
.LC17:
.string "\nx = "
.LC18:
.string "\tMAX_VAL = "
.LC19:
.string "c_count = "
.LC20:
.string "g_count = "
.LC21:
.string "\nCorrect"
.LC22:
.string "\nWRONG!"
.text
.globl main
.type main, @function
main:
.LFB4950:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4950
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
leaq -16384(%rsp), %r11
.cfi_def_cfa 11, 16416
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $512, %rsp
.cfi_def_cfa_offset 16928
movq %fs:40, %rax
movq %rax, 16888(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %ebp
movslq %eax, %rbx
cmpb $0, %fs:_ZGVZNSt12experimental15fundamentals_v217_S_randint_engineEvE5__eng@tpoff
je .L110
.L84:
movabsq $8589934597, %rdx
movq %rbx, %rax
mulq %rdx
movq %rbx, %rax
subq %rdx, %rax
shrq %rax
addq %rax, %rdx
shrq $30, %rdx
movq %rdx, %rax
salq $31, %rax
subq %rdx, %rax
subq %rax, %rbx
movl $1, %eax
cmove %rax, %rbx
movq %rbx, %fs:_ZZNSt12experimental15fundamentals_v217_S_randint_engineEvE5__eng@tpoff
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB5:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebp, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, 36(%rsp)
movl $5, 40(%rsp)
cmpb $0, %fs:_ZGVZNSt12experimental15fundamentals_v217_S_randint_engineEvE5__eng@tpoff
je .L111
.L90:
leaq 36(%rsp), %rdi
movq %fs:0, %rax
leaq _ZZNSt12experimental15fundamentals_v217_S_randint_engineEvE5__eng@tpoff(%rax), %rsi
movq %rdi, %rdx
call _ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE
movl %eax, %ebp
leaq 80(%rsp), %rbx
movq %rbx, %rdi
call _Z8init_vecPA70_i
movq %rbx, %rdi
call _Z8show_vecPA70_i
leaq 16(%rsp), %rdi
movl $16800, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $117, %edx
leaq .LC10(%rip), %r12
movq %r12, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $1, %ecx
movl $16800, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $118, %edx
movq %r12, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, 12(%rsp)
movl $256, %esi
movl $4200, %edi
call _Z8div_ceilii
movl %eax, %ebx
leaq .LC11(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $60, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC12(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $70, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $4200, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC14(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $256, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC15(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC16(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
sall $8, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $256, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl %ebx, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L112
.L97:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $132, %edx
leaq .LC10(%rip), %rbx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 12(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL9d_g_count(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
movl %eax, %edi
movl $134, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 80(%rsp), %rdi
movl %ebp, %esi
call _Z9cpu_countPA70_ii
movl %eax, %ebx
leaq .LC17(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebp, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC18(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $5, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC19(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC20(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 12(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
cmpl %ebx, 12(%rsp)
je .L113
leaq .LC22(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L102:
leaq _ZL9d_g_count(%rip), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 16888(%rsp), %rax
subq %fs:40, %rax
jne .L114
movl $0, %eax
addq $16896, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L110:
.cfi_restore_state
leaq 48(%rsp), %r12
leaq 64(%rsp), %rax
movq %rax, 48(%rsp)
leaq 7+.LC8(%rip), %rdx
leaq -7(%rdx), %rsi
movq %r12, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE5:
leaq 80(%rsp), %rdi
movq %r12, %rsi
.LEHB6:
call _ZNSt13random_device7_M_initERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@PLT
.LEHE6:
movq 48(%rsp), %rdi
leaq 64(%rsp), %rax
cmpq %rax, %rdi
je .L85
movq 64(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L85:
leaq 80(%rsp), %rdi
.LEHB7:
call _ZNSt13random_device9_M_getvalEv@PLT
.LEHE7:
movl %eax, %eax
movl $2147483647, %ecx
movl $0, %edx
divq %rcx
testq %rdx, %rdx
movl $1, %eax
cmove %rax, %rdx
movq %rdx, %fs:_ZZNSt12experimental15fundamentals_v217_S_randint_engineEvE5__eng@tpoff
movb $1, %fs:_ZGVZNSt12experimental15fundamentals_v217_S_randint_engineEvE5__eng@tpoff
leaq 80(%rsp), %rdi
call _ZNSt13random_device7_M_finiEv@PLT
jmp .L84
.L105:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 16888(%rsp), %rax
subq %fs:40, %rax
je .L88
call __stack_chk_fail@PLT
.L88:
movq %rbx, %rdi
.LEHB8:
call _Unwind_Resume@PLT
.LEHE8:
.L104:
endbr64
movq %rax, %rbx
leaq 80(%rsp), %rdi
call _ZNSt13random_device7_M_finiEv@PLT
movq 16888(%rsp), %rax
subq %fs:40, %rax
je .L92
call __stack_chk_fail@PLT
.L92:
movq %rbx, %rdi
.LEHB9:
call _Unwind_Resume@PLT
.L111:
leaq 48(%rsp), %rbx
leaq 64(%rsp), %rax
movq %rax, 48(%rsp)
leaq 7+.LC8(%rip), %rdx
leaq -7(%rdx), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE9:
leaq 80(%rsp), %rdi
movq %rbx, %rsi
.LEHB10:
call _ZNSt13random_device7_M_initERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@PLT
.LEHE10:
movq 48(%rsp), %rdi
leaq 64(%rsp), %rax
cmpq %rax, %rdi
je .L93
movq 64(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L93:
leaq 80(%rsp), %rdi
.LEHB11:
call _ZNSt13random_device9_M_getvalEv@PLT
.LEHE11:
movl %eax, %eax
movl $2147483647, %ecx
movl $0, %edx
divq %rcx
testq %rdx, %rdx
movl $1, %eax
cmove %rax, %rdx
movq %rdx, %fs:_ZZNSt12experimental15fundamentals_v217_S_randint_engineEvE5__eng@tpoff
movb $1, %fs:_ZGVZNSt12experimental15fundamentals_v217_S_randint_engineEvE5__eng@tpoff
leaq 80(%rsp), %rdi
call _ZNSt13random_device7_M_finiEv@PLT
jmp .L90
.L107:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 16888(%rsp), %rax
subq %fs:40, %rax
je .L96
call __stack_chk_fail@PLT
.L96:
movq %rbx, %rdi
.LEHB12:
call _Unwind_Resume@PLT
.LEHE12:
.L106:
endbr64
movq %rax, %rbx
leaq 80(%rsp), %rdi
call _ZNSt13random_device7_M_finiEv@PLT
movq 16888(%rsp), %rax
subq %fs:40, %rax
je .L100
call __stack_chk_fail@PLT
.L100:
movq %rbx, %rdi
.LEHB13:
call _Unwind_Resume@PLT
.L112:
movl %ebp, %esi
movq 16(%rsp), %rdi
call _Z29__device_stub__Z9gpu_countPiiPii
jmp .L97
.L113:
leaq .LC21(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE13:
jmp .L102
.L114:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4950:
.section .gcc_except_table,"a",@progbits
.LLSDA4950:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4950-.LLSDACSB4950
.LLSDACSB4950:
.uleb128 .LEHB5-.LFB4950
.uleb128 .LEHE5-.LEHB5
.uleb128 0
.uleb128 0
.uleb128 .LEHB6-.LFB4950
.uleb128 .LEHE6-.LEHB6
.uleb128 .L105-.LFB4950
.uleb128 0
.uleb128 .LEHB7-.LFB4950
.uleb128 .LEHE7-.LEHB7
.uleb128 .L104-.LFB4950
.uleb128 0
.uleb128 .LEHB8-.LFB4950
.uleb128 .LEHE8-.LEHB8
.uleb128 0
.uleb128 0
.uleb128 .LEHB9-.LFB4950
.uleb128 .LEHE9-.LEHB9
.uleb128 0
.uleb128 0
.uleb128 .LEHB10-.LFB4950
.uleb128 .LEHE10-.LEHB10
.uleb128 .L107-.LFB4950
.uleb128 0
.uleb128 .LEHB11-.LFB4950
.uleb128 .LEHE11-.LEHB11
.uleb128 .L106-.LFB4950
.uleb128 0
.uleb128 .LEHB12-.LFB4950
.uleb128 .LEHE12-.LEHB12
.uleb128 0
.uleb128 0
.uleb128 .LEHB13-.LFB4950
.uleb128 .LEHE13-.LEHB13
.uleb128 0
.uleb128 0
.LLSDACSE4950:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL9d_g_count
.comm _ZL9d_g_count,4,4
.weak _ZGVZNSt12experimental15fundamentals_v217_S_randint_engineEvE5__eng
.section .tbss._ZGVZNSt12experimental15fundamentals_v217_S_randint_engineEvE5__eng,"awTG",@nobits,_ZGVZNSt12experimental15fundamentals_v217_S_randint_engineEvE5__eng,comdat
.align 8
.type _ZGVZNSt12experimental15fundamentals_v217_S_randint_engineEvE5__eng, @gnu_unique_object
.size _ZGVZNSt12experimental15fundamentals_v217_S_randint_engineEvE5__eng, 8
_ZGVZNSt12experimental15fundamentals_v217_S_randint_engineEvE5__eng:
.zero 8
.weak _ZZNSt12experimental15fundamentals_v217_S_randint_engineEvE5__eng
.section .tbss._ZZNSt12experimental15fundamentals_v217_S_randint_engineEvE5__eng,"awTG",@nobits,_ZZNSt12experimental15fundamentals_v217_S_randint_engineEvE5__eng,comdat
.align 8
.type _ZZNSt12experimental15fundamentals_v217_S_randint_engineEvE5__eng, @gnu_unique_object
.size _ZZNSt12experimental15fundamentals_v217_S_randint_engineEvE5__eng, 8
_ZZNSt12experimental15fundamentals_v217_S_randint_engineEvE5__eng:
.zero 8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Esercizio
// Come il precedente ma 2D
// Dato array 2D di NxM interi e un valore intero x conta quanti sono gli elementi di uguali a x
//
// x e N forniti da linea di comando // TODO
// Variante
// Usare grid 2D // TODO
#include <locale>
#include <stdlib.h>
#include <iostream>
#include <experimental/random>
#include <time.h>
#define N 60 // 3 // Rows
#define M 70 // 4 // Cols
#define THREADS_PER_BLOCK 256
#define MAX_VAL 5 // 50
static void HandleError( cudaError_t err, const char *file, int line) {
if (err != cudaSuccess) {
std::cout << cudaGetErrorString( err ) << " in " << file << " line " << line << std::endl;
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err)(HandleError(err, __FILE__, __LINE__))
void init_vec(int v[N][M]) {
for (int i=0; i<N; i++) {
for (int j=0; j<M; j++) {
v[i][j] = std::experimental::randint(0,MAX_VAL);
//std::cout << "i = " << i << "\tj = " << j << std::endl;
//std::cout << "v[i][j] = "<< v[i][j] << std::endl;
//v[i][j] = 0;
//v[i][j] = i*M + j;
//std::cout << "v[i][j] = "<< v[i][j] << "\n" << std::endl;
}
}
}
void show_vec(int v[N][M]) {
std::cout << "[\n";
for (int i=0; i<N; i++) {
for (int j=0; j<M; j++) {
std::cout << v[i][j] << ", ";
}
std::cout << "\n";
}
std::cout << "]\n" << std::endl;
}
int cpu_count(int v[N][M], const int x) {
int c=0;
for (int i=0; i<N; i++) {
for (int j=0; j<M; j++) {
if (v[i][j] == x)
c++;
}
}
return c;
}
int div_ceil(int numerator, int denominator) {
std::div_t res = std::div(numerator, denominator);
return res.rem ? (res.quot + 1) : res.quot;
}
int compute_num_blocks(const int n, const int m) {
int b = div_ceil(n*m, THREADS_PER_BLOCK);
return b;
}
__device__ int d_g_count = 0;
__global__ void gpu_count(int *d_v, const int x) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid >= N*M)
return;
if (d_v[tid] == x) {
atomicAdd(&d_g_count, 1);
printf("%d\t%d - Increment\n", tid, d_v[tid]);
} else {
printf("%d\t%d\n", tid, d_v[tid]);
}
}
int main( void ) {
size_t vec_size = ((size_t)N*M) * sizeof(int);
//std::cout << "N = " << N << std::endl;
//std::cout << "sizeof(int) = " << sizeof(int) << std::endl;
//std::cout << "size = " << vec_size << std::endl;
int seed = (int)time(NULL);
//std::experimental::reseed(3);
std::experimental::reseed(seed);
std::cout << "seed = " << seed << std::endl;
int x;
x = std::experimental::randint(0,MAX_VAL);
//x = N-1; // x is in the last block
int v[N][M];
//int *v;
//v = (int*)malloc(vec_size);
init_vec(v);
show_vec(v);
int *dev_v;
HANDLE_ERROR(cudaMalloc((void**)&dev_v, vec_size));
HANDLE_ERROR(cudaMemcpy(dev_v, v, vec_size, cudaMemcpyHostToDevice));
int g_count=0;
int b = compute_num_blocks(N,M);
std::cout <<
"\nN = " << N <<
"\nM = " << M <<
"\nN*M = " << N*M <<
"\nthreads = " << THREADS_PER_BLOCK <<
"\nb = " << b <<
"\nb*threads = " << b*THREADS_PER_BLOCK << "\n" <<
std::endl;
gpu_count<<<b, THREADS_PER_BLOCK>>>(dev_v, x);
HANDLE_ERROR(cudaDeviceSynchronize());
HANDLE_ERROR(cudaMemcpyFromSymbol(&g_count, d_g_count, sizeof(int))); // better than cudaMemcpy // Look at ref in README
int c_count = cpu_count(v,x);
std::cout << "\nx = " << x << "\tMAX_VAL = " << MAX_VAL << "\n" << std::endl;
std::cout << "c_count = " << c_count << std::endl;
std::cout << "g_count = " << g_count << std::endl;
if (c_count == g_count)
std::cout << "\nCorrect" << std::endl;
else
std::cout << "\nWRONG!" << std::endl;
cudaFree(&d_g_count);
cudaFree(dev_v);
//free(v);
return 0;
} | // Esercizio
// Come il precedente ma 2D
// Dato array 2D di NxM interi e un valore intero x conta quanti sono gli elementi di uguali a x
//
// x e N forniti da linea di comando // TODO
// Variante
// Usare grid 2D // TODO
#include <hip/hip_runtime.h>
#include <locale>
#include <stdlib.h>
#include <iostream>
#include <experimental/random>
#include <time.h>
#define N 60 // 3 // Rows
#define M 70 // 4 // Cols
#define THREADS_PER_BLOCK 256
#define MAX_VAL 5 // 50
static void HandleError( hipError_t err, const char *file, int line) {
if (err != hipSuccess) {
std::cout << hipGetErrorString( err ) << " in " << file << " line " << line << std::endl;
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err)(HandleError(err, __FILE__, __LINE__))
void init_vec(int v[N][M]) {
for (int i=0; i<N; i++) {
for (int j=0; j<M; j++) {
v[i][j] = std::experimental::randint(0,MAX_VAL);
//std::cout << "i = " << i << "\tj = " << j << std::endl;
//std::cout << "v[i][j] = "<< v[i][j] << std::endl;
//v[i][j] = 0;
//v[i][j] = i*M + j;
//std::cout << "v[i][j] = "<< v[i][j] << "\n" << std::endl;
}
}
}
void show_vec(int v[N][M]) {
std::cout << "[\n";
for (int i=0; i<N; i++) {
for (int j=0; j<M; j++) {
std::cout << v[i][j] << ", ";
}
std::cout << "\n";
}
std::cout << "]\n" << std::endl;
}
int cpu_count(int v[N][M], const int x) {
int c=0;
for (int i=0; i<N; i++) {
for (int j=0; j<M; j++) {
if (v[i][j] == x)
c++;
}
}
return c;
}
int div_ceil(int numerator, int denominator) {
std::div_t res = std::div(numerator, denominator);
return res.rem ? (res.quot + 1) : res.quot;
}
int compute_num_blocks(const int n, const int m) {
int b = div_ceil(n*m, THREADS_PER_BLOCK);
return b;
}
__device__ int d_g_count = 0;
__global__ void gpu_count(int *d_v, const int x) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid >= N*M)
return;
if (d_v[tid] == x) {
atomicAdd(&d_g_count, 1);
printf("%d\t%d - Increment\n", tid, d_v[tid]);
} else {
printf("%d\t%d\n", tid, d_v[tid]);
}
}
int main( void ) {
size_t vec_size = ((size_t)N*M) * sizeof(int);
//std::cout << "N = " << N << std::endl;
//std::cout << "sizeof(int) = " << sizeof(int) << std::endl;
//std::cout << "size = " << vec_size << std::endl;
int seed = (int)time(NULL);
//std::experimental::reseed(3);
std::experimental::reseed(seed);
std::cout << "seed = " << seed << std::endl;
int x;
x = std::experimental::randint(0,MAX_VAL);
//x = N-1; // x is in the last block
int v[N][M];
//int *v;
//v = (int*)malloc(vec_size);
init_vec(v);
show_vec(v);
int *dev_v;
HANDLE_ERROR(hipMalloc((void**)&dev_v, vec_size));
HANDLE_ERROR(hipMemcpy(dev_v, v, vec_size, hipMemcpyHostToDevice));
int g_count=0;
int b = compute_num_blocks(N,M);
std::cout <<
"\nN = " << N <<
"\nM = " << M <<
"\nN*M = " << N*M <<
"\nthreads = " << THREADS_PER_BLOCK <<
"\nb = " << b <<
"\nb*threads = " << b*THREADS_PER_BLOCK << "\n" <<
std::endl;
gpu_count<<<b, THREADS_PER_BLOCK>>>(dev_v, x);
HANDLE_ERROR(hipDeviceSynchronize());
HANDLE_ERROR(hipMemcpyFromSymbol(&g_count, HIP_SYMBOL(d_g_count), sizeof(int))); // better than cudaMemcpy // Look at ref in README
int c_count = cpu_count(v,x);
std::cout << "\nx = " << x << "\tMAX_VAL = " << MAX_VAL << "\n" << std::endl;
std::cout << "c_count = " << c_count << std::endl;
std::cout << "g_count = " << g_count << std::endl;
if (c_count == g_count)
std::cout << "\nCorrect" << std::endl;
else
std::cout << "\nWRONG!" << std::endl;
hipFree(&d_g_count);
hipFree(dev_v);
//free(v);
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /***************************************************************************//**
* \file LHS2.cu
* \author Christopher Minar (minarc@oregonstate.edu)
* \brief kernels to generate the left hand side for the poission solve
*/
#include "LHS2.h"
namespace kernels
{
__global__
void LHS2_mid_luo(int *row, int *col, double *val, double *dx, double *dy, int nx, int ny, double dt)
{
int ip = threadIdx.x + blockDim.x * blockIdx.x;
if (ip >= nx*ny)
return;
int I = ip % nx,
J = ip / nx;
if (I == 0 || I == nx-1 || J == 0 || J == ny-1)
return;
int numE = nx*4-2 + (J-1)*(nx*5-2) + I*5-1;
double temp = 0;
//EAST
row[numE] = ip;
col[numE] = ip + 1;
val[numE] = -dt/(dx[I]*(dx[I]+dx[I+1])*0.5);
numE++;
temp += dt/(dx[I]*(dx[I]+dx[I+1])*0.5);
//WEST
row[numE] = ip;
col[numE] = ip - 1;
val[numE] = -dt/(dx[I]*(dx[I]+dx[I-1])*0.5);
temp += dt/(dx[I]*(dx[I]+dx[I-1])*0.5);
numE++;
//NORTH
row[numE] = ip;
col[numE] = ip + nx;
val[numE] = -dt/(dy[J]*(dy[J]+dy[J+1])*0.5);
temp += dt/(dy[J]*(dy[J]+dy[J+1])*0.5);
numE++;
//SOUTH
row[numE] = ip;
col[numE] = ip - nx;
val[numE] = -dt/(dy[J]*(dy[J]+dy[J-1])*0.5);
temp += dt/(dy[J]*(dy[J]+dy[J-1])*0.5);
numE++;
//MID
row[numE] = ip;
col[numE] = ip;
val[numE] = temp;
//do some jank so the solver works, although this modifies the matricies it doesn't really change the results //flag
if(row[numE]==col[numE] && col[numE]==(ny/2)*nx+nx/2)
{
//val[numE] += val[numE];
}
}
} | .file "tmpxft_00148ed6_00000000-6_LHS2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z56__device_stub__ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iidPiS_PdS0_S0_iid
.type _Z56__device_stub__ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iidPiS_PdS0_S0_iid, @function
_Z56__device_stub__ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iidPiS_PdS0_S0_iid:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movl %r9d, 20(%rsp)
movsd %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z56__device_stub__ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iidPiS_PdS0_S0_iid, .-_Z56__device_stub__ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iidPiS_PdS0_S0_iid
.globl _ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid
.type _ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid, @function
_ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z56__device_stub__ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iidPiS_PdS0_S0_iid
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid, .-_ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /***************************************************************************//**
* \file LHS2.cu
* \author Christopher Minar (minarc@oregonstate.edu)
* \brief kernels to generate the left hand side for the poission solve
*/
#include "LHS2.h"
namespace kernels
{
__global__
void LHS2_mid_luo(int *row, int *col, double *val, double *dx, double *dy, int nx, int ny, double dt)
{
int ip = threadIdx.x + blockDim.x * blockIdx.x;
if (ip >= nx*ny)
return;
int I = ip % nx,
J = ip / nx;
if (I == 0 || I == nx-1 || J == 0 || J == ny-1)
return;
int numE = nx*4-2 + (J-1)*(nx*5-2) + I*5-1;
double temp = 0;
//EAST
row[numE] = ip;
col[numE] = ip + 1;
val[numE] = -dt/(dx[I]*(dx[I]+dx[I+1])*0.5);
numE++;
temp += dt/(dx[I]*(dx[I]+dx[I+1])*0.5);
//WEST
row[numE] = ip;
col[numE] = ip - 1;
val[numE] = -dt/(dx[I]*(dx[I]+dx[I-1])*0.5);
temp += dt/(dx[I]*(dx[I]+dx[I-1])*0.5);
numE++;
//NORTH
row[numE] = ip;
col[numE] = ip + nx;
val[numE] = -dt/(dy[J]*(dy[J]+dy[J+1])*0.5);
temp += dt/(dy[J]*(dy[J]+dy[J+1])*0.5);
numE++;
//SOUTH
row[numE] = ip;
col[numE] = ip - nx;
val[numE] = -dt/(dy[J]*(dy[J]+dy[J-1])*0.5);
temp += dt/(dy[J]*(dy[J]+dy[J-1])*0.5);
numE++;
//MID
row[numE] = ip;
col[numE] = ip;
val[numE] = temp;
//do some jank so the solver works, although this modifies the matricies it doesn't really change the results //flag
if(row[numE]==col[numE] && col[numE]==(ny/2)*nx+nx/2)
{
//val[numE] += val[numE];
}
}
} | /***************************************************************************//**
* \file LHS2.cu
* \author Christopher Minar (minarc@oregonstate.edu)
* \brief kernels to generate the left hand side for the poission solve
*/
#include <hip/hip_runtime.h>
#include "LHS2.h"
namespace kernels
{
__global__
void LHS2_mid_luo(int *row, int *col, double *val, double *dx, double *dy, int nx, int ny, double dt)
{
int ip = threadIdx.x + blockDim.x * blockIdx.x;
if (ip >= nx*ny)
return;
int I = ip % nx,
J = ip / nx;
if (I == 0 || I == nx-1 || J == 0 || J == ny-1)
return;
int numE = nx*4-2 + (J-1)*(nx*5-2) + I*5-1;
double temp = 0;
//EAST
row[numE] = ip;
col[numE] = ip + 1;
val[numE] = -dt/(dx[I]*(dx[I]+dx[I+1])*0.5);
numE++;
temp += dt/(dx[I]*(dx[I]+dx[I+1])*0.5);
//WEST
row[numE] = ip;
col[numE] = ip - 1;
val[numE] = -dt/(dx[I]*(dx[I]+dx[I-1])*0.5);
temp += dt/(dx[I]*(dx[I]+dx[I-1])*0.5);
numE++;
//NORTH
row[numE] = ip;
col[numE] = ip + nx;
val[numE] = -dt/(dy[J]*(dy[J]+dy[J+1])*0.5);
temp += dt/(dy[J]*(dy[J]+dy[J+1])*0.5);
numE++;
//SOUTH
row[numE] = ip;
col[numE] = ip - nx;
val[numE] = -dt/(dy[J]*(dy[J]+dy[J-1])*0.5);
temp += dt/(dy[J]*(dy[J]+dy[J-1])*0.5);
numE++;
//MID
row[numE] = ip;
col[numE] = ip;
val[numE] = temp;
//do some jank so the solver works, although this modifies the matricies it doesn't really change the results //flag
if(row[numE]==col[numE] && col[numE]==(ny/2)*nx+nx/2)
{
//val[numE] += val[numE];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /***************************************************************************//**
* \file LHS2.cu
* \author Christopher Minar (minarc@oregonstate.edu)
* \brief kernels to generate the left hand side for the poission solve
*/
#include <hip/hip_runtime.h>
#include "LHS2.h"
namespace kernels
{
__global__
void LHS2_mid_luo(int *row, int *col, double *val, double *dx, double *dy, int nx, int ny, double dt)
{
int ip = threadIdx.x + blockDim.x * blockIdx.x;
if (ip >= nx*ny)
return;
int I = ip % nx,
J = ip / nx;
if (I == 0 || I == nx-1 || J == 0 || J == ny-1)
return;
int numE = nx*4-2 + (J-1)*(nx*5-2) + I*5-1;
double temp = 0;
//EAST
row[numE] = ip;
col[numE] = ip + 1;
val[numE] = -dt/(dx[I]*(dx[I]+dx[I+1])*0.5);
numE++;
temp += dt/(dx[I]*(dx[I]+dx[I+1])*0.5);
//WEST
row[numE] = ip;
col[numE] = ip - 1;
val[numE] = -dt/(dx[I]*(dx[I]+dx[I-1])*0.5);
temp += dt/(dx[I]*(dx[I]+dx[I-1])*0.5);
numE++;
//NORTH
row[numE] = ip;
col[numE] = ip + nx;
val[numE] = -dt/(dy[J]*(dy[J]+dy[J+1])*0.5);
temp += dt/(dy[J]*(dy[J]+dy[J+1])*0.5);
numE++;
//SOUTH
row[numE] = ip;
col[numE] = ip - nx;
val[numE] = -dt/(dy[J]*(dy[J]+dy[J-1])*0.5);
temp += dt/(dy[J]*(dy[J]+dy[J-1])*0.5);
numE++;
//MID
row[numE] = ip;
col[numE] = ip;
val[numE] = temp;
//do some jank so the solver works, although this modifies the matricies it doesn't really change the results //flag
if(row[numE]==col[numE] && col[numE]==(ny/2)*nx+nx/2)
{
//val[numE] += val[numE];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid
.globl _ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid
.p2align 8
.type _ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid,@function
_ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b64 s[12:13], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mul_i32 s2, s13, s12
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_4
s_ashr_i32 s2, s12, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s3, s12, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s3, s3, s2
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s4, 0, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v3
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v3, s2, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v2, v0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v0
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v0, v3
v_mul_lo_u32 v0, v2, s12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v1, v0
v_cmp_ne_u32_e32 vcc_lo, 0, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_4
s_add_i32 s2, s12, -1
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_cmp_ne_u32_e64 s2, s2, v3
s_add_i32 s3, s13, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e64 s3, s3, v2
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_4
s_load_b256 s[4:11], s[0:1], 0x0
v_ashrrev_i32_e32 v4, 31, v3
s_mul_i32 s2, s12, 5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s2, s2, -2
v_lshlrev_b64 v[4:5], 3, v[3:4]
v_lshl_add_u32 v3, v3, 2, v3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s10, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
s_load_b64 s[10:11], s[0:1], 0x30
s_clause 0x1
global_load_b64 v[6:7], v[4:5], off
global_load_b64 v[8:9], v[4:5], off offset:8
s_waitcnt vmcnt(0)
v_add_f64 v[8:9], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[6:7], v[6:7], v[8:9]
v_mul_f64 v[6:7], v[6:7], 0.5
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], -s[10:11]
v_div_scale_f64 v[14:15], vcc_lo, -s[10:11], v[6:7], -s[10:11]
v_rcp_f64_e32 v[10:11], v[8:9]
s_waitcnt_depctr 0xfff
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
v_mul_f64 v[12:13], v[14:15], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[8:9], v[12:13], v[14:15]
v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[12:13]
v_add_nc_u32_e32 v10, -1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v10, s2
s_lshl_b32 s2, s12, 2
v_ashrrev_i32_e32 v11, 31, v10
s_add_i32 s2, s2, -2
v_lshlrev_b64 v[10:11], 3, v[10:11]
v_div_fixup_f64 v[6:7], v[8:9], v[6:7], -s[10:11]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add3_u32 v8, s2, v3, v0
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v0, 1, v1
v_add_nc_u32_e32 v12, -1, v8
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_ashrrev_i32_e32 v13, 31, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], 3, v[12:13]
v_add_co_u32 v14, vcc_lo, s8, v14
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v15, vcc_lo, s9, v15, vcc_lo
global_store_b64 v[14:15], v[6:7], off
s_clause 0x2
global_load_b64 v[6:7], v[4:5], off offset:8
global_load_b64 v[14:15], v[4:5], off
global_load_b64 v[16:17], v[4:5], off offset:-8
s_waitcnt vmcnt(1)
v_add_f64 v[6:7], v[14:15], v[6:7]
s_waitcnt vmcnt(0)
v_add_f64 v[16:17], v[14:15], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[6:7], v[14:15], v[6:7]
v_mul_f64 v[14:15], v[14:15], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[6:7], v[6:7], 0.5
v_mul_f64 v[14:15], v[14:15], 0.5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f64 v[16:17], null, v[6:7], v[6:7], s[10:11]
v_div_scale_f64 v[18:19], null, v[14:15], v[14:15], -s[10:11]
v_div_scale_f64 v[28:29], vcc_lo, s[10:11], v[6:7], s[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[20:21], v[16:17]
v_rcp_f64_e32 v[22:23], v[18:19]
s_waitcnt_depctr 0xfff
v_fma_f64 v[24:25], -v[16:17], v[20:21], 1.0
v_fma_f64 v[26:27], -v[18:19], v[22:23], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[20:21], v[20:21], v[24:25], v[20:21]
v_fma_f64 v[22:23], v[22:23], v[26:27], v[22:23]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[24:25], -v[16:17], v[20:21], 1.0
v_fma_f64 v[26:27], -v[18:19], v[22:23], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[20:21], v[20:21], v[24:25], v[20:21]
v_div_scale_f64 v[24:25], s2, -s[10:11], v[14:15], -s[10:11]
v_fma_f64 v[22:23], v[22:23], v[26:27], v[22:23]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[26:27], v[28:29], v[20:21]
v_mul_f64 v[30:31], v[24:25], v[22:23]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[16:17], -v[16:17], v[26:27], v[28:29]
v_fma_f64 v[18:19], -v[18:19], v[30:31], v[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[16:17], v[16:17], v[20:21], v[26:27]
s_mov_b32 vcc_lo, s2
s_load_b64 s[2:3], s[0:1], 0x20
v_div_fmas_f64 v[18:19], v[18:19], v[22:23], v[30:31]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f64 v[6:7], v[16:17], v[6:7], s[10:11]
v_div_fixup_f64 v[14:15], v[18:19], v[14:15], -s[10:11]
v_lshlrev_b64 v[18:19], 3, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v18, vcc_lo, s8, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s9, v19, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_add_f64 v[6:7], v[6:7], 0
global_store_b64 v[18:19], v[14:15], off
s_clause 0x1
global_load_b64 v[14:15], v[4:5], off
global_load_b64 v[4:5], v[4:5], off offset:-8
s_clause 0x1
global_load_b64 v[18:19], v[2:3], off
global_load_b64 v[20:21], v[2:3], off offset:8
s_waitcnt vmcnt(2)
v_add_f64 v[4:5], v[14:15], v[4:5]
s_waitcnt vmcnt(0)
v_add_f64 v[20:21], v[18:19], v[20:21]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[4:5], v[14:15], v[4:5]
v_mul_f64 v[14:15], v[18:19], v[20:21]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[4:5], v[4:5], 0.5
v_mul_f64 v[14:15], v[14:15], 0.5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f64 v[18:19], null, v[4:5], v[4:5], s[10:11]
v_div_scale_f64 v[20:21], null, v[14:15], v[14:15], -s[10:11]
v_div_scale_f64 v[30:31], vcc_lo, s[10:11], v[4:5], s[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[22:23], v[18:19]
v_rcp_f64_e32 v[24:25], v[20:21]
s_waitcnt_depctr 0xfff
v_fma_f64 v[26:27], -v[18:19], v[22:23], 1.0
v_fma_f64 v[28:29], -v[20:21], v[24:25], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[22:23], v[22:23], v[26:27], v[22:23]
v_fma_f64 v[24:25], v[24:25], v[28:29], v[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[26:27], -v[18:19], v[22:23], 1.0
v_fma_f64 v[28:29], -v[20:21], v[24:25], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[22:23], v[22:23], v[26:27], v[22:23]
v_div_scale_f64 v[26:27], s0, -s[10:11], v[14:15], -s[10:11]
v_fma_f64 v[24:25], v[24:25], v[28:29], v[24:25]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[28:29], v[30:31], v[22:23]
v_mul_f64 v[32:33], v[26:27], v[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[18:19], -v[18:19], v[28:29], v[30:31]
v_fma_f64 v[20:21], -v[20:21], v[32:33], v[26:27]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[18:19], v[18:19], v[22:23], v[28:29]
s_mov_b32 vcc_lo, s0
v_div_fmas_f64 v[20:21], v[20:21], v[24:25], v[32:33]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f64 v[4:5], v[18:19], v[4:5], s[10:11]
v_div_fixup_f64 v[14:15], v[20:21], v[14:15], -s[10:11]
v_add_nc_u32_e32 v20, 1, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v21, 31, v20
v_lshlrev_b64 v[22:23], 3, v[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v22, vcc_lo, s8, v22
v_add_co_ci_u32_e32 v23, vcc_lo, s9, v23, vcc_lo
v_add_co_u32 v10, vcc_lo, s2, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
v_add_f64 v[4:5], v[6:7], v[4:5]
global_store_b64 v[22:23], v[14:15], off
s_clause 0x2
global_load_b64 v[14:15], v[2:3], off
global_load_b64 v[22:23], v[2:3], off offset:8
global_load_b64 v[24:25], v[10:11], off
s_waitcnt vmcnt(1)
v_add_f64 v[22:23], v[14:15], v[22:23]
s_waitcnt vmcnt(0)
v_add_f64 v[24:25], v[14:15], v[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[22:23], v[14:15], v[22:23]
v_mul_f64 v[14:15], v[14:15], v[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[22:23], v[22:23], 0.5
v_mul_f64 v[14:15], v[14:15], 0.5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f64 v[24:25], null, v[22:23], v[22:23], s[10:11]
v_div_scale_f64 v[26:27], null, v[14:15], v[14:15], -s[10:11]
v_div_scale_f64 v[36:37], vcc_lo, s[10:11], v[22:23], s[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[28:29], v[24:25]
v_rcp_f64_e32 v[30:31], v[26:27]
s_waitcnt_depctr 0xfff
v_fma_f64 v[32:33], -v[24:25], v[28:29], 1.0
v_fma_f64 v[34:35], -v[26:27], v[30:31], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[28:29], v[28:29], v[32:33], v[28:29]
v_fma_f64 v[30:31], v[30:31], v[34:35], v[30:31]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[32:33], -v[24:25], v[28:29], 1.0
v_fma_f64 v[34:35], -v[26:27], v[30:31], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[28:29], v[28:29], v[32:33], v[28:29]
v_div_scale_f64 v[32:33], s0, -s[10:11], v[14:15], -s[10:11]
v_fma_f64 v[30:31], v[30:31], v[34:35], v[30:31]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[34:35], v[36:37], v[28:29]
v_mul_f64 v[38:39], v[32:33], v[30:31]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[24:25], -v[24:25], v[34:35], v[36:37]
v_fma_f64 v[26:27], -v[26:27], v[38:39], v[32:33]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[24:25], v[24:25], v[28:29], v[34:35]
s_mov_b32 vcc_lo, s0
v_div_fmas_f64 v[26:27], v[26:27], v[30:31], v[38:39]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f64 v[6:7], v[24:25], v[22:23], s[10:11]
v_div_fixup_f64 v[14:15], v[26:27], v[14:15], -s[10:11]
v_add_nc_u32_e32 v26, 2, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v27, 31, v26
v_lshlrev_b64 v[28:29], 3, v[26:27]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v28, vcc_lo, s8, v28
v_add_co_ci_u32_e32 v29, vcc_lo, s9, v29, vcc_lo
v_add_f64 v[4:5], v[4:5], v[6:7]
v_lshlrev_b64 v[6:7], 2, v[12:13]
v_lshlrev_b64 v[12:13], 2, v[8:9]
global_store_b64 v[28:29], v[14:15], off
s_clause 0x1
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[10:11], v[10:11], off
s_waitcnt vmcnt(0)
v_add_f64 v[10:11], v[2:3], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], v[10:11]
v_mul_f64 v[2:3], v[2:3], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[10:11], null, v[2:3], v[2:3], s[10:11]
v_rcp_f64_e32 v[14:15], v[10:11]
s_waitcnt_depctr 0xfff
v_fma_f64 v[28:29], -v[10:11], v[14:15], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[14:15], v[28:29], v[14:15]
v_fma_f64 v[28:29], -v[10:11], v[14:15], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[14:15], v[28:29], v[14:15]
v_div_scale_f64 v[28:29], vcc_lo, s[10:11], v[2:3], s[10:11]
v_mul_f64 v[16:17], v[28:29], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[10:11], v[16:17], v[28:29]
v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[16:17]
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f64 v[2:3], v[10:11], v[2:3], s[10:11]
v_add_co_u32 v10, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v7, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
v_add_co_u32 v14, vcc_lo, s4, v12
v_add_co_ci_u32_e32 v15, vcc_lo, s5, v13, vcc_lo
global_store_b32 v[10:11], v1, off
global_store_b32 v[6:7], v0, off
global_store_b32 v[14:15], v1, off
v_lshlrev_b64 v[6:7], 2, v[20:21]
v_add_co_u32 v9, vcc_lo, s6, v12
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v13, vcc_lo
v_lshlrev_b64 v[13:14], 2, v[26:27]
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v11, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v7, vcc_lo
v_add_nc_u32_e32 v0, -1, v1
v_add_nc_u32_e32 v15, s12, v1
v_add_f64 v[2:3], v[4:5], v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v6
v_add_nc_u32_e32 v6, 3, v8
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v7, vcc_lo
global_store_b32 v[9:10], v0, off
global_store_b32 v[11:12], v1, off
global_store_b32 v[4:5], v15, off
v_ashrrev_i32_e32 v7, 31, v6
v_add_co_u32 v4, vcc_lo, s4, v13
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[8:9], 2, v[6:7]
v_add_co_u32 v10, vcc_lo, s6, v13
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v14, vcc_lo
v_lshlrev_b64 v[6:7], 3, v[6:7]
v_add_co_u32 v12, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v9, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v8
v_subrev_nc_u32_e32 v0, s12, v1
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
v_add_co_u32 v6, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
global_store_b32 v[4:5], v1, off
global_store_b32 v[10:11], v0, off
global_store_b32 v[12:13], v1, off
global_store_b32 v[8:9], v1, off
global_store_b64 v[6:7], v[2:3], off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 40
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid, .Lfunc_end0-_ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 8
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 40
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /***************************************************************************//**
* \file LHS2.cu
* \author Christopher Minar (minarc@oregonstate.edu)
* \brief kernels to generate the left hand side for the poission solve
*/
#include <hip/hip_runtime.h>
#include "LHS2.h"
namespace kernels
{
__global__
void LHS2_mid_luo(int *row, int *col, double *val, double *dx, double *dy, int nx, int ny, double dt)
{
int ip = threadIdx.x + blockDim.x * blockIdx.x;
if (ip >= nx*ny)
return;
int I = ip % nx,
J = ip / nx;
if (I == 0 || I == nx-1 || J == 0 || J == ny-1)
return;
int numE = nx*4-2 + (J-1)*(nx*5-2) + I*5-1;
double temp = 0;
//EAST
row[numE] = ip;
col[numE] = ip + 1;
val[numE] = -dt/(dx[I]*(dx[I]+dx[I+1])*0.5);
numE++;
temp += dt/(dx[I]*(dx[I]+dx[I+1])*0.5);
//WEST
row[numE] = ip;
col[numE] = ip - 1;
val[numE] = -dt/(dx[I]*(dx[I]+dx[I-1])*0.5);
temp += dt/(dx[I]*(dx[I]+dx[I-1])*0.5);
numE++;
//NORTH
row[numE] = ip;
col[numE] = ip + nx;
val[numE] = -dt/(dy[J]*(dy[J]+dy[J+1])*0.5);
temp += dt/(dy[J]*(dy[J]+dy[J+1])*0.5);
numE++;
//SOUTH
row[numE] = ip;
col[numE] = ip - nx;
val[numE] = -dt/(dy[J]*(dy[J]+dy[J-1])*0.5);
temp += dt/(dy[J]*(dy[J]+dy[J-1])*0.5);
numE++;
//MID
row[numE] = ip;
col[numE] = ip;
val[numE] = temp;
//do some jank so the solver works, although this modifies the matricies it doesn't really change the results //flag
if(row[numE]==col[numE] && col[numE]==(ny/2)*nx+nx/2)
{
//val[numE] += val[numE];
}
}
} | .text
.file "LHS2.hip"
.globl _ZN7kernels27__device_stub__LHS2_mid_luoEPiS0_PdS1_S1_iid # -- Begin function _ZN7kernels27__device_stub__LHS2_mid_luoEPiS0_PdS1_S1_iid
.p2align 4, 0x90
.type _ZN7kernels27__device_stub__LHS2_mid_luoEPiS0_PdS1_S1_iid,@function
_ZN7kernels27__device_stub__LHS2_mid_luoEPiS0_PdS1_S1_iid: # @_ZN7kernels27__device_stub__LHS2_mid_luoEPiS0_PdS1_S1_iid
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 12(%rsp)
movsd %xmm0, 64(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _ZN7kernels27__device_stub__LHS2_mid_luoEPiS0_PdS1_S1_iid, .Lfunc_end0-_ZN7kernels27__device_stub__LHS2_mid_luoEPiS0_PdS1_S1_iid
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid,@object # @_ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid
.section .rodata,"a",@progbits
.globl _ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid
.p2align 3, 0x0
_ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid:
.quad _ZN7kernels27__device_stub__LHS2_mid_luoEPiS0_PdS1_S1_iid
.size _ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid"
.size .L__unnamed_1, 43
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZN7kernels27__device_stub__LHS2_mid_luoEPiS0_PdS1_S1_iid
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00148ed6_00000000-6_LHS2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z56__device_stub__ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iidPiS_PdS0_S0_iid
.type _Z56__device_stub__ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iidPiS_PdS0_S0_iid, @function
_Z56__device_stub__ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iidPiS_PdS0_S0_iid:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movl %r9d, 20(%rsp)
movsd %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z56__device_stub__ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iidPiS_PdS0_S0_iid, .-_Z56__device_stub__ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iidPiS_PdS0_S0_iid
.globl _ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid
.type _ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid, @function
_ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z56__device_stub__ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iidPiS_PdS0_S0_iid
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid, .-_ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "LHS2.hip"
.globl _ZN7kernels27__device_stub__LHS2_mid_luoEPiS0_PdS1_S1_iid # -- Begin function _ZN7kernels27__device_stub__LHS2_mid_luoEPiS0_PdS1_S1_iid
.p2align 4, 0x90
.type _ZN7kernels27__device_stub__LHS2_mid_luoEPiS0_PdS1_S1_iid,@function
_ZN7kernels27__device_stub__LHS2_mid_luoEPiS0_PdS1_S1_iid: # @_ZN7kernels27__device_stub__LHS2_mid_luoEPiS0_PdS1_S1_iid
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 12(%rsp)
movsd %xmm0, 64(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _ZN7kernels27__device_stub__LHS2_mid_luoEPiS0_PdS1_S1_iid, .Lfunc_end0-_ZN7kernels27__device_stub__LHS2_mid_luoEPiS0_PdS1_S1_iid
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid,@object # @_ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid
.section .rodata,"a",@progbits
.globl _ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid
.p2align 3, 0x0
_ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid:
.quad _ZN7kernels27__device_stub__LHS2_mid_luoEPiS0_PdS1_S1_iid
.size _ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid"
.size .L__unnamed_1, 43
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZN7kernels27__device_stub__LHS2_mid_luoEPiS0_PdS1_S1_iid
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZN7kernels12LHS2_mid_luoEPiS0_PdS1_S1_iid
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void use_local_memory_GPU(float in)
{
float f; // variable "f" is in local memory and private to each thread
f = in; // parameter "in" is in local memory and private to each thread
}
__global__ void use_global_memory_GPU(float *array)
{
array[threadIdx.x] = 2.0f * (float) threadIdx.x;
}
__global__ void use_shared_memory_GPU(float *array)
{
int i, index = threadIdx.x;
float average, sum = 0.0f;
__shared__ float sh_arr[128];
sh_arr[index] = array[index];
__syncthreads(); // ensure all the writes to shared memory have completed
for (i=0; i<index; i++) { sum += sh_arr[i]; }
average = sum / (index + 1.0f);
printf("Thread id = %d\t Average = %f\n",index,average);
if (array[index] > average) { array[index] = average; }
sh_arr[index] = 3.14;
}
int main(int argc, char **argv)
{
use_local_memory_GPU<<<1, 128>>>(2.0f);
float h_arr[128]; // convention: h_ variables live on host
float *d_arr; // convention: d_ variables live on device (GPU global mem)
cudaMalloc((void **) &d_arr, sizeof(float) * 128);
cudaMemcpy((void *)d_arr, (void *)h_arr, sizeof(float) * 128, cudaMemcpyHostToDevice);
use_global_memory_GPU<<<1, 128>>>(d_arr); // modifies the contents of array at d_arr
cudaMemcpy((void *)h_arr, (void *)d_arr, sizeof(float) * 128, cudaMemcpyDeviceToHost);
use_shared_memory_GPU<<<1, 128>>>(d_arr);
cudaMemcpy((void *)h_arr, (void *)d_arr, sizeof(float) * 128, cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z21use_shared_memory_GPUPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fe40007ffe0ff */
/*0050*/ IMAD.WIDE R16, R2, R17, c[0x0][0x160] ; /* 0x0000580002107625 */
/* 0x001fca00078e0211 */
/*0060*/ LDG.E R3, [R16.64] ; /* 0x0000002410037981 */
/* 0x000ea2000c1e1900 */
/*0070*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*0080*/ BSSY B2, 0x650 ; /* 0x000005c000027945 */
/* 0x000fe20003800000 */
/*0090*/ IMAD.MOV.U32 R23, RZ, RZ, RZ ; /* 0x000000ffff177224 */
/* 0x000fe200078e00ff */
/*00a0*/ STS [R2.X4], R3 ; /* 0x0000000302007388 */
/* 0x0041e80000004800 */
/*00b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00c0*/ @!P0 BRA 0x640 ; /* 0x0000057000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R0, R2.reuse, -0x1, RZ ; /* 0xffffffff02007810 */
/* 0x041fe20007ffe0ff */
/*00e0*/ BSSY B1, 0x5b0 ; /* 0x000004c000017945 */
/* 0x000fe20003800000 */
/*00f0*/ LOP3.LUT R19, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302137812 */
/* 0x000fe200078ec0ff */
/*0100*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fe200078e00ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f06070 */
/*0120*/ IMAD.MOV.U32 R23, RZ, RZ, RZ ; /* 0x000000ffff177224 */
/* 0x000fd800078e00ff */
/*0130*/ @!P0 BRA 0x5a0 ; /* 0x0000046000008947 */
/* 0x000fea0003800000 */
/*0140*/ IMAD.IADD R0, R2, 0x1, -R19 ; /* 0x0000000102007824 */
/* 0x000fe200078e0a13 */
/*0150*/ BSSY B0, 0x500 ; /* 0x000003a000007945 */
/* 0x000fe20003800000 */
/*0160*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fe400078e00ff */
/*0170*/ IMAD.MOV.U32 R23, RZ, RZ, RZ ; /* 0x000000ffff177224 */
/* 0x000fe200078e00ff */
/*0180*/ ISETP.GT.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f04270 */
/*0190*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fd800078e00ff */
/*01a0*/ @!P0 BRA 0x4f0 ; /* 0x0000034000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R0, 0xc, PT ; /* 0x0000000c0000780c */
/* 0x000fe20003f24270 */
/*01c0*/ BSSY B3, 0x3a0 ; /* 0x000001d000037945 */
/* 0x000fe20003800000 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01e0*/ @!P1 BRA 0x390 ; /* 0x000001a000009947 */
/* 0x000fea0003800000 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0200*/ LDS.128 R4, [R3] ; /* 0x0000000003047984 */
/* 0x000e220000000c00 */
/*0210*/ IADD3 R0, R0, -0x10, RZ ; /* 0xfffffff000007810 */
/* 0x000fe40007ffe0ff */
/*0220*/ IADD3 R18, R18, 0x10, RZ ; /* 0x0000001012127810 */
/* 0x000fe20007ffe0ff */
/*0230*/ LDS.128 R8, [R3+0x10] ; /* 0x0000100003087984 */
/* 0x000e620000000c00 */
/*0240*/ ISETP.GT.AND P1, PT, R0, 0xc, PT ; /* 0x0000000c0000780c */
/* 0x000fc60003f24270 */
/*0250*/ LDS.128 R12, [R3+0x20] ; /* 0x00002000030c7984 */
/* 0x000ea20000000c00 */
/*0260*/ FADD R4, R4, R23 ; /* 0x0000001704047221 */
/* 0x001fc60000000000 */
/*0270*/ LDS.128 R20, [R3+0x30] ; /* 0x0000300003147984 */
/* 0x0000e20000000c00 */
/*0280*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*0290*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fe20000000000 */
/*02a0*/ IADD3 R3, R3, 0x40, RZ ; /* 0x0000004003037810 */
/* 0x001fc60007ffe0ff */
/*02b0*/ FADD R7, R6, R7 ; /* 0x0000000706077221 */
/* 0x000fc80000000000 */
/*02c0*/ FADD R8, R7, R8 ; /* 0x0000000807087221 */
/* 0x002fc80000000000 */
/*02d0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x000fc80000000000 */
/*02e0*/ FADD R10, R9, R10 ; /* 0x0000000a090a7221 */
/* 0x000fc80000000000 */
/*02f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x000fc80000000000 */
/*0300*/ FADD R12, R11, R12 ; /* 0x0000000c0b0c7221 */
/* 0x004fc80000000000 */
/*0310*/ FADD R13, R12, R13 ; /* 0x0000000d0c0d7221 */
/* 0x000fc80000000000 */
/*0320*/ FADD R14, R13, R14 ; /* 0x0000000e0d0e7221 */
/* 0x000fc80000000000 */
/*0330*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x000fc80000000000 */
/*0340*/ FADD R20, R15, R20 ; /* 0x000000140f147221 */
/* 0x008fc80000000000 */
/*0350*/ FADD R21, R20, R21 ; /* 0x0000001514157221 */
/* 0x000fc80000000000 */
/*0360*/ FADD R22, R21, R22 ; /* 0x0000001615167221 */
/* 0x000fc80000000000 */
/*0370*/ FADD R23, R22, R23 ; /* 0x0000001716177221 */
/* 0x000fe20000000000 */
/*0380*/ @P1 BRA 0x200 ; /* 0xfffffe7000001947 */
/* 0x000fea000383ffff */
/*0390*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*03a0*/ ISETP.GT.AND P1, PT, R0, 0x4, PT ; /* 0x000000040000780c */
/* 0x000fe20003f24270 */
/*03b0*/ BSSY B3, 0x4c0 ; /* 0x0000010000037945 */
/* 0x000fd80003800000 */
/*03c0*/ @!P1 BRA 0x4b0 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*03d0*/ LDS.128 R4, [R3] ; /* 0x0000000003047984 */
/* 0x000e220000000c00 */
/*03e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*03f0*/ IADD3 R18, R18, 0x8, RZ ; /* 0x0000000812127810 */
/* 0x000fe20007ffe0ff */
/*0400*/ LDS.128 R8, [R3+0x10] ; /* 0x0000100003087984 */
/* 0x0002a20000000c00 */
/*0410*/ IADD3 R0, R0, -0x8, RZ ; /* 0xfffffff800007810 */
/* 0x000fe40007ffe0ff */
/*0420*/ IADD3 R3, R3, 0x20, RZ ; /* 0x0000002003037810 */
/* 0x002fe20007ffe0ff */
/*0430*/ FADD R4, R23, R4 ; /* 0x0000000417047221 */
/* 0x001fc80000000000 */
/*0440*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*0450*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fc80000000000 */
/*0460*/ FADD R7, R6, R7 ; /* 0x0000000706077221 */
/* 0x000fc80000000000 */
/*0470*/ FADD R8, R7, R8 ; /* 0x0000000807087221 */
/* 0x004fc80000000000 */
/*0480*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x000fc80000000000 */
/*0490*/ FADD R10, R9, R10 ; /* 0x0000000a090a7221 */
/* 0x000fc80000000000 */
/*04a0*/ FADD R23, R10, R11 ; /* 0x0000000b0a177221 */
/* 0x000fe40000000000 */
/*04b0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*04c0*/ ISETP.NE.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0000705670 */
/*04d0*/ @!P0 BREAK B0 ; /* 0x0000000000008942 */
/* 0x000fe20003800000 */
/*04e0*/ @!P0 BRA 0x5a0 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*04f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0500*/ LDS.128 R4, [R3] ; /* 0x0000000003047984 */
/* 0x0000620000000c00 */
/*0510*/ IADD3 R0, R0, -0x4, RZ ; /* 0xfffffffc00007810 */
/* 0x000fe40007ffe0ff */
/*0520*/ IADD3 R18, R18, 0x4, RZ ; /* 0x0000000412127810 */
/* 0x000fe40007ffe0ff */
/*0530*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0540*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x001fe20007ffe0ff */
/*0550*/ FADD R4, R4, R23 ; /* 0x0000001704047221 */
/* 0x002fc80000000000 */
/*0560*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*0570*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fc80000000000 */
/*0580*/ FADD R23, R6, R7 ; /* 0x0000000706177221 */
/* 0x000fe20000000000 */
/*0590*/ @P0 BRA 0x500 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*05a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*05b0*/ ISETP.NE.AND P0, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fda0003f05270 */
/*05c0*/ @!P0 BRA 0x640 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*05d0*/ IMAD.SHL.U32 R18, R18, 0x4, RZ ; /* 0x0000000412127824 */
/* 0x000fca00078e00ff */
/*05e0*/ LDS R0, [R18] ; /* 0x0000000012007984 */
/* 0x0000620000000800 */
/*05f0*/ IADD3 R19, R19, -0x1, RZ ; /* 0xffffffff13137810 */
/* 0x000fc80007ffe0ff */
/*0600*/ ISETP.NE.AND P0, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fe40003f05270 */
/*0610*/ IADD3 R18, R18, 0x4, RZ ; /* 0x0000000412127810 */
/* 0x001fe20007ffe0ff */
/*0620*/ FADD R23, R0, R23 ; /* 0x0000001700177221 */
/* 0x002fd40000000000 */
/*0630*/ @P0 BRA 0x5e0 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0640*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x001fea0003800000 */
/*0650*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0660*/ I2F R0, R2 ; /* 0x0000000200007306 */
/* 0x000e220000201400 */
/*0670*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f3e0ff */
/*0680*/ BSSY B0, 0x770 ; /* 0x000000e000007945 */
/* 0x000fe80003800000 */
/*0690*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fe400008e06ff */
/*06a0*/ FADD R8, R0, 1 ; /* 0x3f80000000087421 */
/* 0x001fc80000000000 */
/*06b0*/ MUFU.RCP R3, R8 ; /* 0x0000000800037308 */
/* 0x000e300000001000 */
/*06c0*/ FCHK P0, R23, R8 ; /* 0x0000000817007302 */
/* 0x000e620000000000 */
/*06d0*/ FFMA R0, -R8, R3, 1 ; /* 0x3f80000008007423 */
/* 0x001fc80000000103 */
/*06e0*/ FFMA R0, R3, R0, R3 ; /* 0x0000000003007223 */
/* 0x000fc80000000003 */
/*06f0*/ FFMA R19, R0, R23, RZ ; /* 0x0000001700137223 */
/* 0x000fc800000000ff */
/*0700*/ FFMA R3, -R8, R19, R23 ; /* 0x0000001308037223 */
/* 0x000fc80000000117 */
/*0710*/ FFMA R19, R0, R3, R19 ; /* 0x0000000300137223 */
/* 0x000fe20000000013 */
/*0720*/ @!P0 BRA 0x760 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0730*/ MOV R0, 0x750 ; /* 0x0000075000007802 */
/* 0x000fe40000000f00 */
/*0740*/ CALL.REL.NOINC 0x8c0 ; /* 0x0000017000007944 */
/* 0x000fea0003c00000 */
/*0750*/ IMAD.MOV.U32 R19, RZ, RZ, R3 ; /* 0x000000ffff137224 */
/* 0x001fe400078e0003 */
/*0760*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0770*/ F2F.F64.F32 R10, R19 ; /* 0x00000013000a7310 */
/* 0x000e220000201800 */
/*0780*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*0790*/ STL [R1], R2 ; /* 0x0000000201007387 */
/* 0x0003e20000100800 */
/*07a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*07b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*07c0*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000ea20000000a00 */
/*07d0*/ STL.64 [R1+0x8], R10 ; /* 0x0000080a01007387 */
/* 0x0013e80000100a00 */
/*07e0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x002fe20000000000 */
/*07f0*/ MOV R3, 0x860 ; /* 0x0000086000037802 */
/* 0x000fc40000000f00 */
/*0800*/ MOV R20, 0x7e0 ; /* 0x000007e000147802 */
/* 0x000fe40000000f00 */
/*0810*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0820*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0830*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0840*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0850*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x004fea0003c00000 */
/*0860*/ LDG.E R0, [R16.64] ; /* 0x0000002410007981 */
/* 0x000ea2000c1e1900 */
/*0870*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4048f5c3 ; /* 0x4048f5c3ff037424 */
/* 0x000fca00078e00ff */
/*0880*/ STS [R2.X4], R3 ; /* 0x0000000302007388 */
/* 0x000fe20000004800 */
/*0890*/ FSETP.GT.AND P0, PT, R0, R19, PT ; /* 0x000000130000720b */
/* 0x004fda0003f04000 */
/*08a0*/ @P0 STG.E [R16.64], R19 ; /* 0x0000001310000986 */
/* 0x000fe2000c101924 */
/*08b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08c0*/ SHF.R.U32.HI R5, RZ, 0x17, R8.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011608 */
/*08d0*/ BSSY B1, 0xf20 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*08e0*/ SHF.R.U32.HI R3, RZ, 0x17, R23.reuse ; /* 0x00000017ff037819 */
/* 0x100fe20000011617 */
/*08f0*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0008 */
/*0900*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*0910*/ LOP3.LUT R11, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff030b7812 */
/* 0x000fe200078ec0ff */
/*0920*/ IMAD.MOV.U32 R3, RZ, RZ, R23 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0017 */
/*0930*/ IADD3 R9, R5, -0x1, RZ ; /* 0xffffffff05097810 */
/* 0x000fe40007ffe0ff */
/*0940*/ IADD3 R12, R11, -0x1, RZ ; /* 0xffffffff0b0c7810 */
/* 0x000fc40007ffe0ff */
/*0950*/ ISETP.GT.U32.AND P0, PT, R9, 0xfd, PT ; /* 0x000000fd0900780c */
/* 0x000fc80003f04070 */
/*0960*/ ISETP.GT.U32.OR P0, PT, R12, 0xfd, P0 ; /* 0x000000fd0c00780c */
/* 0x000fda0000704470 */
/*0970*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff048224 */
/* 0x000fe200078e00ff */
/*0980*/ @!P0 BRA 0xb00 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0990*/ FSETP.GTU.FTZ.AND P0, PT, |R23|, +INF , PT ; /* 0x7f8000001700780b */
/* 0x000fe40003f1c200 */
/*09a0*/ FSETP.GTU.FTZ.AND P1, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fc80003f3c200 */
/*09b0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*09c0*/ @P0 BRA 0xf00 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*09d0*/ LOP3.LUT P0, RZ, R10, 0x7fffffff, R3, 0xc8, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fda000780c803 */
/*09e0*/ @!P0 BRA 0xee0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*09f0*/ FSETP.NEU.FTZ.AND P2, PT, |R23|.reuse, +INF , PT ; /* 0x7f8000001700780b */
/* 0x040fe40003f5d200 */
/*0a00*/ FSETP.NEU.FTZ.AND P1, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fe40003f3d200 */
/*0a10*/ FSETP.NEU.FTZ.AND P0, PT, |R23|, +INF , PT ; /* 0x7f8000001700780b */
/* 0x000fd60003f1d200 */
/*0a20*/ @!P1 BRA !P2, 0xee0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0a30*/ LOP3.LUT P2, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x000fc8000784c0ff */
/*0a40*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0a50*/ @P1 BRA 0xec0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0a60*/ LOP3.LUT P1, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fc8000782c0ff */
/*0a70*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0a80*/ @P0 BRA 0xe90 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0a90*/ ISETP.GE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f06270 */
/*0aa0*/ ISETP.GE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fd60003f26270 */
/*0ab0*/ @P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff040224 */
/* 0x000fe400078e00ff */
/*0ac0*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, -0x40 ; /* 0xffffffc0ff048424 */
/* 0x000fe400078e00ff */
/*0ad0*/ @!P0 FFMA R3, R23, 1.84467440737095516160e+19, RZ ; /* 0x5f80000017038823 */
/* 0x000fe400000000ff */
/*0ae0*/ @!P1 FFMA R10, R8, 1.84467440737095516160e+19, RZ ; /* 0x5f800000080a9823 */
/* 0x000fe200000000ff */
/*0af0*/ @!P1 IADD3 R4, R4, 0x40, RZ ; /* 0x0000004004049810 */
/* 0x000fe40007ffe0ff */
/*0b00*/ LEA R9, R5, 0xc0800000, 0x17 ; /* 0xc080000005097811 */
/* 0x000fe200078eb8ff */
/*0b10*/ BSSY B2, 0xe80 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0b20*/ IADD3 R8, R11, -0x7f, RZ ; /* 0xffffff810b087810 */
/* 0x000fc60007ffe0ff */
/*0b30*/ IMAD.IADD R9, R10, 0x1, -R9 ; /* 0x000000010a097824 */
/* 0x000fe400078e0a09 */
/*0b40*/ IMAD R3, R8.reuse, -0x800000, R3 ; /* 0xff80000008037824 */
/* 0x040fe400078e0203 */
/*0b50*/ MUFU.RCP R10, R9 ; /* 0x00000009000a7308 */
/* 0x0000620000001000 */
/*0b60*/ FADD.FTZ R12, -R9, -RZ ; /* 0x800000ff090c7221 */
/* 0x000fe20000010100 */
/*0b70*/ IADD3 R9, R8, 0x7f, -R5 ; /* 0x0000007f08097810 */
/* 0x001fca0007ffe805 */
/*0b80*/ IMAD.IADD R4, R9, 0x1, R4 ; /* 0x0000000109047824 */
/* 0x000fe400078e0204 */
/*0b90*/ FFMA R11, R10, R12, 1 ; /* 0x3f8000000a0b7423 */
/* 0x002fc8000000000c */
/*0ba0*/ FFMA R14, R10, R11, R10 ; /* 0x0000000b0a0e7223 */
/* 0x000fc8000000000a */
/*0bb0*/ FFMA R10, R3, R14, RZ ; /* 0x0000000e030a7223 */
/* 0x000fc800000000ff */
/*0bc0*/ FFMA R11, R12, R10, R3 ; /* 0x0000000a0c0b7223 */
/* 0x000fc80000000003 */
/*0bd0*/ FFMA R11, R14, R11, R10 ; /* 0x0000000b0e0b7223 */
/* 0x000fc8000000000a */
/*0be0*/ FFMA R12, R12, R11, R3 ; /* 0x0000000b0c0c7223 */
/* 0x000fc80000000003 */
/*0bf0*/ FFMA R3, R14, R12, R11 ; /* 0x0000000c0e037223 */
/* 0x000fca000000000b */
/*0c00*/ SHF.R.U32.HI R5, RZ, 0x17, R3 ; /* 0x00000017ff057819 */
/* 0x000fc80000011603 */
/*0c10*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*0c20*/ IMAD.IADD R10, R5, 0x1, R4 ; /* 0x00000001050a7824 */
/* 0x000fca00078e0204 */
/*0c30*/ IADD3 R5, R10, -0x1, RZ ; /* 0xffffffff0a057810 */
/* 0x000fc80007ffe0ff */
/*0c40*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0c50*/ @!P0 BRA 0xe60 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0c60*/ ISETP.GT.AND P0, PT, R10, 0xfe, PT ; /* 0x000000fe0a00780c */
/* 0x000fda0003f04270 */
/*0c70*/ @P0 BRA 0xe30 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0c80*/ ISETP.GE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fda0003f06270 */
/*0c90*/ @P0 BRA 0xe70 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0ca0*/ ISETP.GE.AND P0, PT, R10, -0x18, PT ; /* 0xffffffe80a00780c */
/* 0x000fe40003f06270 */
/*0cb0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0cc0*/ @!P0 BRA 0xe70 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0cd0*/ FFMA.RZ R4, R14, R12.reuse, R11.reuse ; /* 0x0000000c0e047223 */
/* 0x180fe2000000c00b */
/*0ce0*/ IADD3 R9, R10, 0x20, RZ ; /* 0x000000200a097810 */
/* 0x000fe20007ffe0ff */
/*0cf0*/ FFMA.RM R5, R14, R12.reuse, R11.reuse ; /* 0x0000000c0e057223 */
/* 0x180fe2000000400b */
/*0d00*/ ISETP.NE.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f45270 */
/*0d10*/ LOP3.LUT R8, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04087812 */
/* 0x000fe200078ec0ff */
/*0d20*/ FFMA.RP R4, R14, R12, R11 ; /* 0x0000000c0e047223 */
/* 0x000fe2000000800b */
/*0d30*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f25270 */
/*0d40*/ IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0a0a */
/*0d50*/ LOP3.LUT R8, R8, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000008087812 */
/* 0x000fe400078efcff */
/*0d60*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*0d70*/ SHF.L.U32 R9, R8, R9, RZ ; /* 0x0000000908097219 */
/* 0x000fe400000006ff */
/*0d80*/ SEL R5, R10, RZ, P2 ; /* 0x000000ff0a057207 */
/* 0x000fe40001000000 */
/*0d90*/ ISETP.NE.AND P1, PT, R9, RZ, P1 ; /* 0x000000ff0900720c */
/* 0x000fe40000f25270 */
/*0da0*/ SHF.R.U32.HI R5, RZ, R5, R8 ; /* 0x00000005ff057219 */
/* 0x000fe40000011608 */
/*0db0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0dc0*/ SHF.R.U32.HI R9, RZ, 0x1, R5 ; /* 0x00000001ff097819 */
/* 0x000fc40000011605 */
/*0dd0*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0de0*/ LOP3.LUT R4, R4, 0x1, R9, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef809 */
/*0df0*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0e00*/ IMAD.IADD R4, R9, 0x1, R4 ; /* 0x0000000109047824 */
/* 0x000fca00078e0204 */
/*0e10*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*0e20*/ BRA 0xe70 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0e30*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0e40*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0e50*/ BRA 0xe70 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0e60*/ IMAD R3, R4, 0x800000, R3 ; /* 0x0080000004037824 */
/* 0x000fe400078e0203 */
/*0e70*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0e80*/ BRA 0xf10 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0e90*/ LOP3.LUT R3, R10, 0x80000000, R3, 0x48, !PT ; /* 0x800000000a037812 */
/* 0x000fc800078e4803 */
/*0ea0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0eb0*/ BRA 0xf10 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0ec0*/ LOP3.LUT R3, R10, 0x80000000, R3, 0x48, !PT ; /* 0x800000000a037812 */
/* 0x000fe200078e4803 */
/*0ed0*/ BRA 0xf10 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0ee0*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0ef0*/ BRA 0xf10 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0f00*/ FADD.FTZ R3, R23, R8 ; /* 0x0000000817037221 */
/* 0x000fe40000010000 */
/*0f10*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0f20*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0f30*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0f40*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff0b004007950 */
/* 0x000fea0003c3ffff */
/*0f50*/ BRA 0xf50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z21use_global_memory_GPUPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ I2F.U32 R0, R4 ; /* 0x0000000400007306 */
/* 0x001e300000201000 */
/*0050*/ IMAD.WIDE.U32 R2, R4, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc800078e0003 */
/*0060*/ FADD R5, R0, R0 ; /* 0x0000000000057221 */
/* 0x001fca0000000000 */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z20use_local_memory_GPUf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void use_local_memory_GPU(float in)
{
float f; // variable "f" is in local memory and private to each thread
f = in; // parameter "in" is in local memory and private to each thread
}
__global__ void use_global_memory_GPU(float *array)
{
array[threadIdx.x] = 2.0f * (float) threadIdx.x;
}
__global__ void use_shared_memory_GPU(float *array)
{
int i, index = threadIdx.x;
float average, sum = 0.0f;
__shared__ float sh_arr[128];
sh_arr[index] = array[index];
__syncthreads(); // ensure all the writes to shared memory have completed
for (i=0; i<index; i++) { sum += sh_arr[i]; }
average = sum / (index + 1.0f);
printf("Thread id = %d\t Average = %f\n",index,average);
if (array[index] > average) { array[index] = average; }
sh_arr[index] = 3.14;
}
int main(int argc, char **argv)
{
use_local_memory_GPU<<<1, 128>>>(2.0f);
float h_arr[128]; // convention: h_ variables live on host
float *d_arr; // convention: d_ variables live on device (GPU global mem)
cudaMalloc((void **) &d_arr, sizeof(float) * 128);
cudaMemcpy((void *)d_arr, (void *)h_arr, sizeof(float) * 128, cudaMemcpyHostToDevice);
use_global_memory_GPU<<<1, 128>>>(d_arr); // modifies the contents of array at d_arr
cudaMemcpy((void *)h_arr, (void *)d_arr, sizeof(float) * 128, cudaMemcpyDeviceToHost);
use_shared_memory_GPU<<<1, 128>>>(d_arr);
cudaMemcpy((void *)h_arr, (void *)d_arr, sizeof(float) * 128, cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_0011a9ae_00000000-6_.cuda_p2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z20use_local_memory_GPUff
.type _Z39__device_stub__Z20use_local_memory_GPUff, @function
_Z39__device_stub__Z20use_local_memory_GPUff:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z20use_local_memory_GPUf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z39__device_stub__Z20use_local_memory_GPUff, .-_Z39__device_stub__Z20use_local_memory_GPUff
.globl _Z20use_local_memory_GPUf
.type _Z20use_local_memory_GPUf, @function
_Z20use_local_memory_GPUf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z20use_local_memory_GPUff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z20use_local_memory_GPUf, .-_Z20use_local_memory_GPUf
.globl _Z41__device_stub__Z21use_global_memory_GPUPfPf
.type _Z41__device_stub__Z21use_global_memory_GPUPfPf, @function
_Z41__device_stub__Z21use_global_memory_GPUPfPf:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z21use_global_memory_GPUPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z41__device_stub__Z21use_global_memory_GPUPfPf, .-_Z41__device_stub__Z21use_global_memory_GPUPfPf
.globl _Z21use_global_memory_GPUPf
.type _Z21use_global_memory_GPUPf, @function
_Z21use_global_memory_GPUPf:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z21use_global_memory_GPUPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z21use_global_memory_GPUPf, .-_Z21use_global_memory_GPUPf
.globl _Z41__device_stub__Z21use_shared_memory_GPUPfPf
.type _Z41__device_stub__Z21use_shared_memory_GPUPfPf, @function
_Z41__device_stub__Z21use_shared_memory_GPUPfPf:
.LFB2086:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z21use_shared_memory_GPUPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z41__device_stub__Z21use_shared_memory_GPUPfPf, .-_Z41__device_stub__Z21use_shared_memory_GPUPfPf
.globl _Z21use_shared_memory_GPUPf
.type _Z21use_shared_memory_GPUPf, @function
_Z21use_shared_memory_GPUPf:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z21use_shared_memory_GPUPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z21use_shared_memory_GPUPf, .-_Z21use_shared_memory_GPUPf
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $568, %rsp
.cfi_def_cfa_offset 576
movq %fs:40, %rax
movq %rax, 552(%rsp)
xorl %eax, %eax
movl $128, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L28:
movq %rsp, %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $512, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L29:
leaq 32(%rsp), %rdi
movl $2, %ecx
movl $512, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movl $128, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L30:
leaq 32(%rsp), %rdi
movl $1, %ecx
movl $512, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $568, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movss .LC0(%rip), %xmm0
call _Z39__device_stub__Z20use_local_memory_GPUff
jmp .L28
.L34:
movq (%rsp), %rdi
call _Z41__device_stub__Z21use_global_memory_GPUPfPf
jmp .L29
.L35:
movq (%rsp), %rdi
call _Z41__device_stub__Z21use_shared_memory_GPUPfPf
jmp .L30
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z21use_shared_memory_GPUPf"
.LC2:
.string "_Z21use_global_memory_GPUPf"
.LC3:
.string "_Z20use_local_memory_GPUf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z21use_shared_memory_GPUPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z21use_global_memory_GPUPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z20use_local_memory_GPUf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void use_local_memory_GPU(float in)
{
float f; // variable "f" is in local memory and private to each thread
f = in; // parameter "in" is in local memory and private to each thread
}
__global__ void use_global_memory_GPU(float *array)
{
array[threadIdx.x] = 2.0f * (float) threadIdx.x;
}
__global__ void use_shared_memory_GPU(float *array)
{
int i, index = threadIdx.x;
float average, sum = 0.0f;
__shared__ float sh_arr[128];
sh_arr[index] = array[index];
__syncthreads(); // ensure all the writes to shared memory have completed
for (i=0; i<index; i++) { sum += sh_arr[i]; }
average = sum / (index + 1.0f);
printf("Thread id = %d\t Average = %f\n",index,average);
if (array[index] > average) { array[index] = average; }
sh_arr[index] = 3.14;
}
int main(int argc, char **argv)
{
use_local_memory_GPU<<<1, 128>>>(2.0f);
float h_arr[128]; // convention: h_ variables live on host
float *d_arr; // convention: d_ variables live on device (GPU global mem)
cudaMalloc((void **) &d_arr, sizeof(float) * 128);
cudaMemcpy((void *)d_arr, (void *)h_arr, sizeof(float) * 128, cudaMemcpyHostToDevice);
use_global_memory_GPU<<<1, 128>>>(d_arr); // modifies the contents of array at d_arr
cudaMemcpy((void *)h_arr, (void *)d_arr, sizeof(float) * 128, cudaMemcpyDeviceToHost);
use_shared_memory_GPU<<<1, 128>>>(d_arr);
cudaMemcpy((void *)h_arr, (void *)d_arr, sizeof(float) * 128, cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void use_local_memory_GPU(float in)
{
float f; // variable "f" is in local memory and private to each thread
f = in; // parameter "in" is in local memory and private to each thread
}
__global__ void use_global_memory_GPU(float *array)
{
array[threadIdx.x] = 2.0f * (float) threadIdx.x;
}
__global__ void use_shared_memory_GPU(float *array)
{
int i, index = threadIdx.x;
float average, sum = 0.0f;
__shared__ float sh_arr[128];
sh_arr[index] = array[index];
__syncthreads(); // ensure all the writes to shared memory have completed
for (i=0; i<index; i++) { sum += sh_arr[i]; }
average = sum / (index + 1.0f);
printf("Thread id = %d\t Average = %f\n",index,average);
if (array[index] > average) { array[index] = average; }
sh_arr[index] = 3.14;
}
int main(int argc, char **argv)
{
use_local_memory_GPU<<<1, 128>>>(2.0f);
float h_arr[128]; // convention: h_ variables live on host
float *d_arr; // convention: d_ variables live on device (GPU global mem)
hipMalloc((void **) &d_arr, sizeof(float) * 128);
hipMemcpy((void *)d_arr, (void *)h_arr, sizeof(float) * 128, hipMemcpyHostToDevice);
use_global_memory_GPU<<<1, 128>>>(d_arr); // modifies the contents of array at d_arr
hipMemcpy((void *)h_arr, (void *)d_arr, sizeof(float) * 128, hipMemcpyDeviceToHost);
use_shared_memory_GPU<<<1, 128>>>(d_arr);
hipMemcpy((void *)h_arr, (void *)d_arr, sizeof(float) * 128, hipMemcpyHostToDevice);
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void use_local_memory_GPU(float in)
{
float f; // variable "f" is in local memory and private to each thread
f = in; // parameter "in" is in local memory and private to each thread
}
__global__ void use_global_memory_GPU(float *array)
{
array[threadIdx.x] = 2.0f * (float) threadIdx.x;
}
__global__ void use_shared_memory_GPU(float *array)
{
int i, index = threadIdx.x;
float average, sum = 0.0f;
__shared__ float sh_arr[128];
sh_arr[index] = array[index];
__syncthreads(); // ensure all the writes to shared memory have completed
for (i=0; i<index; i++) { sum += sh_arr[i]; }
average = sum / (index + 1.0f);
printf("Thread id = %d\t Average = %f\n",index,average);
if (array[index] > average) { array[index] = average; }
sh_arr[index] = 3.14;
}
int main(int argc, char **argv)
{
use_local_memory_GPU<<<1, 128>>>(2.0f);
float h_arr[128]; // convention: h_ variables live on host
float *d_arr; // convention: d_ variables live on device (GPU global mem)
hipMalloc((void **) &d_arr, sizeof(float) * 128);
hipMemcpy((void *)d_arr, (void *)h_arr, sizeof(float) * 128, hipMemcpyHostToDevice);
use_global_memory_GPU<<<1, 128>>>(d_arr); // modifies the contents of array at d_arr
hipMemcpy((void *)h_arr, (void *)d_arr, sizeof(float) * 128, hipMemcpyDeviceToHost);
use_shared_memory_GPU<<<1, 128>>>(d_arr);
hipMemcpy((void *)h_arr, (void *)d_arr, sizeof(float) * 128, hipMemcpyHostToDevice);
hipDeviceSynchronize();
return 0;
} | .text
.file ".cuda_p2.hip"
.globl _Z35__device_stub__use_local_memory_GPUf # -- Begin function _Z35__device_stub__use_local_memory_GPUf
.p2align 4, 0x90
.type _Z35__device_stub__use_local_memory_GPUf,@function
_Z35__device_stub__use_local_memory_GPUf: # @_Z35__device_stub__use_local_memory_GPUf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movss %xmm0, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z20use_local_memory_GPUf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z35__device_stub__use_local_memory_GPUf, .Lfunc_end0-_Z35__device_stub__use_local_memory_GPUf
.cfi_endproc
# -- End function
.globl _Z36__device_stub__use_global_memory_GPUPf # -- Begin function _Z36__device_stub__use_global_memory_GPUPf
.p2align 4, 0x90
.type _Z36__device_stub__use_global_memory_GPUPf,@function
_Z36__device_stub__use_global_memory_GPUPf: # @_Z36__device_stub__use_global_memory_GPUPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z21use_global_memory_GPUPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z36__device_stub__use_global_memory_GPUPf, .Lfunc_end1-_Z36__device_stub__use_global_memory_GPUPf
.cfi_endproc
# -- End function
.globl _Z36__device_stub__use_shared_memory_GPUPf # -- Begin function _Z36__device_stub__use_shared_memory_GPUPf
.p2align 4, 0x90
.type _Z36__device_stub__use_shared_memory_GPUPf,@function
_Z36__device_stub__use_shared_memory_GPUPf: # @_Z36__device_stub__use_shared_memory_GPUPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z21use_shared_memory_GPUPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z36__device_stub__use_shared_memory_GPUPf, .Lfunc_end2-_Z36__device_stub__use_shared_memory_GPUPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $600, %rsp # imm = 0x258
.cfi_def_cfa_offset 624
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movabsq $4294967297, %r14 # imm = 0x100000001
leaq 127(%r14), %rbx
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movl $1073741824, 16(%rsp) # imm = 0x40000000
leaq 16(%rsp), %rax
movq %rax, (%rsp)
leaq 80(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movq %rsp, %r9
movl $_Z20use_local_memory_GPUf, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
leaq 8(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $512, %edx # imm = 0x200
movl $1, %ecx
callq hipMemcpy
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 64(%rsp)
leaq 24(%rsp), %rdi
leaq 48(%rsp), %rsi
movq %rsp, %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z21use_global_memory_GPUPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
movq 8(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $512, %edx # imm = 0x200
movl $2, %ecx
callq hipMemcpy
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 64(%rsp)
leaq 24(%rsp), %rdi
leaq 48(%rsp), %rsi
movq %rsp, %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z21use_shared_memory_GPUPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
movq 8(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $512, %edx # imm = 0x200
movl $1, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
xorl %eax, %eax
addq $600, %rsp # imm = 0x258
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20use_local_memory_GPUf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21use_global_memory_GPUPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21use_shared_memory_GPUPf, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20use_local_memory_GPUf,@object # @_Z20use_local_memory_GPUf
.section .rodata,"a",@progbits
.globl _Z20use_local_memory_GPUf
.p2align 3, 0x0
_Z20use_local_memory_GPUf:
.quad _Z35__device_stub__use_local_memory_GPUf
.size _Z20use_local_memory_GPUf, 8
.type _Z21use_global_memory_GPUPf,@object # @_Z21use_global_memory_GPUPf
.globl _Z21use_global_memory_GPUPf
.p2align 3, 0x0
_Z21use_global_memory_GPUPf:
.quad _Z36__device_stub__use_global_memory_GPUPf
.size _Z21use_global_memory_GPUPf, 8
.type _Z21use_shared_memory_GPUPf,@object # @_Z21use_shared_memory_GPUPf
.globl _Z21use_shared_memory_GPUPf
.p2align 3, 0x0
_Z21use_shared_memory_GPUPf:
.quad _Z36__device_stub__use_shared_memory_GPUPf
.size _Z21use_shared_memory_GPUPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20use_local_memory_GPUf"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z21use_global_memory_GPUPf"
.size .L__unnamed_2, 28
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z21use_shared_memory_GPUPf"
.size .L__unnamed_3, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__use_local_memory_GPUf
.addrsig_sym _Z36__device_stub__use_global_memory_GPUPf
.addrsig_sym _Z36__device_stub__use_shared_memory_GPUPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20use_local_memory_GPUf
.addrsig_sym _Z21use_global_memory_GPUPf
.addrsig_sym _Z21use_shared_memory_GPUPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011a9ae_00000000-6_.cuda_p2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z20use_local_memory_GPUff
.type _Z39__device_stub__Z20use_local_memory_GPUff, @function
_Z39__device_stub__Z20use_local_memory_GPUff:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z20use_local_memory_GPUf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z39__device_stub__Z20use_local_memory_GPUff, .-_Z39__device_stub__Z20use_local_memory_GPUff
.globl _Z20use_local_memory_GPUf
.type _Z20use_local_memory_GPUf, @function
_Z20use_local_memory_GPUf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z20use_local_memory_GPUff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z20use_local_memory_GPUf, .-_Z20use_local_memory_GPUf
.globl _Z41__device_stub__Z21use_global_memory_GPUPfPf
.type _Z41__device_stub__Z21use_global_memory_GPUPfPf, @function
_Z41__device_stub__Z21use_global_memory_GPUPfPf:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z21use_global_memory_GPUPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z41__device_stub__Z21use_global_memory_GPUPfPf, .-_Z41__device_stub__Z21use_global_memory_GPUPfPf
.globl _Z21use_global_memory_GPUPf
.type _Z21use_global_memory_GPUPf, @function
_Z21use_global_memory_GPUPf:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z21use_global_memory_GPUPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z21use_global_memory_GPUPf, .-_Z21use_global_memory_GPUPf
.globl _Z41__device_stub__Z21use_shared_memory_GPUPfPf
.type _Z41__device_stub__Z21use_shared_memory_GPUPfPf, @function
_Z41__device_stub__Z21use_shared_memory_GPUPfPf:
.LFB2086:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z21use_shared_memory_GPUPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z41__device_stub__Z21use_shared_memory_GPUPfPf, .-_Z41__device_stub__Z21use_shared_memory_GPUPfPf
.globl _Z21use_shared_memory_GPUPf
.type _Z21use_shared_memory_GPUPf, @function
_Z21use_shared_memory_GPUPf:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z21use_shared_memory_GPUPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z21use_shared_memory_GPUPf, .-_Z21use_shared_memory_GPUPf
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $568, %rsp
.cfi_def_cfa_offset 576
movq %fs:40, %rax
movq %rax, 552(%rsp)
xorl %eax, %eax
movl $128, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L28:
movq %rsp, %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $512, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L29:
leaq 32(%rsp), %rdi
movl $2, %ecx
movl $512, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movl $128, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L30:
leaq 32(%rsp), %rdi
movl $1, %ecx
movl $512, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $568, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movss .LC0(%rip), %xmm0
call _Z39__device_stub__Z20use_local_memory_GPUff
jmp .L28
.L34:
movq (%rsp), %rdi
call _Z41__device_stub__Z21use_global_memory_GPUPfPf
jmp .L29
.L35:
movq (%rsp), %rdi
call _Z41__device_stub__Z21use_shared_memory_GPUPfPf
jmp .L30
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z21use_shared_memory_GPUPf"
.LC2:
.string "_Z21use_global_memory_GPUPf"
.LC3:
.string "_Z20use_local_memory_GPUf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z21use_shared_memory_GPUPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z21use_global_memory_GPUPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z20use_local_memory_GPUf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file ".cuda_p2.hip"
.globl _Z35__device_stub__use_local_memory_GPUf # -- Begin function _Z35__device_stub__use_local_memory_GPUf
.p2align 4, 0x90
.type _Z35__device_stub__use_local_memory_GPUf,@function
_Z35__device_stub__use_local_memory_GPUf: # @_Z35__device_stub__use_local_memory_GPUf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movss %xmm0, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z20use_local_memory_GPUf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z35__device_stub__use_local_memory_GPUf, .Lfunc_end0-_Z35__device_stub__use_local_memory_GPUf
.cfi_endproc
# -- End function
.globl _Z36__device_stub__use_global_memory_GPUPf # -- Begin function _Z36__device_stub__use_global_memory_GPUPf
.p2align 4, 0x90
.type _Z36__device_stub__use_global_memory_GPUPf,@function
_Z36__device_stub__use_global_memory_GPUPf: # @_Z36__device_stub__use_global_memory_GPUPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z21use_global_memory_GPUPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z36__device_stub__use_global_memory_GPUPf, .Lfunc_end1-_Z36__device_stub__use_global_memory_GPUPf
.cfi_endproc
# -- End function
.globl _Z36__device_stub__use_shared_memory_GPUPf # -- Begin function _Z36__device_stub__use_shared_memory_GPUPf
.p2align 4, 0x90
.type _Z36__device_stub__use_shared_memory_GPUPf,@function
_Z36__device_stub__use_shared_memory_GPUPf: # @_Z36__device_stub__use_shared_memory_GPUPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z21use_shared_memory_GPUPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z36__device_stub__use_shared_memory_GPUPf, .Lfunc_end2-_Z36__device_stub__use_shared_memory_GPUPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $600, %rsp # imm = 0x258
.cfi_def_cfa_offset 624
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movabsq $4294967297, %r14 # imm = 0x100000001
leaq 127(%r14), %rbx
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movl $1073741824, 16(%rsp) # imm = 0x40000000
leaq 16(%rsp), %rax
movq %rax, (%rsp)
leaq 80(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movq %rsp, %r9
movl $_Z20use_local_memory_GPUf, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
leaq 8(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $512, %edx # imm = 0x200
movl $1, %ecx
callq hipMemcpy
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 64(%rsp)
leaq 24(%rsp), %rdi
leaq 48(%rsp), %rsi
movq %rsp, %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z21use_global_memory_GPUPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
movq 8(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $512, %edx # imm = 0x200
movl $2, %ecx
callq hipMemcpy
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 64(%rsp)
leaq 24(%rsp), %rdi
leaq 48(%rsp), %rsi
movq %rsp, %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z21use_shared_memory_GPUPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
movq 8(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $512, %edx # imm = 0x200
movl $1, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
xorl %eax, %eax
addq $600, %rsp # imm = 0x258
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20use_local_memory_GPUf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21use_global_memory_GPUPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21use_shared_memory_GPUPf, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20use_local_memory_GPUf,@object # @_Z20use_local_memory_GPUf
.section .rodata,"a",@progbits
.globl _Z20use_local_memory_GPUf
.p2align 3, 0x0
_Z20use_local_memory_GPUf:
.quad _Z35__device_stub__use_local_memory_GPUf
.size _Z20use_local_memory_GPUf, 8
.type _Z21use_global_memory_GPUPf,@object # @_Z21use_global_memory_GPUPf
.globl _Z21use_global_memory_GPUPf
.p2align 3, 0x0
_Z21use_global_memory_GPUPf:
.quad _Z36__device_stub__use_global_memory_GPUPf
.size _Z21use_global_memory_GPUPf, 8
.type _Z21use_shared_memory_GPUPf,@object # @_Z21use_shared_memory_GPUPf
.globl _Z21use_shared_memory_GPUPf
.p2align 3, 0x0
_Z21use_shared_memory_GPUPf:
.quad _Z36__device_stub__use_shared_memory_GPUPf
.size _Z21use_shared_memory_GPUPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20use_local_memory_GPUf"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z21use_global_memory_GPUPf"
.size .L__unnamed_2, 28
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z21use_shared_memory_GPUPf"
.size .L__unnamed_3, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__use_local_memory_GPUf
.addrsig_sym _Z36__device_stub__use_global_memory_GPUPf
.addrsig_sym _Z36__device_stub__use_shared_memory_GPUPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20use_local_memory_GPUf
.addrsig_sym _Z21use_global_memory_GPUPf
.addrsig_sym _Z21use_shared_memory_GPUPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "stdio.h"
#define COLUMNS 3
#define ROWS 2
__global__ void add(int *a, int *b, int *c)
{
int x = blockIdx.x;
int y = blockIdx.y;
int i = (COLUMNS * y) + x;
c[i] = a[i] + b[i];
}
int main()
{
int a[ROWS][COLUMNS], b[ROWS][COLUMNS], c[ROWS][COLUMNS];
int *dev_a, *dev_b, *dev_c;
cudaMalloc((void **)&dev_a, ROWS * COLUMNS * sizeof(int));
cudaMalloc((void **)&dev_b, ROWS * COLUMNS * sizeof(int));
cudaMalloc((void **)&dev_c, ROWS * COLUMNS * sizeof(int));
for (int y = 0; y < ROWS; y++) // Fill Arrays
for (int x = 0; x < COLUMNS; x++)
{
a[y][x] = x;
b[y][x] = y;
}
cudaMemcpy(dev_a, a, ROWS * COLUMNS * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, ROWS * COLUMNS * sizeof(int), cudaMemcpyHostToDevice);
dim3 grid(COLUMNS, ROWS);
add<<<grid, 1>>>(dev_a, dev_b, dev_c);
cudaMemcpy(c, dev_c, ROWS * COLUMNS * sizeof(int), cudaMemcpyDeviceToHost);
for (int y = 0; y < ROWS; y++)
{
for (int x = 0; x < COLUMNS; x++)
{
printf("[%d][%d]=%d ", y, x, c[y][x]);
}
printf("\n");
}
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002600 */
/*0050*/ IMAD R6, R3, 0x3, R6 ; /* 0x0000000303067824 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "stdio.h"
#define COLUMNS 3
#define ROWS 2
__global__ void add(int *a, int *b, int *c)
{
int x = blockIdx.x;
int y = blockIdx.y;
int i = (COLUMNS * y) + x;
c[i] = a[i] + b[i];
}
int main()
{
int a[ROWS][COLUMNS], b[ROWS][COLUMNS], c[ROWS][COLUMNS];
int *dev_a, *dev_b, *dev_c;
cudaMalloc((void **)&dev_a, ROWS * COLUMNS * sizeof(int));
cudaMalloc((void **)&dev_b, ROWS * COLUMNS * sizeof(int));
cudaMalloc((void **)&dev_c, ROWS * COLUMNS * sizeof(int));
for (int y = 0; y < ROWS; y++) // Fill Arrays
for (int x = 0; x < COLUMNS; x++)
{
a[y][x] = x;
b[y][x] = y;
}
cudaMemcpy(dev_a, a, ROWS * COLUMNS * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, ROWS * COLUMNS * sizeof(int), cudaMemcpyHostToDevice);
dim3 grid(COLUMNS, ROWS);
add<<<grid, 1>>>(dev_a, dev_b, dev_c);
cudaMemcpy(c, dev_c, ROWS * COLUMNS * sizeof(int), cudaMemcpyDeviceToHost);
for (int y = 0; y < ROWS; y++)
{
for (int x = 0; x < COLUMNS; x++)
{
printf("[%d][%d]=%d ", y, x, c[y][x]);
}
printf("\n");
}
return 0;
} | .file "tmpxft_00070829_00000000-6_vector-sum-block.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "[%d][%d]=%d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $152, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $24, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $24, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $24, %esi
call cudaMalloc@PLT
movl $0, 48(%rsp)
movl $0, 80(%rsp)
movl $1, 52(%rsp)
movl $0, 84(%rsp)
movl $2, 56(%rsp)
movl $0, 88(%rsp)
movl $0, 60(%rsp)
movl $1, 92(%rsp)
movl $1, 64(%rsp)
movl $1, 96(%rsp)
movl $2, 68(%rsp)
movl $1, 100(%rsp)
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $24, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $24, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $3, 24(%rsp)
movl $2, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L12:
leaq 112(%rsp), %rdi
movl $2, %ecx
movl $24, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L13:
movl 112(%rsp,%rbx,4), %r8d
movl %ebx, %ecx
movl $0, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L13
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movl 124(%rsp,%rbx,4), %r8d
movl %ebx, %ecx
movl $1, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L14
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L12
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "stdio.h"
#define COLUMNS 3
#define ROWS 2
__global__ void add(int *a, int *b, int *c)
{
int x = blockIdx.x;
int y = blockIdx.y;
int i = (COLUMNS * y) + x;
c[i] = a[i] + b[i];
}
int main()
{
int a[ROWS][COLUMNS], b[ROWS][COLUMNS], c[ROWS][COLUMNS];
int *dev_a, *dev_b, *dev_c;
cudaMalloc((void **)&dev_a, ROWS * COLUMNS * sizeof(int));
cudaMalloc((void **)&dev_b, ROWS * COLUMNS * sizeof(int));
cudaMalloc((void **)&dev_c, ROWS * COLUMNS * sizeof(int));
for (int y = 0; y < ROWS; y++) // Fill Arrays
for (int x = 0; x < COLUMNS; x++)
{
a[y][x] = x;
b[y][x] = y;
}
cudaMemcpy(dev_a, a, ROWS * COLUMNS * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, ROWS * COLUMNS * sizeof(int), cudaMemcpyHostToDevice);
dim3 grid(COLUMNS, ROWS);
add<<<grid, 1>>>(dev_a, dev_b, dev_c);
cudaMemcpy(c, dev_c, ROWS * COLUMNS * sizeof(int), cudaMemcpyDeviceToHost);
for (int y = 0; y < ROWS; y++)
{
for (int x = 0; x < COLUMNS; x++)
{
printf("[%d][%d]=%d ", y, x, c[y][x]);
}
printf("\n");
}
return 0;
} | #include <hip/hip_runtime.h>
#include "stdio.h"
#define COLUMNS 3
#define ROWS 2
__global__ void add(int *a, int *b, int *c)
{
int x = blockIdx.x;
int y = blockIdx.y;
int i = (COLUMNS * y) + x;
c[i] = a[i] + b[i];
}
int main()
{
int a[ROWS][COLUMNS], b[ROWS][COLUMNS], c[ROWS][COLUMNS];
int *dev_a, *dev_b, *dev_c;
hipMalloc((void **)&dev_a, ROWS * COLUMNS * sizeof(int));
hipMalloc((void **)&dev_b, ROWS * COLUMNS * sizeof(int));
hipMalloc((void **)&dev_c, ROWS * COLUMNS * sizeof(int));
for (int y = 0; y < ROWS; y++) // Fill Arrays
for (int x = 0; x < COLUMNS; x++)
{
a[y][x] = x;
b[y][x] = y;
}
hipMemcpy(dev_a, a, ROWS * COLUMNS * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, ROWS * COLUMNS * sizeof(int), hipMemcpyHostToDevice);
dim3 grid(COLUMNS, ROWS);
add<<<grid, 1>>>(dev_a, dev_b, dev_c);
hipMemcpy(c, dev_c, ROWS * COLUMNS * sizeof(int), hipMemcpyDeviceToHost);
for (int y = 0; y < ROWS; y++)
{
for (int x = 0; x < COLUMNS; x++)
{
printf("[%d][%d]=%d ", y, x, c[y][x]);
}
printf("\n");
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "stdio.h"
#define COLUMNS 3
#define ROWS 2
__global__ void add(int *a, int *b, int *c)
{
int x = blockIdx.x;
int y = blockIdx.y;
int i = (COLUMNS * y) + x;
c[i] = a[i] + b[i];
}
int main()
{
int a[ROWS][COLUMNS], b[ROWS][COLUMNS], c[ROWS][COLUMNS];
int *dev_a, *dev_b, *dev_c;
hipMalloc((void **)&dev_a, ROWS * COLUMNS * sizeof(int));
hipMalloc((void **)&dev_b, ROWS * COLUMNS * sizeof(int));
hipMalloc((void **)&dev_c, ROWS * COLUMNS * sizeof(int));
for (int y = 0; y < ROWS; y++) // Fill Arrays
for (int x = 0; x < COLUMNS; x++)
{
a[y][x] = x;
b[y][x] = y;
}
hipMemcpy(dev_a, a, ROWS * COLUMNS * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, ROWS * COLUMNS * sizeof(int), hipMemcpyHostToDevice);
dim3 grid(COLUMNS, ROWS);
add<<<grid, 1>>>(dev_a, dev_b, dev_c);
hipMemcpy(c, dev_c, ROWS * COLUMNS * sizeof(int), hipMemcpyDeviceToHost);
for (int y = 0; y < ROWS; y++)
{
for (int x = 0; x < COLUMNS; x++)
{
printf("[%d][%d]=%d ", y, x, c[y][x]);
}
printf("\n");
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s2, s15, 3
s_load_b64 s[0:1], s[0:1], 0x10
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "stdio.h"
#define COLUMNS 3
#define ROWS 2
__global__ void add(int *a, int *b, int *c)
{
int x = blockIdx.x;
int y = blockIdx.y;
int i = (COLUMNS * y) + x;
c[i] = a[i] + b[i];
}
int main()
{
int a[ROWS][COLUMNS], b[ROWS][COLUMNS], c[ROWS][COLUMNS];
int *dev_a, *dev_b, *dev_c;
hipMalloc((void **)&dev_a, ROWS * COLUMNS * sizeof(int));
hipMalloc((void **)&dev_b, ROWS * COLUMNS * sizeof(int));
hipMalloc((void **)&dev_c, ROWS * COLUMNS * sizeof(int));
for (int y = 0; y < ROWS; y++) // Fill Arrays
for (int x = 0; x < COLUMNS; x++)
{
a[y][x] = x;
b[y][x] = y;
}
hipMemcpy(dev_a, a, ROWS * COLUMNS * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, ROWS * COLUMNS * sizeof(int), hipMemcpyHostToDevice);
dim3 grid(COLUMNS, ROWS);
add<<<grid, 1>>>(dev_a, dev_b, dev_c);
hipMemcpy(c, dev_c, ROWS * COLUMNS * sizeof(int), hipMemcpyDeviceToHost);
for (int y = 0; y < ROWS; y++)
{
for (int x = 0; x < COLUMNS; x++)
{
printf("[%d][%d]=%d ", y, x, c[y][x]);
}
printf("\n");
}
return 0;
} | .text
.file "vector-sum-block.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $192, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
movl $24, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $24, %esi
callq hipMalloc
movq %rsp, %rdi
movl $24, %esi
callq hipMalloc
leaq 160(%rsp), %rax
leaq 128(%rsp), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_1: # %.preheader27
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %esi, (%rax,%rsi,4)
movl %edx, (%rcx,%rsi,4)
incq %rsi
cmpq $3, %rsi
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
leaq 1(%rdx), %rsi
addq $12, %rax
addq $12, %rcx
testq %rdx, %rdx
movq %rsi, %rdx
je .LBB1_1
# %bb.4:
movq 16(%rsp), %rdi
leaq 160(%rsp), %rsi
movl $24, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $24, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $8589934595, %rdi # imm = 0x200000003
movabsq $4294967297, %rdx # imm = 0x100000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq (%rsp), %rsi
leaq 96(%rsp), %rbx
movl $24, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %ecx
movl $.L.str, %edi
movl %r14d, %esi
movl %r15d, %edx
xorl %eax, %eax
callq printf
incq %r15
cmpq $3, %r15
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
movl $10, %edi
callq putchar@PLT
leaq 1(%r14), %rax
addq $12, %rbx
testq %r14, %r14
movq %rax, %r14
je .LBB1_7
# %bb.10:
xorl %eax, %eax
addq $192, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[%d][%d]=%d "
.size .L.str, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002600 */
/*0050*/ IMAD R6, R3, 0x3, R6 ; /* 0x0000000303067824 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s2, s15, 3
s_load_b64 s[0:1], s[0:1], 0x10
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00070829_00000000-6_vector-sum-block.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "[%d][%d]=%d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $152, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $24, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $24, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $24, %esi
call cudaMalloc@PLT
movl $0, 48(%rsp)
movl $0, 80(%rsp)
movl $1, 52(%rsp)
movl $0, 84(%rsp)
movl $2, 56(%rsp)
movl $0, 88(%rsp)
movl $0, 60(%rsp)
movl $1, 92(%rsp)
movl $1, 64(%rsp)
movl $1, 96(%rsp)
movl $2, 68(%rsp)
movl $1, 100(%rsp)
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $24, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $24, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $3, 24(%rsp)
movl $2, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L12:
leaq 112(%rsp), %rdi
movl $2, %ecx
movl $24, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L13:
movl 112(%rsp,%rbx,4), %r8d
movl %ebx, %ecx
movl $0, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L13
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movl 124(%rsp,%rbx,4), %r8d
movl %ebx, %ecx
movl $1, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L14
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L12
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vector-sum-block.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $192, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
movl $24, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $24, %esi
callq hipMalloc
movq %rsp, %rdi
movl $24, %esi
callq hipMalloc
leaq 160(%rsp), %rax
leaq 128(%rsp), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_1: # %.preheader27
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %esi, (%rax,%rsi,4)
movl %edx, (%rcx,%rsi,4)
incq %rsi
cmpq $3, %rsi
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
leaq 1(%rdx), %rsi
addq $12, %rax
addq $12, %rcx
testq %rdx, %rdx
movq %rsi, %rdx
je .LBB1_1
# %bb.4:
movq 16(%rsp), %rdi
leaq 160(%rsp), %rsi
movl $24, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $24, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $8589934595, %rdi # imm = 0x200000003
movabsq $4294967297, %rdx # imm = 0x100000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq (%rsp), %rsi
leaq 96(%rsp), %rbx
movl $24, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %ecx
movl $.L.str, %edi
movl %r14d, %esi
movl %r15d, %edx
xorl %eax, %eax
callq printf
incq %r15
cmpq $3, %r15
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
movl $10, %edi
callq putchar@PLT
leaq 1(%r14), %rax
addq $12, %rbx
testq %r14, %r14
movq %rax, %r14
je .LBB1_7
# %bb.10:
xorl %eax, %eax
addq $192, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[%d][%d]=%d "
.size .L.str, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //
// CUDA code to compute minimum distance between n points
//
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#define MAX_POINTS 1048576
#define BLOCK_SIZE 1024
#define M_LOG2E 1.44269504088896340736 //log2(e)
inline long double my_log(const long double x){
return log(x) * M_LOG2E;
}
int blocks; //log2(num_points);
int threads; //num_points/blocks;
int num_points;
// ----------------------------------------------------------------------------
// Kernel Function to compute distance between all pairs of points
// Input:
// X: X[i] = x-coordinate of the ith point
// Y: Y[i] = y-coordinate of the ith point
// n: number of points
//
// Output:
// D: D[0] = minimum distance
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// Compute minimum distance on host to check device computation
// Need to: modify the kernel functino to compute the minimum distance.
// You are allowed to make other changes to the code that facilitate
// parallelization on the GPU
//
// 1. You need to develop CUDA-based parallel code to compute the
// distance between the closest pair of points on a GPU
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// References
// ----------------------------------------------------------------------------
/*
__global__ void VecAdd(float* A, float* B, float* C, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
}
*/
/*
__global__ void MatMult(float* A, float* B, float* C, int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i < N && j < N)
C[i][j] = A[i][j] + B[i][j];
}
*/
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// Kernel function code goes here
// ----------------------------------------------------------------------------
__global__ void minimum_distance(float * X, float * Y, float * D, int n)
{
//CUDA version of the code
int i = blockIdx.y * blockDim.y + threadIdx.y;
//int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
if(threadIdx.y == 0)
{
D[0] = 10;
}
extern __shared__ float mins[];
__threadfence();
//if (i < n && j < n)
if(i<n)
{
for (int j = i+1; j < n; j++)
{
float dx = X[j]-X[i];
float dy = Y[j]-Y[i];
float Dij = sqrtf(dx*dx+dy*dy);
//__threadfence();
//mins local to the block
mins[threadIdx.x] = Dij;
__syncthreads();
}
}
//let the last block handle finding the actual minimum
if(i >= n)
{
//sort mins to
for(unsigned int s = blockDim.y/2; s > 0; s >>= 1)
{
if(threadIdx.y < s)
{
if (mins[threadIdx.y] > mins[threadIdx.y + s])
{
mins[threadIdx.y] = mins[threadIdx.y + s];
}
}
__syncthreads();
}
//now update global minimum
if(threadIdx.y == 0)
{
if(D[0] > mins[0])
{
D[0] = mins[0];
}
}
}
//D[0] = -15;
}
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// Main program - initializes points and computes minimum distance
// between the points
// ----------------------------------------------------------------------------
int main(int argc, char* argv[]) {
// Host Data
float * hVx; // host x-coordinate array
float * hVy; // host y-coordinate array
float * hmin_dist; // minimum value on host
// Device Data
float * dVx; // device x-coordinate array
float * dVy; // device x-coordinate array
float * dmin_dist; // minimum value on device
int i, j, size;// num_points, blocks, threads;
float dx, dy, Dij, distance;
unsigned int seed = 0;
cudaEvent_t start, stop; // GPU timing variables
struct timeval cpu_start, cpu_stop; // CPU timing variables
float time_array[10];
// Timing initializations
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Check input
if (argc != 2) {
printf("Use: %s <number of points>\n", argv[0]);
exit(0);
}
if ((num_points = atoi(argv[argc-1])) > MAX_POINTS) {
printf("Maximum number of points allowed: %d\n", MAX_POINTS);
exit(0);
}
// Allocate host coordinate arrays
size = num_points * sizeof(float);
hVx = (float *) malloc(size);
hVy = (float *) malloc(size);
hmin_dist = (float *) malloc(sizeof(float));
// Initialize points
for (i = 0; i < num_points; i++) {
hVx[i] = (float)(rand_r(&seed))/(float)(RAND_MAX);
hVy[i] = (float)(rand_r(&seed))/(float)(RAND_MAX);
}
// Allocate device coordinate arrays
cudaMalloc(&dVx, size);
cudaMalloc(&dVy, size);
cudaMalloc(&dmin_dist, sizeof(float));
// Copy coordinate arrays from host memory to device memory
cudaEventRecord( start, 0 );
cudaMemcpy(dVx, hVx, size, cudaMemcpyHostToDevice);
cudaMemcpy(dVy, hVy, size, cudaMemcpyHostToDevice);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&(time_array[0]), start, stop);
// Invoke kernel
cudaEventRecord(start, 0);
// ------------------------------------------------------------
//
// Invoke kernel function here
//
// ------------------------------------------------------------
//choose the number of blocks and points
threads = 16; //num_points/blocks;
blocks = num_points/threads; //my_log(num_points);
minimum_distance<<<(blocks), threads>>>(dVx, dVy, dmin_dist, num_points);
//alternative declaration
//dim3 block(16,16);
//dim3 grid((num_points + 15)/16, (num_points + 15)/16);
//minimum_distance<<<grid, block>>>(dVx, dVy, dmin_dist, num_points);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&(time_array[1]), start, stop);
// Copy result from device memory to host memory
cudaEventRecord(start, 0);
//this was wrong! converting size to sizeof(float)
cudaMemcpy(hmin_dist, dmin_dist, sizeof(float), cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&(time_array[2]), start, stop);
printf("Number of Points = %d\n", num_points);
printf("GPU Host-to-device = %f ms \n", time_array[0]);
printf("GPU execution time = %f ms \n", time_array[1]);
printf("GPU Device-to-host = %f ms \n", time_array[2]);
printf("Minimum distance (GPU) = %e\n", hmin_dist[0]);
gettimeofday(&cpu_start, NULL);
dx = hVx[1]-hVx[0];
dy = hVy[1]-hVy[0];
distance = sqrtf(dx*dx+dy*dy);
for (i = 0; i < num_points; i++) {
for (j = i+1; j < num_points; j++) {
dx = hVx[j]-hVx[i];
dy = hVy[j]-hVy[i];
Dij = sqrtf(dx*dx+dy*dy);
if (distance > Dij) distance = Dij;
}
}
gettimeofday(&cpu_stop, NULL);
time_array[3] = 1000*(cpu_stop.tv_sec-cpu_start.tv_sec)
+0.000001*(cpu_stop.tv_usec-cpu_start.tv_usec);
printf("CPU execution time = %f ms\n", time_array[3]);
printf("Minimum distance (CPU) = %e\n", distance);
// Free device memory
cudaFree(dVx);
cudaFree(dVy);
cudaFree(dmin_dist);
// Free host memory
free(hVx);
free(hVy);
free(hmin_dist);
return 0;
}
// ---------------------------------------------------------------------------- | code for sm_80
Function : _Z16minimum_distancePfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e220000002200 */
/*0020*/ S2UR UR4, SR_CTAID.Y ; /* 0x00000000000479c3 */
/* 0x000e620000002600 */
/*0030*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fe20000000f00 */
/*0050*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe40000000a00 */
/*0060*/ ULDC UR5, c[0x0][0x4] ; /* 0x0000010000057ab9 */
/* 0x000fe20000000800 */
/*0070*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fe20003f05270 */
/*0080*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x002fcc000f8e023f */
/*0090*/ IADD3 R4, R7, UR4, RZ ; /* 0x0000000407047c10 */
/* 0x000fc8000fffe0ff */
/*00a0*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fe40003f26270 */
/*00b0*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, 0x41200000 ; /* 0x41200000ff058424 */
/* 0x000fca00078e00ff */
/*00c0*/ @!P0 STG.E [R2.64], R5 ; /* 0x0000000502008986 */
/* 0x0001e2000c101908 */
/*00d0*/ MEMBAR.SC.GPU ; /* 0x0000000000007992 */
/* 0x000fec0000002000 */
/*00e0*/ ERRBAR; /* 0x00000000000079ab */
/* 0x000fc00000000000 */
/*00f0*/ CCTL.IVALL ; /* 0x00000000ff00798f */
/* 0x000fca0002000000 */
/*0100*/ @!P1 BRA 0x2a0 ; /* 0x0000019000009947 */
/* 0x000fea0003800000 */
/*0110*/ ULDC UR5, c[0x0][0x4] ; /* 0x0000010000057ab9 */
/* 0x000fe40000000800 */
/*0120*/ USHF.R.U32.HI UR5, URZ, 0x1, UR5 ; /* 0x000000013f057899 */
/* 0x000fcc0008011605 */
/*0130*/ ISETP.NE.AND P1, PT, RZ, UR5, PT ; /* 0x00000005ff007c0c */
/* 0x000fda000bf25270 */
/*0140*/ @!P1 BRA 0x230 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*0150*/ MOV R0, UR5 ; /* 0x0000000500007c02 */
/* 0x000fe20008000f00 */
/*0160*/ IMAD.SHL.U32 R5, R7, 0x4, RZ ; /* 0x0000000407057824 */
/* 0x001fc600078e00ff */
/*0170*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*0180*/ @P1 BRA 0x1e0 ; /* 0x0000005000001947 */
/* 0x001fea0003800000 */
/*0190*/ LEA R6, R0, R5, 0x2 ; /* 0x0000000500067211 */
/* 0x000fe200078e10ff */
/*01a0*/ LDS R4, [R7.X4] ; /* 0x0000000007047984 */
/* 0x000fea0000004800 */
/*01b0*/ LDS R6, [R6] ; /* 0x0000000006067984 */
/* 0x000e240000000800 */
/*01c0*/ FSETP.GT.AND P1, PT, R4, R6, PT ; /* 0x000000060400720b */
/* 0x001fda0003f24000 */
/*01d0*/ @P1 STS [R7.X4], R6 ; /* 0x0000000607001388 */
/* 0x0001e40000004800 */
/*01e0*/ SHF.R.U32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fe20000011600 */
/*01f0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0200*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe40000010000 */
/*0210*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f25270 */
/*0220*/ @P1 BRA 0x170 ; /* 0xffffff4000001947 */
/* 0x000fea000383ffff */
/*0230*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0240*/ LDG.E R0, [R2.64] ; /* 0x0000000802007981 */
/* 0x000ea8000c1e1900 */
/*0250*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x001ea40000000800 */
/*0260*/ FSETP.GT.AND P0, PT, R0, R5, PT ; /* 0x000000050000720b */
/* 0x004fda0003f04000 */
/*0270*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0280*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101908 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ IADD3 R6, R4, 0x1, RZ ; /* 0x0000000104067810 */
/* 0x000fc80007ffe0ff */
/*02b0*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*02c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02d0*/ LOP3.LUT R2, RZ, UR4, RZ, 0x33, !PT ; /* 0x00000004ff027c12 */
/* 0x001fe2000f8e33ff */
/*02e0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*02f0*/ UMOV UR5, 0x2 ; /* 0x0000000200057882 */
/* 0x000fe20000000000 */
/*0300*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0310*/ IADD3 R2, -R7, c[0x0][0x178], R2 ; /* 0x00005e0007027a10 */
/* 0x000fe20007ffe102 */
/*0320*/ ULDC UR6, c[0x0][0x178] ; /* 0x00005e0000067ab9 */
/* 0x000fe40000000800 */
/*0330*/ UIADD3 UR5, -UR4, UR6, -UR5 ; /* 0x0000000604057290 */
/* 0x000fe2000fffe905 */
/*0340*/ LOP3.LUT P0, R12, R2, 0x3, RZ, 0xc0, !PT ; /* 0x00000003020c7812 */
/* 0x000fe2000780c0ff */
/*0350*/ IMAD.WIDE R2, R4, R11, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc800078e020b */
/*0360*/ IADD3 R7, -R7, UR5, RZ ; /* 0x0000000507077c10 */
/* 0x000fe2000fffe1ff */
/*0370*/ IMAD.WIDE R4, R4, R11, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fce00078e020b */
/*0380*/ @!P0 BRA 0x5b0 ; /* 0x0000022000008947 */
/* 0x000fea0003800000 */
/*0390*/ IMAD.WIDE R8, R6, R11, c[0x0][0x168] ; /* 0x00005a0006087625 */
/* 0x000fc800078e020b */
/*03a0*/ IMAD.WIDE R10, R6, R11, c[0x0][0x160] ; /* 0x00005800060a7625 */
/* 0x000fc800078e020b */
/*03b0*/ LDG.E R15, [R4.64] ; /* 0x00000008040f7981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R16, [R8.64] ; /* 0x0000000808107981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R14, [R10.64] ; /* 0x000000080a0e7981 */
/* 0x000ee8000c1e1900 */
/*03e0*/ LDG.E R13, [R2.64] ; /* 0x00000008020d7981 */
/* 0x000ee2000c1e1900 */
/*03f0*/ BSSY B0, 0x500 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0400*/ FADD R15, -R15, R16 ; /* 0x000000100f0f7221 */
/* 0x004fc40000000100 */
/*0410*/ FADD R13, -R13, R14 ; /* 0x0000000e0d0d7221 */
/* 0x008fe40000000100 */
/*0420*/ FMUL R14, R15, R15 ; /* 0x0000000f0f0e7220 */
/* 0x000fc80000400000 */
/*0430*/ FFMA R18, R13, R13, R14 ; /* 0x0000000d0d127223 */
/* 0x000fc8000000000e */
/*0440*/ MUFU.RSQ R15, R18 ; /* 0x00000012000f7308 */
/* 0x0002a20000001400 */
/*0450*/ IADD3 R13, R18, -0xd000000, RZ ; /* 0xf3000000120d7810 */
/* 0x000fc80007ffe0ff */
/*0460*/ ISETP.GT.U32.AND P0, PT, R13, 0x727fffff, PT ; /* 0x727fffff0d00780c */
/* 0x000fda0003f04070 */
/*0470*/ @!P0 BRA 0x4b0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0480*/ MOV R19, 0x4a0 ; /* 0x000004a000137802 */
/* 0x006fe40000000f00 */
/*0490*/ CALL.REL.NOINC 0xd20 ; /* 0x0000088000007944 */
/* 0x001fea0003c00000 */
/*04a0*/ BRA 0x4f0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*04b0*/ FMUL.FTZ R13, R18, R15 ; /* 0x0000000f120d7220 */
/* 0x006fe40000410000 */
/*04c0*/ FMUL.FTZ R15, R15, 0.5 ; /* 0x3f0000000f0f7820 */
/* 0x000fe40000410000 */
/*04d0*/ FFMA R14, -R13, R13, R18 ; /* 0x0000000d0d0e7223 */
/* 0x000fc80000000112 */
/*04e0*/ FFMA R13, R14, R15, R13 ; /* 0x0000000f0e0d7223 */
/* 0x000fe4000000000d */
/*04f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0500*/ IADD3 R12, R12, -0x1, RZ ; /* 0xffffffff0c0c7810 */
/* 0x000fe20007ffe0ff */
/*0510*/ STS [R0.X4], R13 ; /* 0x0000000d00007388 */
/* 0x0011e20000004800 */
/*0520*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe60003800000 */
/*0530*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0540*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f05270 */
/*0550*/ IADD3 R8, P1, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe40007f3e0ff */
/*0560*/ IADD3 R10, P2, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f5e0ff */
/*0570*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe40007ffe0ff */
/*0580*/ IADD3.X R9, RZ, R9, RZ, P1, !PT ; /* 0x00000009ff097210 */
/* 0x000fe40000ffe4ff */
/*0590*/ IADD3.X R11, RZ, R11, RZ, P2, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fc600017fe4ff */
/*05a0*/ @P0 BRA 0x3b0 ; /* 0xfffffe0000000947 */
/* 0x001fea000383ffff */
/*05b0*/ ISETP.GE.U32.AND P0, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fda0003f06070 */
/*05c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*05d0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*05e0*/ IMAD.WIDE R8, R6, R9, c[0x2][0x0] ; /* 0x0080000006087625 */
/* 0x000fca00078e0209 */
/*05f0*/ IADD3 R10, P0, R8.reuse, c[0x0][0x160], RZ ; /* 0x00005800080a7a10 */
/* 0x040fe40007f1e0ff */
/*0600*/ IADD3 R8, P1, R8, c[0x0][0x168], RZ ; /* 0x00005a0008087a10 */
/* 0x000fe40007f3e0ff */
/*0610*/ IADD3.X R11, R9.reuse, c[0x0][0x164], RZ, P0, !PT ; /* 0x00005900090b7a10 */
/* 0x040fe400007fe4ff */
/*0620*/ IADD3.X R9, R9, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0009097a10 */
/* 0x000fe40000ffe4ff */
/*0630*/ LDG.E R13, [R4.64] ; /* 0x00000008040d7981 */
/* 0x000ea8000c1e1900 */
/*0640*/ LDG.E R14, [R8.64+-0x8] ; /* 0xfffff808080e7981 */
/* 0x000ea8000c1e1900 */
/*0650*/ LDG.E R7, [R2.64] ; /* 0x0000000802077981 */
/* 0x000ee8000c1e1900 */
/*0660*/ LDG.E R12, [R10.64+-0x8] ; /* 0xfffff8080a0c7981 */
/* 0x000ee2000c1e1900 */
/*0670*/ BSSY B0, 0x790 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0680*/ FADD R13, -R13, R14 ; /* 0x0000000e0d0d7221 */
/* 0x004fc40000000100 */
/*0690*/ FADD R7, -R7, R12 ; /* 0x0000000c07077221 */
/* 0x008fe40000000100 */
/*06a0*/ FMUL R12, R13, R13 ; /* 0x0000000d0d0c7220 */
/* 0x000fc80000400000 */
/*06b0*/ FFMA R18, R7, R7, R12 ; /* 0x0000000707127223 */
/* 0x000fc8000000000c */
/*06c0*/ MUFU.RSQ R13, R18 ; /* 0x00000012000d7308 */
/* 0x0002a20000001400 */
/*06d0*/ IADD3 R7, R18, -0xd000000, RZ ; /* 0xf300000012077810 */
/* 0x000fc80007ffe0ff */
/*06e0*/ ISETP.GT.U32.AND P0, PT, R7, 0x727fffff, PT ; /* 0x727fffff0700780c */
/* 0x000fda0003f04070 */
/*06f0*/ @!P0 BRA 0x740 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0700*/ MOV R19, 0x720 ; /* 0x0000072000137802 */
/* 0x006fe40000000f00 */
/*0710*/ CALL.REL.NOINC 0xd20 ; /* 0x0000060000007944 */
/* 0x001fea0003c00000 */
/*0720*/ MOV R7, R13 ; /* 0x0000000d00077202 */
/* 0x000fe20000000f00 */
/*0730*/ BRA 0x780 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0740*/ FMUL.FTZ R7, R18, R13 ; /* 0x0000000d12077220 */
/* 0x006fe40000410000 */
/*0750*/ FMUL.FTZ R13, R13, 0.5 ; /* 0x3f0000000d0d7820 */
/* 0x000fe40000410000 */
/*0760*/ FFMA R12, -R7, R7, R18 ; /* 0x00000007070c7223 */
/* 0x000fc80000000112 */
/*0770*/ FFMA R7, R12, R13, R7 ; /* 0x0000000d0c077223 */
/* 0x000fe40000000007 */
/*0780*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0790*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0011e20000004800 */
/*07a0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe60003800000 */
/*07b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*07c0*/ LDG.E R14, [R4.64] ; /* 0x00000008040e7981 */
/* 0x000ea8000c1e1900 */
/*07d0*/ LDG.E R15, [R8.64+-0x4] ; /* 0xfffffc08080f7981 */
/* 0x000ea8000c1e1900 */
/*07e0*/ LDG.E R12, [R2.64] ; /* 0x00000008020c7981 */
/* 0x000ee8000c1e1900 */
/*07f0*/ LDG.E R13, [R10.64+-0x4] ; /* 0xfffffc080a0d7981 */
/* 0x000ee2000c1e1900 */
/*0800*/ BSSY B0, 0x940 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0810*/ FADD R14, -R14, R15 ; /* 0x0000000f0e0e7221 */
/* 0x004fc40000000100 */
/*0820*/ FADD R12, -R12, R13 ; /* 0x0000000d0c0c7221 */
/* 0x008fe40000000100 */
/*0830*/ FMUL R13, R14, R14 ; /* 0x0000000e0e0d7220 */
/* 0x000fc80000400000 */
/*0840*/ FFMA R18, R12, R12, R13 ; /* 0x0000000c0c127223 */
/* 0x000fc8000000000d */
/*0850*/ MUFU.RSQ R13, R18 ; /* 0x00000012000d7308 */
/* 0x0002a20000001400 */
/*0860*/ IADD3 R7, R18, -0xd000000, RZ ; /* 0xf300000012077810 */
/* 0x001fc80007ffe0ff */
/*0870*/ ISETP.GT.U32.AND P0, PT, R7, 0x727fffff, PT ; /* 0x727fffff0700780c */
/* 0x000fda0003f04070 */
/*0880*/ @!P0 BRA 0x8f0 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0890*/ BSSY B1, 0x8d0 ; /* 0x0000003000017945 */
/* 0x006fe20003800000 */
/*08a0*/ MOV R19, 0x8c0 ; /* 0x000008c000137802 */
/* 0x000fe40000000f00 */
/*08b0*/ CALL.REL.NOINC 0xd20 ; /* 0x0000046000007944 */
/* 0x000fea0003c00000 */
/*08c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08d0*/ MOV R7, R13 ; /* 0x0000000d00077202 */
/* 0x000fe20000000f00 */
/*08e0*/ BRA 0x930 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*08f0*/ FMUL.FTZ R7, R18, R13 ; /* 0x0000000d12077220 */
/* 0x006fe40000410000 */
/*0900*/ FMUL.FTZ R13, R13, 0.5 ; /* 0x3f0000000d0d7820 */
/* 0x000fe40000410000 */
/*0910*/ FFMA R12, -R7, R7, R18 ; /* 0x00000007070c7223 */
/* 0x000fc80000000112 */
/*0920*/ FFMA R7, R12, R13, R7 ; /* 0x0000000d0c077223 */
/* 0x000fe40000000007 */
/*0930*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0940*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0001e80000004800 */
/*0950*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0960*/ LDG.E R14, [R4.64] ; /* 0x00000008040e7981 */
/* 0x000ea8000c1e1900 */
/*0970*/ LDG.E R15, [R8.64] ; /* 0x00000008080f7981 */
/* 0x000ea8000c1e1900 */
/*0980*/ LDG.E R12, [R2.64] ; /* 0x00000008020c7981 */
/* 0x000ee8000c1e1900 */
/*0990*/ LDG.E R13, [R10.64] ; /* 0x000000080a0d7981 */
/* 0x000ee2000c1e1900 */
/*09a0*/ BSSY B0, 0xae0 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*09b0*/ FADD R14, -R14, R15 ; /* 0x0000000f0e0e7221 */
/* 0x004fc40000000100 */
/*09c0*/ FADD R12, -R12, R13 ; /* 0x0000000d0c0c7221 */
/* 0x008fe40000000100 */
/*09d0*/ FMUL R13, R14, R14 ; /* 0x0000000e0e0d7220 */
/* 0x000fc80000400000 */
/*09e0*/ FFMA R18, R12, R12, R13 ; /* 0x0000000c0c127223 */
/* 0x000fc8000000000d */
/*09f0*/ MUFU.RSQ R13, R18 ; /* 0x00000012000d7308 */
/* 0x0000620000001400 */
/*0a00*/ IADD3 R12, R18, -0xd000000, RZ ; /* 0xf3000000120c7810 */
/* 0x000fc80007ffe0ff */
/*0a10*/ ISETP.GT.U32.AND P0, PT, R12, 0x727fffff, PT ; /* 0x727fffff0c00780c */
/* 0x000fda0003f04070 */
/*0a20*/ @!P0 BRA 0xa90 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0a30*/ BSSY B1, 0xa70 ; /* 0x0000003000017945 */
/* 0x003fe20003800000 */
/*0a40*/ MOV R19, 0xa60 ; /* 0x00000a6000137802 */
/* 0x000fe40000000f00 */
/*0a50*/ CALL.REL.NOINC 0xd20 ; /* 0x000002c000007944 */
/* 0x000fea0003c00000 */
/*0a60*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0a70*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000d */
/*0a80*/ BRA 0xad0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0a90*/ FMUL.FTZ R7, R18, R13 ; /* 0x0000000d12077220 */
/* 0x003fe40000410000 */
/*0aa0*/ FMUL.FTZ R13, R13, 0.5 ; /* 0x3f0000000d0d7820 */
/* 0x000fe40000410000 */
/*0ab0*/ FFMA R12, -R7, R7, R18 ; /* 0x00000007070c7223 */
/* 0x000fc80000000112 */
/*0ac0*/ FFMA R7, R12, R13, R7 ; /* 0x0000000d0c077223 */
/* 0x000fe40000000007 */
/*0ad0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0ae0*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0001e80000004800 */
/*0af0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0b00*/ LDG.E R14, [R4.64] ; /* 0x00000008040e7981 */
/* 0x000ea8000c1e1900 */
/*0b10*/ LDG.E R15, [R8.64+0x4] ; /* 0x00000408080f7981 */
/* 0x000ea8000c1e1900 */
/*0b20*/ LDG.E R12, [R2.64] ; /* 0x00000008020c7981 */
/* 0x000ee8000c1e1900 */
/*0b30*/ LDG.E R13, [R10.64+0x4] ; /* 0x000004080a0d7981 */
/* 0x000ee2000c1e1900 */
/*0b40*/ BSSY B0, 0xc80 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0b50*/ FADD R14, -R14, R15 ; /* 0x0000000f0e0e7221 */
/* 0x004fc40000000100 */
/*0b60*/ FADD R12, -R12, R13 ; /* 0x0000000d0c0c7221 */
/* 0x008fe40000000100 */
/*0b70*/ FMUL R13, R14, R14 ; /* 0x0000000e0e0d7220 */
/* 0x000fc80000400000 */
/*0b80*/ FFMA R18, R12, R12, R13 ; /* 0x0000000c0c127223 */
/* 0x000fc8000000000d */
/*0b90*/ MUFU.RSQ R13, R18 ; /* 0x00000012000d7308 */
/* 0x0000620000001400 */
/*0ba0*/ IADD3 R12, R18, -0xd000000, RZ ; /* 0xf3000000120c7810 */
/* 0x000fc80007ffe0ff */
/*0bb0*/ ISETP.GT.U32.AND P0, PT, R12, 0x727fffff, PT ; /* 0x727fffff0c00780c */
/* 0x000fda0003f04070 */
/*0bc0*/ @!P0 BRA 0xc30 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0bd0*/ BSSY B1, 0xc10 ; /* 0x0000003000017945 */
/* 0x003fe20003800000 */
/*0be0*/ MOV R19, 0xc00 ; /* 0x00000c0000137802 */
/* 0x000fe40000000f00 */
/*0bf0*/ CALL.REL.NOINC 0xd20 ; /* 0x0000012000007944 */
/* 0x000fea0003c00000 */
/*0c00*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0c10*/ MOV R7, R13 ; /* 0x0000000d00077202 */
/* 0x000fe20000000f00 */
/*0c20*/ BRA 0xc70 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0c30*/ FMUL.FTZ R7, R18, R13 ; /* 0x0000000d12077220 */
/* 0x003fe40000410000 */
/*0c40*/ FMUL.FTZ R13, R13, 0.5 ; /* 0x3f0000000d0d7820 */
/* 0x000fe40000410000 */
/*0c50*/ FFMA R12, -R7, R7, R18 ; /* 0x00000007070c7223 */
/* 0x000fc80000000112 */
/*0c60*/ FFMA R7, R12, R13, R7 ; /* 0x0000000d0c077223 */
/* 0x000fe40000000007 */
/*0c70*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0c80*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe20007ffe0ff */
/*0c90*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0001e80000004800 */
/*0ca0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0cb0*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fe40003f06270 */
/*0cc0*/ IADD3 R8, P2, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fe40007f5e0ff */
/*0cd0*/ IADD3 R10, P1, R10, 0x10, RZ ; /* 0x000000100a0a7810 */
/* 0x000fc60007f3e0ff */
/*0ce0*/ IMAD.X R9, RZ, RZ, R9, P2 ; /* 0x000000ffff097224 */
/* 0x000fe200010e0609 */
/*0cf0*/ IADD3.X R11, RZ, R11, RZ, P1, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fca0000ffe4ff */
/*0d00*/ @!P0 BRA 0x630 ; /* 0xfffff92000008947 */
/* 0x001fea000383ffff */
/*0d10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d20*/ LOP3.LUT P0, RZ, R18, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff12ff7812 */
/* 0x000fda000780c0ff */
/*0d30*/ @!P0 MOV R13, R18 ; /* 0x00000012000d8202 */
/* 0x000fe20000000f00 */
/*0d40*/ @!P0 BRA 0xe50 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0d50*/ FSETP.GEU.FTZ.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720b */
/* 0x000fda0003f1e000 */
/*0d60*/ @!P0 MOV R13, 0x7fffffff ; /* 0x7fffffff000d8802 */
/* 0x000fe20000000f00 */
/*0d70*/ @!P0 BRA 0xe50 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0d80*/ FSETP.GTU.FTZ.AND P0, PT, |R18|, +INF , PT ; /* 0x7f8000001200780b */
/* 0x000fda0003f1c200 */
/*0d90*/ @P0 FADD.FTZ R13, R18, 1 ; /* 0x3f800000120d0421 */
/* 0x000fe20000010000 */
/*0da0*/ @P0 BRA 0xe50 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0db0*/ FSETP.NEU.FTZ.AND P0, PT, |R18|, +INF , PT ; /* 0x7f8000001200780b */
/* 0x000fda0003f1d200 */
/*0dc0*/ @P0 FFMA R14, R18, 1.84467440737095516160e+19, RZ ; /* 0x5f800000120e0823 */
/* 0x000fc800000000ff */
/*0dd0*/ @P0 MUFU.RSQ R13, R14 ; /* 0x0000000e000d0308 */
/* 0x000e240000001400 */
/*0de0*/ @P0 FMUL.FTZ R15, R14, R13 ; /* 0x0000000d0e0f0220 */
/* 0x001fe40000410000 */
/*0df0*/ @P0 FMUL.FTZ R17, R13, 0.5 ; /* 0x3f0000000d110820 */
/* 0x000fe40000410000 */
/*0e00*/ @P0 FADD.FTZ R16, -R15.reuse, -RZ ; /* 0x800000ff0f100221 */
/* 0x040fe40000010100 */
/*0e10*/ @!P0 IMAD.MOV.U32 R13, RZ, RZ, R18 ; /* 0x000000ffff0d8224 */
/* 0x000fe400078e0012 */
/*0e20*/ @P0 FFMA R16, R15, R16, R14 ; /* 0x000000100f100223 */
/* 0x000fc8000000000e */
/*0e30*/ @P0 FFMA R16, R16, R17, R15 ; /* 0x0000001110100223 */
/* 0x000fc8000000000f */
/*0e40*/ @P0 FMUL.FTZ R13, R16, 2.3283064365386962891e-10 ; /* 0x2f800000100d0820 */
/* 0x000fe40000410000 */
/*0e50*/ HFMA2.MMA R15, -RZ, RZ, 0, 0 ; /* 0x00000000ff0f7435 */
/* 0x000fe200000001ff */
/*0e60*/ MOV R14, R19 ; /* 0x00000013000e7202 */
/* 0x000fca0000000f00 */
/*0e70*/ RET.REL.NODEC R14 0x0 ; /* 0xfffff1800e007950 */
/* 0x000fea0003c3ffff */
/*0e80*/ BRA 0xe80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// CUDA code to compute minimum distance between n points
//
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#define MAX_POINTS 1048576
#define BLOCK_SIZE 1024
#define M_LOG2E 1.44269504088896340736 //log2(e)
inline long double my_log(const long double x){
return log(x) * M_LOG2E;
}
int blocks; //log2(num_points);
int threads; //num_points/blocks;
int num_points;
// ----------------------------------------------------------------------------
// Kernel Function to compute distance between all pairs of points
// Input:
// X: X[i] = x-coordinate of the ith point
// Y: Y[i] = y-coordinate of the ith point
// n: number of points
//
// Output:
// D: D[0] = minimum distance
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// Compute minimum distance on host to check device computation
// Need to: modify the kernel functino to compute the minimum distance.
// You are allowed to make other changes to the code that facilitate
// parallelization on the GPU
//
// 1. You need to develop CUDA-based parallel code to compute the
// distance between the closest pair of points on a GPU
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// References
// ----------------------------------------------------------------------------
/*
__global__ void VecAdd(float* A, float* B, float* C, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
}
*/
/*
__global__ void MatMult(float* A, float* B, float* C, int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i < N && j < N)
C[i][j] = A[i][j] + B[i][j];
}
*/
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// Kernel function code goes here
// ----------------------------------------------------------------------------
__global__ void minimum_distance(float * X, float * Y, float * D, int n)
{
//CUDA version of the code
int i = blockIdx.y * blockDim.y + threadIdx.y;
//int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
if(threadIdx.y == 0)
{
D[0] = 10;
}
extern __shared__ float mins[];
__threadfence();
//if (i < n && j < n)
if(i<n)
{
for (int j = i+1; j < n; j++)
{
float dx = X[j]-X[i];
float dy = Y[j]-Y[i];
float Dij = sqrtf(dx*dx+dy*dy);
//__threadfence();
//mins local to the block
mins[threadIdx.x] = Dij;
__syncthreads();
}
}
//let the last block handle finding the actual minimum
if(i >= n)
{
//sort mins to
for(unsigned int s = blockDim.y/2; s > 0; s >>= 1)
{
if(threadIdx.y < s)
{
if (mins[threadIdx.y] > mins[threadIdx.y + s])
{
mins[threadIdx.y] = mins[threadIdx.y + s];
}
}
__syncthreads();
}
//now update global minimum
if(threadIdx.y == 0)
{
if(D[0] > mins[0])
{
D[0] = mins[0];
}
}
}
//D[0] = -15;
}
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// Main program - initializes points and computes minimum distance
// between the points
// ----------------------------------------------------------------------------
int main(int argc, char* argv[]) {
// Host Data
float * hVx; // host x-coordinate array
float * hVy; // host y-coordinate array
float * hmin_dist; // minimum value on host
// Device Data
float * dVx; // device x-coordinate array
float * dVy; // device x-coordinate array
float * dmin_dist; // minimum value on device
int i, j, size;// num_points, blocks, threads;
float dx, dy, Dij, distance;
unsigned int seed = 0;
cudaEvent_t start, stop; // GPU timing variables
struct timeval cpu_start, cpu_stop; // CPU timing variables
float time_array[10];
// Timing initializations
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Check input
if (argc != 2) {
printf("Use: %s <number of points>\n", argv[0]);
exit(0);
}
if ((num_points = atoi(argv[argc-1])) > MAX_POINTS) {
printf("Maximum number of points allowed: %d\n", MAX_POINTS);
exit(0);
}
// Allocate host coordinate arrays
size = num_points * sizeof(float);
hVx = (float *) malloc(size);
hVy = (float *) malloc(size);
hmin_dist = (float *) malloc(sizeof(float));
// Initialize points
for (i = 0; i < num_points; i++) {
hVx[i] = (float)(rand_r(&seed))/(float)(RAND_MAX);
hVy[i] = (float)(rand_r(&seed))/(float)(RAND_MAX);
}
// Allocate device coordinate arrays
cudaMalloc(&dVx, size);
cudaMalloc(&dVy, size);
cudaMalloc(&dmin_dist, sizeof(float));
// Copy coordinate arrays from host memory to device memory
cudaEventRecord( start, 0 );
cudaMemcpy(dVx, hVx, size, cudaMemcpyHostToDevice);
cudaMemcpy(dVy, hVy, size, cudaMemcpyHostToDevice);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&(time_array[0]), start, stop);
// Invoke kernel
cudaEventRecord(start, 0);
// ------------------------------------------------------------
//
// Invoke kernel function here
//
// ------------------------------------------------------------
//choose the number of blocks and points
threads = 16; //num_points/blocks;
blocks = num_points/threads; //my_log(num_points);
minimum_distance<<<(blocks), threads>>>(dVx, dVy, dmin_dist, num_points);
//alternative declaration
//dim3 block(16,16);
//dim3 grid((num_points + 15)/16, (num_points + 15)/16);
//minimum_distance<<<grid, block>>>(dVx, dVy, dmin_dist, num_points);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&(time_array[1]), start, stop);
// Copy result from device memory to host memory
cudaEventRecord(start, 0);
//this was wrong! converting size to sizeof(float)
cudaMemcpy(hmin_dist, dmin_dist, sizeof(float), cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&(time_array[2]), start, stop);
printf("Number of Points = %d\n", num_points);
printf("GPU Host-to-device = %f ms \n", time_array[0]);
printf("GPU execution time = %f ms \n", time_array[1]);
printf("GPU Device-to-host = %f ms \n", time_array[2]);
printf("Minimum distance (GPU) = %e\n", hmin_dist[0]);
gettimeofday(&cpu_start, NULL);
dx = hVx[1]-hVx[0];
dy = hVy[1]-hVy[0];
distance = sqrtf(dx*dx+dy*dy);
for (i = 0; i < num_points; i++) {
for (j = i+1; j < num_points; j++) {
dx = hVx[j]-hVx[i];
dy = hVy[j]-hVy[i];
Dij = sqrtf(dx*dx+dy*dy);
if (distance > Dij) distance = Dij;
}
}
gettimeofday(&cpu_stop, NULL);
time_array[3] = 1000*(cpu_stop.tv_sec-cpu_start.tv_sec)
+0.000001*(cpu_stop.tv_usec-cpu_start.tv_usec);
printf("CPU execution time = %f ms\n", time_array[3]);
printf("Minimum distance (CPU) = %e\n", distance);
// Free device memory
cudaFree(dVx);
cudaFree(dVy);
cudaFree(dmin_dist);
// Free host memory
free(hVx);
free(hVy);
free(hmin_dist);
return 0;
}
// ---------------------------------------------------------------------------- | .file "tmpxft_000bd9bd_00000000-6_sidney.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z16minimum_distancePfS_S_iPfS_S_i
.type _Z41__device_stub__Z16minimum_distancePfS_S_iPfS_S_i, @function
_Z41__device_stub__Z16minimum_distancePfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16minimum_distancePfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z41__device_stub__Z16minimum_distancePfS_S_iPfS_S_i, .-_Z41__device_stub__Z16minimum_distancePfS_S_iPfS_S_i
.globl _Z16minimum_distancePfS_S_i
.type _Z16minimum_distancePfS_S_i, @function
_Z16minimum_distancePfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16minimum_distancePfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z16minimum_distancePfS_S_i, .-_Z16minimum_distancePfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Use: %s <number of points>\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Maximum number of points allowed: %d\n"
.section .rodata.str1.1
.LC3:
.string "Number of Points = %d\n"
.LC4:
.string "GPU Host-to-device = %f ms \n"
.LC5:
.string "GPU execution time = %f ms \n"
.LC6:
.string "GPU Device-to-host = %f ms \n"
.LC7:
.string "Minimum distance (GPU) = %e\n"
.LC9:
.string "CPU execution time = %f ms\n"
.LC10:
.string "Minimum distance (CPU) = %e\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movl %edi, %ebx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $0, 20(%rsp)
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
cmpl $2, %ebx
je .L12
movq 0(%rbp), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L12:
movq 8(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, num_points(%rip)
cmpl $1048576, %eax
jle .L13
movl $1048576, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L13:
leal 0(,%rax,4), %r14d
movslq %r14d, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbx
movl $4, %edi
call malloc@PLT
movq %rax, %r12
testl %r13d, %r13d
jle .L14
movl $0, %r13d
.L15:
leaq 20(%rsp), %r15
movq %r15, %rdi
call rand_r@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
movss %xmm0, 0(%rbp,%r13,4)
movq %r15, %rdi
call rand_r@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
movss %xmm0, (%rbx,%r13,4)
addq $1, %r13
cmpl %r13d, num_points(%rip)
jg .L15
.L14:
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 96(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $16, threads(%rip)
movl num_points(%rip), %eax
movl $16, %ecx
cltd
idivl %ecx
movl %eax, blocks(%rip)
movl $16, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L16:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 100(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $4, %edx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 104(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl num_points(%rip), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 96(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 100(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 104(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movss 4(%rbp), %xmm0
subss 0(%rbp), %xmm0
movss 4(%rbx), %xmm1
subss (%rbx), %xmm1
mulss %xmm0, %xmm0
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
call sqrtf@PLT
movss %xmm0, 12(%rsp)
movl num_points(%rip), %edx
testl %edx, %edx
jle .L17
movslq %edx, %rsi
movl $1, %ecx
jmp .L21
.L28:
movl num_points(%rip), %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z41__device_stub__Z16minimum_distancePfS_S_iPfS_S_i
jmp .L16
.L24:
movq %rax, %rcx
.L21:
cmpl %ecx, %edx
jle .L18
movss -4(%rbp,%rcx,4), %xmm3
movss -4(%rbx,%rcx,4), %xmm2
movq %rcx, %rax
.L20:
movss 0(%rbp,%rax,4), %xmm0
subss %xmm3, %xmm0
movss (%rbx,%rax,4), %xmm1
subss %xmm2, %xmm1
mulss %xmm0, %xmm0
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
sqrtss %xmm0, %xmm0
minss 12(%rsp), %xmm0
movss %xmm0, 12(%rsp)
addq $1, %rax
cmpl %eax, %edx
jg .L20
.L18:
leaq 1(%rcx), %rax
cmpq %rcx, %rsi
jne .L24
.L17:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 80(%rsp), %rax
subq 64(%rsp), %rax
imulq $1000, %rax, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
mulsd .LC8(%rip), %xmm1
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 108(%rsp)
cvtss2sd %xmm0, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z16minimum_distancePfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z16minimum_distancePfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl num_points
.bss
.align 4
.type num_points, @object
.size num_points, 4
num_points:
.zero 4
.globl threads
.align 4
.type threads, @object
.size threads, 4
threads:
.zero 4
.globl blocks
.align 4
.type blocks, @object
.size blocks, 4
blocks:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 805306368
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// CUDA code to compute minimum distance between n points
//
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#define MAX_POINTS 1048576
#define BLOCK_SIZE 1024
#define M_LOG2E 1.44269504088896340736 //log2(e)
inline long double my_log(const long double x){
return log(x) * M_LOG2E;
}
int blocks; //log2(num_points);
int threads; //num_points/blocks;
int num_points;
// ----------------------------------------------------------------------------
// Kernel Function to compute distance between all pairs of points
// Input:
// X: X[i] = x-coordinate of the ith point
// Y: Y[i] = y-coordinate of the ith point
// n: number of points
//
// Output:
// D: D[0] = minimum distance
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// Compute minimum distance on host to check device computation
// Need to: modify the kernel functino to compute the minimum distance.
// You are allowed to make other changes to the code that facilitate
// parallelization on the GPU
//
// 1. You need to develop CUDA-based parallel code to compute the
// distance between the closest pair of points on a GPU
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// References
// ----------------------------------------------------------------------------
/*
__global__ void VecAdd(float* A, float* B, float* C, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
}
*/
/*
__global__ void MatMult(float* A, float* B, float* C, int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i < N && j < N)
C[i][j] = A[i][j] + B[i][j];
}
*/
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// Kernel function code goes here
// ----------------------------------------------------------------------------
__global__ void minimum_distance(float * X, float * Y, float * D, int n)
{
//CUDA version of the code
int i = blockIdx.y * blockDim.y + threadIdx.y;
//int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
if(threadIdx.y == 0)
{
D[0] = 10;
}
extern __shared__ float mins[];
__threadfence();
//if (i < n && j < n)
if(i<n)
{
for (int j = i+1; j < n; j++)
{
float dx = X[j]-X[i];
float dy = Y[j]-Y[i];
float Dij = sqrtf(dx*dx+dy*dy);
//__threadfence();
//mins local to the block
mins[threadIdx.x] = Dij;
__syncthreads();
}
}
//let the last block handle finding the actual minimum
if(i >= n)
{
//sort mins to
for(unsigned int s = blockDim.y/2; s > 0; s >>= 1)
{
if(threadIdx.y < s)
{
if (mins[threadIdx.y] > mins[threadIdx.y + s])
{
mins[threadIdx.y] = mins[threadIdx.y + s];
}
}
__syncthreads();
}
//now update global minimum
if(threadIdx.y == 0)
{
if(D[0] > mins[0])
{
D[0] = mins[0];
}
}
}
//D[0] = -15;
}
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// Main program - initializes points and computes minimum distance
// between the points
// ----------------------------------------------------------------------------
int main(int argc, char* argv[]) {
// Host Data
float * hVx; // host x-coordinate array
float * hVy; // host y-coordinate array
float * hmin_dist; // minimum value on host
// Device Data
float * dVx; // device x-coordinate array
float * dVy; // device x-coordinate array
float * dmin_dist; // minimum value on device
int i, j, size;// num_points, blocks, threads;
float dx, dy, Dij, distance;
unsigned int seed = 0;
cudaEvent_t start, stop; // GPU timing variables
struct timeval cpu_start, cpu_stop; // CPU timing variables
float time_array[10];
// Timing initializations
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Check input
if (argc != 2) {
printf("Use: %s <number of points>\n", argv[0]);
exit(0);
}
if ((num_points = atoi(argv[argc-1])) > MAX_POINTS) {
printf("Maximum number of points allowed: %d\n", MAX_POINTS);
exit(0);
}
// Allocate host coordinate arrays
size = num_points * sizeof(float);
hVx = (float *) malloc(size);
hVy = (float *) malloc(size);
hmin_dist = (float *) malloc(sizeof(float));
// Initialize points
for (i = 0; i < num_points; i++) {
hVx[i] = (float)(rand_r(&seed))/(float)(RAND_MAX);
hVy[i] = (float)(rand_r(&seed))/(float)(RAND_MAX);
}
// Allocate device coordinate arrays
cudaMalloc(&dVx, size);
cudaMalloc(&dVy, size);
cudaMalloc(&dmin_dist, sizeof(float));
// Copy coordinate arrays from host memory to device memory
cudaEventRecord( start, 0 );
cudaMemcpy(dVx, hVx, size, cudaMemcpyHostToDevice);
cudaMemcpy(dVy, hVy, size, cudaMemcpyHostToDevice);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&(time_array[0]), start, stop);
// Invoke kernel
cudaEventRecord(start, 0);
// ------------------------------------------------------------
//
// Invoke kernel function here
//
// ------------------------------------------------------------
//choose the number of blocks and points
threads = 16; //num_points/blocks;
blocks = num_points/threads; //my_log(num_points);
minimum_distance<<<(blocks), threads>>>(dVx, dVy, dmin_dist, num_points);
//alternative declaration
//dim3 block(16,16);
//dim3 grid((num_points + 15)/16, (num_points + 15)/16);
//minimum_distance<<<grid, block>>>(dVx, dVy, dmin_dist, num_points);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&(time_array[1]), start, stop);
// Copy result from device memory to host memory
cudaEventRecord(start, 0);
//this was wrong! converting size to sizeof(float)
cudaMemcpy(hmin_dist, dmin_dist, sizeof(float), cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&(time_array[2]), start, stop);
printf("Number of Points = %d\n", num_points);
printf("GPU Host-to-device = %f ms \n", time_array[0]);
printf("GPU execution time = %f ms \n", time_array[1]);
printf("GPU Device-to-host = %f ms \n", time_array[2]);
printf("Minimum distance (GPU) = %e\n", hmin_dist[0]);
gettimeofday(&cpu_start, NULL);
dx = hVx[1]-hVx[0];
dy = hVy[1]-hVy[0];
distance = sqrtf(dx*dx+dy*dy);
for (i = 0; i < num_points; i++) {
for (j = i+1; j < num_points; j++) {
dx = hVx[j]-hVx[i];
dy = hVy[j]-hVy[i];
Dij = sqrtf(dx*dx+dy*dy);
if (distance > Dij) distance = Dij;
}
}
gettimeofday(&cpu_stop, NULL);
time_array[3] = 1000*(cpu_stop.tv_sec-cpu_start.tv_sec)
+0.000001*(cpu_stop.tv_usec-cpu_start.tv_usec);
printf("CPU execution time = %f ms\n", time_array[3]);
printf("Minimum distance (CPU) = %e\n", distance);
// Free device memory
cudaFree(dVx);
cudaFree(dVy);
cudaFree(dmin_dist);
// Free host memory
free(hVx);
free(hVy);
free(hmin_dist);
return 0;
}
// ---------------------------------------------------------------------------- | //
// CUDA code to compute minimum distance between n points
//
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#define MAX_POINTS 1048576
#define BLOCK_SIZE 1024
#define M_LOG2E 1.44269504088896340736 //log2(e)
inline long double my_log(const long double x){
return log(x) * M_LOG2E;
}
int blocks; //log2(num_points);
int threads; //num_points/blocks;
int num_points;
// ----------------------------------------------------------------------------
// Kernel Function to compute distance between all pairs of points
// Input:
// X: X[i] = x-coordinate of the ith point
// Y: Y[i] = y-coordinate of the ith point
// n: number of points
//
// Output:
// D: D[0] = minimum distance
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// Compute minimum distance on host to check device computation
// Need to: modify the kernel functino to compute the minimum distance.
// You are allowed to make other changes to the code that facilitate
// parallelization on the GPU
//
// 1. You need to develop CUDA-based parallel code to compute the
// distance between the closest pair of points on a GPU
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// References
// ----------------------------------------------------------------------------
/*
__global__ void VecAdd(float* A, float* B, float* C, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
}
*/
/*
__global__ void MatMult(float* A, float* B, float* C, int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i < N && j < N)
C[i][j] = A[i][j] + B[i][j];
}
*/
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// Kernel function code goes here
// ----------------------------------------------------------------------------
__global__ void minimum_distance(float * X, float * Y, float * D, int n)
{
//CUDA version of the code
int i = blockIdx.y * blockDim.y + threadIdx.y;
//int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
if(threadIdx.y == 0)
{
D[0] = 10;
}
extern __shared__ float mins[];
__threadfence();
//if (i < n && j < n)
if(i<n)
{
for (int j = i+1; j < n; j++)
{
float dx = X[j]-X[i];
float dy = Y[j]-Y[i];
float Dij = sqrtf(dx*dx+dy*dy);
//__threadfence();
//mins local to the block
mins[threadIdx.x] = Dij;
__syncthreads();
}
}
//let the last block handle finding the actual minimum
if(i >= n)
{
//sort mins to
for(unsigned int s = blockDim.y/2; s > 0; s >>= 1)
{
if(threadIdx.y < s)
{
if (mins[threadIdx.y] > mins[threadIdx.y + s])
{
mins[threadIdx.y] = mins[threadIdx.y + s];
}
}
__syncthreads();
}
//now update global minimum
if(threadIdx.y == 0)
{
if(D[0] > mins[0])
{
D[0] = mins[0];
}
}
}
//D[0] = -15;
}
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// Main program - initializes points and computes minimum distance
// between the points
// ----------------------------------------------------------------------------
int main(int argc, char* argv[]) {
// Host Data
float * hVx; // host x-coordinate array
float * hVy; // host y-coordinate array
float * hmin_dist; // minimum value on host
// Device Data
float * dVx; // device x-coordinate array
float * dVy; // device x-coordinate array
float * dmin_dist; // minimum value on device
int i, j, size;// num_points, blocks, threads;
float dx, dy, Dij, distance;
unsigned int seed = 0;
hipEvent_t start, stop; // GPU timing variables
struct timeval cpu_start, cpu_stop; // CPU timing variables
float time_array[10];
// Timing initializations
hipEventCreate(&start);
hipEventCreate(&stop);
// Check input
if (argc != 2) {
printf("Use: %s <number of points>\n", argv[0]);
exit(0);
}
if ((num_points = atoi(argv[argc-1])) > MAX_POINTS) {
printf("Maximum number of points allowed: %d\n", MAX_POINTS);
exit(0);
}
// Allocate host coordinate arrays
size = num_points * sizeof(float);
hVx = (float *) malloc(size);
hVy = (float *) malloc(size);
hmin_dist = (float *) malloc(sizeof(float));
// Initialize points
for (i = 0; i < num_points; i++) {
hVx[i] = (float)(rand_r(&seed))/(float)(RAND_MAX);
hVy[i] = (float)(rand_r(&seed))/(float)(RAND_MAX);
}
// Allocate device coordinate arrays
hipMalloc(&dVx, size);
hipMalloc(&dVy, size);
hipMalloc(&dmin_dist, sizeof(float));
// Copy coordinate arrays from host memory to device memory
hipEventRecord( start, 0 );
hipMemcpy(dVx, hVx, size, hipMemcpyHostToDevice);
hipMemcpy(dVy, hVy, size, hipMemcpyHostToDevice);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&(time_array[0]), start, stop);
// Invoke kernel
hipEventRecord(start, 0);
// ------------------------------------------------------------
//
// Invoke kernel function here
//
// ------------------------------------------------------------
//choose the number of blocks and points
threads = 16; //num_points/blocks;
blocks = num_points/threads; //my_log(num_points);
minimum_distance<<<(blocks), threads>>>(dVx, dVy, dmin_dist, num_points);
//alternative declaration
//dim3 block(16,16);
//dim3 grid((num_points + 15)/16, (num_points + 15)/16);
//minimum_distance<<<grid, block>>>(dVx, dVy, dmin_dist, num_points);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&(time_array[1]), start, stop);
// Copy result from device memory to host memory
hipEventRecord(start, 0);
//this was wrong! converting size to sizeof(float)
hipMemcpy(hmin_dist, dmin_dist, sizeof(float), hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&(time_array[2]), start, stop);
printf("Number of Points = %d\n", num_points);
printf("GPU Host-to-device = %f ms \n", time_array[0]);
printf("GPU execution time = %f ms \n", time_array[1]);
printf("GPU Device-to-host = %f ms \n", time_array[2]);
printf("Minimum distance (GPU) = %e\n", hmin_dist[0]);
gettimeofday(&cpu_start, NULL);
dx = hVx[1]-hVx[0];
dy = hVy[1]-hVy[0];
distance = sqrtf(dx*dx+dy*dy);
for (i = 0; i < num_points; i++) {
for (j = i+1; j < num_points; j++) {
dx = hVx[j]-hVx[i];
dy = hVy[j]-hVy[i];
Dij = sqrtf(dx*dx+dy*dy);
if (distance > Dij) distance = Dij;
}
}
gettimeofday(&cpu_stop, NULL);
time_array[3] = 1000*(cpu_stop.tv_sec-cpu_start.tv_sec)
+0.000001*(cpu_stop.tv_usec-cpu_start.tv_usec);
printf("CPU execution time = %f ms\n", time_array[3]);
printf("Minimum distance (CPU) = %e\n", distance);
// Free device memory
hipFree(dVx);
hipFree(dVy);
hipFree(dmin_dist);
// Free host memory
free(hVx);
free(hVy);
free(hmin_dist);
return 0;
}
// ---------------------------------------------------------------------------- |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //
// CUDA code to compute minimum distance between n points
//
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#define MAX_POINTS 1048576
#define BLOCK_SIZE 1024
#define M_LOG2E 1.44269504088896340736 //log2(e)
inline long double my_log(const long double x){
return log(x) * M_LOG2E;
}
int blocks; //log2(num_points);
int threads; //num_points/blocks;
int num_points;
// ----------------------------------------------------------------------------
// Kernel Function to compute distance between all pairs of points
// Input:
// X: X[i] = x-coordinate of the ith point
// Y: Y[i] = y-coordinate of the ith point
// n: number of points
//
// Output:
// D: D[0] = minimum distance
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// Compute minimum distance on host to check device computation
// Need to: modify the kernel functino to compute the minimum distance.
// You are allowed to make other changes to the code that facilitate
// parallelization on the GPU
//
// 1. You need to develop CUDA-based parallel code to compute the
// distance between the closest pair of points on a GPU
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// References
// ----------------------------------------------------------------------------
/*
__global__ void VecAdd(float* A, float* B, float* C, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
}
*/
/*
__global__ void MatMult(float* A, float* B, float* C, int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i < N && j < N)
C[i][j] = A[i][j] + B[i][j];
}
*/
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// Kernel function code goes here
// ----------------------------------------------------------------------------
__global__ void minimum_distance(float * X, float * Y, float * D, int n)
{
//CUDA version of the code
int i = blockIdx.y * blockDim.y + threadIdx.y;
//int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
if(threadIdx.y == 0)
{
D[0] = 10;
}
extern __shared__ float mins[];
__threadfence();
//if (i < n && j < n)
if(i<n)
{
for (int j = i+1; j < n; j++)
{
float dx = X[j]-X[i];
float dy = Y[j]-Y[i];
float Dij = sqrtf(dx*dx+dy*dy);
//__threadfence();
//mins local to the block
mins[threadIdx.x] = Dij;
__syncthreads();
}
}
//let the last block handle finding the actual minimum
if(i >= n)
{
//sort mins to
for(unsigned int s = blockDim.y/2; s > 0; s >>= 1)
{
if(threadIdx.y < s)
{
if (mins[threadIdx.y] > mins[threadIdx.y + s])
{
mins[threadIdx.y] = mins[threadIdx.y + s];
}
}
__syncthreads();
}
//now update global minimum
if(threadIdx.y == 0)
{
if(D[0] > mins[0])
{
D[0] = mins[0];
}
}
}
//D[0] = -15;
}
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// Main program - initializes points and computes minimum distance
// between the points
// ----------------------------------------------------------------------------
int main(int argc, char* argv[]) {
// Host Data
float * hVx; // host x-coordinate array
float * hVy; // host y-coordinate array
float * hmin_dist; // minimum value on host
// Device Data
float * dVx; // device x-coordinate array
float * dVy; // device x-coordinate array
float * dmin_dist; // minimum value on device
int i, j, size;// num_points, blocks, threads;
float dx, dy, Dij, distance;
unsigned int seed = 0;
hipEvent_t start, stop; // GPU timing variables
struct timeval cpu_start, cpu_stop; // CPU timing variables
float time_array[10];
// Timing initializations
hipEventCreate(&start);
hipEventCreate(&stop);
// Check input
if (argc != 2) {
printf("Use: %s <number of points>\n", argv[0]);
exit(0);
}
if ((num_points = atoi(argv[argc-1])) > MAX_POINTS) {
printf("Maximum number of points allowed: %d\n", MAX_POINTS);
exit(0);
}
// Allocate host coordinate arrays
size = num_points * sizeof(float);
hVx = (float *) malloc(size);
hVy = (float *) malloc(size);
hmin_dist = (float *) malloc(sizeof(float));
// Initialize points
for (i = 0; i < num_points; i++) {
hVx[i] = (float)(rand_r(&seed))/(float)(RAND_MAX);
hVy[i] = (float)(rand_r(&seed))/(float)(RAND_MAX);
}
// Allocate device coordinate arrays
hipMalloc(&dVx, size);
hipMalloc(&dVy, size);
hipMalloc(&dmin_dist, sizeof(float));
// Copy coordinate arrays from host memory to device memory
hipEventRecord( start, 0 );
hipMemcpy(dVx, hVx, size, hipMemcpyHostToDevice);
hipMemcpy(dVy, hVy, size, hipMemcpyHostToDevice);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&(time_array[0]), start, stop);
// Invoke kernel
hipEventRecord(start, 0);
// ------------------------------------------------------------
//
// Invoke kernel function here
//
// ------------------------------------------------------------
//choose the number of blocks and points
threads = 16; //num_points/blocks;
blocks = num_points/threads; //my_log(num_points);
minimum_distance<<<(blocks), threads>>>(dVx, dVy, dmin_dist, num_points);
//alternative declaration
//dim3 block(16,16);
//dim3 grid((num_points + 15)/16, (num_points + 15)/16);
//minimum_distance<<<grid, block>>>(dVx, dVy, dmin_dist, num_points);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&(time_array[1]), start, stop);
// Copy result from device memory to host memory
hipEventRecord(start, 0);
//this was wrong! converting size to sizeof(float)
hipMemcpy(hmin_dist, dmin_dist, sizeof(float), hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&(time_array[2]), start, stop);
printf("Number of Points = %d\n", num_points);
printf("GPU Host-to-device = %f ms \n", time_array[0]);
printf("GPU execution time = %f ms \n", time_array[1]);
printf("GPU Device-to-host = %f ms \n", time_array[2]);
printf("Minimum distance (GPU) = %e\n", hmin_dist[0]);
gettimeofday(&cpu_start, NULL);
dx = hVx[1]-hVx[0];
dy = hVy[1]-hVy[0];
distance = sqrtf(dx*dx+dy*dy);
for (i = 0; i < num_points; i++) {
for (j = i+1; j < num_points; j++) {
dx = hVx[j]-hVx[i];
dy = hVy[j]-hVy[i];
Dij = sqrtf(dx*dx+dy*dy);
if (distance > Dij) distance = Dij;
}
}
gettimeofday(&cpu_stop, NULL);
time_array[3] = 1000*(cpu_stop.tv_sec-cpu_start.tv_sec)
+0.000001*(cpu_stop.tv_usec-cpu_start.tv_usec);
printf("CPU execution time = %f ms\n", time_array[3]);
printf("Minimum distance (CPU) = %e\n", distance);
// Free device memory
hipFree(dVx);
hipFree(dVy);
hipFree(dmin_dist);
// Free host memory
free(hVx);
free(hVy);
free(hmin_dist);
return 0;
}
// ---------------------------------------------------------------------------- | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16minimum_distancePfS_S_i
.globl _Z16minimum_distancePfS_S_i
.p2align 8
.type _Z16minimum_distancePfS_S_i,@function
_Z16minimum_distancePfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0x41200000
global_store_b32 v2, v3, s[4:5]
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_load_b32 s7, s[0:1], 0x18
s_and_b32 s6, 0xffff, s2
s_mov_b32 s9, -1
v_mad_u64_u32 v[2:3], null, s15, s6, v[1:2]
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
buffer_gl1_inv
buffer_gl0_inv
v_cmp_le_i32_e64 s2, s7, v2
v_cmpx_gt_i32_e64 s7, v2
s_cbranch_execz .LBB0_7
v_add_nc_u32_e32 v10, 1, v2
s_mov_b32 s9, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s7, v10
s_cbranch_execz .LBB0_6
s_load_b128 s[12:15], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
v_and_b32_e32 v0, 0x3ff, v0
s_mov_b32 s10, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_lshl_add_u32 v0, v0, 2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v8, s0, v4, 4
v_add_co_ci_u32_e64 v9, s0, 0, v5, s0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, s0, s12, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s13, v5, s0
v_add_co_u32 v4, s0, s14, v4
v_add_co_ci_u32_e64 v5, s0, s15, v5, s0
v_add_co_u32 v6, s0, s12, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s0, s13, v9, s0
v_add_co_u32 v8, s0, s14, v8
v_add_co_ci_u32_e64 v9, s0, s15, v9, s0
.LBB0_5:
global_load_b32 v11, v[8:9], off
global_load_b32 v12, v[4:5], off
global_load_b32 v13, v[6:7], off
global_load_b32 v14, v[2:3], off
v_add_nc_u32_e32 v10, 1, v10
v_add_co_u32 v6, s1, v6, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s1, 0, v7, s1
v_add_co_u32 v8, s1, v8, 4
v_add_co_ci_u32_e64 v9, s1, 0, v9, s1
s_waitcnt vmcnt(2)
v_sub_f32_e32 v11, v11, v12
v_cmp_le_i32_e64 s1, s7, v10
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v12, v13, v14 :: v_dual_mul_f32 v11, v11, v11
s_or_b32 s10, s1, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v11, v12, v12
v_mul_f32_e32 v12, 0x4f800000, v11
v_cmp_gt_f32_e64 s0, 0xf800000, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v11, v11, v12, s0
v_sqrt_f32_e32 v12, v11
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v13, -1, v12
v_add_nc_u32_e32 v14, 1, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v15, -v13, v12, v11
v_fma_f32 v16, -v14, v12, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s3, 0, v15
v_cndmask_b32_e64 v12, v12, v13, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s3, 0, v16
v_cndmask_b32_e64 v12, v12, v14, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v13, 0x37800000, v12
v_cndmask_b32_e64 v12, v12, v13, s0
v_cmp_class_f32_e64 s0, v11, 0x260
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v11, v12, v11, s0
ds_store_b32 v0, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_5
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_or_not1_b32 s9, s2, exec_lo
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s8
s_and_saveexec_b32 s0, s9
s_cbranch_execz .LBB0_17
s_cmp_lt_u32 s6, 2
s_cbranch_scc1 .LBB0_14
v_lshl_add_u32 v0, v1, 2, 0
s_branch .LBB0_11
.p2align 6
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s2
s_cmp_lt_u32 s1, 4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_14
.LBB0_11:
s_mov_b32 s1, s6
s_lshr_b32 s6, s6, 1
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s6, v1
s_cbranch_execz .LBB0_10
v_add_nc_u32_e32 v2, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v3, v0
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e64 s0, v3, v2
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_10
ds_store_b32 v0, v2
s_branch .LBB0_10
.LBB0_14:
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_17
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
global_load_b32 v2, v0, s[4:5]
ds_load_b32 v1, v1
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_ngt_f32_e32 vcc_lo, v2, v1
s_cbranch_vccnz .LBB0_17
global_store_b32 v0, v1, s[4:5]
.LBB0_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16minimum_distancePfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16minimum_distancePfS_S_i, .Lfunc_end0-_Z16minimum_distancePfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16minimum_distancePfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16minimum_distancePfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
// CUDA code to compute minimum distance between n points
//
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#define MAX_POINTS 1048576
#define BLOCK_SIZE 1024
#define M_LOG2E 1.44269504088896340736 //log2(e)
inline long double my_log(const long double x){
return log(x) * M_LOG2E;
}
int blocks; //log2(num_points);
int threads; //num_points/blocks;
int num_points;
// ----------------------------------------------------------------------------
// Kernel Function to compute distance between all pairs of points
// Input:
// X: X[i] = x-coordinate of the ith point
// Y: Y[i] = y-coordinate of the ith point
// n: number of points
//
// Output:
// D: D[0] = minimum distance
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// Compute minimum distance on host to check device computation
// Need to: modify the kernel functino to compute the minimum distance.
// You are allowed to make other changes to the code that facilitate
// parallelization on the GPU
//
// 1. You need to develop CUDA-based parallel code to compute the
// distance between the closest pair of points on a GPU
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// References
// ----------------------------------------------------------------------------
/*
__global__ void VecAdd(float* A, float* B, float* C, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
}
*/
/*
__global__ void MatMult(float* A, float* B, float* C, int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i < N && j < N)
C[i][j] = A[i][j] + B[i][j];
}
*/
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// Kernel function code goes here
// ----------------------------------------------------------------------------
__global__ void minimum_distance(float * X, float * Y, float * D, int n)
{
//CUDA version of the code
int i = blockIdx.y * blockDim.y + threadIdx.y;
//int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
if(threadIdx.y == 0)
{
D[0] = 10;
}
extern __shared__ float mins[];
__threadfence();
//if (i < n && j < n)
if(i<n)
{
for (int j = i+1; j < n; j++)
{
float dx = X[j]-X[i];
float dy = Y[j]-Y[i];
float Dij = sqrtf(dx*dx+dy*dy);
//__threadfence();
//mins local to the block
mins[threadIdx.x] = Dij;
__syncthreads();
}
}
//let the last block handle finding the actual minimum
if(i >= n)
{
//sort mins to
for(unsigned int s = blockDim.y/2; s > 0; s >>= 1)
{
if(threadIdx.y < s)
{
if (mins[threadIdx.y] > mins[threadIdx.y + s])
{
mins[threadIdx.y] = mins[threadIdx.y + s];
}
}
__syncthreads();
}
//now update global minimum
if(threadIdx.y == 0)
{
if(D[0] > mins[0])
{
D[0] = mins[0];
}
}
}
//D[0] = -15;
}
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// Main program - initializes points and computes minimum distance
// between the points
// ----------------------------------------------------------------------------
int main(int argc, char* argv[]) {
// Host Data
float * hVx; // host x-coordinate array
float * hVy; // host y-coordinate array
float * hmin_dist; // minimum value on host
// Device Data
float * dVx; // device x-coordinate array
float * dVy; // device x-coordinate array
float * dmin_dist; // minimum value on device
int i, j, size;// num_points, blocks, threads;
float dx, dy, Dij, distance;
unsigned int seed = 0;
hipEvent_t start, stop; // GPU timing variables
struct timeval cpu_start, cpu_stop; // CPU timing variables
float time_array[10];
// Timing initializations
hipEventCreate(&start);
hipEventCreate(&stop);
// Check input
if (argc != 2) {
printf("Use: %s <number of points>\n", argv[0]);
exit(0);
}
if ((num_points = atoi(argv[argc-1])) > MAX_POINTS) {
printf("Maximum number of points allowed: %d\n", MAX_POINTS);
exit(0);
}
// Allocate host coordinate arrays
size = num_points * sizeof(float);
hVx = (float *) malloc(size);
hVy = (float *) malloc(size);
hmin_dist = (float *) malloc(sizeof(float));
// Initialize points
for (i = 0; i < num_points; i++) {
hVx[i] = (float)(rand_r(&seed))/(float)(RAND_MAX);
hVy[i] = (float)(rand_r(&seed))/(float)(RAND_MAX);
}
// Allocate device coordinate arrays
hipMalloc(&dVx, size);
hipMalloc(&dVy, size);
hipMalloc(&dmin_dist, sizeof(float));
// Copy coordinate arrays from host memory to device memory
hipEventRecord( start, 0 );
hipMemcpy(dVx, hVx, size, hipMemcpyHostToDevice);
hipMemcpy(dVy, hVy, size, hipMemcpyHostToDevice);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&(time_array[0]), start, stop);
// Invoke kernel
hipEventRecord(start, 0);
// ------------------------------------------------------------
//
// Invoke kernel function here
//
// ------------------------------------------------------------
//choose the number of blocks and points
threads = 16; //num_points/blocks;
blocks = num_points/threads; //my_log(num_points);
minimum_distance<<<(blocks), threads>>>(dVx, dVy, dmin_dist, num_points);
//alternative declaration
//dim3 block(16,16);
//dim3 grid((num_points + 15)/16, (num_points + 15)/16);
//minimum_distance<<<grid, block>>>(dVx, dVy, dmin_dist, num_points);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&(time_array[1]), start, stop);
// Copy result from device memory to host memory
hipEventRecord(start, 0);
//this was wrong! converting size to sizeof(float)
hipMemcpy(hmin_dist, dmin_dist, sizeof(float), hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&(time_array[2]), start, stop);
printf("Number of Points = %d\n", num_points);
printf("GPU Host-to-device = %f ms \n", time_array[0]);
printf("GPU execution time = %f ms \n", time_array[1]);
printf("GPU Device-to-host = %f ms \n", time_array[2]);
printf("Minimum distance (GPU) = %e\n", hmin_dist[0]);
gettimeofday(&cpu_start, NULL);
dx = hVx[1]-hVx[0];
dy = hVy[1]-hVy[0];
distance = sqrtf(dx*dx+dy*dy);
for (i = 0; i < num_points; i++) {
for (j = i+1; j < num_points; j++) {
dx = hVx[j]-hVx[i];
dy = hVy[j]-hVy[i];
Dij = sqrtf(dx*dx+dy*dy);
if (distance > Dij) distance = Dij;
}
}
gettimeofday(&cpu_stop, NULL);
time_array[3] = 1000*(cpu_stop.tv_sec-cpu_start.tv_sec)
+0.000001*(cpu_stop.tv_usec-cpu_start.tv_usec);
printf("CPU execution time = %f ms\n", time_array[3]);
printf("Minimum distance (CPU) = %e\n", distance);
// Free device memory
hipFree(dVx);
hipFree(dVy);
hipFree(dmin_dist);
// Free host memory
free(hVx);
free(hVy);
free(hmin_dist);
return 0;
}
// ---------------------------------------------------------------------------- | .text
.file "sidney.hip"
.globl _Z31__device_stub__minimum_distancePfS_S_i # -- Begin function _Z31__device_stub__minimum_distancePfS_S_i
.p2align 4, 0x90
.type _Z31__device_stub__minimum_distancePfS_S_i,@function
_Z31__device_stub__minimum_distancePfS_S_i: # @_Z31__device_stub__minimum_distancePfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16minimum_distancePfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__minimum_distancePfS_S_i, .Lfunc_end0-_Z31__device_stub__minimum_distancePfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movl $0, 56(%rsp)
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
cmpl $2, %ebp
jne .LBB1_22
# %bb.1:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, num_points(%rip)
cmpl $1048577, %eax # imm = 0x100001
jge .LBB1_23
# %bb.2:
shll $2, %eax
movslq %eax, %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movl $4, %edi
callq malloc
movq %rax, %rbp
cmpl $0, num_points(%rip)
jle .LBB1_5
# %bb.3: # %.lr.ph.preheader
xorl %r15d, %r15d
leaq 56(%rsp), %r13
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r13, %rdi
callq rand_r
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%r15,4)
movq %r13, %rdi
callq rand_r
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
movslq num_points(%rip), %rax
cmpq %rax, %r15
jl .LBB1_4
.LBB1_5: # %._crit_edge
leaq 48(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 176(%rsp), %rdi
callq hipEventElapsedTime
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $16, threads(%rip)
movl num_points(%rip), %eax
leal 15(%rax), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $4, %edi
movl %edi, blocks(%rip)
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $16, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movl num_points(%rip), %esi
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %esi, 60(%rsp)
leaq 168(%rsp), %rax
movq %rax, 80(%rsp)
leaq 160(%rsp), %rax
movq %rax, 88(%rsp)
leaq 152(%rsp), %rax
movq %rax, 96(%rsp)
leaq 60(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16minimum_distancePfS_S_i, %edi
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
leaq 180(%rsp), %rdi
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
callq hipEventElapsedTime
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rsi
movl $4, %edx
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
leaq 184(%rsp), %rdi
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
callq hipEventElapsedTime
movl num_points(%rip), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movss 176(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movss 180(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movss 184(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movss (%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
leaq 80(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movss 4(%rbx), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss (%rbx), %xmm1
movss 4(%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%r14), %xmm0
mulss %xmm1, %xmm1
mulss %xmm0, %xmm0
addss %xmm1, %xmm0
xorps %xmm1, %xmm1
ucomiss %xmm1, %xmm0
jb .LBB1_9
# %bb.8:
sqrtss %xmm0, %xmm3
jmp .LBB1_10
.LBB1_9: # %call.sqrt
callq sqrtf
movaps %xmm0, %xmm3
.LBB1_10: # %.split
movq %rbp, 112(%rsp) # 8-byte Spill
cmpl $0, num_points(%rip)
jle .LBB1_11
# %bb.13: # %.lr.ph71.preheader
movl $1, %r15d
xorl %r13d, %r13d
xorps %xmm2, %xmm2
jmp .LBB1_15
.p2align 4, 0x90
.LBB1_16: # in Loop: Header=BB1_15 Depth=1
movaps %xmm3, %xmm0
.LBB1_14: # %.loopexit
# in Loop: Header=BB1_15 Depth=1
movslq num_points(%rip), %rax
incq %r15
movaps %xmm0, %xmm3
cmpq %rax, %r13
jge .LBB1_12
.LBB1_15: # %.lr.ph71
# =>This Loop Header: Depth=1
# Child Loop BB1_18 Depth 2
movq %r13, %rbp
incq %r13
movslq num_points(%rip), %rax
cmpq %rax, %r13
jge .LBB1_16
# %bb.17: # %.lr.ph67
# in Loop: Header=BB1_15 Depth=1
movq %r15, %r12
jmp .LBB1_18
.p2align 4, 0x90
.LBB1_20: # %call.sqrt87
# in Loop: Header=BB1_18 Depth=2
movss %xmm3, 20(%rsp) # 4-byte Spill
callq sqrtf
movss 20(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
xorps %xmm2, %xmm2
.LBB1_21: # %.split86
# in Loop: Header=BB1_18 Depth=2
minss %xmm3, %xmm0
incq %r12
movaps %xmm0, %xmm3
cmpl %r12d, num_points(%rip)
jle .LBB1_14
.LBB1_18: # Parent Loop BB1_15 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss (%rbx,%rbp,4), %xmm1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%r14,%rbp,4), %xmm0
mulss %xmm1, %xmm1
mulss %xmm0, %xmm0
addss %xmm1, %xmm0
ucomiss %xmm2, %xmm0
jb .LBB1_20
# %bb.19: # in Loop: Header=BB1_18 Depth=2
sqrtss %xmm0, %xmm0
jmp .LBB1_21
.LBB1_11:
movaps %xmm3, %xmm0
.LBB1_12: # %._crit_edge72
movss %xmm0, 20(%rsp) # 4-byte Spill
leaq 64(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 64(%rsp), %rax
subq 80(%rsp), %rax
movq 72(%rsp), %rcx
imulq $1000, %rax, %rax # imm = 0x3E8
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
subq 88(%rsp), %rcx
xorps %xmm1, %xmm1
cvtsi2sd %rcx, %xmm1
mulsd .LCPI1_1(%rip), %xmm1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
movss %xmm0, 188(%rsp)
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movss 20(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 112(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_22:
.cfi_def_cfa_offset 272
movq (%rbx), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.LBB1_23:
movl $.L.str.1, %edi
movl $1048576, %esi # imm = 0x100000
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16minimum_distancePfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type blocks,@object # @blocks
.bss
.globl blocks
.p2align 2, 0x0
blocks:
.long 0 # 0x0
.size blocks, 4
.type threads,@object # @threads
.globl threads
.p2align 2, 0x0
threads:
.long 0 # 0x0
.size threads, 4
.type num_points,@object # @num_points
.globl num_points
.p2align 2, 0x0
num_points:
.long 0 # 0x0
.size num_points, 4
.type _Z16minimum_distancePfS_S_i,@object # @_Z16minimum_distancePfS_S_i
.section .rodata,"a",@progbits
.globl _Z16minimum_distancePfS_S_i
.p2align 3, 0x0
_Z16minimum_distancePfS_S_i:
.quad _Z31__device_stub__minimum_distancePfS_S_i
.size _Z16minimum_distancePfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Use: %s <number of points>\n"
.size .L.str, 28
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Maximum number of points allowed: %d\n"
.size .L.str.1, 38
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Number of Points = %d\n"
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPU Host-to-device = %f ms \n"
.size .L.str.3, 29
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPU execution time = %f ms \n"
.size .L.str.4, 29
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "GPU Device-to-host = %f ms \n"
.size .L.str.5, 29
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Minimum distance (GPU) = %e\n"
.size .L.str.6, 29
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "CPU execution time = %f ms\n"
.size .L.str.7, 28
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Minimum distance (CPU) = %e\n"
.size .L.str.8, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16minimum_distancePfS_S_i"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__minimum_distancePfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16minimum_distancePfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16minimum_distancePfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e220000002200 */
/*0020*/ S2UR UR4, SR_CTAID.Y ; /* 0x00000000000479c3 */
/* 0x000e620000002600 */
/*0030*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fe20000000f00 */
/*0050*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe40000000a00 */
/*0060*/ ULDC UR5, c[0x0][0x4] ; /* 0x0000010000057ab9 */
/* 0x000fe20000000800 */
/*0070*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fe20003f05270 */
/*0080*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x002fcc000f8e023f */
/*0090*/ IADD3 R4, R7, UR4, RZ ; /* 0x0000000407047c10 */
/* 0x000fc8000fffe0ff */
/*00a0*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fe40003f26270 */
/*00b0*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, 0x41200000 ; /* 0x41200000ff058424 */
/* 0x000fca00078e00ff */
/*00c0*/ @!P0 STG.E [R2.64], R5 ; /* 0x0000000502008986 */
/* 0x0001e2000c101908 */
/*00d0*/ MEMBAR.SC.GPU ; /* 0x0000000000007992 */
/* 0x000fec0000002000 */
/*00e0*/ ERRBAR; /* 0x00000000000079ab */
/* 0x000fc00000000000 */
/*00f0*/ CCTL.IVALL ; /* 0x00000000ff00798f */
/* 0x000fca0002000000 */
/*0100*/ @!P1 BRA 0x2a0 ; /* 0x0000019000009947 */
/* 0x000fea0003800000 */
/*0110*/ ULDC UR5, c[0x0][0x4] ; /* 0x0000010000057ab9 */
/* 0x000fe40000000800 */
/*0120*/ USHF.R.U32.HI UR5, URZ, 0x1, UR5 ; /* 0x000000013f057899 */
/* 0x000fcc0008011605 */
/*0130*/ ISETP.NE.AND P1, PT, RZ, UR5, PT ; /* 0x00000005ff007c0c */
/* 0x000fda000bf25270 */
/*0140*/ @!P1 BRA 0x230 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*0150*/ MOV R0, UR5 ; /* 0x0000000500007c02 */
/* 0x000fe20008000f00 */
/*0160*/ IMAD.SHL.U32 R5, R7, 0x4, RZ ; /* 0x0000000407057824 */
/* 0x001fc600078e00ff */
/*0170*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*0180*/ @P1 BRA 0x1e0 ; /* 0x0000005000001947 */
/* 0x001fea0003800000 */
/*0190*/ LEA R6, R0, R5, 0x2 ; /* 0x0000000500067211 */
/* 0x000fe200078e10ff */
/*01a0*/ LDS R4, [R7.X4] ; /* 0x0000000007047984 */
/* 0x000fea0000004800 */
/*01b0*/ LDS R6, [R6] ; /* 0x0000000006067984 */
/* 0x000e240000000800 */
/*01c0*/ FSETP.GT.AND P1, PT, R4, R6, PT ; /* 0x000000060400720b */
/* 0x001fda0003f24000 */
/*01d0*/ @P1 STS [R7.X4], R6 ; /* 0x0000000607001388 */
/* 0x0001e40000004800 */
/*01e0*/ SHF.R.U32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fe20000011600 */
/*01f0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0200*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe40000010000 */
/*0210*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f25270 */
/*0220*/ @P1 BRA 0x170 ; /* 0xffffff4000001947 */
/* 0x000fea000383ffff */
/*0230*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0240*/ LDG.E R0, [R2.64] ; /* 0x0000000802007981 */
/* 0x000ea8000c1e1900 */
/*0250*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x001ea40000000800 */
/*0260*/ FSETP.GT.AND P0, PT, R0, R5, PT ; /* 0x000000050000720b */
/* 0x004fda0003f04000 */
/*0270*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0280*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101908 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ IADD3 R6, R4, 0x1, RZ ; /* 0x0000000104067810 */
/* 0x000fc80007ffe0ff */
/*02b0*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*02c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02d0*/ LOP3.LUT R2, RZ, UR4, RZ, 0x33, !PT ; /* 0x00000004ff027c12 */
/* 0x001fe2000f8e33ff */
/*02e0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*02f0*/ UMOV UR5, 0x2 ; /* 0x0000000200057882 */
/* 0x000fe20000000000 */
/*0300*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0310*/ IADD3 R2, -R7, c[0x0][0x178], R2 ; /* 0x00005e0007027a10 */
/* 0x000fe20007ffe102 */
/*0320*/ ULDC UR6, c[0x0][0x178] ; /* 0x00005e0000067ab9 */
/* 0x000fe40000000800 */
/*0330*/ UIADD3 UR5, -UR4, UR6, -UR5 ; /* 0x0000000604057290 */
/* 0x000fe2000fffe905 */
/*0340*/ LOP3.LUT P0, R12, R2, 0x3, RZ, 0xc0, !PT ; /* 0x00000003020c7812 */
/* 0x000fe2000780c0ff */
/*0350*/ IMAD.WIDE R2, R4, R11, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc800078e020b */
/*0360*/ IADD3 R7, -R7, UR5, RZ ; /* 0x0000000507077c10 */
/* 0x000fe2000fffe1ff */
/*0370*/ IMAD.WIDE R4, R4, R11, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fce00078e020b */
/*0380*/ @!P0 BRA 0x5b0 ; /* 0x0000022000008947 */
/* 0x000fea0003800000 */
/*0390*/ IMAD.WIDE R8, R6, R11, c[0x0][0x168] ; /* 0x00005a0006087625 */
/* 0x000fc800078e020b */
/*03a0*/ IMAD.WIDE R10, R6, R11, c[0x0][0x160] ; /* 0x00005800060a7625 */
/* 0x000fc800078e020b */
/*03b0*/ LDG.E R15, [R4.64] ; /* 0x00000008040f7981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R16, [R8.64] ; /* 0x0000000808107981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R14, [R10.64] ; /* 0x000000080a0e7981 */
/* 0x000ee8000c1e1900 */
/*03e0*/ LDG.E R13, [R2.64] ; /* 0x00000008020d7981 */
/* 0x000ee2000c1e1900 */
/*03f0*/ BSSY B0, 0x500 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0400*/ FADD R15, -R15, R16 ; /* 0x000000100f0f7221 */
/* 0x004fc40000000100 */
/*0410*/ FADD R13, -R13, R14 ; /* 0x0000000e0d0d7221 */
/* 0x008fe40000000100 */
/*0420*/ FMUL R14, R15, R15 ; /* 0x0000000f0f0e7220 */
/* 0x000fc80000400000 */
/*0430*/ FFMA R18, R13, R13, R14 ; /* 0x0000000d0d127223 */
/* 0x000fc8000000000e */
/*0440*/ MUFU.RSQ R15, R18 ; /* 0x00000012000f7308 */
/* 0x0002a20000001400 */
/*0450*/ IADD3 R13, R18, -0xd000000, RZ ; /* 0xf3000000120d7810 */
/* 0x000fc80007ffe0ff */
/*0460*/ ISETP.GT.U32.AND P0, PT, R13, 0x727fffff, PT ; /* 0x727fffff0d00780c */
/* 0x000fda0003f04070 */
/*0470*/ @!P0 BRA 0x4b0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0480*/ MOV R19, 0x4a0 ; /* 0x000004a000137802 */
/* 0x006fe40000000f00 */
/*0490*/ CALL.REL.NOINC 0xd20 ; /* 0x0000088000007944 */
/* 0x001fea0003c00000 */
/*04a0*/ BRA 0x4f0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*04b0*/ FMUL.FTZ R13, R18, R15 ; /* 0x0000000f120d7220 */
/* 0x006fe40000410000 */
/*04c0*/ FMUL.FTZ R15, R15, 0.5 ; /* 0x3f0000000f0f7820 */
/* 0x000fe40000410000 */
/*04d0*/ FFMA R14, -R13, R13, R18 ; /* 0x0000000d0d0e7223 */
/* 0x000fc80000000112 */
/*04e0*/ FFMA R13, R14, R15, R13 ; /* 0x0000000f0e0d7223 */
/* 0x000fe4000000000d */
/*04f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0500*/ IADD3 R12, R12, -0x1, RZ ; /* 0xffffffff0c0c7810 */
/* 0x000fe20007ffe0ff */
/*0510*/ STS [R0.X4], R13 ; /* 0x0000000d00007388 */
/* 0x0011e20000004800 */
/*0520*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe60003800000 */
/*0530*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0540*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f05270 */
/*0550*/ IADD3 R8, P1, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe40007f3e0ff */
/*0560*/ IADD3 R10, P2, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f5e0ff */
/*0570*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe40007ffe0ff */
/*0580*/ IADD3.X R9, RZ, R9, RZ, P1, !PT ; /* 0x00000009ff097210 */
/* 0x000fe40000ffe4ff */
/*0590*/ IADD3.X R11, RZ, R11, RZ, P2, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fc600017fe4ff */
/*05a0*/ @P0 BRA 0x3b0 ; /* 0xfffffe0000000947 */
/* 0x001fea000383ffff */
/*05b0*/ ISETP.GE.U32.AND P0, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fda0003f06070 */
/*05c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*05d0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*05e0*/ IMAD.WIDE R8, R6, R9, c[0x2][0x0] ; /* 0x0080000006087625 */
/* 0x000fca00078e0209 */
/*05f0*/ IADD3 R10, P0, R8.reuse, c[0x0][0x160], RZ ; /* 0x00005800080a7a10 */
/* 0x040fe40007f1e0ff */
/*0600*/ IADD3 R8, P1, R8, c[0x0][0x168], RZ ; /* 0x00005a0008087a10 */
/* 0x000fe40007f3e0ff */
/*0610*/ IADD3.X R11, R9.reuse, c[0x0][0x164], RZ, P0, !PT ; /* 0x00005900090b7a10 */
/* 0x040fe400007fe4ff */
/*0620*/ IADD3.X R9, R9, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0009097a10 */
/* 0x000fe40000ffe4ff */
/*0630*/ LDG.E R13, [R4.64] ; /* 0x00000008040d7981 */
/* 0x000ea8000c1e1900 */
/*0640*/ LDG.E R14, [R8.64+-0x8] ; /* 0xfffff808080e7981 */
/* 0x000ea8000c1e1900 */
/*0650*/ LDG.E R7, [R2.64] ; /* 0x0000000802077981 */
/* 0x000ee8000c1e1900 */
/*0660*/ LDG.E R12, [R10.64+-0x8] ; /* 0xfffff8080a0c7981 */
/* 0x000ee2000c1e1900 */
/*0670*/ BSSY B0, 0x790 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0680*/ FADD R13, -R13, R14 ; /* 0x0000000e0d0d7221 */
/* 0x004fc40000000100 */
/*0690*/ FADD R7, -R7, R12 ; /* 0x0000000c07077221 */
/* 0x008fe40000000100 */
/*06a0*/ FMUL R12, R13, R13 ; /* 0x0000000d0d0c7220 */
/* 0x000fc80000400000 */
/*06b0*/ FFMA R18, R7, R7, R12 ; /* 0x0000000707127223 */
/* 0x000fc8000000000c */
/*06c0*/ MUFU.RSQ R13, R18 ; /* 0x00000012000d7308 */
/* 0x0002a20000001400 */
/*06d0*/ IADD3 R7, R18, -0xd000000, RZ ; /* 0xf300000012077810 */
/* 0x000fc80007ffe0ff */
/*06e0*/ ISETP.GT.U32.AND P0, PT, R7, 0x727fffff, PT ; /* 0x727fffff0700780c */
/* 0x000fda0003f04070 */
/*06f0*/ @!P0 BRA 0x740 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0700*/ MOV R19, 0x720 ; /* 0x0000072000137802 */
/* 0x006fe40000000f00 */
/*0710*/ CALL.REL.NOINC 0xd20 ; /* 0x0000060000007944 */
/* 0x001fea0003c00000 */
/*0720*/ MOV R7, R13 ; /* 0x0000000d00077202 */
/* 0x000fe20000000f00 */
/*0730*/ BRA 0x780 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0740*/ FMUL.FTZ R7, R18, R13 ; /* 0x0000000d12077220 */
/* 0x006fe40000410000 */
/*0750*/ FMUL.FTZ R13, R13, 0.5 ; /* 0x3f0000000d0d7820 */
/* 0x000fe40000410000 */
/*0760*/ FFMA R12, -R7, R7, R18 ; /* 0x00000007070c7223 */
/* 0x000fc80000000112 */
/*0770*/ FFMA R7, R12, R13, R7 ; /* 0x0000000d0c077223 */
/* 0x000fe40000000007 */
/*0780*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0790*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0011e20000004800 */
/*07a0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe60003800000 */
/*07b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*07c0*/ LDG.E R14, [R4.64] ; /* 0x00000008040e7981 */
/* 0x000ea8000c1e1900 */
/*07d0*/ LDG.E R15, [R8.64+-0x4] ; /* 0xfffffc08080f7981 */
/* 0x000ea8000c1e1900 */
/*07e0*/ LDG.E R12, [R2.64] ; /* 0x00000008020c7981 */
/* 0x000ee8000c1e1900 */
/*07f0*/ LDG.E R13, [R10.64+-0x4] ; /* 0xfffffc080a0d7981 */
/* 0x000ee2000c1e1900 */
/*0800*/ BSSY B0, 0x940 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0810*/ FADD R14, -R14, R15 ; /* 0x0000000f0e0e7221 */
/* 0x004fc40000000100 */
/*0820*/ FADD R12, -R12, R13 ; /* 0x0000000d0c0c7221 */
/* 0x008fe40000000100 */
/*0830*/ FMUL R13, R14, R14 ; /* 0x0000000e0e0d7220 */
/* 0x000fc80000400000 */
/*0840*/ FFMA R18, R12, R12, R13 ; /* 0x0000000c0c127223 */
/* 0x000fc8000000000d */
/*0850*/ MUFU.RSQ R13, R18 ; /* 0x00000012000d7308 */
/* 0x0002a20000001400 */
/*0860*/ IADD3 R7, R18, -0xd000000, RZ ; /* 0xf300000012077810 */
/* 0x001fc80007ffe0ff */
/*0870*/ ISETP.GT.U32.AND P0, PT, R7, 0x727fffff, PT ; /* 0x727fffff0700780c */
/* 0x000fda0003f04070 */
/*0880*/ @!P0 BRA 0x8f0 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0890*/ BSSY B1, 0x8d0 ; /* 0x0000003000017945 */
/* 0x006fe20003800000 */
/*08a0*/ MOV R19, 0x8c0 ; /* 0x000008c000137802 */
/* 0x000fe40000000f00 */
/*08b0*/ CALL.REL.NOINC 0xd20 ; /* 0x0000046000007944 */
/* 0x000fea0003c00000 */
/*08c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08d0*/ MOV R7, R13 ; /* 0x0000000d00077202 */
/* 0x000fe20000000f00 */
/*08e0*/ BRA 0x930 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*08f0*/ FMUL.FTZ R7, R18, R13 ; /* 0x0000000d12077220 */
/* 0x006fe40000410000 */
/*0900*/ FMUL.FTZ R13, R13, 0.5 ; /* 0x3f0000000d0d7820 */
/* 0x000fe40000410000 */
/*0910*/ FFMA R12, -R7, R7, R18 ; /* 0x00000007070c7223 */
/* 0x000fc80000000112 */
/*0920*/ FFMA R7, R12, R13, R7 ; /* 0x0000000d0c077223 */
/* 0x000fe40000000007 */
/*0930*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0940*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0001e80000004800 */
/*0950*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0960*/ LDG.E R14, [R4.64] ; /* 0x00000008040e7981 */
/* 0x000ea8000c1e1900 */
/*0970*/ LDG.E R15, [R8.64] ; /* 0x00000008080f7981 */
/* 0x000ea8000c1e1900 */
/*0980*/ LDG.E R12, [R2.64] ; /* 0x00000008020c7981 */
/* 0x000ee8000c1e1900 */
/*0990*/ LDG.E R13, [R10.64] ; /* 0x000000080a0d7981 */
/* 0x000ee2000c1e1900 */
/*09a0*/ BSSY B0, 0xae0 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*09b0*/ FADD R14, -R14, R15 ; /* 0x0000000f0e0e7221 */
/* 0x004fc40000000100 */
/*09c0*/ FADD R12, -R12, R13 ; /* 0x0000000d0c0c7221 */
/* 0x008fe40000000100 */
/*09d0*/ FMUL R13, R14, R14 ; /* 0x0000000e0e0d7220 */
/* 0x000fc80000400000 */
/*09e0*/ FFMA R18, R12, R12, R13 ; /* 0x0000000c0c127223 */
/* 0x000fc8000000000d */
/*09f0*/ MUFU.RSQ R13, R18 ; /* 0x00000012000d7308 */
/* 0x0000620000001400 */
/*0a00*/ IADD3 R12, R18, -0xd000000, RZ ; /* 0xf3000000120c7810 */
/* 0x000fc80007ffe0ff */
/*0a10*/ ISETP.GT.U32.AND P0, PT, R12, 0x727fffff, PT ; /* 0x727fffff0c00780c */
/* 0x000fda0003f04070 */
/*0a20*/ @!P0 BRA 0xa90 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0a30*/ BSSY B1, 0xa70 ; /* 0x0000003000017945 */
/* 0x003fe20003800000 */
/*0a40*/ MOV R19, 0xa60 ; /* 0x00000a6000137802 */
/* 0x000fe40000000f00 */
/*0a50*/ CALL.REL.NOINC 0xd20 ; /* 0x000002c000007944 */
/* 0x000fea0003c00000 */
/*0a60*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0a70*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000d */
/*0a80*/ BRA 0xad0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0a90*/ FMUL.FTZ R7, R18, R13 ; /* 0x0000000d12077220 */
/* 0x003fe40000410000 */
/*0aa0*/ FMUL.FTZ R13, R13, 0.5 ; /* 0x3f0000000d0d7820 */
/* 0x000fe40000410000 */
/*0ab0*/ FFMA R12, -R7, R7, R18 ; /* 0x00000007070c7223 */
/* 0x000fc80000000112 */
/*0ac0*/ FFMA R7, R12, R13, R7 ; /* 0x0000000d0c077223 */
/* 0x000fe40000000007 */
/*0ad0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0ae0*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0001e80000004800 */
/*0af0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0b00*/ LDG.E R14, [R4.64] ; /* 0x00000008040e7981 */
/* 0x000ea8000c1e1900 */
/*0b10*/ LDG.E R15, [R8.64+0x4] ; /* 0x00000408080f7981 */
/* 0x000ea8000c1e1900 */
/*0b20*/ LDG.E R12, [R2.64] ; /* 0x00000008020c7981 */
/* 0x000ee8000c1e1900 */
/*0b30*/ LDG.E R13, [R10.64+0x4] ; /* 0x000004080a0d7981 */
/* 0x000ee2000c1e1900 */
/*0b40*/ BSSY B0, 0xc80 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0b50*/ FADD R14, -R14, R15 ; /* 0x0000000f0e0e7221 */
/* 0x004fc40000000100 */
/*0b60*/ FADD R12, -R12, R13 ; /* 0x0000000d0c0c7221 */
/* 0x008fe40000000100 */
/*0b70*/ FMUL R13, R14, R14 ; /* 0x0000000e0e0d7220 */
/* 0x000fc80000400000 */
/*0b80*/ FFMA R18, R12, R12, R13 ; /* 0x0000000c0c127223 */
/* 0x000fc8000000000d */
/*0b90*/ MUFU.RSQ R13, R18 ; /* 0x00000012000d7308 */
/* 0x0000620000001400 */
/*0ba0*/ IADD3 R12, R18, -0xd000000, RZ ; /* 0xf3000000120c7810 */
/* 0x000fc80007ffe0ff */
/*0bb0*/ ISETP.GT.U32.AND P0, PT, R12, 0x727fffff, PT ; /* 0x727fffff0c00780c */
/* 0x000fda0003f04070 */
/*0bc0*/ @!P0 BRA 0xc30 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0bd0*/ BSSY B1, 0xc10 ; /* 0x0000003000017945 */
/* 0x003fe20003800000 */
/*0be0*/ MOV R19, 0xc00 ; /* 0x00000c0000137802 */
/* 0x000fe40000000f00 */
/*0bf0*/ CALL.REL.NOINC 0xd20 ; /* 0x0000012000007944 */
/* 0x000fea0003c00000 */
/*0c00*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0c10*/ MOV R7, R13 ; /* 0x0000000d00077202 */
/* 0x000fe20000000f00 */
/*0c20*/ BRA 0xc70 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0c30*/ FMUL.FTZ R7, R18, R13 ; /* 0x0000000d12077220 */
/* 0x003fe40000410000 */
/*0c40*/ FMUL.FTZ R13, R13, 0.5 ; /* 0x3f0000000d0d7820 */
/* 0x000fe40000410000 */
/*0c50*/ FFMA R12, -R7, R7, R18 ; /* 0x00000007070c7223 */
/* 0x000fc80000000112 */
/*0c60*/ FFMA R7, R12, R13, R7 ; /* 0x0000000d0c077223 */
/* 0x000fe40000000007 */
/*0c70*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0c80*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe20007ffe0ff */
/*0c90*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0001e80000004800 */
/*0ca0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0cb0*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fe40003f06270 */
/*0cc0*/ IADD3 R8, P2, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fe40007f5e0ff */
/*0cd0*/ IADD3 R10, P1, R10, 0x10, RZ ; /* 0x000000100a0a7810 */
/* 0x000fc60007f3e0ff */
/*0ce0*/ IMAD.X R9, RZ, RZ, R9, P2 ; /* 0x000000ffff097224 */
/* 0x000fe200010e0609 */
/*0cf0*/ IADD3.X R11, RZ, R11, RZ, P1, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fca0000ffe4ff */
/*0d00*/ @!P0 BRA 0x630 ; /* 0xfffff92000008947 */
/* 0x001fea000383ffff */
/*0d10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d20*/ LOP3.LUT P0, RZ, R18, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff12ff7812 */
/* 0x000fda000780c0ff */
/*0d30*/ @!P0 MOV R13, R18 ; /* 0x00000012000d8202 */
/* 0x000fe20000000f00 */
/*0d40*/ @!P0 BRA 0xe50 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0d50*/ FSETP.GEU.FTZ.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720b */
/* 0x000fda0003f1e000 */
/*0d60*/ @!P0 MOV R13, 0x7fffffff ; /* 0x7fffffff000d8802 */
/* 0x000fe20000000f00 */
/*0d70*/ @!P0 BRA 0xe50 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0d80*/ FSETP.GTU.FTZ.AND P0, PT, |R18|, +INF , PT ; /* 0x7f8000001200780b */
/* 0x000fda0003f1c200 */
/*0d90*/ @P0 FADD.FTZ R13, R18, 1 ; /* 0x3f800000120d0421 */
/* 0x000fe20000010000 */
/*0da0*/ @P0 BRA 0xe50 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0db0*/ FSETP.NEU.FTZ.AND P0, PT, |R18|, +INF , PT ; /* 0x7f8000001200780b */
/* 0x000fda0003f1d200 */
/*0dc0*/ @P0 FFMA R14, R18, 1.84467440737095516160e+19, RZ ; /* 0x5f800000120e0823 */
/* 0x000fc800000000ff */
/*0dd0*/ @P0 MUFU.RSQ R13, R14 ; /* 0x0000000e000d0308 */
/* 0x000e240000001400 */
/*0de0*/ @P0 FMUL.FTZ R15, R14, R13 ; /* 0x0000000d0e0f0220 */
/* 0x001fe40000410000 */
/*0df0*/ @P0 FMUL.FTZ R17, R13, 0.5 ; /* 0x3f0000000d110820 */
/* 0x000fe40000410000 */
/*0e00*/ @P0 FADD.FTZ R16, -R15.reuse, -RZ ; /* 0x800000ff0f100221 */
/* 0x040fe40000010100 */
/*0e10*/ @!P0 IMAD.MOV.U32 R13, RZ, RZ, R18 ; /* 0x000000ffff0d8224 */
/* 0x000fe400078e0012 */
/*0e20*/ @P0 FFMA R16, R15, R16, R14 ; /* 0x000000100f100223 */
/* 0x000fc8000000000e */
/*0e30*/ @P0 FFMA R16, R16, R17, R15 ; /* 0x0000001110100223 */
/* 0x000fc8000000000f */
/*0e40*/ @P0 FMUL.FTZ R13, R16, 2.3283064365386962891e-10 ; /* 0x2f800000100d0820 */
/* 0x000fe40000410000 */
/*0e50*/ HFMA2.MMA R15, -RZ, RZ, 0, 0 ; /* 0x00000000ff0f7435 */
/* 0x000fe200000001ff */
/*0e60*/ MOV R14, R19 ; /* 0x00000013000e7202 */
/* 0x000fca0000000f00 */
/*0e70*/ RET.REL.NODEC R14 0x0 ; /* 0xfffff1800e007950 */
/* 0x000fea0003c3ffff */
/*0e80*/ BRA 0xe80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16minimum_distancePfS_S_i
.globl _Z16minimum_distancePfS_S_i
.p2align 8
.type _Z16minimum_distancePfS_S_i,@function
_Z16minimum_distancePfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0x41200000
global_store_b32 v2, v3, s[4:5]
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_load_b32 s7, s[0:1], 0x18
s_and_b32 s6, 0xffff, s2
s_mov_b32 s9, -1
v_mad_u64_u32 v[2:3], null, s15, s6, v[1:2]
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
buffer_gl1_inv
buffer_gl0_inv
v_cmp_le_i32_e64 s2, s7, v2
v_cmpx_gt_i32_e64 s7, v2
s_cbranch_execz .LBB0_7
v_add_nc_u32_e32 v10, 1, v2
s_mov_b32 s9, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s7, v10
s_cbranch_execz .LBB0_6
s_load_b128 s[12:15], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
v_and_b32_e32 v0, 0x3ff, v0
s_mov_b32 s10, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_lshl_add_u32 v0, v0, 2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v8, s0, v4, 4
v_add_co_ci_u32_e64 v9, s0, 0, v5, s0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, s0, s12, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s13, v5, s0
v_add_co_u32 v4, s0, s14, v4
v_add_co_ci_u32_e64 v5, s0, s15, v5, s0
v_add_co_u32 v6, s0, s12, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s0, s13, v9, s0
v_add_co_u32 v8, s0, s14, v8
v_add_co_ci_u32_e64 v9, s0, s15, v9, s0
.LBB0_5:
global_load_b32 v11, v[8:9], off
global_load_b32 v12, v[4:5], off
global_load_b32 v13, v[6:7], off
global_load_b32 v14, v[2:3], off
v_add_nc_u32_e32 v10, 1, v10
v_add_co_u32 v6, s1, v6, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s1, 0, v7, s1
v_add_co_u32 v8, s1, v8, 4
v_add_co_ci_u32_e64 v9, s1, 0, v9, s1
s_waitcnt vmcnt(2)
v_sub_f32_e32 v11, v11, v12
v_cmp_le_i32_e64 s1, s7, v10
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v12, v13, v14 :: v_dual_mul_f32 v11, v11, v11
s_or_b32 s10, s1, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v11, v12, v12
v_mul_f32_e32 v12, 0x4f800000, v11
v_cmp_gt_f32_e64 s0, 0xf800000, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v11, v11, v12, s0
v_sqrt_f32_e32 v12, v11
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v13, -1, v12
v_add_nc_u32_e32 v14, 1, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v15, -v13, v12, v11
v_fma_f32 v16, -v14, v12, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s3, 0, v15
v_cndmask_b32_e64 v12, v12, v13, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s3, 0, v16
v_cndmask_b32_e64 v12, v12, v14, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v13, 0x37800000, v12
v_cndmask_b32_e64 v12, v12, v13, s0
v_cmp_class_f32_e64 s0, v11, 0x260
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v11, v12, v11, s0
ds_store_b32 v0, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_5
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_or_not1_b32 s9, s2, exec_lo
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s8
s_and_saveexec_b32 s0, s9
s_cbranch_execz .LBB0_17
s_cmp_lt_u32 s6, 2
s_cbranch_scc1 .LBB0_14
v_lshl_add_u32 v0, v1, 2, 0
s_branch .LBB0_11
.p2align 6
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s2
s_cmp_lt_u32 s1, 4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_14
.LBB0_11:
s_mov_b32 s1, s6
s_lshr_b32 s6, s6, 1
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s6, v1
s_cbranch_execz .LBB0_10
v_add_nc_u32_e32 v2, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v3, v0
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e64 s0, v3, v2
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_10
ds_store_b32 v0, v2
s_branch .LBB0_10
.LBB0_14:
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_17
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
global_load_b32 v2, v0, s[4:5]
ds_load_b32 v1, v1
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_ngt_f32_e32 vcc_lo, v2, v1
s_cbranch_vccnz .LBB0_17
global_store_b32 v0, v1, s[4:5]
.LBB0_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16minimum_distancePfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16minimum_distancePfS_S_i, .Lfunc_end0-_Z16minimum_distancePfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16minimum_distancePfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16minimum_distancePfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bd9bd_00000000-6_sidney.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z16minimum_distancePfS_S_iPfS_S_i
.type _Z41__device_stub__Z16minimum_distancePfS_S_iPfS_S_i, @function
_Z41__device_stub__Z16minimum_distancePfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16minimum_distancePfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z41__device_stub__Z16minimum_distancePfS_S_iPfS_S_i, .-_Z41__device_stub__Z16minimum_distancePfS_S_iPfS_S_i
.globl _Z16minimum_distancePfS_S_i
.type _Z16minimum_distancePfS_S_i, @function
_Z16minimum_distancePfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16minimum_distancePfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z16minimum_distancePfS_S_i, .-_Z16minimum_distancePfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Use: %s <number of points>\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Maximum number of points allowed: %d\n"
.section .rodata.str1.1
.LC3:
.string "Number of Points = %d\n"
.LC4:
.string "GPU Host-to-device = %f ms \n"
.LC5:
.string "GPU execution time = %f ms \n"
.LC6:
.string "GPU Device-to-host = %f ms \n"
.LC7:
.string "Minimum distance (GPU) = %e\n"
.LC9:
.string "CPU execution time = %f ms\n"
.LC10:
.string "Minimum distance (CPU) = %e\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movl %edi, %ebx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $0, 20(%rsp)
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
cmpl $2, %ebx
je .L12
movq 0(%rbp), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L12:
movq 8(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, num_points(%rip)
cmpl $1048576, %eax
jle .L13
movl $1048576, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L13:
leal 0(,%rax,4), %r14d
movslq %r14d, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbx
movl $4, %edi
call malloc@PLT
movq %rax, %r12
testl %r13d, %r13d
jle .L14
movl $0, %r13d
.L15:
leaq 20(%rsp), %r15
movq %r15, %rdi
call rand_r@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
movss %xmm0, 0(%rbp,%r13,4)
movq %r15, %rdi
call rand_r@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
movss %xmm0, (%rbx,%r13,4)
addq $1, %r13
cmpl %r13d, num_points(%rip)
jg .L15
.L14:
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 96(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $16, threads(%rip)
movl num_points(%rip), %eax
movl $16, %ecx
cltd
idivl %ecx
movl %eax, blocks(%rip)
movl $16, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L16:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 100(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $4, %edx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 104(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl num_points(%rip), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 96(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 100(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 104(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movss 4(%rbp), %xmm0
subss 0(%rbp), %xmm0
movss 4(%rbx), %xmm1
subss (%rbx), %xmm1
mulss %xmm0, %xmm0
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
call sqrtf@PLT
movss %xmm0, 12(%rsp)
movl num_points(%rip), %edx
testl %edx, %edx
jle .L17
movslq %edx, %rsi
movl $1, %ecx
jmp .L21
.L28:
movl num_points(%rip), %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z41__device_stub__Z16minimum_distancePfS_S_iPfS_S_i
jmp .L16
.L24:
movq %rax, %rcx
.L21:
cmpl %ecx, %edx
jle .L18
movss -4(%rbp,%rcx,4), %xmm3
movss -4(%rbx,%rcx,4), %xmm2
movq %rcx, %rax
.L20:
movss 0(%rbp,%rax,4), %xmm0
subss %xmm3, %xmm0
movss (%rbx,%rax,4), %xmm1
subss %xmm2, %xmm1
mulss %xmm0, %xmm0
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
sqrtss %xmm0, %xmm0
minss 12(%rsp), %xmm0
movss %xmm0, 12(%rsp)
addq $1, %rax
cmpl %eax, %edx
jg .L20
.L18:
leaq 1(%rcx), %rax
cmpq %rcx, %rsi
jne .L24
.L17:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 80(%rsp), %rax
subq 64(%rsp), %rax
imulq $1000, %rax, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
mulsd .LC8(%rip), %xmm1
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 108(%rsp)
cvtss2sd %xmm0, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z16minimum_distancePfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z16minimum_distancePfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl num_points
.bss
.align 4
.type num_points, @object
.size num_points, 4
num_points:
.zero 4
.globl threads
.align 4
.type threads, @object
.size threads, 4
threads:
.zero 4
.globl blocks
.align 4
.type blocks, @object
.size blocks, 4
blocks:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 805306368
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sidney.hip"
.globl _Z31__device_stub__minimum_distancePfS_S_i # -- Begin function _Z31__device_stub__minimum_distancePfS_S_i
.p2align 4, 0x90
.type _Z31__device_stub__minimum_distancePfS_S_i,@function
_Z31__device_stub__minimum_distancePfS_S_i: # @_Z31__device_stub__minimum_distancePfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16minimum_distancePfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__minimum_distancePfS_S_i, .Lfunc_end0-_Z31__device_stub__minimum_distancePfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movl $0, 56(%rsp)
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
cmpl $2, %ebp
jne .LBB1_22
# %bb.1:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, num_points(%rip)
cmpl $1048577, %eax # imm = 0x100001
jge .LBB1_23
# %bb.2:
shll $2, %eax
movslq %eax, %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movl $4, %edi
callq malloc
movq %rax, %rbp
cmpl $0, num_points(%rip)
jle .LBB1_5
# %bb.3: # %.lr.ph.preheader
xorl %r15d, %r15d
leaq 56(%rsp), %r13
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r13, %rdi
callq rand_r
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%r15,4)
movq %r13, %rdi
callq rand_r
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
movslq num_points(%rip), %rax
cmpq %rax, %r15
jl .LBB1_4
.LBB1_5: # %._crit_edge
leaq 48(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 176(%rsp), %rdi
callq hipEventElapsedTime
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $16, threads(%rip)
movl num_points(%rip), %eax
leal 15(%rax), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $4, %edi
movl %edi, blocks(%rip)
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $16, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movl num_points(%rip), %esi
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %esi, 60(%rsp)
leaq 168(%rsp), %rax
movq %rax, 80(%rsp)
leaq 160(%rsp), %rax
movq %rax, 88(%rsp)
leaq 152(%rsp), %rax
movq %rax, 96(%rsp)
leaq 60(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16minimum_distancePfS_S_i, %edi
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
leaq 180(%rsp), %rdi
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
callq hipEventElapsedTime
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rsi
movl $4, %edx
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
leaq 184(%rsp), %rdi
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
callq hipEventElapsedTime
movl num_points(%rip), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movss 176(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movss 180(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movss 184(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movss (%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
leaq 80(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movss 4(%rbx), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss (%rbx), %xmm1
movss 4(%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%r14), %xmm0
mulss %xmm1, %xmm1
mulss %xmm0, %xmm0
addss %xmm1, %xmm0
xorps %xmm1, %xmm1
ucomiss %xmm1, %xmm0
jb .LBB1_9
# %bb.8:
sqrtss %xmm0, %xmm3
jmp .LBB1_10
.LBB1_9: # %call.sqrt
callq sqrtf
movaps %xmm0, %xmm3
.LBB1_10: # %.split
movq %rbp, 112(%rsp) # 8-byte Spill
cmpl $0, num_points(%rip)
jle .LBB1_11
# %bb.13: # %.lr.ph71.preheader
movl $1, %r15d
xorl %r13d, %r13d
xorps %xmm2, %xmm2
jmp .LBB1_15
.p2align 4, 0x90
.LBB1_16: # in Loop: Header=BB1_15 Depth=1
movaps %xmm3, %xmm0
.LBB1_14: # %.loopexit
# in Loop: Header=BB1_15 Depth=1
movslq num_points(%rip), %rax
incq %r15
movaps %xmm0, %xmm3
cmpq %rax, %r13
jge .LBB1_12
.LBB1_15: # %.lr.ph71
# =>This Loop Header: Depth=1
# Child Loop BB1_18 Depth 2
movq %r13, %rbp
incq %r13
movslq num_points(%rip), %rax
cmpq %rax, %r13
jge .LBB1_16
# %bb.17: # %.lr.ph67
# in Loop: Header=BB1_15 Depth=1
movq %r15, %r12
jmp .LBB1_18
.p2align 4, 0x90
.LBB1_20: # %call.sqrt87
# in Loop: Header=BB1_18 Depth=2
movss %xmm3, 20(%rsp) # 4-byte Spill
callq sqrtf
movss 20(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
xorps %xmm2, %xmm2
.LBB1_21: # %.split86
# in Loop: Header=BB1_18 Depth=2
minss %xmm3, %xmm0
incq %r12
movaps %xmm0, %xmm3
cmpl %r12d, num_points(%rip)
jle .LBB1_14
.LBB1_18: # Parent Loop BB1_15 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss (%rbx,%rbp,4), %xmm1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%r14,%rbp,4), %xmm0
mulss %xmm1, %xmm1
mulss %xmm0, %xmm0
addss %xmm1, %xmm0
ucomiss %xmm2, %xmm0
jb .LBB1_20
# %bb.19: # in Loop: Header=BB1_18 Depth=2
sqrtss %xmm0, %xmm0
jmp .LBB1_21
.LBB1_11:
movaps %xmm3, %xmm0
.LBB1_12: # %._crit_edge72
movss %xmm0, 20(%rsp) # 4-byte Spill
leaq 64(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 64(%rsp), %rax
subq 80(%rsp), %rax
movq 72(%rsp), %rcx
imulq $1000, %rax, %rax # imm = 0x3E8
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
subq 88(%rsp), %rcx
xorps %xmm1, %xmm1
cvtsi2sd %rcx, %xmm1
mulsd .LCPI1_1(%rip), %xmm1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
movss %xmm0, 188(%rsp)
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movss 20(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 112(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_22:
.cfi_def_cfa_offset 272
movq (%rbx), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.LBB1_23:
movl $.L.str.1, %edi
movl $1048576, %esi # imm = 0x100000
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16minimum_distancePfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type blocks,@object # @blocks
.bss
.globl blocks
.p2align 2, 0x0
blocks:
.long 0 # 0x0
.size blocks, 4
.type threads,@object # @threads
.globl threads
.p2align 2, 0x0
threads:
.long 0 # 0x0
.size threads, 4
.type num_points,@object # @num_points
.globl num_points
.p2align 2, 0x0
num_points:
.long 0 # 0x0
.size num_points, 4
.type _Z16minimum_distancePfS_S_i,@object # @_Z16minimum_distancePfS_S_i
.section .rodata,"a",@progbits
.globl _Z16minimum_distancePfS_S_i
.p2align 3, 0x0
_Z16minimum_distancePfS_S_i:
.quad _Z31__device_stub__minimum_distancePfS_S_i
.size _Z16minimum_distancePfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Use: %s <number of points>\n"
.size .L.str, 28
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Maximum number of points allowed: %d\n"
.size .L.str.1, 38
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Number of Points = %d\n"
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPU Host-to-device = %f ms \n"
.size .L.str.3, 29
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPU execution time = %f ms \n"
.size .L.str.4, 29
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "GPU Device-to-host = %f ms \n"
.size .L.str.5, 29
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Minimum distance (GPU) = %e\n"
.size .L.str.6, 29
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "CPU execution time = %f ms\n"
.size .L.str.7, 28
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Minimum distance (CPU) = %e\n"
.size .L.str.8, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16minimum_distancePfS_S_i"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__minimum_distancePfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16minimum_distancePfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <unistd.h>
extern "C" __device__ void profileCount(long index){
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <unistd.h>
extern "C" __device__ void profileCount(long index){
} | .file "tmpxft_000762f1_00000000-6_instCount.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl profileCount
.type profileCount, @function
profileCount:
.LFB2070:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2070:
.size profileCount, .-profileCount
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <unistd.h>
extern "C" __device__ void profileCount(long index){
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <unistd.h>
extern "C" __device__ void profileCount(long index){
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <unistd.h>
extern "C" __device__ void profileCount(long index){
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <unistd.h>
extern "C" __device__ void profileCount(long index){
} | .text
.file "instCount.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000762f1_00000000-6_instCount.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl profileCount
.type profileCount, @function
profileCount:
.LFB2070:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2070:
.size profileCount, .-profileCount
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "instCount.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void helloworld(void)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
printf("Hello World from (%d,%d)!\n", i , j);
}
int main()
{
dim3 grid(2,4);
dim3 block(8,16);
helloworld <<<grid,block>>>();
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z10helloworldv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0040*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0050*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fc60007f1e0ff */
/*0060*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e640000002500 */
/*0070*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe400000e06ff */
/*0080*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R3, R3, c[0x0][0x4], R0 ; /* 0x0000010003037a24 */
/* 0x001fe200078e0200 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fc80000000f00 */
/*00b0*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0000a20000000a00 */
/*00c0*/ IMAD R2, R2, c[0x0][0x0], R5 ; /* 0x0000000002027a24 */
/* 0x002fe400078e0205 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fc600078e00ff */
/*00e0*/ STL.64 [R1], R2 ; /* 0x0000000201007387 */
/* 0x0001e80000100a00 */
/*00f0*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x001fe40000000000 */
/*0100*/ MOV R11, 0x170 ; /* 0x00000170000b7802 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R20, 0xf0 ; /* 0x000000f000147802 */
/* 0x000fe40000000f00 */
/*0120*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0140*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*0150*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0160*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x004fea0003c00000 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void helloworld(void)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
printf("Hello World from (%d,%d)!\n", i , j);
}
int main()
{
dim3 grid(2,4);
dim3 block(8,16);
helloworld <<<grid,block>>>();
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_00167643_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10helloworldvv
.type _Z29__device_stub__Z10helloworldvv, @function
_Z29__device_stub__Z10helloworldvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10helloworldv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10helloworldvv, .-_Z29__device_stub__Z10helloworldvv
.globl _Z10helloworldv
.type _Z10helloworldv, @function
_Z10helloworldv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10helloworldvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10helloworldv, .-_Z10helloworldv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $2, 8(%rsp)
movl $4, 12(%rsp)
movl $8, 20(%rsp)
movl $16, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10helloworldvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10helloworldv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10helloworldv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void helloworld(void)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
printf("Hello World from (%d,%d)!\n", i , j);
}
int main()
{
dim3 grid(2,4);
dim3 block(8,16);
helloworld <<<grid,block>>>();
cudaDeviceSynchronize();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void helloworld(void)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
printf("Hello World from (%d,%d)!\n", i , j);
}
int main()
{
dim3 grid(2,4);
dim3 block(8,16);
helloworld <<<grid,block>>>();
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void helloworld(void)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
printf("Hello World from (%d,%d)!\n", i , j);
}
int main()
{
dim3 grid(2,4);
dim3 block(8,16);
helloworld <<<grid,block>>>();
hipDeviceSynchronize();
return 0;
} | .text
.file "hello.hip"
.globl _Z25__device_stub__helloworldv # -- Begin function _Z25__device_stub__helloworldv
.p2align 4, 0x90
.type _Z25__device_stub__helloworldv,@function
_Z25__device_stub__helloworldv: # @_Z25__device_stub__helloworldv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10helloworldv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__helloworldv, .Lfunc_end0-_Z25__device_stub__helloworldv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $17179869186, %rdi # imm = 0x400000002
movabsq $68719476744, %rdx # imm = 0x1000000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10helloworldv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10helloworldv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10helloworldv,@object # @_Z10helloworldv
.section .rodata,"a",@progbits
.globl _Z10helloworldv
.p2align 3, 0x0
_Z10helloworldv:
.quad _Z25__device_stub__helloworldv
.size _Z10helloworldv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10helloworldv"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__helloworldv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10helloworldv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00167643_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10helloworldvv
.type _Z29__device_stub__Z10helloworldvv, @function
_Z29__device_stub__Z10helloworldvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10helloworldv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10helloworldvv, .-_Z29__device_stub__Z10helloworldvv
.globl _Z10helloworldv
.type _Z10helloworldv, @function
_Z10helloworldv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10helloworldvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10helloworldv, .-_Z10helloworldv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $2, 8(%rsp)
movl $4, 12(%rsp)
movl $8, 20(%rsp)
movl $16, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10helloworldvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10helloworldv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10helloworldv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello.hip"
.globl _Z25__device_stub__helloworldv # -- Begin function _Z25__device_stub__helloworldv
.p2align 4, 0x90
.type _Z25__device_stub__helloworldv,@function
_Z25__device_stub__helloworldv: # @_Z25__device_stub__helloworldv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10helloworldv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__helloworldv, .Lfunc_end0-_Z25__device_stub__helloworldv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $17179869186, %rdi # imm = 0x400000002
movabsq $68719476744, %rdx # imm = 0x1000000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10helloworldv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10helloworldv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10helloworldv,@object # @_Z10helloworldv
.section .rodata,"a",@progbits
.globl _Z10helloworldv
.p2align 3, 0x0
_Z10helloworldv:
.quad _Z25__device_stub__helloworldv
.size _Z10helloworldv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10helloworldv"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__helloworldv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10helloworldv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <limits.h>
#include <string.h>
#include <sys/time.h>
#include <time.h>
#include <iostream>
using namespace std;
/*structure of the nodes of the tree*/
__host__ __device__ int strcmp_(char* str1,char* str2){
const unsigned char* ptr1= (const unsigned char*)str1;
const unsigned char* ptr2= (const unsigned char*)str2;
while(ptr1 && *ptr1 == *ptr2)
++ptr1, ++ptr2;
return *ptr1 - *ptr2;
}
template<class T>
class Node{
public:
int parent;
T key[80];
int height;
int left;
int right;
int succ,pred;
__host__ __device__ Node(T* key_){
strcpy(key,key_);
parent=height=left=right=INT_MIN;
succ=pred=INT_MIN;
}
__host__ __device__ Node(){
new(this)Node("");
}
friend ostream &operator<<(ostream &os, Node& node){
os << node.key;
return os;
}
__host__ __device__ bool operator<(Node &node){
return strcmp_(key,node.key)<0;
}
__host__ __device__ bool operator==(Node& node){
return strcmp_(key,node.key)==0;
}
__host__ __device__ bool operator>(Node &node){
return strcmp_(key,node.key)>0;
}
};
/*Definition of the tree*/
template<class T>
class Tree{
public:
int root,next_index;
int size;
/*container of the tree*/
//node at index 0 is sentinel node with key INT_MIN
// initialized root with key INT_MAX and index=1
Node<T>* arr;
__host__ __device__ Tree(int size_):root(1),next_index(2),size(size_){
arr= new Node<T>[size];
char str_[80];
for(int i=0;i<79;++i)
str_[i]=(char)127;
strcpy(arr[root].key,str_);
arr[root].parent = 0;
arr[0].right= root;
arr[root].pred= 0;
arr[0].succ= root;
arr[root].height=0;
};
__host__ __device__ Tree(){}
void inorder(int);
void preorder(int);
void postorder(int);
__host__ __device__ int search(Node<T>&);
__host__ __device__ int search(T*);
__host__ __device__ int height(int);
__host__ __device__ void insert(T*);
__host__ __device__ void delete_(T*);
__host__ __device__ void delete_rebalance(int);
__host__ __device__ void init_node(Node<T>&, int, int, int, int);
__host__ __device__ int tri_node_restructure(int, int, int);
__host__ __device__ void recompute_height(int);
__host__ __device__ int taller_child(int);
__host__ __device__ bool search_2(T*);
void insert_nodes(char*,int);
};
template<class T>
void Tree<T>::inorder(int index){
if(index==INT_MIN || strcmp_(arr[index].key,"")==0)
return;
inorder(arr[index].left);
cout<< arr[index] <<"\n";
inorder(arr[index].right);
}
template<class T>
void Tree<T>::preorder(int index){
if(index==INT_MIN || strcmp_(arr[index],"")==0)
return;
cout << arr[index] <<" ";
preorder(arr[index].left);
preorder(arr[index].right);
}
template<class T>
void Tree<T>::postorder(int index){
if(index==INT_MIN || strcmp_(arr[index].key,"")==0)
return;
postorder(arr[index].left);
postorder(arr[index].right);
cout << arr[index] <<" ";
}
template<typename T> __host__ __device__
int Tree<T>::search(Node<T> &node){
int temp=root;
while(temp!=INT_MIN){
if(arr[temp]==node)
return temp;
int child= (arr[temp]<node? arr[temp].right:
arr[temp].left);
if(child==INT_MIN)
return temp;
temp= child;
}
return temp;
}
template<typename T> __host__ __device__
int Tree<T>::search(T* key_){
int temp= root;
while(temp!=INT_MIN){
if(arr[temp].key == key_)
return temp;
int child= (arr[temp].key <key_?arr[temp].right
:arr[temp].left);
if(child==INT_MIN)
return temp;
temp=child;
}
return temp;
}
template<typename T> __host__ __device__
void Tree<T>::recompute_height(int x){
while(x!=root){
arr[x].height = max(height(arr[x].right), height(arr[x].left));
x= arr[x].parent;
}
}
template<typename T> __host__ __device__
int Tree<T>::height(int index){
if(index==INT_MIN)
return 0;
return arr[index].height+1;
}
template<typename T> __host__ __device__
int Tree<T>::tri_node_restructure(int x, int y, int z){
/*
x= parent(y)
y= parent(z)
*/
bool z_is_left_child= (arr[y].left ==z);
bool y_is_left_child = (arr[x].left== y);
int a=INT_MIN,b=INT_MIN,c=INT_MIN;
int t0=INT_MIN,t1=INT_MIN,t2=INT_MIN,t3=INT_MIN;
if(z_is_left_child && y_is_left_child){
a= z; b = y; c= x;
t0 = arr[z].left; t1= arr[z].right;
t2= arr[y].right; t3= arr[x].right;
// printf("first if: %d %d %d %d\n",t0,t1,t2,t3);
}else if(!z_is_left_child && y_is_left_child){
a= y; b=z; c= x;
t0= arr[y].left; t1= arr[z].left;
t2= arr[z].right; t3= arr[x].right;
// printf("second if: %d %d %d %d\n",t0,t1,t2,t3);
}else if(z_is_left_child && !y_is_left_child){
a=x; c= y; b=z;
t0= arr[x].left; t1= arr[z].left;
t2= arr[z].right; t3= arr[y].right;
// printf("third if: %d %d %d %d\n",t0,t1,t2,t3);
}else{
a=x; b=y; c=z;
t0= arr[x].left; t1= arr[y].left;
t2= arr[z].left; t3= arr[z].right;
// printf("fourth if:%d %d %d %d %d\n",arr[z].left,t0,t1,t2,t3);
}
// attach b to the parent of x
if(x==root){
root= b;
arr[b].parent= INT_MIN;
}else{
int parent_x= arr[x].parent;
arr[b].parent=parent_x;
if(arr[parent_x].left == x)
arr[parent_x].left = b;
else arr[parent_x].right = b;
}
/* make b
/ \
a c */
arr[b].left= a;
arr[a].parent= b;
arr[b].right = c;
arr[c].parent =b;
/*attach t0, t1, t2 and t3*/
arr[a].left = t0;
if(t0!=INT_MIN) arr[t0].parent = a;
arr[a].right = t1;
if(t1!=INT_MIN) arr[t1].parent = a;
arr[c].left= t2;
if(t2!=INT_MIN) arr[t2].parent = c;
arr[c].right = t3;
if(t3!=INT_MIN) arr[t3].parent = c;
recompute_height(a);
recompute_height(c);
return b;
}
template<typename T> __host__ __device__
void Tree<T>::init_node(Node<T>& node,int curr_ind, int pred_, int succ_, int parent_){
arr[curr_ind].parent= parent_;
arr[curr_ind].height=0;
arr[curr_ind].pred= pred_;
arr[curr_ind].succ= succ_;
arr[succ_].pred= curr_ind;
arr[pred_].succ= curr_ind;
if(arr[parent_] < node)
arr[parent_].right= curr_ind;
else arr[parent_].left= curr_ind;
}
template<typename T> __host__ __device__
void Tree<T>::insert(T* key_){
strcpy(arr[next_index].key,key_);
int p= search(arr[next_index]);
if(arr[p] == arr[next_index]){
strcpy(arr[next_index].key,"");
return;
}
int pred_= arr[p] < arr[next_index]?p: arr[p].pred;
int succ_= arr[pred_].succ;
init_node(arr[next_index],next_index,pred_,succ_,p);
// // after insert maximum one node will get imbalanced
recompute_height(p);
int x,y,z;
x=y=z= next_index;
while(x!=root){
if(abs(height(arr[x].left) - height(arr[x].right))<=1){
z=y;
y=x;
x= arr[x].parent;
}else break;
}
if(x!=root)
tri_node_restructure(x,y,z);
++next_index;
}
template<typename T> __host__ __device__
int Tree<T>::taller_child(int x){
return (height(arr[x].left) > height(arr[x].right)?
arr[x].left : arr[x].right);
}
template<typename T> __host__ __device__
void Tree<T>::delete_rebalance(int p){
int x,y,z;
while(p!=root){
if(abs(height(arr[p].left)-height(arr[p].right))>1){
x=p;
y= taller_child(x);
z= taller_child(y);
p= tri_node_restructure(x,y,z);
}
p=arr[p].parent;
}
}
template<typename T> __host__ __device__
void Tree<T>::delete_(T* key_){
int p;
int parent_;
int succ_;
p= search(key_);
if(strcmp_(arr[p].key,key_)==0)
return;
// node has no children
parent_ = arr[p].parent;
if(arr[p].left==INT_MIN && arr[p].right == INT_MIN){
if(arr[parent_].right == p)
arr[parent_].right= INT_MIN;
else arr[parent_].left = INT_MIN;
recompute_height(parent_);
delete_rebalance(parent_);
return;
}else if(arr[p].left==INT_MIN){ // when deleted node has only right child
if(arr[parent_].left==p)
arr[parent_].left= arr[p].right;
else arr[parent_].right = arr[p].right;
recompute_height(parent_);
delete_rebalance(parent_);
return;
}else if(arr[p].right == INT_MIN){ // when deleted node has only left child
if(arr[parent_].left==p)
arr[parent_].left= arr[p].left;
else arr[parent_].right= arr[p].left;
recompute_height(parent_);
delete_rebalance(parent_);
return;
} // when deleted node has both children
succ_ = arr[p].right;
while(arr[succ_].left!=INT_MIN)
succ_ = arr[succ_].left;
strcpy(arr[p].key,arr[succ_].key);
parent_= arr[succ_].parent;
arr[parent_].left = arr[succ_].right;
recompute_height(parent_);
delete_rebalance(parent_);
return;
}
template<typename T> __host__ __device__
bool Tree<T>::search_2(T* key_){
int p=search(key_);
Node<char> node= Node<char>(key_);
while(arr[p]> node)
p= arr[p].pred;
int x= p;
while(arr[p]< node)
p= arr[p].succ;
int y=p;
return (arr[x] == node ||arr[y] == node);
}
template<typename T>
void Tree<T>::insert_nodes(char* filename,int max){
FILE* fp= fopen(filename,"r");
char buff[200];
fgets(buff,200,fp);
int size= atoi(buff);
Tree<char>*tree= new Tree(size+max);
while(fgets(buff,200,fp)!=NULL){
buff[strlen(buff)-1]='\0';
char* temp1= strtok(buff,"$");
char* temp2= strtok(NULL,"$");
// // Node<char> *node=new Node<char>(temp1);
tree->insert(temp1);
}
fclose(fp);
*this = *tree;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <limits.h>
#include <string.h>
#include <sys/time.h>
#include <time.h>
#include <iostream>
using namespace std;
/*structure of the nodes of the tree*/
__host__ __device__ int strcmp_(char* str1,char* str2){
const unsigned char* ptr1= (const unsigned char*)str1;
const unsigned char* ptr2= (const unsigned char*)str2;
while(ptr1 && *ptr1 == *ptr2)
++ptr1, ++ptr2;
return *ptr1 - *ptr2;
}
template<class T>
class Node{
public:
int parent;
T key[80];
int height;
int left;
int right;
int succ,pred;
__host__ __device__ Node(T* key_){
strcpy(key,key_);
parent=height=left=right=INT_MIN;
succ=pred=INT_MIN;
}
__host__ __device__ Node(){
new(this)Node("");
}
friend ostream &operator<<(ostream &os, Node& node){
os << node.key;
return os;
}
__host__ __device__ bool operator<(Node &node){
return strcmp_(key,node.key)<0;
}
__host__ __device__ bool operator==(Node& node){
return strcmp_(key,node.key)==0;
}
__host__ __device__ bool operator>(Node &node){
return strcmp_(key,node.key)>0;
}
};
/*Definition of the tree*/
template<class T>
class Tree{
public:
int root,next_index;
int size;
/*container of the tree*/
//node at index 0 is sentinel node with key INT_MIN
// initialized root with key INT_MAX and index=1
Node<T>* arr;
__host__ __device__ Tree(int size_):root(1),next_index(2),size(size_){
arr= new Node<T>[size];
char str_[80];
for(int i=0;i<79;++i)
str_[i]=(char)127;
strcpy(arr[root].key,str_);
arr[root].parent = 0;
arr[0].right= root;
arr[root].pred= 0;
arr[0].succ= root;
arr[root].height=0;
};
__host__ __device__ Tree(){}
void inorder(int);
void preorder(int);
void postorder(int);
__host__ __device__ int search(Node<T>&);
__host__ __device__ int search(T*);
__host__ __device__ int height(int);
__host__ __device__ void insert(T*);
__host__ __device__ void delete_(T*);
__host__ __device__ void delete_rebalance(int);
__host__ __device__ void init_node(Node<T>&, int, int, int, int);
__host__ __device__ int tri_node_restructure(int, int, int);
__host__ __device__ void recompute_height(int);
__host__ __device__ int taller_child(int);
__host__ __device__ bool search_2(T*);
void insert_nodes(char*,int);
};
template<class T>
void Tree<T>::inorder(int index){
if(index==INT_MIN || strcmp_(arr[index].key,"")==0)
return;
inorder(arr[index].left);
cout<< arr[index] <<"\n";
inorder(arr[index].right);
}
template<class T>
void Tree<T>::preorder(int index){
if(index==INT_MIN || strcmp_(arr[index],"")==0)
return;
cout << arr[index] <<" ";
preorder(arr[index].left);
preorder(arr[index].right);
}
template<class T>
void Tree<T>::postorder(int index){
if(index==INT_MIN || strcmp_(arr[index].key,"")==0)
return;
postorder(arr[index].left);
postorder(arr[index].right);
cout << arr[index] <<" ";
}
template<typename T> __host__ __device__
int Tree<T>::search(Node<T> &node){
int temp=root;
while(temp!=INT_MIN){
if(arr[temp]==node)
return temp;
int child= (arr[temp]<node? arr[temp].right:
arr[temp].left);
if(child==INT_MIN)
return temp;
temp= child;
}
return temp;
}
template<typename T> __host__ __device__
int Tree<T>::search(T* key_){
int temp= root;
while(temp!=INT_MIN){
if(arr[temp].key == key_)
return temp;
int child= (arr[temp].key <key_?arr[temp].right
:arr[temp].left);
if(child==INT_MIN)
return temp;
temp=child;
}
return temp;
}
template<typename T> __host__ __device__
void Tree<T>::recompute_height(int x){
while(x!=root){
arr[x].height = max(height(arr[x].right), height(arr[x].left));
x= arr[x].parent;
}
}
template<typename T> __host__ __device__
int Tree<T>::height(int index){
if(index==INT_MIN)
return 0;
return arr[index].height+1;
}
template<typename T> __host__ __device__
int Tree<T>::tri_node_restructure(int x, int y, int z){
/*
x= parent(y)
y= parent(z)
*/
bool z_is_left_child= (arr[y].left ==z);
bool y_is_left_child = (arr[x].left== y);
int a=INT_MIN,b=INT_MIN,c=INT_MIN;
int t0=INT_MIN,t1=INT_MIN,t2=INT_MIN,t3=INT_MIN;
if(z_is_left_child && y_is_left_child){
a= z; b = y; c= x;
t0 = arr[z].left; t1= arr[z].right;
t2= arr[y].right; t3= arr[x].right;
// printf("first if: %d %d %d %d\n",t0,t1,t2,t3);
}else if(!z_is_left_child && y_is_left_child){
a= y; b=z; c= x;
t0= arr[y].left; t1= arr[z].left;
t2= arr[z].right; t3= arr[x].right;
// printf("second if: %d %d %d %d\n",t0,t1,t2,t3);
}else if(z_is_left_child && !y_is_left_child){
a=x; c= y; b=z;
t0= arr[x].left; t1= arr[z].left;
t2= arr[z].right; t3= arr[y].right;
// printf("third if: %d %d %d %d\n",t0,t1,t2,t3);
}else{
a=x; b=y; c=z;
t0= arr[x].left; t1= arr[y].left;
t2= arr[z].left; t3= arr[z].right;
// printf("fourth if:%d %d %d %d %d\n",arr[z].left,t0,t1,t2,t3);
}
// attach b to the parent of x
if(x==root){
root= b;
arr[b].parent= INT_MIN;
}else{
int parent_x= arr[x].parent;
arr[b].parent=parent_x;
if(arr[parent_x].left == x)
arr[parent_x].left = b;
else arr[parent_x].right = b;
}
/* make b
/ \
a c */
arr[b].left= a;
arr[a].parent= b;
arr[b].right = c;
arr[c].parent =b;
/*attach t0, t1, t2 and t3*/
arr[a].left = t0;
if(t0!=INT_MIN) arr[t0].parent = a;
arr[a].right = t1;
if(t1!=INT_MIN) arr[t1].parent = a;
arr[c].left= t2;
if(t2!=INT_MIN) arr[t2].parent = c;
arr[c].right = t3;
if(t3!=INT_MIN) arr[t3].parent = c;
recompute_height(a);
recompute_height(c);
return b;
}
template<typename T> __host__ __device__
void Tree<T>::init_node(Node<T>& node,int curr_ind, int pred_, int succ_, int parent_){
arr[curr_ind].parent= parent_;
arr[curr_ind].height=0;
arr[curr_ind].pred= pred_;
arr[curr_ind].succ= succ_;
arr[succ_].pred= curr_ind;
arr[pred_].succ= curr_ind;
if(arr[parent_] < node)
arr[parent_].right= curr_ind;
else arr[parent_].left= curr_ind;
}
template<typename T> __host__ __device__
void Tree<T>::insert(T* key_){
strcpy(arr[next_index].key,key_);
int p= search(arr[next_index]);
if(arr[p] == arr[next_index]){
strcpy(arr[next_index].key,"");
return;
}
int pred_= arr[p] < arr[next_index]?p: arr[p].pred;
int succ_= arr[pred_].succ;
init_node(arr[next_index],next_index,pred_,succ_,p);
// // after insert maximum one node will get imbalanced
recompute_height(p);
int x,y,z;
x=y=z= next_index;
while(x!=root){
if(abs(height(arr[x].left) - height(arr[x].right))<=1){
z=y;
y=x;
x= arr[x].parent;
}else break;
}
if(x!=root)
tri_node_restructure(x,y,z);
++next_index;
}
template<typename T> __host__ __device__
int Tree<T>::taller_child(int x){
return (height(arr[x].left) > height(arr[x].right)?
arr[x].left : arr[x].right);
}
template<typename T> __host__ __device__
void Tree<T>::delete_rebalance(int p){
int x,y,z;
while(p!=root){
if(abs(height(arr[p].left)-height(arr[p].right))>1){
x=p;
y= taller_child(x);
z= taller_child(y);
p= tri_node_restructure(x,y,z);
}
p=arr[p].parent;
}
}
template<typename T> __host__ __device__
void Tree<T>::delete_(T* key_){
int p;
int parent_;
int succ_;
p= search(key_);
if(strcmp_(arr[p].key,key_)==0)
return;
// node has no children
parent_ = arr[p].parent;
if(arr[p].left==INT_MIN && arr[p].right == INT_MIN){
if(arr[parent_].right == p)
arr[parent_].right= INT_MIN;
else arr[parent_].left = INT_MIN;
recompute_height(parent_);
delete_rebalance(parent_);
return;
}else if(arr[p].left==INT_MIN){ // when deleted node has only right child
if(arr[parent_].left==p)
arr[parent_].left= arr[p].right;
else arr[parent_].right = arr[p].right;
recompute_height(parent_);
delete_rebalance(parent_);
return;
}else if(arr[p].right == INT_MIN){ // when deleted node has only left child
if(arr[parent_].left==p)
arr[parent_].left= arr[p].left;
else arr[parent_].right= arr[p].left;
recompute_height(parent_);
delete_rebalance(parent_);
return;
} // when deleted node has both children
succ_ = arr[p].right;
while(arr[succ_].left!=INT_MIN)
succ_ = arr[succ_].left;
strcpy(arr[p].key,arr[succ_].key);
parent_= arr[succ_].parent;
arr[parent_].left = arr[succ_].right;
recompute_height(parent_);
delete_rebalance(parent_);
return;
}
template<typename T> __host__ __device__
bool Tree<T>::search_2(T* key_){
int p=search(key_);
Node<char> node= Node<char>(key_);
while(arr[p]> node)
p= arr[p].pred;
int x= p;
while(arr[p]< node)
p= arr[p].succ;
int y=p;
return (arr[x] == node ||arr[y] == node);
}
template<typename T>
void Tree<T>::insert_nodes(char* filename,int max){
FILE* fp= fopen(filename,"r");
char buff[200];
fgets(buff,200,fp);
int size= atoi(buff);
Tree<char>*tree= new Tree(size+max);
while(fgets(buff,200,fp)!=NULL){
buff[strlen(buff)-1]='\0';
char* temp1= strtok(buff,"$");
char* temp2= strtok(NULL,"$");
// // Node<char> *node=new Node<char>(temp1);
tree->insert(temp1);
}
fclose(fp);
*this = *tree;
} | .file "tmpxft_001857e7_00000000-6_AVL_Concurrent_Str_Lib.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7strcmp_PcS_
.type _Z7strcmp_PcS_, @function
_Z7strcmp_PcS_:
.LFB3669:
.cfi_startproc
endbr64
testq %rdi, %rdi
jne .L4
jmp .L5
.L6:
addq $1, %rdi
addq $1, %rsi
.L4:
movzbl (%rsi), %eax
cmpb %al, (%rdi)
je .L6
.L5:
movzbl (%rdi), %eax
movzbl (%rsi), %edx
subl %edx, %eax
ret
.cfi_endproc
.LFE3669:
.size _Z7strcmp_PcS_, .-_Z7strcmp_PcS_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3718:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3718:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <limits.h>
#include <string.h>
#include <sys/time.h>
#include <time.h>
#include <iostream>
using namespace std;
/*structure of the nodes of the tree*/
__host__ __device__ int strcmp_(char* str1,char* str2){
const unsigned char* ptr1= (const unsigned char*)str1;
const unsigned char* ptr2= (const unsigned char*)str2;
while(ptr1 && *ptr1 == *ptr2)
++ptr1, ++ptr2;
return *ptr1 - *ptr2;
}
template<class T>
class Node{
public:
int parent;
T key[80];
int height;
int left;
int right;
int succ,pred;
__host__ __device__ Node(T* key_){
strcpy(key,key_);
parent=height=left=right=INT_MIN;
succ=pred=INT_MIN;
}
__host__ __device__ Node(){
new(this)Node("");
}
friend ostream &operator<<(ostream &os, Node& node){
os << node.key;
return os;
}
__host__ __device__ bool operator<(Node &node){
return strcmp_(key,node.key)<0;
}
__host__ __device__ bool operator==(Node& node){
return strcmp_(key,node.key)==0;
}
__host__ __device__ bool operator>(Node &node){
return strcmp_(key,node.key)>0;
}
};
/*Definition of the tree*/
template<class T>
class Tree{
public:
int root,next_index;
int size;
/*container of the tree*/
//node at index 0 is sentinel node with key INT_MIN
// initialized root with key INT_MAX and index=1
Node<T>* arr;
__host__ __device__ Tree(int size_):root(1),next_index(2),size(size_){
arr= new Node<T>[size];
char str_[80];
for(int i=0;i<79;++i)
str_[i]=(char)127;
strcpy(arr[root].key,str_);
arr[root].parent = 0;
arr[0].right= root;
arr[root].pred= 0;
arr[0].succ= root;
arr[root].height=0;
};
__host__ __device__ Tree(){}
void inorder(int);
void preorder(int);
void postorder(int);
__host__ __device__ int search(Node<T>&);
__host__ __device__ int search(T*);
__host__ __device__ int height(int);
__host__ __device__ void insert(T*);
__host__ __device__ void delete_(T*);
__host__ __device__ void delete_rebalance(int);
__host__ __device__ void init_node(Node<T>&, int, int, int, int);
__host__ __device__ int tri_node_restructure(int, int, int);
__host__ __device__ void recompute_height(int);
__host__ __device__ int taller_child(int);
__host__ __device__ bool search_2(T*);
void insert_nodes(char*,int);
};
template<class T>
void Tree<T>::inorder(int index){
if(index==INT_MIN || strcmp_(arr[index].key,"")==0)
return;
inorder(arr[index].left);
cout<< arr[index] <<"\n";
inorder(arr[index].right);
}
template<class T>
void Tree<T>::preorder(int index){
if(index==INT_MIN || strcmp_(arr[index],"")==0)
return;
cout << arr[index] <<" ";
preorder(arr[index].left);
preorder(arr[index].right);
}
template<class T>
void Tree<T>::postorder(int index){
if(index==INT_MIN || strcmp_(arr[index].key,"")==0)
return;
postorder(arr[index].left);
postorder(arr[index].right);
cout << arr[index] <<" ";
}
template<typename T> __host__ __device__
int Tree<T>::search(Node<T> &node){
int temp=root;
while(temp!=INT_MIN){
if(arr[temp]==node)
return temp;
int child= (arr[temp]<node? arr[temp].right:
arr[temp].left);
if(child==INT_MIN)
return temp;
temp= child;
}
return temp;
}
template<typename T> __host__ __device__
int Tree<T>::search(T* key_){
int temp= root;
while(temp!=INT_MIN){
if(arr[temp].key == key_)
return temp;
int child= (arr[temp].key <key_?arr[temp].right
:arr[temp].left);
if(child==INT_MIN)
return temp;
temp=child;
}
return temp;
}
template<typename T> __host__ __device__
void Tree<T>::recompute_height(int x){
while(x!=root){
arr[x].height = max(height(arr[x].right), height(arr[x].left));
x= arr[x].parent;
}
}
template<typename T> __host__ __device__
int Tree<T>::height(int index){
if(index==INT_MIN)
return 0;
return arr[index].height+1;
}
template<typename T> __host__ __device__
int Tree<T>::tri_node_restructure(int x, int y, int z){
/*
x= parent(y)
y= parent(z)
*/
bool z_is_left_child= (arr[y].left ==z);
bool y_is_left_child = (arr[x].left== y);
int a=INT_MIN,b=INT_MIN,c=INT_MIN;
int t0=INT_MIN,t1=INT_MIN,t2=INT_MIN,t3=INT_MIN;
if(z_is_left_child && y_is_left_child){
a= z; b = y; c= x;
t0 = arr[z].left; t1= arr[z].right;
t2= arr[y].right; t3= arr[x].right;
// printf("first if: %d %d %d %d\n",t0,t1,t2,t3);
}else if(!z_is_left_child && y_is_left_child){
a= y; b=z; c= x;
t0= arr[y].left; t1= arr[z].left;
t2= arr[z].right; t3= arr[x].right;
// printf("second if: %d %d %d %d\n",t0,t1,t2,t3);
}else if(z_is_left_child && !y_is_left_child){
a=x; c= y; b=z;
t0= arr[x].left; t1= arr[z].left;
t2= arr[z].right; t3= arr[y].right;
// printf("third if: %d %d %d %d\n",t0,t1,t2,t3);
}else{
a=x; b=y; c=z;
t0= arr[x].left; t1= arr[y].left;
t2= arr[z].left; t3= arr[z].right;
// printf("fourth if:%d %d %d %d %d\n",arr[z].left,t0,t1,t2,t3);
}
// attach b to the parent of x
if(x==root){
root= b;
arr[b].parent= INT_MIN;
}else{
int parent_x= arr[x].parent;
arr[b].parent=parent_x;
if(arr[parent_x].left == x)
arr[parent_x].left = b;
else arr[parent_x].right = b;
}
/* make b
/ \
a c */
arr[b].left= a;
arr[a].parent= b;
arr[b].right = c;
arr[c].parent =b;
/*attach t0, t1, t2 and t3*/
arr[a].left = t0;
if(t0!=INT_MIN) arr[t0].parent = a;
arr[a].right = t1;
if(t1!=INT_MIN) arr[t1].parent = a;
arr[c].left= t2;
if(t2!=INT_MIN) arr[t2].parent = c;
arr[c].right = t3;
if(t3!=INT_MIN) arr[t3].parent = c;
recompute_height(a);
recompute_height(c);
return b;
}
template<typename T> __host__ __device__
void Tree<T>::init_node(Node<T>& node,int curr_ind, int pred_, int succ_, int parent_){
arr[curr_ind].parent= parent_;
arr[curr_ind].height=0;
arr[curr_ind].pred= pred_;
arr[curr_ind].succ= succ_;
arr[succ_].pred= curr_ind;
arr[pred_].succ= curr_ind;
if(arr[parent_] < node)
arr[parent_].right= curr_ind;
else arr[parent_].left= curr_ind;
}
template<typename T> __host__ __device__
void Tree<T>::insert(T* key_){
strcpy(arr[next_index].key,key_);
int p= search(arr[next_index]);
if(arr[p] == arr[next_index]){
strcpy(arr[next_index].key,"");
return;
}
int pred_= arr[p] < arr[next_index]?p: arr[p].pred;
int succ_= arr[pred_].succ;
init_node(arr[next_index],next_index,pred_,succ_,p);
// // after insert maximum one node will get imbalanced
recompute_height(p);
int x,y,z;
x=y=z= next_index;
while(x!=root){
if(abs(height(arr[x].left) - height(arr[x].right))<=1){
z=y;
y=x;
x= arr[x].parent;
}else break;
}
if(x!=root)
tri_node_restructure(x,y,z);
++next_index;
}
template<typename T> __host__ __device__
int Tree<T>::taller_child(int x){
return (height(arr[x].left) > height(arr[x].right)?
arr[x].left : arr[x].right);
}
template<typename T> __host__ __device__
void Tree<T>::delete_rebalance(int p){
int x,y,z;
while(p!=root){
if(abs(height(arr[p].left)-height(arr[p].right))>1){
x=p;
y= taller_child(x);
z= taller_child(y);
p= tri_node_restructure(x,y,z);
}
p=arr[p].parent;
}
}
template<typename T> __host__ __device__
void Tree<T>::delete_(T* key_){
int p;
int parent_;
int succ_;
p= search(key_);
if(strcmp_(arr[p].key,key_)==0)
return;
// node has no children
parent_ = arr[p].parent;
if(arr[p].left==INT_MIN && arr[p].right == INT_MIN){
if(arr[parent_].right == p)
arr[parent_].right= INT_MIN;
else arr[parent_].left = INT_MIN;
recompute_height(parent_);
delete_rebalance(parent_);
return;
}else if(arr[p].left==INT_MIN){ // when deleted node has only right child
if(arr[parent_].left==p)
arr[parent_].left= arr[p].right;
else arr[parent_].right = arr[p].right;
recompute_height(parent_);
delete_rebalance(parent_);
return;
}else if(arr[p].right == INT_MIN){ // when deleted node has only left child
if(arr[parent_].left==p)
arr[parent_].left= arr[p].left;
else arr[parent_].right= arr[p].left;
recompute_height(parent_);
delete_rebalance(parent_);
return;
} // when deleted node has both children
succ_ = arr[p].right;
while(arr[succ_].left!=INT_MIN)
succ_ = arr[succ_].left;
strcpy(arr[p].key,arr[succ_].key);
parent_= arr[succ_].parent;
arr[parent_].left = arr[succ_].right;
recompute_height(parent_);
delete_rebalance(parent_);
return;
}
template<typename T> __host__ __device__
bool Tree<T>::search_2(T* key_){
int p=search(key_);
Node<char> node= Node<char>(key_);
while(arr[p]> node)
p= arr[p].pred;
int x= p;
while(arr[p]< node)
p= arr[p].succ;
int y=p;
return (arr[x] == node ||arr[y] == node);
}
template<typename T>
void Tree<T>::insert_nodes(char* filename,int max){
FILE* fp= fopen(filename,"r");
char buff[200];
fgets(buff,200,fp);
int size= atoi(buff);
Tree<char>*tree= new Tree(size+max);
while(fgets(buff,200,fp)!=NULL){
buff[strlen(buff)-1]='\0';
char* temp1= strtok(buff,"$");
char* temp2= strtok(NULL,"$");
// // Node<char> *node=new Node<char>(temp1);
tree->insert(temp1);
}
fclose(fp);
*this = *tree;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <limits.h>
#include <string.h>
#include <sys/time.h>
#include <time.h>
#include <iostream>
using namespace std;
/*structure of the nodes of the tree*/
__host__ __device__ int strcmp_(char* str1,char* str2){
const unsigned char* ptr1= (const unsigned char*)str1;
const unsigned char* ptr2= (const unsigned char*)str2;
while(ptr1 && *ptr1 == *ptr2)
++ptr1, ++ptr2;
return *ptr1 - *ptr2;
}
template<class T>
class Node{
public:
int parent;
T key[80];
int height;
int left;
int right;
int succ,pred;
__host__ __device__ Node(T* key_){
strcpy(key,key_);
parent=height=left=right=INT_MIN;
succ=pred=INT_MIN;
}
__host__ __device__ Node(){
new(this)Node("");
}
friend ostream &operator<<(ostream &os, Node& node){
os << node.key;
return os;
}
__host__ __device__ bool operator<(Node &node){
return strcmp_(key,node.key)<0;
}
__host__ __device__ bool operator==(Node& node){
return strcmp_(key,node.key)==0;
}
__host__ __device__ bool operator>(Node &node){
return strcmp_(key,node.key)>0;
}
};
/*Definition of the tree*/
template<class T>
class Tree{
public:
int root,next_index;
int size;
/*container of the tree*/
//node at index 0 is sentinel node with key INT_MIN
// initialized root with key INT_MAX and index=1
Node<T>* arr;
__host__ __device__ Tree(int size_):root(1),next_index(2),size(size_){
arr= new Node<T>[size];
char str_[80];
for(int i=0;i<79;++i)
str_[i]=(char)127;
strcpy(arr[root].key,str_);
arr[root].parent = 0;
arr[0].right= root;
arr[root].pred= 0;
arr[0].succ= root;
arr[root].height=0;
};
__host__ __device__ Tree(){}
void inorder(int);
void preorder(int);
void postorder(int);
__host__ __device__ int search(Node<T>&);
__host__ __device__ int search(T*);
__host__ __device__ int height(int);
__host__ __device__ void insert(T*);
__host__ __device__ void delete_(T*);
__host__ __device__ void delete_rebalance(int);
__host__ __device__ void init_node(Node<T>&, int, int, int, int);
__host__ __device__ int tri_node_restructure(int, int, int);
__host__ __device__ void recompute_height(int);
__host__ __device__ int taller_child(int);
__host__ __device__ bool search_2(T*);
void insert_nodes(char*,int);
};
template<class T>
void Tree<T>::inorder(int index){
if(index==INT_MIN || strcmp_(arr[index].key,"")==0)
return;
inorder(arr[index].left);
cout<< arr[index] <<"\n";
inorder(arr[index].right);
}
template<class T>
void Tree<T>::preorder(int index){
if(index==INT_MIN || strcmp_(arr[index],"")==0)
return;
cout << arr[index] <<" ";
preorder(arr[index].left);
preorder(arr[index].right);
}
template<class T>
void Tree<T>::postorder(int index){
if(index==INT_MIN || strcmp_(arr[index].key,"")==0)
return;
postorder(arr[index].left);
postorder(arr[index].right);
cout << arr[index] <<" ";
}
template<typename T> __host__ __device__
int Tree<T>::search(Node<T> &node){
int temp=root;
while(temp!=INT_MIN){
if(arr[temp]==node)
return temp;
int child= (arr[temp]<node? arr[temp].right:
arr[temp].left);
if(child==INT_MIN)
return temp;
temp= child;
}
return temp;
}
template<typename T> __host__ __device__
int Tree<T>::search(T* key_){
int temp= root;
while(temp!=INT_MIN){
if(arr[temp].key == key_)
return temp;
int child= (arr[temp].key <key_?arr[temp].right
:arr[temp].left);
if(child==INT_MIN)
return temp;
temp=child;
}
return temp;
}
template<typename T> __host__ __device__
void Tree<T>::recompute_height(int x){
while(x!=root){
arr[x].height = max(height(arr[x].right), height(arr[x].left));
x= arr[x].parent;
}
}
template<typename T> __host__ __device__
int Tree<T>::height(int index){
if(index==INT_MIN)
return 0;
return arr[index].height+1;
}
template<typename T> __host__ __device__
int Tree<T>::tri_node_restructure(int x, int y, int z){
/*
x= parent(y)
y= parent(z)
*/
bool z_is_left_child= (arr[y].left ==z);
bool y_is_left_child = (arr[x].left== y);
int a=INT_MIN,b=INT_MIN,c=INT_MIN;
int t0=INT_MIN,t1=INT_MIN,t2=INT_MIN,t3=INT_MIN;
if(z_is_left_child && y_is_left_child){
a= z; b = y; c= x;
t0 = arr[z].left; t1= arr[z].right;
t2= arr[y].right; t3= arr[x].right;
// printf("first if: %d %d %d %d\n",t0,t1,t2,t3);
}else if(!z_is_left_child && y_is_left_child){
a= y; b=z; c= x;
t0= arr[y].left; t1= arr[z].left;
t2= arr[z].right; t3= arr[x].right;
// printf("second if: %d %d %d %d\n",t0,t1,t2,t3);
}else if(z_is_left_child && !y_is_left_child){
a=x; c= y; b=z;
t0= arr[x].left; t1= arr[z].left;
t2= arr[z].right; t3= arr[y].right;
// printf("third if: %d %d %d %d\n",t0,t1,t2,t3);
}else{
a=x; b=y; c=z;
t0= arr[x].left; t1= arr[y].left;
t2= arr[z].left; t3= arr[z].right;
// printf("fourth if:%d %d %d %d %d\n",arr[z].left,t0,t1,t2,t3);
}
// attach b to the parent of x
if(x==root){
root= b;
arr[b].parent= INT_MIN;
}else{
int parent_x= arr[x].parent;
arr[b].parent=parent_x;
if(arr[parent_x].left == x)
arr[parent_x].left = b;
else arr[parent_x].right = b;
}
/* make b
/ \
a c */
arr[b].left= a;
arr[a].parent= b;
arr[b].right = c;
arr[c].parent =b;
/*attach t0, t1, t2 and t3*/
arr[a].left = t0;
if(t0!=INT_MIN) arr[t0].parent = a;
arr[a].right = t1;
if(t1!=INT_MIN) arr[t1].parent = a;
arr[c].left= t2;
if(t2!=INT_MIN) arr[t2].parent = c;
arr[c].right = t3;
if(t3!=INT_MIN) arr[t3].parent = c;
recompute_height(a);
recompute_height(c);
return b;
}
template<typename T> __host__ __device__
void Tree<T>::init_node(Node<T>& node,int curr_ind, int pred_, int succ_, int parent_){
arr[curr_ind].parent= parent_;
arr[curr_ind].height=0;
arr[curr_ind].pred= pred_;
arr[curr_ind].succ= succ_;
arr[succ_].pred= curr_ind;
arr[pred_].succ= curr_ind;
if(arr[parent_] < node)
arr[parent_].right= curr_ind;
else arr[parent_].left= curr_ind;
}
template<typename T> __host__ __device__
void Tree<T>::insert(T* key_){
strcpy(arr[next_index].key,key_);
int p= search(arr[next_index]);
if(arr[p] == arr[next_index]){
strcpy(arr[next_index].key,"");
return;
}
int pred_= arr[p] < arr[next_index]?p: arr[p].pred;
int succ_= arr[pred_].succ;
init_node(arr[next_index],next_index,pred_,succ_,p);
// // after insert maximum one node will get imbalanced
recompute_height(p);
int x,y,z;
x=y=z= next_index;
while(x!=root){
if(abs(height(arr[x].left) - height(arr[x].right))<=1){
z=y;
y=x;
x= arr[x].parent;
}else break;
}
if(x!=root)
tri_node_restructure(x,y,z);
++next_index;
}
template<typename T> __host__ __device__
int Tree<T>::taller_child(int x){
return (height(arr[x].left) > height(arr[x].right)?
arr[x].left : arr[x].right);
}
template<typename T> __host__ __device__
void Tree<T>::delete_rebalance(int p){
int x,y,z;
while(p!=root){
if(abs(height(arr[p].left)-height(arr[p].right))>1){
x=p;
y= taller_child(x);
z= taller_child(y);
p= tri_node_restructure(x,y,z);
}
p=arr[p].parent;
}
}
template<typename T> __host__ __device__
void Tree<T>::delete_(T* key_){
int p;
int parent_;
int succ_;
p= search(key_);
if(strcmp_(arr[p].key,key_)==0)
return;
// node has no children
parent_ = arr[p].parent;
if(arr[p].left==INT_MIN && arr[p].right == INT_MIN){
if(arr[parent_].right == p)
arr[parent_].right= INT_MIN;
else arr[parent_].left = INT_MIN;
recompute_height(parent_);
delete_rebalance(parent_);
return;
}else if(arr[p].left==INT_MIN){ // when deleted node has only right child
if(arr[parent_].left==p)
arr[parent_].left= arr[p].right;
else arr[parent_].right = arr[p].right;
recompute_height(parent_);
delete_rebalance(parent_);
return;
}else if(arr[p].right == INT_MIN){ // when deleted node has only left child
if(arr[parent_].left==p)
arr[parent_].left= arr[p].left;
else arr[parent_].right= arr[p].left;
recompute_height(parent_);
delete_rebalance(parent_);
return;
} // when deleted node has both children
succ_ = arr[p].right;
while(arr[succ_].left!=INT_MIN)
succ_ = arr[succ_].left;
strcpy(arr[p].key,arr[succ_].key);
parent_= arr[succ_].parent;
arr[parent_].left = arr[succ_].right;
recompute_height(parent_);
delete_rebalance(parent_);
return;
}
template<typename T> __host__ __device__
bool Tree<T>::search_2(T* key_){
int p=search(key_);
Node<char> node= Node<char>(key_);
while(arr[p]> node)
p= arr[p].pred;
int x= p;
while(arr[p]< node)
p= arr[p].succ;
int y=p;
return (arr[x] == node ||arr[y] == node);
}
template<typename T>
void Tree<T>::insert_nodes(char* filename,int max){
FILE* fp= fopen(filename,"r");
char buff[200];
fgets(buff,200,fp);
int size= atoi(buff);
Tree<char>*tree= new Tree(size+max);
while(fgets(buff,200,fp)!=NULL){
buff[strlen(buff)-1]='\0';
char* temp1= strtok(buff,"$");
char* temp2= strtok(NULL,"$");
// // Node<char> *node=new Node<char>(temp1);
tree->insert(temp1);
}
fclose(fp);
*this = *tree;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <limits.h>
#include <string.h>
#include <sys/time.h>
#include <time.h>
#include <iostream>
using namespace std;
/*structure of the nodes of the tree*/
__host__ __device__ int strcmp_(char* str1,char* str2){
const unsigned char* ptr1= (const unsigned char*)str1;
const unsigned char* ptr2= (const unsigned char*)str2;
while(ptr1 && *ptr1 == *ptr2)
++ptr1, ++ptr2;
return *ptr1 - *ptr2;
}
template<class T>
class Node{
public:
int parent;
T key[80];
int height;
int left;
int right;
int succ,pred;
__host__ __device__ Node(T* key_){
strcpy(key,key_);
parent=height=left=right=INT_MIN;
succ=pred=INT_MIN;
}
__host__ __device__ Node(){
new(this)Node("");
}
friend ostream &operator<<(ostream &os, Node& node){
os << node.key;
return os;
}
__host__ __device__ bool operator<(Node &node){
return strcmp_(key,node.key)<0;
}
__host__ __device__ bool operator==(Node& node){
return strcmp_(key,node.key)==0;
}
__host__ __device__ bool operator>(Node &node){
return strcmp_(key,node.key)>0;
}
};
/*Definition of the tree*/
template<class T>
class Tree{
public:
int root,next_index;
int size;
/*container of the tree*/
//node at index 0 is sentinel node with key INT_MIN
// initialized root with key INT_MAX and index=1
Node<T>* arr;
__host__ __device__ Tree(int size_):root(1),next_index(2),size(size_){
arr= new Node<T>[size];
char str_[80];
for(int i=0;i<79;++i)
str_[i]=(char)127;
strcpy(arr[root].key,str_);
arr[root].parent = 0;
arr[0].right= root;
arr[root].pred= 0;
arr[0].succ= root;
arr[root].height=0;
};
__host__ __device__ Tree(){}
void inorder(int);
void preorder(int);
void postorder(int);
__host__ __device__ int search(Node<T>&);
__host__ __device__ int search(T*);
__host__ __device__ int height(int);
__host__ __device__ void insert(T*);
__host__ __device__ void delete_(T*);
__host__ __device__ void delete_rebalance(int);
__host__ __device__ void init_node(Node<T>&, int, int, int, int);
__host__ __device__ int tri_node_restructure(int, int, int);
__host__ __device__ void recompute_height(int);
__host__ __device__ int taller_child(int);
__host__ __device__ bool search_2(T*);
void insert_nodes(char*,int);
};
template<class T>
void Tree<T>::inorder(int index){
if(index==INT_MIN || strcmp_(arr[index].key,"")==0)
return;
inorder(arr[index].left);
cout<< arr[index] <<"\n";
inorder(arr[index].right);
}
template<class T>
void Tree<T>::preorder(int index){
if(index==INT_MIN || strcmp_(arr[index],"")==0)
return;
cout << arr[index] <<" ";
preorder(arr[index].left);
preorder(arr[index].right);
}
template<class T>
void Tree<T>::postorder(int index){
if(index==INT_MIN || strcmp_(arr[index].key,"")==0)
return;
postorder(arr[index].left);
postorder(arr[index].right);
cout << arr[index] <<" ";
}
template<typename T> __host__ __device__
int Tree<T>::search(Node<T> &node){
int temp=root;
while(temp!=INT_MIN){
if(arr[temp]==node)
return temp;
int child= (arr[temp]<node? arr[temp].right:
arr[temp].left);
if(child==INT_MIN)
return temp;
temp= child;
}
return temp;
}
template<typename T> __host__ __device__
int Tree<T>::search(T* key_){
int temp= root;
while(temp!=INT_MIN){
if(arr[temp].key == key_)
return temp;
int child= (arr[temp].key <key_?arr[temp].right
:arr[temp].left);
if(child==INT_MIN)
return temp;
temp=child;
}
return temp;
}
template<typename T> __host__ __device__
void Tree<T>::recompute_height(int x){
while(x!=root){
arr[x].height = max(height(arr[x].right), height(arr[x].left));
x= arr[x].parent;
}
}
template<typename T> __host__ __device__
int Tree<T>::height(int index){
if(index==INT_MIN)
return 0;
return arr[index].height+1;
}
template<typename T> __host__ __device__
int Tree<T>::tri_node_restructure(int x, int y, int z){
/*
x= parent(y)
y= parent(z)
*/
bool z_is_left_child= (arr[y].left ==z);
bool y_is_left_child = (arr[x].left== y);
int a=INT_MIN,b=INT_MIN,c=INT_MIN;
int t0=INT_MIN,t1=INT_MIN,t2=INT_MIN,t3=INT_MIN;
if(z_is_left_child && y_is_left_child){
a= z; b = y; c= x;
t0 = arr[z].left; t1= arr[z].right;
t2= arr[y].right; t3= arr[x].right;
// printf("first if: %d %d %d %d\n",t0,t1,t2,t3);
}else if(!z_is_left_child && y_is_left_child){
a= y; b=z; c= x;
t0= arr[y].left; t1= arr[z].left;
t2= arr[z].right; t3= arr[x].right;
// printf("second if: %d %d %d %d\n",t0,t1,t2,t3);
}else if(z_is_left_child && !y_is_left_child){
a=x; c= y; b=z;
t0= arr[x].left; t1= arr[z].left;
t2= arr[z].right; t3= arr[y].right;
// printf("third if: %d %d %d %d\n",t0,t1,t2,t3);
}else{
a=x; b=y; c=z;
t0= arr[x].left; t1= arr[y].left;
t2= arr[z].left; t3= arr[z].right;
// printf("fourth if:%d %d %d %d %d\n",arr[z].left,t0,t1,t2,t3);
}
// attach b to the parent of x
if(x==root){
root= b;
arr[b].parent= INT_MIN;
}else{
int parent_x= arr[x].parent;
arr[b].parent=parent_x;
if(arr[parent_x].left == x)
arr[parent_x].left = b;
else arr[parent_x].right = b;
}
/* make b
/ \
a c */
arr[b].left= a;
arr[a].parent= b;
arr[b].right = c;
arr[c].parent =b;
/*attach t0, t1, t2 and t3*/
arr[a].left = t0;
if(t0!=INT_MIN) arr[t0].parent = a;
arr[a].right = t1;
if(t1!=INT_MIN) arr[t1].parent = a;
arr[c].left= t2;
if(t2!=INT_MIN) arr[t2].parent = c;
arr[c].right = t3;
if(t3!=INT_MIN) arr[t3].parent = c;
recompute_height(a);
recompute_height(c);
return b;
}
template<typename T> __host__ __device__
void Tree<T>::init_node(Node<T>& node,int curr_ind, int pred_, int succ_, int parent_){
arr[curr_ind].parent= parent_;
arr[curr_ind].height=0;
arr[curr_ind].pred= pred_;
arr[curr_ind].succ= succ_;
arr[succ_].pred= curr_ind;
arr[pred_].succ= curr_ind;
if(arr[parent_] < node)
arr[parent_].right= curr_ind;
else arr[parent_].left= curr_ind;
}
template<typename T> __host__ __device__
void Tree<T>::insert(T* key_){
strcpy(arr[next_index].key,key_);
int p= search(arr[next_index]);
if(arr[p] == arr[next_index]){
strcpy(arr[next_index].key,"");
return;
}
int pred_= arr[p] < arr[next_index]?p: arr[p].pred;
int succ_= arr[pred_].succ;
init_node(arr[next_index],next_index,pred_,succ_,p);
// // after insert maximum one node will get imbalanced
recompute_height(p);
int x,y,z;
x=y=z= next_index;
while(x!=root){
if(abs(height(arr[x].left) - height(arr[x].right))<=1){
z=y;
y=x;
x= arr[x].parent;
}else break;
}
if(x!=root)
tri_node_restructure(x,y,z);
++next_index;
}
template<typename T> __host__ __device__
int Tree<T>::taller_child(int x){
return (height(arr[x].left) > height(arr[x].right)?
arr[x].left : arr[x].right);
}
template<typename T> __host__ __device__
void Tree<T>::delete_rebalance(int p){
int x,y,z;
while(p!=root){
if(abs(height(arr[p].left)-height(arr[p].right))>1){
x=p;
y= taller_child(x);
z= taller_child(y);
p= tri_node_restructure(x,y,z);
}
p=arr[p].parent;
}
}
template<typename T> __host__ __device__
void Tree<T>::delete_(T* key_){
int p;
int parent_;
int succ_;
p= search(key_);
if(strcmp_(arr[p].key,key_)==0)
return;
// node has no children
parent_ = arr[p].parent;
if(arr[p].left==INT_MIN && arr[p].right == INT_MIN){
if(arr[parent_].right == p)
arr[parent_].right= INT_MIN;
else arr[parent_].left = INT_MIN;
recompute_height(parent_);
delete_rebalance(parent_);
return;
}else if(arr[p].left==INT_MIN){ // when deleted node has only right child
if(arr[parent_].left==p)
arr[parent_].left= arr[p].right;
else arr[parent_].right = arr[p].right;
recompute_height(parent_);
delete_rebalance(parent_);
return;
}else if(arr[p].right == INT_MIN){ // when deleted node has only left child
if(arr[parent_].left==p)
arr[parent_].left= arr[p].left;
else arr[parent_].right= arr[p].left;
recompute_height(parent_);
delete_rebalance(parent_);
return;
} // when deleted node has both children
succ_ = arr[p].right;
while(arr[succ_].left!=INT_MIN)
succ_ = arr[succ_].left;
strcpy(arr[p].key,arr[succ_].key);
parent_= arr[succ_].parent;
arr[parent_].left = arr[succ_].right;
recompute_height(parent_);
delete_rebalance(parent_);
return;
}
template<typename T> __host__ __device__
bool Tree<T>::search_2(T* key_){
int p=search(key_);
Node<char> node= Node<char>(key_);
while(arr[p]> node)
p= arr[p].pred;
int x= p;
while(arr[p]< node)
p= arr[p].succ;
int y=p;
return (arr[x] == node ||arr[y] == node);
}
template<typename T>
void Tree<T>::insert_nodes(char* filename,int max){
FILE* fp= fopen(filename,"r");
char buff[200];
fgets(buff,200,fp);
int size= atoi(buff);
Tree<char>*tree= new Tree(size+max);
while(fgets(buff,200,fp)!=NULL){
buff[strlen(buff)-1]='\0';
char* temp1= strtok(buff,"$");
char* temp2= strtok(NULL,"$");
// // Node<char> *node=new Node<char>(temp1);
tree->insert(temp1);
}
fclose(fp);
*this = *tree;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <limits.h>
#include <string.h>
#include <sys/time.h>
#include <time.h>
#include <iostream>
using namespace std;
/*structure of the nodes of the tree*/
__host__ __device__ int strcmp_(char* str1,char* str2){
const unsigned char* ptr1= (const unsigned char*)str1;
const unsigned char* ptr2= (const unsigned char*)str2;
while(ptr1 && *ptr1 == *ptr2)
++ptr1, ++ptr2;
return *ptr1 - *ptr2;
}
template<class T>
class Node{
public:
int parent;
T key[80];
int height;
int left;
int right;
int succ,pred;
__host__ __device__ Node(T* key_){
strcpy(key,key_);
parent=height=left=right=INT_MIN;
succ=pred=INT_MIN;
}
__host__ __device__ Node(){
new(this)Node("");
}
friend ostream &operator<<(ostream &os, Node& node){
os << node.key;
return os;
}
__host__ __device__ bool operator<(Node &node){
return strcmp_(key,node.key)<0;
}
__host__ __device__ bool operator==(Node& node){
return strcmp_(key,node.key)==0;
}
__host__ __device__ bool operator>(Node &node){
return strcmp_(key,node.key)>0;
}
};
/*Definition of the tree*/
template<class T>
class Tree{
public:
int root,next_index;
int size;
/*container of the tree*/
//node at index 0 is sentinel node with key INT_MIN
// initialized root with key INT_MAX and index=1
Node<T>* arr;
__host__ __device__ Tree(int size_):root(1),next_index(2),size(size_){
arr= new Node<T>[size];
char str_[80];
for(int i=0;i<79;++i)
str_[i]=(char)127;
strcpy(arr[root].key,str_);
arr[root].parent = 0;
arr[0].right= root;
arr[root].pred= 0;
arr[0].succ= root;
arr[root].height=0;
};
__host__ __device__ Tree(){}
void inorder(int);
void preorder(int);
void postorder(int);
__host__ __device__ int search(Node<T>&);
__host__ __device__ int search(T*);
__host__ __device__ int height(int);
__host__ __device__ void insert(T*);
__host__ __device__ void delete_(T*);
__host__ __device__ void delete_rebalance(int);
__host__ __device__ void init_node(Node<T>&, int, int, int, int);
__host__ __device__ int tri_node_restructure(int, int, int);
__host__ __device__ void recompute_height(int);
__host__ __device__ int taller_child(int);
__host__ __device__ bool search_2(T*);
void insert_nodes(char*,int);
};
template<class T>
void Tree<T>::inorder(int index){
if(index==INT_MIN || strcmp_(arr[index].key,"")==0)
return;
inorder(arr[index].left);
cout<< arr[index] <<"\n";
inorder(arr[index].right);
}
template<class T>
void Tree<T>::preorder(int index){
if(index==INT_MIN || strcmp_(arr[index],"")==0)
return;
cout << arr[index] <<" ";
preorder(arr[index].left);
preorder(arr[index].right);
}
template<class T>
void Tree<T>::postorder(int index){
if(index==INT_MIN || strcmp_(arr[index].key,"")==0)
return;
postorder(arr[index].left);
postorder(arr[index].right);
cout << arr[index] <<" ";
}
template<typename T> __host__ __device__
int Tree<T>::search(Node<T> &node){
int temp=root;
while(temp!=INT_MIN){
if(arr[temp]==node)
return temp;
int child= (arr[temp]<node? arr[temp].right:
arr[temp].left);
if(child==INT_MIN)
return temp;
temp= child;
}
return temp;
}
template<typename T> __host__ __device__
int Tree<T>::search(T* key_){
int temp= root;
while(temp!=INT_MIN){
if(arr[temp].key == key_)
return temp;
int child= (arr[temp].key <key_?arr[temp].right
:arr[temp].left);
if(child==INT_MIN)
return temp;
temp=child;
}
return temp;
}
template<typename T> __host__ __device__
void Tree<T>::recompute_height(int x){
while(x!=root){
arr[x].height = max(height(arr[x].right), height(arr[x].left));
x= arr[x].parent;
}
}
template<typename T> __host__ __device__
int Tree<T>::height(int index){
if(index==INT_MIN)
return 0;
return arr[index].height+1;
}
template<typename T> __host__ __device__
int Tree<T>::tri_node_restructure(int x, int y, int z){
/*
x= parent(y)
y= parent(z)
*/
bool z_is_left_child= (arr[y].left ==z);
bool y_is_left_child = (arr[x].left== y);
int a=INT_MIN,b=INT_MIN,c=INT_MIN;
int t0=INT_MIN,t1=INT_MIN,t2=INT_MIN,t3=INT_MIN;
if(z_is_left_child && y_is_left_child){
a= z; b = y; c= x;
t0 = arr[z].left; t1= arr[z].right;
t2= arr[y].right; t3= arr[x].right;
// printf("first if: %d %d %d %d\n",t0,t1,t2,t3);
}else if(!z_is_left_child && y_is_left_child){
a= y; b=z; c= x;
t0= arr[y].left; t1= arr[z].left;
t2= arr[z].right; t3= arr[x].right;
// printf("second if: %d %d %d %d\n",t0,t1,t2,t3);
}else if(z_is_left_child && !y_is_left_child){
a=x; c= y; b=z;
t0= arr[x].left; t1= arr[z].left;
t2= arr[z].right; t3= arr[y].right;
// printf("third if: %d %d %d %d\n",t0,t1,t2,t3);
}else{
a=x; b=y; c=z;
t0= arr[x].left; t1= arr[y].left;
t2= arr[z].left; t3= arr[z].right;
// printf("fourth if:%d %d %d %d %d\n",arr[z].left,t0,t1,t2,t3);
}
// attach b to the parent of x
if(x==root){
root= b;
arr[b].parent= INT_MIN;
}else{
int parent_x= arr[x].parent;
arr[b].parent=parent_x;
if(arr[parent_x].left == x)
arr[parent_x].left = b;
else arr[parent_x].right = b;
}
/* make b
/ \
a c */
arr[b].left= a;
arr[a].parent= b;
arr[b].right = c;
arr[c].parent =b;
/*attach t0, t1, t2 and t3*/
arr[a].left = t0;
if(t0!=INT_MIN) arr[t0].parent = a;
arr[a].right = t1;
if(t1!=INT_MIN) arr[t1].parent = a;
arr[c].left= t2;
if(t2!=INT_MIN) arr[t2].parent = c;
arr[c].right = t3;
if(t3!=INT_MIN) arr[t3].parent = c;
recompute_height(a);
recompute_height(c);
return b;
}
template<typename T> __host__ __device__
void Tree<T>::init_node(Node<T>& node,int curr_ind, int pred_, int succ_, int parent_){
arr[curr_ind].parent= parent_;
arr[curr_ind].height=0;
arr[curr_ind].pred= pred_;
arr[curr_ind].succ= succ_;
arr[succ_].pred= curr_ind;
arr[pred_].succ= curr_ind;
if(arr[parent_] < node)
arr[parent_].right= curr_ind;
else arr[parent_].left= curr_ind;
}
template<typename T> __host__ __device__
void Tree<T>::insert(T* key_){
strcpy(arr[next_index].key,key_);
int p= search(arr[next_index]);
if(arr[p] == arr[next_index]){
strcpy(arr[next_index].key,"");
return;
}
int pred_= arr[p] < arr[next_index]?p: arr[p].pred;
int succ_= arr[pred_].succ;
init_node(arr[next_index],next_index,pred_,succ_,p);
// // after insert maximum one node will get imbalanced
recompute_height(p);
int x,y,z;
x=y=z= next_index;
while(x!=root){
if(abs(height(arr[x].left) - height(arr[x].right))<=1){
z=y;
y=x;
x= arr[x].parent;
}else break;
}
if(x!=root)
tri_node_restructure(x,y,z);
++next_index;
}
template<typename T> __host__ __device__
int Tree<T>::taller_child(int x){
return (height(arr[x].left) > height(arr[x].right)?
arr[x].left : arr[x].right);
}
template<typename T> __host__ __device__
void Tree<T>::delete_rebalance(int p){
int x,y,z;
while(p!=root){
if(abs(height(arr[p].left)-height(arr[p].right))>1){
x=p;
y= taller_child(x);
z= taller_child(y);
p= tri_node_restructure(x,y,z);
}
p=arr[p].parent;
}
}
template<typename T> __host__ __device__
void Tree<T>::delete_(T* key_){
int p;
int parent_;
int succ_;
p= search(key_);
if(strcmp_(arr[p].key,key_)==0)
return;
// node has no children
parent_ = arr[p].parent;
if(arr[p].left==INT_MIN && arr[p].right == INT_MIN){
if(arr[parent_].right == p)
arr[parent_].right= INT_MIN;
else arr[parent_].left = INT_MIN;
recompute_height(parent_);
delete_rebalance(parent_);
return;
}else if(arr[p].left==INT_MIN){ // when deleted node has only right child
if(arr[parent_].left==p)
arr[parent_].left= arr[p].right;
else arr[parent_].right = arr[p].right;
recompute_height(parent_);
delete_rebalance(parent_);
return;
}else if(arr[p].right == INT_MIN){ // when deleted node has only left child
if(arr[parent_].left==p)
arr[parent_].left= arr[p].left;
else arr[parent_].right= arr[p].left;
recompute_height(parent_);
delete_rebalance(parent_);
return;
} // when deleted node has both children
succ_ = arr[p].right;
while(arr[succ_].left!=INT_MIN)
succ_ = arr[succ_].left;
strcpy(arr[p].key,arr[succ_].key);
parent_= arr[succ_].parent;
arr[parent_].left = arr[succ_].right;
recompute_height(parent_);
delete_rebalance(parent_);
return;
}
template<typename T> __host__ __device__
bool Tree<T>::search_2(T* key_){
int p=search(key_);
Node<char> node= Node<char>(key_);
while(arr[p]> node)
p= arr[p].pred;
int x= p;
while(arr[p]< node)
p= arr[p].succ;
int y=p;
return (arr[x] == node ||arr[y] == node);
}
template<typename T>
void Tree<T>::insert_nodes(char* filename,int max){
FILE* fp= fopen(filename,"r");
char buff[200];
fgets(buff,200,fp);
int size= atoi(buff);
Tree<char>*tree= new Tree(size+max);
while(fgets(buff,200,fp)!=NULL){
buff[strlen(buff)-1]='\0';
char* temp1= strtok(buff,"$");
char* temp2= strtok(NULL,"$");
// // Node<char> *node=new Node<char>(temp1);
tree->insert(temp1);
}
fclose(fp);
*this = *tree;
} | .text
.file "AVL_Concurrent_Str_Lib.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z7strcmp_PcS_ # -- Begin function _Z7strcmp_PcS_
.p2align 4, 0x90
.type _Z7strcmp_PcS_,@function
_Z7strcmp_PcS_: # @_Z7strcmp_PcS_
.cfi_startproc
# %bb.0:
testq %rdi, %rdi
je .LBB0_4
# %bb.1: # %.lr.ph.preheader
movzbl (%rdi), %eax
cmpb (%rsi), %al
jne .LBB0_4
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leaq 1(%rsi), %rcx
movzbl 1(%rdi), %eax
incq %rdi
cmpb 1(%rsi), %al
movq %rcx, %rsi
je .LBB0_2
jmp .LBB0_5
.LBB0_4:
movq %rsi, %rcx
.LBB0_5: # %.critedge
movzbl (%rdi), %eax
movzbl (%rcx), %ecx
subl %ecx, %eax
retq
.Lfunc_end0:
.size _Z7strcmp_PcS_, .Lfunc_end0-_Z7strcmp_PcS_
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001857e7_00000000-6_AVL_Concurrent_Str_Lib.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7strcmp_PcS_
.type _Z7strcmp_PcS_, @function
_Z7strcmp_PcS_:
.LFB3669:
.cfi_startproc
endbr64
testq %rdi, %rdi
jne .L4
jmp .L5
.L6:
addq $1, %rdi
addq $1, %rsi
.L4:
movzbl (%rsi), %eax
cmpb %al, (%rdi)
je .L6
.L5:
movzbl (%rdi), %eax
movzbl (%rsi), %edx
subl %edx, %eax
ret
.cfi_endproc
.LFE3669:
.size _Z7strcmp_PcS_, .-_Z7strcmp_PcS_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3718:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3718:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "AVL_Concurrent_Str_Lib.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z7strcmp_PcS_ # -- Begin function _Z7strcmp_PcS_
.p2align 4, 0x90
.type _Z7strcmp_PcS_,@function
_Z7strcmp_PcS_: # @_Z7strcmp_PcS_
.cfi_startproc
# %bb.0:
testq %rdi, %rdi
je .LBB0_4
# %bb.1: # %.lr.ph.preheader
movzbl (%rdi), %eax
cmpb (%rsi), %al
jne .LBB0_4
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leaq 1(%rsi), %rcx
movzbl 1(%rdi), %eax
incq %rdi
cmpb 1(%rsi), %al
movq %rcx, %rsi
je .LBB0_2
jmp .LBB0_5
.LBB0_4:
movq %rsi, %rcx
.LBB0_5: # %.critedge
movzbl (%rdi), %eax
movzbl (%rcx), %ecx
subl %ecx, %eax
retq
.Lfunc_end0:
.size _Z7strcmp_PcS_, .Lfunc_end0-_Z7strcmp_PcS_
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*
* See cuda.h for error code descriptions.
*/
#define CHECK_CUDA_RESULT(N) { \
CUresult result = N; \
if (result != 0) { \
printf("CUDA call on line %d returned error %d\n", __LINE__, \
result); \
exit(1); \
} }
/*Thread - take in a number and square it*/
__global__ void square(float * d_in, float * d_out)
{
/*threadIdx is actually a C struct with three members
* x, y, z - we only need x right now*/
int threadId = threadIdx.x;
float data = d_in[threadId];
d_out[threadId] = data * data;
}
int main(int argc, char **argv)
{
const int ARRAY_SIZE = 64;
const int ARRAY_BYTES = 64 * sizeof(float);
/*Allocate CPU memory*/
float * h_in = (float *) malloc(ARRAY_BYTES);
float * h_out = (float *) malloc(ARRAY_BYTES);
/*Declare GPU pointers*/
float * d_in;
float * d_out;
for (int index = 0; index < ARRAY_SIZE; index++)
{
/*Fill in host array*/
h_in[index] = float(index);
}
/*Allocate memory on the GPU*/
cudaMalloc((void **) &d_in, ARRAY_BYTES);
cudaMalloc((void **) &d_out, ARRAY_BYTES);
/*Now memory is allocated and filled on CPU side, and allocated on GPU side
* Next step is to copy the input array from the CPU to the GPU*/
cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice); //Host is CPU, device is GPU
/*Launch the GPU kernel
* 1 block
* ARRAY_SIZE threads in the block*/
square<<<1, ARRAY_SIZE>>>(d_in, d_out);
/*the kernel call is blocking?
* Anyways copy from d_out to h_out*/
cudaMemcpy(h_out, d_out, ARRAY_BYTES, cudaMemcpyDeviceToHost);
/*On CPU, print results to ensure correctness*/
for (int index = 0; index < ARRAY_SIZE; index++)
{
printf("Num: %f \t Num Squared: %f\n", h_in[index], h_out[index]);
}
/*Never forget to free the memory when you are done*/
free(h_out);
free(h_in);
cudaFree(d_out);
cudaFree(d_in);
return 0;
} | code for sm_80
Function : _Z6squarePfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x001fcc00078e0205 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*0070*/ FMUL R7, R2, R2 ; /* 0x0000000202077220 */
/* 0x004fca0000400000 */
/*0080*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*
* See cuda.h for error code descriptions.
*/
#define CHECK_CUDA_RESULT(N) { \
CUresult result = N; \
if (result != 0) { \
printf("CUDA call on line %d returned error %d\n", __LINE__, \
result); \
exit(1); \
} }
/*Thread - take in a number and square it*/
__global__ void square(float * d_in, float * d_out)
{
/*threadIdx is actually a C struct with three members
* x, y, z - we only need x right now*/
int threadId = threadIdx.x;
float data = d_in[threadId];
d_out[threadId] = data * data;
}
int main(int argc, char **argv)
{
const int ARRAY_SIZE = 64;
const int ARRAY_BYTES = 64 * sizeof(float);
/*Allocate CPU memory*/
float * h_in = (float *) malloc(ARRAY_BYTES);
float * h_out = (float *) malloc(ARRAY_BYTES);
/*Declare GPU pointers*/
float * d_in;
float * d_out;
for (int index = 0; index < ARRAY_SIZE; index++)
{
/*Fill in host array*/
h_in[index] = float(index);
}
/*Allocate memory on the GPU*/
cudaMalloc((void **) &d_in, ARRAY_BYTES);
cudaMalloc((void **) &d_out, ARRAY_BYTES);
/*Now memory is allocated and filled on CPU side, and allocated on GPU side
* Next step is to copy the input array from the CPU to the GPU*/
cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice); //Host is CPU, device is GPU
/*Launch the GPU kernel
* 1 block
* ARRAY_SIZE threads in the block*/
square<<<1, ARRAY_SIZE>>>(d_in, d_out);
/*the kernel call is blocking?
* Anyways copy from d_out to h_out*/
cudaMemcpy(h_out, d_out, ARRAY_BYTES, cudaMemcpyDeviceToHost);
/*On CPU, print results to ensure correctness*/
for (int index = 0; index < ARRAY_SIZE; index++)
{
printf("Num: %f \t Num Squared: %f\n", h_in[index], h_out[index]);
}
/*Never forget to free the memory when you are done*/
free(h_out);
free(h_in);
cudaFree(d_out);
cudaFree(d_in);
return 0;
} | .file "tmpxft_0000d0e6_00000000-6_square.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6squarePfS_PfS_
.type _Z27__device_stub__Z6squarePfS_PfS_, @function
_Z27__device_stub__Z6squarePfS_PfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6squarePfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z6squarePfS_PfS_, .-_Z27__device_stub__Z6squarePfS_PfS_
.globl _Z6squarePfS_
.type _Z6squarePfS_, @function
_Z6squarePfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6squarePfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6squarePfS_, .-_Z6squarePfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Num: %f \t Num Squared: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $256, %edi
call malloc@PLT
movq %rax, %rbp
movl $256, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $64, %rax
jne .L12
movq %rsp, %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $256, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $256, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %r13
.L14:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx), %xmm0
pxor %xmm1, %xmm1
cvtss2sd (%r12,%rbx), %xmm1
movq %r13, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $256, %rbx
jne .L14
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z27__device_stub__Z6squarePfS_PfS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6squarePfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6squarePfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*
* See cuda.h for error code descriptions.
*/
#define CHECK_CUDA_RESULT(N) { \
CUresult result = N; \
if (result != 0) { \
printf("CUDA call on line %d returned error %d\n", __LINE__, \
result); \
exit(1); \
} }
/*Thread - take in a number and square it*/
__global__ void square(float * d_in, float * d_out)
{
/*threadIdx is actually a C struct with three members
* x, y, z - we only need x right now*/
int threadId = threadIdx.x;
float data = d_in[threadId];
d_out[threadId] = data * data;
}
int main(int argc, char **argv)
{
const int ARRAY_SIZE = 64;
const int ARRAY_BYTES = 64 * sizeof(float);
/*Allocate CPU memory*/
float * h_in = (float *) malloc(ARRAY_BYTES);
float * h_out = (float *) malloc(ARRAY_BYTES);
/*Declare GPU pointers*/
float * d_in;
float * d_out;
for (int index = 0; index < ARRAY_SIZE; index++)
{
/*Fill in host array*/
h_in[index] = float(index);
}
/*Allocate memory on the GPU*/
cudaMalloc((void **) &d_in, ARRAY_BYTES);
cudaMalloc((void **) &d_out, ARRAY_BYTES);
/*Now memory is allocated and filled on CPU side, and allocated on GPU side
* Next step is to copy the input array from the CPU to the GPU*/
cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice); //Host is CPU, device is GPU
/*Launch the GPU kernel
* 1 block
* ARRAY_SIZE threads in the block*/
square<<<1, ARRAY_SIZE>>>(d_in, d_out);
/*the kernel call is blocking?
* Anyways copy from d_out to h_out*/
cudaMemcpy(h_out, d_out, ARRAY_BYTES, cudaMemcpyDeviceToHost);
/*On CPU, print results to ensure correctness*/
for (int index = 0; index < ARRAY_SIZE; index++)
{
printf("Num: %f \t Num Squared: %f\n", h_in[index], h_out[index]);
}
/*Never forget to free the memory when you are done*/
free(h_out);
free(h_in);
cudaFree(d_out);
cudaFree(d_in);
return 0;
} | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*
* See cuda.h for error code descriptions.
*/
#define CHECK_CUDA_RESULT(N) { \
hipError_t result = N; \
if (result != 0) { \
printf("CUDA call on line %d returned error %d\n", __LINE__, \
result); \
exit(1); \
} }
/*Thread - take in a number and square it*/
__global__ void square(float * d_in, float * d_out)
{
/*threadIdx is actually a C struct with three members
* x, y, z - we only need x right now*/
int threadId = threadIdx.x;
float data = d_in[threadId];
d_out[threadId] = data * data;
}
int main(int argc, char **argv)
{
const int ARRAY_SIZE = 64;
const int ARRAY_BYTES = 64 * sizeof(float);
/*Allocate CPU memory*/
float * h_in = (float *) malloc(ARRAY_BYTES);
float * h_out = (float *) malloc(ARRAY_BYTES);
/*Declare GPU pointers*/
float * d_in;
float * d_out;
for (int index = 0; index < ARRAY_SIZE; index++)
{
/*Fill in host array*/
h_in[index] = float(index);
}
/*Allocate memory on the GPU*/
hipMalloc((void **) &d_in, ARRAY_BYTES);
hipMalloc((void **) &d_out, ARRAY_BYTES);
/*Now memory is allocated and filled on CPU side, and allocated on GPU side
* Next step is to copy the input array from the CPU to the GPU*/
hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice); //Host is CPU, device is GPU
/*Launch the GPU kernel
* 1 block
* ARRAY_SIZE threads in the block*/
square<<<1, ARRAY_SIZE>>>(d_in, d_out);
/*the kernel call is blocking?
* Anyways copy from d_out to h_out*/
hipMemcpy(h_out, d_out, ARRAY_BYTES, hipMemcpyDeviceToHost);
/*On CPU, print results to ensure correctness*/
for (int index = 0; index < ARRAY_SIZE; index++)
{
printf("Num: %f \t Num Squared: %f\n", h_in[index], h_out[index]);
}
/*Never forget to free the memory when you are done*/
free(h_out);
free(h_in);
hipFree(d_out);
hipFree(d_in);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*
* See cuda.h for error code descriptions.
*/
#define CHECK_CUDA_RESULT(N) { \
hipError_t result = N; \
if (result != 0) { \
printf("CUDA call on line %d returned error %d\n", __LINE__, \
result); \
exit(1); \
} }
/*Thread - take in a number and square it*/
__global__ void square(float * d_in, float * d_out)
{
/*threadIdx is actually a C struct with three members
* x, y, z - we only need x right now*/
int threadId = threadIdx.x;
float data = d_in[threadId];
d_out[threadId] = data * data;
}
int main(int argc, char **argv)
{
const int ARRAY_SIZE = 64;
const int ARRAY_BYTES = 64 * sizeof(float);
/*Allocate CPU memory*/
float * h_in = (float *) malloc(ARRAY_BYTES);
float * h_out = (float *) malloc(ARRAY_BYTES);
/*Declare GPU pointers*/
float * d_in;
float * d_out;
for (int index = 0; index < ARRAY_SIZE; index++)
{
/*Fill in host array*/
h_in[index] = float(index);
}
/*Allocate memory on the GPU*/
hipMalloc((void **) &d_in, ARRAY_BYTES);
hipMalloc((void **) &d_out, ARRAY_BYTES);
/*Now memory is allocated and filled on CPU side, and allocated on GPU side
* Next step is to copy the input array from the CPU to the GPU*/
hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice); //Host is CPU, device is GPU
/*Launch the GPU kernel
* 1 block
* ARRAY_SIZE threads in the block*/
square<<<1, ARRAY_SIZE>>>(d_in, d_out);
/*the kernel call is blocking?
* Anyways copy from d_out to h_out*/
hipMemcpy(h_out, d_out, ARRAY_BYTES, hipMemcpyDeviceToHost);
/*On CPU, print results to ensure correctness*/
for (int index = 0; index < ARRAY_SIZE; index++)
{
printf("Num: %f \t Num Squared: %f\n", h_in[index], h_out[index]);
}
/*Never forget to free the memory when you are done*/
free(h_out);
free(h_in);
hipFree(d_out);
hipFree(d_in);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6squarePfS_
.globl _Z6squarePfS_
.p2align 8
.type _Z6squarePfS_,@function
_Z6squarePfS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v1, v1, v1
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6squarePfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6squarePfS_, .Lfunc_end0-_Z6squarePfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6squarePfS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z6squarePfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*
* See cuda.h for error code descriptions.
*/
#define CHECK_CUDA_RESULT(N) { \
hipError_t result = N; \
if (result != 0) { \
printf("CUDA call on line %d returned error %d\n", __LINE__, \
result); \
exit(1); \
} }
/*Thread - take in a number and square it*/
__global__ void square(float * d_in, float * d_out)
{
/*threadIdx is actually a C struct with three members
* x, y, z - we only need x right now*/
int threadId = threadIdx.x;
float data = d_in[threadId];
d_out[threadId] = data * data;
}
int main(int argc, char **argv)
{
const int ARRAY_SIZE = 64;
const int ARRAY_BYTES = 64 * sizeof(float);
/*Allocate CPU memory*/
float * h_in = (float *) malloc(ARRAY_BYTES);
float * h_out = (float *) malloc(ARRAY_BYTES);
/*Declare GPU pointers*/
float * d_in;
float * d_out;
for (int index = 0; index < ARRAY_SIZE; index++)
{
/*Fill in host array*/
h_in[index] = float(index);
}
/*Allocate memory on the GPU*/
hipMalloc((void **) &d_in, ARRAY_BYTES);
hipMalloc((void **) &d_out, ARRAY_BYTES);
/*Now memory is allocated and filled on CPU side, and allocated on GPU side
* Next step is to copy the input array from the CPU to the GPU*/
hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice); //Host is CPU, device is GPU
/*Launch the GPU kernel
* 1 block
* ARRAY_SIZE threads in the block*/
square<<<1, ARRAY_SIZE>>>(d_in, d_out);
/*the kernel call is blocking?
* Anyways copy from d_out to h_out*/
hipMemcpy(h_out, d_out, ARRAY_BYTES, hipMemcpyDeviceToHost);
/*On CPU, print results to ensure correctness*/
for (int index = 0; index < ARRAY_SIZE; index++)
{
printf("Num: %f \t Num Squared: %f\n", h_in[index], h_out[index]);
}
/*Never forget to free the memory when you are done*/
free(h_out);
free(h_in);
hipFree(d_out);
hipFree(d_in);
return 0;
} | .text
.file "square.hip"
.globl _Z21__device_stub__squarePfS_ # -- Begin function _Z21__device_stub__squarePfS_
.p2align 4, 0x90
.type _Z21__device_stub__squarePfS_,@function
_Z21__device_stub__squarePfS_: # @_Z21__device_stub__squarePfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6squarePfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__squarePfS_, .Lfunc_end0-_Z21__device_stub__squarePfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %rbx
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $64, %rax
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq %rsp, %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq 8(%rsp), %rdi
movl $256, %edx # imm = 0x100
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 63(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6squarePfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
movl $256, %edx # imm = 0x100
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%r14,%r15,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
movb $2, %al
callq printf
incq %r15
cmpq $64, %r15
jne .LBB1_5
# %bb.6:
movq %r14, %rdi
callq free
movq %rbx, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6squarePfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6squarePfS_,@object # @_Z6squarePfS_
.section .rodata,"a",@progbits
.globl _Z6squarePfS_
.p2align 3, 0x0
_Z6squarePfS_:
.quad _Z21__device_stub__squarePfS_
.size _Z6squarePfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Num: %f \t Num Squared: %f\n"
.size .L.str, 27
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6squarePfS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__squarePfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6squarePfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6squarePfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x001fcc00078e0205 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*0070*/ FMUL R7, R2, R2 ; /* 0x0000000202077220 */
/* 0x004fca0000400000 */
/*0080*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6squarePfS_
.globl _Z6squarePfS_
.p2align 8
.type _Z6squarePfS_,@function
_Z6squarePfS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v1, v1, v1
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6squarePfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6squarePfS_, .Lfunc_end0-_Z6squarePfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6squarePfS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z6squarePfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000d0e6_00000000-6_square.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6squarePfS_PfS_
.type _Z27__device_stub__Z6squarePfS_PfS_, @function
_Z27__device_stub__Z6squarePfS_PfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6squarePfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z6squarePfS_PfS_, .-_Z27__device_stub__Z6squarePfS_PfS_
.globl _Z6squarePfS_
.type _Z6squarePfS_, @function
_Z6squarePfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6squarePfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6squarePfS_, .-_Z6squarePfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Num: %f \t Num Squared: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $256, %edi
call malloc@PLT
movq %rax, %rbp
movl $256, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $64, %rax
jne .L12
movq %rsp, %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $256, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $256, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %r13
.L14:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx), %xmm0
pxor %xmm1, %xmm1
cvtss2sd (%r12,%rbx), %xmm1
movq %r13, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $256, %rbx
jne .L14
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z27__device_stub__Z6squarePfS_PfS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6squarePfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6squarePfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "square.hip"
.globl _Z21__device_stub__squarePfS_ # -- Begin function _Z21__device_stub__squarePfS_
.p2align 4, 0x90
.type _Z21__device_stub__squarePfS_,@function
_Z21__device_stub__squarePfS_: # @_Z21__device_stub__squarePfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6squarePfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__squarePfS_, .Lfunc_end0-_Z21__device_stub__squarePfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %rbx
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $64, %rax
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq %rsp, %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq 8(%rsp), %rdi
movl $256, %edx # imm = 0x100
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 63(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6squarePfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
movl $256, %edx # imm = 0x100
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%r14,%r15,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
movb $2, %al
callq printf
incq %r15
cmpq $64, %r15
jne .LBB1_5
# %bb.6:
movq %r14, %rdi
callq free
movq %rbx, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6squarePfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6squarePfS_,@object # @_Z6squarePfS_
.section .rodata,"a",@progbits
.globl _Z6squarePfS_
.p2align 3, 0x0
_Z6squarePfS_:
.quad _Z21__device_stub__squarePfS_
.size _Z6squarePfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Num: %f \t Num Squared: %f\n"
.size .L.str, 27
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6squarePfS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__squarePfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6squarePfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //pass
//--blockDim=[128,128] --gridDim=[4,4]
#include <cuda.h>
//////////////////////////////////////////////////////////////////////////////
//// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
//// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
//// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
//// PARTICULAR PURPOSE.
////
//// Copyright (c) Microsoft Corporation. All rights reserved
//////////////////////////////////////////////////////////////////////////////
//----------------------------------------------------------------------------
// File: Convolution.cpp
//
// Implement C++ AMP based simple and tiled version of Convolution filter used in
// image processing.
//----------------------------------------------------------------------------
#define DEFAULT_WIDTH 512
#define DEFAULT_HEIGHT 512
// TILE_SIZE should be multiple of both DEFAULT_WIDTH and DEFAULT_HEIGHT
#define TILE_SIZE 128
#define radius 7
#define width DEFAULT_WIDTH
#define height DEFAULT_HEIGHT
#define clamp(a, b, c) ((a) < (b) ? (b) : ((a) > (c) ? (c) : (a)))
//----------------------------------------------------------------------------
// Simple implementation of convolution filter along different dimension
//----------------------------------------------------------------------------
static __attribute__((always_inline)) __device__ float convolution_dim_simple(const float* img, const float* filter)
{
float sum = 0.0f;
for (int k = -radius; k <= radius; k++)
{
int dim = clamp((blockDim.y*blockIdx.y + threadIdx.y) + k, 0, height-1);
int aIdxX = (blockDim.x*blockIdx.x + threadIdx.x);
int aIdxY = dim;
int kidx = k + radius;
sum += img[aIdxY*width + aIdxX]*filter[kidx];
}
return sum;
}
//----------------------------------------------------------------------------
// Simple implementation of convolution separable filter
//----------------------------------------------------------------------------
__global__ void convolution_simple(float* v_img, float* v_filter, float* v_result)
{
v_result[(blockDim.y*blockIdx.y + threadIdx.y)*width + (blockDim.x*blockIdx.x + threadIdx.x)] = convolution_dim_simple(v_img, v_filter);
#ifdef MUTATION
v_result[(blockDim.y*blockIdx.y + threadIdx.y)*width + (blockDim.x*blockIdx.x + threadIdx.x) + 1] = v_result[(blockDim.y*blockIdx.y + threadIdx.y)*width + (blockDim.x*blockIdx.x + threadIdx.x) + 1];
/* BUGINJECT: ADD_ACCESS, UP */
#endif
} | code for sm_80
Function : _Z18convolution_simplePfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R15, SR_CTAID.Y ; /* 0x00000000000f7919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0040*/ S2R R12, SR_CTAID.X ; /* 0x00000000000c7919 */
/* 0x000e680000002500 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R15, R15, c[0x0][0x4], R0 ; /* 0x000001000f0f7a24 */
/* 0x001fca00078e0200 */
/*0070*/ IADD3 R0, R15.reuse, -0x7, RZ ; /* 0xfffffff90f007810 */
/* 0x040fe40007ffe0ff */
/*0080*/ IADD3 R2, R15, -0x6, RZ ; /* 0xfffffffa0f027810 */
/* 0x000fe20007ffe0ff */
/*0090*/ IMAD R12, R12, c[0x0][0x0], R3 ; /* 0x000000000c0c7a24 */
/* 0x002fe200078e0203 */
/*00a0*/ IMNMX.U32 R3, R0, 0x1ff, PT ; /* 0x000001ff00037817 */
/* 0x000fe20003800000 */
/*00b0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*00c0*/ IMNMX.U32 R7, R2, 0x1ff, PT ; /* 0x000001ff02077817 */
/* 0x000fe40003800000 */
/*00d0*/ LEA R3, R3, R12, 0x9 ; /* 0x0000000c03037211 */
/* 0x000fe400078e48ff */
/*00e0*/ IADD3 R6, R15, -0x5, RZ ; /* 0xfffffffb0f067810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD R7, R7, 0x200, R12 ; /* 0x0000020007077824 */
/* 0x000fe200078e020c */
/*0100*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD.WIDE R4, R3, R0, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fe200078e0200 */
/*0120*/ IMNMX.U32 R9, R6, 0x1ff, PT ; /* 0x000001ff06097817 */
/* 0x000fc40003800000 */
/*0130*/ IADD3 R6, R15, -0x4, RZ ; /* 0xfffffffc0f067810 */
/* 0x000fe20007ffe0ff */
/*0140*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe200078e00ff */
/*0150*/ LEA R23, R9, R12, 0x9 ; /* 0x0000000c09177211 */
/* 0x000fe200078e48ff */
/*0160*/ IMAD.WIDE R16, R7, R0, c[0x0][0x160] ; /* 0x0000580007107625 */
/* 0x000fe200078e0200 */
/*0170*/ IMNMX.U32 R7, R6, 0x1ff, PT ; /* 0x000001ff06077817 */
/* 0x000fe20003800000 */
/*0180*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x0000a2000c1e1900 */
/*0190*/ IADD3 R10, R15, -0x3, RZ ; /* 0xfffffffd0f0a7810 */
/* 0x000fc60007ffe0ff */
/*01a0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ IMAD.WIDE R22, R23, R0, c[0x0][0x160] ; /* 0x0000580017167625 */
/* 0x000fe200078e0200 */
/*01c0*/ IMNMX.U32 R11, R10, 0x1ff, PT ; /* 0x000001ff0a0b7817 */
/* 0x000fe40003800000 */
/*01d0*/ LDG.E R6, [R16.64] ; /* 0x0000000410067981 */
/* 0x0002e2000c1e1900 */
/*01e0*/ IMAD R25, R7, 0x200, R12 ; /* 0x0000020007197824 */
/* 0x000fc600078e020c */
/*01f0*/ LDG.E R7, [R2.64+0x4] ; /* 0x0000040402077981 */
/* 0x000ee2000c1e1900 */
/*0200*/ LEA R11, R11, R12, 0x9 ; /* 0x0000000c0b0b7211 */
/* 0x000fe200078e48ff */
/*0210*/ IMAD.WIDE R24, R25, R0.reuse, c[0x0][0x160] ; /* 0x0000580019187625 */
/* 0x080fe400078e0200 */
/*0220*/ LDG.E R18, [R22.64] ; /* 0x0000000416127981 */
/* 0x000968000c1e1900 */
/*0230*/ LDG.E R19, [R2.64+0x8] ; /* 0x0000080402137981 */
/* 0x000f62000c1e1900 */
/*0240*/ IMAD.WIDE R26, R11, R0, c[0x0][0x160] ; /* 0x000058000b1a7625 */
/* 0x000fc600078e0200 */
/*0250*/ LDG.E R11, [R24.64] ; /* 0x00000004180b7981 */
/* 0x000168000c1e1900 */
/*0260*/ LDG.E R20, [R2.64+0xc] ; /* 0x00000c0402147981 */
/* 0x000f68000c1e1900 */
/*0270*/ LDG.E R21, [R26.64] ; /* 0x000000041a157981 */
/* 0x000368000c1e1900 */
/*0280*/ LDG.E R10, [R2.64+0x10] ; /* 0x00001004020a7981 */
/* 0x000f62000c1e1900 */
/*0290*/ IADD3 R4, R15, -0x2, RZ ; /* 0xfffffffe0f047810 */
/* 0x001fc40007ffe0ff */
/*02a0*/ IMNMX.U32 R13, R15, 0x1ff, PT ; /* 0x000001ff0f0d7817 */
/* 0x000fe20003800000 */
/*02b0*/ LDG.E R28, [R2.64+0x38] ; /* 0x00003804021c7981 */
/* 0x000162000c1e1900 */
/*02c0*/ IMNMX.U32 R5, R4, 0x1ff, PT ; /* 0x000001ff04057817 */
/* 0x000fc60003800000 */
/*02d0*/ IMAD R13, R13, 0x200, R12 ; /* 0x000002000d0d7824 */
/* 0x000fe200078e020c */
/*02e0*/ LEA R5, R5, R12, 0x9 ; /* 0x0000000c05057211 */
/* 0x000fe200078e48ff */
/*02f0*/ LDG.E R26, [R2.64+0x30] ; /* 0x00003004021a7981 */
/* 0x002164000c1e1900 */
/*0300*/ IMAD.WIDE R16, R13, R0, c[0x0][0x160] ; /* 0x000058000d107625 */
/* 0x000fe200078e0200 */
/*0310*/ IADD3 R13, R15, -0x1, RZ ; /* 0xffffffff0f0d7810 */
/* 0x000fc60007ffe0ff */
/*0320*/ IMAD.WIDE R4, R5, R0.reuse, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x080fe200078e0200 */
/*0330*/ IMNMX.U32 R13, R13, 0x1ff, PT ; /* 0x000001ff0d0d7817 */
/* 0x000fe20003800000 */
/*0340*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000362000c1e1900 */
/*0350*/ IADD3 R22, R15.reuse, 0x1, RZ ; /* 0x000000010f167810 */
/* 0x050fe40007ffe0ff */
/*0360*/ IADD3 R24, R15.reuse, 0x2, RZ ; /* 0x000000020f187810 */
/* 0x040fe20007ffe0ff */
/*0370*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000962000c1e1900 */
/*0380*/ IADD3 R25, R15, 0x3, RZ ; /* 0x000000030f197810 */
/* 0x000fe20007ffe0ff */
/*0390*/ IMAD R13, R13, 0x200, R12 ; /* 0x000002000d0d7824 */
/* 0x000fe200078e020c */
/*03a0*/ IMNMX.U32 R23, R22, 0x1ff, PT ; /* 0x000001ff16177817 */
/* 0x000fe40003800000 */
/*03b0*/ IMNMX.U32 R27, R24, 0x1ff, PT ; /* 0x000001ff181b7817 */
/* 0x000fe20003800000 */
/*03c0*/ LDG.E R17, [R2.64+0x14] ; /* 0x0000140402117981 */
/* 0x002f62000c1e1900 */
/*03d0*/ IMNMX.U32 R29, R25, 0x1ff, PT ; /* 0x000001ff191d7817 */
/* 0x000fe20003800000 */
/*03e0*/ IMAD.WIDE R24, R13, R0, c[0x0][0x160] ; /* 0x000058000d187625 */
/* 0x000fe200078e0200 */
/*03f0*/ LEA R27, R27, R12, 0x9 ; /* 0x0000000c1b1b7211 */
/* 0x000fc600078e48ff */
/*0400*/ IMAD R5, R29, 0x200, R12 ; /* 0x000002001d057824 */
/* 0x010fe200078e020c */
/*0410*/ LDG.E R13, [R24.64] ; /* 0x00000004180d7981 */
/* 0x000328000c1e1900 */
/*0420*/ LDG.E R29, [R2.64+0x2c] ; /* 0x00002c04021d7981 */
/* 0x000128000c1e1900 */
/*0430*/ LDG.E R25, [R2.64+0x20] ; /* 0x0000200402197981 */
/* 0x002128000c1e1900 */
/*0440*/ LDG.E R24, [R2.64+0x24] ; /* 0x0000240402187981 */
/* 0x000122000c1e1900 */
/*0450*/ FFMA R8, R8, R9, RZ ; /* 0x0000000908087223 */
/* 0x004fe200000000ff */
/*0460*/ LEA R9, R23, R12, 0x9 ; /* 0x0000000c17097211 */
/* 0x000fc600078e48ff */
/*0470*/ FFMA R4, R6, R7, R8 ; /* 0x0000000706047223 */
/* 0x008fe20000000008 */
/*0480*/ IADD3 R23, R15, 0x4, RZ ; /* 0x000000040f177810 */
/* 0x000fe20007ffe0ff */
/*0490*/ IMAD.WIDE R8, R9, R0, c[0x0][0x160] ; /* 0x0000580009087625 */
/* 0x000fc800078e0200 */
/*04a0*/ FFMA R22, R18, R19, R4 ; /* 0x0000001312167223 */
/* 0x020fe40000000004 */
/*04b0*/ IMAD.WIDE R6, R27, R0, c[0x0][0x160] ; /* 0x000058001b067625 */
/* 0x000fe200078e0200 */
/*04c0*/ IMNMX.U32 R23, R23, 0x1ff, PT ; /* 0x000001ff17177817 */
/* 0x000fe20003800000 */
/*04d0*/ LDG.E R27, [R2.64+0x1c] ; /* 0x00001c04021b7981 */
/* 0x0000a4000c1e1900 */
/*04e0*/ FFMA R11, R11, R20, R22 ; /* 0x000000140b0b7223 */
/* 0x000fe40000000016 */
/*04f0*/ LDG.E R18, [R8.64] ; /* 0x0000000408127981 */
/* 0x0002e8000c1e1900 */
/*0500*/ LDG.E R22, [R2.64+0x18] ; /* 0x0000180402167981 */
/* 0x000122000c1e1900 */
/*0510*/ FFMA R21, R21, R10, R11 ; /* 0x0000000a15157223 */
/* 0x000fe2000000000b */
/*0520*/ IADD3 R10, R15, 0x5, RZ ; /* 0x000000050f0a7810 */
/* 0x000fe20007ffe0ff */
/*0530*/ IMAD.WIDE R4, R5, R0, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe200078e0200 */
/*0540*/ IADD3 R8, R15, 0x6, RZ ; /* 0x000000060f087810 */
/* 0x002fe20007ffe0ff */
/*0550*/ LDG.E R19, [R6.64] ; /* 0x0000000406137981 */
/* 0x000362000c1e1900 */
/*0560*/ IMNMX.U32 R9, R10, 0x1ff, PT ; /* 0x000001ff0a097817 */
/* 0x000fc40003800000 */
/*0570*/ IMNMX.U32 R11, R8, 0x1ff, PT ; /* 0x000001ff080b7817 */
/* 0x000fe20003800000 */
/*0580*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000162000c1e1900 */
/*0590*/ LEA R7, R23, R12, 0x9 ; /* 0x0000000c17077211 */
/* 0x002fc600078e48ff */
/*05a0*/ LDG.E R23, [R2.64+0x28] ; /* 0x0000280402177981 */
/* 0x000362000c1e1900 */
/*05b0*/ IADD3 R4, R15, 0x7, RZ ; /* 0x000000070f047810 */
/* 0x001fe20007ffe0ff */
/*05c0*/ IMAD.WIDE R6, R7, R0, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fe200078e0200 */
/*05d0*/ LEA R5, R9, R12, 0x9 ; /* 0x0000000c09057211 */
/* 0x000fc600078e48ff */
/*05e0*/ IMAD R9, R11, 0x200, R12 ; /* 0x000002000b097824 */
/* 0x000fe200078e020c */
/*05f0*/ IMNMX.U32 R11, R4, 0x1ff, PT ; /* 0x000001ff040b7817 */
/* 0x000fe20003800000 */
/*0600*/ IMAD.WIDE R4, R5, R0, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe200078e0200 */
/*0610*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f64000c1e1900 */
/*0620*/ LEA R11, R11, R12, 0x9 ; /* 0x0000000c0b0b7211 */
/* 0x000fe200078e48ff */
/*0630*/ IMAD.WIDE R8, R9, R0.reuse, c[0x0][0x160] ; /* 0x0000580009087625 */
/* 0x080fe400078e0200 */
/*0640*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000164000c1e1900 */
/*0650*/ IMAD.WIDE R10, R11, R0, c[0x0][0x160] ; /* 0x000058000b0a7625 */
/* 0x000fc400078e0200 */
/*0660*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f68000c1e1900 */
/*0670*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000f68000c1e1900 */
/*0680*/ LDG.E R5, [R2.64+0x34] ; /* 0x0000340402057981 */
/* 0x001362000c1e1900 */
/*0690*/ FFMA R14, R14, R17, R21 ; /* 0x000000110e0e7223 */
/* 0x000fe20000000015 */
/*06a0*/ LEA R15, R15, R12, 0x9 ; /* 0x0000000c0f0f7211 */
/* 0x000fca00078e48ff */
/*06b0*/ IMAD.WIDE.U32 R2, R15, R0, c[0x0][0x170] ; /* 0x00005c000f027625 */
/* 0x002fc800078e0000 */
/*06c0*/ FFMA R13, R13, R22, R14 ; /* 0x000000160d0d7223 */
/* 0x010fc8000000000e */
/*06d0*/ FFMA R13, R16, R27, R13 ; /* 0x0000001b100d7223 */
/* 0x004fc8000000000d */
/*06e0*/ FFMA R13, R18, R25, R13 ; /* 0x00000019120d7223 */
/* 0x008fc8000000000d */
/*06f0*/ FFMA R13, R19, R24, R13 ; /* 0x00000018130d7223 */
/* 0x020fc8000000000d */
/*0700*/ FFMA R13, R20, R23, R13 ; /* 0x00000017140d7223 */
/* 0x000fc8000000000d */
/*0710*/ FFMA R13, R6, R29, R13 ; /* 0x0000001d060d7223 */
/* 0x000fc8000000000d */
/*0720*/ FFMA R4, R4, R26, R13 ; /* 0x0000001a04047223 */
/* 0x000fc8000000000d */
/*0730*/ FFMA R4, R8, R5, R4 ; /* 0x0000000508047223 */
/* 0x000fc80000000004 */
/*0740*/ FFMA R11, R11, R28, R4 ; /* 0x0000001c0b0b7223 */
/* 0x000fca0000000004 */
/*0750*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c101904 */
/*0760*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0770*/ BRA 0x770; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //pass
//--blockDim=[128,128] --gridDim=[4,4]
#include <cuda.h>
//////////////////////////////////////////////////////////////////////////////
//// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
//// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
//// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
//// PARTICULAR PURPOSE.
////
//// Copyright (c) Microsoft Corporation. All rights reserved
//////////////////////////////////////////////////////////////////////////////
//----------------------------------------------------------------------------
// File: Convolution.cpp
//
// Implement C++ AMP based simple and tiled version of Convolution filter used in
// image processing.
//----------------------------------------------------------------------------
#define DEFAULT_WIDTH 512
#define DEFAULT_HEIGHT 512
// TILE_SIZE should be multiple of both DEFAULT_WIDTH and DEFAULT_HEIGHT
#define TILE_SIZE 128
#define radius 7
#define width DEFAULT_WIDTH
#define height DEFAULT_HEIGHT
#define clamp(a, b, c) ((a) < (b) ? (b) : ((a) > (c) ? (c) : (a)))
//----------------------------------------------------------------------------
// Simple implementation of convolution filter along different dimension
//----------------------------------------------------------------------------
static __attribute__((always_inline)) __device__ float convolution_dim_simple(const float* img, const float* filter)
{
float sum = 0.0f;
for (int k = -radius; k <= radius; k++)
{
int dim = clamp((blockDim.y*blockIdx.y + threadIdx.y) + k, 0, height-1);
int aIdxX = (blockDim.x*blockIdx.x + threadIdx.x);
int aIdxY = dim;
int kidx = k + radius;
sum += img[aIdxY*width + aIdxX]*filter[kidx];
}
return sum;
}
//----------------------------------------------------------------------------
// Simple implementation of convolution separable filter
//----------------------------------------------------------------------------
__global__ void convolution_simple(float* v_img, float* v_filter, float* v_result)
{
v_result[(blockDim.y*blockIdx.y + threadIdx.y)*width + (blockDim.x*blockIdx.x + threadIdx.x)] = convolution_dim_simple(v_img, v_filter);
#ifdef MUTATION
v_result[(blockDim.y*blockIdx.y + threadIdx.y)*width + (blockDim.x*blockIdx.x + threadIdx.x) + 1] = v_result[(blockDim.y*blockIdx.y + threadIdx.y)*width + (blockDim.x*blockIdx.x + threadIdx.x) + 1];
/* BUGINJECT: ADD_ACCESS, UP */
#endif
} | .file "tmpxft_0006a483_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z18convolution_simplePfS_S_PfS_S_
.type _Z42__device_stub__Z18convolution_simplePfS_S_PfS_S_, @function
_Z42__device_stub__Z18convolution_simplePfS_S_PfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18convolution_simplePfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z42__device_stub__Z18convolution_simplePfS_S_PfS_S_, .-_Z42__device_stub__Z18convolution_simplePfS_S_PfS_S_
.globl _Z18convolution_simplePfS_S_
.type _Z18convolution_simplePfS_S_, @function
_Z18convolution_simplePfS_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18convolution_simplePfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z18convolution_simplePfS_S_, .-_Z18convolution_simplePfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18convolution_simplePfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18convolution_simplePfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //pass
//--blockDim=[128,128] --gridDim=[4,4]
#include <cuda.h>
//////////////////////////////////////////////////////////////////////////////
//// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
//// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
//// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
//// PARTICULAR PURPOSE.
////
//// Copyright (c) Microsoft Corporation. All rights reserved
//////////////////////////////////////////////////////////////////////////////
//----------------------------------------------------------------------------
// File: Convolution.cpp
//
// Implement C++ AMP based simple and tiled version of Convolution filter used in
// image processing.
//----------------------------------------------------------------------------
#define DEFAULT_WIDTH 512
#define DEFAULT_HEIGHT 512
// TILE_SIZE should be multiple of both DEFAULT_WIDTH and DEFAULT_HEIGHT
#define TILE_SIZE 128
#define radius 7
#define width DEFAULT_WIDTH
#define height DEFAULT_HEIGHT
#define clamp(a, b, c) ((a) < (b) ? (b) : ((a) > (c) ? (c) : (a)))
//----------------------------------------------------------------------------
// Simple implementation of convolution filter along different dimension
//----------------------------------------------------------------------------
static __attribute__((always_inline)) __device__ float convolution_dim_simple(const float* img, const float* filter)
{
float sum = 0.0f;
for (int k = -radius; k <= radius; k++)
{
int dim = clamp((blockDim.y*blockIdx.y + threadIdx.y) + k, 0, height-1);
int aIdxX = (blockDim.x*blockIdx.x + threadIdx.x);
int aIdxY = dim;
int kidx = k + radius;
sum += img[aIdxY*width + aIdxX]*filter[kidx];
}
return sum;
}
//----------------------------------------------------------------------------
// Simple implementation of convolution separable filter
//----------------------------------------------------------------------------
__global__ void convolution_simple(float* v_img, float* v_filter, float* v_result)
{
v_result[(blockDim.y*blockIdx.y + threadIdx.y)*width + (blockDim.x*blockIdx.x + threadIdx.x)] = convolution_dim_simple(v_img, v_filter);
#ifdef MUTATION
v_result[(blockDim.y*blockIdx.y + threadIdx.y)*width + (blockDim.x*blockIdx.x + threadIdx.x) + 1] = v_result[(blockDim.y*blockIdx.y + threadIdx.y)*width + (blockDim.x*blockIdx.x + threadIdx.x) + 1];
/* BUGINJECT: ADD_ACCESS, UP */
#endif
} | //pass
//--blockDim=[128,128] --gridDim=[4,4]
#include <hip/hip_runtime.h>
//////////////////////////////////////////////////////////////////////////////
//// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
//// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
//// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
//// PARTICULAR PURPOSE.
////
//// Copyright (c) Microsoft Corporation. All rights reserved
//////////////////////////////////////////////////////////////////////////////
//----------------------------------------------------------------------------
// File: Convolution.cpp
//
// Implement C++ AMP based simple and tiled version of Convolution filter used in
// image processing.
//----------------------------------------------------------------------------
#define DEFAULT_WIDTH 512
#define DEFAULT_HEIGHT 512
// TILE_SIZE should be multiple of both DEFAULT_WIDTH and DEFAULT_HEIGHT
#define TILE_SIZE 128
#define radius 7
#define width DEFAULT_WIDTH
#define height DEFAULT_HEIGHT
#define clamp(a, b, c) ((a) < (b) ? (b) : ((a) > (c) ? (c) : (a)))
//----------------------------------------------------------------------------
// Simple implementation of convolution filter along different dimension
//----------------------------------------------------------------------------
static __attribute__((always_inline)) __device__ float convolution_dim_simple(const float* img, const float* filter)
{
float sum = 0.0f;
for (int k = -radius; k <= radius; k++)
{
int dim = clamp((blockDim.y*blockIdx.y + threadIdx.y) + k, 0, height-1);
int aIdxX = (blockDim.x*blockIdx.x + threadIdx.x);
int aIdxY = dim;
int kidx = k + radius;
sum += img[aIdxY*width + aIdxX]*filter[kidx];
}
return sum;
}
//----------------------------------------------------------------------------
// Simple implementation of convolution separable filter
//----------------------------------------------------------------------------
__global__ void convolution_simple(float* v_img, float* v_filter, float* v_result)
{
v_result[(blockDim.y*blockIdx.y + threadIdx.y)*width + (blockDim.x*blockIdx.x + threadIdx.x)] = convolution_dim_simple(v_img, v_filter);
#ifdef MUTATION
v_result[(blockDim.y*blockIdx.y + threadIdx.y)*width + (blockDim.x*blockIdx.x + threadIdx.x) + 1] = v_result[(blockDim.y*blockIdx.y + threadIdx.y)*width + (blockDim.x*blockIdx.x + threadIdx.x) + 1];
/* BUGINJECT: ADD_ACCESS, UP */
#endif
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //pass
//--blockDim=[128,128] --gridDim=[4,4]
#include <hip/hip_runtime.h>
//////////////////////////////////////////////////////////////////////////////
//// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
//// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
//// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
//// PARTICULAR PURPOSE.
////
//// Copyright (c) Microsoft Corporation. All rights reserved
//////////////////////////////////////////////////////////////////////////////
//----------------------------------------------------------------------------
// File: Convolution.cpp
//
// Implement C++ AMP based simple and tiled version of Convolution filter used in
// image processing.
//----------------------------------------------------------------------------
#define DEFAULT_WIDTH 512
#define DEFAULT_HEIGHT 512
// TILE_SIZE should be multiple of both DEFAULT_WIDTH and DEFAULT_HEIGHT
#define TILE_SIZE 128
#define radius 7
#define width DEFAULT_WIDTH
#define height DEFAULT_HEIGHT
#define clamp(a, b, c) ((a) < (b) ? (b) : ((a) > (c) ? (c) : (a)))
//----------------------------------------------------------------------------
// Simple implementation of convolution filter along different dimension
//----------------------------------------------------------------------------
static __attribute__((always_inline)) __device__ float convolution_dim_simple(const float* img, const float* filter)
{
float sum = 0.0f;
for (int k = -radius; k <= radius; k++)
{
int dim = clamp((blockDim.y*blockIdx.y + threadIdx.y) + k, 0, height-1);
int aIdxX = (blockDim.x*blockIdx.x + threadIdx.x);
int aIdxY = dim;
int kidx = k + radius;
sum += img[aIdxY*width + aIdxX]*filter[kidx];
}
return sum;
}
//----------------------------------------------------------------------------
// Simple implementation of convolution separable filter
//----------------------------------------------------------------------------
__global__ void convolution_simple(float* v_img, float* v_filter, float* v_result)
{
v_result[(blockDim.y*blockIdx.y + threadIdx.y)*width + (blockDim.x*blockIdx.x + threadIdx.x)] = convolution_dim_simple(v_img, v_filter);
#ifdef MUTATION
v_result[(blockDim.y*blockIdx.y + threadIdx.y)*width + (blockDim.x*blockIdx.x + threadIdx.x) + 1] = v_result[(blockDim.y*blockIdx.y + threadIdx.y)*width + (blockDim.x*blockIdx.x + threadIdx.x) + 1];
/* BUGINJECT: ADD_ACCESS, UP */
#endif
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18convolution_simplePfS_S_
.globl _Z18convolution_simplePfS_S_
.p2align 8
.type _Z18convolution_simplePfS_S_,@function
_Z18convolution_simplePfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v2, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_mul_i32 s15, s15, s3
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v2, s15, v3
s_mov_b32 s2, -7
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v3, s2, v2
s_load_b32 s3, s[6:7], 0x0
s_add_i32 s2, s2, 1
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
v_min_u32_e32 v3, 0x1ff, v3
s_cmp_lg_u32 s2, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v3, v3, 9, v0
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v1, s3, v3
s_cbranch_scc1 .LBB0_1
s_load_b64 s[0:1], s[0:1], 0x10
v_lshl_add_u32 v2, v2, 9, v0
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18convolution_simplePfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18convolution_simplePfS_S_, .Lfunc_end0-_Z18convolution_simplePfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18convolution_simplePfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18convolution_simplePfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //pass
//--blockDim=[128,128] --gridDim=[4,4]
#include <hip/hip_runtime.h>
//////////////////////////////////////////////////////////////////////////////
//// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
//// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
//// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
//// PARTICULAR PURPOSE.
////
//// Copyright (c) Microsoft Corporation. All rights reserved
//////////////////////////////////////////////////////////////////////////////
//----------------------------------------------------------------------------
// File: Convolution.cpp
//
// Implement C++ AMP based simple and tiled version of Convolution filter used in
// image processing.
//----------------------------------------------------------------------------
#define DEFAULT_WIDTH 512
#define DEFAULT_HEIGHT 512
// TILE_SIZE should be multiple of both DEFAULT_WIDTH and DEFAULT_HEIGHT
#define TILE_SIZE 128
#define radius 7
#define width DEFAULT_WIDTH
#define height DEFAULT_HEIGHT
#define clamp(a, b, c) ((a) < (b) ? (b) : ((a) > (c) ? (c) : (a)))
//----------------------------------------------------------------------------
// Simple implementation of convolution filter along different dimension
//----------------------------------------------------------------------------
static __attribute__((always_inline)) __device__ float convolution_dim_simple(const float* img, const float* filter)
{
float sum = 0.0f;
for (int k = -radius; k <= radius; k++)
{
int dim = clamp((blockDim.y*blockIdx.y + threadIdx.y) + k, 0, height-1);
int aIdxX = (blockDim.x*blockIdx.x + threadIdx.x);
int aIdxY = dim;
int kidx = k + radius;
sum += img[aIdxY*width + aIdxX]*filter[kidx];
}
return sum;
}
//----------------------------------------------------------------------------
// Simple implementation of convolution separable filter
//----------------------------------------------------------------------------
__global__ void convolution_simple(float* v_img, float* v_filter, float* v_result)
{
v_result[(blockDim.y*blockIdx.y + threadIdx.y)*width + (blockDim.x*blockIdx.x + threadIdx.x)] = convolution_dim_simple(v_img, v_filter);
#ifdef MUTATION
v_result[(blockDim.y*blockIdx.y + threadIdx.y)*width + (blockDim.x*blockIdx.x + threadIdx.x) + 1] = v_result[(blockDim.y*blockIdx.y + threadIdx.y)*width + (blockDim.x*blockIdx.x + threadIdx.x) + 1];
/* BUGINJECT: ADD_ACCESS, UP */
#endif
} | .text
.file "kernel.hip"
.globl _Z33__device_stub__convolution_simplePfS_S_ # -- Begin function _Z33__device_stub__convolution_simplePfS_S_
.p2align 4, 0x90
.type _Z33__device_stub__convolution_simplePfS_S_,@function
_Z33__device_stub__convolution_simplePfS_S_: # @_Z33__device_stub__convolution_simplePfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18convolution_simplePfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z33__device_stub__convolution_simplePfS_S_, .Lfunc_end0-_Z33__device_stub__convolution_simplePfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18convolution_simplePfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18convolution_simplePfS_S_,@object # @_Z18convolution_simplePfS_S_
.section .rodata,"a",@progbits
.globl _Z18convolution_simplePfS_S_
.p2align 3, 0x0
_Z18convolution_simplePfS_S_:
.quad _Z33__device_stub__convolution_simplePfS_S_
.size _Z18convolution_simplePfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18convolution_simplePfS_S_"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__convolution_simplePfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18convolution_simplePfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18convolution_simplePfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R15, SR_CTAID.Y ; /* 0x00000000000f7919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0040*/ S2R R12, SR_CTAID.X ; /* 0x00000000000c7919 */
/* 0x000e680000002500 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R15, R15, c[0x0][0x4], R0 ; /* 0x000001000f0f7a24 */
/* 0x001fca00078e0200 */
/*0070*/ IADD3 R0, R15.reuse, -0x7, RZ ; /* 0xfffffff90f007810 */
/* 0x040fe40007ffe0ff */
/*0080*/ IADD3 R2, R15, -0x6, RZ ; /* 0xfffffffa0f027810 */
/* 0x000fe20007ffe0ff */
/*0090*/ IMAD R12, R12, c[0x0][0x0], R3 ; /* 0x000000000c0c7a24 */
/* 0x002fe200078e0203 */
/*00a0*/ IMNMX.U32 R3, R0, 0x1ff, PT ; /* 0x000001ff00037817 */
/* 0x000fe20003800000 */
/*00b0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*00c0*/ IMNMX.U32 R7, R2, 0x1ff, PT ; /* 0x000001ff02077817 */
/* 0x000fe40003800000 */
/*00d0*/ LEA R3, R3, R12, 0x9 ; /* 0x0000000c03037211 */
/* 0x000fe400078e48ff */
/*00e0*/ IADD3 R6, R15, -0x5, RZ ; /* 0xfffffffb0f067810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD R7, R7, 0x200, R12 ; /* 0x0000020007077824 */
/* 0x000fe200078e020c */
/*0100*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD.WIDE R4, R3, R0, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fe200078e0200 */
/*0120*/ IMNMX.U32 R9, R6, 0x1ff, PT ; /* 0x000001ff06097817 */
/* 0x000fc40003800000 */
/*0130*/ IADD3 R6, R15, -0x4, RZ ; /* 0xfffffffc0f067810 */
/* 0x000fe20007ffe0ff */
/*0140*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe200078e00ff */
/*0150*/ LEA R23, R9, R12, 0x9 ; /* 0x0000000c09177211 */
/* 0x000fe200078e48ff */
/*0160*/ IMAD.WIDE R16, R7, R0, c[0x0][0x160] ; /* 0x0000580007107625 */
/* 0x000fe200078e0200 */
/*0170*/ IMNMX.U32 R7, R6, 0x1ff, PT ; /* 0x000001ff06077817 */
/* 0x000fe20003800000 */
/*0180*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x0000a2000c1e1900 */
/*0190*/ IADD3 R10, R15, -0x3, RZ ; /* 0xfffffffd0f0a7810 */
/* 0x000fc60007ffe0ff */
/*01a0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ IMAD.WIDE R22, R23, R0, c[0x0][0x160] ; /* 0x0000580017167625 */
/* 0x000fe200078e0200 */
/*01c0*/ IMNMX.U32 R11, R10, 0x1ff, PT ; /* 0x000001ff0a0b7817 */
/* 0x000fe40003800000 */
/*01d0*/ LDG.E R6, [R16.64] ; /* 0x0000000410067981 */
/* 0x0002e2000c1e1900 */
/*01e0*/ IMAD R25, R7, 0x200, R12 ; /* 0x0000020007197824 */
/* 0x000fc600078e020c */
/*01f0*/ LDG.E R7, [R2.64+0x4] ; /* 0x0000040402077981 */
/* 0x000ee2000c1e1900 */
/*0200*/ LEA R11, R11, R12, 0x9 ; /* 0x0000000c0b0b7211 */
/* 0x000fe200078e48ff */
/*0210*/ IMAD.WIDE R24, R25, R0.reuse, c[0x0][0x160] ; /* 0x0000580019187625 */
/* 0x080fe400078e0200 */
/*0220*/ LDG.E R18, [R22.64] ; /* 0x0000000416127981 */
/* 0x000968000c1e1900 */
/*0230*/ LDG.E R19, [R2.64+0x8] ; /* 0x0000080402137981 */
/* 0x000f62000c1e1900 */
/*0240*/ IMAD.WIDE R26, R11, R0, c[0x0][0x160] ; /* 0x000058000b1a7625 */
/* 0x000fc600078e0200 */
/*0250*/ LDG.E R11, [R24.64] ; /* 0x00000004180b7981 */
/* 0x000168000c1e1900 */
/*0260*/ LDG.E R20, [R2.64+0xc] ; /* 0x00000c0402147981 */
/* 0x000f68000c1e1900 */
/*0270*/ LDG.E R21, [R26.64] ; /* 0x000000041a157981 */
/* 0x000368000c1e1900 */
/*0280*/ LDG.E R10, [R2.64+0x10] ; /* 0x00001004020a7981 */
/* 0x000f62000c1e1900 */
/*0290*/ IADD3 R4, R15, -0x2, RZ ; /* 0xfffffffe0f047810 */
/* 0x001fc40007ffe0ff */
/*02a0*/ IMNMX.U32 R13, R15, 0x1ff, PT ; /* 0x000001ff0f0d7817 */
/* 0x000fe20003800000 */
/*02b0*/ LDG.E R28, [R2.64+0x38] ; /* 0x00003804021c7981 */
/* 0x000162000c1e1900 */
/*02c0*/ IMNMX.U32 R5, R4, 0x1ff, PT ; /* 0x000001ff04057817 */
/* 0x000fc60003800000 */
/*02d0*/ IMAD R13, R13, 0x200, R12 ; /* 0x000002000d0d7824 */
/* 0x000fe200078e020c */
/*02e0*/ LEA R5, R5, R12, 0x9 ; /* 0x0000000c05057211 */
/* 0x000fe200078e48ff */
/*02f0*/ LDG.E R26, [R2.64+0x30] ; /* 0x00003004021a7981 */
/* 0x002164000c1e1900 */
/*0300*/ IMAD.WIDE R16, R13, R0, c[0x0][0x160] ; /* 0x000058000d107625 */
/* 0x000fe200078e0200 */
/*0310*/ IADD3 R13, R15, -0x1, RZ ; /* 0xffffffff0f0d7810 */
/* 0x000fc60007ffe0ff */
/*0320*/ IMAD.WIDE R4, R5, R0.reuse, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x080fe200078e0200 */
/*0330*/ IMNMX.U32 R13, R13, 0x1ff, PT ; /* 0x000001ff0d0d7817 */
/* 0x000fe20003800000 */
/*0340*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000362000c1e1900 */
/*0350*/ IADD3 R22, R15.reuse, 0x1, RZ ; /* 0x000000010f167810 */
/* 0x050fe40007ffe0ff */
/*0360*/ IADD3 R24, R15.reuse, 0x2, RZ ; /* 0x000000020f187810 */
/* 0x040fe20007ffe0ff */
/*0370*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000962000c1e1900 */
/*0380*/ IADD3 R25, R15, 0x3, RZ ; /* 0x000000030f197810 */
/* 0x000fe20007ffe0ff */
/*0390*/ IMAD R13, R13, 0x200, R12 ; /* 0x000002000d0d7824 */
/* 0x000fe200078e020c */
/*03a0*/ IMNMX.U32 R23, R22, 0x1ff, PT ; /* 0x000001ff16177817 */
/* 0x000fe40003800000 */
/*03b0*/ IMNMX.U32 R27, R24, 0x1ff, PT ; /* 0x000001ff181b7817 */
/* 0x000fe20003800000 */
/*03c0*/ LDG.E R17, [R2.64+0x14] ; /* 0x0000140402117981 */
/* 0x002f62000c1e1900 */
/*03d0*/ IMNMX.U32 R29, R25, 0x1ff, PT ; /* 0x000001ff191d7817 */
/* 0x000fe20003800000 */
/*03e0*/ IMAD.WIDE R24, R13, R0, c[0x0][0x160] ; /* 0x000058000d187625 */
/* 0x000fe200078e0200 */
/*03f0*/ LEA R27, R27, R12, 0x9 ; /* 0x0000000c1b1b7211 */
/* 0x000fc600078e48ff */
/*0400*/ IMAD R5, R29, 0x200, R12 ; /* 0x000002001d057824 */
/* 0x010fe200078e020c */
/*0410*/ LDG.E R13, [R24.64] ; /* 0x00000004180d7981 */
/* 0x000328000c1e1900 */
/*0420*/ LDG.E R29, [R2.64+0x2c] ; /* 0x00002c04021d7981 */
/* 0x000128000c1e1900 */
/*0430*/ LDG.E R25, [R2.64+0x20] ; /* 0x0000200402197981 */
/* 0x002128000c1e1900 */
/*0440*/ LDG.E R24, [R2.64+0x24] ; /* 0x0000240402187981 */
/* 0x000122000c1e1900 */
/*0450*/ FFMA R8, R8, R9, RZ ; /* 0x0000000908087223 */
/* 0x004fe200000000ff */
/*0460*/ LEA R9, R23, R12, 0x9 ; /* 0x0000000c17097211 */
/* 0x000fc600078e48ff */
/*0470*/ FFMA R4, R6, R7, R8 ; /* 0x0000000706047223 */
/* 0x008fe20000000008 */
/*0480*/ IADD3 R23, R15, 0x4, RZ ; /* 0x000000040f177810 */
/* 0x000fe20007ffe0ff */
/*0490*/ IMAD.WIDE R8, R9, R0, c[0x0][0x160] ; /* 0x0000580009087625 */
/* 0x000fc800078e0200 */
/*04a0*/ FFMA R22, R18, R19, R4 ; /* 0x0000001312167223 */
/* 0x020fe40000000004 */
/*04b0*/ IMAD.WIDE R6, R27, R0, c[0x0][0x160] ; /* 0x000058001b067625 */
/* 0x000fe200078e0200 */
/*04c0*/ IMNMX.U32 R23, R23, 0x1ff, PT ; /* 0x000001ff17177817 */
/* 0x000fe20003800000 */
/*04d0*/ LDG.E R27, [R2.64+0x1c] ; /* 0x00001c04021b7981 */
/* 0x0000a4000c1e1900 */
/*04e0*/ FFMA R11, R11, R20, R22 ; /* 0x000000140b0b7223 */
/* 0x000fe40000000016 */
/*04f0*/ LDG.E R18, [R8.64] ; /* 0x0000000408127981 */
/* 0x0002e8000c1e1900 */
/*0500*/ LDG.E R22, [R2.64+0x18] ; /* 0x0000180402167981 */
/* 0x000122000c1e1900 */
/*0510*/ FFMA R21, R21, R10, R11 ; /* 0x0000000a15157223 */
/* 0x000fe2000000000b */
/*0520*/ IADD3 R10, R15, 0x5, RZ ; /* 0x000000050f0a7810 */
/* 0x000fe20007ffe0ff */
/*0530*/ IMAD.WIDE R4, R5, R0, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe200078e0200 */
/*0540*/ IADD3 R8, R15, 0x6, RZ ; /* 0x000000060f087810 */
/* 0x002fe20007ffe0ff */
/*0550*/ LDG.E R19, [R6.64] ; /* 0x0000000406137981 */
/* 0x000362000c1e1900 */
/*0560*/ IMNMX.U32 R9, R10, 0x1ff, PT ; /* 0x000001ff0a097817 */
/* 0x000fc40003800000 */
/*0570*/ IMNMX.U32 R11, R8, 0x1ff, PT ; /* 0x000001ff080b7817 */
/* 0x000fe20003800000 */
/*0580*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000162000c1e1900 */
/*0590*/ LEA R7, R23, R12, 0x9 ; /* 0x0000000c17077211 */
/* 0x002fc600078e48ff */
/*05a0*/ LDG.E R23, [R2.64+0x28] ; /* 0x0000280402177981 */
/* 0x000362000c1e1900 */
/*05b0*/ IADD3 R4, R15, 0x7, RZ ; /* 0x000000070f047810 */
/* 0x001fe20007ffe0ff */
/*05c0*/ IMAD.WIDE R6, R7, R0, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fe200078e0200 */
/*05d0*/ LEA R5, R9, R12, 0x9 ; /* 0x0000000c09057211 */
/* 0x000fc600078e48ff */
/*05e0*/ IMAD R9, R11, 0x200, R12 ; /* 0x000002000b097824 */
/* 0x000fe200078e020c */
/*05f0*/ IMNMX.U32 R11, R4, 0x1ff, PT ; /* 0x000001ff040b7817 */
/* 0x000fe20003800000 */
/*0600*/ IMAD.WIDE R4, R5, R0, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe200078e0200 */
/*0610*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f64000c1e1900 */
/*0620*/ LEA R11, R11, R12, 0x9 ; /* 0x0000000c0b0b7211 */
/* 0x000fe200078e48ff */
/*0630*/ IMAD.WIDE R8, R9, R0.reuse, c[0x0][0x160] ; /* 0x0000580009087625 */
/* 0x080fe400078e0200 */
/*0640*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000164000c1e1900 */
/*0650*/ IMAD.WIDE R10, R11, R0, c[0x0][0x160] ; /* 0x000058000b0a7625 */
/* 0x000fc400078e0200 */
/*0660*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f68000c1e1900 */
/*0670*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000f68000c1e1900 */
/*0680*/ LDG.E R5, [R2.64+0x34] ; /* 0x0000340402057981 */
/* 0x001362000c1e1900 */
/*0690*/ FFMA R14, R14, R17, R21 ; /* 0x000000110e0e7223 */
/* 0x000fe20000000015 */
/*06a0*/ LEA R15, R15, R12, 0x9 ; /* 0x0000000c0f0f7211 */
/* 0x000fca00078e48ff */
/*06b0*/ IMAD.WIDE.U32 R2, R15, R0, c[0x0][0x170] ; /* 0x00005c000f027625 */
/* 0x002fc800078e0000 */
/*06c0*/ FFMA R13, R13, R22, R14 ; /* 0x000000160d0d7223 */
/* 0x010fc8000000000e */
/*06d0*/ FFMA R13, R16, R27, R13 ; /* 0x0000001b100d7223 */
/* 0x004fc8000000000d */
/*06e0*/ FFMA R13, R18, R25, R13 ; /* 0x00000019120d7223 */
/* 0x008fc8000000000d */
/*06f0*/ FFMA R13, R19, R24, R13 ; /* 0x00000018130d7223 */
/* 0x020fc8000000000d */
/*0700*/ FFMA R13, R20, R23, R13 ; /* 0x00000017140d7223 */
/* 0x000fc8000000000d */
/*0710*/ FFMA R13, R6, R29, R13 ; /* 0x0000001d060d7223 */
/* 0x000fc8000000000d */
/*0720*/ FFMA R4, R4, R26, R13 ; /* 0x0000001a04047223 */
/* 0x000fc8000000000d */
/*0730*/ FFMA R4, R8, R5, R4 ; /* 0x0000000508047223 */
/* 0x000fc80000000004 */
/*0740*/ FFMA R11, R11, R28, R4 ; /* 0x0000001c0b0b7223 */
/* 0x000fca0000000004 */
/*0750*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c101904 */
/*0760*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0770*/ BRA 0x770; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18convolution_simplePfS_S_
.globl _Z18convolution_simplePfS_S_
.p2align 8
.type _Z18convolution_simplePfS_S_,@function
_Z18convolution_simplePfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v2, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_mul_i32 s15, s15, s3
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v2, s15, v3
s_mov_b32 s2, -7
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v3, s2, v2
s_load_b32 s3, s[6:7], 0x0
s_add_i32 s2, s2, 1
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
v_min_u32_e32 v3, 0x1ff, v3
s_cmp_lg_u32 s2, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v3, v3, 9, v0
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v1, s3, v3
s_cbranch_scc1 .LBB0_1
s_load_b64 s[0:1], s[0:1], 0x10
v_lshl_add_u32 v2, v2, 9, v0
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18convolution_simplePfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18convolution_simplePfS_S_, .Lfunc_end0-_Z18convolution_simplePfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18convolution_simplePfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18convolution_simplePfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006a483_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z18convolution_simplePfS_S_PfS_S_
.type _Z42__device_stub__Z18convolution_simplePfS_S_PfS_S_, @function
_Z42__device_stub__Z18convolution_simplePfS_S_PfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18convolution_simplePfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z42__device_stub__Z18convolution_simplePfS_S_PfS_S_, .-_Z42__device_stub__Z18convolution_simplePfS_S_PfS_S_
.globl _Z18convolution_simplePfS_S_
.type _Z18convolution_simplePfS_S_, @function
_Z18convolution_simplePfS_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18convolution_simplePfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z18convolution_simplePfS_S_, .-_Z18convolution_simplePfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18convolution_simplePfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18convolution_simplePfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z33__device_stub__convolution_simplePfS_S_ # -- Begin function _Z33__device_stub__convolution_simplePfS_S_
.p2align 4, 0x90
.type _Z33__device_stub__convolution_simplePfS_S_,@function
_Z33__device_stub__convolution_simplePfS_S_: # @_Z33__device_stub__convolution_simplePfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18convolution_simplePfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z33__device_stub__convolution_simplePfS_S_, .Lfunc_end0-_Z33__device_stub__convolution_simplePfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18convolution_simplePfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18convolution_simplePfS_S_,@object # @_Z18convolution_simplePfS_S_
.section .rodata,"a",@progbits
.globl _Z18convolution_simplePfS_S_
.p2align 3, 0x0
_Z18convolution_simplePfS_S_:
.quad _Z33__device_stub__convolution_simplePfS_S_
.size _Z18convolution_simplePfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18convolution_simplePfS_S_"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__convolution_simplePfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18convolution_simplePfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
int main(){
cudaDeviceProp devProps;
cudaGetDeviceProperties(&devProps,0);
printf("Device 0 name: %s\n",devProps.name);
printf("Compute capability %d.%d\n",devProps.major,devProps.minor);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
int main(){
cudaDeviceProp devProps;
cudaGetDeviceProperties(&devProps,0);
printf("Device 0 name: %s\n",devProps.name);
printf("Compute capability %d.%d\n",devProps.major,devProps.minor);
} | .file "tmpxft_001bc81e_00000000-6_device_specs.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Device 0 name: %s\n"
.LC1:
.string "Compute capability %d.%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1040, %rsp
.cfi_def_cfa_offset 1056
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq %rsp, %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %ecx
movl 360(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $1040, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
int main(){
cudaDeviceProp devProps;
cudaGetDeviceProperties(&devProps,0);
printf("Device 0 name: %s\n",devProps.name);
printf("Compute capability %d.%d\n",devProps.major,devProps.minor);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
int main(){
hipDeviceProp_t devProps;
hipGetDeviceProperties(&devProps,0);
printf("Device 0 name: %s\n",devProps.name);
printf("Compute capability %d.%d\n",devProps.major,devProps.minor);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
int main(){
hipDeviceProp_t devProps;
hipGetDeviceProperties(&devProps,0);
printf("Device 0 name: %s\n",devProps.name);
printf("Compute capability %d.%d\n",devProps.major,devProps.minor);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
int main(){
hipDeviceProp_t devProps;
hipGetDeviceProperties(&devProps,0);
printf("Device 0 name: %s\n",devProps.name);
printf("Compute capability %d.%d\n",devProps.major,devProps.minor);
} | .text
.file "device_specs.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 1488
.cfi_offset %rbx, -16
movq %rsp, %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 360(%rsp), %esi
movl 364(%rsp), %edx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device 0 name: %s\n"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Compute capability %d.%d\n"
.size .L.str.1, 26
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001bc81e_00000000-6_device_specs.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Device 0 name: %s\n"
.LC1:
.string "Compute capability %d.%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1040, %rsp
.cfi_def_cfa_offset 1056
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq %rsp, %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %ecx
movl 360(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $1040, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "device_specs.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 1488
.cfi_offset %rbx, -16
movq %rsp, %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 360(%rsp), %esi
movl 364(%rsp), %edx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device 0 name: %s\n"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Compute capability %d.%d\n"
.size .L.str.1, 26
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // #include <gtest/gtest.h>
// #include <matazure/cuda/lambda_tensor.hpp>
// #include <mtensor.hpp>
// // #include <nvfunctional>
// using namespace matazure;
// using namespace testing;
// __device__ void print(int i) { printf("%d,", i); }
// struct print_op {
// MATAZURE_GENERAL void operator()(int i) { printf("%d, ", i); }
// };
// // #pragma nv_exec_check_disable
// // MATAZURE_GENERAL void printhd(int i) { print(i); }
// TEST(LauchTest, OnlySupportDeviceLambda) {
// cuda::launch([] __device__() { /*printf("thread x: %d\n", threadIdx.x);*/ });
// }
// TEST(ForIndexTest, Lambda) {
// cuda::for_index(0, 10, [] MATAZURE_GENERAL(int i) { printf("%d,", i); });
// printf("\n");
// cuda::for_index(0, 10, [] __device__(int i) { printf("%d,", i); });
// printf("\n");
// // if use device code in host, will do none
// matazure::for_index(0, 10, [] __device__(int i) { printf("%d,", i); });
// printf("\n");
// // cuda::for_index(0, 10, print_op{});
// // printf("\n");
// } | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // #include <gtest/gtest.h>
// #include <matazure/cuda/lambda_tensor.hpp>
// #include <mtensor.hpp>
// // #include <nvfunctional>
// using namespace matazure;
// using namespace testing;
// __device__ void print(int i) { printf("%d,", i); }
// struct print_op {
// MATAZURE_GENERAL void operator()(int i) { printf("%d, ", i); }
// };
// // #pragma nv_exec_check_disable
// // MATAZURE_GENERAL void printhd(int i) { print(i); }
// TEST(LauchTest, OnlySupportDeviceLambda) {
// cuda::launch([] __device__() { /*printf("thread x: %d\n", threadIdx.x);*/ });
// }
// TEST(ForIndexTest, Lambda) {
// cuda::for_index(0, 10, [] MATAZURE_GENERAL(int i) { printf("%d,", i); });
// printf("\n");
// cuda::for_index(0, 10, [] __device__(int i) { printf("%d,", i); });
// printf("\n");
// // if use device code in host, will do none
// matazure::for_index(0, 10, [] __device__(int i) { printf("%d,", i); });
// printf("\n");
// // cuda::for_index(0, 10, print_op{});
// // printf("\n");
// } | .file "tmpxft_00000df1_00000000-6_ut_algorithm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // #include <gtest/gtest.h>
// #include <matazure/cuda/lambda_tensor.hpp>
// #include <mtensor.hpp>
// // #include <nvfunctional>
// using namespace matazure;
// using namespace testing;
// __device__ void print(int i) { printf("%d,", i); }
// struct print_op {
// MATAZURE_GENERAL void operator()(int i) { printf("%d, ", i); }
// };
// // #pragma nv_exec_check_disable
// // MATAZURE_GENERAL void printhd(int i) { print(i); }
// TEST(LauchTest, OnlySupportDeviceLambda) {
// cuda::launch([] __device__() { /*printf("thread x: %d\n", threadIdx.x);*/ });
// }
// TEST(ForIndexTest, Lambda) {
// cuda::for_index(0, 10, [] MATAZURE_GENERAL(int i) { printf("%d,", i); });
// printf("\n");
// cuda::for_index(0, 10, [] __device__(int i) { printf("%d,", i); });
// printf("\n");
// // if use device code in host, will do none
// matazure::for_index(0, 10, [] __device__(int i) { printf("%d,", i); });
// printf("\n");
// // cuda::for_index(0, 10, print_op{});
// // printf("\n");
// } | #include <hip/hip_runtime.h>
// #include <gtest/gtest.h>
// #include <matazure/cuda/lambda_tensor.hpp>
// #include <mtensor.hpp>
// // #include <nvfunctional>
// using namespace matazure;
// using namespace testing;
// __device__ void print(int i) { printf("%d,", i); }
// struct print_op {
// MATAZURE_GENERAL void operator()(int i) { printf("%d, ", i); }
// };
// // #pragma nv_exec_check_disable
// // MATAZURE_GENERAL void printhd(int i) { print(i); }
// TEST(LauchTest, OnlySupportDeviceLambda) {
// cuda::launch([] __device__() { /*printf("thread x: %d\n", threadIdx.x);*/ });
// }
// TEST(ForIndexTest, Lambda) {
// cuda::for_index(0, 10, [] MATAZURE_GENERAL(int i) { printf("%d,", i); });
// printf("\n");
// cuda::for_index(0, 10, [] __device__(int i) { printf("%d,", i); });
// printf("\n");
// // if use device code in host, will do none
// matazure::for_index(0, 10, [] __device__(int i) { printf("%d,", i); });
// printf("\n");
// // cuda::for_index(0, 10, print_op{});
// // printf("\n");
// } |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// #include <gtest/gtest.h>
// #include <matazure/cuda/lambda_tensor.hpp>
// #include <mtensor.hpp>
// // #include <nvfunctional>
// using namespace matazure;
// using namespace testing;
// __device__ void print(int i) { printf("%d,", i); }
// struct print_op {
// MATAZURE_GENERAL void operator()(int i) { printf("%d, ", i); }
// };
// // #pragma nv_exec_check_disable
// // MATAZURE_GENERAL void printhd(int i) { print(i); }
// TEST(LauchTest, OnlySupportDeviceLambda) {
// cuda::launch([] __device__() { /*printf("thread x: %d\n", threadIdx.x);*/ });
// }
// TEST(ForIndexTest, Lambda) {
// cuda::for_index(0, 10, [] MATAZURE_GENERAL(int i) { printf("%d,", i); });
// printf("\n");
// cuda::for_index(0, 10, [] __device__(int i) { printf("%d,", i); });
// printf("\n");
// // if use device code in host, will do none
// matazure::for_index(0, 10, [] __device__(int i) { printf("%d,", i); });
// printf("\n");
// // cuda::for_index(0, 10, print_op{});
// // printf("\n");
// } | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// #include <gtest/gtest.h>
// #include <matazure/cuda/lambda_tensor.hpp>
// #include <mtensor.hpp>
// // #include <nvfunctional>
// using namespace matazure;
// using namespace testing;
// __device__ void print(int i) { printf("%d,", i); }
// struct print_op {
// MATAZURE_GENERAL void operator()(int i) { printf("%d, ", i); }
// };
// // #pragma nv_exec_check_disable
// // MATAZURE_GENERAL void printhd(int i) { print(i); }
// TEST(LauchTest, OnlySupportDeviceLambda) {
// cuda::launch([] __device__() { /*printf("thread x: %d\n", threadIdx.x);*/ });
// }
// TEST(ForIndexTest, Lambda) {
// cuda::for_index(0, 10, [] MATAZURE_GENERAL(int i) { printf("%d,", i); });
// printf("\n");
// cuda::for_index(0, 10, [] __device__(int i) { printf("%d,", i); });
// printf("\n");
// // if use device code in host, will do none
// matazure::for_index(0, 10, [] __device__(int i) { printf("%d,", i); });
// printf("\n");
// // cuda::for_index(0, 10, print_op{});
// // printf("\n");
// } | .text
.file "ut_algorithm.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00000df1_00000000-6_ut_algorithm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ut_algorithm.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <iostream>
#include <cuda_profiler_api.h>
//#include <cutil.h>
#include <cuda_runtime.h>
float* h_A;
float* h_B;
float* h_C;
float* h_res;
float* d_A;
float* d_B;
float* d_C;
float* d_res;
__global__
//void compute(const float* A, const float* B, const float* C, float* D, int n) {
void compute(float* D, int n, int div) {
int tid = blockDim.x * blockIdx.x + threadIdx.x;
float I1 = tid * 2.0;
int thread_id = threadIdx.x % 32;
if (thread_id < div) {
__asm volatile (
" .reg .s32 %r129;\n\t"
" .reg .s32 %r30;\n\t"
" .reg .s32 %r31;\n\t"
" .reg .s32 %r32;\n\t"
" .reg .s32 %r33;\n\t"
" .reg .s32 %r34;\n\t"
" .reg .s32 %r35;\n\t"
" .reg .s32 %r36;\n\t"
" .reg .s32 %r37;\n\t"
" .reg .s32 %r38;\n\t"
" .reg .s32 %r39;\n\t"
" .reg .s32 %r40;\n\t"
" .reg .s32 %r41;\n\t"
" .reg .s32 %r42;\n\t"
" .reg .s32 %r43;\n\t"
" .reg .s32 %r44;\n\t"
" .reg .s32 %r45;\n\t"
" .reg .f64 %r112;\n\t"
" .reg .f64 %r113;\n\t"
" .reg .f64 %r114;\n\t"
" .reg .f64 %r115;\n\t"
" .reg .f64 %r116;\n\t"
" .reg .f64 %r117;\n\t"
" .reg .f64 %r118;\n\t"
" .reg .f64 %r119;\n\t"
" .reg .f64 %r120;\n\t"
" .reg .f64 %r121;\n\t"
" .reg .f64 %r122;\n\t"
" .reg .f64 %r123;\n\t"
" .reg .f64 %r124;\n\t"
" .reg .f64 %r125;\n\t"
" .reg .f64 %r126;\n\t"
" .reg .f64 %r127;\n\t"
" .reg .f64 %r128;\n\t"
"mov.f64 %r112, 4.4;\n\t"
"mov.f64 %r113, %r112;\n\t"
"mov.f64 %r114, 2.2;\n\t"
"mov.f64 %r115, 3.3;\n\t"
"mov.f64 %r116, 1.23;\n\t"
"mov.f64 %r117, 2.42;\n\t"
"mov.f64 %r118, 3.34;\n\t"
"mov.f64 %r119, 5.62;\n\t"
"mov.f64 %r120, 2.56;\n\t"
"mov.f64 %r121, 1.56;\n\t"
"mov.f64 %r122, 2.56;\n\t"
"mov.f64 %r123, 5.56;\n\t"
"mov.f64 %r124, 8.56;\n\t"
"mov.f64 %r125, 3.56;\n\t"
"mov.f64 %r126, 5.56;\n\t"
"mov.f64 %r127, 6.56;\n\t"
"mov.f64 %r128, 5.6;\n\t"
);
for (int k = 0; k < n; k++) {
__asm volatile (
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
);
}
}
// __syncthreads();
// if ((blockDim.x * blockIdx.x + threadIdx.x) == 0)
*D = I1;
// __syncthreads();
}
void usage() {
std::cout << "Usage ./binary <num_blocks> <num_threads_per_block> <iterations>" "threads active per warp" << std::endl;
}
int main(int argc, char **argv)
{
if (argc != 5) {
usage();
exit(1);
}
int num_blocks = atoi(argv[1]);
int num_threads_per_block = atoi(argv[2]);
int iterations = atoi(argv[3]);
int divergence = atoi(argv[4]);
// h_A = new float(2.0);
// h_B = new float(3.0);
// h_C = new float(4.0);
// cudaMalloc((void**)&d_A, sizeof(float));
// cudaMalloc((void**)&d_B, sizeof(float));
// cudaMalloc((void**)&d_C, sizeof(float));
cudaMalloc((void**)&d_res, sizeof(float));
// cudaMemcpy(d_A, h_A, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_B, h_B, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_C, h_C, sizeof(float), cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
float time;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
cudaProfilerStart();
// compute<<<num_blocks, num_threads_per_block>>>(d_A, d_B, d_C, d_res, iterations);
compute<<<num_blocks, num_threads_per_block>>>(d_res, iterations, divergence);
cudaDeviceSynchronize();
cudaProfilerStop();
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
std::cout << "GPU Elapsed Time = " << time << std::endl;
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy(h_res, d_res, sizeof(float), cudaMemcpyDeviceToHost);
return 0;
} | code for sm_80
Function : _Z7computePfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0060*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0200 */
/*0070*/ I2F.F64 R2, R0 ; /* 0x0000000000027312 */
/* 0x000e240000201c00 */
/*0080*/ DADD R2, R2, R2 ; /* 0x0000000002027229 */
/* 0x001e140000000002 */
/*0090*/ F2F.F32.F64 R3, R2 ; /* 0x0000000200037310 */
/* 0x001e240000301000 */
/*00a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x001fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <iostream>
#include <cuda_profiler_api.h>
//#include <cutil.h>
#include <cuda_runtime.h>
float* h_A;
float* h_B;
float* h_C;
float* h_res;
float* d_A;
float* d_B;
float* d_C;
float* d_res;
__global__
//void compute(const float* A, const float* B, const float* C, float* D, int n) {
void compute(float* D, int n, int div) {
int tid = blockDim.x * blockIdx.x + threadIdx.x;
float I1 = tid * 2.0;
int thread_id = threadIdx.x % 32;
if (thread_id < div) {
__asm volatile (
" .reg .s32 %r129;\n\t"
" .reg .s32 %r30;\n\t"
" .reg .s32 %r31;\n\t"
" .reg .s32 %r32;\n\t"
" .reg .s32 %r33;\n\t"
" .reg .s32 %r34;\n\t"
" .reg .s32 %r35;\n\t"
" .reg .s32 %r36;\n\t"
" .reg .s32 %r37;\n\t"
" .reg .s32 %r38;\n\t"
" .reg .s32 %r39;\n\t"
" .reg .s32 %r40;\n\t"
" .reg .s32 %r41;\n\t"
" .reg .s32 %r42;\n\t"
" .reg .s32 %r43;\n\t"
" .reg .s32 %r44;\n\t"
" .reg .s32 %r45;\n\t"
" .reg .f64 %r112;\n\t"
" .reg .f64 %r113;\n\t"
" .reg .f64 %r114;\n\t"
" .reg .f64 %r115;\n\t"
" .reg .f64 %r116;\n\t"
" .reg .f64 %r117;\n\t"
" .reg .f64 %r118;\n\t"
" .reg .f64 %r119;\n\t"
" .reg .f64 %r120;\n\t"
" .reg .f64 %r121;\n\t"
" .reg .f64 %r122;\n\t"
" .reg .f64 %r123;\n\t"
" .reg .f64 %r124;\n\t"
" .reg .f64 %r125;\n\t"
" .reg .f64 %r126;\n\t"
" .reg .f64 %r127;\n\t"
" .reg .f64 %r128;\n\t"
"mov.f64 %r112, 4.4;\n\t"
"mov.f64 %r113, %r112;\n\t"
"mov.f64 %r114, 2.2;\n\t"
"mov.f64 %r115, 3.3;\n\t"
"mov.f64 %r116, 1.23;\n\t"
"mov.f64 %r117, 2.42;\n\t"
"mov.f64 %r118, 3.34;\n\t"
"mov.f64 %r119, 5.62;\n\t"
"mov.f64 %r120, 2.56;\n\t"
"mov.f64 %r121, 1.56;\n\t"
"mov.f64 %r122, 2.56;\n\t"
"mov.f64 %r123, 5.56;\n\t"
"mov.f64 %r124, 8.56;\n\t"
"mov.f64 %r125, 3.56;\n\t"
"mov.f64 %r126, 5.56;\n\t"
"mov.f64 %r127, 6.56;\n\t"
"mov.f64 %r128, 5.6;\n\t"
);
for (int k = 0; k < n; k++) {
__asm volatile (
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
);
}
}
// __syncthreads();
// if ((blockDim.x * blockIdx.x + threadIdx.x) == 0)
*D = I1;
// __syncthreads();
}
void usage() {
std::cout << "Usage ./binary <num_blocks> <num_threads_per_block> <iterations>" "threads active per warp" << std::endl;
}
int main(int argc, char **argv)
{
if (argc != 5) {
usage();
exit(1);
}
int num_blocks = atoi(argv[1]);
int num_threads_per_block = atoi(argv[2]);
int iterations = atoi(argv[3]);
int divergence = atoi(argv[4]);
// h_A = new float(2.0);
// h_B = new float(3.0);
// h_C = new float(4.0);
// cudaMalloc((void**)&d_A, sizeof(float));
// cudaMalloc((void**)&d_B, sizeof(float));
// cudaMalloc((void**)&d_C, sizeof(float));
cudaMalloc((void**)&d_res, sizeof(float));
// cudaMemcpy(d_A, h_A, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_B, h_B, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_C, h_C, sizeof(float), cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
float time;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
cudaProfilerStart();
// compute<<<num_blocks, num_threads_per_block>>>(d_A, d_B, d_C, d_res, iterations);
compute<<<num_blocks, num_threads_per_block>>>(d_res, iterations, divergence);
cudaDeviceSynchronize();
cudaProfilerStop();
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
std::cout << "GPU Elapsed Time = " << time << std::endl;
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy(h_res, d_res, sizeof(float), cudaMemcpyDeviceToHost);
return 0;
} | .file "tmpxft_000870de_00000000-6_cvt_32p_asm.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Usage ./binary <num_blocks> <num_threads_per_block> <iterations>threads active per warp"
.text
.globl _Z5usagev
.type _Z5usagev, @function
_Z5usagev:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl $87, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L8
cmpb $0, 56(%rbx)
je .L5
movzbl 67(%rbx), %esi
.L6:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L5:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L6
.cfi_endproc
.LFE3669:
.size _Z5usagev, .-_Z5usagev
.globl _Z28__device_stub__Z7computePfiiPfii
.type _Z28__device_stub__Z7computePfiiPfii, @function
_Z28__device_stub__Z7computePfiiPfii:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7computePfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z28__device_stub__Z7computePfiiPfii, .-_Z28__device_stub__Z7computePfiiPfii
.globl _Z7computePfii
.type _Z7computePfii, @function
_Z7computePfii:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7computePfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z7computePfii, .-_Z7computePfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "GPU Elapsed Time = "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $5, %edi
jne .L22
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl $4, %esi
leaq d_res(%rip), %rdi
call cudaMalloc@PLT
movq %rsp, %rdi
call cudaEventCreate@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
call cudaProfilerStart@PLT
movl %r12d, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %ebp, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
call cudaDeviceSynchronize@PLT
call cudaProfilerStop@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movq 8(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 28(%rsp), %rdi
movq 8(%rsp), %rdx
movq (%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq (%rsp), %rdi
call cudaEventDestroy@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
movl $2, %ecx
movl $4, %edx
movq d_res(%rip), %rsi
movq h_res(%rip), %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call _Z5usagev
movl $1, %edi
call exit@PLT
.L23:
movl %ebx, %edx
movl %r13d, %esi
movq d_res(%rip), %rdi
call _Z28__device_stub__Z7computePfiiPfii
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z7computePfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computePfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl d_res
.bss
.align 8
.type d_res, @object
.size d_res, 8
d_res:
.zero 8
.globl d_C
.align 8
.type d_C, @object
.size d_C, 8
d_C:
.zero 8
.globl d_B
.align 8
.type d_B, @object
.size d_B, 8
d_B:
.zero 8
.globl d_A
.align 8
.type d_A, @object
.size d_A, 8
d_A:
.zero 8
.globl h_res
.align 8
.type h_res, @object
.size h_res, 8
h_res:
.zero 8
.globl h_C
.align 8
.type h_C, @object
.size h_C, 8
h_C:
.zero 8
.globl h_B
.align 8
.type h_B, @object
.size h_B, 8
h_B:
.zero 8
.globl h_A
.align 8
.type h_A, @object
.size h_A, 8
h_A:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <iostream>
#include <cuda_profiler_api.h>
//#include <cutil.h>
#include <cuda_runtime.h>
float* h_A;
float* h_B;
float* h_C;
float* h_res;
float* d_A;
float* d_B;
float* d_C;
float* d_res;
__global__
//void compute(const float* A, const float* B, const float* C, float* D, int n) {
void compute(float* D, int n, int div) {
int tid = blockDim.x * blockIdx.x + threadIdx.x;
float I1 = tid * 2.0;
int thread_id = threadIdx.x % 32;
if (thread_id < div) {
__asm volatile (
" .reg .s32 %r129;\n\t"
" .reg .s32 %r30;\n\t"
" .reg .s32 %r31;\n\t"
" .reg .s32 %r32;\n\t"
" .reg .s32 %r33;\n\t"
" .reg .s32 %r34;\n\t"
" .reg .s32 %r35;\n\t"
" .reg .s32 %r36;\n\t"
" .reg .s32 %r37;\n\t"
" .reg .s32 %r38;\n\t"
" .reg .s32 %r39;\n\t"
" .reg .s32 %r40;\n\t"
" .reg .s32 %r41;\n\t"
" .reg .s32 %r42;\n\t"
" .reg .s32 %r43;\n\t"
" .reg .s32 %r44;\n\t"
" .reg .s32 %r45;\n\t"
" .reg .f64 %r112;\n\t"
" .reg .f64 %r113;\n\t"
" .reg .f64 %r114;\n\t"
" .reg .f64 %r115;\n\t"
" .reg .f64 %r116;\n\t"
" .reg .f64 %r117;\n\t"
" .reg .f64 %r118;\n\t"
" .reg .f64 %r119;\n\t"
" .reg .f64 %r120;\n\t"
" .reg .f64 %r121;\n\t"
" .reg .f64 %r122;\n\t"
" .reg .f64 %r123;\n\t"
" .reg .f64 %r124;\n\t"
" .reg .f64 %r125;\n\t"
" .reg .f64 %r126;\n\t"
" .reg .f64 %r127;\n\t"
" .reg .f64 %r128;\n\t"
"mov.f64 %r112, 4.4;\n\t"
"mov.f64 %r113, %r112;\n\t"
"mov.f64 %r114, 2.2;\n\t"
"mov.f64 %r115, 3.3;\n\t"
"mov.f64 %r116, 1.23;\n\t"
"mov.f64 %r117, 2.42;\n\t"
"mov.f64 %r118, 3.34;\n\t"
"mov.f64 %r119, 5.62;\n\t"
"mov.f64 %r120, 2.56;\n\t"
"mov.f64 %r121, 1.56;\n\t"
"mov.f64 %r122, 2.56;\n\t"
"mov.f64 %r123, 5.56;\n\t"
"mov.f64 %r124, 8.56;\n\t"
"mov.f64 %r125, 3.56;\n\t"
"mov.f64 %r126, 5.56;\n\t"
"mov.f64 %r127, 6.56;\n\t"
"mov.f64 %r128, 5.6;\n\t"
);
for (int k = 0; k < n; k++) {
__asm volatile (
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
);
}
}
// __syncthreads();
// if ((blockDim.x * blockIdx.x + threadIdx.x) == 0)
*D = I1;
// __syncthreads();
}
void usage() {
std::cout << "Usage ./binary <num_blocks> <num_threads_per_block> <iterations>" "threads active per warp" << std::endl;
}
int main(int argc, char **argv)
{
if (argc != 5) {
usage();
exit(1);
}
int num_blocks = atoi(argv[1]);
int num_threads_per_block = atoi(argv[2]);
int iterations = atoi(argv[3]);
int divergence = atoi(argv[4]);
// h_A = new float(2.0);
// h_B = new float(3.0);
// h_C = new float(4.0);
// cudaMalloc((void**)&d_A, sizeof(float));
// cudaMalloc((void**)&d_B, sizeof(float));
// cudaMalloc((void**)&d_C, sizeof(float));
cudaMalloc((void**)&d_res, sizeof(float));
// cudaMemcpy(d_A, h_A, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_B, h_B, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_C, h_C, sizeof(float), cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
float time;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
cudaProfilerStart();
// compute<<<num_blocks, num_threads_per_block>>>(d_A, d_B, d_C, d_res, iterations);
compute<<<num_blocks, num_threads_per_block>>>(d_res, iterations, divergence);
cudaDeviceSynchronize();
cudaProfilerStop();
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
std::cout << "GPU Elapsed Time = " << time << std::endl;
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy(h_res, d_res, sizeof(float), cudaMemcpyDeviceToHost);
return 0;
} | #include <stdio.h>
#include <iostream>
#include <hip/hip_runtime_api.h>
//#include <cutil.h>
#include <hip/hip_runtime.h>
float* h_A;
float* h_B;
float* h_C;
float* h_res;
float* d_A;
float* d_B;
float* d_C;
float* d_res;
__global__
//void compute(const float* A, const float* B, const float* C, float* D, int n) {
void compute(float* D, int n, int div) {
int tid = blockDim.x * blockIdx.x + threadIdx.x;
float I1 = tid * 2.0;
int thread_id = threadIdx.x % 32;
if (thread_id < div) {
__asm volatile (
" .reg .s32 %r129;\n\t"
" .reg .s32 %r30;\n\t"
" .reg .s32 %r31;\n\t"
" .reg .s32 %r32;\n\t"
" .reg .s32 %r33;\n\t"
" .reg .s32 %r34;\n\t"
" .reg .s32 %r35;\n\t"
" .reg .s32 %r36;\n\t"
" .reg .s32 %r37;\n\t"
" .reg .s32 %r38;\n\t"
" .reg .s32 %r39;\n\t"
" .reg .s32 %r40;\n\t"
" .reg .s32 %r41;\n\t"
" .reg .s32 %r42;\n\t"
" .reg .s32 %r43;\n\t"
" .reg .s32 %r44;\n\t"
" .reg .s32 %r45;\n\t"
" .reg .f64 %r112;\n\t"
" .reg .f64 %r113;\n\t"
" .reg .f64 %r114;\n\t"
" .reg .f64 %r115;\n\t"
" .reg .f64 %r116;\n\t"
" .reg .f64 %r117;\n\t"
" .reg .f64 %r118;\n\t"
" .reg .f64 %r119;\n\t"
" .reg .f64 %r120;\n\t"
" .reg .f64 %r121;\n\t"
" .reg .f64 %r122;\n\t"
" .reg .f64 %r123;\n\t"
" .reg .f64 %r124;\n\t"
" .reg .f64 %r125;\n\t"
" .reg .f64 %r126;\n\t"
" .reg .f64 %r127;\n\t"
" .reg .f64 %r128;\n\t"
"mov.f64 %r112, 4.4;\n\t"
"mov.f64 %r113, %r112;\n\t"
"mov.f64 %r114, 2.2;\n\t"
"mov.f64 %r115, 3.3;\n\t"
"mov.f64 %r116, 1.23;\n\t"
"mov.f64 %r117, 2.42;\n\t"
"mov.f64 %r118, 3.34;\n\t"
"mov.f64 %r119, 5.62;\n\t"
"mov.f64 %r120, 2.56;\n\t"
"mov.f64 %r121, 1.56;\n\t"
"mov.f64 %r122, 2.56;\n\t"
"mov.f64 %r123, 5.56;\n\t"
"mov.f64 %r124, 8.56;\n\t"
"mov.f64 %r125, 3.56;\n\t"
"mov.f64 %r126, 5.56;\n\t"
"mov.f64 %r127, 6.56;\n\t"
"mov.f64 %r128, 5.6;\n\t"
);
for (int k = 0; k < n; k++) {
__asm volatile (
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
);
}
}
// __syncthreads();
// if ((blockDim.x * blockIdx.x + threadIdx.x) == 0)
*D = I1;
// __syncthreads();
}
void usage() {
std::cout << "Usage ./binary <num_blocks> <num_threads_per_block> <iterations>" "threads active per warp" << std::endl;
}
int main(int argc, char **argv)
{
if (argc != 5) {
usage();
exit(1);
}
int num_blocks = atoi(argv[1]);
int num_threads_per_block = atoi(argv[2]);
int iterations = atoi(argv[3]);
int divergence = atoi(argv[4]);
// h_A = new float(2.0);
// h_B = new float(3.0);
// h_C = new float(4.0);
// cudaMalloc((void**)&d_A, sizeof(float));
// cudaMalloc((void**)&d_B, sizeof(float));
// cudaMalloc((void**)&d_C, sizeof(float));
hipMalloc((void**)&d_res, sizeof(float));
// cudaMemcpy(d_A, h_A, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_B, h_B, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_C, h_C, sizeof(float), cudaMemcpyHostToDevice);
hipEvent_t start, stop;
float time;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
hipProfilerStart();
// compute<<<num_blocks, num_threads_per_block>>>(d_A, d_B, d_C, d_res, iterations);
compute<<<num_blocks, num_threads_per_block>>>(d_res, iterations, divergence);
hipDeviceSynchronize();
hipProfilerStop();
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
std::cout << "GPU Elapsed Time = " << time << std::endl;
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy(h_res, d_res, sizeof(float), hipMemcpyDeviceToHost);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <iostream>
#include <hip/hip_runtime_api.h>
//#include <cutil.h>
#include <hip/hip_runtime.h>
float* h_A;
float* h_B;
float* h_C;
float* h_res;
float* d_A;
float* d_B;
float* d_C;
float* d_res;
__global__
//void compute(const float* A, const float* B, const float* C, float* D, int n) {
void compute(float* D, int n, int div) {
int tid = blockDim.x * blockIdx.x + threadIdx.x;
float I1 = tid * 2.0;
int thread_id = threadIdx.x % 32;
if (thread_id < div) {
__asm volatile (
" .reg .s32 %r129;\n\t"
" .reg .s32 %r30;\n\t"
" .reg .s32 %r31;\n\t"
" .reg .s32 %r32;\n\t"
" .reg .s32 %r33;\n\t"
" .reg .s32 %r34;\n\t"
" .reg .s32 %r35;\n\t"
" .reg .s32 %r36;\n\t"
" .reg .s32 %r37;\n\t"
" .reg .s32 %r38;\n\t"
" .reg .s32 %r39;\n\t"
" .reg .s32 %r40;\n\t"
" .reg .s32 %r41;\n\t"
" .reg .s32 %r42;\n\t"
" .reg .s32 %r43;\n\t"
" .reg .s32 %r44;\n\t"
" .reg .s32 %r45;\n\t"
" .reg .f64 %r112;\n\t"
" .reg .f64 %r113;\n\t"
" .reg .f64 %r114;\n\t"
" .reg .f64 %r115;\n\t"
" .reg .f64 %r116;\n\t"
" .reg .f64 %r117;\n\t"
" .reg .f64 %r118;\n\t"
" .reg .f64 %r119;\n\t"
" .reg .f64 %r120;\n\t"
" .reg .f64 %r121;\n\t"
" .reg .f64 %r122;\n\t"
" .reg .f64 %r123;\n\t"
" .reg .f64 %r124;\n\t"
" .reg .f64 %r125;\n\t"
" .reg .f64 %r126;\n\t"
" .reg .f64 %r127;\n\t"
" .reg .f64 %r128;\n\t"
"mov.f64 %r112, 4.4;\n\t"
"mov.f64 %r113, %r112;\n\t"
"mov.f64 %r114, 2.2;\n\t"
"mov.f64 %r115, 3.3;\n\t"
"mov.f64 %r116, 1.23;\n\t"
"mov.f64 %r117, 2.42;\n\t"
"mov.f64 %r118, 3.34;\n\t"
"mov.f64 %r119, 5.62;\n\t"
"mov.f64 %r120, 2.56;\n\t"
"mov.f64 %r121, 1.56;\n\t"
"mov.f64 %r122, 2.56;\n\t"
"mov.f64 %r123, 5.56;\n\t"
"mov.f64 %r124, 8.56;\n\t"
"mov.f64 %r125, 3.56;\n\t"
"mov.f64 %r126, 5.56;\n\t"
"mov.f64 %r127, 6.56;\n\t"
"mov.f64 %r128, 5.6;\n\t"
);
for (int k = 0; k < n; k++) {
__asm volatile (
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
);
}
}
// __syncthreads();
// if ((blockDim.x * blockIdx.x + threadIdx.x) == 0)
*D = I1;
// __syncthreads();
}
void usage() {
std::cout << "Usage ./binary <num_blocks> <num_threads_per_block> <iterations>" "threads active per warp" << std::endl;
}
int main(int argc, char **argv)
{
if (argc != 5) {
usage();
exit(1);
}
int num_blocks = atoi(argv[1]);
int num_threads_per_block = atoi(argv[2]);
int iterations = atoi(argv[3]);
int divergence = atoi(argv[4]);
// h_A = new float(2.0);
// h_B = new float(3.0);
// h_C = new float(4.0);
// cudaMalloc((void**)&d_A, sizeof(float));
// cudaMalloc((void**)&d_B, sizeof(float));
// cudaMalloc((void**)&d_C, sizeof(float));
hipMalloc((void**)&d_res, sizeof(float));
// cudaMemcpy(d_A, h_A, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_B, h_B, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_C, h_C, sizeof(float), cudaMemcpyHostToDevice);
hipEvent_t start, stop;
float time;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
hipProfilerStart();
// compute<<<num_blocks, num_threads_per_block>>>(d_A, d_B, d_C, d_res, iterations);
compute<<<num_blocks, num_threads_per_block>>>(d_res, iterations, divergence);
hipDeviceSynchronize();
hipProfilerStop();
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
std::cout << "GPU Elapsed Time = " << time << std::endl;
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy(h_res, d_res, sizeof(float), hipMemcpyDeviceToHost);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7computePfii
.globl _Z7computePfii
.p2align 8
.type _Z7computePfii,@function
_Z7computePfii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0xc
s_load_b32 s2, s[0:1], 0x1c
v_and_b32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b32 s4, s[0:1], 0x8
.reg .s32 %r129
.reg .s32 %r30
.reg .s32 %r31
.reg .s32 %r32
.reg .s32 %r33
.reg .s32 %r34
.reg .s32 %r35
.reg .s32 %r36
.reg .s32 %r37
.reg .s32 %r38
.reg .s32 %r39
.reg .s32 %r40
.reg .s32 %r41
.reg .s32 %r42
.reg .s32 %r43
.reg .s32 %r44
.reg .s32 %r45
.reg .f64 %r112
.reg .f64 %r113
.reg .f64 %r114
.reg .f64 %r115
.reg .f64 %r116
.reg .f64 %r117
.reg .f64 %r118
.reg .f64 %r119
.reg .f64 %r120
.reg .f64 %r121
.reg .f64 %r122
.reg .f64 %r123
.reg .f64 %r124
.reg .f64 %r125
.reg .f64 %r126
.reg .f64 %r127
.reg .f64 %r128
mov.f64 %r112, 4.4
mov.f64 %r113, %r112
mov.f64 %r114, 2.2
mov.f64 %r115, 3.3
mov.f64 %r116, 1.23
mov.f64 %r117, 2.42
mov.f64 %r118, 3.34
mov.f64 %r119, 5.62
mov.f64 %r120, 2.56
mov.f64 %r121, 1.56
mov.f64 %r122, 2.56
mov.f64 %r123, 5.56
mov.f64 %r124, 8.56
mov.f64 %r125, 3.56
mov.f64 %r126, 5.56
mov.f64 %r127, 6.56
mov.f64 %r128, 5.6
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
.LBB0_2:
s_add_i32 s4, s4, -1
cvt.rni.s32.f64 %r30, %r113
cvt.rm.f64.s32 %r113, %r30
cvt.rni.s32.f64 %r31, %r114
cvt.rm.f64.s32 %r114, %r31
cvt.rni.s32.f64 %r32, %r115
cvt.rm.f64.s32 %r115, %r32
cvt.rni.s32.f64 %r33, %r116
cvt.rm.f64.s32 %r116, %r33
cvt.rni.s32.f64 %r34, %r117
cvt.rm.f64.s32 %r117, %r34
cvt.rni.s32.f64 %r35, %r118
cvt.rm.f64.s32 %r118, %r35
cvt.rni.s32.f64 %r36, %r119
cvt.rm.f64.s32 %r119, %r36
cvt.rni.s32.f64 %r37, %r120
cvt.rm.f64.s32 %r120, %r37
cvt.rni.s32.f64 %r38, %r121
cvt.rm.f64.s32 %r121, %r38
cvt.rni.s32.f64 %r39, %r122
cvt.rm.f64.s32 %r122, %r39
cvt.rni.s32.f64 %r40, %r123
cvt.rm.f64.s32 %r123, %r40
cvt.rni.s32.f64 %r41, %r124
cvt.rm.f64.s32 %r124, %r41
cvt.rni.s32.f64 %r42, %r125
cvt.rm.f64.s32 %r125, %r42
cvt.rni.s32.f64 %r43, %r126
cvt.rm.f64.s32 %r126, %r43
cvt.rni.s32.f64 %r44, %r127
cvt.rm.f64.s32 %r127, %r44
cvt.rni.s32.f64 %r45, %r128
cvt.rm.f64.s32 %r128, %r45
cvt.rni.s32.f64 %r30, %r113
cvt.rm.f64.s32 %r113, %r30
cvt.rni.s32.f64 %r31, %r114
cvt.rm.f64.s32 %r114, %r31
cvt.rni.s32.f64 %r32, %r115
cvt.rm.f64.s32 %r115, %r32
cvt.rni.s32.f64 %r33, %r116
cvt.rm.f64.s32 %r116, %r33
cvt.rni.s32.f64 %r34, %r117
cvt.rm.f64.s32 %r117, %r34
cvt.rni.s32.f64 %r35, %r118
cvt.rm.f64.s32 %r118, %r35
cvt.rni.s32.f64 %r36, %r119
cvt.rm.f64.s32 %r119, %r36
cvt.rni.s32.f64 %r37, %r120
cvt.rm.f64.s32 %r120, %r37
cvt.rni.s32.f64 %r38, %r121
cvt.rm.f64.s32 %r121, %r38
cvt.rni.s32.f64 %r39, %r122
cvt.rm.f64.s32 %r122, %r39
cvt.rni.s32.f64 %r40, %r123
cvt.rm.f64.s32 %r123, %r40
cvt.rni.s32.f64 %r41, %r124
cvt.rm.f64.s32 %r124, %r41
cvt.rni.s32.f64 %r42, %r125
cvt.rm.f64.s32 %r125, %r42
cvt.rni.s32.f64 %r43, %r126
cvt.rm.f64.s32 %r126, %r43
cvt.rni.s32.f64 %r44, %r127
cvt.rm.f64.s32 %r127, %r44
cvt.rni.s32.f64 %r45, %r128
cvt.rm.f64.s32 %r128, %r45
cvt.rni.s32.f64 %r30, %r113
cvt.rm.f64.s32 %r113, %r30
cvt.rni.s32.f64 %r31, %r114
cvt.rm.f64.s32 %r114, %r31
cvt.rni.s32.f64 %r32, %r115
cvt.rm.f64.s32 %r115, %r32
cvt.rni.s32.f64 %r33, %r116
cvt.rm.f64.s32 %r116, %r33
cvt.rni.s32.f64 %r34, %r117
cvt.rm.f64.s32 %r117, %r34
cvt.rni.s32.f64 %r35, %r118
cvt.rm.f64.s32 %r118, %r35
cvt.rni.s32.f64 %r36, %r119
cvt.rm.f64.s32 %r119, %r36
cvt.rni.s32.f64 %r37, %r120
cvt.rm.f64.s32 %r120, %r37
cvt.rni.s32.f64 %r38, %r121
cvt.rm.f64.s32 %r121, %r38
cvt.rni.s32.f64 %r39, %r122
cvt.rm.f64.s32 %r122, %r39
cvt.rni.s32.f64 %r40, %r123
cvt.rm.f64.s32 %r123, %r40
cvt.rni.s32.f64 %r41, %r124
cvt.rm.f64.s32 %r124, %r41
cvt.rni.s32.f64 %r42, %r125
cvt.rm.f64.s32 %r125, %r42
cvt.rni.s32.f64 %r43, %r126
cvt.rm.f64.s32 %r126, %r43
cvt.rni.s32.f64 %r44, %r127
cvt.rm.f64.s32 %r127, %r44
cvt.rni.s32.f64 %r45, %r128
cvt.rm.f64.s32 %r128, %r45
cvt.rni.s32.f64 %r30, %r113
cvt.rm.f64.s32 %r113, %r30
cvt.rni.s32.f64 %r31, %r114
cvt.rm.f64.s32 %r114, %r31
cvt.rni.s32.f64 %r32, %r115
cvt.rm.f64.s32 %r115, %r32
cvt.rni.s32.f64 %r33, %r116
cvt.rm.f64.s32 %r116, %r33
cvt.rni.s32.f64 %r34, %r117
cvt.rm.f64.s32 %r117, %r34
cvt.rni.s32.f64 %r35, %r118
cvt.rm.f64.s32 %r118, %r35
cvt.rni.s32.f64 %r36, %r119
cvt.rm.f64.s32 %r119, %r36
cvt.rni.s32.f64 %r37, %r120
cvt.rm.f64.s32 %r120, %r37
cvt.rni.s32.f64 %r38, %r121
cvt.rm.f64.s32 %r121, %r38
cvt.rni.s32.f64 %r39, %r122
cvt.rm.f64.s32 %r122, %r39
cvt.rni.s32.f64 %r40, %r123
cvt.rm.f64.s32 %r123, %r40
cvt.rni.s32.f64 %r41, %r124
cvt.rm.f64.s32 %r124, %r41
cvt.rni.s32.f64 %r42, %r125
cvt.rm.f64.s32 %r125, %r42
cvt.rni.s32.f64 %r43, %r126
cvt.rm.f64.s32 %r126, %r43
cvt.rni.s32.f64 %r44, %r127
cvt.rm.f64.s32 %r127, %r44
cvt.rni.s32.f64 %r45, %r128
cvt.rm.f64.s32 %r128, %r45
cvt.rni.s32.f64 %r30, %r113
cvt.rm.f64.s32 %r113, %r30
cvt.rni.s32.f64 %r31, %r114
cvt.rm.f64.s32 %r114, %r31
cvt.rni.s32.f64 %r32, %r115
cvt.rm.f64.s32 %r115, %r32
cvt.rni.s32.f64 %r33, %r116
cvt.rm.f64.s32 %r116, %r33
cvt.rni.s32.f64 %r34, %r117
cvt.rm.f64.s32 %r117, %r34
cvt.rni.s32.f64 %r35, %r118
cvt.rm.f64.s32 %r118, %r35
cvt.rni.s32.f64 %r36, %r119
cvt.rm.f64.s32 %r119, %r36
cvt.rni.s32.f64 %r37, %r120
cvt.rm.f64.s32 %r120, %r37
cvt.rni.s32.f64 %r38, %r121
cvt.rm.f64.s32 %r121, %r38
cvt.rni.s32.f64 %r39, %r122
cvt.rm.f64.s32 %r122, %r39
cvt.rni.s32.f64 %r40, %r123
cvt.rm.f64.s32 %r123, %r40
cvt.rni.s32.f64 %r41, %r124
cvt.rm.f64.s32 %r124, %r41
cvt.rni.s32.f64 %r42, %r125
cvt.rm.f64.s32 %r125, %r42
cvt.rni.s32.f64 %r43, %r126
cvt.rm.f64.s32 %r126, %r43
cvt.rni.s32.f64 %r44, %r127
cvt.rm.f64.s32 %r127, %r44
cvt.rni.s32.f64 %r45, %r128
cvt.rm.f64.s32 %r128, %r45
cvt.rni.s32.f64 %r30, %r113
cvt.rm.f64.s32 %r113, %r30
cvt.rni.s32.f64 %r31, %r114
cvt.rm.f64.s32 %r114, %r31
cvt.rni.s32.f64 %r32, %r115
cvt.rm.f64.s32 %r115, %r32
cvt.rni.s32.f64 %r33, %r116
cvt.rm.f64.s32 %r116, %r33
cvt.rni.s32.f64 %r34, %r117
cvt.rm.f64.s32 %r117, %r34
cvt.rni.s32.f64 %r35, %r118
cvt.rm.f64.s32 %r118, %r35
cvt.rni.s32.f64 %r36, %r119
cvt.rm.f64.s32 %r119, %r36
cvt.rni.s32.f64 %r37, %r120
cvt.rm.f64.s32 %r120, %r37
cvt.rni.s32.f64 %r38, %r121
cvt.rm.f64.s32 %r121, %r38
cvt.rni.s32.f64 %r39, %r122
cvt.rm.f64.s32 %r122, %r39
cvt.rni.s32.f64 %r40, %r123
cvt.rm.f64.s32 %r123, %r40
cvt.rni.s32.f64 %r41, %r124
cvt.rm.f64.s32 %r124, %r41
cvt.rni.s32.f64 %r42, %r125
cvt.rm.f64.s32 %r125, %r42
cvt.rni.s32.f64 %r43, %r126
cvt.rm.f64.s32 %r126, %r43
cvt.rni.s32.f64 %r44, %r127
cvt.rm.f64.s32 %r127, %r44
cvt.rni.s32.f64 %r45, %r128
cvt.rm.f64.s32 %r128, %r45
cvt.rni.s32.f64 %r30, %r113
cvt.rm.f64.s32 %r113, %r30
cvt.rni.s32.f64 %r31, %r114
cvt.rm.f64.s32 %r114, %r31
cvt.rni.s32.f64 %r32, %r115
cvt.rm.f64.s32 %r115, %r32
cvt.rni.s32.f64 %r33, %r116
cvt.rm.f64.s32 %r116, %r33
cvt.rni.s32.f64 %r34, %r117
cvt.rm.f64.s32 %r117, %r34
cvt.rni.s32.f64 %r35, %r118
cvt.rm.f64.s32 %r118, %r35
cvt.rni.s32.f64 %r36, %r119
cvt.rm.f64.s32 %r119, %r36
cvt.rni.s32.f64 %r37, %r120
cvt.rm.f64.s32 %r120, %r37
cvt.rni.s32.f64 %r38, %r121
cvt.rm.f64.s32 %r121, %r38
cvt.rni.s32.f64 %r39, %r122
cvt.rm.f64.s32 %r122, %r39
cvt.rni.s32.f64 %r40, %r123
cvt.rm.f64.s32 %r123, %r40
cvt.rni.s32.f64 %r41, %r124
cvt.rm.f64.s32 %r124, %r41
cvt.rni.s32.f64 %r42, %r125
cvt.rm.f64.s32 %r125, %r42
cvt.rni.s32.f64 %r43, %r126
cvt.rm.f64.s32 %r126, %r43
cvt.rni.s32.f64 %r44, %r127
cvt.rm.f64.s32 %r127, %r44
cvt.rni.s32.f64 %r45, %r128
cvt.rm.f64.s32 %r128, %r45
cvt.rni.s32.f64 %r30, %r113
cvt.rm.f64.s32 %r113, %r30
cvt.rni.s32.f64 %r31, %r114
cvt.rm.f64.s32 %r114, %r31
cvt.rni.s32.f64 %r32, %r115
cvt.rm.f64.s32 %r115, %r32
cvt.rni.s32.f64 %r33, %r116
cvt.rm.f64.s32 %r116, %r33
cvt.rni.s32.f64 %r34, %r117
cvt.rm.f64.s32 %r117, %r34
cvt.rni.s32.f64 %r35, %r118
cvt.rm.f64.s32 %r118, %r35
cvt.rni.s32.f64 %r36, %r119
cvt.rm.f64.s32 %r119, %r36
cvt.rni.s32.f64 %r37, %r120
cvt.rm.f64.s32 %r120, %r37
cvt.rni.s32.f64 %r38, %r121
cvt.rm.f64.s32 %r121, %r38
cvt.rni.s32.f64 %r39, %r122
cvt.rm.f64.s32 %r122, %r39
cvt.rni.s32.f64 %r40, %r123
cvt.rm.f64.s32 %r123, %r40
cvt.rni.s32.f64 %r41, %r124
cvt.rm.f64.s32 %r124, %r41
cvt.rni.s32.f64 %r42, %r125
cvt.rm.f64.s32 %r125, %r42
cvt.rni.s32.f64 %r43, %r126
cvt.rm.f64.s32 %r126, %r43
cvt.rni.s32.f64 %r44, %r127
cvt.rm.f64.s32 %r127, %r44
cvt.rni.s32.f64 %r45, %r128
cvt.rm.f64.s32 %r128, %r45
s_cmp_lg_u32 s4, 0
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s3
s_and_b32 s2, 0xffff, s2
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_i32_e32 v[0:1], v1
v_add_f64 v[0:1], v[0:1], v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v0, v[0:1]
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7computePfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7computePfii, .Lfunc_end0-_Z7computePfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7computePfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7computePfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <iostream>
#include <hip/hip_runtime_api.h>
//#include <cutil.h>
#include <hip/hip_runtime.h>
float* h_A;
float* h_B;
float* h_C;
float* h_res;
float* d_A;
float* d_B;
float* d_C;
float* d_res;
__global__
//void compute(const float* A, const float* B, const float* C, float* D, int n) {
void compute(float* D, int n, int div) {
int tid = blockDim.x * blockIdx.x + threadIdx.x;
float I1 = tid * 2.0;
int thread_id = threadIdx.x % 32;
if (thread_id < div) {
__asm volatile (
" .reg .s32 %r129;\n\t"
" .reg .s32 %r30;\n\t"
" .reg .s32 %r31;\n\t"
" .reg .s32 %r32;\n\t"
" .reg .s32 %r33;\n\t"
" .reg .s32 %r34;\n\t"
" .reg .s32 %r35;\n\t"
" .reg .s32 %r36;\n\t"
" .reg .s32 %r37;\n\t"
" .reg .s32 %r38;\n\t"
" .reg .s32 %r39;\n\t"
" .reg .s32 %r40;\n\t"
" .reg .s32 %r41;\n\t"
" .reg .s32 %r42;\n\t"
" .reg .s32 %r43;\n\t"
" .reg .s32 %r44;\n\t"
" .reg .s32 %r45;\n\t"
" .reg .f64 %r112;\n\t"
" .reg .f64 %r113;\n\t"
" .reg .f64 %r114;\n\t"
" .reg .f64 %r115;\n\t"
" .reg .f64 %r116;\n\t"
" .reg .f64 %r117;\n\t"
" .reg .f64 %r118;\n\t"
" .reg .f64 %r119;\n\t"
" .reg .f64 %r120;\n\t"
" .reg .f64 %r121;\n\t"
" .reg .f64 %r122;\n\t"
" .reg .f64 %r123;\n\t"
" .reg .f64 %r124;\n\t"
" .reg .f64 %r125;\n\t"
" .reg .f64 %r126;\n\t"
" .reg .f64 %r127;\n\t"
" .reg .f64 %r128;\n\t"
"mov.f64 %r112, 4.4;\n\t"
"mov.f64 %r113, %r112;\n\t"
"mov.f64 %r114, 2.2;\n\t"
"mov.f64 %r115, 3.3;\n\t"
"mov.f64 %r116, 1.23;\n\t"
"mov.f64 %r117, 2.42;\n\t"
"mov.f64 %r118, 3.34;\n\t"
"mov.f64 %r119, 5.62;\n\t"
"mov.f64 %r120, 2.56;\n\t"
"mov.f64 %r121, 1.56;\n\t"
"mov.f64 %r122, 2.56;\n\t"
"mov.f64 %r123, 5.56;\n\t"
"mov.f64 %r124, 8.56;\n\t"
"mov.f64 %r125, 3.56;\n\t"
"mov.f64 %r126, 5.56;\n\t"
"mov.f64 %r127, 6.56;\n\t"
"mov.f64 %r128, 5.6;\n\t"
);
for (int k = 0; k < n; k++) {
__asm volatile (
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
"cvt.rni.s32.f64 %r30, %r113;\n\t"
"cvt.rm.f64.s32 %r113, %r30;\n\t"
"cvt.rni.s32.f64 %r31, %r114;\n\t"
"cvt.rm.f64.s32 %r114, %r31;\n\t"
"cvt.rni.s32.f64 %r32, %r115;\n\t"
"cvt.rm.f64.s32 %r115, %r32;\n\t"
"cvt.rni.s32.f64 %r33, %r116;\n\t"
"cvt.rm.f64.s32 %r116, %r33;\n\t"
"cvt.rni.s32.f64 %r34, %r117;\n\t"
"cvt.rm.f64.s32 %r117, %r34;\n\t"
"cvt.rni.s32.f64 %r35, %r118;\n\t"
"cvt.rm.f64.s32 %r118, %r35;\n\t"
"cvt.rni.s32.f64 %r36, %r119;\n\t"
"cvt.rm.f64.s32 %r119, %r36;\n\t"
"cvt.rni.s32.f64 %r37, %r120;\n\t"
"cvt.rm.f64.s32 %r120, %r37;\n\t"
"cvt.rni.s32.f64 %r38, %r121;\n\t"
"cvt.rm.f64.s32 %r121, %r38;\n\t"
"cvt.rni.s32.f64 %r39, %r122;\n\t"
"cvt.rm.f64.s32 %r122, %r39;\n\t"
"cvt.rni.s32.f64 %r40, %r123;\n\t"
"cvt.rm.f64.s32 %r123, %r40;\n\t"
"cvt.rni.s32.f64 %r41, %r124;\n\t"
"cvt.rm.f64.s32 %r124, %r41;\n\t"
"cvt.rni.s32.f64 %r42, %r125;\n\t"
"cvt.rm.f64.s32 %r125, %r42;\n\t"
"cvt.rni.s32.f64 %r43, %r126;\n\t"
"cvt.rm.f64.s32 %r126, %r43;\n\t"
"cvt.rni.s32.f64 %r44, %r127;\n\t"
"cvt.rm.f64.s32 %r127, %r44;\n\t"
"cvt.rni.s32.f64 %r45, %r128;\n\t"
"cvt.rm.f64.s32 %r128, %r45;\n\t"
);
}
}
// __syncthreads();
// if ((blockDim.x * blockIdx.x + threadIdx.x) == 0)
*D = I1;
// __syncthreads();
}
void usage() {
std::cout << "Usage ./binary <num_blocks> <num_threads_per_block> <iterations>" "threads active per warp" << std::endl;
}
int main(int argc, char **argv)
{
if (argc != 5) {
usage();
exit(1);
}
int num_blocks = atoi(argv[1]);
int num_threads_per_block = atoi(argv[2]);
int iterations = atoi(argv[3]);
int divergence = atoi(argv[4]);
// h_A = new float(2.0);
// h_B = new float(3.0);
// h_C = new float(4.0);
// cudaMalloc((void**)&d_A, sizeof(float));
// cudaMalloc((void**)&d_B, sizeof(float));
// cudaMalloc((void**)&d_C, sizeof(float));
hipMalloc((void**)&d_res, sizeof(float));
// cudaMemcpy(d_A, h_A, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_B, h_B, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_C, h_C, sizeof(float), cudaMemcpyHostToDevice);
hipEvent_t start, stop;
float time;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
hipProfilerStart();
// compute<<<num_blocks, num_threads_per_block>>>(d_A, d_B, d_C, d_res, iterations);
compute<<<num_blocks, num_threads_per_block>>>(d_res, iterations, divergence);
hipDeviceSynchronize();
hipProfilerStop();
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
std::cout << "GPU Elapsed Time = " << time << std::endl;
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy(h_res, d_res, sizeof(float), hipMemcpyDeviceToHost);
return 0;
} | .text
.file "cvt_32p_asm.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__computePfii # -- Begin function _Z22__device_stub__computePfii
.p2align 4, 0x90
.type _Z22__device_stub__computePfii,@function
_Z22__device_stub__computePfii: # @_Z22__device_stub__computePfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7computePfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__computePfii, .Lfunc_end0-_Z22__device_stub__computePfii
.cfi_endproc
# -- End function
.globl _Z5usagev # -- Begin function _Z5usagev
.p2align 4, 0x90
.type _Z5usagev,@function
_Z5usagev: # @_Z5usagev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $87, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_5
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB1_5:
.cfi_def_cfa_offset 16
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z5usagev, .Lfunc_end1-_Z5usagev
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $5, %edi
jne .LBB2_8
# %bb.1:
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 24(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 32(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movl $d_res, %edi
movl $4, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
callq hipProfilerStart
movl %r15d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r12d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_3
# %bb.2:
movq d_res(%rip), %rax
movq %rax, 112(%rsp)
movl %ebx, 28(%rsp)
movl %r14d, 24(%rsp)
leaq 112(%rsp), %rax
movq %rax, 32(%rsp)
leaq 28(%rsp), %rax
movq %rax, 40(%rsp)
leaq 24(%rsp), %rax
movq %rax, 48(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z7computePfii, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_3:
callq hipDeviceSynchronize
callq hipProfilerStop
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_9
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_6
# %bb.5:
movzbl 67(%rbx), %ecx
jmp .LBB2_7
.LBB2_6:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq h_res(%rip), %rdi
movq d_res(%rip), %rsi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_8:
.cfi_def_cfa_offset 160
callq _Z5usagev
movl $1, %edi
callq exit
.LBB2_9:
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computePfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type h_A,@object # @h_A
.bss
.globl h_A
.p2align 3, 0x0
h_A:
.quad 0
.size h_A, 8
.type h_B,@object # @h_B
.globl h_B
.p2align 3, 0x0
h_B:
.quad 0
.size h_B, 8
.type h_C,@object # @h_C
.globl h_C
.p2align 3, 0x0
h_C:
.quad 0
.size h_C, 8
.type h_res,@object # @h_res
.globl h_res
.p2align 3, 0x0
h_res:
.quad 0
.size h_res, 8
.type d_A,@object # @d_A
.globl d_A
.p2align 3, 0x0
d_A:
.quad 0
.size d_A, 8
.type d_B,@object # @d_B
.globl d_B
.p2align 3, 0x0
d_B:
.quad 0
.size d_B, 8
.type d_C,@object # @d_C
.globl d_C
.p2align 3, 0x0
d_C:
.quad 0
.size d_C, 8
.type d_res,@object # @d_res
.globl d_res
.p2align 3, 0x0
d_res:
.quad 0
.size d_res, 8
.type _Z7computePfii,@object # @_Z7computePfii
.section .rodata,"a",@progbits
.globl _Z7computePfii
.p2align 3, 0x0
_Z7computePfii:
.quad _Z22__device_stub__computePfii
.size _Z7computePfii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage ./binary <num_blocks> <num_threads_per_block> <iterations>threads active per warp"
.size .L.str, 88
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU Elapsed Time = "
.size .L.str.1, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7computePfii"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computePfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_res
.addrsig_sym _Z7computePfii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7computePfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0060*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0200 */
/*0070*/ I2F.F64 R2, R0 ; /* 0x0000000000027312 */
/* 0x000e240000201c00 */
/*0080*/ DADD R2, R2, R2 ; /* 0x0000000002027229 */
/* 0x001e140000000002 */
/*0090*/ F2F.F32.F64 R3, R2 ; /* 0x0000000200037310 */
/* 0x001e240000301000 */
/*00a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x001fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7computePfii
.globl _Z7computePfii
.p2align 8
.type _Z7computePfii,@function
_Z7computePfii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0xc
s_load_b32 s2, s[0:1], 0x1c
v_and_b32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b32 s4, s[0:1], 0x8
.reg .s32 %r129
.reg .s32 %r30
.reg .s32 %r31
.reg .s32 %r32
.reg .s32 %r33
.reg .s32 %r34
.reg .s32 %r35
.reg .s32 %r36
.reg .s32 %r37
.reg .s32 %r38
.reg .s32 %r39
.reg .s32 %r40
.reg .s32 %r41
.reg .s32 %r42
.reg .s32 %r43
.reg .s32 %r44
.reg .s32 %r45
.reg .f64 %r112
.reg .f64 %r113
.reg .f64 %r114
.reg .f64 %r115
.reg .f64 %r116
.reg .f64 %r117
.reg .f64 %r118
.reg .f64 %r119
.reg .f64 %r120
.reg .f64 %r121
.reg .f64 %r122
.reg .f64 %r123
.reg .f64 %r124
.reg .f64 %r125
.reg .f64 %r126
.reg .f64 %r127
.reg .f64 %r128
mov.f64 %r112, 4.4
mov.f64 %r113, %r112
mov.f64 %r114, 2.2
mov.f64 %r115, 3.3
mov.f64 %r116, 1.23
mov.f64 %r117, 2.42
mov.f64 %r118, 3.34
mov.f64 %r119, 5.62
mov.f64 %r120, 2.56
mov.f64 %r121, 1.56
mov.f64 %r122, 2.56
mov.f64 %r123, 5.56
mov.f64 %r124, 8.56
mov.f64 %r125, 3.56
mov.f64 %r126, 5.56
mov.f64 %r127, 6.56
mov.f64 %r128, 5.6
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
.LBB0_2:
s_add_i32 s4, s4, -1
cvt.rni.s32.f64 %r30, %r113
cvt.rm.f64.s32 %r113, %r30
cvt.rni.s32.f64 %r31, %r114
cvt.rm.f64.s32 %r114, %r31
cvt.rni.s32.f64 %r32, %r115
cvt.rm.f64.s32 %r115, %r32
cvt.rni.s32.f64 %r33, %r116
cvt.rm.f64.s32 %r116, %r33
cvt.rni.s32.f64 %r34, %r117
cvt.rm.f64.s32 %r117, %r34
cvt.rni.s32.f64 %r35, %r118
cvt.rm.f64.s32 %r118, %r35
cvt.rni.s32.f64 %r36, %r119
cvt.rm.f64.s32 %r119, %r36
cvt.rni.s32.f64 %r37, %r120
cvt.rm.f64.s32 %r120, %r37
cvt.rni.s32.f64 %r38, %r121
cvt.rm.f64.s32 %r121, %r38
cvt.rni.s32.f64 %r39, %r122
cvt.rm.f64.s32 %r122, %r39
cvt.rni.s32.f64 %r40, %r123
cvt.rm.f64.s32 %r123, %r40
cvt.rni.s32.f64 %r41, %r124
cvt.rm.f64.s32 %r124, %r41
cvt.rni.s32.f64 %r42, %r125
cvt.rm.f64.s32 %r125, %r42
cvt.rni.s32.f64 %r43, %r126
cvt.rm.f64.s32 %r126, %r43
cvt.rni.s32.f64 %r44, %r127
cvt.rm.f64.s32 %r127, %r44
cvt.rni.s32.f64 %r45, %r128
cvt.rm.f64.s32 %r128, %r45
cvt.rni.s32.f64 %r30, %r113
cvt.rm.f64.s32 %r113, %r30
cvt.rni.s32.f64 %r31, %r114
cvt.rm.f64.s32 %r114, %r31
cvt.rni.s32.f64 %r32, %r115
cvt.rm.f64.s32 %r115, %r32
cvt.rni.s32.f64 %r33, %r116
cvt.rm.f64.s32 %r116, %r33
cvt.rni.s32.f64 %r34, %r117
cvt.rm.f64.s32 %r117, %r34
cvt.rni.s32.f64 %r35, %r118
cvt.rm.f64.s32 %r118, %r35
cvt.rni.s32.f64 %r36, %r119
cvt.rm.f64.s32 %r119, %r36
cvt.rni.s32.f64 %r37, %r120
cvt.rm.f64.s32 %r120, %r37
cvt.rni.s32.f64 %r38, %r121
cvt.rm.f64.s32 %r121, %r38
cvt.rni.s32.f64 %r39, %r122
cvt.rm.f64.s32 %r122, %r39
cvt.rni.s32.f64 %r40, %r123
cvt.rm.f64.s32 %r123, %r40
cvt.rni.s32.f64 %r41, %r124
cvt.rm.f64.s32 %r124, %r41
cvt.rni.s32.f64 %r42, %r125
cvt.rm.f64.s32 %r125, %r42
cvt.rni.s32.f64 %r43, %r126
cvt.rm.f64.s32 %r126, %r43
cvt.rni.s32.f64 %r44, %r127
cvt.rm.f64.s32 %r127, %r44
cvt.rni.s32.f64 %r45, %r128
cvt.rm.f64.s32 %r128, %r45
cvt.rni.s32.f64 %r30, %r113
cvt.rm.f64.s32 %r113, %r30
cvt.rni.s32.f64 %r31, %r114
cvt.rm.f64.s32 %r114, %r31
cvt.rni.s32.f64 %r32, %r115
cvt.rm.f64.s32 %r115, %r32
cvt.rni.s32.f64 %r33, %r116
cvt.rm.f64.s32 %r116, %r33
cvt.rni.s32.f64 %r34, %r117
cvt.rm.f64.s32 %r117, %r34
cvt.rni.s32.f64 %r35, %r118
cvt.rm.f64.s32 %r118, %r35
cvt.rni.s32.f64 %r36, %r119
cvt.rm.f64.s32 %r119, %r36
cvt.rni.s32.f64 %r37, %r120
cvt.rm.f64.s32 %r120, %r37
cvt.rni.s32.f64 %r38, %r121
cvt.rm.f64.s32 %r121, %r38
cvt.rni.s32.f64 %r39, %r122
cvt.rm.f64.s32 %r122, %r39
cvt.rni.s32.f64 %r40, %r123
cvt.rm.f64.s32 %r123, %r40
cvt.rni.s32.f64 %r41, %r124
cvt.rm.f64.s32 %r124, %r41
cvt.rni.s32.f64 %r42, %r125
cvt.rm.f64.s32 %r125, %r42
cvt.rni.s32.f64 %r43, %r126
cvt.rm.f64.s32 %r126, %r43
cvt.rni.s32.f64 %r44, %r127
cvt.rm.f64.s32 %r127, %r44
cvt.rni.s32.f64 %r45, %r128
cvt.rm.f64.s32 %r128, %r45
cvt.rni.s32.f64 %r30, %r113
cvt.rm.f64.s32 %r113, %r30
cvt.rni.s32.f64 %r31, %r114
cvt.rm.f64.s32 %r114, %r31
cvt.rni.s32.f64 %r32, %r115
cvt.rm.f64.s32 %r115, %r32
cvt.rni.s32.f64 %r33, %r116
cvt.rm.f64.s32 %r116, %r33
cvt.rni.s32.f64 %r34, %r117
cvt.rm.f64.s32 %r117, %r34
cvt.rni.s32.f64 %r35, %r118
cvt.rm.f64.s32 %r118, %r35
cvt.rni.s32.f64 %r36, %r119
cvt.rm.f64.s32 %r119, %r36
cvt.rni.s32.f64 %r37, %r120
cvt.rm.f64.s32 %r120, %r37
cvt.rni.s32.f64 %r38, %r121
cvt.rm.f64.s32 %r121, %r38
cvt.rni.s32.f64 %r39, %r122
cvt.rm.f64.s32 %r122, %r39
cvt.rni.s32.f64 %r40, %r123
cvt.rm.f64.s32 %r123, %r40
cvt.rni.s32.f64 %r41, %r124
cvt.rm.f64.s32 %r124, %r41
cvt.rni.s32.f64 %r42, %r125
cvt.rm.f64.s32 %r125, %r42
cvt.rni.s32.f64 %r43, %r126
cvt.rm.f64.s32 %r126, %r43
cvt.rni.s32.f64 %r44, %r127
cvt.rm.f64.s32 %r127, %r44
cvt.rni.s32.f64 %r45, %r128
cvt.rm.f64.s32 %r128, %r45
cvt.rni.s32.f64 %r30, %r113
cvt.rm.f64.s32 %r113, %r30
cvt.rni.s32.f64 %r31, %r114
cvt.rm.f64.s32 %r114, %r31
cvt.rni.s32.f64 %r32, %r115
cvt.rm.f64.s32 %r115, %r32
cvt.rni.s32.f64 %r33, %r116
cvt.rm.f64.s32 %r116, %r33
cvt.rni.s32.f64 %r34, %r117
cvt.rm.f64.s32 %r117, %r34
cvt.rni.s32.f64 %r35, %r118
cvt.rm.f64.s32 %r118, %r35
cvt.rni.s32.f64 %r36, %r119
cvt.rm.f64.s32 %r119, %r36
cvt.rni.s32.f64 %r37, %r120
cvt.rm.f64.s32 %r120, %r37
cvt.rni.s32.f64 %r38, %r121
cvt.rm.f64.s32 %r121, %r38
cvt.rni.s32.f64 %r39, %r122
cvt.rm.f64.s32 %r122, %r39
cvt.rni.s32.f64 %r40, %r123
cvt.rm.f64.s32 %r123, %r40
cvt.rni.s32.f64 %r41, %r124
cvt.rm.f64.s32 %r124, %r41
cvt.rni.s32.f64 %r42, %r125
cvt.rm.f64.s32 %r125, %r42
cvt.rni.s32.f64 %r43, %r126
cvt.rm.f64.s32 %r126, %r43
cvt.rni.s32.f64 %r44, %r127
cvt.rm.f64.s32 %r127, %r44
cvt.rni.s32.f64 %r45, %r128
cvt.rm.f64.s32 %r128, %r45
cvt.rni.s32.f64 %r30, %r113
cvt.rm.f64.s32 %r113, %r30
cvt.rni.s32.f64 %r31, %r114
cvt.rm.f64.s32 %r114, %r31
cvt.rni.s32.f64 %r32, %r115
cvt.rm.f64.s32 %r115, %r32
cvt.rni.s32.f64 %r33, %r116
cvt.rm.f64.s32 %r116, %r33
cvt.rni.s32.f64 %r34, %r117
cvt.rm.f64.s32 %r117, %r34
cvt.rni.s32.f64 %r35, %r118
cvt.rm.f64.s32 %r118, %r35
cvt.rni.s32.f64 %r36, %r119
cvt.rm.f64.s32 %r119, %r36
cvt.rni.s32.f64 %r37, %r120
cvt.rm.f64.s32 %r120, %r37
cvt.rni.s32.f64 %r38, %r121
cvt.rm.f64.s32 %r121, %r38
cvt.rni.s32.f64 %r39, %r122
cvt.rm.f64.s32 %r122, %r39
cvt.rni.s32.f64 %r40, %r123
cvt.rm.f64.s32 %r123, %r40
cvt.rni.s32.f64 %r41, %r124
cvt.rm.f64.s32 %r124, %r41
cvt.rni.s32.f64 %r42, %r125
cvt.rm.f64.s32 %r125, %r42
cvt.rni.s32.f64 %r43, %r126
cvt.rm.f64.s32 %r126, %r43
cvt.rni.s32.f64 %r44, %r127
cvt.rm.f64.s32 %r127, %r44
cvt.rni.s32.f64 %r45, %r128
cvt.rm.f64.s32 %r128, %r45
cvt.rni.s32.f64 %r30, %r113
cvt.rm.f64.s32 %r113, %r30
cvt.rni.s32.f64 %r31, %r114
cvt.rm.f64.s32 %r114, %r31
cvt.rni.s32.f64 %r32, %r115
cvt.rm.f64.s32 %r115, %r32
cvt.rni.s32.f64 %r33, %r116
cvt.rm.f64.s32 %r116, %r33
cvt.rni.s32.f64 %r34, %r117
cvt.rm.f64.s32 %r117, %r34
cvt.rni.s32.f64 %r35, %r118
cvt.rm.f64.s32 %r118, %r35
cvt.rni.s32.f64 %r36, %r119
cvt.rm.f64.s32 %r119, %r36
cvt.rni.s32.f64 %r37, %r120
cvt.rm.f64.s32 %r120, %r37
cvt.rni.s32.f64 %r38, %r121
cvt.rm.f64.s32 %r121, %r38
cvt.rni.s32.f64 %r39, %r122
cvt.rm.f64.s32 %r122, %r39
cvt.rni.s32.f64 %r40, %r123
cvt.rm.f64.s32 %r123, %r40
cvt.rni.s32.f64 %r41, %r124
cvt.rm.f64.s32 %r124, %r41
cvt.rni.s32.f64 %r42, %r125
cvt.rm.f64.s32 %r125, %r42
cvt.rni.s32.f64 %r43, %r126
cvt.rm.f64.s32 %r126, %r43
cvt.rni.s32.f64 %r44, %r127
cvt.rm.f64.s32 %r127, %r44
cvt.rni.s32.f64 %r45, %r128
cvt.rm.f64.s32 %r128, %r45
cvt.rni.s32.f64 %r30, %r113
cvt.rm.f64.s32 %r113, %r30
cvt.rni.s32.f64 %r31, %r114
cvt.rm.f64.s32 %r114, %r31
cvt.rni.s32.f64 %r32, %r115
cvt.rm.f64.s32 %r115, %r32
cvt.rni.s32.f64 %r33, %r116
cvt.rm.f64.s32 %r116, %r33
cvt.rni.s32.f64 %r34, %r117
cvt.rm.f64.s32 %r117, %r34
cvt.rni.s32.f64 %r35, %r118
cvt.rm.f64.s32 %r118, %r35
cvt.rni.s32.f64 %r36, %r119
cvt.rm.f64.s32 %r119, %r36
cvt.rni.s32.f64 %r37, %r120
cvt.rm.f64.s32 %r120, %r37
cvt.rni.s32.f64 %r38, %r121
cvt.rm.f64.s32 %r121, %r38
cvt.rni.s32.f64 %r39, %r122
cvt.rm.f64.s32 %r122, %r39
cvt.rni.s32.f64 %r40, %r123
cvt.rm.f64.s32 %r123, %r40
cvt.rni.s32.f64 %r41, %r124
cvt.rm.f64.s32 %r124, %r41
cvt.rni.s32.f64 %r42, %r125
cvt.rm.f64.s32 %r125, %r42
cvt.rni.s32.f64 %r43, %r126
cvt.rm.f64.s32 %r126, %r43
cvt.rni.s32.f64 %r44, %r127
cvt.rm.f64.s32 %r127, %r44
cvt.rni.s32.f64 %r45, %r128
cvt.rm.f64.s32 %r128, %r45
s_cmp_lg_u32 s4, 0
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s3
s_and_b32 s2, 0xffff, s2
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_i32_e32 v[0:1], v1
v_add_f64 v[0:1], v[0:1], v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v0, v[0:1]
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7computePfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7computePfii, .Lfunc_end0-_Z7computePfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7computePfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7computePfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000870de_00000000-6_cvt_32p_asm.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Usage ./binary <num_blocks> <num_threads_per_block> <iterations>threads active per warp"
.text
.globl _Z5usagev
.type _Z5usagev, @function
_Z5usagev:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl $87, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L8
cmpb $0, 56(%rbx)
je .L5
movzbl 67(%rbx), %esi
.L6:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L5:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L6
.cfi_endproc
.LFE3669:
.size _Z5usagev, .-_Z5usagev
.globl _Z28__device_stub__Z7computePfiiPfii
.type _Z28__device_stub__Z7computePfiiPfii, @function
_Z28__device_stub__Z7computePfiiPfii:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7computePfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z28__device_stub__Z7computePfiiPfii, .-_Z28__device_stub__Z7computePfiiPfii
.globl _Z7computePfii
.type _Z7computePfii, @function
_Z7computePfii:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7computePfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z7computePfii, .-_Z7computePfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "GPU Elapsed Time = "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $5, %edi
jne .L22
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl $4, %esi
leaq d_res(%rip), %rdi
call cudaMalloc@PLT
movq %rsp, %rdi
call cudaEventCreate@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
call cudaProfilerStart@PLT
movl %r12d, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %ebp, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
call cudaDeviceSynchronize@PLT
call cudaProfilerStop@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movq 8(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 28(%rsp), %rdi
movq 8(%rsp), %rdx
movq (%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq (%rsp), %rdi
call cudaEventDestroy@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
movl $2, %ecx
movl $4, %edx
movq d_res(%rip), %rsi
movq h_res(%rip), %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call _Z5usagev
movl $1, %edi
call exit@PLT
.L23:
movl %ebx, %edx
movl %r13d, %esi
movq d_res(%rip), %rdi
call _Z28__device_stub__Z7computePfiiPfii
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z7computePfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computePfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl d_res
.bss
.align 8
.type d_res, @object
.size d_res, 8
d_res:
.zero 8
.globl d_C
.align 8
.type d_C, @object
.size d_C, 8
d_C:
.zero 8
.globl d_B
.align 8
.type d_B, @object
.size d_B, 8
d_B:
.zero 8
.globl d_A
.align 8
.type d_A, @object
.size d_A, 8
d_A:
.zero 8
.globl h_res
.align 8
.type h_res, @object
.size h_res, 8
h_res:
.zero 8
.globl h_C
.align 8
.type h_C, @object
.size h_C, 8
h_C:
.zero 8
.globl h_B
.align 8
.type h_B, @object
.size h_B, 8
h_B:
.zero 8
.globl h_A
.align 8
.type h_A, @object
.size h_A, 8
h_A:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cvt_32p_asm.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__computePfii # -- Begin function _Z22__device_stub__computePfii
.p2align 4, 0x90
.type _Z22__device_stub__computePfii,@function
_Z22__device_stub__computePfii: # @_Z22__device_stub__computePfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7computePfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__computePfii, .Lfunc_end0-_Z22__device_stub__computePfii
.cfi_endproc
# -- End function
.globl _Z5usagev # -- Begin function _Z5usagev
.p2align 4, 0x90
.type _Z5usagev,@function
_Z5usagev: # @_Z5usagev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $87, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_5
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB1_5:
.cfi_def_cfa_offset 16
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z5usagev, .Lfunc_end1-_Z5usagev
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $5, %edi
jne .LBB2_8
# %bb.1:
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 24(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 32(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movl $d_res, %edi
movl $4, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
callq hipProfilerStart
movl %r15d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r12d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_3
# %bb.2:
movq d_res(%rip), %rax
movq %rax, 112(%rsp)
movl %ebx, 28(%rsp)
movl %r14d, 24(%rsp)
leaq 112(%rsp), %rax
movq %rax, 32(%rsp)
leaq 28(%rsp), %rax
movq %rax, 40(%rsp)
leaq 24(%rsp), %rax
movq %rax, 48(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z7computePfii, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_3:
callq hipDeviceSynchronize
callq hipProfilerStop
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_9
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_6
# %bb.5:
movzbl 67(%rbx), %ecx
jmp .LBB2_7
.LBB2_6:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq h_res(%rip), %rdi
movq d_res(%rip), %rsi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_8:
.cfi_def_cfa_offset 160
callq _Z5usagev
movl $1, %edi
callq exit
.LBB2_9:
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computePfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type h_A,@object # @h_A
.bss
.globl h_A
.p2align 3, 0x0
h_A:
.quad 0
.size h_A, 8
.type h_B,@object # @h_B
.globl h_B
.p2align 3, 0x0
h_B:
.quad 0
.size h_B, 8
.type h_C,@object # @h_C
.globl h_C
.p2align 3, 0x0
h_C:
.quad 0
.size h_C, 8
.type h_res,@object # @h_res
.globl h_res
.p2align 3, 0x0
h_res:
.quad 0
.size h_res, 8
.type d_A,@object # @d_A
.globl d_A
.p2align 3, 0x0
d_A:
.quad 0
.size d_A, 8
.type d_B,@object # @d_B
.globl d_B
.p2align 3, 0x0
d_B:
.quad 0
.size d_B, 8
.type d_C,@object # @d_C
.globl d_C
.p2align 3, 0x0
d_C:
.quad 0
.size d_C, 8
.type d_res,@object # @d_res
.globl d_res
.p2align 3, 0x0
d_res:
.quad 0
.size d_res, 8
.type _Z7computePfii,@object # @_Z7computePfii
.section .rodata,"a",@progbits
.globl _Z7computePfii
.p2align 3, 0x0
_Z7computePfii:
.quad _Z22__device_stub__computePfii
.size _Z7computePfii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage ./binary <num_blocks> <num_threads_per_block> <iterations>threads active per warp"
.size .L.str, 88
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU Elapsed Time = "
.size .L.str.1, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7computePfii"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computePfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_res
.addrsig_sym _Z7computePfii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
__global__ void print_from_gpu(void) {
printf(
"Hello World from device!\n\
threadIdx.x: %d\n\
threadIdx.y: %d\n\
blockIdx.x: %d\n\
blockIdx.y: %d\n\
blockDim.x: %d\n\
blockDim.y: %d\n",
threadIdx.x, threadIdx.y, blockIdx.x, blockIdx.y, blockDim.x, blockDim.y);
}
int main(void) {
printf("Hello World from host!\n");
dim3 DimGrid(2, 2);
dim3 DimBlock(3, 2);
print_from_gpu<<<DimGrid, DimBlock>>>();
cudaDeviceSynchronize();
printf("Can this be ahead of kernel?\n");
printf("Dim change\n");
DimGrid.x = 2; DimGrid.y = 1;
DimBlock.x = 2; DimBlock.y = 3;
print_from_gpu<<<DimGrid, DimBlock>>>();
cudaDeviceSynchronize();
printf("sizeof(double): %d", sizeof(double));
return 0;
} | code for sm_80
Function : _Z14print_from_gpuv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002200 */
/*0020*/ IADD3 R1, R1, -0x18, RZ ; /* 0xffffffe801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0c7624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff0d7624 */
/* 0x000fe200078e00ff */
/*0070*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0080*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a20000000a00 */
/*0090*/ S2R R11, SR_CTAID.Y ; /* 0x00000000000b7919 */
/* 0x000ee20000002600 */
/*00a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*00c0*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000ee20000002500 */
/*00d0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fc600000e06ff */
/*00e0*/ STL.64 [R1+0x10], R12 ; /* 0x0000100c01007387 */
/* 0x0003e80000100a00 */
/*00f0*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100a00 */
/*0100*/ STL.64 [R1+0x8], R10 ; /* 0x0000080a01007387 */
/* 0x0083e40000100a00 */
/*0110*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x006fe40000000000 */
/*0120*/ MOV R11, 0x190 ; /* 0x00000190000b7802 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R20, 0x110 ; /* 0x0000011000147802 */
/* 0x000fc40000000f00 */
/*0140*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0150*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0160*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0170*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0180*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
__global__ void print_from_gpu(void) {
printf(
"Hello World from device!\n\
threadIdx.x: %d\n\
threadIdx.y: %d\n\
blockIdx.x: %d\n\
blockIdx.y: %d\n\
blockDim.x: %d\n\
blockDim.y: %d\n",
threadIdx.x, threadIdx.y, blockIdx.x, blockIdx.y, blockDim.x, blockDim.y);
}
int main(void) {
printf("Hello World from host!\n");
dim3 DimGrid(2, 2);
dim3 DimBlock(3, 2);
print_from_gpu<<<DimGrid, DimBlock>>>();
cudaDeviceSynchronize();
printf("Can this be ahead of kernel?\n");
printf("Dim change\n");
DimGrid.x = 2; DimGrid.y = 1;
DimBlock.x = 2; DimBlock.y = 3;
print_from_gpu<<<DimGrid, DimBlock>>>();
cudaDeviceSynchronize();
printf("sizeof(double): %d", sizeof(double));
return 0;
} | .file "tmpxft_0014f764_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z14print_from_gpuvv
.type _Z33__device_stub__Z14print_from_gpuvv, @function
_Z33__device_stub__Z14print_from_gpuvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z14print_from_gpuv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z14print_from_gpuvv, .-_Z33__device_stub__Z14print_from_gpuvv
.globl _Z14print_from_gpuv
.type _Z14print_from_gpuv, @function
_Z14print_from_gpuv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z14print_from_gpuvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14print_from_gpuv, .-_Z14print_from_gpuv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World from host!\n"
.LC1:
.string "Can this be ahead of kernel?\n"
.LC2:
.string "Dim change\n"
.LC3:
.string "sizeof(double): %d"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, 8(%rsp)
movl $2, 12(%rsp)
movl $1, 16(%rsp)
movl $3, 20(%rsp)
movl $2, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaDeviceSynchronize@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 12(%rsp)
movl $2, 20(%rsp)
movl $3, 24(%rsp)
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl 16(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L13:
call cudaDeviceSynchronize@PLT
movl $8, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call _Z33__device_stub__Z14print_from_gpuvv
jmp .L12
.L16:
call _Z33__device_stub__Z14print_from_gpuvv
jmp .L13
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z14print_from_gpuv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z14print_from_gpuv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
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