system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
__global__ void print_from_gpu(void) {
printf(
"Hello World from device!\n\
threadIdx.x: %d\n\
threadIdx.y: %d\n\
blockIdx.x: %d\n\
blockIdx.y: %d\n\
blockDim.x: %d\n\
blockDim.y: %d\n",
threadIdx.x, threadIdx.y, blockIdx.x, blockIdx.y, blockDim.x, blockDim.y);
}
int main(void) {
printf("Hello World from host!\n");
dim3 DimGrid(2, 2);
dim3 DimBlock(3, 2);
print_from_gpu<<<DimGrid, DimBlock>>>();
cudaDeviceSynchronize();
printf("Can this be ahead of kernel?\n");
printf("Dim change\n");
DimGrid.x = 2; DimGrid.y = 1;
DimBlock.x = 2; DimBlock.y = 3;
print_from_gpu<<<DimGrid, DimBlock>>>();
cudaDeviceSynchronize();
printf("sizeof(double): %d", sizeof(double));
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void print_from_gpu(void) {
printf(
"Hello World from device!\n\
threadIdx.x: %d\n\
threadIdx.y: %d\n\
blockIdx.x: %d\n\
blockIdx.y: %d\n\
blockDim.x: %d\n\
blockDim.y: %d\n",
threadIdx.x, threadIdx.y, blockIdx.x, blockIdx.y, blockDim.x, blockDim.y);
}
int main(void) {
printf("Hello World from host!\n");
dim3 DimGrid(2, 2);
dim3 DimBlock(3, 2);
print_from_gpu<<<DimGrid, DimBlock>>>();
hipDeviceSynchronize();
printf("Can this be ahead of kernel?\n");
printf("Dim change\n");
DimGrid.x = 2; DimGrid.y = 1;
DimBlock.x = 2; DimBlock.y = 3;
print_from_gpu<<<DimGrid, DimBlock>>>();
hipDeviceSynchronize();
printf("sizeof(double): %d", sizeof(double));
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void print_from_gpu(void) {
printf(
"Hello World from device!\n\
threadIdx.x: %d\n\
threadIdx.y: %d\n\
blockIdx.x: %d\n\
blockIdx.y: %d\n\
blockDim.x: %d\n\
blockDim.y: %d\n",
threadIdx.x, threadIdx.y, blockIdx.x, blockIdx.y, blockDim.x, blockDim.y);
}
int main(void) {
printf("Hello World from host!\n");
dim3 DimGrid(2, 2);
dim3 DimBlock(3, 2);
print_from_gpu<<<DimGrid, DimBlock>>>();
hipDeviceSynchronize();
printf("Can this be ahead of kernel?\n");
printf("Dim change\n");
DimGrid.x = 2; DimGrid.y = 1;
DimBlock.x = 2; DimBlock.y = 3;
print_from_gpu<<<DimGrid, DimBlock>>>();
hipDeviceSynchronize();
printf("sizeof(double): %d", sizeof(double));
return 0;
} | .text
.file "hello.hip"
.globl _Z29__device_stub__print_from_gpuv # -- Begin function _Z29__device_stub__print_from_gpuv
.p2align 4, 0x90
.type _Z29__device_stub__print_from_gpuv,@function
_Z29__device_stub__print_from_gpuv: # @_Z29__device_stub__print_from_gpuv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14print_from_gpuv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z29__device_stub__print_from_gpuv, .Lfunc_end0-_Z29__device_stub__print_from_gpuv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $8589934594, %rdi # imm = 0x200000002
leaq 1(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14print_from_gpuv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
movabsq $4294967298, %rdi # imm = 0x100000002
movabsq $12884901890, %rdx # imm = 0x300000002
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14print_from_gpuv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movl $.L.str.3, %edi
movl $8, %esi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14print_from_gpuv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14print_from_gpuv,@object # @_Z14print_from_gpuv
.section .rodata,"a",@progbits
.globl _Z14print_from_gpuv
.p2align 3, 0x0
_Z14print_from_gpuv:
.quad _Z29__device_stub__print_from_gpuv
.size _Z14print_from_gpuv, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "sizeof(double): %d"
.size .L.str.3, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14print_from_gpuv"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World from host!"
.size .Lstr, 23
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Can this be ahead of kernel?"
.size .Lstr.1, 29
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Dim change"
.size .Lstr.2, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__print_from_gpuv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14print_from_gpuv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014f764_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z14print_from_gpuvv
.type _Z33__device_stub__Z14print_from_gpuvv, @function
_Z33__device_stub__Z14print_from_gpuvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z14print_from_gpuv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z14print_from_gpuvv, .-_Z33__device_stub__Z14print_from_gpuvv
.globl _Z14print_from_gpuv
.type _Z14print_from_gpuv, @function
_Z14print_from_gpuv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z14print_from_gpuvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14print_from_gpuv, .-_Z14print_from_gpuv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World from host!\n"
.LC1:
.string "Can this be ahead of kernel?\n"
.LC2:
.string "Dim change\n"
.LC3:
.string "sizeof(double): %d"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, 8(%rsp)
movl $2, 12(%rsp)
movl $1, 16(%rsp)
movl $3, 20(%rsp)
movl $2, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaDeviceSynchronize@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 12(%rsp)
movl $2, 20(%rsp)
movl $3, 24(%rsp)
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl 16(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L13:
call cudaDeviceSynchronize@PLT
movl $8, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call _Z33__device_stub__Z14print_from_gpuvv
jmp .L12
.L16:
call _Z33__device_stub__Z14print_from_gpuvv
jmp .L13
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z14print_from_gpuv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z14print_from_gpuv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello.hip"
.globl _Z29__device_stub__print_from_gpuv # -- Begin function _Z29__device_stub__print_from_gpuv
.p2align 4, 0x90
.type _Z29__device_stub__print_from_gpuv,@function
_Z29__device_stub__print_from_gpuv: # @_Z29__device_stub__print_from_gpuv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14print_from_gpuv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z29__device_stub__print_from_gpuv, .Lfunc_end0-_Z29__device_stub__print_from_gpuv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $8589934594, %rdi # imm = 0x200000002
leaq 1(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14print_from_gpuv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
movabsq $4294967298, %rdi # imm = 0x100000002
movabsq $12884901890, %rdx # imm = 0x300000002
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14print_from_gpuv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movl $.L.str.3, %edi
movl $8, %esi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14print_from_gpuv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14print_from_gpuv,@object # @_Z14print_from_gpuv
.section .rodata,"a",@progbits
.globl _Z14print_from_gpuv
.p2align 3, 0x0
_Z14print_from_gpuv:
.quad _Z29__device_stub__print_from_gpuv
.size _Z14print_from_gpuv, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "sizeof(double): %d"
.size .L.str.3, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14print_from_gpuv"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World from host!"
.size .Lstr, 23
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Can this be ahead of kernel?"
.size .Lstr.1, 29
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Dim change"
.size .Lstr.2, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__print_from_gpuv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14print_from_gpuv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "sum-reduction.cuh"
#define THREADS_PER_BLOCK_SUM_REDUCTION 512U
template <int blockSize>
__global__ void cuSumReduce__(int *list, int n)
{
__shared__ int s_data[blockSize];
int tid = threadIdx.x;
int i = threadIdx.x;
int gridSize = blockSize * 2;
int mySum = 0;
while (i < n)
{
mySum += list[i];
if (i + blockSize < n)
{
mySum += list[i + blockSize];
}
i += gridSize;
}
s_data[tid] = mySum;
__syncthreads();
if (blockSize >= 512)
{
if (tid < 256)
{
s_data[tid] = mySum = mySum + s_data[tid + 256];
}
__syncthreads();
}
if (blockSize >= 256)
{
if (tid < 128)
{
s_data[tid] = mySum = mySum + s_data[tid + 128];
}
__syncthreads();
}
if (blockSize >= 128)
{
if (tid < 64)
{
s_data[tid] = mySum = mySum + s_data[tid + 64];
}
__syncthreads();
}
if (tid < 32)
{
volatile int *smem = s_data;
if (blockSize >= 64)
{
smem[tid] = mySum = mySum + smem[tid + 32];
}
if (blockSize >= 32)
{
smem[tid] = mySum = mySum + smem[tid + 16];
}
if (blockSize >= 16)
{
smem[tid] = mySum = mySum + smem[tid + 8];
}
if (blockSize >= 8)
{
smem[tid] = mySum = mySum + smem[tid + 4];
}
if (blockSize >= 4)
{
smem[tid] = mySum = mySum + smem[tid + 2];
}
if (blockSize >= 2)
{
smem[tid] = mySum = mySum + smem[tid + 1];
}
}
if (threadIdx.x == 0)
{
list[0] = s_data[0];
}
}
int nextPowerOf2__(int x)
{
--x;
x |= x >> 1;
x |= x >> 2;
x |= x >> 4;
x |= x >> 8;
x |= x >> 16;
return ++x;
}
void getThreadAndBlockCountFoSumReduction(int n, int &blocks, int &threads)
{
threads = max(1, nextPowerOf2__(((n - 1) >> 1))), //threads must be power of 2
threads = min(threads, THREADS_PER_BLOCK_SUM_REDUCTION);
blocks = 1;
// printf("block = %d, threads = %d, n = %d, p =%d\n", blocks, threads, n, p );
}
void sum_reduce(int *d_list, int n)
{
int threads, blocks;
getThreadAndBlockCountFoSumReduction(n, blocks, threads);
int smemSize = (threads <= 32) ? 2 * threads * sizeof(float) : threads * sizeof(float);
switch (threads)
{
case 512:
cuSumReduce__<512> <<< blocks, threads, smemSize >>>(d_list, n); break;
case 256:
cuSumReduce__<256> <<< blocks, threads, smemSize >>>(d_list, n); break;
case 128:
cuSumReduce__<128> <<< blocks, threads, smemSize >>>(d_list, n); break;
case 64:
cuSumReduce__<64> <<< blocks, threads, smemSize >>>(d_list, n); break;
case 32:
cuSumReduce__<32> <<< blocks, threads, smemSize >>>(d_list, n); break;
case 16:
cuSumReduce__<16> <<< blocks, threads, smemSize >>>(d_list, n); break;
case 8:
cuSumReduce__<8> <<< blocks, threads, smemSize >>>(d_list, n); break;
case 4:
cuSumReduce__<4> <<< blocks, threads, smemSize >>>(d_list, n); break;
case 2:
cuSumReduce__<2> <<< blocks, threads, smemSize >>>(d_list, n); break;
case 1:
cuSumReduce__<1> <<< blocks, threads, smemSize >>>(d_list, n); break;
}
} | .file "tmpxft_001aa546_00000000-6_sum-reduction.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL43__device_stub__Z13cuSumReduce__ILi512EEvPiiPii, @function
_ZL43__device_stub__Z13cuSumReduce__ILi512EEvPiiPii:
.LFB2056:
.cfi_startproc
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13cuSumReduce__ILi512EEvPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _ZL43__device_stub__Z13cuSumReduce__ILi512EEvPiiPii, .-_ZL43__device_stub__Z13cuSumReduce__ILi512EEvPiiPii
.section .text._Z13cuSumReduce__ILi512EEvPii,"axG",@progbits,_Z13cuSumReduce__ILi512EEvPii,comdat
.weak _Z13cuSumReduce__ILi512EEvPii
.type _Z13cuSumReduce__ILi512EEvPii, @function
_Z13cuSumReduce__ILi512EEvPii:
.LFB2123:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL43__device_stub__Z13cuSumReduce__ILi512EEvPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2123:
.size _Z13cuSumReduce__ILi512EEvPii, .-_Z13cuSumReduce__ILi512EEvPii
.text
.type _ZL43__device_stub__Z13cuSumReduce__ILi256EEvPiiPii, @function
_ZL43__device_stub__Z13cuSumReduce__ILi256EEvPiiPii:
.LFB2058:
.cfi_startproc
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13cuSumReduce__ILi256EEvPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _ZL43__device_stub__Z13cuSumReduce__ILi256EEvPiiPii, .-_ZL43__device_stub__Z13cuSumReduce__ILi256EEvPiiPii
.section .text._Z13cuSumReduce__ILi256EEvPii,"axG",@progbits,_Z13cuSumReduce__ILi256EEvPii,comdat
.weak _Z13cuSumReduce__ILi256EEvPii
.type _Z13cuSumReduce__ILi256EEvPii, @function
_Z13cuSumReduce__ILi256EEvPii:
.LFB2124:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL43__device_stub__Z13cuSumReduce__ILi256EEvPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2124:
.size _Z13cuSumReduce__ILi256EEvPii, .-_Z13cuSumReduce__ILi256EEvPii
.text
.type _ZL43__device_stub__Z13cuSumReduce__ILi128EEvPiiPii, @function
_ZL43__device_stub__Z13cuSumReduce__ILi128EEvPiiPii:
.LFB2060:
.cfi_startproc
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13cuSumReduce__ILi128EEvPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _ZL43__device_stub__Z13cuSumReduce__ILi128EEvPiiPii, .-_ZL43__device_stub__Z13cuSumReduce__ILi128EEvPiiPii
.section .text._Z13cuSumReduce__ILi128EEvPii,"axG",@progbits,_Z13cuSumReduce__ILi128EEvPii,comdat
.weak _Z13cuSumReduce__ILi128EEvPii
.type _Z13cuSumReduce__ILi128EEvPii, @function
_Z13cuSumReduce__ILi128EEvPii:
.LFB2125:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL43__device_stub__Z13cuSumReduce__ILi128EEvPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2125:
.size _Z13cuSumReduce__ILi128EEvPii, .-_Z13cuSumReduce__ILi128EEvPii
.text
.type _ZL42__device_stub__Z13cuSumReduce__ILi64EEvPiiPii, @function
_ZL42__device_stub__Z13cuSumReduce__ILi64EEvPiiPii:
.LFB2062:
.cfi_startproc
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13cuSumReduce__ILi64EEvPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _ZL42__device_stub__Z13cuSumReduce__ILi64EEvPiiPii, .-_ZL42__device_stub__Z13cuSumReduce__ILi64EEvPiiPii
.section .text._Z13cuSumReduce__ILi64EEvPii,"axG",@progbits,_Z13cuSumReduce__ILi64EEvPii,comdat
.weak _Z13cuSumReduce__ILi64EEvPii
.type _Z13cuSumReduce__ILi64EEvPii, @function
_Z13cuSumReduce__ILi64EEvPii:
.LFB2126:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL42__device_stub__Z13cuSumReduce__ILi64EEvPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2126:
.size _Z13cuSumReduce__ILi64EEvPii, .-_Z13cuSumReduce__ILi64EEvPii
.text
.type _ZL42__device_stub__Z13cuSumReduce__ILi32EEvPiiPii, @function
_ZL42__device_stub__Z13cuSumReduce__ILi32EEvPiiPii:
.LFB2064:
.cfi_startproc
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13cuSumReduce__ILi32EEvPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2064:
.size _ZL42__device_stub__Z13cuSumReduce__ILi32EEvPiiPii, .-_ZL42__device_stub__Z13cuSumReduce__ILi32EEvPiiPii
.section .text._Z13cuSumReduce__ILi32EEvPii,"axG",@progbits,_Z13cuSumReduce__ILi32EEvPii,comdat
.weak _Z13cuSumReduce__ILi32EEvPii
.type _Z13cuSumReduce__ILi32EEvPii, @function
_Z13cuSumReduce__ILi32EEvPii:
.LFB2127:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL42__device_stub__Z13cuSumReduce__ILi32EEvPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2127:
.size _Z13cuSumReduce__ILi32EEvPii, .-_Z13cuSumReduce__ILi32EEvPii
.text
.type _ZL42__device_stub__Z13cuSumReduce__ILi16EEvPiiPii, @function
_ZL42__device_stub__Z13cuSumReduce__ILi16EEvPiiPii:
.LFB2066:
.cfi_startproc
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13cuSumReduce__ILi16EEvPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2066:
.size _ZL42__device_stub__Z13cuSumReduce__ILi16EEvPiiPii, .-_ZL42__device_stub__Z13cuSumReduce__ILi16EEvPiiPii
.section .text._Z13cuSumReduce__ILi16EEvPii,"axG",@progbits,_Z13cuSumReduce__ILi16EEvPii,comdat
.weak _Z13cuSumReduce__ILi16EEvPii
.type _Z13cuSumReduce__ILi16EEvPii, @function
_Z13cuSumReduce__ILi16EEvPii:
.LFB2128:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL42__device_stub__Z13cuSumReduce__ILi16EEvPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2128:
.size _Z13cuSumReduce__ILi16EEvPii, .-_Z13cuSumReduce__ILi16EEvPii
.text
.type _ZL41__device_stub__Z13cuSumReduce__ILi8EEvPiiPii, @function
_ZL41__device_stub__Z13cuSumReduce__ILi8EEvPiiPii:
.LFB2068:
.cfi_startproc
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L53
.L49:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L54
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13cuSumReduce__ILi8EEvPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L49
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2068:
.size _ZL41__device_stub__Z13cuSumReduce__ILi8EEvPiiPii, .-_ZL41__device_stub__Z13cuSumReduce__ILi8EEvPiiPii
.section .text._Z13cuSumReduce__ILi8EEvPii,"axG",@progbits,_Z13cuSumReduce__ILi8EEvPii,comdat
.weak _Z13cuSumReduce__ILi8EEvPii
.type _Z13cuSumReduce__ILi8EEvPii, @function
_Z13cuSumReduce__ILi8EEvPii:
.LFB2129:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL41__device_stub__Z13cuSumReduce__ILi8EEvPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2129:
.size _Z13cuSumReduce__ILi8EEvPii, .-_Z13cuSumReduce__ILi8EEvPii
.text
.type _ZL41__device_stub__Z13cuSumReduce__ILi4EEvPiiPii, @function
_ZL41__device_stub__Z13cuSumReduce__ILi4EEvPiiPii:
.LFB2070:
.cfi_startproc
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L61
.L57:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L62
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13cuSumReduce__ILi4EEvPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L57
.L62:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size _ZL41__device_stub__Z13cuSumReduce__ILi4EEvPiiPii, .-_ZL41__device_stub__Z13cuSumReduce__ILi4EEvPiiPii
.section .text._Z13cuSumReduce__ILi4EEvPii,"axG",@progbits,_Z13cuSumReduce__ILi4EEvPii,comdat
.weak _Z13cuSumReduce__ILi4EEvPii
.type _Z13cuSumReduce__ILi4EEvPii, @function
_Z13cuSumReduce__ILi4EEvPii:
.LFB2130:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL41__device_stub__Z13cuSumReduce__ILi4EEvPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2130:
.size _Z13cuSumReduce__ILi4EEvPii, .-_Z13cuSumReduce__ILi4EEvPii
.text
.type _ZL41__device_stub__Z13cuSumReduce__ILi2EEvPiiPii, @function
_ZL41__device_stub__Z13cuSumReduce__ILi2EEvPiiPii:
.LFB2072:
.cfi_startproc
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L69
.L65:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L70
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L69:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13cuSumReduce__ILi2EEvPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L65
.L70:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2072:
.size _ZL41__device_stub__Z13cuSumReduce__ILi2EEvPiiPii, .-_ZL41__device_stub__Z13cuSumReduce__ILi2EEvPiiPii
.section .text._Z13cuSumReduce__ILi2EEvPii,"axG",@progbits,_Z13cuSumReduce__ILi2EEvPii,comdat
.weak _Z13cuSumReduce__ILi2EEvPii
.type _Z13cuSumReduce__ILi2EEvPii, @function
_Z13cuSumReduce__ILi2EEvPii:
.LFB2131:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL41__device_stub__Z13cuSumReduce__ILi2EEvPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2131:
.size _Z13cuSumReduce__ILi2EEvPii, .-_Z13cuSumReduce__ILi2EEvPii
.text
.type _ZL41__device_stub__Z13cuSumReduce__ILi1EEvPiiPii, @function
_ZL41__device_stub__Z13cuSumReduce__ILi1EEvPiiPii:
.LFB2074:
.cfi_startproc
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L77
.L73:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L78
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L77:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13cuSumReduce__ILi1EEvPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L73
.L78:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2074:
.size _ZL41__device_stub__Z13cuSumReduce__ILi1EEvPiiPii, .-_ZL41__device_stub__Z13cuSumReduce__ILi1EEvPiiPii
.section .text._Z13cuSumReduce__ILi1EEvPii,"axG",@progbits,_Z13cuSumReduce__ILi1EEvPii,comdat
.weak _Z13cuSumReduce__ILi1EEvPii
.type _Z13cuSumReduce__ILi1EEvPii, @function
_Z13cuSumReduce__ILi1EEvPii:
.LFB2132:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL41__device_stub__Z13cuSumReduce__ILi1EEvPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2132:
.size _Z13cuSumReduce__ILi1EEvPii, .-_Z13cuSumReduce__ILi1EEvPii
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2034:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2034:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14nextPowerOf2__i
.type _Z14nextPowerOf2__i, @function
_Z14nextPowerOf2__i:
.LFB2029:
.cfi_startproc
endbr64
subl $1, %edi
movl %edi, %eax
sarl %eax
orl %edi, %eax
movl %eax, %edi
sarl $2, %edi
orl %eax, %edi
movl %edi, %eax
sarl $4, %eax
orl %edi, %eax
movl %eax, %edx
sarl $8, %edx
orl %eax, %edx
movl %edx, %eax
sarl $16, %eax
orl %edx, %eax
addl $1, %eax
ret
.cfi_endproc
.LFE2029:
.size _Z14nextPowerOf2__i, .-_Z14nextPowerOf2__i
.globl _Z36getThreadAndBlockCountFoSumReductioniRiS_
.type _Z36getThreadAndBlockCountFoSumReductioniRiS_, @function
_Z36getThreadAndBlockCountFoSumReductioniRiS_:
.LFB2030:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rsi, %rbx
movq %rdx, %rbp
subl $1, %edi
sarl %edi
call _Z14nextPowerOf2__i
testl %eax, %eax
movl $1, %edx
cmovle %edx, %eax
movl $512, %edx
cmpl %edx, %eax
cmova %edx, %eax
movl %eax, 0(%rbp)
movl $1, (%rbx)
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _Z36getThreadAndBlockCountFoSumReductioniRiS_, .-_Z36getThreadAndBlockCountFoSumReductioniRiS_
.globl _Z10sum_reducePii
.type _Z10sum_reducePii, @function
_Z10sum_reducePii:
.LFB2031:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movl %esi, %ebx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdx
leaq 12(%rsp), %rsi
movl %ebx, %edi
call _Z36getThreadAndBlockCountFoSumReductioniRiS_
movl 8(%rsp), %eax
cmpl $32, %eax
jg .L87
leal 0(,%rax,8), %r8d
testl %eax, %eax
jle .L86
cmpl $32, %eax
ja .L86
movl %eax, %eax
leaq .L93(%rip), %rdx
movslq (%rdx,%rax,4), %rax
addq %rdx, %rax
notrack jmp *%rax
.section .rodata
.align 4
.align 4
.L93:
.long .L86-.L93
.long .L98-.L93
.long .L97-.L93
.long .L86-.L93
.long .L96-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L95-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L94-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L92-.L93
.text
.L87:
leal 0(,%rax,4), %r8d
cmpl $256, %eax
je .L115
jg .L99
cmpl $64, %eax
je .L100
cmpl $128, %eax
jne .L86
movl $128, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl 12(%rsp), %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movslq %r8d, %r8
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L86
movl %ebx, %esi
movq %rbp, %rdi
call _ZL43__device_stub__Z13cuSumReduce__ILi128EEvPiiPii
jmp .L86
.L99:
cmpl $512, %eax
jne .L86
movl $512, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl 12(%rsp), %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movslq %r8d, %r8
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L116
.L86:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L117
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L116:
.cfi_restore_state
movl %ebx, %esi
movq %rbp, %rdi
call _ZL43__device_stub__Z13cuSumReduce__ILi512EEvPiiPii
jmp .L86
.L115:
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl 12(%rsp), %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movslq %r8d, %r8
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L86
movl %ebx, %esi
movq %rbp, %rdi
call _ZL43__device_stub__Z13cuSumReduce__ILi256EEvPiiPii
jmp .L86
.L100:
movl $64, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl 12(%rsp), %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movslq %r8d, %r8
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L86
movl %ebx, %esi
movq %rbp, %rdi
call _ZL42__device_stub__Z13cuSumReduce__ILi64EEvPiiPii
jmp .L86
.L92:
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl 12(%rsp), %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movslq %r8d, %r8
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L86
movl %ebx, %esi
movq %rbp, %rdi
call _ZL42__device_stub__Z13cuSumReduce__ILi32EEvPiiPii
jmp .L86
.L94:
movl $16, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl 12(%rsp), %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movslq %r8d, %r8
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L86
movl %ebx, %esi
movq %rbp, %rdi
call _ZL42__device_stub__Z13cuSumReduce__ILi16EEvPiiPii
jmp .L86
.L95:
movl $8, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl 12(%rsp), %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movslq %r8d, %r8
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L86
movl %ebx, %esi
movq %rbp, %rdi
call _ZL41__device_stub__Z13cuSumReduce__ILi8EEvPiiPii
jmp .L86
.L96:
movl $4, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl 12(%rsp), %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movslq %r8d, %r8
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L86
movl %ebx, %esi
movq %rbp, %rdi
call _ZL41__device_stub__Z13cuSumReduce__ILi4EEvPiiPii
jmp .L86
.L97:
movl $2, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl 12(%rsp), %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movslq %r8d, %r8
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L86
movl %ebx, %esi
movq %rbp, %rdi
call _ZL41__device_stub__Z13cuSumReduce__ILi2EEvPiiPii
jmp .L86
.L98:
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl 12(%rsp), %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movslq %r8d, %r8
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L86
movl %ebx, %esi
movq %rbp, %rdi
call _ZL41__device_stub__Z13cuSumReduce__ILi1EEvPiiPii
jmp .L86
.L117:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2031:
.size _Z10sum_reducePii, .-_Z10sum_reducePii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13cuSumReduce__ILi1EEvPii"
.LC1:
.string "_Z13cuSumReduce__ILi2EEvPii"
.LC2:
.string "_Z13cuSumReduce__ILi4EEvPii"
.LC3:
.string "_Z13cuSumReduce__ILi8EEvPii"
.LC4:
.string "_Z13cuSumReduce__ILi16EEvPii"
.LC5:
.string "_Z13cuSumReduce__ILi32EEvPii"
.LC6:
.string "_Z13cuSumReduce__ILi64EEvPii"
.LC7:
.string "_Z13cuSumReduce__ILi128EEvPii"
.LC8:
.string "_Z13cuSumReduce__ILi256EEvPii"
.LC9:
.string "_Z13cuSumReduce__ILi512EEvPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2077:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cuSumReduce__ILi1EEvPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cuSumReduce__ILi2EEvPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cuSumReduce__ILi4EEvPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cuSumReduce__ILi8EEvPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cuSumReduce__ILi16EEvPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cuSumReduce__ILi32EEvPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cuSumReduce__ILi64EEvPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cuSumReduce__ILi128EEvPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cuSumReduce__ILi256EEvPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cuSumReduce__ILi512EEvPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2077:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "sum-reduction.cuh"
#define THREADS_PER_BLOCK_SUM_REDUCTION 512U
template <int blockSize>
__global__ void cuSumReduce__(int *list, int n)
{
__shared__ int s_data[blockSize];
int tid = threadIdx.x;
int i = threadIdx.x;
int gridSize = blockSize * 2;
int mySum = 0;
while (i < n)
{
mySum += list[i];
if (i + blockSize < n)
{
mySum += list[i + blockSize];
}
i += gridSize;
}
s_data[tid] = mySum;
__syncthreads();
if (blockSize >= 512)
{
if (tid < 256)
{
s_data[tid] = mySum = mySum + s_data[tid + 256];
}
__syncthreads();
}
if (blockSize >= 256)
{
if (tid < 128)
{
s_data[tid] = mySum = mySum + s_data[tid + 128];
}
__syncthreads();
}
if (blockSize >= 128)
{
if (tid < 64)
{
s_data[tid] = mySum = mySum + s_data[tid + 64];
}
__syncthreads();
}
if (tid < 32)
{
volatile int *smem = s_data;
if (blockSize >= 64)
{
smem[tid] = mySum = mySum + smem[tid + 32];
}
if (blockSize >= 32)
{
smem[tid] = mySum = mySum + smem[tid + 16];
}
if (blockSize >= 16)
{
smem[tid] = mySum = mySum + smem[tid + 8];
}
if (blockSize >= 8)
{
smem[tid] = mySum = mySum + smem[tid + 4];
}
if (blockSize >= 4)
{
smem[tid] = mySum = mySum + smem[tid + 2];
}
if (blockSize >= 2)
{
smem[tid] = mySum = mySum + smem[tid + 1];
}
}
if (threadIdx.x == 0)
{
list[0] = s_data[0];
}
}
int nextPowerOf2__(int x)
{
--x;
x |= x >> 1;
x |= x >> 2;
x |= x >> 4;
x |= x >> 8;
x |= x >> 16;
return ++x;
}
void getThreadAndBlockCountFoSumReduction(int n, int &blocks, int &threads)
{
threads = max(1, nextPowerOf2__(((n - 1) >> 1))), //threads must be power of 2
threads = min(threads, THREADS_PER_BLOCK_SUM_REDUCTION);
blocks = 1;
// printf("block = %d, threads = %d, n = %d, p =%d\n", blocks, threads, n, p );
}
void sum_reduce(int *d_list, int n)
{
int threads, blocks;
getThreadAndBlockCountFoSumReduction(n, blocks, threads);
int smemSize = (threads <= 32) ? 2 * threads * sizeof(float) : threads * sizeof(float);
switch (threads)
{
case 512:
cuSumReduce__<512> <<< blocks, threads, smemSize >>>(d_list, n); break;
case 256:
cuSumReduce__<256> <<< blocks, threads, smemSize >>>(d_list, n); break;
case 128:
cuSumReduce__<128> <<< blocks, threads, smemSize >>>(d_list, n); break;
case 64:
cuSumReduce__<64> <<< blocks, threads, smemSize >>>(d_list, n); break;
case 32:
cuSumReduce__<32> <<< blocks, threads, smemSize >>>(d_list, n); break;
case 16:
cuSumReduce__<16> <<< blocks, threads, smemSize >>>(d_list, n); break;
case 8:
cuSumReduce__<8> <<< blocks, threads, smemSize >>>(d_list, n); break;
case 4:
cuSumReduce__<4> <<< blocks, threads, smemSize >>>(d_list, n); break;
case 2:
cuSumReduce__<2> <<< blocks, threads, smemSize >>>(d_list, n); break;
case 1:
cuSumReduce__<1> <<< blocks, threads, smemSize >>>(d_list, n); break;
}
} | #ifndef SUM_REDUCTION_
#define SUM_REDUCTION_
void sum_reduce(int *list, int n);
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef SUM_REDUCTION_
#define SUM_REDUCTION_
void sum_reduce(int *list, int n);
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef SUM_REDUCTION_
#define SUM_REDUCTION_
void sum_reduce(int *list, int n);
#endif | .text
.file "sum-reduction.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001aa546_00000000-6_sum-reduction.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL43__device_stub__Z13cuSumReduce__ILi512EEvPiiPii, @function
_ZL43__device_stub__Z13cuSumReduce__ILi512EEvPiiPii:
.LFB2056:
.cfi_startproc
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13cuSumReduce__ILi512EEvPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _ZL43__device_stub__Z13cuSumReduce__ILi512EEvPiiPii, .-_ZL43__device_stub__Z13cuSumReduce__ILi512EEvPiiPii
.section .text._Z13cuSumReduce__ILi512EEvPii,"axG",@progbits,_Z13cuSumReduce__ILi512EEvPii,comdat
.weak _Z13cuSumReduce__ILi512EEvPii
.type _Z13cuSumReduce__ILi512EEvPii, @function
_Z13cuSumReduce__ILi512EEvPii:
.LFB2123:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL43__device_stub__Z13cuSumReduce__ILi512EEvPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2123:
.size _Z13cuSumReduce__ILi512EEvPii, .-_Z13cuSumReduce__ILi512EEvPii
.text
.type _ZL43__device_stub__Z13cuSumReduce__ILi256EEvPiiPii, @function
_ZL43__device_stub__Z13cuSumReduce__ILi256EEvPiiPii:
.LFB2058:
.cfi_startproc
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13cuSumReduce__ILi256EEvPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _ZL43__device_stub__Z13cuSumReduce__ILi256EEvPiiPii, .-_ZL43__device_stub__Z13cuSumReduce__ILi256EEvPiiPii
.section .text._Z13cuSumReduce__ILi256EEvPii,"axG",@progbits,_Z13cuSumReduce__ILi256EEvPii,comdat
.weak _Z13cuSumReduce__ILi256EEvPii
.type _Z13cuSumReduce__ILi256EEvPii, @function
_Z13cuSumReduce__ILi256EEvPii:
.LFB2124:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL43__device_stub__Z13cuSumReduce__ILi256EEvPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2124:
.size _Z13cuSumReduce__ILi256EEvPii, .-_Z13cuSumReduce__ILi256EEvPii
.text
.type _ZL43__device_stub__Z13cuSumReduce__ILi128EEvPiiPii, @function
_ZL43__device_stub__Z13cuSumReduce__ILi128EEvPiiPii:
.LFB2060:
.cfi_startproc
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13cuSumReduce__ILi128EEvPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _ZL43__device_stub__Z13cuSumReduce__ILi128EEvPiiPii, .-_ZL43__device_stub__Z13cuSumReduce__ILi128EEvPiiPii
.section .text._Z13cuSumReduce__ILi128EEvPii,"axG",@progbits,_Z13cuSumReduce__ILi128EEvPii,comdat
.weak _Z13cuSumReduce__ILi128EEvPii
.type _Z13cuSumReduce__ILi128EEvPii, @function
_Z13cuSumReduce__ILi128EEvPii:
.LFB2125:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL43__device_stub__Z13cuSumReduce__ILi128EEvPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2125:
.size _Z13cuSumReduce__ILi128EEvPii, .-_Z13cuSumReduce__ILi128EEvPii
.text
.type _ZL42__device_stub__Z13cuSumReduce__ILi64EEvPiiPii, @function
_ZL42__device_stub__Z13cuSumReduce__ILi64EEvPiiPii:
.LFB2062:
.cfi_startproc
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13cuSumReduce__ILi64EEvPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _ZL42__device_stub__Z13cuSumReduce__ILi64EEvPiiPii, .-_ZL42__device_stub__Z13cuSumReduce__ILi64EEvPiiPii
.section .text._Z13cuSumReduce__ILi64EEvPii,"axG",@progbits,_Z13cuSumReduce__ILi64EEvPii,comdat
.weak _Z13cuSumReduce__ILi64EEvPii
.type _Z13cuSumReduce__ILi64EEvPii, @function
_Z13cuSumReduce__ILi64EEvPii:
.LFB2126:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL42__device_stub__Z13cuSumReduce__ILi64EEvPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2126:
.size _Z13cuSumReduce__ILi64EEvPii, .-_Z13cuSumReduce__ILi64EEvPii
.text
.type _ZL42__device_stub__Z13cuSumReduce__ILi32EEvPiiPii, @function
_ZL42__device_stub__Z13cuSumReduce__ILi32EEvPiiPii:
.LFB2064:
.cfi_startproc
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13cuSumReduce__ILi32EEvPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2064:
.size _ZL42__device_stub__Z13cuSumReduce__ILi32EEvPiiPii, .-_ZL42__device_stub__Z13cuSumReduce__ILi32EEvPiiPii
.section .text._Z13cuSumReduce__ILi32EEvPii,"axG",@progbits,_Z13cuSumReduce__ILi32EEvPii,comdat
.weak _Z13cuSumReduce__ILi32EEvPii
.type _Z13cuSumReduce__ILi32EEvPii, @function
_Z13cuSumReduce__ILi32EEvPii:
.LFB2127:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL42__device_stub__Z13cuSumReduce__ILi32EEvPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2127:
.size _Z13cuSumReduce__ILi32EEvPii, .-_Z13cuSumReduce__ILi32EEvPii
.text
.type _ZL42__device_stub__Z13cuSumReduce__ILi16EEvPiiPii, @function
_ZL42__device_stub__Z13cuSumReduce__ILi16EEvPiiPii:
.LFB2066:
.cfi_startproc
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13cuSumReduce__ILi16EEvPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2066:
.size _ZL42__device_stub__Z13cuSumReduce__ILi16EEvPiiPii, .-_ZL42__device_stub__Z13cuSumReduce__ILi16EEvPiiPii
.section .text._Z13cuSumReduce__ILi16EEvPii,"axG",@progbits,_Z13cuSumReduce__ILi16EEvPii,comdat
.weak _Z13cuSumReduce__ILi16EEvPii
.type _Z13cuSumReduce__ILi16EEvPii, @function
_Z13cuSumReduce__ILi16EEvPii:
.LFB2128:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL42__device_stub__Z13cuSumReduce__ILi16EEvPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2128:
.size _Z13cuSumReduce__ILi16EEvPii, .-_Z13cuSumReduce__ILi16EEvPii
.text
.type _ZL41__device_stub__Z13cuSumReduce__ILi8EEvPiiPii, @function
_ZL41__device_stub__Z13cuSumReduce__ILi8EEvPiiPii:
.LFB2068:
.cfi_startproc
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L53
.L49:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L54
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13cuSumReduce__ILi8EEvPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L49
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2068:
.size _ZL41__device_stub__Z13cuSumReduce__ILi8EEvPiiPii, .-_ZL41__device_stub__Z13cuSumReduce__ILi8EEvPiiPii
.section .text._Z13cuSumReduce__ILi8EEvPii,"axG",@progbits,_Z13cuSumReduce__ILi8EEvPii,comdat
.weak _Z13cuSumReduce__ILi8EEvPii
.type _Z13cuSumReduce__ILi8EEvPii, @function
_Z13cuSumReduce__ILi8EEvPii:
.LFB2129:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL41__device_stub__Z13cuSumReduce__ILi8EEvPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2129:
.size _Z13cuSumReduce__ILi8EEvPii, .-_Z13cuSumReduce__ILi8EEvPii
.text
.type _ZL41__device_stub__Z13cuSumReduce__ILi4EEvPiiPii, @function
_ZL41__device_stub__Z13cuSumReduce__ILi4EEvPiiPii:
.LFB2070:
.cfi_startproc
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L61
.L57:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L62
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13cuSumReduce__ILi4EEvPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L57
.L62:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size _ZL41__device_stub__Z13cuSumReduce__ILi4EEvPiiPii, .-_ZL41__device_stub__Z13cuSumReduce__ILi4EEvPiiPii
.section .text._Z13cuSumReduce__ILi4EEvPii,"axG",@progbits,_Z13cuSumReduce__ILi4EEvPii,comdat
.weak _Z13cuSumReduce__ILi4EEvPii
.type _Z13cuSumReduce__ILi4EEvPii, @function
_Z13cuSumReduce__ILi4EEvPii:
.LFB2130:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL41__device_stub__Z13cuSumReduce__ILi4EEvPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2130:
.size _Z13cuSumReduce__ILi4EEvPii, .-_Z13cuSumReduce__ILi4EEvPii
.text
.type _ZL41__device_stub__Z13cuSumReduce__ILi2EEvPiiPii, @function
_ZL41__device_stub__Z13cuSumReduce__ILi2EEvPiiPii:
.LFB2072:
.cfi_startproc
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L69
.L65:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L70
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L69:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13cuSumReduce__ILi2EEvPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L65
.L70:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2072:
.size _ZL41__device_stub__Z13cuSumReduce__ILi2EEvPiiPii, .-_ZL41__device_stub__Z13cuSumReduce__ILi2EEvPiiPii
.section .text._Z13cuSumReduce__ILi2EEvPii,"axG",@progbits,_Z13cuSumReduce__ILi2EEvPii,comdat
.weak _Z13cuSumReduce__ILi2EEvPii
.type _Z13cuSumReduce__ILi2EEvPii, @function
_Z13cuSumReduce__ILi2EEvPii:
.LFB2131:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL41__device_stub__Z13cuSumReduce__ILi2EEvPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2131:
.size _Z13cuSumReduce__ILi2EEvPii, .-_Z13cuSumReduce__ILi2EEvPii
.text
.type _ZL41__device_stub__Z13cuSumReduce__ILi1EEvPiiPii, @function
_ZL41__device_stub__Z13cuSumReduce__ILi1EEvPiiPii:
.LFB2074:
.cfi_startproc
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L77
.L73:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L78
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L77:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13cuSumReduce__ILi1EEvPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L73
.L78:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2074:
.size _ZL41__device_stub__Z13cuSumReduce__ILi1EEvPiiPii, .-_ZL41__device_stub__Z13cuSumReduce__ILi1EEvPiiPii
.section .text._Z13cuSumReduce__ILi1EEvPii,"axG",@progbits,_Z13cuSumReduce__ILi1EEvPii,comdat
.weak _Z13cuSumReduce__ILi1EEvPii
.type _Z13cuSumReduce__ILi1EEvPii, @function
_Z13cuSumReduce__ILi1EEvPii:
.LFB2132:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL41__device_stub__Z13cuSumReduce__ILi1EEvPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2132:
.size _Z13cuSumReduce__ILi1EEvPii, .-_Z13cuSumReduce__ILi1EEvPii
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2034:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2034:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14nextPowerOf2__i
.type _Z14nextPowerOf2__i, @function
_Z14nextPowerOf2__i:
.LFB2029:
.cfi_startproc
endbr64
subl $1, %edi
movl %edi, %eax
sarl %eax
orl %edi, %eax
movl %eax, %edi
sarl $2, %edi
orl %eax, %edi
movl %edi, %eax
sarl $4, %eax
orl %edi, %eax
movl %eax, %edx
sarl $8, %edx
orl %eax, %edx
movl %edx, %eax
sarl $16, %eax
orl %edx, %eax
addl $1, %eax
ret
.cfi_endproc
.LFE2029:
.size _Z14nextPowerOf2__i, .-_Z14nextPowerOf2__i
.globl _Z36getThreadAndBlockCountFoSumReductioniRiS_
.type _Z36getThreadAndBlockCountFoSumReductioniRiS_, @function
_Z36getThreadAndBlockCountFoSumReductioniRiS_:
.LFB2030:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rsi, %rbx
movq %rdx, %rbp
subl $1, %edi
sarl %edi
call _Z14nextPowerOf2__i
testl %eax, %eax
movl $1, %edx
cmovle %edx, %eax
movl $512, %edx
cmpl %edx, %eax
cmova %edx, %eax
movl %eax, 0(%rbp)
movl $1, (%rbx)
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _Z36getThreadAndBlockCountFoSumReductioniRiS_, .-_Z36getThreadAndBlockCountFoSumReductioniRiS_
.globl _Z10sum_reducePii
.type _Z10sum_reducePii, @function
_Z10sum_reducePii:
.LFB2031:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movl %esi, %ebx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdx
leaq 12(%rsp), %rsi
movl %ebx, %edi
call _Z36getThreadAndBlockCountFoSumReductioniRiS_
movl 8(%rsp), %eax
cmpl $32, %eax
jg .L87
leal 0(,%rax,8), %r8d
testl %eax, %eax
jle .L86
cmpl $32, %eax
ja .L86
movl %eax, %eax
leaq .L93(%rip), %rdx
movslq (%rdx,%rax,4), %rax
addq %rdx, %rax
notrack jmp *%rax
.section .rodata
.align 4
.align 4
.L93:
.long .L86-.L93
.long .L98-.L93
.long .L97-.L93
.long .L86-.L93
.long .L96-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L95-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L94-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L86-.L93
.long .L92-.L93
.text
.L87:
leal 0(,%rax,4), %r8d
cmpl $256, %eax
je .L115
jg .L99
cmpl $64, %eax
je .L100
cmpl $128, %eax
jne .L86
movl $128, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl 12(%rsp), %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movslq %r8d, %r8
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L86
movl %ebx, %esi
movq %rbp, %rdi
call _ZL43__device_stub__Z13cuSumReduce__ILi128EEvPiiPii
jmp .L86
.L99:
cmpl $512, %eax
jne .L86
movl $512, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl 12(%rsp), %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movslq %r8d, %r8
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L116
.L86:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L117
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L116:
.cfi_restore_state
movl %ebx, %esi
movq %rbp, %rdi
call _ZL43__device_stub__Z13cuSumReduce__ILi512EEvPiiPii
jmp .L86
.L115:
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl 12(%rsp), %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movslq %r8d, %r8
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L86
movl %ebx, %esi
movq %rbp, %rdi
call _ZL43__device_stub__Z13cuSumReduce__ILi256EEvPiiPii
jmp .L86
.L100:
movl $64, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl 12(%rsp), %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movslq %r8d, %r8
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L86
movl %ebx, %esi
movq %rbp, %rdi
call _ZL42__device_stub__Z13cuSumReduce__ILi64EEvPiiPii
jmp .L86
.L92:
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl 12(%rsp), %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movslq %r8d, %r8
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L86
movl %ebx, %esi
movq %rbp, %rdi
call _ZL42__device_stub__Z13cuSumReduce__ILi32EEvPiiPii
jmp .L86
.L94:
movl $16, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl 12(%rsp), %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movslq %r8d, %r8
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L86
movl %ebx, %esi
movq %rbp, %rdi
call _ZL42__device_stub__Z13cuSumReduce__ILi16EEvPiiPii
jmp .L86
.L95:
movl $8, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl 12(%rsp), %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movslq %r8d, %r8
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L86
movl %ebx, %esi
movq %rbp, %rdi
call _ZL41__device_stub__Z13cuSumReduce__ILi8EEvPiiPii
jmp .L86
.L96:
movl $4, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl 12(%rsp), %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movslq %r8d, %r8
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L86
movl %ebx, %esi
movq %rbp, %rdi
call _ZL41__device_stub__Z13cuSumReduce__ILi4EEvPiiPii
jmp .L86
.L97:
movl $2, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl 12(%rsp), %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movslq %r8d, %r8
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L86
movl %ebx, %esi
movq %rbp, %rdi
call _ZL41__device_stub__Z13cuSumReduce__ILi2EEvPiiPii
jmp .L86
.L98:
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl 12(%rsp), %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movslq %r8d, %r8
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L86
movl %ebx, %esi
movq %rbp, %rdi
call _ZL41__device_stub__Z13cuSumReduce__ILi1EEvPiiPii
jmp .L86
.L117:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2031:
.size _Z10sum_reducePii, .-_Z10sum_reducePii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13cuSumReduce__ILi1EEvPii"
.LC1:
.string "_Z13cuSumReduce__ILi2EEvPii"
.LC2:
.string "_Z13cuSumReduce__ILi4EEvPii"
.LC3:
.string "_Z13cuSumReduce__ILi8EEvPii"
.LC4:
.string "_Z13cuSumReduce__ILi16EEvPii"
.LC5:
.string "_Z13cuSumReduce__ILi32EEvPii"
.LC6:
.string "_Z13cuSumReduce__ILi64EEvPii"
.LC7:
.string "_Z13cuSumReduce__ILi128EEvPii"
.LC8:
.string "_Z13cuSumReduce__ILi256EEvPii"
.LC9:
.string "_Z13cuSumReduce__ILi512EEvPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2077:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cuSumReduce__ILi1EEvPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cuSumReduce__ILi2EEvPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cuSumReduce__ILi4EEvPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cuSumReduce__ILi8EEvPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cuSumReduce__ILi16EEvPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cuSumReduce__ILi32EEvPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cuSumReduce__ILi64EEvPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cuSumReduce__ILi128EEvPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cuSumReduce__ILi256EEvPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cuSumReduce__ILi512EEvPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2077:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sum-reduction.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //#include "BLACKCAT_GPU_MATHEMATICS.cuh"
//
//
//
// __global__ void GPU_MATHEMATICS::copy(unsigned* s, const unsigned* ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD) {
//
// unsigned store_index = 0;
// unsigned m1_index = 0;
//
// if (order == 1) {
// copy<<<256,256>>>(s, m1, ranks[order-1]);
//
// } else {
//
// for (unsigned i = 0; i < ranks[order-1]; ++i) {
// copy<<<256,256>>>(&s[store_index], ranks, order-1, s_LD, &m1[m1_index], m1_LD);
// store_index += s_LD[order-1];
// m1_index += m1_LD[order-1];
// }
// }
//}
//
// __global__ void GPU_MATHEMATICS::fill(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, unsigned m1) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// fill<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, m1);
// }
// }
//}
//
//
////----
//
// __global__ void GPU_MATHEMATICS::power(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// //s[i] = pow(m1[i], m2[i]);
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// power<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
//
// __global__ void GPU_MATHEMATICS::multiply(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] * m2[i];
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// multiply<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
//
// __global__ void GPU_MATHEMATICS::divide(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] / m2[i];
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// divide<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
//
// __global__ void GPU_MATHEMATICS::add(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] + m2[i];
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// add<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
//
//
// __global__ void GPU_MATHEMATICS::subtract(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] - m2[i];
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// subtract<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
////-----------------------------------------------Scalar Methods ----------------------------------------------------//
//
//__global__ void GPU_MATHEMATICS::power (unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD,
// const unsigned* m1, const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// // s[i] = pow(m1[i], scal);
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// power<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
//
//__global__ void GPU_MATHEMATICS::multiply(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD,
// const unsigned* m1, const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] * scal;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// multiply<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
//
//__global__ void GPU_MATHEMATICS::divide(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1,
// const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] / scal;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// divide<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
//
//__global__ void GPU_MATHEMATICS::add(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1,
// const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] + scal;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// add<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
//
//__global__ void GPU_MATHEMATICS::subtract(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1,
// const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] - scal;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// subtract<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
// | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //#include "BLACKCAT_GPU_MATHEMATICS.cuh"
//
//
//
// __global__ void GPU_MATHEMATICS::copy(unsigned* s, const unsigned* ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD) {
//
// unsigned store_index = 0;
// unsigned m1_index = 0;
//
// if (order == 1) {
// copy<<<256,256>>>(s, m1, ranks[order-1]);
//
// } else {
//
// for (unsigned i = 0; i < ranks[order-1]; ++i) {
// copy<<<256,256>>>(&s[store_index], ranks, order-1, s_LD, &m1[m1_index], m1_LD);
// store_index += s_LD[order-1];
// m1_index += m1_LD[order-1];
// }
// }
//}
//
// __global__ void GPU_MATHEMATICS::fill(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, unsigned m1) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// fill<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, m1);
// }
// }
//}
//
//
////----
//
// __global__ void GPU_MATHEMATICS::power(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// //s[i] = pow(m1[i], m2[i]);
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// power<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
//
// __global__ void GPU_MATHEMATICS::multiply(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] * m2[i];
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// multiply<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
//
// __global__ void GPU_MATHEMATICS::divide(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] / m2[i];
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// divide<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
//
// __global__ void GPU_MATHEMATICS::add(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] + m2[i];
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// add<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
//
//
// __global__ void GPU_MATHEMATICS::subtract(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] - m2[i];
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// subtract<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
////-----------------------------------------------Scalar Methods ----------------------------------------------------//
//
//__global__ void GPU_MATHEMATICS::power (unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD,
// const unsigned* m1, const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// // s[i] = pow(m1[i], scal);
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// power<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
//
//__global__ void GPU_MATHEMATICS::multiply(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD,
// const unsigned* m1, const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] * scal;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// multiply<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
//
//__global__ void GPU_MATHEMATICS::divide(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1,
// const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] / scal;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// divide<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
//
//__global__ void GPU_MATHEMATICS::add(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1,
// const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] + scal;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// add<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
//
//__global__ void GPU_MATHEMATICS::subtract(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1,
// const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] - scal;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// subtract<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
// | .file "tmpxft_0013f7b7_00000000-6_LAR_PointwiseHighDegree_CUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //#include "BLACKCAT_GPU_MATHEMATICS.cuh"
//
//
//
// __global__ void GPU_MATHEMATICS::copy(unsigned* s, const unsigned* ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD) {
//
// unsigned store_index = 0;
// unsigned m1_index = 0;
//
// if (order == 1) {
// copy<<<256,256>>>(s, m1, ranks[order-1]);
//
// } else {
//
// for (unsigned i = 0; i < ranks[order-1]; ++i) {
// copy<<<256,256>>>(&s[store_index], ranks, order-1, s_LD, &m1[m1_index], m1_LD);
// store_index += s_LD[order-1];
// m1_index += m1_LD[order-1];
// }
// }
//}
//
// __global__ void GPU_MATHEMATICS::fill(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, unsigned m1) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// fill<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, m1);
// }
// }
//}
//
//
////----
//
// __global__ void GPU_MATHEMATICS::power(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// //s[i] = pow(m1[i], m2[i]);
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// power<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
//
// __global__ void GPU_MATHEMATICS::multiply(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] * m2[i];
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// multiply<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
//
// __global__ void GPU_MATHEMATICS::divide(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] / m2[i];
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// divide<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
//
// __global__ void GPU_MATHEMATICS::add(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] + m2[i];
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// add<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
//
//
// __global__ void GPU_MATHEMATICS::subtract(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] - m2[i];
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// subtract<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
////-----------------------------------------------Scalar Methods ----------------------------------------------------//
//
//__global__ void GPU_MATHEMATICS::power (unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD,
// const unsigned* m1, const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// // s[i] = pow(m1[i], scal);
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// power<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
//
//__global__ void GPU_MATHEMATICS::multiply(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD,
// const unsigned* m1, const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] * scal;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// multiply<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
//
//__global__ void GPU_MATHEMATICS::divide(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1,
// const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] / scal;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// divide<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
//
//__global__ void GPU_MATHEMATICS::add(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1,
// const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] + scal;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// add<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
//
//__global__ void GPU_MATHEMATICS::subtract(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1,
// const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] - scal;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// subtract<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
// | #include <hip/hip_runtime.h>
//#include "BLACKCAT_GPU_MATHEMATICS.cuh"
//
//
//
// __global__ void GPU_MATHEMATICS::copy(unsigned* s, const unsigned* ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD) {
//
// unsigned store_index = 0;
// unsigned m1_index = 0;
//
// if (order == 1) {
// copy<<<256,256>>>(s, m1, ranks[order-1]);
//
// } else {
//
// for (unsigned i = 0; i < ranks[order-1]; ++i) {
// copy<<<256,256>>>(&s[store_index], ranks, order-1, s_LD, &m1[m1_index], m1_LD);
// store_index += s_LD[order-1];
// m1_index += m1_LD[order-1];
// }
// }
//}
//
// __global__ void GPU_MATHEMATICS::fill(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, unsigned m1) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// fill<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, m1);
// }
// }
//}
//
//
////----
//
// __global__ void GPU_MATHEMATICS::power(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// //s[i] = pow(m1[i], m2[i]);
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// power<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
//
// __global__ void GPU_MATHEMATICS::multiply(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] * m2[i];
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// multiply<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
//
// __global__ void GPU_MATHEMATICS::divide(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] / m2[i];
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// divide<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
//
// __global__ void GPU_MATHEMATICS::add(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] + m2[i];
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// add<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
//
//
// __global__ void GPU_MATHEMATICS::subtract(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] - m2[i];
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// subtract<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
////-----------------------------------------------Scalar Methods ----------------------------------------------------//
//
//__global__ void GPU_MATHEMATICS::power (unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD,
// const unsigned* m1, const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// // s[i] = pow(m1[i], scal);
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// power<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
//
//__global__ void GPU_MATHEMATICS::multiply(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD,
// const unsigned* m1, const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] * scal;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// multiply<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
//
//__global__ void GPU_MATHEMATICS::divide(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1,
// const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] / scal;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// divide<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
//
//__global__ void GPU_MATHEMATICS::add(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1,
// const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] + scal;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// add<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
//
//__global__ void GPU_MATHEMATICS::subtract(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1,
// const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] - scal;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// subtract<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
// |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//#include "BLACKCAT_GPU_MATHEMATICS.cuh"
//
//
//
// __global__ void GPU_MATHEMATICS::copy(unsigned* s, const unsigned* ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD) {
//
// unsigned store_index = 0;
// unsigned m1_index = 0;
//
// if (order == 1) {
// copy<<<256,256>>>(s, m1, ranks[order-1]);
//
// } else {
//
// for (unsigned i = 0; i < ranks[order-1]; ++i) {
// copy<<<256,256>>>(&s[store_index], ranks, order-1, s_LD, &m1[m1_index], m1_LD);
// store_index += s_LD[order-1];
// m1_index += m1_LD[order-1];
// }
// }
//}
//
// __global__ void GPU_MATHEMATICS::fill(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, unsigned m1) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// fill<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, m1);
// }
// }
//}
//
//
////----
//
// __global__ void GPU_MATHEMATICS::power(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// //s[i] = pow(m1[i], m2[i]);
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// power<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
//
// __global__ void GPU_MATHEMATICS::multiply(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] * m2[i];
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// multiply<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
//
// __global__ void GPU_MATHEMATICS::divide(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] / m2[i];
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// divide<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
//
// __global__ void GPU_MATHEMATICS::add(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] + m2[i];
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// add<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
//
//
// __global__ void GPU_MATHEMATICS::subtract(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] - m2[i];
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// subtract<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
////-----------------------------------------------Scalar Methods ----------------------------------------------------//
//
//__global__ void GPU_MATHEMATICS::power (unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD,
// const unsigned* m1, const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// // s[i] = pow(m1[i], scal);
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// power<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
//
//__global__ void GPU_MATHEMATICS::multiply(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD,
// const unsigned* m1, const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] * scal;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// multiply<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
//
//__global__ void GPU_MATHEMATICS::divide(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1,
// const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] / scal;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// divide<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
//
//__global__ void GPU_MATHEMATICS::add(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1,
// const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] + scal;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// add<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
//
//__global__ void GPU_MATHEMATICS::subtract(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1,
// const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] - scal;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// subtract<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
// | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//#include "BLACKCAT_GPU_MATHEMATICS.cuh"
//
//
//
// __global__ void GPU_MATHEMATICS::copy(unsigned* s, const unsigned* ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD) {
//
// unsigned store_index = 0;
// unsigned m1_index = 0;
//
// if (order == 1) {
// copy<<<256,256>>>(s, m1, ranks[order-1]);
//
// } else {
//
// for (unsigned i = 0; i < ranks[order-1]; ++i) {
// copy<<<256,256>>>(&s[store_index], ranks, order-1, s_LD, &m1[m1_index], m1_LD);
// store_index += s_LD[order-1];
// m1_index += m1_LD[order-1];
// }
// }
//}
//
// __global__ void GPU_MATHEMATICS::fill(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, unsigned m1) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// fill<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, m1);
// }
// }
//}
//
//
////----
//
// __global__ void GPU_MATHEMATICS::power(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// //s[i] = pow(m1[i], m2[i]);
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// power<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
//
// __global__ void GPU_MATHEMATICS::multiply(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] * m2[i];
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// multiply<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
//
// __global__ void GPU_MATHEMATICS::divide(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] / m2[i];
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// divide<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
//
// __global__ void GPU_MATHEMATICS::add(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] + m2[i];
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// add<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
//
//
// __global__ void GPU_MATHEMATICS::subtract(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1, const unsigned* m1_LD,
// const unsigned* m2, const unsigned* m2_LD) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] - m2[i];
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// subtract<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, &m2[m2_LD[order - 1] * i], m2_LD);
// }
// }
//}
//
////-----------------------------------------------Scalar Methods ----------------------------------------------------//
//
//__global__ void GPU_MATHEMATICS::power (unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD,
// const unsigned* m1, const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// // s[i] = pow(m1[i], scal);
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// power<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
//
//__global__ void GPU_MATHEMATICS::multiply(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD,
// const unsigned* m1, const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] * scal;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// multiply<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
//
//__global__ void GPU_MATHEMATICS::divide(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1,
// const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] / scal;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// divide<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
//
//__global__ void GPU_MATHEMATICS::add(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1,
// const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] + scal;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// add<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
//
//__global__ void GPU_MATHEMATICS::subtract(unsigned* s, const unsigned* s_ranks, unsigned order, const unsigned *s_LD, const unsigned* m1,
// const unsigned* m1_LD, const unsigned scal) {
// if (order == 1) {
// for (unsigned i = 0; i < s_ranks[0]; ++i) {
// s[i] = m1[i] - scal;
// }
// } else {
// for (unsigned i = 0; i < s_ranks[order - 1]; ++i) {
// subtract<<<256,256>>>(&s[s_LD[order - 1] * i], s_ranks, order - 1, s_LD, &m1[m1_LD[order - 1] * i], m1_LD, scal);
// }
// }
//}
// | .text
.file "LAR_PointwiseHighDegree_CUDA.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013f7b7_00000000-6_LAR_PointwiseHighDegree_CUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "LAR_PointwiseHighDegree_CUDA.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#include <sys/time.h>
inline double seconds()
{
struct timeval tp;
struct timezone tzp;
int i = gettimeofday(&tp, &tzp);
return ((double)tp.tv_sec + (double)tp.tv_usec * 1.e-6);
}
void intialData(float *input, int n)
{
for (int i=0;i<n;i++)
{
input[i] = (float)rand()/10.f;
}
return;
}
void transposeHost(float *out, const float *in , const int nx, const int ny)
{
for (int j = 0;j<ny;j++)
{
for (int i = 0;i<nx;i++)
{
out[i*ny+j] = in[j*nx+i];
}
}
return ;
}
__global__ void warmup(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[j*nx+i] = in[j*nx+i];
}
}
__global__ void copyGlobalRow(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[j*nx+i] = in[j*nx+i];
}
}
__global__ void copyGlobalCol(float *out, float *in, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[i*ny+j] = in[i*ny+j];
}
}
__global__ void transposeGlobalRow(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[i*ny+j] = in[j*nx+i];
}
}
__global__ void transposeGlobalCol(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[j*nx+i] = in[i*ny+j];
}
}
void verify(const float *host, const float *gpu , const int nx, const int ny)
{
for (int j = 0;j<ny;j++)
{
for (int i = 0;i<nx;i++)
{
if (host[j*nx + i] != gpu[j*nx + i]){
printf("Error\n");
break;
}
}
}
}
int main(){
int nx = 1 <<11;
int ny = 1 <<11;
size_t nBytes = (nx*ny)*sizeof(float);
int nRep = 1;
float ms = 0;
float bw = 0;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
dim3 block (16, 16);
dim3 grid ((nx + block.x - 1) / block.x, (ny + block.y - 1) / block.y);
float *a_h = (float *)malloc(nBytes);
float *hostRef = (float *)malloc(nBytes);
float *gpuRef = (float *)malloc(nBytes);
printf("Matrix %d nx %d ny\n", nx,ny);
intialData(a_h, nx*ny);
transposeHost(hostRef, a_h, nx, ny);
//allocate device memory
float *a_d, *c_d;
cudaMalloc((float **)&a_d,nBytes);
cudaMalloc((float **)&c_d,nBytes);
//copy data
cudaMemcpy(a_d,a_h, nBytes, cudaMemcpyHostToDevice);
warmup<<<grid,block>>>(a_d,c_d,nx,ny);
//copyGlobalRow
cudaEventRecord(start,0);
for (int k=0;k<nRep;k++)
{
copyGlobalRow<<<grid,block>>>(a_d,c_d,nx,ny);
}
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&ms, start, stop);
bw = 2 * nx * ny * sizeof(float)/ms/1e6;
printf("copyGlobalRow: %f ms, effective bandwidth %f GB/s\n",ms/((float)nRep),bw/((float)nRep));
//copyGlobalCol
cudaEventRecord(start);
for (int k=0;k<nRep;k++)
{
copyGlobalCol<<<grid,block>>>(a_d,c_d,nx,ny);
}
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&ms, start, stop);
bw = 2 * nx * ny * sizeof(float)/ms/1e6;
printf("copyGlobalCol: %f ms, effective bandwidth %f GB/s\n",ms/((float)nRep),bw/((float)nRep));
//transposeGlobalRow
cudaEventRecord(start,0);
for (int k=0;k<nRep;k++)
{
transposeGlobalRow<<<grid,block>>>(a_d,c_d,nx,ny);
}
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&ms, start, stop);
bw = 2 * nx * ny * sizeof(float)/ms*1e-6;
printf("transposeGlobalRow: %f ms, effective bandwidth %f GB/s\n",ms/((float)nRep),bw/((float)nRep));
cudaMemcpy(gpuRef,c_d, nBytes, cudaMemcpyDeviceToHost);
verify(hostRef,gpuRef,nx,ny);
//transposeGlobalCol
cudaEventRecord(start,0);
for (int k=0;k<nRep;k++)
{
transposeGlobalCol<<<grid,block>>>(a_d,c_d,nx,ny);
}
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&ms, start, stop);
bw = 2 * nx * ny * sizeof(float)/ms*1e-6;
printf("transposeGlobalCol: %f ms, effective bandwidth %f GB/s\n",ms/((float)nRep),bw/((float)nRep));
cudaMemcpy(gpuRef,c_d, nBytes, cudaMemcpyDeviceToHost);
verify(hostRef,gpuRef,nx,ny);
cudaFree(a_d);
cudaFree(c_d);
free(hostRef);
free(gpuRef);
free(a_h);
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z18transposeGlobalColPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R0, c[0x0][0x174], R5 ; /* 0x00005d0000027a24 */
/* 0x000fe200078e0205 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE.U32 R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0004 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD R5, R5, c[0x0][0x170], R0 ; /* 0x00005c0005057a24 */
/* 0x000fc800078e0200 */
/*0100*/ IMAD.WIDE.U32 R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0004 */
/*0110*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z18transposeGlobalRowPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R5, c[0x0][0x170], R0 ; /* 0x00005c0005027a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE.U32 R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0004 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD R5, R0, c[0x0][0x174], R5 ; /* 0x00005d0000057a24 */
/* 0x000fc800078e0205 */
/*0100*/ IMAD.WIDE.U32 R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0004 */
/*0110*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13copyGlobalColPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R0, c[0x0][0x174], R3 ; /* 0x00005d0000007a24 */
/* 0x000fe200078e0203 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0005 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0005 */
/*0100*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13copyGlobalRowPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x170], R0 ; /* 0x00005c0003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0005 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0005 */
/*0100*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z6warmupPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x170], R0 ; /* 0x00005c0003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0005 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0005 */
/*0100*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#include <sys/time.h>
inline double seconds()
{
struct timeval tp;
struct timezone tzp;
int i = gettimeofday(&tp, &tzp);
return ((double)tp.tv_sec + (double)tp.tv_usec * 1.e-6);
}
void intialData(float *input, int n)
{
for (int i=0;i<n;i++)
{
input[i] = (float)rand()/10.f;
}
return;
}
void transposeHost(float *out, const float *in , const int nx, const int ny)
{
for (int j = 0;j<ny;j++)
{
for (int i = 0;i<nx;i++)
{
out[i*ny+j] = in[j*nx+i];
}
}
return ;
}
__global__ void warmup(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[j*nx+i] = in[j*nx+i];
}
}
__global__ void copyGlobalRow(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[j*nx+i] = in[j*nx+i];
}
}
__global__ void copyGlobalCol(float *out, float *in, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[i*ny+j] = in[i*ny+j];
}
}
__global__ void transposeGlobalRow(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[i*ny+j] = in[j*nx+i];
}
}
__global__ void transposeGlobalCol(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[j*nx+i] = in[i*ny+j];
}
}
void verify(const float *host, const float *gpu , const int nx, const int ny)
{
for (int j = 0;j<ny;j++)
{
for (int i = 0;i<nx;i++)
{
if (host[j*nx + i] != gpu[j*nx + i]){
printf("Error\n");
break;
}
}
}
}
int main(){
int nx = 1 <<11;
int ny = 1 <<11;
size_t nBytes = (nx*ny)*sizeof(float);
int nRep = 1;
float ms = 0;
float bw = 0;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
dim3 block (16, 16);
dim3 grid ((nx + block.x - 1) / block.x, (ny + block.y - 1) / block.y);
float *a_h = (float *)malloc(nBytes);
float *hostRef = (float *)malloc(nBytes);
float *gpuRef = (float *)malloc(nBytes);
printf("Matrix %d nx %d ny\n", nx,ny);
intialData(a_h, nx*ny);
transposeHost(hostRef, a_h, nx, ny);
//allocate device memory
float *a_d, *c_d;
cudaMalloc((float **)&a_d,nBytes);
cudaMalloc((float **)&c_d,nBytes);
//copy data
cudaMemcpy(a_d,a_h, nBytes, cudaMemcpyHostToDevice);
warmup<<<grid,block>>>(a_d,c_d,nx,ny);
//copyGlobalRow
cudaEventRecord(start,0);
for (int k=0;k<nRep;k++)
{
copyGlobalRow<<<grid,block>>>(a_d,c_d,nx,ny);
}
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&ms, start, stop);
bw = 2 * nx * ny * sizeof(float)/ms/1e6;
printf("copyGlobalRow: %f ms, effective bandwidth %f GB/s\n",ms/((float)nRep),bw/((float)nRep));
//copyGlobalCol
cudaEventRecord(start);
for (int k=0;k<nRep;k++)
{
copyGlobalCol<<<grid,block>>>(a_d,c_d,nx,ny);
}
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&ms, start, stop);
bw = 2 * nx * ny * sizeof(float)/ms/1e6;
printf("copyGlobalCol: %f ms, effective bandwidth %f GB/s\n",ms/((float)nRep),bw/((float)nRep));
//transposeGlobalRow
cudaEventRecord(start,0);
for (int k=0;k<nRep;k++)
{
transposeGlobalRow<<<grid,block>>>(a_d,c_d,nx,ny);
}
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&ms, start, stop);
bw = 2 * nx * ny * sizeof(float)/ms*1e-6;
printf("transposeGlobalRow: %f ms, effective bandwidth %f GB/s\n",ms/((float)nRep),bw/((float)nRep));
cudaMemcpy(gpuRef,c_d, nBytes, cudaMemcpyDeviceToHost);
verify(hostRef,gpuRef,nx,ny);
//transposeGlobalCol
cudaEventRecord(start,0);
for (int k=0;k<nRep;k++)
{
transposeGlobalCol<<<grid,block>>>(a_d,c_d,nx,ny);
}
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&ms, start, stop);
bw = 2 * nx * ny * sizeof(float)/ms*1e-6;
printf("transposeGlobalCol: %f ms, effective bandwidth %f GB/s\n",ms/((float)nRep),bw/((float)nRep));
cudaMemcpy(gpuRef,c_d, nBytes, cudaMemcpyDeviceToHost);
verify(hostRef,gpuRef,nx,ny);
cudaFree(a_d);
cudaFree(c_d);
free(hostRef);
free(gpuRef);
free(a_h);
cudaDeviceReset();
return 0;
} | .file "tmpxft_00142f17_00000000-6_matrixTranspose.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10intialDataPfi
.type _Z10intialDataPfi, @function
_Z10intialDataPfi:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2058:
.size _Z10intialDataPfi, .-_Z10intialDataPfi
.globl _Z13transposeHostPfPKfii
.type _Z13transposeHostPfPKfii, @function
_Z13transposeHostPfPKfii:
.LFB2059:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L19
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rsi, %rbx
movl %edx, %r11d
movslq %ecx, %r8
salq $2, %r8
movl $0, %r10d
movl $0, %r9d
movslq %edx, %rbp
jmp .L13
.L15:
movslq %r10d, %rdx
leaq (%rbx,%rdx,4), %rax
addq %rbp, %rdx
leaq (%rbx,%rdx,4), %rsi
movq %rdi, %rdx
.L14:
movss (%rax), %xmm0
movss %xmm0, (%rdx)
addq $4, %rax
addq %r8, %rdx
cmpq %rsi, %rax
jne .L14
.L16:
addl $1, %r9d
addq $4, %rdi
addl %r11d, %r10d
cmpl %r9d, %ecx
je .L11
.L13:
testl %r11d, %r11d
jg .L15
jmp .L16
.L11:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2059:
.size _Z13transposeHostPfPKfii, .-_Z13transposeHostPfPKfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Error\n"
.text
.globl _Z6verifyPKfS0_ii
.type _Z6verifyPKfS0_ii, @function
_Z6verifyPKfS0_ii:
.LFB2060:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L33
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %rsi, %rbp
movl %edx, %r12d
movl %ecx, %r15d
movl $0, %r14d
movl $0, %r13d
jmp .L24
.L30:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L27:
addl $1, %r13d
addl %r12d, %r14d
cmpl %r13d, %r15d
je .L22
.L24:
testl %r12d, %r12d
jle .L27
movslq %r14d, %rcx
leaq 0(,%rcx,4), %rax
movslq %r12d, %rdx
addq %rcx, %rdx
salq $2, %rdx
.L28:
movss (%rbx,%rax), %xmm0
ucomiss 0(%rbp,%rax), %xmm0
jp .L30
jne .L30
addq $4, %rax
cmpq %rdx, %rax
jne .L28
jmp .L27
.L22:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2060:
.size _Z6verifyPKfS0_ii, .-_Z6verifyPKfS0_ii
.globl _Z29__device_stub__Z6warmupPfS_iiPfS_ii
.type _Z29__device_stub__Z6warmupPfS_iiPfS_ii, @function
_Z29__device_stub__Z6warmupPfS_iiPfS_ii:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L41
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6warmupPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z29__device_stub__Z6warmupPfS_iiPfS_ii, .-_Z29__device_stub__Z6warmupPfS_iiPfS_ii
.globl _Z6warmupPfS_ii
.type _Z6warmupPfS_ii, @function
_Z6warmupPfS_ii:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6warmupPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z6warmupPfS_ii, .-_Z6warmupPfS_ii
.globl _Z37__device_stub__Z13copyGlobalRowPfS_iiPfS_ii
.type _Z37__device_stub__Z13copyGlobalRowPfS_iiPfS_ii, @function
_Z37__device_stub__Z13copyGlobalRowPfS_iiPfS_ii:
.LFB2088:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L48
.L44:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L49
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13copyGlobalRowPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L44
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z37__device_stub__Z13copyGlobalRowPfS_iiPfS_ii, .-_Z37__device_stub__Z13copyGlobalRowPfS_iiPfS_ii
.globl _Z13copyGlobalRowPfS_ii
.type _Z13copyGlobalRowPfS_ii, @function
_Z13copyGlobalRowPfS_ii:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13copyGlobalRowPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z13copyGlobalRowPfS_ii, .-_Z13copyGlobalRowPfS_ii
.globl _Z37__device_stub__Z13copyGlobalColPfS_iiPfS_ii
.type _Z37__device_stub__Z13copyGlobalColPfS_iiPfS_ii, @function
_Z37__device_stub__Z13copyGlobalColPfS_iiPfS_ii:
.LFB2090:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L56
.L52:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L57
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13copyGlobalColPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L52
.L57:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z37__device_stub__Z13copyGlobalColPfS_iiPfS_ii, .-_Z37__device_stub__Z13copyGlobalColPfS_iiPfS_ii
.globl _Z13copyGlobalColPfS_ii
.type _Z13copyGlobalColPfS_ii, @function
_Z13copyGlobalColPfS_ii:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13copyGlobalColPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z13copyGlobalColPfS_ii, .-_Z13copyGlobalColPfS_ii
.globl _Z42__device_stub__Z18transposeGlobalRowPfS_iiPfS_ii
.type _Z42__device_stub__Z18transposeGlobalRowPfS_iiPfS_ii, @function
_Z42__device_stub__Z18transposeGlobalRowPfS_iiPfS_ii:
.LFB2092:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L64
.L60:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L65
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L64:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18transposeGlobalRowPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L60
.L65:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z42__device_stub__Z18transposeGlobalRowPfS_iiPfS_ii, .-_Z42__device_stub__Z18transposeGlobalRowPfS_iiPfS_ii
.globl _Z18transposeGlobalRowPfS_ii
.type _Z18transposeGlobalRowPfS_ii, @function
_Z18transposeGlobalRowPfS_ii:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18transposeGlobalRowPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z18transposeGlobalRowPfS_ii, .-_Z18transposeGlobalRowPfS_ii
.globl _Z42__device_stub__Z18transposeGlobalColPfS_iiPfS_ii
.type _Z42__device_stub__Z18transposeGlobalColPfS_iiPfS_ii, @function
_Z42__device_stub__Z18transposeGlobalColPfS_iiPfS_ii:
.LFB2094:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L72
.L68:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L73
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L72:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18transposeGlobalColPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L68
.L73:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2094:
.size _Z42__device_stub__Z18transposeGlobalColPfS_iiPfS_ii, .-_Z42__device_stub__Z18transposeGlobalColPfS_iiPfS_ii
.globl _Z18transposeGlobalColPfS_ii
.type _Z18transposeGlobalColPfS_ii, @function
_Z18transposeGlobalColPfS_ii:
.LFB2095:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18transposeGlobalColPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _Z18transposeGlobalColPfS_ii, .-_Z18transposeGlobalColPfS_ii
.section .rodata.str1.1
.LC3:
.string "Matrix %d nx %d ny\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "copyGlobalRow: %f ms, effective bandwidth %f GB/s\n"
.align 8
.LC7:
.string "copyGlobalCol: %f ms, effective bandwidth %f GB/s\n"
.align 8
.LC9:
.string "transposeGlobalRow: %f ms, effective bandwidth %f GB/s\n"
.align 8
.LC10:
.string "transposeGlobalCol: %f ms, effective bandwidth %f GB/s\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $0x00000000, 12(%rsp)
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $1, 56(%rsp)
movl $128, 60(%rsp)
movl $128, 64(%rsp)
movl $1, 68(%rsp)
movl $16777216, %edi
call malloc@PLT
movq %rax, %r12
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbp
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbx
movl $2048, %ecx
movl $2048, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4194304, %esi
movq %r12, %rdi
call _Z10intialDataPfi
movl $2048, %ecx
movl $2048, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _Z13transposeHostPfPKfii
leaq 32(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $16777216, %edx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 48(%rsp)
movl $16, 52(%rsp)
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L84
.L77:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L78
movl $2048, %ecx
movl $2048, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z37__device_stub__Z13copyGlobalRowPfS_iiPfS_ii
.L78:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 12(%rsp), %xmm0
movss .LC4(%rip), %xmm1
divss %xmm0, %xmm1
divss .LC5(%rip), %xmm1
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L85
.L79:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 12(%rsp), %xmm0
movss .LC4(%rip), %xmm1
divss %xmm0, %xmm1
divss .LC5(%rip), %xmm1
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L80
movl $2048, %ecx
movl $2048, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z42__device_stub__Z18transposeGlobalRowPfS_iiPfS_ii
.L80:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 12(%rsp), %xmm0
movss .LC4(%rip), %xmm1
divss %xmm0, %xmm1
cvtss2sd %xmm1, %xmm1
mulsd .LC8(%rip), %xmm1
cvtsd2ss %xmm1, %xmm1
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $16777216, %edx
movq 40(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $2048, %ecx
movl $2048, %edx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z6verifyPKfS0_ii
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L86
.L81:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 12(%rsp), %xmm0
movss .LC4(%rip), %xmm1
divss %xmm0, %xmm1
cvtss2sd %xmm1, %xmm1
mulsd .LC8(%rip), %xmm1
cvtsd2ss %xmm1, %xmm1
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $16777216, %edx
movq 40(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $2048, %ecx
movl $2048, %edx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z6verifyPKfS0_ii
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
call cudaDeviceReset@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L87
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L84:
.cfi_restore_state
movl $2048, %ecx
movl $2048, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z29__device_stub__Z6warmupPfS_iiPfS_ii
jmp .L77
.L85:
movl $2048, %ecx
movl $2048, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z37__device_stub__Z13copyGlobalColPfS_iiPfS_ii
jmp .L79
.L86:
movl $2048, %ecx
movl $2048, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z42__device_stub__Z18transposeGlobalColPfS_iiPfS_ii
jmp .L81
.L87:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z18transposeGlobalColPfS_ii"
.LC12:
.string "_Z18transposeGlobalRowPfS_ii"
.LC13:
.string "_Z13copyGlobalColPfS_ii"
.LC14:
.string "_Z13copyGlobalRowPfS_ii"
.LC15:
.string "_Z6warmupPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2097:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z18transposeGlobalColPfS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z18transposeGlobalRowPfS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z13copyGlobalColPfS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z13copyGlobalRowPfS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z6warmupPfS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1092616192
.align 4
.LC4:
.long 1275068416
.align 4
.LC5:
.long 1232348160
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
#include <sys/time.h>
inline double seconds()
{
struct timeval tp;
struct timezone tzp;
int i = gettimeofday(&tp, &tzp);
return ((double)tp.tv_sec + (double)tp.tv_usec * 1.e-6);
}
void intialData(float *input, int n)
{
for (int i=0;i<n;i++)
{
input[i] = (float)rand()/10.f;
}
return;
}
void transposeHost(float *out, const float *in , const int nx, const int ny)
{
for (int j = 0;j<ny;j++)
{
for (int i = 0;i<nx;i++)
{
out[i*ny+j] = in[j*nx+i];
}
}
return ;
}
__global__ void warmup(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[j*nx+i] = in[j*nx+i];
}
}
__global__ void copyGlobalRow(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[j*nx+i] = in[j*nx+i];
}
}
__global__ void copyGlobalCol(float *out, float *in, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[i*ny+j] = in[i*ny+j];
}
}
__global__ void transposeGlobalRow(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[i*ny+j] = in[j*nx+i];
}
}
__global__ void transposeGlobalCol(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[j*nx+i] = in[i*ny+j];
}
}
void verify(const float *host, const float *gpu , const int nx, const int ny)
{
for (int j = 0;j<ny;j++)
{
for (int i = 0;i<nx;i++)
{
if (host[j*nx + i] != gpu[j*nx + i]){
printf("Error\n");
break;
}
}
}
}
int main(){
int nx = 1 <<11;
int ny = 1 <<11;
size_t nBytes = (nx*ny)*sizeof(float);
int nRep = 1;
float ms = 0;
float bw = 0;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
dim3 block (16, 16);
dim3 grid ((nx + block.x - 1) / block.x, (ny + block.y - 1) / block.y);
float *a_h = (float *)malloc(nBytes);
float *hostRef = (float *)malloc(nBytes);
float *gpuRef = (float *)malloc(nBytes);
printf("Matrix %d nx %d ny\n", nx,ny);
intialData(a_h, nx*ny);
transposeHost(hostRef, a_h, nx, ny);
//allocate device memory
float *a_d, *c_d;
cudaMalloc((float **)&a_d,nBytes);
cudaMalloc((float **)&c_d,nBytes);
//copy data
cudaMemcpy(a_d,a_h, nBytes, cudaMemcpyHostToDevice);
warmup<<<grid,block>>>(a_d,c_d,nx,ny);
//copyGlobalRow
cudaEventRecord(start,0);
for (int k=0;k<nRep;k++)
{
copyGlobalRow<<<grid,block>>>(a_d,c_d,nx,ny);
}
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&ms, start, stop);
bw = 2 * nx * ny * sizeof(float)/ms/1e6;
printf("copyGlobalRow: %f ms, effective bandwidth %f GB/s\n",ms/((float)nRep),bw/((float)nRep));
//copyGlobalCol
cudaEventRecord(start);
for (int k=0;k<nRep;k++)
{
copyGlobalCol<<<grid,block>>>(a_d,c_d,nx,ny);
}
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&ms, start, stop);
bw = 2 * nx * ny * sizeof(float)/ms/1e6;
printf("copyGlobalCol: %f ms, effective bandwidth %f GB/s\n",ms/((float)nRep),bw/((float)nRep));
//transposeGlobalRow
cudaEventRecord(start,0);
for (int k=0;k<nRep;k++)
{
transposeGlobalRow<<<grid,block>>>(a_d,c_d,nx,ny);
}
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&ms, start, stop);
bw = 2 * nx * ny * sizeof(float)/ms*1e-6;
printf("transposeGlobalRow: %f ms, effective bandwidth %f GB/s\n",ms/((float)nRep),bw/((float)nRep));
cudaMemcpy(gpuRef,c_d, nBytes, cudaMemcpyDeviceToHost);
verify(hostRef,gpuRef,nx,ny);
//transposeGlobalCol
cudaEventRecord(start,0);
for (int k=0;k<nRep;k++)
{
transposeGlobalCol<<<grid,block>>>(a_d,c_d,nx,ny);
}
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&ms, start, stop);
bw = 2 * nx * ny * sizeof(float)/ms*1e-6;
printf("transposeGlobalCol: %f ms, effective bandwidth %f GB/s\n",ms/((float)nRep),bw/((float)nRep));
cudaMemcpy(gpuRef,c_d, nBytes, cudaMemcpyDeviceToHost);
verify(hostRef,gpuRef,nx,ny);
cudaFree(a_d);
cudaFree(c_d);
free(hostRef);
free(gpuRef);
free(a_h);
cudaDeviceReset();
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
inline double seconds()
{
struct timeval tp;
struct timezone tzp;
int i = gettimeofday(&tp, &tzp);
return ((double)tp.tv_sec + (double)tp.tv_usec * 1.e-6);
}
void intialData(float *input, int n)
{
for (int i=0;i<n;i++)
{
input[i] = (float)rand()/10.f;
}
return;
}
void transposeHost(float *out, const float *in , const int nx, const int ny)
{
for (int j = 0;j<ny;j++)
{
for (int i = 0;i<nx;i++)
{
out[i*ny+j] = in[j*nx+i];
}
}
return ;
}
__global__ void warmup(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[j*nx+i] = in[j*nx+i];
}
}
__global__ void copyGlobalRow(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[j*nx+i] = in[j*nx+i];
}
}
__global__ void copyGlobalCol(float *out, float *in, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[i*ny+j] = in[i*ny+j];
}
}
__global__ void transposeGlobalRow(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[i*ny+j] = in[j*nx+i];
}
}
__global__ void transposeGlobalCol(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[j*nx+i] = in[i*ny+j];
}
}
void verify(const float *host, const float *gpu , const int nx, const int ny)
{
for (int j = 0;j<ny;j++)
{
for (int i = 0;i<nx;i++)
{
if (host[j*nx + i] != gpu[j*nx + i]){
printf("Error\n");
break;
}
}
}
}
int main(){
int nx = 1 <<11;
int ny = 1 <<11;
size_t nBytes = (nx*ny)*sizeof(float);
int nRep = 1;
float ms = 0;
float bw = 0;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
dim3 block (16, 16);
dim3 grid ((nx + block.x - 1) / block.x, (ny + block.y - 1) / block.y);
float *a_h = (float *)malloc(nBytes);
float *hostRef = (float *)malloc(nBytes);
float *gpuRef = (float *)malloc(nBytes);
printf("Matrix %d nx %d ny\n", nx,ny);
intialData(a_h, nx*ny);
transposeHost(hostRef, a_h, nx, ny);
//allocate device memory
float *a_d, *c_d;
hipMalloc((float **)&a_d,nBytes);
hipMalloc((float **)&c_d,nBytes);
//copy data
hipMemcpy(a_d,a_h, nBytes, hipMemcpyHostToDevice);
warmup<<<grid,block>>>(a_d,c_d,nx,ny);
//copyGlobalRow
hipEventRecord(start,0);
for (int k=0;k<nRep;k++)
{
copyGlobalRow<<<grid,block>>>(a_d,c_d,nx,ny);
}
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&ms, start, stop);
bw = 2 * nx * ny * sizeof(float)/ms/1e6;
printf("copyGlobalRow: %f ms, effective bandwidth %f GB/s\n",ms/((float)nRep),bw/((float)nRep));
//copyGlobalCol
hipEventRecord(start);
for (int k=0;k<nRep;k++)
{
copyGlobalCol<<<grid,block>>>(a_d,c_d,nx,ny);
}
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&ms, start, stop);
bw = 2 * nx * ny * sizeof(float)/ms/1e6;
printf("copyGlobalCol: %f ms, effective bandwidth %f GB/s\n",ms/((float)nRep),bw/((float)nRep));
//transposeGlobalRow
hipEventRecord(start,0);
for (int k=0;k<nRep;k++)
{
transposeGlobalRow<<<grid,block>>>(a_d,c_d,nx,ny);
}
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&ms, start, stop);
bw = 2 * nx * ny * sizeof(float)/ms*1e-6;
printf("transposeGlobalRow: %f ms, effective bandwidth %f GB/s\n",ms/((float)nRep),bw/((float)nRep));
hipMemcpy(gpuRef,c_d, nBytes, hipMemcpyDeviceToHost);
verify(hostRef,gpuRef,nx,ny);
//transposeGlobalCol
hipEventRecord(start,0);
for (int k=0;k<nRep;k++)
{
transposeGlobalCol<<<grid,block>>>(a_d,c_d,nx,ny);
}
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&ms, start, stop);
bw = 2 * nx * ny * sizeof(float)/ms*1e-6;
printf("transposeGlobalCol: %f ms, effective bandwidth %f GB/s\n",ms/((float)nRep),bw/((float)nRep));
hipMemcpy(gpuRef,c_d, nBytes, hipMemcpyDeviceToHost);
verify(hostRef,gpuRef,nx,ny);
hipFree(a_d);
hipFree(c_d);
free(hostRef);
free(gpuRef);
free(a_h);
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
inline double seconds()
{
struct timeval tp;
struct timezone tzp;
int i = gettimeofday(&tp, &tzp);
return ((double)tp.tv_sec + (double)tp.tv_usec * 1.e-6);
}
void intialData(float *input, int n)
{
for (int i=0;i<n;i++)
{
input[i] = (float)rand()/10.f;
}
return;
}
void transposeHost(float *out, const float *in , const int nx, const int ny)
{
for (int j = 0;j<ny;j++)
{
for (int i = 0;i<nx;i++)
{
out[i*ny+j] = in[j*nx+i];
}
}
return ;
}
__global__ void warmup(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[j*nx+i] = in[j*nx+i];
}
}
__global__ void copyGlobalRow(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[j*nx+i] = in[j*nx+i];
}
}
__global__ void copyGlobalCol(float *out, float *in, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[i*ny+j] = in[i*ny+j];
}
}
__global__ void transposeGlobalRow(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[i*ny+j] = in[j*nx+i];
}
}
__global__ void transposeGlobalCol(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[j*nx+i] = in[i*ny+j];
}
}
void verify(const float *host, const float *gpu , const int nx, const int ny)
{
for (int j = 0;j<ny;j++)
{
for (int i = 0;i<nx;i++)
{
if (host[j*nx + i] != gpu[j*nx + i]){
printf("Error\n");
break;
}
}
}
}
int main(){
int nx = 1 <<11;
int ny = 1 <<11;
size_t nBytes = (nx*ny)*sizeof(float);
int nRep = 1;
float ms = 0;
float bw = 0;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
dim3 block (16, 16);
dim3 grid ((nx + block.x - 1) / block.x, (ny + block.y - 1) / block.y);
float *a_h = (float *)malloc(nBytes);
float *hostRef = (float *)malloc(nBytes);
float *gpuRef = (float *)malloc(nBytes);
printf("Matrix %d nx %d ny\n", nx,ny);
intialData(a_h, nx*ny);
transposeHost(hostRef, a_h, nx, ny);
//allocate device memory
float *a_d, *c_d;
hipMalloc((float **)&a_d,nBytes);
hipMalloc((float **)&c_d,nBytes);
//copy data
hipMemcpy(a_d,a_h, nBytes, hipMemcpyHostToDevice);
warmup<<<grid,block>>>(a_d,c_d,nx,ny);
//copyGlobalRow
hipEventRecord(start,0);
for (int k=0;k<nRep;k++)
{
copyGlobalRow<<<grid,block>>>(a_d,c_d,nx,ny);
}
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&ms, start, stop);
bw = 2 * nx * ny * sizeof(float)/ms/1e6;
printf("copyGlobalRow: %f ms, effective bandwidth %f GB/s\n",ms/((float)nRep),bw/((float)nRep));
//copyGlobalCol
hipEventRecord(start);
for (int k=0;k<nRep;k++)
{
copyGlobalCol<<<grid,block>>>(a_d,c_d,nx,ny);
}
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&ms, start, stop);
bw = 2 * nx * ny * sizeof(float)/ms/1e6;
printf("copyGlobalCol: %f ms, effective bandwidth %f GB/s\n",ms/((float)nRep),bw/((float)nRep));
//transposeGlobalRow
hipEventRecord(start,0);
for (int k=0;k<nRep;k++)
{
transposeGlobalRow<<<grid,block>>>(a_d,c_d,nx,ny);
}
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&ms, start, stop);
bw = 2 * nx * ny * sizeof(float)/ms*1e-6;
printf("transposeGlobalRow: %f ms, effective bandwidth %f GB/s\n",ms/((float)nRep),bw/((float)nRep));
hipMemcpy(gpuRef,c_d, nBytes, hipMemcpyDeviceToHost);
verify(hostRef,gpuRef,nx,ny);
//transposeGlobalCol
hipEventRecord(start,0);
for (int k=0;k<nRep;k++)
{
transposeGlobalCol<<<grid,block>>>(a_d,c_d,nx,ny);
}
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&ms, start, stop);
bw = 2 * nx * ny * sizeof(float)/ms*1e-6;
printf("transposeGlobalCol: %f ms, effective bandwidth %f GB/s\n",ms/((float)nRep),bw/((float)nRep));
hipMemcpy(gpuRef,c_d, nBytes, hipMemcpyDeviceToHost);
verify(hostRef,gpuRef,nx,ny);
hipFree(a_d);
hipFree(c_d);
free(hostRef);
free(gpuRef);
free(a_h);
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6warmupPfS_ii
.globl _Z6warmupPfS_ii
.p2align 8
.type _Z6warmupPfS_ii,@function
_Z6warmupPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6warmupPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6warmupPfS_ii, .Lfunc_end0-_Z6warmupPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13copyGlobalRowPfS_ii
.globl _Z13copyGlobalRowPfS_ii
.p2align 8
.type _Z13copyGlobalRowPfS_ii,@function
_Z13copyGlobalRowPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13copyGlobalRowPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13copyGlobalRowPfS_ii, .Lfunc_end1-_Z13copyGlobalRowPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13copyGlobalColPfS_ii
.globl _Z13copyGlobalColPfS_ii
.p2align 8
.type _Z13copyGlobalColPfS_ii,@function
_Z13copyGlobalColPfS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB2_2
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
v_mov_b32_e32 v3, 0
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13copyGlobalColPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z13copyGlobalColPfS_ii, .Lfunc_end2-_Z13copyGlobalColPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z18transposeGlobalRowPfS_ii
.globl _Z18transposeGlobalRowPfS_ii
.p2align 8
.type _Z18transposeGlobalRowPfS_ii,@function
_Z18transposeGlobalRowPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB3_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[4:5], null, v0, s5, v[1:2]
v_mov_b32_e32 v5, v3
v_lshlrev_b64 v[0:1], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB3_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18transposeGlobalRowPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z18transposeGlobalRowPfS_ii, .Lfunc_end3-_Z18transposeGlobalRowPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z18transposeGlobalColPfS_ii
.globl _Z18transposeGlobalColPfS_ii
.p2align 8
.type _Z18transposeGlobalColPfS_ii,@function
_Z18transposeGlobalColPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB4_2
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s5, v[1:2]
v_mov_b32_e32 v3, 0
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b32 v2, v[4:5], off
v_mad_u64_u32 v[4:5], null, v1, s4, v[0:1]
v_mov_b32_e32 v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[4:5]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB4_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18transposeGlobalColPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z18transposeGlobalColPfS_ii, .Lfunc_end4-_Z18transposeGlobalColPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6warmupPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6warmupPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13copyGlobalRowPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13copyGlobalRowPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13copyGlobalColPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13copyGlobalColPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18transposeGlobalRowPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18transposeGlobalRowPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18transposeGlobalColPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18transposeGlobalColPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
inline double seconds()
{
struct timeval tp;
struct timezone tzp;
int i = gettimeofday(&tp, &tzp);
return ((double)tp.tv_sec + (double)tp.tv_usec * 1.e-6);
}
void intialData(float *input, int n)
{
for (int i=0;i<n;i++)
{
input[i] = (float)rand()/10.f;
}
return;
}
void transposeHost(float *out, const float *in , const int nx, const int ny)
{
for (int j = 0;j<ny;j++)
{
for (int i = 0;i<nx;i++)
{
out[i*ny+j] = in[j*nx+i];
}
}
return ;
}
__global__ void warmup(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[j*nx+i] = in[j*nx+i];
}
}
__global__ void copyGlobalRow(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[j*nx+i] = in[j*nx+i];
}
}
__global__ void copyGlobalCol(float *out, float *in, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[i*ny+j] = in[i*ny+j];
}
}
__global__ void transposeGlobalRow(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[i*ny+j] = in[j*nx+i];
}
}
__global__ void transposeGlobalCol(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[j*nx+i] = in[i*ny+j];
}
}
void verify(const float *host, const float *gpu , const int nx, const int ny)
{
for (int j = 0;j<ny;j++)
{
for (int i = 0;i<nx;i++)
{
if (host[j*nx + i] != gpu[j*nx + i]){
printf("Error\n");
break;
}
}
}
}
int main(){
int nx = 1 <<11;
int ny = 1 <<11;
size_t nBytes = (nx*ny)*sizeof(float);
int nRep = 1;
float ms = 0;
float bw = 0;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
dim3 block (16, 16);
dim3 grid ((nx + block.x - 1) / block.x, (ny + block.y - 1) / block.y);
float *a_h = (float *)malloc(nBytes);
float *hostRef = (float *)malloc(nBytes);
float *gpuRef = (float *)malloc(nBytes);
printf("Matrix %d nx %d ny\n", nx,ny);
intialData(a_h, nx*ny);
transposeHost(hostRef, a_h, nx, ny);
//allocate device memory
float *a_d, *c_d;
hipMalloc((float **)&a_d,nBytes);
hipMalloc((float **)&c_d,nBytes);
//copy data
hipMemcpy(a_d,a_h, nBytes, hipMemcpyHostToDevice);
warmup<<<grid,block>>>(a_d,c_d,nx,ny);
//copyGlobalRow
hipEventRecord(start,0);
for (int k=0;k<nRep;k++)
{
copyGlobalRow<<<grid,block>>>(a_d,c_d,nx,ny);
}
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&ms, start, stop);
bw = 2 * nx * ny * sizeof(float)/ms/1e6;
printf("copyGlobalRow: %f ms, effective bandwidth %f GB/s\n",ms/((float)nRep),bw/((float)nRep));
//copyGlobalCol
hipEventRecord(start);
for (int k=0;k<nRep;k++)
{
copyGlobalCol<<<grid,block>>>(a_d,c_d,nx,ny);
}
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&ms, start, stop);
bw = 2 * nx * ny * sizeof(float)/ms/1e6;
printf("copyGlobalCol: %f ms, effective bandwidth %f GB/s\n",ms/((float)nRep),bw/((float)nRep));
//transposeGlobalRow
hipEventRecord(start,0);
for (int k=0;k<nRep;k++)
{
transposeGlobalRow<<<grid,block>>>(a_d,c_d,nx,ny);
}
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&ms, start, stop);
bw = 2 * nx * ny * sizeof(float)/ms*1e-6;
printf("transposeGlobalRow: %f ms, effective bandwidth %f GB/s\n",ms/((float)nRep),bw/((float)nRep));
hipMemcpy(gpuRef,c_d, nBytes, hipMemcpyDeviceToHost);
verify(hostRef,gpuRef,nx,ny);
//transposeGlobalCol
hipEventRecord(start,0);
for (int k=0;k<nRep;k++)
{
transposeGlobalCol<<<grid,block>>>(a_d,c_d,nx,ny);
}
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&ms, start, stop);
bw = 2 * nx * ny * sizeof(float)/ms*1e-6;
printf("transposeGlobalCol: %f ms, effective bandwidth %f GB/s\n",ms/((float)nRep),bw/((float)nRep));
hipMemcpy(gpuRef,c_d, nBytes, hipMemcpyDeviceToHost);
verify(hostRef,gpuRef,nx,ny);
hipFree(a_d);
hipFree(c_d);
free(hostRef);
free(gpuRef);
free(a_h);
hipDeviceReset();
return 0;
} | .text
.file "matrixTranspose.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10intialDataPfi
.LCPI0_0:
.long 0x41200000 # float 10
.text
.globl _Z10intialDataPfi
.p2align 4, 0x90
.type _Z10intialDataPfi,@function
_Z10intialDataPfi: # @_Z10intialDataPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss .LCPI0_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
retq
.Lfunc_end0:
.size _Z10intialDataPfi, .Lfunc_end0-_Z10intialDataPfi
.cfi_endproc
# -- End function
.globl _Z13transposeHostPfPKfii # -- Begin function _Z13transposeHostPfPKfii
.p2align 4, 0x90
.type _Z13transposeHostPfPKfii,@function
_Z13transposeHostPfPKfii: # @_Z13transposeHostPfPKfii
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB1_7
# %bb.1: # %.preheader.lr.ph
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %ecx, %eax
movl %edx, %ecx
leaq (,%rax,4), %r8
xorl %r9d, %r9d
xorl %r10d, %r10d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r10
addl %edx, %r9d
addq $4, %rdi
cmpq %rax, %r10
je .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %edx, %edx
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %r9d, %r11d
leaq (%rsi,%r11,4), %r11
movq %rdi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r11,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rbx)
incq %r14
addq %r8, %rbx
cmpq %r14, %rcx
jne .LBB1_4
jmp .LBB1_5
.LBB1_6:
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB1_7: # %._crit_edge18
retq
.Lfunc_end1:
.size _Z13transposeHostPfPKfii, .Lfunc_end1-_Z13transposeHostPfPKfii
.cfi_endproc
# -- End function
.globl _Z21__device_stub__warmupPfS_ii # -- Begin function _Z21__device_stub__warmupPfS_ii
.p2align 4, 0x90
.type _Z21__device_stub__warmupPfS_ii,@function
_Z21__device_stub__warmupPfS_ii: # @_Z21__device_stub__warmupPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6warmupPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z21__device_stub__warmupPfS_ii, .Lfunc_end2-_Z21__device_stub__warmupPfS_ii
.cfi_endproc
# -- End function
.globl _Z28__device_stub__copyGlobalRowPfS_ii # -- Begin function _Z28__device_stub__copyGlobalRowPfS_ii
.p2align 4, 0x90
.type _Z28__device_stub__copyGlobalRowPfS_ii,@function
_Z28__device_stub__copyGlobalRowPfS_ii: # @_Z28__device_stub__copyGlobalRowPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13copyGlobalRowPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z28__device_stub__copyGlobalRowPfS_ii, .Lfunc_end3-_Z28__device_stub__copyGlobalRowPfS_ii
.cfi_endproc
# -- End function
.globl _Z28__device_stub__copyGlobalColPfS_ii # -- Begin function _Z28__device_stub__copyGlobalColPfS_ii
.p2align 4, 0x90
.type _Z28__device_stub__copyGlobalColPfS_ii,@function
_Z28__device_stub__copyGlobalColPfS_ii: # @_Z28__device_stub__copyGlobalColPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13copyGlobalColPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z28__device_stub__copyGlobalColPfS_ii, .Lfunc_end4-_Z28__device_stub__copyGlobalColPfS_ii
.cfi_endproc
# -- End function
.globl _Z33__device_stub__transposeGlobalRowPfS_ii # -- Begin function _Z33__device_stub__transposeGlobalRowPfS_ii
.p2align 4, 0x90
.type _Z33__device_stub__transposeGlobalRowPfS_ii,@function
_Z33__device_stub__transposeGlobalRowPfS_ii: # @_Z33__device_stub__transposeGlobalRowPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18transposeGlobalRowPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end5:
.size _Z33__device_stub__transposeGlobalRowPfS_ii, .Lfunc_end5-_Z33__device_stub__transposeGlobalRowPfS_ii
.cfi_endproc
# -- End function
.globl _Z33__device_stub__transposeGlobalColPfS_ii # -- Begin function _Z33__device_stub__transposeGlobalColPfS_ii
.p2align 4, 0x90
.type _Z33__device_stub__transposeGlobalColPfS_ii,@function
_Z33__device_stub__transposeGlobalColPfS_ii: # @_Z33__device_stub__transposeGlobalColPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18transposeGlobalColPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end6:
.size _Z33__device_stub__transposeGlobalColPfS_ii, .Lfunc_end6-_Z33__device_stub__transposeGlobalColPfS_ii
.cfi_endproc
# -- End function
.globl _Z6verifyPKfS0_ii # -- Begin function _Z6verifyPKfS0_ii
.p2align 4, 0x90
.type _Z6verifyPKfS0_ii,@function
_Z6verifyPKfS0_ii: # @_Z6verifyPKfS0_ii
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB7_9
# %bb.1: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movq %rdi, %r15
movslq %edx, %r12
movl %ecx, %r13d
movl %r12d, %ebp
shlq $2, %r12
xorl %ebx, %ebx
movl %edx, 4(%rsp) # 4-byte Spill
jmp .LBB7_2
.p2align 4, 0x90
.LBB7_6: # in Loop: Header=BB7_2 Depth=1
movl $.Lstr, %edi
callq puts@PLT
movl 4(%rsp), %edx # 4-byte Reload
.LBB7_7: # %.loopexit
# in Loop: Header=BB7_2 Depth=1
incq %rbx
addq %r12, %r15
addq %r12, %r14
cmpq %r13, %rbx
je .LBB7_8
.LBB7_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB7_5 Depth 2
testl %edx, %edx
jle .LBB7_7
# %bb.3: # %.lr.ph
# in Loop: Header=BB7_2 Depth=1
xorl %eax, %eax
.p2align 4, 0x90
.LBB7_5: # Parent Loop BB7_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss (%r14,%rax,4), %xmm0
jne .LBB7_6
jp .LBB7_6
# %bb.4: # in Loop: Header=BB7_5 Depth=2
incq %rax
cmpq %rax, %rbp
jne .LBB7_5
jmp .LBB7_7
.LBB7_8:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB7_9: # %._crit_edge
retq
.Lfunc_end7:
.size _Z6verifyPKfS0_ii, .Lfunc_end7-_Z6verifyPKfS0_ii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI8_0:
.long 0x41200000 # float 10
.LCPI8_1:
.long 0x4c000000 # float 33554432
.LCPI8_2:
.long 0x49742400 # float 1.0E+6
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI8_3:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $0, 12(%rsp)
leaq 96(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r12
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, 144(%rsp) # 8-byte Spill
xorl %r14d, %r14d
movl $.L.str.1, %edi
movl $2048, %esi # imm = 0x800
movl $2048, %edx # imm = 0x800
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB8_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss .LCPI8_0(%rip), %xmm0
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq $4194304, %r14 # imm = 0x400000
jne .LBB8_1
# %bb.2: # %.preheader.i.preheader
xorl %eax, %eax
movq %r12, %rcx
movq %rbx, %rdx
.p2align 4, 0x90
.LBB8_3: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB8_4 Depth 2
movq %rcx, %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB8_4: # Parent Loop BB8_3 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdx,%rdi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rsi)
incq %rdi
addq $8192, %rsi # imm = 0x2000
cmpq $2048, %rdi # imm = 0x800
jne .LBB8_4
# %bb.5: # %._crit_edge.i
# in Loop: Header=BB8_3 Depth=1
incq %rax
addq $8192, %rdx # imm = 0x2000
addq $4, %rcx
cmpq $2048, %rax # imm = 0x800
jne .LBB8_3
# %bb.6: # %_Z13transposeHostPfPKfii.exit
movabsq $549755814016, %r15 # imm = 0x8000000080
movabsq $68719476752, %r14 # imm = 0x1000000010
leaq 104(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
leaq 88(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movq 104(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_8
# %bb.7:
movq 104(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl $2048, 8(%rsp) # imm = 0x800
movl $2048, 4(%rsp) # imm = 0x800
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6warmupPfS_ii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_8: # %.critedge
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_10
# %bb.9:
movq 104(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl $2048, 8(%rsp) # imm = 0x800
movl $2048, 4(%rsp) # imm = 0x800
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13copyGlobalRowPfS_ii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_10: # %.critedge122
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 96(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI8_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
divss .LCPI8_2(%rip), %xmm1
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.2, %edi
movb $2, %al
callq printf
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_12
# %bb.11:
movq 104(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl $2048, 8(%rsp) # imm = 0x800
movl $2048, 4(%rsp) # imm = 0x800
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13copyGlobalColPfS_ii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_12: # %.critedge124
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 96(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI8_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
divss .LCPI8_2(%rip), %xmm1
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.3, %edi
movb $2, %al
callq printf
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_14
# %bb.13:
movq 104(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl $2048, 8(%rsp) # imm = 0x800
movl $2048, 4(%rsp) # imm = 0x800
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z18transposeGlobalRowPfS_ii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_14: # %.critedge126
movq 16(%rsp), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 96(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI8_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
cvtss2sd %xmm1, %xmm1
mulsd .LCPI8_3(%rip), %xmm1
cvtsd2ss %xmm1, %xmm1
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.4, %edi
movb $2, %al
callq printf
movq 88(%rsp), %rsi
movl $16777216, %edx # imm = 0x1000000
movq 144(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq %r12, %r13
jmp .LBB8_15
.p2align 4, 0x90
.LBB8_18: # in Loop: Header=BB8_15 Depth=1
movl $.Lstr, %edi
callq puts@PLT
.LBB8_19: # %.loopexit.i
# in Loop: Header=BB8_15 Depth=1
incq %rbp
addq $8192, %r15 # imm = 0x2000
addq $8192, %r12 # imm = 0x2000
cmpq $2048, %rbp # imm = 0x800
je .LBB8_20
.LBB8_15: # %.preheader.i149
# =>This Loop Header: Depth=1
# Child Loop BB8_17 Depth 2
xorl %eax, %eax
.p2align 4, 0x90
.LBB8_17: # Parent Loop BB8_15 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss (%r15,%rax,4), %xmm0
jne .LBB8_18
jp .LBB8_18
# %bb.16: # in Loop: Header=BB8_17 Depth=2
incq %rax
cmpq $2048, %rax # imm = 0x800
jne .LBB8_17
jmp .LBB8_19
.LBB8_20: # %_Z6verifyPKfS0_ii.exit
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $549755814016, %rdi # imm = 0x8000000080
movl $1, %esi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_22
# %bb.21:
movq 104(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl $2048, 8(%rsp) # imm = 0x800
movl $2048, 4(%rsp) # imm = 0x800
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z18transposeGlobalColPfS_ii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_22:
movq 16(%rsp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 96(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI8_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
cvtss2sd %xmm1, %xmm1
mulsd .LCPI8_3(%rip), %xmm1
cvtsd2ss %xmm1, %xmm1
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.5, %edi
movb $2, %al
callq printf
movq 88(%rsp), %rsi
movl $16777216, %edx # imm = 0x1000000
movq 144(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq %r13, %r14
jmp .LBB8_23
.p2align 4, 0x90
.LBB8_26: # in Loop: Header=BB8_23 Depth=1
movl $.Lstr, %edi
callq puts@PLT
.LBB8_27: # %.loopexit.i167
# in Loop: Header=BB8_23 Depth=1
incq %r12
addq $8192, %r15 # imm = 0x2000
addq $8192, %r14 # imm = 0x2000
cmpq $2048, %r12 # imm = 0x800
je .LBB8_28
.LBB8_23: # %.preheader.i161
# =>This Loop Header: Depth=1
# Child Loop BB8_25 Depth 2
xorl %eax, %eax
.p2align 4, 0x90
.LBB8_25: # Parent Loop BB8_23 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss (%r15,%rax,4), %xmm0
jne .LBB8_26
jp .LBB8_26
# %bb.24: # in Loop: Header=BB8_25 Depth=2
incq %rax
cmpq $2048, %rax # imm = 0x800
jne .LBB8_25
jmp .LBB8_27
.LBB8_28: # %_Z6verifyPKfS0_ii.exit172
movq 104(%rsp), %rdi
callq hipFree
movq 88(%rsp), %rdi
callq hipFree
movq %r13, %rdi
callq free
movq 144(%rsp), %rdi # 8-byte Reload
callq free
movq %rbx, %rdi
callq free
callq hipDeviceReset
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size main, .Lfunc_end8-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6warmupPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13copyGlobalRowPfS_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13copyGlobalColPfS_ii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18transposeGlobalRowPfS_ii, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18transposeGlobalColPfS_ii, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6warmupPfS_ii,@object # @_Z6warmupPfS_ii
.section .rodata,"a",@progbits
.globl _Z6warmupPfS_ii
.p2align 3, 0x0
_Z6warmupPfS_ii:
.quad _Z21__device_stub__warmupPfS_ii
.size _Z6warmupPfS_ii, 8
.type _Z13copyGlobalRowPfS_ii,@object # @_Z13copyGlobalRowPfS_ii
.globl _Z13copyGlobalRowPfS_ii
.p2align 3, 0x0
_Z13copyGlobalRowPfS_ii:
.quad _Z28__device_stub__copyGlobalRowPfS_ii
.size _Z13copyGlobalRowPfS_ii, 8
.type _Z13copyGlobalColPfS_ii,@object # @_Z13copyGlobalColPfS_ii
.globl _Z13copyGlobalColPfS_ii
.p2align 3, 0x0
_Z13copyGlobalColPfS_ii:
.quad _Z28__device_stub__copyGlobalColPfS_ii
.size _Z13copyGlobalColPfS_ii, 8
.type _Z18transposeGlobalRowPfS_ii,@object # @_Z18transposeGlobalRowPfS_ii
.globl _Z18transposeGlobalRowPfS_ii
.p2align 3, 0x0
_Z18transposeGlobalRowPfS_ii:
.quad _Z33__device_stub__transposeGlobalRowPfS_ii
.size _Z18transposeGlobalRowPfS_ii, 8
.type _Z18transposeGlobalColPfS_ii,@object # @_Z18transposeGlobalColPfS_ii
.globl _Z18transposeGlobalColPfS_ii
.p2align 3, 0x0
_Z18transposeGlobalColPfS_ii:
.quad _Z33__device_stub__transposeGlobalColPfS_ii
.size _Z18transposeGlobalColPfS_ii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Matrix %d nx %d ny\n"
.size .L.str.1, 20
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "copyGlobalRow: %f ms, effective bandwidth %f GB/s\n"
.size .L.str.2, 51
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "copyGlobalCol: %f ms, effective bandwidth %f GB/s\n"
.size .L.str.3, 51
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "transposeGlobalRow: %f ms, effective bandwidth %f GB/s\n"
.size .L.str.4, 56
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "transposeGlobalCol: %f ms, effective bandwidth %f GB/s\n"
.size .L.str.5, 56
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6warmupPfS_ii"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13copyGlobalRowPfS_ii"
.size .L__unnamed_2, 24
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13copyGlobalColPfS_ii"
.size .L__unnamed_3, 24
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z18transposeGlobalRowPfS_ii"
.size .L__unnamed_4, 29
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z18transposeGlobalColPfS_ii"
.size .L__unnamed_5, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error"
.size .Lstr, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__warmupPfS_ii
.addrsig_sym _Z28__device_stub__copyGlobalRowPfS_ii
.addrsig_sym _Z28__device_stub__copyGlobalColPfS_ii
.addrsig_sym _Z33__device_stub__transposeGlobalRowPfS_ii
.addrsig_sym _Z33__device_stub__transposeGlobalColPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6warmupPfS_ii
.addrsig_sym _Z13copyGlobalRowPfS_ii
.addrsig_sym _Z13copyGlobalColPfS_ii
.addrsig_sym _Z18transposeGlobalRowPfS_ii
.addrsig_sym _Z18transposeGlobalColPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18transposeGlobalColPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R0, c[0x0][0x174], R5 ; /* 0x00005d0000027a24 */
/* 0x000fe200078e0205 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE.U32 R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0004 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD R5, R5, c[0x0][0x170], R0 ; /* 0x00005c0005057a24 */
/* 0x000fc800078e0200 */
/*0100*/ IMAD.WIDE.U32 R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0004 */
/*0110*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z18transposeGlobalRowPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R5, c[0x0][0x170], R0 ; /* 0x00005c0005027a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE.U32 R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0004 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD R5, R0, c[0x0][0x174], R5 ; /* 0x00005d0000057a24 */
/* 0x000fc800078e0205 */
/*0100*/ IMAD.WIDE.U32 R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0004 */
/*0110*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13copyGlobalColPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R0, c[0x0][0x174], R3 ; /* 0x00005d0000007a24 */
/* 0x000fe200078e0203 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0005 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0005 */
/*0100*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13copyGlobalRowPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x170], R0 ; /* 0x00005c0003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0005 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0005 */
/*0100*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z6warmupPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x170], R0 ; /* 0x00005c0003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0005 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0005 */
/*0100*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6warmupPfS_ii
.globl _Z6warmupPfS_ii
.p2align 8
.type _Z6warmupPfS_ii,@function
_Z6warmupPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6warmupPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6warmupPfS_ii, .Lfunc_end0-_Z6warmupPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13copyGlobalRowPfS_ii
.globl _Z13copyGlobalRowPfS_ii
.p2align 8
.type _Z13copyGlobalRowPfS_ii,@function
_Z13copyGlobalRowPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13copyGlobalRowPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13copyGlobalRowPfS_ii, .Lfunc_end1-_Z13copyGlobalRowPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13copyGlobalColPfS_ii
.globl _Z13copyGlobalColPfS_ii
.p2align 8
.type _Z13copyGlobalColPfS_ii,@function
_Z13copyGlobalColPfS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB2_2
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
v_mov_b32_e32 v3, 0
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13copyGlobalColPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z13copyGlobalColPfS_ii, .Lfunc_end2-_Z13copyGlobalColPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z18transposeGlobalRowPfS_ii
.globl _Z18transposeGlobalRowPfS_ii
.p2align 8
.type _Z18transposeGlobalRowPfS_ii,@function
_Z18transposeGlobalRowPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB3_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[4:5], null, v0, s5, v[1:2]
v_mov_b32_e32 v5, v3
v_lshlrev_b64 v[0:1], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB3_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18transposeGlobalRowPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z18transposeGlobalRowPfS_ii, .Lfunc_end3-_Z18transposeGlobalRowPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z18transposeGlobalColPfS_ii
.globl _Z18transposeGlobalColPfS_ii
.p2align 8
.type _Z18transposeGlobalColPfS_ii,@function
_Z18transposeGlobalColPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB4_2
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s5, v[1:2]
v_mov_b32_e32 v3, 0
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b32 v2, v[4:5], off
v_mad_u64_u32 v[4:5], null, v1, s4, v[0:1]
v_mov_b32_e32 v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[4:5]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB4_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18transposeGlobalColPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z18transposeGlobalColPfS_ii, .Lfunc_end4-_Z18transposeGlobalColPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6warmupPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6warmupPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13copyGlobalRowPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13copyGlobalRowPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13copyGlobalColPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13copyGlobalColPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18transposeGlobalRowPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18transposeGlobalRowPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18transposeGlobalColPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18transposeGlobalColPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
using namespace std;
int main(void)
{
cout << "Hello nvcc!" << endl;
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
using namespace std;
int main(void)
{
cout << "Hello nvcc!" << endl;
return 0;
} | .file "tmpxft_00193ada_00000000-6_helloworld.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello nvcc!"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
using namespace std;
int main(void)
{
cout << "Hello nvcc!" << endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
int main(void)
{
cout << "Hello nvcc!" << endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
int main(void)
{
cout << "Hello nvcc!" << endl;
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
int main(void)
{
cout << "Hello nvcc!" << endl;
return 0;
} | .text
.file "helloworld.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_5
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB0_4
.LBB0_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_5:
.cfi_def_cfa_offset 16
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Hello nvcc!"
.size .L.str, 12
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00193ada_00000000-6_helloworld.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello nvcc!"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "helloworld.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_5
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB0_4
.LBB0_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_5:
.cfi_def_cfa_offset 16
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Hello nvcc!"
.size .L.str, 12
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
int main(void) {
int deviceCount = 0;
cudaGetDeviceCount(&deviceCount);
printf("CUDA devices count is %d.\n", deviceCount);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
int main(void) {
int deviceCount = 0;
cudaGetDeviceCount(&deviceCount);
printf("CUDA devices count is %d.\n", deviceCount);
return 0;
} | .file "tmpxft_00115ab1_00000000-6_hw1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA devices count is %d.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 4(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
int main(void) {
int deviceCount = 0;
cudaGetDeviceCount(&deviceCount);
printf("CUDA devices count is %d.\n", deviceCount);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
int main(void) {
int deviceCount = 0;
hipGetDeviceCount(&deviceCount);
printf("CUDA devices count is %d.\n", deviceCount);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
int main(void) {
int deviceCount = 0;
hipGetDeviceCount(&deviceCount);
printf("CUDA devices count is %d.\n", deviceCount);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
int main(void) {
int deviceCount = 0;
hipGetDeviceCount(&deviceCount);
printf("CUDA devices count is %d.\n", deviceCount);
return 0;
} | .text
.file "hw1.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl 4(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA devices count is %d.\n"
.size .L.str, 27
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00115ab1_00000000-6_hw1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA devices count is %d.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 4(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hw1.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl 4(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA devices count is %d.\n"
.size .L.str, 27
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float* var_11,float* var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float var_23,float var_24) {
for (int i=0; i < var_1; ++i) {
comp = var_3 * floorf(+1.5144E35f);
float tmp_1 = -0.0f + (var_4 + fmodf((var_5 * (+1.1032E-36f - (var_6 * -0.0f + +0.0f))), -1.8364E35f));
comp += tmp_1 * (-1.7594E-25f + (var_7 - var_8 - var_9));
comp += tanhf(floorf(+1.6852E-43f + var_10 * -1.1582E-36f));
for (int i=0; i < var_2; ++i) {
var_11[i] = -1.6470E-22f;
var_12[i] = +1.0940E36f;
comp += var_12[i] / var_11[i] + (var_13 / (var_14 + var_15));
}
if (comp >= -1.4099E35f + (-1.8257E34f + -1.0592E27f)) {
comp = var_16 - var_17 / var_18 - -1.7750E-37f / -1.9396E-19f + var_19;
comp += var_20 - -0.0f;
comp += (+1.9299E-37f + (+1.9056E12f / var_21));
comp += var_22 - -1.5014E-36f * log10f(+1.0657E-43f);
}
if (comp > -1.2880E1f / +1.7427E-44f - +1.5180E7f) {
comp = var_23 - (var_24 / -1.6423E11f);
comp = (+1.4207E-36f - +1.3393E34f + -1.1701E-43f);
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float* tmp_12 = initPointer( atof(argv[12]) );
float* tmp_13 = initPointer( atof(argv[13]) );
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float tmp_24 = atof(argv[24]);
float tmp_25 = atof(argv[25]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25);
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_0005ef86_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z51__device_stub__Z7computefiiffffffffPfS_fffffffffffffiiffffffffPfS_ffffffffffff
.type _Z51__device_stub__Z7computefiiffffffffPfS_fffffffffffffiiffffffffPfS_ffffffffffff, @function
_Z51__device_stub__Z7computefiiffffffffPfS_fffffffffffffiiffffffffPfS_ffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $344, %rsp
.cfi_def_cfa_offset 352
movss %xmm0, 60(%rsp)
movl %edi, 56(%rsp)
movl %esi, 52(%rsp)
movss %xmm1, 48(%rsp)
movss %xmm2, 44(%rsp)
movss %xmm3, 40(%rsp)
movss %xmm4, 36(%rsp)
movss %xmm5, 32(%rsp)
movss %xmm6, 28(%rsp)
movss %xmm7, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 328(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 36(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 28(%rsp), %rax
movq %rax, 192(%rsp)
leaq 24(%rsp), %rax
movq %rax, 200(%rsp)
leaq 352(%rsp), %rax
movq %rax, 208(%rsp)
leaq 16(%rsp), %rax
movq %rax, 216(%rsp)
leaq 8(%rsp), %rax
movq %rax, 224(%rsp)
leaq 360(%rsp), %rax
movq %rax, 232(%rsp)
leaq 368(%rsp), %rax
movq %rax, 240(%rsp)
leaq 376(%rsp), %rax
movq %rax, 248(%rsp)
leaq 384(%rsp), %rax
movq %rax, 256(%rsp)
leaq 392(%rsp), %rax
movq %rax, 264(%rsp)
leaq 400(%rsp), %rax
movq %rax, 272(%rsp)
leaq 408(%rsp), %rax
movq %rax, 280(%rsp)
leaq 416(%rsp), %rax
movq %rax, 288(%rsp)
leaq 424(%rsp), %rax
movq %rax, 296(%rsp)
leaq 432(%rsp), %rax
movq %rax, 304(%rsp)
leaq 440(%rsp), %rax
movq %rax, 312(%rsp)
leaq 448(%rsp), %rax
movq %rax, 320(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 328(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $344, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 360
pushq 72(%rsp)
.cfi_def_cfa_offset 368
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z7computefiiffffffffPfS_ffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 352
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z51__device_stub__Z7computefiiffffffffPfS_fffffffffffffiiffffffffPfS_ffffffffffff, .-_Z51__device_stub__Z7computefiiffffffffPfS_fffffffffffffiiffffffffPfS_ffffffffffff
.globl _Z7computefiiffffffffPfS_ffffffffffff
.type _Z7computefiiffffffffPfS_ffffffffffff, @function
_Z7computefiiffffffffPfS_ffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movss 224(%rsp), %xmm8
movss %xmm8, 96(%rsp)
movss 216(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 208(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 200(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 192(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 184(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 176(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 168(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 160(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 152(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 144(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 136(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 128(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z51__device_stub__Z7computefiiffffffffPfS_fffffffffffffiiffffffffPfS_ffffffffffff
addq $120, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefiiffffffffPfS_ffffffffffff, .-_Z7computefiiffffffffPfS_ffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $208, %rsp
.cfi_def_cfa_offset 256
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 168(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 160(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r13
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r14
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 176(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 184(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 192(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 200(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movl $1, 196(%rsp)
movl $1, 200(%rsp)
movl $1, 184(%rsp)
movl $1, 188(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 196(%rsp), %rdx
movl $1, %ecx
movq 184(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $208, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 168(%rsp), %xmm0
subq $112, %rsp
.cfi_def_cfa_offset 368
pxor %xmm1, %xmm1
cvtsd2ss 120(%rsp), %xmm1
movss %xmm1, 96(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 128(%rsp), %xmm1
movss %xmm1, 88(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 136(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 144(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 152(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 160(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 168(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 176(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 184(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 192(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 200(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 208(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 216(%rsp), %xmm1
movss %xmm1, (%rsp)
movq %r14, %rcx
movq %r13, %rdx
pxor %xmm7, %xmm7
cvtsd2ss 224(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 232(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 240(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 248(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 256(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 264(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 272(%rsp), %xmm1
movl %r12d, %esi
movl %ebp, %edi
call _Z51__device_stub__Z7computefiiffffffffPfS_fffffffffffffiiffffffffPfS_ffffffffffff
addq $112, %rsp
.cfi_def_cfa_offset 256
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computefiiffffffffPfS_ffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefiiffffffffPfS_ffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float* var_11,float* var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float var_23,float var_24) {
for (int i=0; i < var_1; ++i) {
comp = var_3 * floorf(+1.5144E35f);
float tmp_1 = -0.0f + (var_4 + fmodf((var_5 * (+1.1032E-36f - (var_6 * -0.0f + +0.0f))), -1.8364E35f));
comp += tmp_1 * (-1.7594E-25f + (var_7 - var_8 - var_9));
comp += tanhf(floorf(+1.6852E-43f + var_10 * -1.1582E-36f));
for (int i=0; i < var_2; ++i) {
var_11[i] = -1.6470E-22f;
var_12[i] = +1.0940E36f;
comp += var_12[i] / var_11[i] + (var_13 / (var_14 + var_15));
}
if (comp >= -1.4099E35f + (-1.8257E34f + -1.0592E27f)) {
comp = var_16 - var_17 / var_18 - -1.7750E-37f / -1.9396E-19f + var_19;
comp += var_20 - -0.0f;
comp += (+1.9299E-37f + (+1.9056E12f / var_21));
comp += var_22 - -1.5014E-36f * log10f(+1.0657E-43f);
}
if (comp > -1.2880E1f / +1.7427E-44f - +1.5180E7f) {
comp = var_23 - (var_24 / -1.6423E11f);
comp = (+1.4207E-36f - +1.3393E34f + -1.1701E-43f);
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float* tmp_12 = initPointer( atof(argv[12]) );
float* tmp_13 = initPointer( atof(argv[13]) );
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float tmp_24 = atof(argv[24]);
float tmp_25 = atof(argv[25]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25);
cudaDeviceSynchronize();
return 0;
} | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float* var_11,float* var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float var_23,float var_24) {
for (int i=0; i < var_1; ++i) {
comp = var_3 * floorf(+1.5144E35f);
float tmp_1 = -0.0f + (var_4 + fmodf((var_5 * (+1.1032E-36f - (var_6 * -0.0f + +0.0f))), -1.8364E35f));
comp += tmp_1 * (-1.7594E-25f + (var_7 - var_8 - var_9));
comp += tanhf(floorf(+1.6852E-43f + var_10 * -1.1582E-36f));
for (int i=0; i < var_2; ++i) {
var_11[i] = -1.6470E-22f;
var_12[i] = +1.0940E36f;
comp += var_12[i] / var_11[i] + (var_13 / (var_14 + var_15));
}
if (comp >= -1.4099E35f + (-1.8257E34f + -1.0592E27f)) {
comp = var_16 - var_17 / var_18 - -1.7750E-37f / -1.9396E-19f + var_19;
comp += var_20 - -0.0f;
comp += (+1.9299E-37f + (+1.9056E12f / var_21));
comp += var_22 - -1.5014E-36f * log10f(+1.0657E-43f);
}
if (comp > -1.2880E1f / +1.7427E-44f - +1.5180E7f) {
comp = var_23 - (var_24 / -1.6423E11f);
comp = (+1.4207E-36f - +1.3393E34f + -1.1701E-43f);
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float* tmp_12 = initPointer( atof(argv[12]) );
float* tmp_13 = initPointer( atof(argv[13]) );
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float tmp_24 = atof(argv[24]);
float tmp_25 = atof(argv[25]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25);
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float* var_11,float* var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float var_23,float var_24) {
for (int i=0; i < var_1; ++i) {
comp = var_3 * floorf(+1.5144E35f);
float tmp_1 = -0.0f + (var_4 + fmodf((var_5 * (+1.1032E-36f - (var_6 * -0.0f + +0.0f))), -1.8364E35f));
comp += tmp_1 * (-1.7594E-25f + (var_7 - var_8 - var_9));
comp += tanhf(floorf(+1.6852E-43f + var_10 * -1.1582E-36f));
for (int i=0; i < var_2; ++i) {
var_11[i] = -1.6470E-22f;
var_12[i] = +1.0940E36f;
comp += var_12[i] / var_11[i] + (var_13 / (var_14 + var_15));
}
if (comp >= -1.4099E35f + (-1.8257E34f + -1.0592E27f)) {
comp = var_16 - var_17 / var_18 - -1.7750E-37f / -1.9396E-19f + var_19;
comp += var_20 - -0.0f;
comp += (+1.9299E-37f + (+1.9056E12f / var_21));
comp += var_22 - -1.5014E-36f * log10f(+1.0657E-43f);
}
if (comp > -1.2880E1f / +1.7427E-44f - +1.5180E7f) {
comp = var_23 - (var_24 / -1.6423E11f);
comp = (+1.4207E-36f - +1.3393E34f + -1.1701E-43f);
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float* tmp_12 = initPointer( atof(argv[12]) );
float* tmp_13 = initPointer( atof(argv[13]) );
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float tmp_24 = atof(argv[24]);
float tmp_25 = atof(argv[25]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25);
hipDeviceSynchronize();
return 0;
} | .text
.file "test.hip"
.globl _Z22__device_stub__computefiiffffffffPfS_ffffffffffff # -- Begin function _Z22__device_stub__computefiiffffffffPfS_ffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefiiffffffffPfS_ffffffffffff,@function
_Z22__device_stub__computefiiffffffffPfS_ffffffffffff: # @_Z22__device_stub__computefiiffffffffPfS_ffffffffffff
.cfi_startproc
# %bb.0:
subq $312, %rsp # imm = 0x138
.cfi_def_cfa_offset 320
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movl %esi, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movss %xmm3, 24(%rsp)
movss %xmm4, 20(%rsp)
movss %xmm5, 16(%rsp)
movss %xmm6, 12(%rsp)
movss %xmm7, 8(%rsp)
movq %rdx, 104(%rsp)
movq %rcx, 96(%rsp)
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 320(%rsp), %rax
movq %rax, 192(%rsp)
leaq 104(%rsp), %rax
movq %rax, 200(%rsp)
leaq 96(%rsp), %rax
movq %rax, 208(%rsp)
leaq 328(%rsp), %rax
movq %rax, 216(%rsp)
leaq 336(%rsp), %rax
movq %rax, 224(%rsp)
leaq 344(%rsp), %rax
movq %rax, 232(%rsp)
leaq 352(%rsp), %rax
movq %rax, 240(%rsp)
leaq 360(%rsp), %rax
movq %rax, 248(%rsp)
leaq 368(%rsp), %rax
movq %rax, 256(%rsp)
leaq 376(%rsp), %rax
movq %rax, 264(%rsp)
leaq 384(%rsp), %rax
movq %rax, 272(%rsp)
leaq 392(%rsp), %rax
movq %rax, 280(%rsp)
leaq 400(%rsp), %rax
movq %rax, 288(%rsp)
leaq 408(%rsp), %rax
movq %rax, 296(%rsp)
leaq 416(%rsp), %rax
movq %rax, 304(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7computefiiffffffffPfS_ffffffffffff, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $328, %rsp # imm = 0x148
.cfi_adjust_cfa_offset -328
retq
.Lfunc_end0:
.size _Z22__device_stub__computefiiffffffffPfS_ffffffffffff, .Lfunc_end0-_Z22__device_stub__computefiiffffffffPfS_ffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movq 8(%rsi), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
callq strtod
movsd %xmm0, 272(%rsp) # 8-byte Spill
movq 16(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 32(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 264(%rsp) # 8-byte Spill
movq 40(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 256(%rsp) # 8-byte Spill
movq 48(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq 56(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 136(%rsp) # 8-byte Spill
movq 64(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 128(%rsp) # 8-byte Spill
movq 72(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq 80(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 248(%rsp) # 8-byte Spill
movq 88(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 240(%rsp) # 8-byte Spill
movq 96(%r15), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 112(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 112(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r12
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r12,%r13,4)
incq %r13
cmpq $10, %r13
jne .LBB2_1
# %bb.2: # %_Z11initPointerf.exit
movq 104(%r15), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 112(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 112(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r13
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r13,%rbp,4)
incq %rbp
cmpq $10, %rbp
jne .LBB2_3
# %bb.4: # %_Z11initPointerf.exit54
movq 112(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 112(%rsp) # 8-byte Spill
movq 120(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movq 128(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 136(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 144(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 152(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 160(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 168(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 176(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movq 184(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 192(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 200(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 152(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movsd 152(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 160(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 168(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 240(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 248(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 112(%rsp) # 4-byte Spill
movsd 120(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 120(%rsp) # 4-byte Spill
movsd 128(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 128(%rsp) # 4-byte Spill
movsd 136(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 136(%rsp) # 4-byte Spill
movsd 144(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 144(%rsp) # 4-byte Spill
movsd 256(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 264(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 272(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 96(%rsp)
movss %xmm9, 88(%rsp)
movss %xmm10, 80(%rsp)
movss %xmm11, 72(%rsp)
movss %xmm12, 64(%rsp)
movss %xmm13, 56(%rsp)
movss %xmm14, 48(%rsp)
movss %xmm15, 40(%rsp)
movss %xmm3, 32(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 16(%rsp)
movss %xmm6, 8(%rsp)
movss %xmm7, (%rsp)
movl %ebx, %edi
movl %r14d, %esi
movss 144(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss 136(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 128(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 120(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 112(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
movq %r12, %rdx
movq %r13, %rcx
callq _Z22__device_stub__computefiiffffffffPfS_ffffffffffff
.LBB2_6:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefiiffffffffPfS_ffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefiiffffffffPfS_ffffffffffff,@object # @_Z7computefiiffffffffPfS_ffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefiiffffffffPfS_ffffffffffff
.p2align 3, 0x0
_Z7computefiiffffffffPfS_ffffffffffff:
.quad _Z22__device_stub__computefiiffffffffPfS_ffffffffffff
.size _Z7computefiiffffffffPfS_ffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefiiffffffffPfS_ffffffffffff"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefiiffffffffPfS_ffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefiiffffffffPfS_ffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005ef86_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z51__device_stub__Z7computefiiffffffffPfS_fffffffffffffiiffffffffPfS_ffffffffffff
.type _Z51__device_stub__Z7computefiiffffffffPfS_fffffffffffffiiffffffffPfS_ffffffffffff, @function
_Z51__device_stub__Z7computefiiffffffffPfS_fffffffffffffiiffffffffPfS_ffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $344, %rsp
.cfi_def_cfa_offset 352
movss %xmm0, 60(%rsp)
movl %edi, 56(%rsp)
movl %esi, 52(%rsp)
movss %xmm1, 48(%rsp)
movss %xmm2, 44(%rsp)
movss %xmm3, 40(%rsp)
movss %xmm4, 36(%rsp)
movss %xmm5, 32(%rsp)
movss %xmm6, 28(%rsp)
movss %xmm7, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 328(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 36(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 28(%rsp), %rax
movq %rax, 192(%rsp)
leaq 24(%rsp), %rax
movq %rax, 200(%rsp)
leaq 352(%rsp), %rax
movq %rax, 208(%rsp)
leaq 16(%rsp), %rax
movq %rax, 216(%rsp)
leaq 8(%rsp), %rax
movq %rax, 224(%rsp)
leaq 360(%rsp), %rax
movq %rax, 232(%rsp)
leaq 368(%rsp), %rax
movq %rax, 240(%rsp)
leaq 376(%rsp), %rax
movq %rax, 248(%rsp)
leaq 384(%rsp), %rax
movq %rax, 256(%rsp)
leaq 392(%rsp), %rax
movq %rax, 264(%rsp)
leaq 400(%rsp), %rax
movq %rax, 272(%rsp)
leaq 408(%rsp), %rax
movq %rax, 280(%rsp)
leaq 416(%rsp), %rax
movq %rax, 288(%rsp)
leaq 424(%rsp), %rax
movq %rax, 296(%rsp)
leaq 432(%rsp), %rax
movq %rax, 304(%rsp)
leaq 440(%rsp), %rax
movq %rax, 312(%rsp)
leaq 448(%rsp), %rax
movq %rax, 320(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 328(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $344, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 360
pushq 72(%rsp)
.cfi_def_cfa_offset 368
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z7computefiiffffffffPfS_ffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 352
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z51__device_stub__Z7computefiiffffffffPfS_fffffffffffffiiffffffffPfS_ffffffffffff, .-_Z51__device_stub__Z7computefiiffffffffPfS_fffffffffffffiiffffffffPfS_ffffffffffff
.globl _Z7computefiiffffffffPfS_ffffffffffff
.type _Z7computefiiffffffffPfS_ffffffffffff, @function
_Z7computefiiffffffffPfS_ffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movss 224(%rsp), %xmm8
movss %xmm8, 96(%rsp)
movss 216(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 208(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 200(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 192(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 184(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 176(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 168(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 160(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 152(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 144(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 136(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 128(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z51__device_stub__Z7computefiiffffffffPfS_fffffffffffffiiffffffffPfS_ffffffffffff
addq $120, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefiiffffffffPfS_ffffffffffff, .-_Z7computefiiffffffffPfS_ffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $208, %rsp
.cfi_def_cfa_offset 256
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 168(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 160(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r13
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r14
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 176(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 184(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 192(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 200(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movl $1, 196(%rsp)
movl $1, 200(%rsp)
movl $1, 184(%rsp)
movl $1, 188(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 196(%rsp), %rdx
movl $1, %ecx
movq 184(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $208, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 168(%rsp), %xmm0
subq $112, %rsp
.cfi_def_cfa_offset 368
pxor %xmm1, %xmm1
cvtsd2ss 120(%rsp), %xmm1
movss %xmm1, 96(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 128(%rsp), %xmm1
movss %xmm1, 88(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 136(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 144(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 152(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 160(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 168(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 176(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 184(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 192(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 200(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 208(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 216(%rsp), %xmm1
movss %xmm1, (%rsp)
movq %r14, %rcx
movq %r13, %rdx
pxor %xmm7, %xmm7
cvtsd2ss 224(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 232(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 240(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 248(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 256(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 264(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 272(%rsp), %xmm1
movl %r12d, %esi
movl %ebp, %edi
call _Z51__device_stub__Z7computefiiffffffffPfS_fffffffffffffiiffffffffPfS_ffffffffffff
addq $112, %rsp
.cfi_def_cfa_offset 256
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computefiiffffffffPfS_ffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefiiffffffffPfS_ffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z22__device_stub__computefiiffffffffPfS_ffffffffffff # -- Begin function _Z22__device_stub__computefiiffffffffPfS_ffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefiiffffffffPfS_ffffffffffff,@function
_Z22__device_stub__computefiiffffffffPfS_ffffffffffff: # @_Z22__device_stub__computefiiffffffffPfS_ffffffffffff
.cfi_startproc
# %bb.0:
subq $312, %rsp # imm = 0x138
.cfi_def_cfa_offset 320
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movl %esi, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movss %xmm3, 24(%rsp)
movss %xmm4, 20(%rsp)
movss %xmm5, 16(%rsp)
movss %xmm6, 12(%rsp)
movss %xmm7, 8(%rsp)
movq %rdx, 104(%rsp)
movq %rcx, 96(%rsp)
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 320(%rsp), %rax
movq %rax, 192(%rsp)
leaq 104(%rsp), %rax
movq %rax, 200(%rsp)
leaq 96(%rsp), %rax
movq %rax, 208(%rsp)
leaq 328(%rsp), %rax
movq %rax, 216(%rsp)
leaq 336(%rsp), %rax
movq %rax, 224(%rsp)
leaq 344(%rsp), %rax
movq %rax, 232(%rsp)
leaq 352(%rsp), %rax
movq %rax, 240(%rsp)
leaq 360(%rsp), %rax
movq %rax, 248(%rsp)
leaq 368(%rsp), %rax
movq %rax, 256(%rsp)
leaq 376(%rsp), %rax
movq %rax, 264(%rsp)
leaq 384(%rsp), %rax
movq %rax, 272(%rsp)
leaq 392(%rsp), %rax
movq %rax, 280(%rsp)
leaq 400(%rsp), %rax
movq %rax, 288(%rsp)
leaq 408(%rsp), %rax
movq %rax, 296(%rsp)
leaq 416(%rsp), %rax
movq %rax, 304(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7computefiiffffffffPfS_ffffffffffff, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $328, %rsp # imm = 0x148
.cfi_adjust_cfa_offset -328
retq
.Lfunc_end0:
.size _Z22__device_stub__computefiiffffffffPfS_ffffffffffff, .Lfunc_end0-_Z22__device_stub__computefiiffffffffPfS_ffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movq 8(%rsi), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
callq strtod
movsd %xmm0, 272(%rsp) # 8-byte Spill
movq 16(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 32(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 264(%rsp) # 8-byte Spill
movq 40(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 256(%rsp) # 8-byte Spill
movq 48(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq 56(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 136(%rsp) # 8-byte Spill
movq 64(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 128(%rsp) # 8-byte Spill
movq 72(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq 80(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 248(%rsp) # 8-byte Spill
movq 88(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 240(%rsp) # 8-byte Spill
movq 96(%r15), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 112(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 112(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r12
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r12,%r13,4)
incq %r13
cmpq $10, %r13
jne .LBB2_1
# %bb.2: # %_Z11initPointerf.exit
movq 104(%r15), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 112(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 112(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r13
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r13,%rbp,4)
incq %rbp
cmpq $10, %rbp
jne .LBB2_3
# %bb.4: # %_Z11initPointerf.exit54
movq 112(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 112(%rsp) # 8-byte Spill
movq 120(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movq 128(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 136(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 144(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 152(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 160(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 168(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 176(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movq 184(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 192(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 200(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 152(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movsd 152(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 160(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 168(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 240(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 248(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 112(%rsp) # 4-byte Spill
movsd 120(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 120(%rsp) # 4-byte Spill
movsd 128(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 128(%rsp) # 4-byte Spill
movsd 136(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 136(%rsp) # 4-byte Spill
movsd 144(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 144(%rsp) # 4-byte Spill
movsd 256(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 264(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 272(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 96(%rsp)
movss %xmm9, 88(%rsp)
movss %xmm10, 80(%rsp)
movss %xmm11, 72(%rsp)
movss %xmm12, 64(%rsp)
movss %xmm13, 56(%rsp)
movss %xmm14, 48(%rsp)
movss %xmm15, 40(%rsp)
movss %xmm3, 32(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 16(%rsp)
movss %xmm6, 8(%rsp)
movss %xmm7, (%rsp)
movl %ebx, %edi
movl %r14d, %esi
movss 144(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss 136(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 128(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 120(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 112(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
movq %r12, %rdx
movq %r13, %rcx
callq _Z22__device_stub__computefiiffffffffPfS_ffffffffffff
.LBB2_6:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefiiffffffffPfS_ffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefiiffffffffPfS_ffffffffffff,@object # @_Z7computefiiffffffffPfS_ffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefiiffffffffPfS_ffffffffffff
.p2align 3, 0x0
_Z7computefiiffffffffPfS_ffffffffffff:
.quad _Z22__device_stub__computefiiffffffffPfS_ffffffffffff
.size _Z7computefiiffffffffPfS_ffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefiiffffffffPfS_ffffffffffff"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefiiffffffffPfS_ffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefiiffffffffPfS_ffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //---------------------------------------------------------------------------------
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <iostream>
//---------------------------------------------------------------------------------
static const int N = 1000001; //Number of rows in input matrix
static const int M = 100; //Number of columns in input matrix
using namespace std;
//---------------------------------------------------------------------------------
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN(value) { \
cudaError_t _m_cudaStat = value; \
if (_m_cudaStat != cudaSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
//---------------------------------------------------------------------------------
__global__ void matrixTranspose(unsigned int* A_d, unsigned int *T_d, int rowCount, int colCount) {
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Populate vecADD kernel function ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if (row < rowCount && col < colCount){
T_d[col*rowCount+row] = A_d[row*colCount+col];
}
}
//---------------------------------------------------------------------------------
int main(void) {
unsigned int **A ;
unsigned int **T ;
unsigned int *A_h;
unsigned int *A_d;
unsigned int *T_h;
unsigned int *T_d;
//Set Device
CUDA_CHECK_RETURN(cudaSetDevice(0));
//See random number generator
srand(time(NULL));
//Clear command prompt
cout << "\033[2J\033[1;1H";
cout << "Allocating arrays on host ... ";
A_h = new unsigned int[N*M];
T_h = new unsigned int[N*M];
A = new unsigned int* [N];
for (int i = 0; i < N; ++i) {
A[i] = new unsigned int[M];
}
T = new unsigned int* [M];
for (int i = 0; i < M; ++i) {
T[i] = new unsigned int[N];
}
cout << "done.\nPopluating input matrix on host ... ";
for (int i = 0; i < N; ++i) {
for (int j = 0; j < M; ++j) {
A[i][j] = rand();
}
}
cout << "done.\nConverting 2-dimensional input matrix to 1-dimensional array on host ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add code for converting 2-dimensional input matrix to 1-dimensional array here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for (int i = 0; i < N; ++i) {
for (int j = 0; j < M; ++j) {
A_h[i*M+j] = A[i][j];
}
}
cout << "done.\nAllocating arrays on device ... ";
CUDA_CHECK_RETURN(
cudaMalloc((void** ) &A_d, sizeof(unsigned int) * N*M));
CUDA_CHECK_RETURN(
cudaMalloc((void** ) &T_d, sizeof(unsigned int) * N*M));
cout << "done.\nCopying arrays from host to device ... ";
CUDA_CHECK_RETURN(
cudaMemcpy(A_d, A_h, sizeof(int) * N*M,
cudaMemcpyHostToDevice));
cout << "done.\nLaunching kernel ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** define kernel launch parameters ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
dim3 dimBlock(32,32);
dim3 dimGrid(ceil((double)M/32), ceil((double)N/32));
//Time kernel launch
//Time kernel launch
cudaEvent_t start, stop;
CUDA_CHECK_RETURN(cudaEventCreate(&start));
CUDA_CHECK_RETURN(cudaEventCreate(&stop));
float elapsedTime;
CUDA_CHECK_RETURN(cudaEventRecord(start, 0));
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add kernel call here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
matrixTranspose<<< dimGrid, dimBlock >>>(A_d, T_d, N, M);
CUDA_CHECK_RETURN(cudaEventRecord(stop, 0));
CUDA_CHECK_RETURN(cudaEventSynchronize(stop));
CUDA_CHECK_RETURN(cudaEventElapsedTime(&elapsedTime, start, stop));
CUDA_CHECK_RETURN(cudaThreadSynchronize()); // Wait for the GPU launched work to complete
CUDA_CHECK_RETURN(cudaGetLastError()); //Check if an error occurred in device code
CUDA_CHECK_RETURN(cudaEventDestroy(start));
CUDA_CHECK_RETURN(cudaEventDestroy(stop));
cout << "done.\nElapsed kernel time: " << elapsedTime << " ms\n";
cout << "Copying results back to host .... ";
CUDA_CHECK_RETURN(
cudaMemcpy(T_h, T_d, sizeof(int) * N*M,
cudaMemcpyDeviceToHost));
cout << "done.\nConverting 1-dimensional output array to 2-dimensional matrix on host ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
//**** Add code for converting 1-dimensional output array to 2-dimensional matrix here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for (int i = 0; i < M; ++i) {
for (int j = 0; j < N; ++j) {
T[i][j] = T_h[i*N+j];
}
}
cout << "done.\nVerifying results on host ... ";
//Add code to time host calculations
clock_t st, ed;
st = clock();
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Check that results from kernel are correct ****
// **** Complete validation code below ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
bool valid = true;
for (int i = 0; i < M; i++){
for(int j = 0; j < N; j++){
if (T[i][j] != A[j][i])
{
cout << "done.\n***GPU results are incorrect***";
valid = false;
break;
}
}
if(!valid){
break;
}
}
cout << "done\n";
if (valid) {
cout << "GPU results are valid.\n";
}
ed = clock() - st;
cout << "Elapsed time on host: " << ((float) ed) / CLOCKS_PER_SEC * 1000
<< " ms" << endl;
cout << "Freeing memory on device ... ";
CUDA_CHECK_RETURN(cudaFree((void* ) A_d));
CUDA_CHECK_RETURN(cudaFree((void* ) T_d));
CUDA_CHECK_RETURN(cudaDeviceReset());
cout << "done.\nFreeing memory on host ... ";
delete[] A_h;
delete[] T_h;
for (int i = 0; i < N; ++i) {
delete[] A[i];
}
delete[] A;
for (int i = 0; i < M; ++i) {
delete[] T[i];
}
delete[] T;
cout << "done.\nExiting program.\n";
return 0;
} | code for sm_80
Function : _Z15matrixTransposePjS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x170], P0 ; /* 0x00005c0005007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R5, c[0x0][0x174], R0 ; /* 0x00005d0005027a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0204 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD R5, R0, c[0x0][0x170], R5 ; /* 0x00005c0000057a24 */
/* 0x000fc800078e0205 */
/*0100*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0204 */
/*0110*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //---------------------------------------------------------------------------------
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <iostream>
//---------------------------------------------------------------------------------
static const int N = 1000001; //Number of rows in input matrix
static const int M = 100; //Number of columns in input matrix
using namespace std;
//---------------------------------------------------------------------------------
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN(value) { \
cudaError_t _m_cudaStat = value; \
if (_m_cudaStat != cudaSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
//---------------------------------------------------------------------------------
__global__ void matrixTranspose(unsigned int* A_d, unsigned int *T_d, int rowCount, int colCount) {
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Populate vecADD kernel function ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if (row < rowCount && col < colCount){
T_d[col*rowCount+row] = A_d[row*colCount+col];
}
}
//---------------------------------------------------------------------------------
int main(void) {
unsigned int **A ;
unsigned int **T ;
unsigned int *A_h;
unsigned int *A_d;
unsigned int *T_h;
unsigned int *T_d;
//Set Device
CUDA_CHECK_RETURN(cudaSetDevice(0));
//See random number generator
srand(time(NULL));
//Clear command prompt
cout << "\033[2J\033[1;1H";
cout << "Allocating arrays on host ... ";
A_h = new unsigned int[N*M];
T_h = new unsigned int[N*M];
A = new unsigned int* [N];
for (int i = 0; i < N; ++i) {
A[i] = new unsigned int[M];
}
T = new unsigned int* [M];
for (int i = 0; i < M; ++i) {
T[i] = new unsigned int[N];
}
cout << "done.\nPopluating input matrix on host ... ";
for (int i = 0; i < N; ++i) {
for (int j = 0; j < M; ++j) {
A[i][j] = rand();
}
}
cout << "done.\nConverting 2-dimensional input matrix to 1-dimensional array on host ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add code for converting 2-dimensional input matrix to 1-dimensional array here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for (int i = 0; i < N; ++i) {
for (int j = 0; j < M; ++j) {
A_h[i*M+j] = A[i][j];
}
}
cout << "done.\nAllocating arrays on device ... ";
CUDA_CHECK_RETURN(
cudaMalloc((void** ) &A_d, sizeof(unsigned int) * N*M));
CUDA_CHECK_RETURN(
cudaMalloc((void** ) &T_d, sizeof(unsigned int) * N*M));
cout << "done.\nCopying arrays from host to device ... ";
CUDA_CHECK_RETURN(
cudaMemcpy(A_d, A_h, sizeof(int) * N*M,
cudaMemcpyHostToDevice));
cout << "done.\nLaunching kernel ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** define kernel launch parameters ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
dim3 dimBlock(32,32);
dim3 dimGrid(ceil((double)M/32), ceil((double)N/32));
//Time kernel launch
//Time kernel launch
cudaEvent_t start, stop;
CUDA_CHECK_RETURN(cudaEventCreate(&start));
CUDA_CHECK_RETURN(cudaEventCreate(&stop));
float elapsedTime;
CUDA_CHECK_RETURN(cudaEventRecord(start, 0));
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add kernel call here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
matrixTranspose<<< dimGrid, dimBlock >>>(A_d, T_d, N, M);
CUDA_CHECK_RETURN(cudaEventRecord(stop, 0));
CUDA_CHECK_RETURN(cudaEventSynchronize(stop));
CUDA_CHECK_RETURN(cudaEventElapsedTime(&elapsedTime, start, stop));
CUDA_CHECK_RETURN(cudaThreadSynchronize()); // Wait for the GPU launched work to complete
CUDA_CHECK_RETURN(cudaGetLastError()); //Check if an error occurred in device code
CUDA_CHECK_RETURN(cudaEventDestroy(start));
CUDA_CHECK_RETURN(cudaEventDestroy(stop));
cout << "done.\nElapsed kernel time: " << elapsedTime << " ms\n";
cout << "Copying results back to host .... ";
CUDA_CHECK_RETURN(
cudaMemcpy(T_h, T_d, sizeof(int) * N*M,
cudaMemcpyDeviceToHost));
cout << "done.\nConverting 1-dimensional output array to 2-dimensional matrix on host ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
//**** Add code for converting 1-dimensional output array to 2-dimensional matrix here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for (int i = 0; i < M; ++i) {
for (int j = 0; j < N; ++j) {
T[i][j] = T_h[i*N+j];
}
}
cout << "done.\nVerifying results on host ... ";
//Add code to time host calculations
clock_t st, ed;
st = clock();
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Check that results from kernel are correct ****
// **** Complete validation code below ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
bool valid = true;
for (int i = 0; i < M; i++){
for(int j = 0; j < N; j++){
if (T[i][j] != A[j][i])
{
cout << "done.\n***GPU results are incorrect***";
valid = false;
break;
}
}
if(!valid){
break;
}
}
cout << "done\n";
if (valid) {
cout << "GPU results are valid.\n";
}
ed = clock() - st;
cout << "Elapsed time on host: " << ((float) ed) / CLOCKS_PER_SEC * 1000
<< " ms" << endl;
cout << "Freeing memory on device ... ";
CUDA_CHECK_RETURN(cudaFree((void* ) A_d));
CUDA_CHECK_RETURN(cudaFree((void* ) T_d));
CUDA_CHECK_RETURN(cudaDeviceReset());
cout << "done.\nFreeing memory on host ... ";
delete[] A_h;
delete[] T_h;
for (int i = 0; i < N; ++i) {
delete[] A[i];
}
delete[] A;
for (int i = 0; i < M; ++i) {
delete[] T[i];
}
delete[] T;
cout << "done.\nExiting program.\n";
return 0;
} | .file "tmpxft_000d3f26_00000000-6_transposenxm.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15matrixTransposePjS_iiPjS_ii
.type _Z39__device_stub__Z15matrixTransposePjS_iiPjS_ii, @function
_Z39__device_stub__Z15matrixTransposePjS_iiPjS_ii:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrixTransposePjS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z39__device_stub__Z15matrixTransposePjS_iiPjS_ii, .-_Z39__device_stub__Z15matrixTransposePjS_iiPjS_ii
.globl _Z15matrixTransposePjS_ii
.type _Z15matrixTransposePjS_ii, @function
_Z15matrixTransposePjS_ii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15matrixTransposePjS_iiPjS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z15matrixTransposePjS_ii, .-_Z15matrixTransposePjS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/kusht07/Parallel-Cuda-codes/master/transposeMat/src/transposenxm.cu"
.align 8
.LC1:
.string "Error %s at line %d in file %s\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "\033[2J\033[1;1H"
.section .rodata.str1.8
.align 8
.LC3:
.string "Allocating arrays on host ... "
.align 8
.LC4:
.string "done.\nPopluating input matrix on host ... "
.align 8
.LC5:
.string "done.\nConverting 2-dimensional input matrix to 1-dimensional array on host ... "
.align 8
.LC6:
.string "done.\nAllocating arrays on device ... "
.align 8
.LC7:
.string "done.\nCopying arrays from host to device ... "
.section .rodata.str1.1
.LC8:
.string "done.\nLaunching kernel ... "
.LC9:
.string "done.\nElapsed kernel time: "
.LC10:
.string " ms\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "Copying results back to host .... "
.align 8
.LC12:
.string "done.\nConverting 1-dimensional output array to 2-dimensional matrix on host ... "
.align 8
.LC13:
.string "done.\nVerifying results on host ... "
.align 8
.LC14:
.string "done.\n***GPU results are incorrect***"
.section .rodata.str1.1
.LC15:
.string "done\n"
.LC16:
.string "GPU results are valid.\n"
.LC17:
.string "Elapsed time on host: "
.LC20:
.string " ms"
.LC21:
.string "Freeing memory on device ... "
.section .rodata.str1.8
.align 8
.LC22:
.string "done.\nFreeing memory on host ... "
.section .rodata.str1.1
.LC23:
.string "done.\nExiting program.\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
movl %eax, %r14d
testl %eax, %eax
jne .L61
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $400000400, %edi
call _Znam@PLT
movq %rax, 24(%rsp)
movl $400000400, %edi
call _Znam@PLT
movq %rax, 32(%rsp)
movl $8000008, %edi
call _Znam@PLT
movq %rax, %rbx
movq %rax, 16(%rsp)
movq %rax, %r13
leaq 8000008(%rax), %r15
.L13:
movl $400, %edi
call _Znam@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %r15, %rbx
jne .L13
movl $800, %edi
call _Znam@PLT
movq %rax, %rbx
movq %rax, 40(%rsp)
movq %rax, %r12
leaq 800(%rax), %rax
movq %rax, 8(%rsp)
.L14:
movl $4000004, %edi
call _Znam@PLT
movq %rax, (%rbx)
addq $8, %rbx
movq 8(%rsp), %rax
cmpq %rax, %rbx
jne .L14
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 16(%rsp), %rbp
.L15:
movl $0, %ebx
.L16:
call rand@PLT
movq 0(%rbp), %rdx
movl %eax, (%rdx,%rbx)
addq $4, %rbx
cmpq $400, %rbx
jne .L16
addq $8, %rbp
cmpq %r15, %rbp
jne .L15
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 24(%rsp), %rcx
movq 16(%rsp), %rdi
.L18:
movq (%rdi), %rsi
movl $0, %eax
.L19:
movl (%rsi,%rax), %edx
movl %edx, (%rcx,%rax)
addq $4, %rax
cmpq $400, %rax
jne .L19
addq $8, %rdi
addl $100, %r14d
addq $400, %rcx
cmpl $100000100, %r14d
jne .L18
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 64(%rsp), %rdi
movl $400000400, %esi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L62
leaq 72(%rsp), %rdi
movl $400000400, %esi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L63
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $1, %ecx
movl $400000400, %edx
movq 24(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
testl %eax, %eax
jne .L64
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $32, 96(%rsp)
movl $32, 100(%rsp)
movl $1, 104(%rsp)
movl $4, 108(%rsp)
movl $31251, 112(%rsp)
movl $1, 116(%rsp)
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
testl %eax, %eax
jne .L65
leaq 88(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
testl %eax, %eax
jne .L66
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
testl %eax, %eax
jne .L67
movl 104(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movq 108(%rsp), %rdi
movl 116(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L68
.L27:
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
testl %eax, %eax
jne .L69
movq 88(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %edi
testl %eax, %eax
jne .L70
leaq 60(%rsp), %rdi
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %edi
testl %eax, %eax
jne .L71
call cudaThreadSynchronize@PLT
movl %eax, %edi
testl %eax, %eax
jne .L72
call cudaGetLastError@PLT
movl %eax, %edi
testl %eax, %eax
jne .L73
movq 80(%rsp), %rdi
call cudaEventDestroy@PLT
movl %eax, %edi
testl %eax, %eax
jne .L74
movq 88(%rsp), %rdi
call cudaEventDestroy@PLT
movl %eax, %edi
testl %eax, %eax
jne .L75
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC10(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC11(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $2, %ecx
movl $400000400, %edx
movq 72(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L76
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 32(%rsp), %rcx
movq 40(%rsp), %rdi
jmp .L36
.L61:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $50, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L62:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $92, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L63:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $94, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L64:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $98, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L65:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $114, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L66:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $115, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L67:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $118, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L68:
movl $100, %ecx
movl $1000001, %edx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z39__device_stub__Z15matrixTransposePjS_iiPjS_ii
jmp .L27
.L69:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $128, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L70:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $130, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L71:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $131, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L72:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $132, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L73:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $133, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L74:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $134, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L75:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $135, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L76:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $139, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L77:
addq $8, %rdi
addl $1000001, %ebx
addq $4000004, %rcx
cmpl $100000100, %ebx
je .L38
.L36:
movq (%rdi), %rsi
movl $0, %eax
.L37:
movl (%rcx,%rax), %edx
movl %edx, (%rsi,%rax)
addq $4, %rax
cmpq $4000004, %rax
jne .L37
jmp .L77
.L38:
leaq .LC13(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call clock@PLT
movq %rax, %rbp
movl $0, %eax
.L39:
movq 40(%rsp), %rdi
movq (%rdi,%rax,2), %rcx
movl $0, %edx
.L42:
movq 16(%rsp), %rdi
movq (%rdi,%rdx,8), %rsi
movl (%rsi,%rax), %edi
cmpl %edi, (%rcx,%rdx,4)
jne .L78
addq $1, %rdx
cmpq $1000001, %rdx
jne .L42
addq $4, %rax
cmpq $400, %rax
jne .L39
leaq .LC15(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC16(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L41
.L78:
leaq .LC14(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC15(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L41:
call clock@PLT
subq %rbp, %rax
movq %rax, %r14
leaq .LC17(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtsi2ssq %r14, %xmm0
divss .LC18(%rip), %xmm0
mulss .LC19(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC20(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC21(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
testl %eax, %eax
jne .L79
movq 72(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
testl %eax, %eax
jne .L80
call cudaDeviceReset@PLT
movl %eax, %edi
testl %eax, %eax
jne .L81
leaq .LC22(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 24(%rsp), %rdi
call _ZdaPv@PLT
movq 32(%rsp), %rdi
call _ZdaPv@PLT
jmp .L48
.L79:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $196, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L80:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $197, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L81:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $198, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L47:
addq $8, %r13
cmpq %r15, %r13
je .L82
.L48:
movq 0(%r13), %rdi
testq %rdi, %rdi
je .L47
call _ZdaPv@PLT
jmp .L47
.L82:
movq 16(%rsp), %rdi
call _ZdaPv@PLT
jmp .L50
.L49:
addq $8, %r12
movq 8(%rsp), %rax
cmpq %rax, %r12
je .L83
.L50:
movq (%r12), %rdi
testq %rdi, %rdi
je .L49
call _ZdaPv@PLT
jmp .L49
.L83:
movq 40(%rsp), %rdi
call _ZdaPv@PLT
leaq .LC23(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L84
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L84:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC24:
.string "_Z15matrixTransposePjS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC24(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixTransposePjS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC18:
.long 1232348160
.align 4
.LC19:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //---------------------------------------------------------------------------------
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <iostream>
//---------------------------------------------------------------------------------
static const int N = 1000001; //Number of rows in input matrix
static const int M = 100; //Number of columns in input matrix
using namespace std;
//---------------------------------------------------------------------------------
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN(value) { \
cudaError_t _m_cudaStat = value; \
if (_m_cudaStat != cudaSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
//---------------------------------------------------------------------------------
__global__ void matrixTranspose(unsigned int* A_d, unsigned int *T_d, int rowCount, int colCount) {
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Populate vecADD kernel function ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if (row < rowCount && col < colCount){
T_d[col*rowCount+row] = A_d[row*colCount+col];
}
}
//---------------------------------------------------------------------------------
int main(void) {
unsigned int **A ;
unsigned int **T ;
unsigned int *A_h;
unsigned int *A_d;
unsigned int *T_h;
unsigned int *T_d;
//Set Device
CUDA_CHECK_RETURN(cudaSetDevice(0));
//See random number generator
srand(time(NULL));
//Clear command prompt
cout << "\033[2J\033[1;1H";
cout << "Allocating arrays on host ... ";
A_h = new unsigned int[N*M];
T_h = new unsigned int[N*M];
A = new unsigned int* [N];
for (int i = 0; i < N; ++i) {
A[i] = new unsigned int[M];
}
T = new unsigned int* [M];
for (int i = 0; i < M; ++i) {
T[i] = new unsigned int[N];
}
cout << "done.\nPopluating input matrix on host ... ";
for (int i = 0; i < N; ++i) {
for (int j = 0; j < M; ++j) {
A[i][j] = rand();
}
}
cout << "done.\nConverting 2-dimensional input matrix to 1-dimensional array on host ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add code for converting 2-dimensional input matrix to 1-dimensional array here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for (int i = 0; i < N; ++i) {
for (int j = 0; j < M; ++j) {
A_h[i*M+j] = A[i][j];
}
}
cout << "done.\nAllocating arrays on device ... ";
CUDA_CHECK_RETURN(
cudaMalloc((void** ) &A_d, sizeof(unsigned int) * N*M));
CUDA_CHECK_RETURN(
cudaMalloc((void** ) &T_d, sizeof(unsigned int) * N*M));
cout << "done.\nCopying arrays from host to device ... ";
CUDA_CHECK_RETURN(
cudaMemcpy(A_d, A_h, sizeof(int) * N*M,
cudaMemcpyHostToDevice));
cout << "done.\nLaunching kernel ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** define kernel launch parameters ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
dim3 dimBlock(32,32);
dim3 dimGrid(ceil((double)M/32), ceil((double)N/32));
//Time kernel launch
//Time kernel launch
cudaEvent_t start, stop;
CUDA_CHECK_RETURN(cudaEventCreate(&start));
CUDA_CHECK_RETURN(cudaEventCreate(&stop));
float elapsedTime;
CUDA_CHECK_RETURN(cudaEventRecord(start, 0));
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add kernel call here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
matrixTranspose<<< dimGrid, dimBlock >>>(A_d, T_d, N, M);
CUDA_CHECK_RETURN(cudaEventRecord(stop, 0));
CUDA_CHECK_RETURN(cudaEventSynchronize(stop));
CUDA_CHECK_RETURN(cudaEventElapsedTime(&elapsedTime, start, stop));
CUDA_CHECK_RETURN(cudaThreadSynchronize()); // Wait for the GPU launched work to complete
CUDA_CHECK_RETURN(cudaGetLastError()); //Check if an error occurred in device code
CUDA_CHECK_RETURN(cudaEventDestroy(start));
CUDA_CHECK_RETURN(cudaEventDestroy(stop));
cout << "done.\nElapsed kernel time: " << elapsedTime << " ms\n";
cout << "Copying results back to host .... ";
CUDA_CHECK_RETURN(
cudaMemcpy(T_h, T_d, sizeof(int) * N*M,
cudaMemcpyDeviceToHost));
cout << "done.\nConverting 1-dimensional output array to 2-dimensional matrix on host ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
//**** Add code for converting 1-dimensional output array to 2-dimensional matrix here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for (int i = 0; i < M; ++i) {
for (int j = 0; j < N; ++j) {
T[i][j] = T_h[i*N+j];
}
}
cout << "done.\nVerifying results on host ... ";
//Add code to time host calculations
clock_t st, ed;
st = clock();
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Check that results from kernel are correct ****
// **** Complete validation code below ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
bool valid = true;
for (int i = 0; i < M; i++){
for(int j = 0; j < N; j++){
if (T[i][j] != A[j][i])
{
cout << "done.\n***GPU results are incorrect***";
valid = false;
break;
}
}
if(!valid){
break;
}
}
cout << "done\n";
if (valid) {
cout << "GPU results are valid.\n";
}
ed = clock() - st;
cout << "Elapsed time on host: " << ((float) ed) / CLOCKS_PER_SEC * 1000
<< " ms" << endl;
cout << "Freeing memory on device ... ";
CUDA_CHECK_RETURN(cudaFree((void* ) A_d));
CUDA_CHECK_RETURN(cudaFree((void* ) T_d));
CUDA_CHECK_RETURN(cudaDeviceReset());
cout << "done.\nFreeing memory on host ... ";
delete[] A_h;
delete[] T_h;
for (int i = 0; i < N; ++i) {
delete[] A[i];
}
delete[] A;
for (int i = 0; i < M; ++i) {
delete[] T[i];
}
delete[] T;
cout << "done.\nExiting program.\n";
return 0;
} | //---------------------------------------------------------------------------------
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <iostream>
//---------------------------------------------------------------------------------
static const int N = 1000001; //Number of rows in input matrix
static const int M = 100; //Number of columns in input matrix
using namespace std;
//---------------------------------------------------------------------------------
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN(value) { \
hipError_t _m_cudaStat = value; \
if (_m_cudaStat != hipSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
hipGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
//---------------------------------------------------------------------------------
__global__ void matrixTranspose(unsigned int* A_d, unsigned int *T_d, int rowCount, int colCount) {
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Populate vecADD kernel function ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if (row < rowCount && col < colCount){
T_d[col*rowCount+row] = A_d[row*colCount+col];
}
}
//---------------------------------------------------------------------------------
int main(void) {
unsigned int **A ;
unsigned int **T ;
unsigned int *A_h;
unsigned int *A_d;
unsigned int *T_h;
unsigned int *T_d;
//Set Device
CUDA_CHECK_RETURN(hipSetDevice(0));
//See random number generator
srand(time(NULL));
//Clear command prompt
cout << "\033[2J\033[1;1H";
cout << "Allocating arrays on host ... ";
A_h = new unsigned int[N*M];
T_h = new unsigned int[N*M];
A = new unsigned int* [N];
for (int i = 0; i < N; ++i) {
A[i] = new unsigned int[M];
}
T = new unsigned int* [M];
for (int i = 0; i < M; ++i) {
T[i] = new unsigned int[N];
}
cout << "done.\nPopluating input matrix on host ... ";
for (int i = 0; i < N; ++i) {
for (int j = 0; j < M; ++j) {
A[i][j] = rand();
}
}
cout << "done.\nConverting 2-dimensional input matrix to 1-dimensional array on host ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add code for converting 2-dimensional input matrix to 1-dimensional array here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for (int i = 0; i < N; ++i) {
for (int j = 0; j < M; ++j) {
A_h[i*M+j] = A[i][j];
}
}
cout << "done.\nAllocating arrays on device ... ";
CUDA_CHECK_RETURN(
hipMalloc((void** ) &A_d, sizeof(unsigned int) * N*M));
CUDA_CHECK_RETURN(
hipMalloc((void** ) &T_d, sizeof(unsigned int) * N*M));
cout << "done.\nCopying arrays from host to device ... ";
CUDA_CHECK_RETURN(
hipMemcpy(A_d, A_h, sizeof(int) * N*M,
hipMemcpyHostToDevice));
cout << "done.\nLaunching kernel ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** define kernel launch parameters ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
dim3 dimBlock(32,32);
dim3 dimGrid(ceil((double)M/32), ceil((double)N/32));
//Time kernel launch
//Time kernel launch
hipEvent_t start, stop;
CUDA_CHECK_RETURN(hipEventCreate(&start));
CUDA_CHECK_RETURN(hipEventCreate(&stop));
float elapsedTime;
CUDA_CHECK_RETURN(hipEventRecord(start, 0));
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add kernel call here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
matrixTranspose<<< dimGrid, dimBlock >>>(A_d, T_d, N, M);
CUDA_CHECK_RETURN(hipEventRecord(stop, 0));
CUDA_CHECK_RETURN(hipEventSynchronize(stop));
CUDA_CHECK_RETURN(hipEventElapsedTime(&elapsedTime, start, stop));
CUDA_CHECK_RETURN(hipDeviceSynchronize()); // Wait for the GPU launched work to complete
CUDA_CHECK_RETURN(hipGetLastError()); //Check if an error occurred in device code
CUDA_CHECK_RETURN(hipEventDestroy(start));
CUDA_CHECK_RETURN(hipEventDestroy(stop));
cout << "done.\nElapsed kernel time: " << elapsedTime << " ms\n";
cout << "Copying results back to host .... ";
CUDA_CHECK_RETURN(
hipMemcpy(T_h, T_d, sizeof(int) * N*M,
hipMemcpyDeviceToHost));
cout << "done.\nConverting 1-dimensional output array to 2-dimensional matrix on host ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
//**** Add code for converting 1-dimensional output array to 2-dimensional matrix here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for (int i = 0; i < M; ++i) {
for (int j = 0; j < N; ++j) {
T[i][j] = T_h[i*N+j];
}
}
cout << "done.\nVerifying results on host ... ";
//Add code to time host calculations
clock_t st, ed;
st = clock();
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Check that results from kernel are correct ****
// **** Complete validation code below ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
bool valid = true;
for (int i = 0; i < M; i++){
for(int j = 0; j < N; j++){
if (T[i][j] != A[j][i])
{
cout << "done.\n***GPU results are incorrect***";
valid = false;
break;
}
}
if(!valid){
break;
}
}
cout << "done\n";
if (valid) {
cout << "GPU results are valid.\n";
}
ed = clock() - st;
cout << "Elapsed time on host: " << ((float) ed) / CLOCKS_PER_SEC * 1000
<< " ms" << endl;
cout << "Freeing memory on device ... ";
CUDA_CHECK_RETURN(hipFree((void* ) A_d));
CUDA_CHECK_RETURN(hipFree((void* ) T_d));
CUDA_CHECK_RETURN(hipDeviceReset());
cout << "done.\nFreeing memory on host ... ";
delete[] A_h;
delete[] T_h;
for (int i = 0; i < N; ++i) {
delete[] A[i];
}
delete[] A;
for (int i = 0; i < M; ++i) {
delete[] T[i];
}
delete[] T;
cout << "done.\nExiting program.\n";
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //---------------------------------------------------------------------------------
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <iostream>
//---------------------------------------------------------------------------------
static const int N = 1000001; //Number of rows in input matrix
static const int M = 100; //Number of columns in input matrix
using namespace std;
//---------------------------------------------------------------------------------
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN(value) { \
hipError_t _m_cudaStat = value; \
if (_m_cudaStat != hipSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
hipGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
//---------------------------------------------------------------------------------
__global__ void matrixTranspose(unsigned int* A_d, unsigned int *T_d, int rowCount, int colCount) {
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Populate vecADD kernel function ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if (row < rowCount && col < colCount){
T_d[col*rowCount+row] = A_d[row*colCount+col];
}
}
//---------------------------------------------------------------------------------
int main(void) {
unsigned int **A ;
unsigned int **T ;
unsigned int *A_h;
unsigned int *A_d;
unsigned int *T_h;
unsigned int *T_d;
//Set Device
CUDA_CHECK_RETURN(hipSetDevice(0));
//See random number generator
srand(time(NULL));
//Clear command prompt
cout << "\033[2J\033[1;1H";
cout << "Allocating arrays on host ... ";
A_h = new unsigned int[N*M];
T_h = new unsigned int[N*M];
A = new unsigned int* [N];
for (int i = 0; i < N; ++i) {
A[i] = new unsigned int[M];
}
T = new unsigned int* [M];
for (int i = 0; i < M; ++i) {
T[i] = new unsigned int[N];
}
cout << "done.\nPopluating input matrix on host ... ";
for (int i = 0; i < N; ++i) {
for (int j = 0; j < M; ++j) {
A[i][j] = rand();
}
}
cout << "done.\nConverting 2-dimensional input matrix to 1-dimensional array on host ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add code for converting 2-dimensional input matrix to 1-dimensional array here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for (int i = 0; i < N; ++i) {
for (int j = 0; j < M; ++j) {
A_h[i*M+j] = A[i][j];
}
}
cout << "done.\nAllocating arrays on device ... ";
CUDA_CHECK_RETURN(
hipMalloc((void** ) &A_d, sizeof(unsigned int) * N*M));
CUDA_CHECK_RETURN(
hipMalloc((void** ) &T_d, sizeof(unsigned int) * N*M));
cout << "done.\nCopying arrays from host to device ... ";
CUDA_CHECK_RETURN(
hipMemcpy(A_d, A_h, sizeof(int) * N*M,
hipMemcpyHostToDevice));
cout << "done.\nLaunching kernel ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** define kernel launch parameters ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
dim3 dimBlock(32,32);
dim3 dimGrid(ceil((double)M/32), ceil((double)N/32));
//Time kernel launch
//Time kernel launch
hipEvent_t start, stop;
CUDA_CHECK_RETURN(hipEventCreate(&start));
CUDA_CHECK_RETURN(hipEventCreate(&stop));
float elapsedTime;
CUDA_CHECK_RETURN(hipEventRecord(start, 0));
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add kernel call here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
matrixTranspose<<< dimGrid, dimBlock >>>(A_d, T_d, N, M);
CUDA_CHECK_RETURN(hipEventRecord(stop, 0));
CUDA_CHECK_RETURN(hipEventSynchronize(stop));
CUDA_CHECK_RETURN(hipEventElapsedTime(&elapsedTime, start, stop));
CUDA_CHECK_RETURN(hipDeviceSynchronize()); // Wait for the GPU launched work to complete
CUDA_CHECK_RETURN(hipGetLastError()); //Check if an error occurred in device code
CUDA_CHECK_RETURN(hipEventDestroy(start));
CUDA_CHECK_RETURN(hipEventDestroy(stop));
cout << "done.\nElapsed kernel time: " << elapsedTime << " ms\n";
cout << "Copying results back to host .... ";
CUDA_CHECK_RETURN(
hipMemcpy(T_h, T_d, sizeof(int) * N*M,
hipMemcpyDeviceToHost));
cout << "done.\nConverting 1-dimensional output array to 2-dimensional matrix on host ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
//**** Add code for converting 1-dimensional output array to 2-dimensional matrix here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for (int i = 0; i < M; ++i) {
for (int j = 0; j < N; ++j) {
T[i][j] = T_h[i*N+j];
}
}
cout << "done.\nVerifying results on host ... ";
//Add code to time host calculations
clock_t st, ed;
st = clock();
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Check that results from kernel are correct ****
// **** Complete validation code below ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
bool valid = true;
for (int i = 0; i < M; i++){
for(int j = 0; j < N; j++){
if (T[i][j] != A[j][i])
{
cout << "done.\n***GPU results are incorrect***";
valid = false;
break;
}
}
if(!valid){
break;
}
}
cout << "done\n";
if (valid) {
cout << "GPU results are valid.\n";
}
ed = clock() - st;
cout << "Elapsed time on host: " << ((float) ed) / CLOCKS_PER_SEC * 1000
<< " ms" << endl;
cout << "Freeing memory on device ... ";
CUDA_CHECK_RETURN(hipFree((void* ) A_d));
CUDA_CHECK_RETURN(hipFree((void* ) T_d));
CUDA_CHECK_RETURN(hipDeviceReset());
cout << "done.\nFreeing memory on host ... ";
delete[] A_h;
delete[] T_h;
for (int i = 0; i < N; ++i) {
delete[] A[i];
}
delete[] A;
for (int i = 0; i < M; ++i) {
delete[] T[i];
}
delete[] T;
cout << "done.\nExiting program.\n";
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15matrixTransposePjS_ii
.globl _Z15matrixTransposePjS_ii
.p2align 8
.type _Z15matrixTransposePjS_ii,@function
_Z15matrixTransposePjS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
v_cmp_gt_i32_e64 s2, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s5, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v4, v[2:3], off
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matrixTransposePjS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15matrixTransposePjS_ii, .Lfunc_end0-_Z15matrixTransposePjS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matrixTransposePjS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15matrixTransposePjS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //---------------------------------------------------------------------------------
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <iostream>
//---------------------------------------------------------------------------------
static const int N = 1000001; //Number of rows in input matrix
static const int M = 100; //Number of columns in input matrix
using namespace std;
//---------------------------------------------------------------------------------
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN(value) { \
hipError_t _m_cudaStat = value; \
if (_m_cudaStat != hipSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
hipGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
//---------------------------------------------------------------------------------
__global__ void matrixTranspose(unsigned int* A_d, unsigned int *T_d, int rowCount, int colCount) {
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Populate vecADD kernel function ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if (row < rowCount && col < colCount){
T_d[col*rowCount+row] = A_d[row*colCount+col];
}
}
//---------------------------------------------------------------------------------
int main(void) {
unsigned int **A ;
unsigned int **T ;
unsigned int *A_h;
unsigned int *A_d;
unsigned int *T_h;
unsigned int *T_d;
//Set Device
CUDA_CHECK_RETURN(hipSetDevice(0));
//See random number generator
srand(time(NULL));
//Clear command prompt
cout << "\033[2J\033[1;1H";
cout << "Allocating arrays on host ... ";
A_h = new unsigned int[N*M];
T_h = new unsigned int[N*M];
A = new unsigned int* [N];
for (int i = 0; i < N; ++i) {
A[i] = new unsigned int[M];
}
T = new unsigned int* [M];
for (int i = 0; i < M; ++i) {
T[i] = new unsigned int[N];
}
cout << "done.\nPopluating input matrix on host ... ";
for (int i = 0; i < N; ++i) {
for (int j = 0; j < M; ++j) {
A[i][j] = rand();
}
}
cout << "done.\nConverting 2-dimensional input matrix to 1-dimensional array on host ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add code for converting 2-dimensional input matrix to 1-dimensional array here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for (int i = 0; i < N; ++i) {
for (int j = 0; j < M; ++j) {
A_h[i*M+j] = A[i][j];
}
}
cout << "done.\nAllocating arrays on device ... ";
CUDA_CHECK_RETURN(
hipMalloc((void** ) &A_d, sizeof(unsigned int) * N*M));
CUDA_CHECK_RETURN(
hipMalloc((void** ) &T_d, sizeof(unsigned int) * N*M));
cout << "done.\nCopying arrays from host to device ... ";
CUDA_CHECK_RETURN(
hipMemcpy(A_d, A_h, sizeof(int) * N*M,
hipMemcpyHostToDevice));
cout << "done.\nLaunching kernel ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** define kernel launch parameters ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
dim3 dimBlock(32,32);
dim3 dimGrid(ceil((double)M/32), ceil((double)N/32));
//Time kernel launch
//Time kernel launch
hipEvent_t start, stop;
CUDA_CHECK_RETURN(hipEventCreate(&start));
CUDA_CHECK_RETURN(hipEventCreate(&stop));
float elapsedTime;
CUDA_CHECK_RETURN(hipEventRecord(start, 0));
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add kernel call here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
matrixTranspose<<< dimGrid, dimBlock >>>(A_d, T_d, N, M);
CUDA_CHECK_RETURN(hipEventRecord(stop, 0));
CUDA_CHECK_RETURN(hipEventSynchronize(stop));
CUDA_CHECK_RETURN(hipEventElapsedTime(&elapsedTime, start, stop));
CUDA_CHECK_RETURN(hipDeviceSynchronize()); // Wait for the GPU launched work to complete
CUDA_CHECK_RETURN(hipGetLastError()); //Check if an error occurred in device code
CUDA_CHECK_RETURN(hipEventDestroy(start));
CUDA_CHECK_RETURN(hipEventDestroy(stop));
cout << "done.\nElapsed kernel time: " << elapsedTime << " ms\n";
cout << "Copying results back to host .... ";
CUDA_CHECK_RETURN(
hipMemcpy(T_h, T_d, sizeof(int) * N*M,
hipMemcpyDeviceToHost));
cout << "done.\nConverting 1-dimensional output array to 2-dimensional matrix on host ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
//**** Add code for converting 1-dimensional output array to 2-dimensional matrix here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for (int i = 0; i < M; ++i) {
for (int j = 0; j < N; ++j) {
T[i][j] = T_h[i*N+j];
}
}
cout << "done.\nVerifying results on host ... ";
//Add code to time host calculations
clock_t st, ed;
st = clock();
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Check that results from kernel are correct ****
// **** Complete validation code below ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
bool valid = true;
for (int i = 0; i < M; i++){
for(int j = 0; j < N; j++){
if (T[i][j] != A[j][i])
{
cout << "done.\n***GPU results are incorrect***";
valid = false;
break;
}
}
if(!valid){
break;
}
}
cout << "done\n";
if (valid) {
cout << "GPU results are valid.\n";
}
ed = clock() - st;
cout << "Elapsed time on host: " << ((float) ed) / CLOCKS_PER_SEC * 1000
<< " ms" << endl;
cout << "Freeing memory on device ... ";
CUDA_CHECK_RETURN(hipFree((void* ) A_d));
CUDA_CHECK_RETURN(hipFree((void* ) T_d));
CUDA_CHECK_RETURN(hipDeviceReset());
cout << "done.\nFreeing memory on host ... ";
delete[] A_h;
delete[] T_h;
for (int i = 0; i < N; ++i) {
delete[] A[i];
}
delete[] A;
for (int i = 0; i < M; ++i) {
delete[] T[i];
}
delete[] T;
cout << "done.\nExiting program.\n";
return 0;
} | .text
.file "transposenxm.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__matrixTransposePjS_ii # -- Begin function _Z30__device_stub__matrixTransposePjS_ii
.p2align 4, 0x90
.type _Z30__device_stub__matrixTransposePjS_ii,@function
_Z30__device_stub__matrixTransposePjS_ii: # @_Z30__device_stub__matrixTransposePjS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrixTransposePjS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__matrixTransposePjS_ii, .Lfunc_end0-_Z30__device_stub__matrixTransposePjS_ii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x49742400 # float 1.0E+6
.LCPI1_1:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB1_1
# %bb.3:
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $30, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $400000400, %edi # imm = 0x17D78590
callq _Znam
movq %rax, %rbp
movl $400000400, %edi # imm = 0x17D78590
callq _Znam
movq %rax, %r12
movl $8000008, %edi # imm = 0x7A1208
callq _Znam
movq %rax, %r14
.p2align 4, 0x90
.LBB1_4: # =>This Inner Loop Header: Depth=1
movl $400, %edi # imm = 0x190
callq _Znam
movq %rax, (%r14,%rbx,8)
incq %rbx
cmpq $1000001, %rbx # imm = 0xF4241
jne .LBB1_4
# %bb.5:
movl $800, %edi # imm = 0x320
callq _Znam
movq %rax, %rbx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_6: # =>This Inner Loop Header: Depth=1
movl $4000004, %edi # imm = 0x3D0904
callq _Znam
movq %rax, (%rbx,%r15,8)
incq %r15
cmpq $100, %r15
jne .LBB1_6
# %bb.7:
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $42, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_8: # %.preheader162
# =>This Loop Header: Depth=1
# Child Loop BB1_9 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_9: # Parent Loop BB1_8 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movq (%r14,%r15,8), %rcx
movl %eax, (%rcx,%r13,4)
incq %r13
cmpq $100, %r13
jne .LBB1_9
# %bb.10: # in Loop: Header=BB1_8 Depth=1
incq %r15
cmpq $1000001, %r15 # imm = 0xF4241
jne .LBB1_8
# %bb.11:
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $79, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %eax, %eax
movq %rbp, %rcx
.p2align 4, 0x90
.LBB1_12: # %.preheader161
# =>This Loop Header: Depth=1
# Child Loop BB1_13 Depth 2
movq (%r14,%rax,8), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_13: # Parent Loop BB1_12 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rdx,%rsi,4), %edi
movl %edi, (%rcx,%rsi,4)
incq %rsi
cmpq $100, %rsi
jne .LBB1_13
# %bb.14: # in Loop: Header=BB1_12 Depth=1
incq %rax
addq $400, %rcx # imm = 0x190
cmpq $1000001, %rax # imm = 0xF4241
jne .LBB1_12
# %bb.15:
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $38, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 24(%rsp), %rdi
movl $400000400, %esi # imm = 0x17D78590
callq hipMalloc
testl %eax, %eax
jne .LBB1_16
# %bb.17:
leaq 16(%rsp), %rdi
movl $400000400, %esi # imm = 0x17D78590
callq hipMalloc
testl %eax, %eax
jne .LBB1_18
# %bb.19:
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $45, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 24(%rsp), %rdi
movl $400000400, %edx # imm = 0x17D78590
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_20
# %bb.21:
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 8(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_22
# %bb.23:
movq %rsp, %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_24
# %bb.25:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_26
# %bb.27:
movabsq $134222022967300, %rdi # imm = 0x7A1300000004
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_29
# %bb.28:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl $1000001, 36(%rsp) # imm = 0xF4241
movl $100, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15matrixTransposePjS_ii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_29:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_30
# %bb.31:
movq (%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB1_32
# %bb.33:
movq 8(%rsp), %rsi
movq (%rsp), %rdx
leaq 112(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB1_34
# %bb.35:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_36
# %bb.37:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_38
# %bb.39:
movq 8(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB1_40
# %bb.41:
movq (%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB1_42
# %bb.43:
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 112(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.10, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
movl $34, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 16(%rsp), %rsi
movl $400000400, %edx # imm = 0x17D78590
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_44
# %bb.45:
movl $_ZSt4cout, %edi
movl $.L.str.12, %esi
movl $80, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %eax, %eax
movq %r12, %rcx
.p2align 4, 0x90
.LBB1_46: # %.preheader160
# =>This Loop Header: Depth=1
# Child Loop BB1_47 Depth 2
movq (%rbx,%rax,8), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_47: # Parent Loop BB1_46 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rcx,%rsi,4), %edi
movl %edi, (%rdx,%rsi,4)
incq %rsi
cmpq $1000001, %rsi # imm = 0xF4241
jne .LBB1_47
# %bb.48: # in Loop: Header=BB1_46 Depth=1
incq %rax
addq $4000004, %rcx # imm = 0x3D0904
cmpq $100, %rax
jne .LBB1_46
# %bb.49:
movq %r12, 40(%rsp) # 8-byte Spill
movq %rbp, %r12
movl $_ZSt4cout, %edi
movl $.L.str.13, %esi
movl $36, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movb $1, %bpl
xorl %r15d, %r15d
callq clock
movq %rax, %r13
.p2align 4, 0x90
.LBB1_50: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_52 Depth 2
movq (%rbx,%r15,8), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_52: # Parent Loop BB1_50 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rax,%rcx,4), %edx
movq (%r14,%rcx,8), %rsi
cmpl (%rsi,%r15,4), %edx
jne .LBB1_53
# %bb.51: # in Loop: Header=BB1_52 Depth=2
incq %rcx
cmpq $1000001, %rcx # imm = 0xF4241
jne .LBB1_52
# %bb.54: # %.loopexit
# in Loop: Header=BB1_50 Depth=1
testb $1, %bpl
jne .LBB1_55
jmp .LBB1_56
.p2align 4, 0x90
.LBB1_53: # in Loop: Header=BB1_50 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.14, %esi
movl $37, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %ebp, %ebp
testb $1, %bpl
je .LBB1_56
.LBB1_55: # %.loopexit
# in Loop: Header=BB1_50 Depth=1
incq %r15
cmpq $100, %r15
jne .LBB1_50
.LBB1_56:
movl $_ZSt4cout, %edi
movl $.L.str.15, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testb $1, %bpl
je .LBB1_58
# %bb.57:
movl $_ZSt4cout, %edi
movl $.L.str.16, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB1_58:
callq clock
movq %rax, %rbp
subq %r13, %rbp
movl $_ZSt4cout, %edi
movl $.L.str.17, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cvtsi2ss %rbp, %xmm0
divss .LCPI1_0(%rip), %xmm0
mulss .LCPI1_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.18, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %rbp
testq %rbp, %rbp
je .LBB1_77
# %bb.59: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbp)
je .LBB1_61
# %bb.60:
movzbl 67(%rbp), %eax
jmp .LBB1_62
.LBB1_61:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_62: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r13, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.19, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_63
# %bb.64:
movq %r12, %r15
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
movq 40(%rsp), %r12 # 8-byte Reload
jne .LBB1_65
# %bb.66:
callq hipDeviceReset
testl %eax, %eax
jne .LBB1_67
# %bb.68:
movl $_ZSt4cout, %edi
movl $.L.str.20, %esi
movl $33, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r15, %rdi
callq _ZdaPv
movq %r12, %rdi
callq _ZdaPv
xorl %r15d, %r15d
jmp .LBB1_69
.p2align 4, 0x90
.LBB1_71: # in Loop: Header=BB1_69 Depth=1
incq %r15
cmpq $1000001, %r15 # imm = 0xF4241
je .LBB1_72
.LBB1_69: # =>This Inner Loop Header: Depth=1
movq (%r14,%r15,8), %rdi
testq %rdi, %rdi
je .LBB1_71
# %bb.70: # in Loop: Header=BB1_69 Depth=1
callq _ZdaPv
jmp .LBB1_71
.LBB1_72:
movq %r14, %rdi
callq _ZdaPv
xorl %r14d, %r14d
jmp .LBB1_73
.p2align 4, 0x90
.LBB1_75: # in Loop: Header=BB1_73 Depth=1
incq %r14
cmpq $100, %r14
je .LBB1_76
.LBB1_73: # =>This Inner Loop Header: Depth=1
movq (%rbx,%r14,8), %rdi
testq %rdi, %rdi
je .LBB1_75
# %bb.74: # in Loop: Header=BB1_73 Depth=1
callq _ZdaPv
jmp .LBB1_75
.LBB1_76:
movq %rbx, %rdi
callq _ZdaPv
movl $_ZSt4cout, %edi
movl $.L.str.21, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 208
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $52, %ecx
jmp .LBB1_2
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $95, %ecx
jmp .LBB1_2
.LBB1_18:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $97, %ecx
jmp .LBB1_2
.LBB1_20:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $102, %ecx
jmp .LBB1_2
.LBB1_22:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $116, %ecx
jmp .LBB1_2
.LBB1_24:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $117, %ecx
jmp .LBB1_2
.LBB1_26:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $120, %ecx
jmp .LBB1_2
.LBB1_30:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $130, %ecx
jmp .LBB1_2
.LBB1_32:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $132, %ecx
jmp .LBB1_2
.LBB1_34:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $133, %ecx
jmp .LBB1_2
.LBB1_36:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $134, %ecx
jmp .LBB1_2
.LBB1_38:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $135, %ecx
jmp .LBB1_2
.LBB1_40:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $136, %ecx
jmp .LBB1_2
.LBB1_42:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $137, %ecx
jmp .LBB1_2
.LBB1_44:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $143, %ecx
jmp .LBB1_2
.LBB1_77:
callq _ZSt16__throw_bad_castv
.LBB1_63:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $198, %ecx
jmp .LBB1_2
.LBB1_65:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $199, %ecx
jmp .LBB1_2
.LBB1_67:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $200, %ecx
.LBB1_2:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixTransposePjS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15matrixTransposePjS_ii,@object # @_Z15matrixTransposePjS_ii
.section .rodata,"a",@progbits
.globl _Z15matrixTransposePjS_ii
.p2align 3, 0x0
_Z15matrixTransposePjS_ii:
.quad _Z30__device_stub__matrixTransposePjS_ii
.size _Z15matrixTransposePjS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error %s at line %d in file %s\n"
.size .L.str, 32
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/kusht07/Parallel-Cuda-codes/master/transposeMat/src/transposenxm.hip"
.size .L.str.1, 126
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\033[2J\033[1
.size .L.str.2, 11
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Allocating arrays on host ... "
.size .L.str.3, 31
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "done.\nPopluating input matrix on host ... "
.size .L.str.4, 43
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "done.\nConverting 2-dimensional input matrix to 1-dimensional array on host ... "
.size .L.str.5, 80
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "done.\nAllocating arrays on device ... "
.size .L.str.6, 39
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "done.\nCopying arrays from host to device ... "
.size .L.str.7, 46
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "done.\nLaunching kernel ... "
.size .L.str.8, 28
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "done.\nElapsed kernel time: "
.size .L.str.9, 28
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " ms\n"
.size .L.str.10, 5
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Copying results back to host .... "
.size .L.str.11, 35
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "done.\nConverting 1-dimensional output array to 2-dimensional matrix on host ... "
.size .L.str.12, 81
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "done.\nVerifying results on host ... "
.size .L.str.13, 37
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "done.\n***GPU results are incorrect***"
.size .L.str.14, 38
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "done\n"
.size .L.str.15, 6
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "GPU results are valid.\n"
.size .L.str.16, 24
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Elapsed time on host: "
.size .L.str.17, 23
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz " ms"
.size .L.str.18, 4
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "Freeing memory on device ... "
.size .L.str.19, 30
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "done.\nFreeing memory on host ... "
.size .L.str.20, 34
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "done.\nExiting program.\n"
.size .L.str.21, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15matrixTransposePjS_ii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__matrixTransposePjS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15matrixTransposePjS_ii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15matrixTransposePjS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x170], P0 ; /* 0x00005c0005007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R5, c[0x0][0x174], R0 ; /* 0x00005d0005027a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0204 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD R5, R0, c[0x0][0x170], R5 ; /* 0x00005c0000057a24 */
/* 0x000fc800078e0205 */
/*0100*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0204 */
/*0110*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15matrixTransposePjS_ii
.globl _Z15matrixTransposePjS_ii
.p2align 8
.type _Z15matrixTransposePjS_ii,@function
_Z15matrixTransposePjS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
v_cmp_gt_i32_e64 s2, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s5, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v4, v[2:3], off
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matrixTransposePjS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15matrixTransposePjS_ii, .Lfunc_end0-_Z15matrixTransposePjS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matrixTransposePjS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15matrixTransposePjS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d3f26_00000000-6_transposenxm.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15matrixTransposePjS_iiPjS_ii
.type _Z39__device_stub__Z15matrixTransposePjS_iiPjS_ii, @function
_Z39__device_stub__Z15matrixTransposePjS_iiPjS_ii:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrixTransposePjS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z39__device_stub__Z15matrixTransposePjS_iiPjS_ii, .-_Z39__device_stub__Z15matrixTransposePjS_iiPjS_ii
.globl _Z15matrixTransposePjS_ii
.type _Z15matrixTransposePjS_ii, @function
_Z15matrixTransposePjS_ii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15matrixTransposePjS_iiPjS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z15matrixTransposePjS_ii, .-_Z15matrixTransposePjS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/kusht07/Parallel-Cuda-codes/master/transposeMat/src/transposenxm.cu"
.align 8
.LC1:
.string "Error %s at line %d in file %s\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "\033[2J\033[1;1H"
.section .rodata.str1.8
.align 8
.LC3:
.string "Allocating arrays on host ... "
.align 8
.LC4:
.string "done.\nPopluating input matrix on host ... "
.align 8
.LC5:
.string "done.\nConverting 2-dimensional input matrix to 1-dimensional array on host ... "
.align 8
.LC6:
.string "done.\nAllocating arrays on device ... "
.align 8
.LC7:
.string "done.\nCopying arrays from host to device ... "
.section .rodata.str1.1
.LC8:
.string "done.\nLaunching kernel ... "
.LC9:
.string "done.\nElapsed kernel time: "
.LC10:
.string " ms\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "Copying results back to host .... "
.align 8
.LC12:
.string "done.\nConverting 1-dimensional output array to 2-dimensional matrix on host ... "
.align 8
.LC13:
.string "done.\nVerifying results on host ... "
.align 8
.LC14:
.string "done.\n***GPU results are incorrect***"
.section .rodata.str1.1
.LC15:
.string "done\n"
.LC16:
.string "GPU results are valid.\n"
.LC17:
.string "Elapsed time on host: "
.LC20:
.string " ms"
.LC21:
.string "Freeing memory on device ... "
.section .rodata.str1.8
.align 8
.LC22:
.string "done.\nFreeing memory on host ... "
.section .rodata.str1.1
.LC23:
.string "done.\nExiting program.\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
movl %eax, %r14d
testl %eax, %eax
jne .L61
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $400000400, %edi
call _Znam@PLT
movq %rax, 24(%rsp)
movl $400000400, %edi
call _Znam@PLT
movq %rax, 32(%rsp)
movl $8000008, %edi
call _Znam@PLT
movq %rax, %rbx
movq %rax, 16(%rsp)
movq %rax, %r13
leaq 8000008(%rax), %r15
.L13:
movl $400, %edi
call _Znam@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %r15, %rbx
jne .L13
movl $800, %edi
call _Znam@PLT
movq %rax, %rbx
movq %rax, 40(%rsp)
movq %rax, %r12
leaq 800(%rax), %rax
movq %rax, 8(%rsp)
.L14:
movl $4000004, %edi
call _Znam@PLT
movq %rax, (%rbx)
addq $8, %rbx
movq 8(%rsp), %rax
cmpq %rax, %rbx
jne .L14
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 16(%rsp), %rbp
.L15:
movl $0, %ebx
.L16:
call rand@PLT
movq 0(%rbp), %rdx
movl %eax, (%rdx,%rbx)
addq $4, %rbx
cmpq $400, %rbx
jne .L16
addq $8, %rbp
cmpq %r15, %rbp
jne .L15
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 24(%rsp), %rcx
movq 16(%rsp), %rdi
.L18:
movq (%rdi), %rsi
movl $0, %eax
.L19:
movl (%rsi,%rax), %edx
movl %edx, (%rcx,%rax)
addq $4, %rax
cmpq $400, %rax
jne .L19
addq $8, %rdi
addl $100, %r14d
addq $400, %rcx
cmpl $100000100, %r14d
jne .L18
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 64(%rsp), %rdi
movl $400000400, %esi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L62
leaq 72(%rsp), %rdi
movl $400000400, %esi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L63
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $1, %ecx
movl $400000400, %edx
movq 24(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
testl %eax, %eax
jne .L64
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $32, 96(%rsp)
movl $32, 100(%rsp)
movl $1, 104(%rsp)
movl $4, 108(%rsp)
movl $31251, 112(%rsp)
movl $1, 116(%rsp)
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
testl %eax, %eax
jne .L65
leaq 88(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
testl %eax, %eax
jne .L66
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
testl %eax, %eax
jne .L67
movl 104(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movq 108(%rsp), %rdi
movl 116(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L68
.L27:
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
testl %eax, %eax
jne .L69
movq 88(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %edi
testl %eax, %eax
jne .L70
leaq 60(%rsp), %rdi
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %edi
testl %eax, %eax
jne .L71
call cudaThreadSynchronize@PLT
movl %eax, %edi
testl %eax, %eax
jne .L72
call cudaGetLastError@PLT
movl %eax, %edi
testl %eax, %eax
jne .L73
movq 80(%rsp), %rdi
call cudaEventDestroy@PLT
movl %eax, %edi
testl %eax, %eax
jne .L74
movq 88(%rsp), %rdi
call cudaEventDestroy@PLT
movl %eax, %edi
testl %eax, %eax
jne .L75
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC10(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC11(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $2, %ecx
movl $400000400, %edx
movq 72(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L76
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 32(%rsp), %rcx
movq 40(%rsp), %rdi
jmp .L36
.L61:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $50, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L62:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $92, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L63:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $94, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L64:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $98, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L65:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $114, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L66:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $115, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L67:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $118, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L68:
movl $100, %ecx
movl $1000001, %edx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z39__device_stub__Z15matrixTransposePjS_iiPjS_ii
jmp .L27
.L69:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $128, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L70:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $130, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L71:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $131, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L72:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $132, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L73:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $133, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L74:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $134, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L75:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $135, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L76:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $139, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L77:
addq $8, %rdi
addl $1000001, %ebx
addq $4000004, %rcx
cmpl $100000100, %ebx
je .L38
.L36:
movq (%rdi), %rsi
movl $0, %eax
.L37:
movl (%rcx,%rax), %edx
movl %edx, (%rsi,%rax)
addq $4, %rax
cmpq $4000004, %rax
jne .L37
jmp .L77
.L38:
leaq .LC13(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call clock@PLT
movq %rax, %rbp
movl $0, %eax
.L39:
movq 40(%rsp), %rdi
movq (%rdi,%rax,2), %rcx
movl $0, %edx
.L42:
movq 16(%rsp), %rdi
movq (%rdi,%rdx,8), %rsi
movl (%rsi,%rax), %edi
cmpl %edi, (%rcx,%rdx,4)
jne .L78
addq $1, %rdx
cmpq $1000001, %rdx
jne .L42
addq $4, %rax
cmpq $400, %rax
jne .L39
leaq .LC15(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC16(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L41
.L78:
leaq .LC14(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC15(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L41:
call clock@PLT
subq %rbp, %rax
movq %rax, %r14
leaq .LC17(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtsi2ssq %r14, %xmm0
divss .LC18(%rip), %xmm0
mulss .LC19(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC20(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC21(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
testl %eax, %eax
jne .L79
movq 72(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
testl %eax, %eax
jne .L80
call cudaDeviceReset@PLT
movl %eax, %edi
testl %eax, %eax
jne .L81
leaq .LC22(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 24(%rsp), %rdi
call _ZdaPv@PLT
movq 32(%rsp), %rdi
call _ZdaPv@PLT
jmp .L48
.L79:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $196, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L80:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $197, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L81:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $198, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L47:
addq $8, %r13
cmpq %r15, %r13
je .L82
.L48:
movq 0(%r13), %rdi
testq %rdi, %rdi
je .L47
call _ZdaPv@PLT
jmp .L47
.L82:
movq 16(%rsp), %rdi
call _ZdaPv@PLT
jmp .L50
.L49:
addq $8, %r12
movq 8(%rsp), %rax
cmpq %rax, %r12
je .L83
.L50:
movq (%r12), %rdi
testq %rdi, %rdi
je .L49
call _ZdaPv@PLT
jmp .L49
.L83:
movq 40(%rsp), %rdi
call _ZdaPv@PLT
leaq .LC23(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L84
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L84:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC24:
.string "_Z15matrixTransposePjS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC24(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixTransposePjS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC18:
.long 1232348160
.align 4
.LC19:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "transposenxm.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__matrixTransposePjS_ii # -- Begin function _Z30__device_stub__matrixTransposePjS_ii
.p2align 4, 0x90
.type _Z30__device_stub__matrixTransposePjS_ii,@function
_Z30__device_stub__matrixTransposePjS_ii: # @_Z30__device_stub__matrixTransposePjS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrixTransposePjS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__matrixTransposePjS_ii, .Lfunc_end0-_Z30__device_stub__matrixTransposePjS_ii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x49742400 # float 1.0E+6
.LCPI1_1:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB1_1
# %bb.3:
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $30, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $400000400, %edi # imm = 0x17D78590
callq _Znam
movq %rax, %rbp
movl $400000400, %edi # imm = 0x17D78590
callq _Znam
movq %rax, %r12
movl $8000008, %edi # imm = 0x7A1208
callq _Znam
movq %rax, %r14
.p2align 4, 0x90
.LBB1_4: # =>This Inner Loop Header: Depth=1
movl $400, %edi # imm = 0x190
callq _Znam
movq %rax, (%r14,%rbx,8)
incq %rbx
cmpq $1000001, %rbx # imm = 0xF4241
jne .LBB1_4
# %bb.5:
movl $800, %edi # imm = 0x320
callq _Znam
movq %rax, %rbx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_6: # =>This Inner Loop Header: Depth=1
movl $4000004, %edi # imm = 0x3D0904
callq _Znam
movq %rax, (%rbx,%r15,8)
incq %r15
cmpq $100, %r15
jne .LBB1_6
# %bb.7:
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $42, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_8: # %.preheader162
# =>This Loop Header: Depth=1
# Child Loop BB1_9 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_9: # Parent Loop BB1_8 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movq (%r14,%r15,8), %rcx
movl %eax, (%rcx,%r13,4)
incq %r13
cmpq $100, %r13
jne .LBB1_9
# %bb.10: # in Loop: Header=BB1_8 Depth=1
incq %r15
cmpq $1000001, %r15 # imm = 0xF4241
jne .LBB1_8
# %bb.11:
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $79, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %eax, %eax
movq %rbp, %rcx
.p2align 4, 0x90
.LBB1_12: # %.preheader161
# =>This Loop Header: Depth=1
# Child Loop BB1_13 Depth 2
movq (%r14,%rax,8), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_13: # Parent Loop BB1_12 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rdx,%rsi,4), %edi
movl %edi, (%rcx,%rsi,4)
incq %rsi
cmpq $100, %rsi
jne .LBB1_13
# %bb.14: # in Loop: Header=BB1_12 Depth=1
incq %rax
addq $400, %rcx # imm = 0x190
cmpq $1000001, %rax # imm = 0xF4241
jne .LBB1_12
# %bb.15:
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $38, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 24(%rsp), %rdi
movl $400000400, %esi # imm = 0x17D78590
callq hipMalloc
testl %eax, %eax
jne .LBB1_16
# %bb.17:
leaq 16(%rsp), %rdi
movl $400000400, %esi # imm = 0x17D78590
callq hipMalloc
testl %eax, %eax
jne .LBB1_18
# %bb.19:
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $45, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 24(%rsp), %rdi
movl $400000400, %edx # imm = 0x17D78590
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_20
# %bb.21:
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 8(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_22
# %bb.23:
movq %rsp, %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_24
# %bb.25:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_26
# %bb.27:
movabsq $134222022967300, %rdi # imm = 0x7A1300000004
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_29
# %bb.28:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl $1000001, 36(%rsp) # imm = 0xF4241
movl $100, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15matrixTransposePjS_ii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_29:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_30
# %bb.31:
movq (%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB1_32
# %bb.33:
movq 8(%rsp), %rsi
movq (%rsp), %rdx
leaq 112(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB1_34
# %bb.35:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_36
# %bb.37:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_38
# %bb.39:
movq 8(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB1_40
# %bb.41:
movq (%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB1_42
# %bb.43:
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 112(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.10, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
movl $34, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 16(%rsp), %rsi
movl $400000400, %edx # imm = 0x17D78590
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_44
# %bb.45:
movl $_ZSt4cout, %edi
movl $.L.str.12, %esi
movl $80, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %eax, %eax
movq %r12, %rcx
.p2align 4, 0x90
.LBB1_46: # %.preheader160
# =>This Loop Header: Depth=1
# Child Loop BB1_47 Depth 2
movq (%rbx,%rax,8), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_47: # Parent Loop BB1_46 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rcx,%rsi,4), %edi
movl %edi, (%rdx,%rsi,4)
incq %rsi
cmpq $1000001, %rsi # imm = 0xF4241
jne .LBB1_47
# %bb.48: # in Loop: Header=BB1_46 Depth=1
incq %rax
addq $4000004, %rcx # imm = 0x3D0904
cmpq $100, %rax
jne .LBB1_46
# %bb.49:
movq %r12, 40(%rsp) # 8-byte Spill
movq %rbp, %r12
movl $_ZSt4cout, %edi
movl $.L.str.13, %esi
movl $36, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movb $1, %bpl
xorl %r15d, %r15d
callq clock
movq %rax, %r13
.p2align 4, 0x90
.LBB1_50: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_52 Depth 2
movq (%rbx,%r15,8), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_52: # Parent Loop BB1_50 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rax,%rcx,4), %edx
movq (%r14,%rcx,8), %rsi
cmpl (%rsi,%r15,4), %edx
jne .LBB1_53
# %bb.51: # in Loop: Header=BB1_52 Depth=2
incq %rcx
cmpq $1000001, %rcx # imm = 0xF4241
jne .LBB1_52
# %bb.54: # %.loopexit
# in Loop: Header=BB1_50 Depth=1
testb $1, %bpl
jne .LBB1_55
jmp .LBB1_56
.p2align 4, 0x90
.LBB1_53: # in Loop: Header=BB1_50 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.14, %esi
movl $37, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %ebp, %ebp
testb $1, %bpl
je .LBB1_56
.LBB1_55: # %.loopexit
# in Loop: Header=BB1_50 Depth=1
incq %r15
cmpq $100, %r15
jne .LBB1_50
.LBB1_56:
movl $_ZSt4cout, %edi
movl $.L.str.15, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testb $1, %bpl
je .LBB1_58
# %bb.57:
movl $_ZSt4cout, %edi
movl $.L.str.16, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB1_58:
callq clock
movq %rax, %rbp
subq %r13, %rbp
movl $_ZSt4cout, %edi
movl $.L.str.17, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cvtsi2ss %rbp, %xmm0
divss .LCPI1_0(%rip), %xmm0
mulss .LCPI1_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.18, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %rbp
testq %rbp, %rbp
je .LBB1_77
# %bb.59: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbp)
je .LBB1_61
# %bb.60:
movzbl 67(%rbp), %eax
jmp .LBB1_62
.LBB1_61:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_62: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r13, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.19, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_63
# %bb.64:
movq %r12, %r15
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
movq 40(%rsp), %r12 # 8-byte Reload
jne .LBB1_65
# %bb.66:
callq hipDeviceReset
testl %eax, %eax
jne .LBB1_67
# %bb.68:
movl $_ZSt4cout, %edi
movl $.L.str.20, %esi
movl $33, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r15, %rdi
callq _ZdaPv
movq %r12, %rdi
callq _ZdaPv
xorl %r15d, %r15d
jmp .LBB1_69
.p2align 4, 0x90
.LBB1_71: # in Loop: Header=BB1_69 Depth=1
incq %r15
cmpq $1000001, %r15 # imm = 0xF4241
je .LBB1_72
.LBB1_69: # =>This Inner Loop Header: Depth=1
movq (%r14,%r15,8), %rdi
testq %rdi, %rdi
je .LBB1_71
# %bb.70: # in Loop: Header=BB1_69 Depth=1
callq _ZdaPv
jmp .LBB1_71
.LBB1_72:
movq %r14, %rdi
callq _ZdaPv
xorl %r14d, %r14d
jmp .LBB1_73
.p2align 4, 0x90
.LBB1_75: # in Loop: Header=BB1_73 Depth=1
incq %r14
cmpq $100, %r14
je .LBB1_76
.LBB1_73: # =>This Inner Loop Header: Depth=1
movq (%rbx,%r14,8), %rdi
testq %rdi, %rdi
je .LBB1_75
# %bb.74: # in Loop: Header=BB1_73 Depth=1
callq _ZdaPv
jmp .LBB1_75
.LBB1_76:
movq %rbx, %rdi
callq _ZdaPv
movl $_ZSt4cout, %edi
movl $.L.str.21, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 208
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $52, %ecx
jmp .LBB1_2
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $95, %ecx
jmp .LBB1_2
.LBB1_18:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $97, %ecx
jmp .LBB1_2
.LBB1_20:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $102, %ecx
jmp .LBB1_2
.LBB1_22:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $116, %ecx
jmp .LBB1_2
.LBB1_24:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $117, %ecx
jmp .LBB1_2
.LBB1_26:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $120, %ecx
jmp .LBB1_2
.LBB1_30:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $130, %ecx
jmp .LBB1_2
.LBB1_32:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $132, %ecx
jmp .LBB1_2
.LBB1_34:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $133, %ecx
jmp .LBB1_2
.LBB1_36:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $134, %ecx
jmp .LBB1_2
.LBB1_38:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $135, %ecx
jmp .LBB1_2
.LBB1_40:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $136, %ecx
jmp .LBB1_2
.LBB1_42:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $137, %ecx
jmp .LBB1_2
.LBB1_44:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $143, %ecx
jmp .LBB1_2
.LBB1_77:
callq _ZSt16__throw_bad_castv
.LBB1_63:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $198, %ecx
jmp .LBB1_2
.LBB1_65:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $199, %ecx
jmp .LBB1_2
.LBB1_67:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $200, %ecx
.LBB1_2:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixTransposePjS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15matrixTransposePjS_ii,@object # @_Z15matrixTransposePjS_ii
.section .rodata,"a",@progbits
.globl _Z15matrixTransposePjS_ii
.p2align 3, 0x0
_Z15matrixTransposePjS_ii:
.quad _Z30__device_stub__matrixTransposePjS_ii
.size _Z15matrixTransposePjS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error %s at line %d in file %s\n"
.size .L.str, 32
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/kusht07/Parallel-Cuda-codes/master/transposeMat/src/transposenxm.hip"
.size .L.str.1, 126
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\033[2J\033[1
.size .L.str.2, 11
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Allocating arrays on host ... "
.size .L.str.3, 31
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "done.\nPopluating input matrix on host ... "
.size .L.str.4, 43
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "done.\nConverting 2-dimensional input matrix to 1-dimensional array on host ... "
.size .L.str.5, 80
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "done.\nAllocating arrays on device ... "
.size .L.str.6, 39
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "done.\nCopying arrays from host to device ... "
.size .L.str.7, 46
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "done.\nLaunching kernel ... "
.size .L.str.8, 28
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "done.\nElapsed kernel time: "
.size .L.str.9, 28
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " ms\n"
.size .L.str.10, 5
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Copying results back to host .... "
.size .L.str.11, 35
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "done.\nConverting 1-dimensional output array to 2-dimensional matrix on host ... "
.size .L.str.12, 81
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "done.\nVerifying results on host ... "
.size .L.str.13, 37
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "done.\n***GPU results are incorrect***"
.size .L.str.14, 38
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "done\n"
.size .L.str.15, 6
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "GPU results are valid.\n"
.size .L.str.16, 24
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Elapsed time on host: "
.size .L.str.17, 23
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz " ms"
.size .L.str.18, 4
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "Freeing memory on device ... "
.size .L.str.19, 30
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "done.\nFreeing memory on host ... "
.size .L.str.20, 34
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "done.\nExiting program.\n"
.size .L.str.21, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15matrixTransposePjS_ii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__matrixTransposePjS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15matrixTransposePjS_ii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #ifdef _WIN32
#include <time.h>
#else
#include <sys/time.h>
#endif
double wall_time(void)
{
#ifdef _WIN32
return (double)((double)clock() / (double)CLOCKS_PER_SEC);
#else
struct timeval tv;
struct timezone tz;
gettimeofday(&tv, &tz);
return(tv.tv_sec + tv.tv_usec/1000000.0);
#endif
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #ifdef _WIN32
#include <time.h>
#else
#include <sys/time.h>
#endif
double wall_time(void)
{
#ifdef _WIN32
return (double)((double)clock() / (double)CLOCKS_PER_SEC);
#else
struct timeval tv;
struct timezone tz;
gettimeofday(&tv, &tz);
return(tv.tv_sec + tv.tv_usec/1000000.0);
#endif
} | .file "tmpxft_000570a3_00000000-6_wall_time.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9wall_timev
.type _Z9wall_timev, @function
_Z9wall_timev:
.LFB2027:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size _Z9wall_timev, .-_Z9wall_timev
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #ifdef _WIN32
#include <time.h>
#else
#include <sys/time.h>
#endif
double wall_time(void)
{
#ifdef _WIN32
return (double)((double)clock() / (double)CLOCKS_PER_SEC);
#else
struct timeval tv;
struct timezone tz;
gettimeofday(&tv, &tz);
return(tv.tv_sec + tv.tv_usec/1000000.0);
#endif
} | #ifdef _WIN32
#include <hip/hip_runtime.h>
#include <time.h>
#else
#include <sys/time.h>
#endif
double wall_time(void)
{
#ifdef _WIN32
return (double)((double)clock() / (double)CLOCKS_PER_SEC);
#else
struct timeval tv;
struct timezone tz;
gettimeofday(&tv, &tz);
return(tv.tv_sec + tv.tv_usec/1000000.0);
#endif
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifdef _WIN32
#include <hip/hip_runtime.h>
#include <time.h>
#else
#include <sys/time.h>
#endif
double wall_time(void)
{
#ifdef _WIN32
return (double)((double)clock() / (double)CLOCKS_PER_SEC);
#else
struct timeval tv;
struct timezone tz;
gettimeofday(&tv, &tz);
return(tv.tv_sec + tv.tv_usec/1000000.0);
#endif
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifdef _WIN32
#include <hip/hip_runtime.h>
#include <time.h>
#else
#include <sys/time.h>
#endif
double wall_time(void)
{
#ifdef _WIN32
return (double)((double)clock() / (double)CLOCKS_PER_SEC);
#else
struct timeval tv;
struct timezone tz;
gettimeofday(&tv, &tz);
return(tv.tv_sec + tv.tv_usec/1000000.0);
#endif
} | .text
.file "wall_time.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9wall_timev
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z9wall_timev
.p2align 4, 0x90
.type _Z9wall_timev,@function
_Z9wall_timev: # @_Z9wall_timev
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsp, %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
cvtsi2sdq (%rsp), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
divsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z9wall_timev, .Lfunc_end0-_Z9wall_timev
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000570a3_00000000-6_wall_time.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9wall_timev
.type _Z9wall_timev, @function
_Z9wall_timev:
.LFB2027:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size _Z9wall_timev, .-_Z9wall_timev
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "wall_time.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9wall_timev
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z9wall_timev
.p2align 4, 0x90
.type _Z9wall_timev,@function
_Z9wall_timev: # @_Z9wall_timev
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsp, %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
cvtsi2sdq (%rsp), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
divsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z9wall_timev, .Lfunc_end0-_Z9wall_timev
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C" {
__global__ void writeTest(int* array){
for(int i = 0; i < 8; i++){
array[i] *= 2;
}
}
} | code for sm_80
Function : writeTest
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0050*/ LDG.E R4, [R2.64+0x4] ; /* 0x0000040402047981 */
/* 0x000ee8000c1e1900 */
/*0060*/ LDG.E R6, [R2.64+0x8] ; /* 0x0000080402067981 */
/* 0x000f28000c1e1900 */
/*0070*/ LDG.E R8, [R2.64+0xc] ; /* 0x00000c0402087981 */
/* 0x000f68000c1e1900 */
/*0080*/ LDG.E R10, [R2.64+0x10] ; /* 0x00001004020a7981 */
/* 0x000f68000c1e1900 */
/*0090*/ LDG.E R12, [R2.64+0x14] ; /* 0x00001404020c7981 */
/* 0x000f68000c1e1900 */
/*00a0*/ LDG.E R14, [R2.64+0x18] ; /* 0x00001804020e7981 */
/* 0x000f68000c1e1900 */
/*00b0*/ LDG.E R16, [R2.64+0x1c] ; /* 0x00001c0402107981 */
/* 0x000f62000c1e1900 */
/*00c0*/ SHF.L.U32 R5, R0, 0x1, RZ ; /* 0x0000000100057819 */
/* 0x004fe200000006ff */
/*00d0*/ IMAD.SHL.U32 R7, R4, 0x2, RZ ; /* 0x0000000204077824 */
/* 0x008fc800078e00ff */
/*00e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00f0*/ SHF.L.U32 R9, R6, 0x1, RZ ; /* 0x0000000106097819 */
/* 0x010fc600000006ff */
/*0100*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x000fe2000c101904 */
/*0110*/ IMAD.SHL.U32 R11, R8, 0x2, RZ ; /* 0x00000002080b7824 */
/* 0x020fc600078e00ff */
/*0120*/ STG.E [R2.64+0x8], R9 ; /* 0x0000080902007986 */
/* 0x000fe2000c101904 */
/*0130*/ SHF.L.U32 R13, R10, 0x1, RZ ; /* 0x000000010a0d7819 */
/* 0x000fc600000006ff */
/*0140*/ STG.E [R2.64+0xc], R11 ; /* 0x00000c0b02007986 */
/* 0x000fe2000c101904 */
/*0150*/ IMAD.SHL.U32 R15, R12, 0x2, RZ ; /* 0x000000020c0f7824 */
/* 0x000fc600078e00ff */
/*0160*/ STG.E [R2.64+0x10], R13 ; /* 0x0000100d02007986 */
/* 0x000fe2000c101904 */
/*0170*/ SHF.L.U32 R17, R14, 0x1, RZ ; /* 0x000000010e117819 */
/* 0x000fc600000006ff */
/*0180*/ STG.E [R2.64+0x14], R15 ; /* 0x0000140f02007986 */
/* 0x000fe2000c101904 */
/*0190*/ IMAD.SHL.U32 R19, R16, 0x2, RZ ; /* 0x0000000210137824 */
/* 0x000fc600078e00ff */
/*01a0*/ STG.E [R2.64+0x18], R17 ; /* 0x0000181102007986 */
/* 0x000fe8000c101904 */
/*01b0*/ STG.E [R2.64+0x1c], R19 ; /* 0x00001c1302007986 */
/* 0x000fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C" {
__global__ void writeTest(int* array){
for(int i = 0; i < 8; i++){
array[i] *= 2;
}
}
} | .file "tmpxft_000df5a7_00000000-6_writeTest_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z9writeTestPiPi
.type _Z28__device_stub__Z9writeTestPiPi, @function
_Z28__device_stub__Z9writeTestPiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq writeTest(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z9writeTestPiPi, .-_Z28__device_stub__Z9writeTestPiPi
.globl writeTest
.type writeTest, @function
writeTest:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z9writeTestPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size writeTest, .-writeTest
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "writeTest"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq writeTest(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C" {
__global__ void writeTest(int* array){
for(int i = 0; i < 8; i++){
array[i] *= 2;
}
}
} | #include <hip/hip_runtime.h>
extern "C" {
__global__ void writeTest(int* array){
for(int i = 0; i < 8; i++){
array[i] *= 2;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C" {
__global__ void writeTest(int* array){
for(int i = 0; i < 8; i++){
array[i] *= 2;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected writeTest
.globl writeTest
.p2align 8
.type writeTest,@function
writeTest:
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_mov_b64 s[2:3], 0
.LBB0_1:
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s0, s2
s_addc_u32 s5, s1, s3
s_add_u32 s2, s2, 4
global_load_b32 v1, v0, s[4:5]
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 32
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v1, 1, v1
global_store_b32 v0, v1, s[4:5]
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel writeTest
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 6
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size writeTest, .Lfunc_end0-writeTest
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: writeTest
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: writeTest.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C" {
__global__ void writeTest(int* array){
for(int i = 0; i < 8; i++){
array[i] *= 2;
}
}
} | .text
.file "writeTest_kernel.hip"
.globl __device_stub__writeTest # -- Begin function __device_stub__writeTest
.p2align 4, 0x90
.type __device_stub__writeTest,@function
__device_stub__writeTest: # @__device_stub__writeTest
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $writeTest, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size __device_stub__writeTest, .Lfunc_end0-__device_stub__writeTest
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $writeTest, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type writeTest,@object # @writeTest
.section .rodata,"a",@progbits
.globl writeTest
.p2align 3, 0x0
writeTest:
.quad __device_stub__writeTest
.size writeTest, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "writeTest"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__writeTest
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym writeTest
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : writeTest
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0050*/ LDG.E R4, [R2.64+0x4] ; /* 0x0000040402047981 */
/* 0x000ee8000c1e1900 */
/*0060*/ LDG.E R6, [R2.64+0x8] ; /* 0x0000080402067981 */
/* 0x000f28000c1e1900 */
/*0070*/ LDG.E R8, [R2.64+0xc] ; /* 0x00000c0402087981 */
/* 0x000f68000c1e1900 */
/*0080*/ LDG.E R10, [R2.64+0x10] ; /* 0x00001004020a7981 */
/* 0x000f68000c1e1900 */
/*0090*/ LDG.E R12, [R2.64+0x14] ; /* 0x00001404020c7981 */
/* 0x000f68000c1e1900 */
/*00a0*/ LDG.E R14, [R2.64+0x18] ; /* 0x00001804020e7981 */
/* 0x000f68000c1e1900 */
/*00b0*/ LDG.E R16, [R2.64+0x1c] ; /* 0x00001c0402107981 */
/* 0x000f62000c1e1900 */
/*00c0*/ SHF.L.U32 R5, R0, 0x1, RZ ; /* 0x0000000100057819 */
/* 0x004fe200000006ff */
/*00d0*/ IMAD.SHL.U32 R7, R4, 0x2, RZ ; /* 0x0000000204077824 */
/* 0x008fc800078e00ff */
/*00e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00f0*/ SHF.L.U32 R9, R6, 0x1, RZ ; /* 0x0000000106097819 */
/* 0x010fc600000006ff */
/*0100*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x000fe2000c101904 */
/*0110*/ IMAD.SHL.U32 R11, R8, 0x2, RZ ; /* 0x00000002080b7824 */
/* 0x020fc600078e00ff */
/*0120*/ STG.E [R2.64+0x8], R9 ; /* 0x0000080902007986 */
/* 0x000fe2000c101904 */
/*0130*/ SHF.L.U32 R13, R10, 0x1, RZ ; /* 0x000000010a0d7819 */
/* 0x000fc600000006ff */
/*0140*/ STG.E [R2.64+0xc], R11 ; /* 0x00000c0b02007986 */
/* 0x000fe2000c101904 */
/*0150*/ IMAD.SHL.U32 R15, R12, 0x2, RZ ; /* 0x000000020c0f7824 */
/* 0x000fc600078e00ff */
/*0160*/ STG.E [R2.64+0x10], R13 ; /* 0x0000100d02007986 */
/* 0x000fe2000c101904 */
/*0170*/ SHF.L.U32 R17, R14, 0x1, RZ ; /* 0x000000010e117819 */
/* 0x000fc600000006ff */
/*0180*/ STG.E [R2.64+0x14], R15 ; /* 0x0000140f02007986 */
/* 0x000fe2000c101904 */
/*0190*/ IMAD.SHL.U32 R19, R16, 0x2, RZ ; /* 0x0000000210137824 */
/* 0x000fc600078e00ff */
/*01a0*/ STG.E [R2.64+0x18], R17 ; /* 0x0000181102007986 */
/* 0x000fe8000c101904 */
/*01b0*/ STG.E [R2.64+0x1c], R19 ; /* 0x00001c1302007986 */
/* 0x000fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected writeTest
.globl writeTest
.p2align 8
.type writeTest,@function
writeTest:
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_mov_b64 s[2:3], 0
.LBB0_1:
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s0, s2
s_addc_u32 s5, s1, s3
s_add_u32 s2, s2, 4
global_load_b32 v1, v0, s[4:5]
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 32
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v1, 1, v1
global_store_b32 v0, v1, s[4:5]
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel writeTest
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 6
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size writeTest, .Lfunc_end0-writeTest
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: writeTest
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: writeTest.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000df5a7_00000000-6_writeTest_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z9writeTestPiPi
.type _Z28__device_stub__Z9writeTestPiPi, @function
_Z28__device_stub__Z9writeTestPiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq writeTest(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z9writeTestPiPi, .-_Z28__device_stub__Z9writeTestPiPi
.globl writeTest
.type writeTest, @function
writeTest:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z9writeTestPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size writeTest, .-writeTest
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "writeTest"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq writeTest(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "writeTest_kernel.hip"
.globl __device_stub__writeTest # -- Begin function __device_stub__writeTest
.p2align 4, 0x90
.type __device_stub__writeTest,@function
__device_stub__writeTest: # @__device_stub__writeTest
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $writeTest, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size __device_stub__writeTest, .Lfunc_end0-__device_stub__writeTest
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $writeTest, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type writeTest,@object # @writeTest
.section .rodata,"a",@progbits
.globl writeTest
.p2align 3, 0x0
writeTest:
.quad __device_stub__writeTest
.size writeTest, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "writeTest"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__writeTest
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym writeTest
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void histo_kernel( unsigned char *buffer, long size, unsigned int *histo ) {
// calculate the starting index and the offset to the next
// block that each thread will be processing
int i = threadIdx.x + blockIdx.x * blockDim.x;
int stride = blockDim.x * gridDim.x;
while (i < size) {
atomicAdd( &histo[buffer[i]], 1 );
i += stride;
}
} | code for sm_80
Function : _Z12histo_kernelPhlPj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.AND.EX P0, PT, R2, c[0x0][0x16c], PT, P0 ; /* 0x00005b0002007a0c */
/* 0x000fda0003f06300 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fca00078e0000 */
/*00b0*/ IADD3 R4, P0, R6, c[0x0][0x160], RZ ; /* 0x0000580006047a10 */
/* 0x000fc80007f1e0ff */
/*00c0*/ IADD3.X R5, R7, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590007057a10 */
/* 0x000fca00007fe4ff */
/*00d0*/ LDG.E.U8 R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x001ea2000c1e1100 */
/*00e0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x000fe200078e00ff */
/*00f0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0100*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe200078e00ff */
/*0110*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0120*/ IMAD R6, R7, c[0x0][0xc], R0 ; /* 0x0000030007067a24 */
/* 0x000fca00078e0200 */
/*0130*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fe40003f06070 */
/*0140*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fc80000011406 */
/*0150*/ ISETP.GE.AND.EX P0, PT, R7, c[0x0][0x16c], PT, P0 ; /* 0x00005b0007007a0c */
/* 0x000fe40003f06300 */
/*0160*/ MOV R0, R6 ; /* 0x0000000600007202 */
/* 0x000fe20000000f00 */
/*0170*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x004fca00078e0003 */
/*0180*/ RED.E.ADD.STRONG.GPU [R2.64], R9 ; /* 0x000000090200798e */
/* 0x0001ea000c10e184 */
/*0190*/ @!P0 BRA 0xb0 ; /* 0xffffff1000008947 */
/* 0x000fea000383ffff */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void histo_kernel( unsigned char *buffer, long size, unsigned int *histo ) {
// calculate the starting index and the offset to the next
// block that each thread will be processing
int i = threadIdx.x + blockIdx.x * blockDim.x;
int stride = blockDim.x * gridDim.x;
while (i < size) {
atomicAdd( &histo[buffer[i]], 1 );
i += stride;
}
} | .file "tmpxft_001458d6_00000000-6_histo_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z12histo_kernelPhlPjPhlPj
.type _Z35__device_stub__Z12histo_kernelPhlPjPhlPj, @function
_Z35__device_stub__Z12histo_kernelPhlPjPhlPj:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12histo_kernelPhlPj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z12histo_kernelPhlPjPhlPj, .-_Z35__device_stub__Z12histo_kernelPhlPjPhlPj
.globl _Z12histo_kernelPhlPj
.type _Z12histo_kernelPhlPj, @function
_Z12histo_kernelPhlPj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12histo_kernelPhlPjPhlPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12histo_kernelPhlPj, .-_Z12histo_kernelPhlPj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12histo_kernelPhlPj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12histo_kernelPhlPj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void histo_kernel( unsigned char *buffer, long size, unsigned int *histo ) {
// calculate the starting index and the offset to the next
// block that each thread will be processing
int i = threadIdx.x + blockIdx.x * blockDim.x;
int stride = blockDim.x * gridDim.x;
while (i < size) {
atomicAdd( &histo[buffer[i]], 1 );
i += stride;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void histo_kernel( unsigned char *buffer, long size, unsigned int *histo ) {
// calculate the starting index and the offset to the next
// block that each thread will be processing
int i = threadIdx.x + blockIdx.x * blockDim.x;
int stride = blockDim.x * gridDim.x;
while (i < size) {
atomicAdd( &histo[buffer[i]], 1 );
i += stride;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void histo_kernel( unsigned char *buffer, long size, unsigned int *histo ) {
// calculate the starting index and the offset to the next
// block that each thread will be processing
int i = threadIdx.x + blockIdx.x * blockDim.x;
int stride = blockDim.x * gridDim.x;
while (i < size) {
atomicAdd( &histo[buffer[i]], 1 );
i += stride;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12histo_kernelPhlPj
.globl _Z12histo_kernelPhlPj
.p2align 8
.type _Z12histo_kernelPhlPj,@function
_Z12histo_kernelPhlPj:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s7, s[4:5], 0x0
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s8, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s15, s15, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s15, s6, v[0:1]
s_mul_i32 s6, s7, s6
s_ashr_i32 s7, s6, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v0, 31, v3
v_sub_co_u32 v3, vcc_lo, v3, s6
v_subrev_co_ci_u32_e32 v4, vcc_lo, s7, v0, vcc_lo
v_mov_b32_e32 v0, 1
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, s6
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_u8 v1, v[1:2], off
v_ashrrev_i32_e32 v2, 31, v3
v_cmp_le_i64_e32 vcc_lo, s[2:3], v[3:4]
s_or_b32 s8, vcc_lo, s8
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v1, 2, v1
global_atomic_add_u32 v1, v0, s[0:1]
v_mov_b32_e32 v1, v3
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12histo_kernelPhlPj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12histo_kernelPhlPj, .Lfunc_end0-_Z12histo_kernelPhlPj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12histo_kernelPhlPj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12histo_kernelPhlPj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void histo_kernel( unsigned char *buffer, long size, unsigned int *histo ) {
// calculate the starting index and the offset to the next
// block that each thread will be processing
int i = threadIdx.x + blockIdx.x * blockDim.x;
int stride = blockDim.x * gridDim.x;
while (i < size) {
atomicAdd( &histo[buffer[i]], 1 );
i += stride;
}
} | .text
.file "histo_kernel.hip"
.globl _Z27__device_stub__histo_kernelPhlPj # -- Begin function _Z27__device_stub__histo_kernelPhlPj
.p2align 4, 0x90
.type _Z27__device_stub__histo_kernelPhlPj,@function
_Z27__device_stub__histo_kernelPhlPj: # @_Z27__device_stub__histo_kernelPhlPj
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12histo_kernelPhlPj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__histo_kernelPhlPj, .Lfunc_end0-_Z27__device_stub__histo_kernelPhlPj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12histo_kernelPhlPj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12histo_kernelPhlPj,@object # @_Z12histo_kernelPhlPj
.section .rodata,"a",@progbits
.globl _Z12histo_kernelPhlPj
.p2align 3, 0x0
_Z12histo_kernelPhlPj:
.quad _Z27__device_stub__histo_kernelPhlPj
.size _Z12histo_kernelPhlPj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12histo_kernelPhlPj"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__histo_kernelPhlPj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12histo_kernelPhlPj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12histo_kernelPhlPj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.AND.EX P0, PT, R2, c[0x0][0x16c], PT, P0 ; /* 0x00005b0002007a0c */
/* 0x000fda0003f06300 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fca00078e0000 */
/*00b0*/ IADD3 R4, P0, R6, c[0x0][0x160], RZ ; /* 0x0000580006047a10 */
/* 0x000fc80007f1e0ff */
/*00c0*/ IADD3.X R5, R7, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590007057a10 */
/* 0x000fca00007fe4ff */
/*00d0*/ LDG.E.U8 R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x001ea2000c1e1100 */
/*00e0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x000fe200078e00ff */
/*00f0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0100*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe200078e00ff */
/*0110*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0120*/ IMAD R6, R7, c[0x0][0xc], R0 ; /* 0x0000030007067a24 */
/* 0x000fca00078e0200 */
/*0130*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fe40003f06070 */
/*0140*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fc80000011406 */
/*0150*/ ISETP.GE.AND.EX P0, PT, R7, c[0x0][0x16c], PT, P0 ; /* 0x00005b0007007a0c */
/* 0x000fe40003f06300 */
/*0160*/ MOV R0, R6 ; /* 0x0000000600007202 */
/* 0x000fe20000000f00 */
/*0170*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x004fca00078e0003 */
/*0180*/ RED.E.ADD.STRONG.GPU [R2.64], R9 ; /* 0x000000090200798e */
/* 0x0001ea000c10e184 */
/*0190*/ @!P0 BRA 0xb0 ; /* 0xffffff1000008947 */
/* 0x000fea000383ffff */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12histo_kernelPhlPj
.globl _Z12histo_kernelPhlPj
.p2align 8
.type _Z12histo_kernelPhlPj,@function
_Z12histo_kernelPhlPj:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s7, s[4:5], 0x0
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s8, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s15, s15, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s15, s6, v[0:1]
s_mul_i32 s6, s7, s6
s_ashr_i32 s7, s6, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v0, 31, v3
v_sub_co_u32 v3, vcc_lo, v3, s6
v_subrev_co_ci_u32_e32 v4, vcc_lo, s7, v0, vcc_lo
v_mov_b32_e32 v0, 1
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, s6
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_u8 v1, v[1:2], off
v_ashrrev_i32_e32 v2, 31, v3
v_cmp_le_i64_e32 vcc_lo, s[2:3], v[3:4]
s_or_b32 s8, vcc_lo, s8
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v1, 2, v1
global_atomic_add_u32 v1, v0, s[0:1]
v_mov_b32_e32 v1, v3
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12histo_kernelPhlPj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12histo_kernelPhlPj, .Lfunc_end0-_Z12histo_kernelPhlPj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12histo_kernelPhlPj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12histo_kernelPhlPj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001458d6_00000000-6_histo_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z12histo_kernelPhlPjPhlPj
.type _Z35__device_stub__Z12histo_kernelPhlPjPhlPj, @function
_Z35__device_stub__Z12histo_kernelPhlPjPhlPj:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12histo_kernelPhlPj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z12histo_kernelPhlPjPhlPj, .-_Z35__device_stub__Z12histo_kernelPhlPjPhlPj
.globl _Z12histo_kernelPhlPj
.type _Z12histo_kernelPhlPj, @function
_Z12histo_kernelPhlPj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12histo_kernelPhlPjPhlPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12histo_kernelPhlPj, .-_Z12histo_kernelPhlPj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12histo_kernelPhlPj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12histo_kernelPhlPj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "histo_kernel.hip"
.globl _Z27__device_stub__histo_kernelPhlPj # -- Begin function _Z27__device_stub__histo_kernelPhlPj
.p2align 4, 0x90
.type _Z27__device_stub__histo_kernelPhlPj,@function
_Z27__device_stub__histo_kernelPhlPj: # @_Z27__device_stub__histo_kernelPhlPj
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12histo_kernelPhlPj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__histo_kernelPhlPj, .Lfunc_end0-_Z27__device_stub__histo_kernelPhlPj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12histo_kernelPhlPj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12histo_kernelPhlPj,@object # @_Z12histo_kernelPhlPj
.section .rodata,"a",@progbits
.globl _Z12histo_kernelPhlPj
.p2align 3, 0x0
_Z12histo_kernelPhlPj:
.quad _Z27__device_stub__histo_kernelPhlPj
.size _Z12histo_kernelPhlPj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12histo_kernelPhlPj"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__histo_kernelPhlPj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12histo_kernelPhlPj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cstdio>
#include <cstdlib>
#include <cstring>
#include <ctime>
int hgetLPierre(int d, int i, int j) {
// If j > i, then we take the transpose of L
if (j > i) {
int t = i;
i = j;
j = t;
}
int l_position = i*(i+1) / 2 + j;
// int l_position = i*(i-1) / 2 + j-1;
return l_position;
}
int hgetDPierre(int i) {
int d_position = i;
return d_position;
}
void generate_systems(float *A, float *Y, int N, int d, bool verbose=true) {
int matrix_size = d + d * (d + 1) / 2;
for (int i = 0; i < N; i++) {
float *D = &A[i * matrix_size];
float *T = &A[i * matrix_size + d];
for (int j=0; j < (d * (d + 1) / 2); j++)
T[j] = ((float) rand()+1)*1./RAND_MAX;
for (int j=0; j<d; j++)
T[hgetLPierre(d, j,j)] = 1.0f;
for (int j=0; j<d; j++) {
D[j] = ((float) rand()+1)*1./RAND_MAX;
Y[d * i + j] = ((float) rand()+1)*1./RAND_MAX;
}
}
}
// ************************************************************************ //
// __device__ int getLPierre(float* T, int n, int d, int matrix_id, int i, int j)
__device__ int getLPierre(int d, int i, int j)
{
// If j > i, then we take the transpose of L
if (j > i) {int t = i; i = j; j = t;};
// int matrix_memory_size = (d+d*(d+1)/2);
int l_position = d + i*(i+1) / 2 + j;
// int l_position = i*(i-1) / 2 + j-1;
// int l_position = d + i*(i-1) / 2 + j;
return l_position;
// return &T[matrix_id * matrix_memory_size + l_position]
}
// __device__ int getDPierre(float* T, int n, int d, int matrix_id, int i)
__device__ int getDPierre(int d, int i)
{
// int matrix_memory_size = (d+d*(d+1)/2);
int d_position = i;
return d_position;
// return &T[matrix_id * matrix_memory_size + d_position]
}
__device__ void parallel_copy(float* src, float* dest, int n)
{
int i = threadIdx.x;
int stride = blockDim.x;
while(i<n){
dest[i] = src[i];
i += stride;
}
__syncthreads();
}
// __global__ void LDLt_max_col_k(float* AGPU, int d)
__global__ void LDLt_max_col_k(float* sA, int d)
{
int tidx = threadIdx.x%d;
int Qt = (threadIdx.x-tidx)/d;
int A_size = d*(d+1)/2+d;
int minTB = blockDim.x/d;
// printf("minTB %d\n", minTB);
int nt = (blockIdx.x*minTB + Qt) * A_size;
// int gbx = Qt + blockIdx.x*(blockDim.x/d);
// extern __shared__ float sA[];
// //copy ACPU to sA
// parallel_copy(sA, &AGPU[(blockIdx.x*minTB + Qt)*A_size], minTB*A_size);
// tidx==i
// Perform the LDLt factorization
int j, k;
for(j=0; j<d; j++){
// D_j,j :
if(tidx==0){
for(k=0; k<j; k++){
sA[nt+getDPierre(d, j)] -= sA[nt+getDPierre(d,k)]*
sA[nt+getLPierre(d,j,k)]*
sA[nt+getLPierre(d,j,k)];
}
}
__syncthreads();
// L_:,j parallel
if(tidx>j){
//printf("(%d,%d,%d,%d),", nt+getLPierre(d,tidx,j), nt, tidx, j);
sA[nt+getLPierre(d,tidx,j)] /= sA[nt+getDPierre(d,j)];
for(k=0; k<j; k++){
sA[nt+getLPierre(d,tidx,j)] -= sA[nt+getLPierre(d,tidx,k)]*
sA[nt+getLPierre(d,j,k)]*
sA[nt+getDPierre(d,k)]/
sA[nt+getDPierre(d,j)];
}
}
__syncthreads();
}
// parallel_copy(&AGPU[(blockIdx.x*minTB + Qt)*A_size], sA, minTB*A_size);
}
// __global__ void LDLt_max_row_k(float* AGPU, int d)
__global__ void LDLt_max_row_k(float* sA, int d)
{
int tidx = threadIdx.x%d;
int Qt = (threadIdx.x-tidx)/d;
int A_size = d*(d+1)/2+d;
int minTB = blockDim.x/d;
// printf("minTB %d\n", minTB);
int nt = (blockIdx.x*minTB + Qt) * A_size;
// int gbx = Qt + blockIdx.x*(blockDim.x/d);
// extern __shared__ float sA[];
// //copy ACPU to sA
// parallel_copy(sA, &AGPU[(blockIdx.x*minTB + Qt)*A_size], minTB*A_size);
// Perform the LDLt factorization
int i, k;
for(i=0; i<d; i++){
// D_i,i :
if(tidx==0){
for(k=0; k<i; k++){
sA[nt+getDPierre(d, i)] -= sA[nt+getDPierre(d,k)]*
sA[nt+getLPierre(d,i,k)]*
sA[nt+getLPierre(d,i,k)];
}
}
__syncthreads();
// L_i,: parallel
if(i<tidx){
//printf("(%d,%d,%d,%d),", nt+getLPierre(d,i,tidx), nt, i,tidx);
sA[nt+getLPierre(d,i,tidx)] /= sA[nt+getDPierre(d,i)];
for(k=0; k<i; k++){
sA[nt+getLPierre(d,i,tidx)] -= sA[nt+getLPierre(d,k,tidx)]*
sA[nt+getLPierre(d,k,i)]*
sA[nt+getDPierre(d,k)]/
sA[nt+getDPierre(d,i)];
}
}
__syncthreads();
}
// parallel_copy(&sA[(blockIdx.x*minTB + Qt)*A_size], A_host, minTB*A_size);
}
// __global__ void LDLt_max_row_k(float* AGPU, int d)
__global__ void LDLt_max_row_k_SHARED(float* A_host, int d)
{
int tidx = threadIdx.x%d;
int Qt = (threadIdx.x-tidx)/d;
int A_size = d*(d+1)/2+d;
int minTB = blockDim.x/d;
// printf("minTB %d\n", minTB);
int nt = Qt * A_size;
// int gbx = Qt + blockIdx.x*(blockDim.x/d);
extern __shared__ float sA[];
//copy ACPU to sA
parallel_copy(&A_host[blockIdx.x*minTB*A_size], sA, minTB*A_size);
// tidx==j
// Perform the LDLt factorization
int i, k;
for(i=0; i<d; i++){
// D_i,i :
if(tidx==0){
for(k=0; k<i; k++){
sA[nt+getDPierre(d, i)] -= sA[nt+getDPierre(d,k)]*
sA[nt+getLPierre(d,i,k)]*
sA[nt+getLPierre(d,i,k)];
}
}
__syncthreads();
// L_i,: parallel
if(i<tidx){
//printf("(%d,%d,%d,%d),", nt+getLPierre(d,i,tidx), nt, i,tidx);
sA[nt+getLPierre(d,i,tidx)] /= sA[nt+getDPierre(d,i)];
for(k=0; k<i; k++){
sA[nt+getLPierre(d,i,tidx)] -= sA[nt+getLPierre(d,k,tidx)]*
sA[nt+getLPierre(d,k,i)]*
sA[nt+getDPierre(d,k)]/
sA[nt+getDPierre(d,i)];
}
}
__syncthreads();
}
parallel_copy(sA, &A_host[blockIdx.x*minTB*A_size], minTB*A_size);
}
// ************************************************************************ // | .file "tmpxft_000476e6_00000000-6_LDLt.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3677:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3677:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11hgetLPierreiii
.type _Z11hgetLPierreiii, @function
_Z11hgetLPierreiii:
.LFB3669:
.cfi_startproc
endbr64
cmpl %esi, %edx
jg .L4
movl %edx, %eax
movl %esi, %edx
movl %eax, %esi
.L4:
leal 1(%rdx), %eax
imull %eax, %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
addl %esi, %eax
ret
.cfi_endproc
.LFE3669:
.size _Z11hgetLPierreiii, .-_Z11hgetLPierreiii
.globl _Z11hgetDPierrei
.type _Z11hgetDPierrei, @function
_Z11hgetDPierrei:
.LFB3670:
.cfi_startproc
endbr64
movl %edi, %eax
ret
.cfi_endproc
.LFE3670:
.size _Z11hgetDPierrei, .-_Z11hgetDPierrei
.globl _Z16generate_systemsPfS_iib
.type _Z16generate_systemsPfS_iib, @function
_Z16generate_systemsPfS_iib:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rsi, 48(%rsp)
movl %edx, %esi
movl %ecx, %ebp
leal 1(%rcx), %edx
imull %ecx, %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
leal (%rax,%rcx), %ecx
testl %esi, %esi
jle .L6
movl %eax, %r14d
movslq %ecx, %rcx
leaq 0(,%rcx,4), %rax
movq %rax, 24(%rsp)
movslq %ebp, %r8
leaq (%rdi,%r8,4), %r12
movl $0, 20(%rsp)
movq $0, 8(%rsp)
movl $0, 16(%rsp)
movl .LC0(%rip), %r13d
movl %edx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %rdi, 56(%rsp)
movl %esi, 44(%rsp)
.L13:
movq %r12, %r15
cmpl $1, 40(%rsp)
jle .L8
movl $0, %ebx
.L9:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addss .LC0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LC1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r15,%rbx,4)
addq $1, %rbx
cmpl %ebx, %r14d
jg .L9
.L8:
testl %ebp, %ebp
jle .L10
movl $0, %ebx
.L11:
movl %ebx, %edx
movl %ebx, %esi
movl %ebp, %edi
call _Z11hgetLPierreiii
cltq
movl %r13d, (%r15,%rax,4)
addl $1, %ebx
cmpl %ebx, %ebp
jne .L11
movq 56(%rsp), %rax
movq 8(%rsp), %rcx
leaq (%rax,%rcx,4), %rbx
movslq 20(%rsp), %rax
movq 48(%rsp), %rdx
leaq (%rdx,%rax,4), %r15
.L12:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addss .LC0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LC1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addss .LC0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LC1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r15)
addq $4, %rbx
addq $4, %r15
cmpq %r12, %rbx
jne .L12
.L10:
addl $1, 16(%rsp)
movl 16(%rsp), %eax
movq 24(%rsp), %rcx
addq %rcx, %r12
movq 32(%rsp), %rdi
addq %rdi, 8(%rsp)
addl %ebp, 20(%rsp)
cmpl %eax, 44(%rsp)
jne .L13
.L6:
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size _Z16generate_systemsPfS_iib, .-_Z16generate_systemsPfS_iib
.globl _Z10getLPierreiii
.type _Z10getLPierreiii, @function
_Z10getLPierreiii:
.LFB3672:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3672:
.size _Z10getLPierreiii, .-_Z10getLPierreiii
.globl _Z10getDPierreii
.type _Z10getDPierreii, @function
_Z10getDPierreii:
.LFB3673:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3673:
.size _Z10getDPierreii, .-_Z10getDPierreii
.globl _Z13parallel_copyPfS_i
.type _Z13parallel_copyPfS_i, @function
_Z13parallel_copyPfS_i:
.LFB3674:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3674:
.size _Z13parallel_copyPfS_i, .-_Z13parallel_copyPfS_i
.globl _Z35__device_stub__Z14LDLt_max_col_kPfiPfi
.type _Z35__device_stub__Z14LDLt_max_col_kPfiPfi, @function
_Z35__device_stub__Z14LDLt_max_col_kPfiPfi:
.LFB3699:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14LDLt_max_col_kPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z35__device_stub__Z14LDLt_max_col_kPfiPfi, .-_Z35__device_stub__Z14LDLt_max_col_kPfiPfi
.globl _Z14LDLt_max_col_kPfi
.type _Z14LDLt_max_col_kPfi, @function
_Z14LDLt_max_col_kPfi:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z14LDLt_max_col_kPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z14LDLt_max_col_kPfi, .-_Z14LDLt_max_col_kPfi
.globl _Z35__device_stub__Z14LDLt_max_row_kPfiPfi
.type _Z35__device_stub__Z14LDLt_max_row_kPfiPfi, @function
_Z35__device_stub__Z14LDLt_max_row_kPfiPfi:
.LFB3701:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14LDLt_max_row_kPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _Z35__device_stub__Z14LDLt_max_row_kPfiPfi, .-_Z35__device_stub__Z14LDLt_max_row_kPfiPfi
.globl _Z14LDLt_max_row_kPfi
.type _Z14LDLt_max_row_kPfi, @function
_Z14LDLt_max_row_kPfi:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z14LDLt_max_row_kPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _Z14LDLt_max_row_kPfi, .-_Z14LDLt_max_row_kPfi
.globl _Z42__device_stub__Z21LDLt_max_row_k_SHAREDPfiPfi
.type _Z42__device_stub__Z21LDLt_max_row_k_SHAREDPfiPfi, @function
_Z42__device_stub__Z21LDLt_max_row_k_SHAREDPfiPfi:
.LFB3703:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z21LDLt_max_row_k_SHAREDPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3703:
.size _Z42__device_stub__Z21LDLt_max_row_k_SHAREDPfiPfi, .-_Z42__device_stub__Z21LDLt_max_row_k_SHAREDPfiPfi
.globl _Z21LDLt_max_row_k_SHAREDPfi
.type _Z21LDLt_max_row_k_SHAREDPfi, @function
_Z21LDLt_max_row_k_SHAREDPfi:
.LFB3704:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z21LDLt_max_row_k_SHAREDPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _Z21LDLt_max_row_k_SHAREDPfi, .-_Z21LDLt_max_row_k_SHAREDPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z21LDLt_max_row_k_SHAREDPfi"
.LC3:
.string "_Z14LDLt_max_row_kPfi"
.LC4:
.string "_Z14LDLt_max_col_kPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3706:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z21LDLt_max_row_k_SHAREDPfi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z14LDLt_max_row_kPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z14LDLt_max_col_kPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3706:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -4194304
.long 1105199103
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cstdio>
#include <cstdlib>
#include <cstring>
#include <ctime>
int hgetLPierre(int d, int i, int j) {
// If j > i, then we take the transpose of L
if (j > i) {
int t = i;
i = j;
j = t;
}
int l_position = i*(i+1) / 2 + j;
// int l_position = i*(i-1) / 2 + j-1;
return l_position;
}
int hgetDPierre(int i) {
int d_position = i;
return d_position;
}
void generate_systems(float *A, float *Y, int N, int d, bool verbose=true) {
int matrix_size = d + d * (d + 1) / 2;
for (int i = 0; i < N; i++) {
float *D = &A[i * matrix_size];
float *T = &A[i * matrix_size + d];
for (int j=0; j < (d * (d + 1) / 2); j++)
T[j] = ((float) rand()+1)*1./RAND_MAX;
for (int j=0; j<d; j++)
T[hgetLPierre(d, j,j)] = 1.0f;
for (int j=0; j<d; j++) {
D[j] = ((float) rand()+1)*1./RAND_MAX;
Y[d * i + j] = ((float) rand()+1)*1./RAND_MAX;
}
}
}
// ************************************************************************ //
// __device__ int getLPierre(float* T, int n, int d, int matrix_id, int i, int j)
__device__ int getLPierre(int d, int i, int j)
{
// If j > i, then we take the transpose of L
if (j > i) {int t = i; i = j; j = t;};
// int matrix_memory_size = (d+d*(d+1)/2);
int l_position = d + i*(i+1) / 2 + j;
// int l_position = i*(i-1) / 2 + j-1;
// int l_position = d + i*(i-1) / 2 + j;
return l_position;
// return &T[matrix_id * matrix_memory_size + l_position]
}
// __device__ int getDPierre(float* T, int n, int d, int matrix_id, int i)
__device__ int getDPierre(int d, int i)
{
// int matrix_memory_size = (d+d*(d+1)/2);
int d_position = i;
return d_position;
// return &T[matrix_id * matrix_memory_size + d_position]
}
__device__ void parallel_copy(float* src, float* dest, int n)
{
int i = threadIdx.x;
int stride = blockDim.x;
while(i<n){
dest[i] = src[i];
i += stride;
}
__syncthreads();
}
// __global__ void LDLt_max_col_k(float* AGPU, int d)
__global__ void LDLt_max_col_k(float* sA, int d)
{
int tidx = threadIdx.x%d;
int Qt = (threadIdx.x-tidx)/d;
int A_size = d*(d+1)/2+d;
int minTB = blockDim.x/d;
// printf("minTB %d\n", minTB);
int nt = (blockIdx.x*minTB + Qt) * A_size;
// int gbx = Qt + blockIdx.x*(blockDim.x/d);
// extern __shared__ float sA[];
// //copy ACPU to sA
// parallel_copy(sA, &AGPU[(blockIdx.x*minTB + Qt)*A_size], minTB*A_size);
// tidx==i
// Perform the LDLt factorization
int j, k;
for(j=0; j<d; j++){
// D_j,j :
if(tidx==0){
for(k=0; k<j; k++){
sA[nt+getDPierre(d, j)] -= sA[nt+getDPierre(d,k)]*
sA[nt+getLPierre(d,j,k)]*
sA[nt+getLPierre(d,j,k)];
}
}
__syncthreads();
// L_:,j parallel
if(tidx>j){
//printf("(%d,%d,%d,%d),", nt+getLPierre(d,tidx,j), nt, tidx, j);
sA[nt+getLPierre(d,tidx,j)] /= sA[nt+getDPierre(d,j)];
for(k=0; k<j; k++){
sA[nt+getLPierre(d,tidx,j)] -= sA[nt+getLPierre(d,tidx,k)]*
sA[nt+getLPierre(d,j,k)]*
sA[nt+getDPierre(d,k)]/
sA[nt+getDPierre(d,j)];
}
}
__syncthreads();
}
// parallel_copy(&AGPU[(blockIdx.x*minTB + Qt)*A_size], sA, minTB*A_size);
}
// __global__ void LDLt_max_row_k(float* AGPU, int d)
__global__ void LDLt_max_row_k(float* sA, int d)
{
int tidx = threadIdx.x%d;
int Qt = (threadIdx.x-tidx)/d;
int A_size = d*(d+1)/2+d;
int minTB = blockDim.x/d;
// printf("minTB %d\n", minTB);
int nt = (blockIdx.x*minTB + Qt) * A_size;
// int gbx = Qt + blockIdx.x*(blockDim.x/d);
// extern __shared__ float sA[];
// //copy ACPU to sA
// parallel_copy(sA, &AGPU[(blockIdx.x*minTB + Qt)*A_size], minTB*A_size);
// Perform the LDLt factorization
int i, k;
for(i=0; i<d; i++){
// D_i,i :
if(tidx==0){
for(k=0; k<i; k++){
sA[nt+getDPierre(d, i)] -= sA[nt+getDPierre(d,k)]*
sA[nt+getLPierre(d,i,k)]*
sA[nt+getLPierre(d,i,k)];
}
}
__syncthreads();
// L_i,: parallel
if(i<tidx){
//printf("(%d,%d,%d,%d),", nt+getLPierre(d,i,tidx), nt, i,tidx);
sA[nt+getLPierre(d,i,tidx)] /= sA[nt+getDPierre(d,i)];
for(k=0; k<i; k++){
sA[nt+getLPierre(d,i,tidx)] -= sA[nt+getLPierre(d,k,tidx)]*
sA[nt+getLPierre(d,k,i)]*
sA[nt+getDPierre(d,k)]/
sA[nt+getDPierre(d,i)];
}
}
__syncthreads();
}
// parallel_copy(&sA[(blockIdx.x*minTB + Qt)*A_size], A_host, minTB*A_size);
}
// __global__ void LDLt_max_row_k(float* AGPU, int d)
__global__ void LDLt_max_row_k_SHARED(float* A_host, int d)
{
int tidx = threadIdx.x%d;
int Qt = (threadIdx.x-tidx)/d;
int A_size = d*(d+1)/2+d;
int minTB = blockDim.x/d;
// printf("minTB %d\n", minTB);
int nt = Qt * A_size;
// int gbx = Qt + blockIdx.x*(blockDim.x/d);
extern __shared__ float sA[];
//copy ACPU to sA
parallel_copy(&A_host[blockIdx.x*minTB*A_size], sA, minTB*A_size);
// tidx==j
// Perform the LDLt factorization
int i, k;
for(i=0; i<d; i++){
// D_i,i :
if(tidx==0){
for(k=0; k<i; k++){
sA[nt+getDPierre(d, i)] -= sA[nt+getDPierre(d,k)]*
sA[nt+getLPierre(d,i,k)]*
sA[nt+getLPierre(d,i,k)];
}
}
__syncthreads();
// L_i,: parallel
if(i<tidx){
//printf("(%d,%d,%d,%d),", nt+getLPierre(d,i,tidx), nt, i,tidx);
sA[nt+getLPierre(d,i,tidx)] /= sA[nt+getDPierre(d,i)];
for(k=0; k<i; k++){
sA[nt+getLPierre(d,i,tidx)] -= sA[nt+getLPierre(d,k,tidx)]*
sA[nt+getLPierre(d,k,i)]*
sA[nt+getDPierre(d,k)]/
sA[nt+getDPierre(d,i)];
}
}
__syncthreads();
}
parallel_copy(sA, &A_host[blockIdx.x*minTB*A_size], minTB*A_size);
}
// ************************************************************************ // | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdio>
#include <cstdlib>
#include <cstring>
#include <ctime>
int hgetLPierre(int d, int i, int j) {
// If j > i, then we take the transpose of L
if (j > i) {
int t = i;
i = j;
j = t;
}
int l_position = i*(i+1) / 2 + j;
// int l_position = i*(i-1) / 2 + j-1;
return l_position;
}
int hgetDPierre(int i) {
int d_position = i;
return d_position;
}
void generate_systems(float *A, float *Y, int N, int d, bool verbose=true) {
int matrix_size = d + d * (d + 1) / 2;
for (int i = 0; i < N; i++) {
float *D = &A[i * matrix_size];
float *T = &A[i * matrix_size + d];
for (int j=0; j < (d * (d + 1) / 2); j++)
T[j] = ((float) rand()+1)*1./RAND_MAX;
for (int j=0; j<d; j++)
T[hgetLPierre(d, j,j)] = 1.0f;
for (int j=0; j<d; j++) {
D[j] = ((float) rand()+1)*1./RAND_MAX;
Y[d * i + j] = ((float) rand()+1)*1./RAND_MAX;
}
}
}
// ************************************************************************ //
// __device__ int getLPierre(float* T, int n, int d, int matrix_id, int i, int j)
__device__ int getLPierre(int d, int i, int j)
{
// If j > i, then we take the transpose of L
if (j > i) {int t = i; i = j; j = t;};
// int matrix_memory_size = (d+d*(d+1)/2);
int l_position = d + i*(i+1) / 2 + j;
// int l_position = i*(i-1) / 2 + j-1;
// int l_position = d + i*(i-1) / 2 + j;
return l_position;
// return &T[matrix_id * matrix_memory_size + l_position]
}
// __device__ int getDPierre(float* T, int n, int d, int matrix_id, int i)
__device__ int getDPierre(int d, int i)
{
// int matrix_memory_size = (d+d*(d+1)/2);
int d_position = i;
return d_position;
// return &T[matrix_id * matrix_memory_size + d_position]
}
__device__ void parallel_copy(float* src, float* dest, int n)
{
int i = threadIdx.x;
int stride = blockDim.x;
while(i<n){
dest[i] = src[i];
i += stride;
}
__syncthreads();
}
// __global__ void LDLt_max_col_k(float* AGPU, int d)
__global__ void LDLt_max_col_k(float* sA, int d)
{
int tidx = threadIdx.x%d;
int Qt = (threadIdx.x-tidx)/d;
int A_size = d*(d+1)/2+d;
int minTB = blockDim.x/d;
// printf("minTB %d\n", minTB);
int nt = (blockIdx.x*minTB + Qt) * A_size;
// int gbx = Qt + blockIdx.x*(blockDim.x/d);
// extern __shared__ float sA[];
// //copy ACPU to sA
// parallel_copy(sA, &AGPU[(blockIdx.x*minTB + Qt)*A_size], minTB*A_size);
// tidx==i
// Perform the LDLt factorization
int j, k;
for(j=0; j<d; j++){
// D_j,j :
if(tidx==0){
for(k=0; k<j; k++){
sA[nt+getDPierre(d, j)] -= sA[nt+getDPierre(d,k)]*
sA[nt+getLPierre(d,j,k)]*
sA[nt+getLPierre(d,j,k)];
}
}
__syncthreads();
// L_:,j parallel
if(tidx>j){
//printf("(%d,%d,%d,%d),", nt+getLPierre(d,tidx,j), nt, tidx, j);
sA[nt+getLPierre(d,tidx,j)] /= sA[nt+getDPierre(d,j)];
for(k=0; k<j; k++){
sA[nt+getLPierre(d,tidx,j)] -= sA[nt+getLPierre(d,tidx,k)]*
sA[nt+getLPierre(d,j,k)]*
sA[nt+getDPierre(d,k)]/
sA[nt+getDPierre(d,j)];
}
}
__syncthreads();
}
// parallel_copy(&AGPU[(blockIdx.x*minTB + Qt)*A_size], sA, minTB*A_size);
}
// __global__ void LDLt_max_row_k(float* AGPU, int d)
__global__ void LDLt_max_row_k(float* sA, int d)
{
int tidx = threadIdx.x%d;
int Qt = (threadIdx.x-tidx)/d;
int A_size = d*(d+1)/2+d;
int minTB = blockDim.x/d;
// printf("minTB %d\n", minTB);
int nt = (blockIdx.x*minTB + Qt) * A_size;
// int gbx = Qt + blockIdx.x*(blockDim.x/d);
// extern __shared__ float sA[];
// //copy ACPU to sA
// parallel_copy(sA, &AGPU[(blockIdx.x*minTB + Qt)*A_size], minTB*A_size);
// Perform the LDLt factorization
int i, k;
for(i=0; i<d; i++){
// D_i,i :
if(tidx==0){
for(k=0; k<i; k++){
sA[nt+getDPierre(d, i)] -= sA[nt+getDPierre(d,k)]*
sA[nt+getLPierre(d,i,k)]*
sA[nt+getLPierre(d,i,k)];
}
}
__syncthreads();
// L_i,: parallel
if(i<tidx){
//printf("(%d,%d,%d,%d),", nt+getLPierre(d,i,tidx), nt, i,tidx);
sA[nt+getLPierre(d,i,tidx)] /= sA[nt+getDPierre(d,i)];
for(k=0; k<i; k++){
sA[nt+getLPierre(d,i,tidx)] -= sA[nt+getLPierre(d,k,tidx)]*
sA[nt+getLPierre(d,k,i)]*
sA[nt+getDPierre(d,k)]/
sA[nt+getDPierre(d,i)];
}
}
__syncthreads();
}
// parallel_copy(&sA[(blockIdx.x*minTB + Qt)*A_size], A_host, minTB*A_size);
}
// __global__ void LDLt_max_row_k(float* AGPU, int d)
__global__ void LDLt_max_row_k_SHARED(float* A_host, int d)
{
int tidx = threadIdx.x%d;
int Qt = (threadIdx.x-tidx)/d;
int A_size = d*(d+1)/2+d;
int minTB = blockDim.x/d;
// printf("minTB %d\n", minTB);
int nt = Qt * A_size;
// int gbx = Qt + blockIdx.x*(blockDim.x/d);
extern __shared__ float sA[];
//copy ACPU to sA
parallel_copy(&A_host[blockIdx.x*minTB*A_size], sA, minTB*A_size);
// tidx==j
// Perform the LDLt factorization
int i, k;
for(i=0; i<d; i++){
// D_i,i :
if(tidx==0){
for(k=0; k<i; k++){
sA[nt+getDPierre(d, i)] -= sA[nt+getDPierre(d,k)]*
sA[nt+getLPierre(d,i,k)]*
sA[nt+getLPierre(d,i,k)];
}
}
__syncthreads();
// L_i,: parallel
if(i<tidx){
//printf("(%d,%d,%d,%d),", nt+getLPierre(d,i,tidx), nt, i,tidx);
sA[nt+getLPierre(d,i,tidx)] /= sA[nt+getDPierre(d,i)];
for(k=0; k<i; k++){
sA[nt+getLPierre(d,i,tidx)] -= sA[nt+getLPierre(d,k,tidx)]*
sA[nt+getLPierre(d,k,i)]*
sA[nt+getDPierre(d,k)]/
sA[nt+getDPierre(d,i)];
}
}
__syncthreads();
}
parallel_copy(sA, &A_host[blockIdx.x*minTB*A_size], minTB*A_size);
}
// ************************************************************************ // |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdio>
#include <cstdlib>
#include <cstring>
#include <ctime>
int hgetLPierre(int d, int i, int j) {
// If j > i, then we take the transpose of L
if (j > i) {
int t = i;
i = j;
j = t;
}
int l_position = i*(i+1) / 2 + j;
// int l_position = i*(i-1) / 2 + j-1;
return l_position;
}
int hgetDPierre(int i) {
int d_position = i;
return d_position;
}
void generate_systems(float *A, float *Y, int N, int d, bool verbose=true) {
int matrix_size = d + d * (d + 1) / 2;
for (int i = 0; i < N; i++) {
float *D = &A[i * matrix_size];
float *T = &A[i * matrix_size + d];
for (int j=0; j < (d * (d + 1) / 2); j++)
T[j] = ((float) rand()+1)*1./RAND_MAX;
for (int j=0; j<d; j++)
T[hgetLPierre(d, j,j)] = 1.0f;
for (int j=0; j<d; j++) {
D[j] = ((float) rand()+1)*1./RAND_MAX;
Y[d * i + j] = ((float) rand()+1)*1./RAND_MAX;
}
}
}
// ************************************************************************ //
// __device__ int getLPierre(float* T, int n, int d, int matrix_id, int i, int j)
__device__ int getLPierre(int d, int i, int j)
{
// If j > i, then we take the transpose of L
if (j > i) {int t = i; i = j; j = t;};
// int matrix_memory_size = (d+d*(d+1)/2);
int l_position = d + i*(i+1) / 2 + j;
// int l_position = i*(i-1) / 2 + j-1;
// int l_position = d + i*(i-1) / 2 + j;
return l_position;
// return &T[matrix_id * matrix_memory_size + l_position]
}
// __device__ int getDPierre(float* T, int n, int d, int matrix_id, int i)
__device__ int getDPierre(int d, int i)
{
// int matrix_memory_size = (d+d*(d+1)/2);
int d_position = i;
return d_position;
// return &T[matrix_id * matrix_memory_size + d_position]
}
__device__ void parallel_copy(float* src, float* dest, int n)
{
int i = threadIdx.x;
int stride = blockDim.x;
while(i<n){
dest[i] = src[i];
i += stride;
}
__syncthreads();
}
// __global__ void LDLt_max_col_k(float* AGPU, int d)
__global__ void LDLt_max_col_k(float* sA, int d)
{
int tidx = threadIdx.x%d;
int Qt = (threadIdx.x-tidx)/d;
int A_size = d*(d+1)/2+d;
int minTB = blockDim.x/d;
// printf("minTB %d\n", minTB);
int nt = (blockIdx.x*minTB + Qt) * A_size;
// int gbx = Qt + blockIdx.x*(blockDim.x/d);
// extern __shared__ float sA[];
// //copy ACPU to sA
// parallel_copy(sA, &AGPU[(blockIdx.x*minTB + Qt)*A_size], minTB*A_size);
// tidx==i
// Perform the LDLt factorization
int j, k;
for(j=0; j<d; j++){
// D_j,j :
if(tidx==0){
for(k=0; k<j; k++){
sA[nt+getDPierre(d, j)] -= sA[nt+getDPierre(d,k)]*
sA[nt+getLPierre(d,j,k)]*
sA[nt+getLPierre(d,j,k)];
}
}
__syncthreads();
// L_:,j parallel
if(tidx>j){
//printf("(%d,%d,%d,%d),", nt+getLPierre(d,tidx,j), nt, tidx, j);
sA[nt+getLPierre(d,tidx,j)] /= sA[nt+getDPierre(d,j)];
for(k=0; k<j; k++){
sA[nt+getLPierre(d,tidx,j)] -= sA[nt+getLPierre(d,tidx,k)]*
sA[nt+getLPierre(d,j,k)]*
sA[nt+getDPierre(d,k)]/
sA[nt+getDPierre(d,j)];
}
}
__syncthreads();
}
// parallel_copy(&AGPU[(blockIdx.x*minTB + Qt)*A_size], sA, minTB*A_size);
}
// __global__ void LDLt_max_row_k(float* AGPU, int d)
__global__ void LDLt_max_row_k(float* sA, int d)
{
int tidx = threadIdx.x%d;
int Qt = (threadIdx.x-tidx)/d;
int A_size = d*(d+1)/2+d;
int minTB = blockDim.x/d;
// printf("minTB %d\n", minTB);
int nt = (blockIdx.x*minTB + Qt) * A_size;
// int gbx = Qt + blockIdx.x*(blockDim.x/d);
// extern __shared__ float sA[];
// //copy ACPU to sA
// parallel_copy(sA, &AGPU[(blockIdx.x*minTB + Qt)*A_size], minTB*A_size);
// Perform the LDLt factorization
int i, k;
for(i=0; i<d; i++){
// D_i,i :
if(tidx==0){
for(k=0; k<i; k++){
sA[nt+getDPierre(d, i)] -= sA[nt+getDPierre(d,k)]*
sA[nt+getLPierre(d,i,k)]*
sA[nt+getLPierre(d,i,k)];
}
}
__syncthreads();
// L_i,: parallel
if(i<tidx){
//printf("(%d,%d,%d,%d),", nt+getLPierre(d,i,tidx), nt, i,tidx);
sA[nt+getLPierre(d,i,tidx)] /= sA[nt+getDPierre(d,i)];
for(k=0; k<i; k++){
sA[nt+getLPierre(d,i,tidx)] -= sA[nt+getLPierre(d,k,tidx)]*
sA[nt+getLPierre(d,k,i)]*
sA[nt+getDPierre(d,k)]/
sA[nt+getDPierre(d,i)];
}
}
__syncthreads();
}
// parallel_copy(&sA[(blockIdx.x*minTB + Qt)*A_size], A_host, minTB*A_size);
}
// __global__ void LDLt_max_row_k(float* AGPU, int d)
__global__ void LDLt_max_row_k_SHARED(float* A_host, int d)
{
int tidx = threadIdx.x%d;
int Qt = (threadIdx.x-tidx)/d;
int A_size = d*(d+1)/2+d;
int minTB = blockDim.x/d;
// printf("minTB %d\n", minTB);
int nt = Qt * A_size;
// int gbx = Qt + blockIdx.x*(blockDim.x/d);
extern __shared__ float sA[];
//copy ACPU to sA
parallel_copy(&A_host[blockIdx.x*minTB*A_size], sA, minTB*A_size);
// tidx==j
// Perform the LDLt factorization
int i, k;
for(i=0; i<d; i++){
// D_i,i :
if(tidx==0){
for(k=0; k<i; k++){
sA[nt+getDPierre(d, i)] -= sA[nt+getDPierre(d,k)]*
sA[nt+getLPierre(d,i,k)]*
sA[nt+getLPierre(d,i,k)];
}
}
__syncthreads();
// L_i,: parallel
if(i<tidx){
//printf("(%d,%d,%d,%d),", nt+getLPierre(d,i,tidx), nt, i,tidx);
sA[nt+getLPierre(d,i,tidx)] /= sA[nt+getDPierre(d,i)];
for(k=0; k<i; k++){
sA[nt+getLPierre(d,i,tidx)] -= sA[nt+getLPierre(d,k,tidx)]*
sA[nt+getLPierre(d,k,i)]*
sA[nt+getDPierre(d,k)]/
sA[nt+getDPierre(d,i)];
}
}
__syncthreads();
}
parallel_copy(sA, &A_host[blockIdx.x*minTB*A_size], minTB*A_size);
}
// ************************************************************************ // | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14LDLt_max_col_kPfi
.globl _Z14LDLt_max_col_kPfi
.p2align 8
.type _Z14LDLt_max_col_kPfi,@function
_Z14LDLt_max_col_kPfi:
s_load_b32 s4, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s4
s_cmp_lt_i32 s4, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1)
v_readfirstlane_b32 s2, v1
s_cbranch_scc1 .LBB0_10
s_sub_i32 s3, 0, s4
s_load_b32 s5, s[0:1], 0x1c
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s3, s3, s2
s_mul_hi_u32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s6, s2, s3
s_add_i32 s2, s4, 1
v_mad_u64_u32 v[1:2], null, v0, s6, 0
s_mul_i32 s7, s2, s4
s_load_b64 s[2:3], s[0:1], 0x0
s_lshr_b32 s8, s7, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s8
s_ashr_i32 s1, s7, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v1, v2, s4
v_add_nc_u32_e32 v3, 1, v2
s_add_i32 s1, s1, s4
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s5, 0xffff
s_mul_hi_u32 s5, s0, s6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_sub_nc_u32_e32 v1, v0, v1
s_mul_i32 s6, s5, s4
s_sub_i32 s0, s0, s6
s_add_i32 s6, s5, 1
s_delay_alu instid0(VALU_DEP_1)
v_subrev_nc_u32_e32 v4, s4, v1
v_cmp_le_u32_e32 vcc_lo, s4, v1
s_sub_i32 s7, s0, s4
s_cmp_ge_u32 s0, s4
s_cselect_b32 s5, s6, s5
v_dual_cndmask_b32 v2, v2, v3 :: v_dual_cndmask_b32 v1, v1, v4
s_cselect_b32 s0, s7, s0
s_add_i32 s6, s5, 1
s_cmp_ge_u32 s0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, 1, v2
v_cmp_le_u32_e32 vcc_lo, s4, v1
s_cselect_b32 s0, s6, s5
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s0, s15, v[2:3]
v_mul_lo_u32 v1, v3, s1
v_mul_lo_u32 v3, v2, s4
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_sub_nc_u32_e32 v0, v0, v3
v_add_nc_u32_e32 v10, s4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_cmp_eq_u32_e64 s0, 0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
s_add_i32 s1, s1, 1
s_waitcnt_vscnt null, 0x0
s_cmp_lg_u32 s1, s4
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_10
.LBB0_3:
s_cmp_lg_u32 s1, 0
v_add_nc_u32_e32 v4, s1, v1
s_cselect_b32 s5, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s6, s0, s5
s_and_saveexec_b32 s5, s6
s_cbranch_execz .LBB0_6
v_ashrrev_i32_e32 v5, 31, v4
v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v7, v2
s_mov_b32 s6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[4:5]
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v9, v[5:6], off
.p2align 6
.LBB0_5:
s_max_i32 s7, s6, s1
s_min_i32 s8, s6, s1
s_add_i32 s9, s7, 1
s_add_i32 s6, s6, 1
s_mul_i32 s9, s9, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_lshr_b32 s7, s9, 1
s_cmp_lt_u32 s6, s1
v_add3_u32 v11, s7, s8, v10
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_u32 v11, vcc_lo, s2, v11
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
global_load_b32 v13, v[7:8], off
global_load_b32 v11, v[11:12], off
v_add_co_u32 v7, vcc_lo, v7, 4
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v12, v13, v11
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v9, -v11, v12, v9
global_store_b32 v[5:6], v9, off
s_cbranch_scc1 .LBB0_5
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s5, exec_lo
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_lt_u32_e64 s1, v0
s_cbranch_execz .LBB0_2
v_max_i32_e32 v5, s1, v0
s_cmp_eq_u32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[6:7], null, v5, v5, v[5:6]
v_min_i32_e32 v5, s1, v0
v_lshrrev_b32_e32 v6, 1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v6, v10, v5, v6
v_ashrrev_i32_e32 v5, 31, v4
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_clause 0x1
global_load_b32 v8, v[4:5], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v11, null, v8, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v12, v11
s_waitcnt_depctr 0xfff
v_fma_f32 v13, -v11, v12, 1.0
v_fmac_f32_e32 v12, v13, v12
v_div_scale_f32 v13, vcc_lo, v9, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v14, v13, v12
v_fma_f32 v15, -v11, v14, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v14, v15, v12
v_fma_f32 v11, -v11, v14, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v11, v11, v12, v14
v_div_fixup_f32 v8, v11, v8, v9
global_store_b32 v[6:7], v8, off
s_cbranch_scc1 .LBB0_2
v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
s_mov_b32 s6, 0
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1)
v_max_i32_e32 v11, s6, v0
s_max_i32 s7, s6, s1
v_min_i32_e32 v14, s6, v0
s_add_i32 s9, s7, 1
s_min_i32 s8, s6, s1
v_mad_u64_u32 v[12:13], null, v11, v11, v[11:12]
s_mul_i32 s9, s9, s7
s_add_i32 s6, s6, 1
s_lshr_b32 s7, s9, 1
s_cmp_lt_u32 s6, s1
v_add3_u32 v11, s7, s8, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshrrev_b32_e32 v13, 1, v12
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v13, v10, v14, v13
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v14, 31, v13
v_add_co_u32 v11, vcc_lo, s2, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[13:14], 2, v[13:14]
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v13, vcc_lo, s2, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s3, v14, vcc_lo
s_clause 0x1
global_load_b32 v11, v[11:12], off
global_load_b32 v12, v[13:14], off
global_load_b32 v13, v[8:9], off
s_clause 0x1
global_load_b32 v14, v[4:5], off
global_load_b32 v15, v[6:7], off
s_waitcnt vmcnt(3)
v_mul_f32_e32 v11, v12, v11
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v11, v11, v13
s_waitcnt vmcnt(1)
v_div_scale_f32 v12, null, v14, v14, v11
v_div_scale_f32 v17, vcc_lo, v11, v14, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v13, v12
s_waitcnt_depctr 0xfff
v_fma_f32 v16, -v12, v13, 1.0
v_fmac_f32_e32 v13, v16, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v16, v17, v13
v_fma_f32 v18, -v12, v16, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v16, v18, v13
v_fma_f32 v12, -v12, v16, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f32 v12, v12, v13, v16
v_add_co_u32 v8, vcc_lo, v8, 4
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
v_div_fixup_f32 v11, v12, v14, v11
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_sub_f32_e32 v11, v15, v11
global_store_b32 v[6:7], v11, off
s_cbranch_scc1 .LBB0_9
s_branch .LBB0_2
.LBB0_10:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14LDLt_max_col_kPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14LDLt_max_col_kPfi, .Lfunc_end0-_Z14LDLt_max_col_kPfi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14LDLt_max_row_kPfi
.globl _Z14LDLt_max_row_kPfi
.p2align 8
.type _Z14LDLt_max_row_kPfi,@function
_Z14LDLt_max_row_kPfi:
s_load_b32 s4, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s4
s_cmp_lt_i32 s4, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1)
v_readfirstlane_b32 s2, v1
s_cbranch_scc1 .LBB1_10
s_sub_i32 s3, 0, s4
s_load_b32 s5, s[0:1], 0x1c
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s3, s3, s2
s_mul_hi_u32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s6, s2, s3
s_add_i32 s2, s4, 1
v_mad_u64_u32 v[1:2], null, v0, s6, 0
s_mul_i32 s7, s2, s4
s_load_b64 s[2:3], s[0:1], 0x0
s_lshr_b32 s8, s7, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s8
s_ashr_i32 s1, s7, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v1, v2, s4
v_add_nc_u32_e32 v3, 1, v2
s_add_i32 s1, s1, s4
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s5, 0xffff
s_mul_hi_u32 s5, s0, s6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_sub_nc_u32_e32 v1, v0, v1
s_mul_i32 s6, s5, s4
s_sub_i32 s0, s0, s6
s_add_i32 s6, s5, 1
s_delay_alu instid0(VALU_DEP_1)
v_subrev_nc_u32_e32 v4, s4, v1
v_cmp_le_u32_e32 vcc_lo, s4, v1
s_sub_i32 s7, s0, s4
s_cmp_ge_u32 s0, s4
s_cselect_b32 s5, s6, s5
v_dual_cndmask_b32 v2, v2, v3 :: v_dual_cndmask_b32 v1, v1, v4
s_cselect_b32 s0, s7, s0
s_add_i32 s6, s5, 1
s_cmp_ge_u32 s0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, 1, v2
v_cmp_le_u32_e32 vcc_lo, s4, v1
s_cselect_b32 s0, s6, s5
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s0, s15, v[2:3]
v_mul_lo_u32 v1, v3, s1
v_mul_lo_u32 v3, v2, s4
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_sub_nc_u32_e32 v0, v0, v3
v_add_nc_u32_e32 v10, s4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_cmp_eq_u32_e64 s0, 0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_branch .LBB1_3
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s5
s_add_i32 s1, s1, 1
s_waitcnt_vscnt null, 0x0
s_cmp_lg_u32 s1, s4
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_10
.LBB1_3:
s_cmp_lg_u32 s1, 0
v_add_nc_u32_e32 v4, s1, v1
s_cselect_b32 s5, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s6, s0, s5
s_and_saveexec_b32 s5, s6
s_cbranch_execz .LBB1_6
v_ashrrev_i32_e32 v5, 31, v4
v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v7, v2
s_mov_b32 s6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[4:5]
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v9, v[5:6], off
.p2align 6
.LBB1_5:
s_max_i32 s7, s6, s1
s_min_i32 s8, s6, s1
s_add_i32 s9, s7, 1
s_add_i32 s6, s6, 1
s_mul_i32 s9, s9, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_lshr_b32 s7, s9, 1
s_cmp_lt_u32 s6, s1
v_add3_u32 v11, s7, s8, v10
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_u32 v11, vcc_lo, s2, v11
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
global_load_b32 v13, v[7:8], off
global_load_b32 v11, v[11:12], off
v_add_co_u32 v7, vcc_lo, v7, 4
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v12, v13, v11
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v9, -v11, v12, v9
global_store_b32 v[5:6], v9, off
s_cbranch_scc1 .LBB1_5
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s5, exec_lo
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_lt_u32_e64 s1, v0
s_cbranch_execz .LBB1_2
v_max_i32_e32 v5, s1, v0
s_cmp_eq_u32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[6:7], null, v5, v5, v[5:6]
v_min_i32_e32 v5, s1, v0
v_lshrrev_b32_e32 v6, 1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v6, v10, v5, v6
v_ashrrev_i32_e32 v5, 31, v4
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_clause 0x1
global_load_b32 v8, v[4:5], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v11, null, v8, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v12, v11
s_waitcnt_depctr 0xfff
v_fma_f32 v13, -v11, v12, 1.0
v_fmac_f32_e32 v12, v13, v12
v_div_scale_f32 v13, vcc_lo, v9, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v14, v13, v12
v_fma_f32 v15, -v11, v14, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v14, v15, v12
v_fma_f32 v11, -v11, v14, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v11, v11, v12, v14
v_div_fixup_f32 v8, v11, v8, v9
global_store_b32 v[6:7], v8, off
s_cbranch_scc1 .LBB1_2
v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
s_mov_b32 s6, 0
.LBB1_9:
s_delay_alu instid0(SALU_CYCLE_1)
v_max_i32_e32 v11, s6, v0
s_max_i32 s7, s1, s6
v_min_i32_e32 v14, s6, v0
s_add_i32 s9, s7, 1
s_min_i32 s8, s1, s6
v_mad_u64_u32 v[12:13], null, v11, v11, v[11:12]
s_mul_i32 s9, s9, s7
s_add_i32 s6, s6, 1
s_lshr_b32 s7, s9, 1
s_cmp_lt_u32 s6, s1
v_add3_u32 v11, s7, s8, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshrrev_b32_e32 v13, 1, v12
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v13, v10, v14, v13
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v14, 31, v13
v_add_co_u32 v11, vcc_lo, s2, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[13:14], 2, v[13:14]
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v13, vcc_lo, s2, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s3, v14, vcc_lo
s_clause 0x1
global_load_b32 v11, v[11:12], off
global_load_b32 v12, v[13:14], off
global_load_b32 v13, v[8:9], off
s_clause 0x1
global_load_b32 v14, v[4:5], off
global_load_b32 v15, v[6:7], off
s_waitcnt vmcnt(3)
v_mul_f32_e32 v11, v12, v11
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v11, v11, v13
s_waitcnt vmcnt(1)
v_div_scale_f32 v12, null, v14, v14, v11
v_div_scale_f32 v17, vcc_lo, v11, v14, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v13, v12
s_waitcnt_depctr 0xfff
v_fma_f32 v16, -v12, v13, 1.0
v_fmac_f32_e32 v13, v16, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v16, v17, v13
v_fma_f32 v18, -v12, v16, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v16, v18, v13
v_fma_f32 v12, -v12, v16, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f32 v12, v12, v13, v16
v_add_co_u32 v8, vcc_lo, v8, 4
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
v_div_fixup_f32 v11, v12, v14, v11
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_sub_f32_e32 v11, v15, v11
global_store_b32 v[6:7], v11, off
s_cbranch_scc1 .LBB1_9
s_branch .LBB1_2
.LBB1_10:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14LDLt_max_row_kPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z14LDLt_max_row_kPfi, .Lfunc_end1-_Z14LDLt_max_row_kPfi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z21LDLt_max_row_k_SHAREDPfi
.globl _Z21LDLt_max_row_k_SHAREDPfi
.p2align 8
.type _Z21LDLt_max_row_k_SHAREDPfi,@function
_Z21LDLt_max_row_k_SHAREDPfi:
s_clause 0x2
s_load_b32 s8, s[0:1], 0x8
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s8
s_sub_i32 s0, 0, s8
s_add_i32 s1, s8, 1
s_and_b32 s6, s4, 0xffff
s_mul_i32 s1, s1, s8
v_rcp_iflag_f32_e32 v1, v1
s_lshr_b32 s4, s1, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s1, s1, s4
s_ashr_i32 s9, s1, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_add_i32 s9, s9, s8
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s5, v1
s_mul_i32 s0, s0, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s0, s5, s0
s_add_i32 s5, s5, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_hi_u32 s0, s6, s5
v_mad_u64_u32 v[1:2], null, v0, s5, 0
s_mul_i32 s1, s0, s8
s_add_i32 s4, s0, 1
s_sub_i32 s1, s6, s1
s_mov_b32 s5, 0
s_sub_i32 s7, s1, s8
s_cmp_ge_u32 s1, s8
s_cselect_b32 s0, s4, s0
s_cselect_b32 s1, s7, s1
s_add_i32 s4, s0, 1
s_cmp_ge_u32 s1, s8
s_cselect_b32 s7, s4, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s7, s7, s9
v_cmp_gt_i32_e64 s0, s7, v0
s_mul_i32 s4, s7, s15
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s10, s0
s_cbranch_execz .LBB2_3
v_lshlrev_b32_e32 v3, 2, v0
s_lshl_b64 s[12:13], s[4:5], 2
s_lshl_b32 s11, s6, 2
s_add_u32 s1, s2, s12
s_addc_u32 s12, s3, s13
v_add_co_u32 v3, s1, s1, v3
v_lshl_add_u32 v1, v0, 2, 0
v_add_co_ci_u32_e64 v4, null, s12, 0, s1
v_mov_b32_e32 v5, v0
s_mov_b32 s12, s5
s_mov_b32 s13, s5
.LBB2_2:
global_load_b32 v6, v[3:4], off
v_add_nc_u32_e32 v5, s6, v5
v_add_co_u32 v3, vcc_lo, v3, s11
v_add_co_ci_u32_e32 v4, vcc_lo, s12, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s1, s7, v5
s_or_b32 s13, s1, s13
s_waitcnt vmcnt(0)
ds_store_b32 v1, v6
v_add_nc_u32_e32 v1, s11, v1
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execnz .LBB2_2
.LBB2_3:
s_or_b32 exec_lo, exec_lo, s10
s_cmp_lt_i32 s8, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB2_13
v_mul_lo_u32 v1, v2, s8
v_add_nc_u32_e32 v3, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v0, v1
v_subrev_nc_u32_e32 v4, s8, v1
v_cmp_le_u32_e32 vcc_lo, s8, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v2, v2, v3 :: v_dual_cndmask_b32 v1, v1, v4
v_add_nc_u32_e32 v3, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s8, v1
v_cndmask_b32_e32 v1, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v1, s8
v_mul_lo_u32 v1, v1, s9
s_mov_b32 s9, 0
v_sub_nc_u32_e32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v3, s8, v1
v_lshl_add_u32 v4, v1, 2, 0
v_cmp_eq_u32_e64 s1, 0, v2
s_branch .LBB2_6
.LBB2_5:
s_or_b32 exec_lo, exec_lo, s10
s_add_i32 s9, s9, 1
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s9, s8
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB2_13
.LBB2_6:
s_cmp_lg_u32 s9, 0
v_add_nc_u32_e32 v5, s9, v1
s_cselect_b32 s10, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s11, s1, s10
s_and_saveexec_b32 s10, s11
s_cbranch_execz .LBB2_9
v_lshl_add_u32 v6, v5, 2, 0
v_mov_b32_e32 v8, v4
s_mov_b32 s11, 0
ds_load_b32 v7, v6
.p2align 6
.LBB2_8:
s_max_i32 s12, s11, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s12, 1
s_mul_i32 s13, s13, s12
s_min_i32 s12, s11, s9
s_lshr_b32 s13, s13, 1
s_add_i32 s11, s11, 1
v_add3_u32 v9, s13, s12, v3
s_cmp_lt_u32 s11, s9
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v9, v9, 2, 0
ds_load_b32 v10, v8
ds_load_b32 v9, v9
v_add_nc_u32_e32 v8, 4, v8
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v10, v10, v9
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v7, -v9, v10, v7
ds_store_b32 v6, v7
s_cbranch_scc1 .LBB2_8
.LBB2_9:
s_or_b32 exec_lo, exec_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_lt_u32_e64 s9, v2
s_cbranch_execz .LBB2_5
v_max_i32_e32 v6, s9, v2
v_lshl_add_u32 v5, v5, 2, 0
s_cmp_eq_u32 s9, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[7:8], null, v6, v6, v[6:7]
v_min_i32_e32 v6, s9, v2
v_lshrrev_b32_e32 v7, 1, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v6, v3, v6, v7
v_lshl_add_u32 v6, v6, 2, 0
ds_load_b32 v7, v5
ds_load_b32 v8, v6
s_waitcnt lgkmcnt(0)
v_div_scale_f32 v9, null, v7, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v10, v9
s_waitcnt_depctr 0xfff
v_fma_f32 v11, -v9, v10, 1.0
v_fmac_f32_e32 v10, v11, v10
v_div_scale_f32 v11, vcc_lo, v8, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v12, v11, v10
v_fma_f32 v13, -v9, v12, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v12, v13, v10
v_fma_f32 v9, -v9, v12, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v9, v9, v10, v12
v_div_fixup_f32 v7, v9, v7, v8
ds_store_b32 v6, v7
s_cbranch_scc1 .LBB2_5
v_mov_b32_e32 v7, v4
s_mov_b32 s11, 0
.LBB2_12:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_max_i32_e32 v8, s11, v2
s_max_i32 s12, s9, s11
s_min_i32 s13, s9, s11
s_add_i32 s14, s12, 1
s_mul_i32 s14, s14, s12
v_mad_u64_u32 v[9:10], null, v8, v8, v[8:9]
v_min_i32_e32 v8, s11, v2
s_lshr_b32 s12, s14, 1
s_add_i32 s11, s11, 1
v_add3_u32 v10, s12, s13, v3
s_cmp_lt_u32 s11, s9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v9, 1, v9
v_add3_u32 v8, v3, v8, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v9, v10, 2, 0
v_lshl_add_u32 v8, v8, 2, 0
ds_load_b32 v9, v9
ds_load_b32 v8, v8
ds_load_b32 v10, v7
ds_load_b32 v11, v5
ds_load_b32 v12, v6
s_waitcnt lgkmcnt(3)
v_dual_mul_f32 v8, v8, v9 :: v_dual_add_nc_u32 v7, 4, v7
s_waitcnt lgkmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, v8, v10
s_waitcnt lgkmcnt(1)
v_div_scale_f32 v9, null, v11, v11, v8
v_div_scale_f32 v14, vcc_lo, v8, v11, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v10, v9
s_waitcnt_depctr 0xfff
v_fma_f32 v13, -v9, v10, 1.0
v_fmac_f32_e32 v10, v13, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v13, v14, v10
v_fma_f32 v15, -v9, v13, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v13, v15, v10
v_fma_f32 v9, -v9, v13, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v9, v9, v10, v13
v_div_fixup_f32 v8, v9, v11, v8
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_sub_f32_e32 v8, v12, v8
ds_store_b32 v6, v8
s_cbranch_scc1 .LBB2_12
s_branch .LBB2_5
.LBB2_13:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB2_16
v_lshlrev_b32_e32 v1, 2, v0
s_lshl_b64 s[8:9], s[4:5], 2
s_lshl_b32 s4, s6, 2
s_add_u32 s0, s2, s8
s_addc_u32 s2, s3, s9
v_add_nc_u32_e32 v3, 0, v1
v_add_co_u32 v1, s0, s0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v2, null, s2, 0, s0
s_mov_b32 s2, 0
s_mov_b32 s3, s2
.LBB2_15:
ds_load_b32 v4, v3
v_add_nc_u32_e32 v0, s6, v0
v_add_nc_u32_e32 v3, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, s7, v0
s_or_b32 s3, vcc_lo, s3
s_waitcnt lgkmcnt(0)
global_store_b32 v[1:2], v4, off
v_add_co_u32 v1, s0, v1, s4
v_add_co_ci_u32_e64 v2, s0, s2, v2, s0
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB2_15
.LBB2_16:
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21LDLt_max_row_k_SHAREDPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z21LDLt_max_row_k_SHAREDPfi, .Lfunc_end2-_Z21LDLt_max_row_k_SHAREDPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14LDLt_max_col_kPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14LDLt_max_col_kPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14LDLt_max_row_kPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14LDLt_max_row_kPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21LDLt_max_row_k_SHAREDPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21LDLt_max_row_k_SHAREDPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdio>
#include <cstdlib>
#include <cstring>
#include <ctime>
int hgetLPierre(int d, int i, int j) {
// If j > i, then we take the transpose of L
if (j > i) {
int t = i;
i = j;
j = t;
}
int l_position = i*(i+1) / 2 + j;
// int l_position = i*(i-1) / 2 + j-1;
return l_position;
}
int hgetDPierre(int i) {
int d_position = i;
return d_position;
}
void generate_systems(float *A, float *Y, int N, int d, bool verbose=true) {
int matrix_size = d + d * (d + 1) / 2;
for (int i = 0; i < N; i++) {
float *D = &A[i * matrix_size];
float *T = &A[i * matrix_size + d];
for (int j=0; j < (d * (d + 1) / 2); j++)
T[j] = ((float) rand()+1)*1./RAND_MAX;
for (int j=0; j<d; j++)
T[hgetLPierre(d, j,j)] = 1.0f;
for (int j=0; j<d; j++) {
D[j] = ((float) rand()+1)*1./RAND_MAX;
Y[d * i + j] = ((float) rand()+1)*1./RAND_MAX;
}
}
}
// ************************************************************************ //
// __device__ int getLPierre(float* T, int n, int d, int matrix_id, int i, int j)
__device__ int getLPierre(int d, int i, int j)
{
// If j > i, then we take the transpose of L
if (j > i) {int t = i; i = j; j = t;};
// int matrix_memory_size = (d+d*(d+1)/2);
int l_position = d + i*(i+1) / 2 + j;
// int l_position = i*(i-1) / 2 + j-1;
// int l_position = d + i*(i-1) / 2 + j;
return l_position;
// return &T[matrix_id * matrix_memory_size + l_position]
}
// __device__ int getDPierre(float* T, int n, int d, int matrix_id, int i)
__device__ int getDPierre(int d, int i)
{
// int matrix_memory_size = (d+d*(d+1)/2);
int d_position = i;
return d_position;
// return &T[matrix_id * matrix_memory_size + d_position]
}
__device__ void parallel_copy(float* src, float* dest, int n)
{
int i = threadIdx.x;
int stride = blockDim.x;
while(i<n){
dest[i] = src[i];
i += stride;
}
__syncthreads();
}
// __global__ void LDLt_max_col_k(float* AGPU, int d)
__global__ void LDLt_max_col_k(float* sA, int d)
{
int tidx = threadIdx.x%d;
int Qt = (threadIdx.x-tidx)/d;
int A_size = d*(d+1)/2+d;
int minTB = blockDim.x/d;
// printf("minTB %d\n", minTB);
int nt = (blockIdx.x*minTB + Qt) * A_size;
// int gbx = Qt + blockIdx.x*(blockDim.x/d);
// extern __shared__ float sA[];
// //copy ACPU to sA
// parallel_copy(sA, &AGPU[(blockIdx.x*minTB + Qt)*A_size], minTB*A_size);
// tidx==i
// Perform the LDLt factorization
int j, k;
for(j=0; j<d; j++){
// D_j,j :
if(tidx==0){
for(k=0; k<j; k++){
sA[nt+getDPierre(d, j)] -= sA[nt+getDPierre(d,k)]*
sA[nt+getLPierre(d,j,k)]*
sA[nt+getLPierre(d,j,k)];
}
}
__syncthreads();
// L_:,j parallel
if(tidx>j){
//printf("(%d,%d,%d,%d),", nt+getLPierre(d,tidx,j), nt, tidx, j);
sA[nt+getLPierre(d,tidx,j)] /= sA[nt+getDPierre(d,j)];
for(k=0; k<j; k++){
sA[nt+getLPierre(d,tidx,j)] -= sA[nt+getLPierre(d,tidx,k)]*
sA[nt+getLPierre(d,j,k)]*
sA[nt+getDPierre(d,k)]/
sA[nt+getDPierre(d,j)];
}
}
__syncthreads();
}
// parallel_copy(&AGPU[(blockIdx.x*minTB + Qt)*A_size], sA, minTB*A_size);
}
// __global__ void LDLt_max_row_k(float* AGPU, int d)
__global__ void LDLt_max_row_k(float* sA, int d)
{
int tidx = threadIdx.x%d;
int Qt = (threadIdx.x-tidx)/d;
int A_size = d*(d+1)/2+d;
int minTB = blockDim.x/d;
// printf("minTB %d\n", minTB);
int nt = (blockIdx.x*minTB + Qt) * A_size;
// int gbx = Qt + blockIdx.x*(blockDim.x/d);
// extern __shared__ float sA[];
// //copy ACPU to sA
// parallel_copy(sA, &AGPU[(blockIdx.x*minTB + Qt)*A_size], minTB*A_size);
// Perform the LDLt factorization
int i, k;
for(i=0; i<d; i++){
// D_i,i :
if(tidx==0){
for(k=0; k<i; k++){
sA[nt+getDPierre(d, i)] -= sA[nt+getDPierre(d,k)]*
sA[nt+getLPierre(d,i,k)]*
sA[nt+getLPierre(d,i,k)];
}
}
__syncthreads();
// L_i,: parallel
if(i<tidx){
//printf("(%d,%d,%d,%d),", nt+getLPierre(d,i,tidx), nt, i,tidx);
sA[nt+getLPierre(d,i,tidx)] /= sA[nt+getDPierre(d,i)];
for(k=0; k<i; k++){
sA[nt+getLPierre(d,i,tidx)] -= sA[nt+getLPierre(d,k,tidx)]*
sA[nt+getLPierre(d,k,i)]*
sA[nt+getDPierre(d,k)]/
sA[nt+getDPierre(d,i)];
}
}
__syncthreads();
}
// parallel_copy(&sA[(blockIdx.x*minTB + Qt)*A_size], A_host, minTB*A_size);
}
// __global__ void LDLt_max_row_k(float* AGPU, int d)
__global__ void LDLt_max_row_k_SHARED(float* A_host, int d)
{
int tidx = threadIdx.x%d;
int Qt = (threadIdx.x-tidx)/d;
int A_size = d*(d+1)/2+d;
int minTB = blockDim.x/d;
// printf("minTB %d\n", minTB);
int nt = Qt * A_size;
// int gbx = Qt + blockIdx.x*(blockDim.x/d);
extern __shared__ float sA[];
//copy ACPU to sA
parallel_copy(&A_host[blockIdx.x*minTB*A_size], sA, minTB*A_size);
// tidx==j
// Perform the LDLt factorization
int i, k;
for(i=0; i<d; i++){
// D_i,i :
if(tidx==0){
for(k=0; k<i; k++){
sA[nt+getDPierre(d, i)] -= sA[nt+getDPierre(d,k)]*
sA[nt+getLPierre(d,i,k)]*
sA[nt+getLPierre(d,i,k)];
}
}
__syncthreads();
// L_i,: parallel
if(i<tidx){
//printf("(%d,%d,%d,%d),", nt+getLPierre(d,i,tidx), nt, i,tidx);
sA[nt+getLPierre(d,i,tidx)] /= sA[nt+getDPierre(d,i)];
for(k=0; k<i; k++){
sA[nt+getLPierre(d,i,tidx)] -= sA[nt+getLPierre(d,k,tidx)]*
sA[nt+getLPierre(d,k,i)]*
sA[nt+getDPierre(d,k)]/
sA[nt+getDPierre(d,i)];
}
}
__syncthreads();
}
parallel_copy(sA, &A_host[blockIdx.x*minTB*A_size], minTB*A_size);
}
// ************************************************************************ // | .text
.file "LDLt.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z11hgetLPierreiii # -- Begin function _Z11hgetLPierreiii
.p2align 4, 0x90
.type _Z11hgetLPierreiii,@function
_Z11hgetLPierreiii: # @_Z11hgetLPierreiii
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
cmpl %esi, %edx
movl %esi, %ecx
cmovll %edx, %ecx
cmovgl %edx, %esi
leal 1(%rsi), %edx
imull %esi, %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
addl %ecx, %eax
retq
.Lfunc_end0:
.size _Z11hgetLPierreiii, .Lfunc_end0-_Z11hgetLPierreiii
.cfi_endproc
# -- End function
.globl _Z11hgetDPierrei # -- Begin function _Z11hgetDPierrei
.p2align 4, 0x90
.type _Z11hgetDPierrei,@function
_Z11hgetDPierrei: # @_Z11hgetDPierrei
.cfi_startproc
# %bb.0:
movl %edi, %eax
retq
.Lfunc_end1:
.size _Z11hgetDPierrei, .Lfunc_end1-_Z11hgetDPierrei
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z16generate_systemsPfS_iib
.LCPI2_0:
.long 0x3f800000 # float 1
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_1:
.quad 0x41dfffffffc00000 # double 2147483647
.text
.globl _Z16generate_systemsPfS_iib
.p2align 4, 0x90
.type _Z16generate_systemsPfS_iib,@function
_Z16generate_systemsPfS_iib: # @_Z16generate_systemsPfS_iib
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, 40(%rsp) # 8-byte Spill
testl %edx, %edx
jle .LBB2_12
# %bb.1: # %.lr.ph46
movl %ecx, %ebx
movq %rdi, %r15
leal 1(%rbx), %ecx
imull %ebx, %ecx
movl %ecx, %eax
shrl $31, %eax
movl %ecx, 20(%rsp) # 4-byte Spill
addl %ecx, %eax
sarl %eax
leal (%rax,%rbx), %ecx
movslq %ecx, %rsi
movslq %ebx, %rcx
movl %edx, %edx
movq %rdx, 64(%rsp) # 8-byte Spill
leaq (%rdi,%rcx,4), %r13
movl %eax, %ebp
movl %ecx, %r14d
movq %rsi, 32(%rsp) # 8-byte Spill
leaq (,%rsi,4), %rax
movq %rax, 48(%rsp) # 8-byte Spill
xorl %eax, %eax
movq %rax, 8(%rsp) # 8-byte Spill
movq %r13, 24(%rsp) # 8-byte Spill
xorl %eax, %eax
movq %rax, (%rsp) # 8-byte Spill
movq %rbp, 56(%rsp) # 8-byte Spill
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_11: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movq (%rsp), %rdx # 8-byte Reload
incq %rdx
movq 48(%rsp), %rax # 8-byte Reload
addq %rax, %r13
movq 8(%rsp), %rcx # 8-byte Reload
addl %ebx, %ecx
movq %rcx, 8(%rsp) # 8-byte Spill
addq %rax, %r15
movq %rdx, %rax
movq %rdx, (%rsp) # 8-byte Spill
cmpq 64(%rsp), %rdx # 8-byte Folded Reload
movq 56(%rsp), %rbp # 8-byte Reload
je .LBB2_12
.LBB2_2: # =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
# Child Loop BB2_7 Depth 2
# Child Loop BB2_10 Depth 2
cmpl $2, 20(%rsp) # 4-byte Folded Reload
jl .LBB2_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB2_2 Depth=1
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
addss .LCPI2_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LCPI2_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r13,%r12,4)
incq %r12
cmpq %r12, %rbp
jne .LBB2_4
.LBB2_5: # %.preheader38
# in Loop: Header=BB2_2 Depth=1
testl %ebx, %ebx
jle .LBB2_8
# %bb.6: # %.lr.ph41.preheader
# in Loop: Header=BB2_2 Depth=1
movq (%rsp), %rax # 8-byte Reload
imulq 32(%rsp), %rax # 8-byte Folded Reload
movq 24(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rax
movl $2, %ecx
xorl %edx, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_7: # %.lr.ph41
# Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %edx, %edi
shrl %edi
addq %rsi, %rdi
incq %rsi
movl $1065353216, (%rax,%rdi,4) # imm = 0x3F800000
addl %ecx, %edx
addl $2, %ecx
cmpl %esi, %ebx
jne .LBB2_7
.LBB2_8: # %.preheader
# in Loop: Header=BB2_2 Depth=1
testl %ebx, %ebx
jle .LBB2_11
# %bb.9: # %.lr.ph43
# in Loop: Header=BB2_2 Depth=1
movl 8(%rsp), %eax # 4-byte Reload
movq 40(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_10: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
addss .LCPI2_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LCPI2_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r15,%r12,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
addss .LCPI2_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LCPI2_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbp,%r12,4)
incq %r12
cmpq %r12, %r14
jne .LBB2_10
jmp .LBB2_11
.LBB2_12: # %._crit_edge47
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z16generate_systemsPfS_iib, .Lfunc_end2-_Z16generate_systemsPfS_iib
.cfi_endproc
# -- End function
.globl _Z29__device_stub__LDLt_max_col_kPfi # -- Begin function _Z29__device_stub__LDLt_max_col_kPfi
.p2align 4, 0x90
.type _Z29__device_stub__LDLt_max_col_kPfi,@function
_Z29__device_stub__LDLt_max_col_kPfi: # @_Z29__device_stub__LDLt_max_col_kPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14LDLt_max_col_kPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z29__device_stub__LDLt_max_col_kPfi, .Lfunc_end3-_Z29__device_stub__LDLt_max_col_kPfi
.cfi_endproc
# -- End function
.globl _Z29__device_stub__LDLt_max_row_kPfi # -- Begin function _Z29__device_stub__LDLt_max_row_kPfi
.p2align 4, 0x90
.type _Z29__device_stub__LDLt_max_row_kPfi,@function
_Z29__device_stub__LDLt_max_row_kPfi: # @_Z29__device_stub__LDLt_max_row_kPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14LDLt_max_row_kPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z29__device_stub__LDLt_max_row_kPfi, .Lfunc_end4-_Z29__device_stub__LDLt_max_row_kPfi
.cfi_endproc
# -- End function
.globl _Z36__device_stub__LDLt_max_row_k_SHAREDPfi # -- Begin function _Z36__device_stub__LDLt_max_row_k_SHAREDPfi
.p2align 4, 0x90
.type _Z36__device_stub__LDLt_max_row_k_SHAREDPfi,@function
_Z36__device_stub__LDLt_max_row_k_SHAREDPfi: # @_Z36__device_stub__LDLt_max_row_k_SHAREDPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z21LDLt_max_row_k_SHAREDPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end5:
.size _Z36__device_stub__LDLt_max_row_k_SHAREDPfi, .Lfunc_end5-_Z36__device_stub__LDLt_max_row_k_SHAREDPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14LDLt_max_col_kPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14LDLt_max_row_kPfi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21LDLt_max_row_k_SHAREDPfi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14LDLt_max_col_kPfi,@object # @_Z14LDLt_max_col_kPfi
.section .rodata,"a",@progbits
.globl _Z14LDLt_max_col_kPfi
.p2align 3, 0x0
_Z14LDLt_max_col_kPfi:
.quad _Z29__device_stub__LDLt_max_col_kPfi
.size _Z14LDLt_max_col_kPfi, 8
.type _Z14LDLt_max_row_kPfi,@object # @_Z14LDLt_max_row_kPfi
.globl _Z14LDLt_max_row_kPfi
.p2align 3, 0x0
_Z14LDLt_max_row_kPfi:
.quad _Z29__device_stub__LDLt_max_row_kPfi
.size _Z14LDLt_max_row_kPfi, 8
.type _Z21LDLt_max_row_k_SHAREDPfi,@object # @_Z21LDLt_max_row_k_SHAREDPfi
.globl _Z21LDLt_max_row_k_SHAREDPfi
.p2align 3, 0x0
_Z21LDLt_max_row_k_SHAREDPfi:
.quad _Z36__device_stub__LDLt_max_row_k_SHAREDPfi
.size _Z21LDLt_max_row_k_SHAREDPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14LDLt_max_col_kPfi"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z14LDLt_max_row_kPfi"
.size .L__unnamed_2, 22
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z21LDLt_max_row_k_SHAREDPfi"
.size .L__unnamed_3, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__LDLt_max_col_kPfi
.addrsig_sym _Z29__device_stub__LDLt_max_row_kPfi
.addrsig_sym _Z36__device_stub__LDLt_max_row_k_SHAREDPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14LDLt_max_col_kPfi
.addrsig_sym _Z14LDLt_max_row_kPfi
.addrsig_sym _Z21LDLt_max_row_k_SHAREDPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000476e6_00000000-6_LDLt.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3677:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3677:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11hgetLPierreiii
.type _Z11hgetLPierreiii, @function
_Z11hgetLPierreiii:
.LFB3669:
.cfi_startproc
endbr64
cmpl %esi, %edx
jg .L4
movl %edx, %eax
movl %esi, %edx
movl %eax, %esi
.L4:
leal 1(%rdx), %eax
imull %eax, %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
addl %esi, %eax
ret
.cfi_endproc
.LFE3669:
.size _Z11hgetLPierreiii, .-_Z11hgetLPierreiii
.globl _Z11hgetDPierrei
.type _Z11hgetDPierrei, @function
_Z11hgetDPierrei:
.LFB3670:
.cfi_startproc
endbr64
movl %edi, %eax
ret
.cfi_endproc
.LFE3670:
.size _Z11hgetDPierrei, .-_Z11hgetDPierrei
.globl _Z16generate_systemsPfS_iib
.type _Z16generate_systemsPfS_iib, @function
_Z16generate_systemsPfS_iib:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rsi, 48(%rsp)
movl %edx, %esi
movl %ecx, %ebp
leal 1(%rcx), %edx
imull %ecx, %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
leal (%rax,%rcx), %ecx
testl %esi, %esi
jle .L6
movl %eax, %r14d
movslq %ecx, %rcx
leaq 0(,%rcx,4), %rax
movq %rax, 24(%rsp)
movslq %ebp, %r8
leaq (%rdi,%r8,4), %r12
movl $0, 20(%rsp)
movq $0, 8(%rsp)
movl $0, 16(%rsp)
movl .LC0(%rip), %r13d
movl %edx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %rdi, 56(%rsp)
movl %esi, 44(%rsp)
.L13:
movq %r12, %r15
cmpl $1, 40(%rsp)
jle .L8
movl $0, %ebx
.L9:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addss .LC0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LC1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r15,%rbx,4)
addq $1, %rbx
cmpl %ebx, %r14d
jg .L9
.L8:
testl %ebp, %ebp
jle .L10
movl $0, %ebx
.L11:
movl %ebx, %edx
movl %ebx, %esi
movl %ebp, %edi
call _Z11hgetLPierreiii
cltq
movl %r13d, (%r15,%rax,4)
addl $1, %ebx
cmpl %ebx, %ebp
jne .L11
movq 56(%rsp), %rax
movq 8(%rsp), %rcx
leaq (%rax,%rcx,4), %rbx
movslq 20(%rsp), %rax
movq 48(%rsp), %rdx
leaq (%rdx,%rax,4), %r15
.L12:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addss .LC0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LC1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addss .LC0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LC1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r15)
addq $4, %rbx
addq $4, %r15
cmpq %r12, %rbx
jne .L12
.L10:
addl $1, 16(%rsp)
movl 16(%rsp), %eax
movq 24(%rsp), %rcx
addq %rcx, %r12
movq 32(%rsp), %rdi
addq %rdi, 8(%rsp)
addl %ebp, 20(%rsp)
cmpl %eax, 44(%rsp)
jne .L13
.L6:
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size _Z16generate_systemsPfS_iib, .-_Z16generate_systemsPfS_iib
.globl _Z10getLPierreiii
.type _Z10getLPierreiii, @function
_Z10getLPierreiii:
.LFB3672:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3672:
.size _Z10getLPierreiii, .-_Z10getLPierreiii
.globl _Z10getDPierreii
.type _Z10getDPierreii, @function
_Z10getDPierreii:
.LFB3673:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3673:
.size _Z10getDPierreii, .-_Z10getDPierreii
.globl _Z13parallel_copyPfS_i
.type _Z13parallel_copyPfS_i, @function
_Z13parallel_copyPfS_i:
.LFB3674:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3674:
.size _Z13parallel_copyPfS_i, .-_Z13parallel_copyPfS_i
.globl _Z35__device_stub__Z14LDLt_max_col_kPfiPfi
.type _Z35__device_stub__Z14LDLt_max_col_kPfiPfi, @function
_Z35__device_stub__Z14LDLt_max_col_kPfiPfi:
.LFB3699:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14LDLt_max_col_kPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z35__device_stub__Z14LDLt_max_col_kPfiPfi, .-_Z35__device_stub__Z14LDLt_max_col_kPfiPfi
.globl _Z14LDLt_max_col_kPfi
.type _Z14LDLt_max_col_kPfi, @function
_Z14LDLt_max_col_kPfi:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z14LDLt_max_col_kPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z14LDLt_max_col_kPfi, .-_Z14LDLt_max_col_kPfi
.globl _Z35__device_stub__Z14LDLt_max_row_kPfiPfi
.type _Z35__device_stub__Z14LDLt_max_row_kPfiPfi, @function
_Z35__device_stub__Z14LDLt_max_row_kPfiPfi:
.LFB3701:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14LDLt_max_row_kPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _Z35__device_stub__Z14LDLt_max_row_kPfiPfi, .-_Z35__device_stub__Z14LDLt_max_row_kPfiPfi
.globl _Z14LDLt_max_row_kPfi
.type _Z14LDLt_max_row_kPfi, @function
_Z14LDLt_max_row_kPfi:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z14LDLt_max_row_kPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _Z14LDLt_max_row_kPfi, .-_Z14LDLt_max_row_kPfi
.globl _Z42__device_stub__Z21LDLt_max_row_k_SHAREDPfiPfi
.type _Z42__device_stub__Z21LDLt_max_row_k_SHAREDPfiPfi, @function
_Z42__device_stub__Z21LDLt_max_row_k_SHAREDPfiPfi:
.LFB3703:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z21LDLt_max_row_k_SHAREDPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3703:
.size _Z42__device_stub__Z21LDLt_max_row_k_SHAREDPfiPfi, .-_Z42__device_stub__Z21LDLt_max_row_k_SHAREDPfiPfi
.globl _Z21LDLt_max_row_k_SHAREDPfi
.type _Z21LDLt_max_row_k_SHAREDPfi, @function
_Z21LDLt_max_row_k_SHAREDPfi:
.LFB3704:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z21LDLt_max_row_k_SHAREDPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _Z21LDLt_max_row_k_SHAREDPfi, .-_Z21LDLt_max_row_k_SHAREDPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z21LDLt_max_row_k_SHAREDPfi"
.LC3:
.string "_Z14LDLt_max_row_kPfi"
.LC4:
.string "_Z14LDLt_max_col_kPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3706:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z21LDLt_max_row_k_SHAREDPfi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z14LDLt_max_row_kPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z14LDLt_max_col_kPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3706:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -4194304
.long 1105199103
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "LDLt.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z11hgetLPierreiii # -- Begin function _Z11hgetLPierreiii
.p2align 4, 0x90
.type _Z11hgetLPierreiii,@function
_Z11hgetLPierreiii: # @_Z11hgetLPierreiii
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
cmpl %esi, %edx
movl %esi, %ecx
cmovll %edx, %ecx
cmovgl %edx, %esi
leal 1(%rsi), %edx
imull %esi, %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
addl %ecx, %eax
retq
.Lfunc_end0:
.size _Z11hgetLPierreiii, .Lfunc_end0-_Z11hgetLPierreiii
.cfi_endproc
# -- End function
.globl _Z11hgetDPierrei # -- Begin function _Z11hgetDPierrei
.p2align 4, 0x90
.type _Z11hgetDPierrei,@function
_Z11hgetDPierrei: # @_Z11hgetDPierrei
.cfi_startproc
# %bb.0:
movl %edi, %eax
retq
.Lfunc_end1:
.size _Z11hgetDPierrei, .Lfunc_end1-_Z11hgetDPierrei
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z16generate_systemsPfS_iib
.LCPI2_0:
.long 0x3f800000 # float 1
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_1:
.quad 0x41dfffffffc00000 # double 2147483647
.text
.globl _Z16generate_systemsPfS_iib
.p2align 4, 0x90
.type _Z16generate_systemsPfS_iib,@function
_Z16generate_systemsPfS_iib: # @_Z16generate_systemsPfS_iib
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, 40(%rsp) # 8-byte Spill
testl %edx, %edx
jle .LBB2_12
# %bb.1: # %.lr.ph46
movl %ecx, %ebx
movq %rdi, %r15
leal 1(%rbx), %ecx
imull %ebx, %ecx
movl %ecx, %eax
shrl $31, %eax
movl %ecx, 20(%rsp) # 4-byte Spill
addl %ecx, %eax
sarl %eax
leal (%rax,%rbx), %ecx
movslq %ecx, %rsi
movslq %ebx, %rcx
movl %edx, %edx
movq %rdx, 64(%rsp) # 8-byte Spill
leaq (%rdi,%rcx,4), %r13
movl %eax, %ebp
movl %ecx, %r14d
movq %rsi, 32(%rsp) # 8-byte Spill
leaq (,%rsi,4), %rax
movq %rax, 48(%rsp) # 8-byte Spill
xorl %eax, %eax
movq %rax, 8(%rsp) # 8-byte Spill
movq %r13, 24(%rsp) # 8-byte Spill
xorl %eax, %eax
movq %rax, (%rsp) # 8-byte Spill
movq %rbp, 56(%rsp) # 8-byte Spill
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_11: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movq (%rsp), %rdx # 8-byte Reload
incq %rdx
movq 48(%rsp), %rax # 8-byte Reload
addq %rax, %r13
movq 8(%rsp), %rcx # 8-byte Reload
addl %ebx, %ecx
movq %rcx, 8(%rsp) # 8-byte Spill
addq %rax, %r15
movq %rdx, %rax
movq %rdx, (%rsp) # 8-byte Spill
cmpq 64(%rsp), %rdx # 8-byte Folded Reload
movq 56(%rsp), %rbp # 8-byte Reload
je .LBB2_12
.LBB2_2: # =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
# Child Loop BB2_7 Depth 2
# Child Loop BB2_10 Depth 2
cmpl $2, 20(%rsp) # 4-byte Folded Reload
jl .LBB2_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB2_2 Depth=1
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
addss .LCPI2_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LCPI2_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r13,%r12,4)
incq %r12
cmpq %r12, %rbp
jne .LBB2_4
.LBB2_5: # %.preheader38
# in Loop: Header=BB2_2 Depth=1
testl %ebx, %ebx
jle .LBB2_8
# %bb.6: # %.lr.ph41.preheader
# in Loop: Header=BB2_2 Depth=1
movq (%rsp), %rax # 8-byte Reload
imulq 32(%rsp), %rax # 8-byte Folded Reload
movq 24(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rax
movl $2, %ecx
xorl %edx, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_7: # %.lr.ph41
# Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %edx, %edi
shrl %edi
addq %rsi, %rdi
incq %rsi
movl $1065353216, (%rax,%rdi,4) # imm = 0x3F800000
addl %ecx, %edx
addl $2, %ecx
cmpl %esi, %ebx
jne .LBB2_7
.LBB2_8: # %.preheader
# in Loop: Header=BB2_2 Depth=1
testl %ebx, %ebx
jle .LBB2_11
# %bb.9: # %.lr.ph43
# in Loop: Header=BB2_2 Depth=1
movl 8(%rsp), %eax # 4-byte Reload
movq 40(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_10: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
addss .LCPI2_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LCPI2_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r15,%r12,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
addss .LCPI2_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LCPI2_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbp,%r12,4)
incq %r12
cmpq %r12, %r14
jne .LBB2_10
jmp .LBB2_11
.LBB2_12: # %._crit_edge47
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z16generate_systemsPfS_iib, .Lfunc_end2-_Z16generate_systemsPfS_iib
.cfi_endproc
# -- End function
.globl _Z29__device_stub__LDLt_max_col_kPfi # -- Begin function _Z29__device_stub__LDLt_max_col_kPfi
.p2align 4, 0x90
.type _Z29__device_stub__LDLt_max_col_kPfi,@function
_Z29__device_stub__LDLt_max_col_kPfi: # @_Z29__device_stub__LDLt_max_col_kPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14LDLt_max_col_kPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z29__device_stub__LDLt_max_col_kPfi, .Lfunc_end3-_Z29__device_stub__LDLt_max_col_kPfi
.cfi_endproc
# -- End function
.globl _Z29__device_stub__LDLt_max_row_kPfi # -- Begin function _Z29__device_stub__LDLt_max_row_kPfi
.p2align 4, 0x90
.type _Z29__device_stub__LDLt_max_row_kPfi,@function
_Z29__device_stub__LDLt_max_row_kPfi: # @_Z29__device_stub__LDLt_max_row_kPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14LDLt_max_row_kPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z29__device_stub__LDLt_max_row_kPfi, .Lfunc_end4-_Z29__device_stub__LDLt_max_row_kPfi
.cfi_endproc
# -- End function
.globl _Z36__device_stub__LDLt_max_row_k_SHAREDPfi # -- Begin function _Z36__device_stub__LDLt_max_row_k_SHAREDPfi
.p2align 4, 0x90
.type _Z36__device_stub__LDLt_max_row_k_SHAREDPfi,@function
_Z36__device_stub__LDLt_max_row_k_SHAREDPfi: # @_Z36__device_stub__LDLt_max_row_k_SHAREDPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z21LDLt_max_row_k_SHAREDPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end5:
.size _Z36__device_stub__LDLt_max_row_k_SHAREDPfi, .Lfunc_end5-_Z36__device_stub__LDLt_max_row_k_SHAREDPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14LDLt_max_col_kPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14LDLt_max_row_kPfi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21LDLt_max_row_k_SHAREDPfi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14LDLt_max_col_kPfi,@object # @_Z14LDLt_max_col_kPfi
.section .rodata,"a",@progbits
.globl _Z14LDLt_max_col_kPfi
.p2align 3, 0x0
_Z14LDLt_max_col_kPfi:
.quad _Z29__device_stub__LDLt_max_col_kPfi
.size _Z14LDLt_max_col_kPfi, 8
.type _Z14LDLt_max_row_kPfi,@object # @_Z14LDLt_max_row_kPfi
.globl _Z14LDLt_max_row_kPfi
.p2align 3, 0x0
_Z14LDLt_max_row_kPfi:
.quad _Z29__device_stub__LDLt_max_row_kPfi
.size _Z14LDLt_max_row_kPfi, 8
.type _Z21LDLt_max_row_k_SHAREDPfi,@object # @_Z21LDLt_max_row_k_SHAREDPfi
.globl _Z21LDLt_max_row_k_SHAREDPfi
.p2align 3, 0x0
_Z21LDLt_max_row_k_SHAREDPfi:
.quad _Z36__device_stub__LDLt_max_row_k_SHAREDPfi
.size _Z21LDLt_max_row_k_SHAREDPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14LDLt_max_col_kPfi"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z14LDLt_max_row_kPfi"
.size .L__unnamed_2, 22
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z21LDLt_max_row_k_SHAREDPfi"
.size .L__unnamed_3, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__LDLt_max_col_kPfi
.addrsig_sym _Z29__device_stub__LDLt_max_row_kPfi
.addrsig_sym _Z36__device_stub__LDLt_max_row_k_SHAREDPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14LDLt_max_col_kPfi
.addrsig_sym _Z14LDLt_max_row_kPfi
.addrsig_sym _Z21LDLt_max_row_k_SHAREDPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void ZeroMeanImpl(float* solutions, int rowSize, int matCount) {
const int matricesPerBlock = BLOCK_SIZE / rowSize;
const int matrixIdx = blockIdx.x * matricesPerBlock + threadIdx.x / rowSize;
const int tid = threadIdx.x;
const int col = threadIdx.x & (rowSize - 1);
const int inBlockOffset = threadIdx.x / rowSize;
__shared__ double beta[BLOCK_SIZE];
__shared__ double line[BLOCK_SIZE];
if (matrixIdx >= matCount) {
return;
}
solutions += matrixIdx * rowSize;
beta[tid] = col != (rowSize - 1) ? solutions[col] : 0;
line[tid] = beta[tid];
__syncthreads();
for (int s = rowSize >> 1; s > 0; s >>= 1) {
if (col < s) {
line[tid] += line[tid + s];
}
__syncthreads();
}
beta[tid] -= line[rowSize * inBlockOffset] / rowSize;
solutions[col] = beta[tid];
} | code for sm_80
Function : _Z12ZeroMeanImplPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R9, c[0x0][0x168] ; /* 0x00005a0000097a13 */
/* 0x000fe20000000000 */
/*0020*/ I2F.U32.RP R7, c[0x0][0x168] ; /* 0x00005a0000077b06 */
/* 0x000e220000209000 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0040*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000eac0000002500 */
/*0050*/ I2F.RP R6, R9 ; /* 0x0000000900067306 */
/* 0x000ef00000209400 */
/*0060*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e300000001000 */
/*0070*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x008ee20000001000 */
/*0080*/ IADD3 R4, R7, 0xffffffe, RZ ; /* 0x0ffffffe07047810 */
/* 0x001fce0007ffe0ff */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000122000021f000 */
/*00a0*/ IADD3 R2, R6, 0xffffffe, RZ ; /* 0x0ffffffe06027810 */
/* 0x008fce0007ffe0ff */
/*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000762000021f000 */
/*00c0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*00d0*/ IMAD.MOV R6, RZ, RZ, -R5 ; /* 0x000000ffff067224 */
/* 0x010fe400078e0a05 */
/*00e0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x008fe400078e00ff */
/*00f0*/ IMAD R7, R6, c[0x0][0x168], RZ ; /* 0x00005a0006077a24 */
/* 0x000fe400078e02ff */
/*0100*/ IMAD.MOV R8, RZ, RZ, -R3 ; /* 0x000000ffff087224 */
/* 0x020fe400078e0a03 */
/*0110*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fc800078e0004 */
/*0120*/ IMAD R11, R8, R9, RZ ; /* 0x00000009080b7224 */
/* 0x000fe400078e02ff */
/*0130*/ IMAD.HI.U32 R5, R5, R0, RZ ; /* 0x0000000005057227 */
/* 0x002fc800078e00ff */
/*0140*/ IMAD.HI.U32 R3, R3, R11, R2 ; /* 0x0000000b03037227 */
/* 0x000fc800078e0002 */
/*0150*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0a05 */
/*0160*/ IMAD.HI.U32 R3, R3, 0x3e8, RZ ; /* 0x000003e803037827 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R2, RZ, RZ, -R3 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0a03 */
/*0180*/ IMAD R4, R7, c[0x0][0x168], R0 ; /* 0x00005a0007047a24 */
/* 0x000fe400078e0200 */
/*0190*/ IMAD R2, R9.reuse, R2, 0x3e8 ; /* 0x000003e809027424 */
/* 0x040fe400078e0202 */
/*01a0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0b7624 */
/* 0x000fe200078e00ff */
/*01b0*/ ISETP.GE.U32.AND P2, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fe40003f46070 */
/*01c0*/ ISETP.GT.U32.AND P4, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fd60003f84070 */
/*01d0*/ @P2 IADD3 R4, R4, -c[0x0][0x168], RZ ; /* 0x80005a0004042a10 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P4 IMAD.IADD R2, R2, 0x1, -R9 ; /* 0x000000010202c824 */
/* 0x000fe200078e0a09 */
/*01f0*/ @!P4 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303c810 */
/* 0x000fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fe40003f26070 */
/*0210*/ ISETP.GE.U32.AND P3, PT, R2, R9, PT ; /* 0x000000090200720c */
/* 0x000fe40003f66070 */
/*0220*/ LOP3.LUT R2, R11, 0x3e8, RZ, 0x3c, !PT ; /* 0x000003e80b027812 */
/* 0x000fe400078e3cff */
/*0230*/ @P2 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105052810 */
/* 0x000fc40007ffe0ff */
/*0240*/ ISETP.GE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f06270 */
/*0250*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe40003f45070 */
/*0260*/ LOP3.LUT R2, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff027a12 */
/* 0x000fe400078e33ff */
/*0270*/ @P1 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105051810 */
/* 0x000fe40007ffe0ff */
/*0280*/ @P3 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103033810 */
/* 0x000fe40007ffe0ff */
/*0290*/ ISETP.NE.AND P3, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fc40003f65270 */
/*02a0*/ SEL R5, R2, R5, !P2 ; /* 0x0000000502057207 */
/* 0x000fe20005000000 */
/*02b0*/ @!P0 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff038224 */
/* 0x000fca00078e0a03 */
/*02c0*/ SEL R2, R2, R3, !P3 ; /* 0x0000000302027207 */
/* 0x000fca0005800000 */
/*02d0*/ IMAD R5, R2, UR4, R5 ; /* 0x0000000402057c24 */
/* 0x004fca000f8e0205 */
/*02e0*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x16c], PT ; /* 0x00005b0005007a0c */
/* 0x000fda0003f06270 */
/*02f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0300*/ IADD3 R3, R11, -0x1, RZ ; /* 0xffffffff0b037810 */
/* 0x000fe20007ffe0ff */
/*0310*/ IMAD R5, R5, c[0x0][0x168], RZ ; /* 0x00005a0005057a24 */
/* 0x000fe200078e02ff */
/*0320*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0330*/ LOP3.LUT R2, R3, R0, RZ, 0xc0, !PT ; /* 0x0000000003027212 */
/* 0x000fc800078ec0ff */
/*0340*/ SHF.R.S32.HI R4, RZ, 0x1f, R2 ; /* 0x0000001fff047819 */
/* 0x000fe40000011402 */
/*0350*/ IADD3 R6, P1, R2.reuse, R5, RZ ; /* 0x0000000502067210 */
/* 0x040fe40007f3e0ff */
/*0360*/ ISETP.NE.AND P0, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fe40003f05270 */
/*0370*/ LEA.HI.X.SX32 R5, R5, R4, 0x1, P1 ; /* 0x0000000405057211 */
/* 0x000fe400008f0eff */
/*0380*/ LEA R4, P1, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006047a11 */
/* 0x000fc800078210ff */
/*0390*/ LEA.HI.X R5, R6, c[0x0][0x164], R5, 0x2, P1 ; /* 0x0000590006057a11 */
/* 0x000fca00008f1405 */
/*03a0*/ @P0 LDG.E R10, [R4.64] ; /* 0x00000004040a0981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ I2F.U32.RP R3, c[0x0][0x168] ; /* 0x00005a0000037b06 */
/* 0x000e220000209000 */
/*03c0*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fce0003f45070 */
/*03d0*/ MUFU.RCP R3, R3 ; /* 0x0000000300037308 */
/* 0x001e240000001000 */
/*03e0*/ IADD3 R6, R3, 0xffffffe, RZ ; /* 0x0ffffffe03067810 */
/* 0x001fcc0007ffe0ff */
/*03f0*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0400*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0410*/ IMAD.MOV R9, RZ, RZ, -R7 ; /* 0x000000ffff097224 */
/* 0x002fc800078e0a07 */
/*0420*/ IMAD R9, R9, c[0x0][0x168], RZ ; /* 0x00005a0009097a24 */
/* 0x000fc800078e02ff */
/*0430*/ IMAD.HI.U32 R9, R7, R9, R6 ; /* 0x0000000907097227 */
/* 0x000fe400078e0006 */
/*0440*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fc8000001ff00 */
/*0450*/ IMAD.HI.U32 R9, R9, R0, RZ ; /* 0x0000000009097227 */
/* 0x000fc800078e00ff */
/*0460*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fc800078e0a09 */
/*0470*/ IMAD R13, R9, c[0x0][0x168], R0 ; /* 0x00005a00090d7a24 */
/* 0x000fe400078e0200 */
/*0480*/ I2F.F64 R8, c[0x0][0x168] ; /* 0x00005a0000087b12 */
/* 0x000e260000201c00 */
/*0490*/ ISETP.GE.U32.AND P1, PT, R13, c[0x0][0x168], PT ; /* 0x00005a000d007a0c */
/* 0x000fda0003f26070 */
/*04a0*/ @P1 IADD3 R13, R13, -c[0x0][0x168], RZ ; /* 0x80005a000d0d1a10 */
/* 0x000fe20007ffe0ff */
/*04b0*/ MUFU.RCP64H R3, R9 ; /* 0x0000000900037308 */
/* 0x0010660000001800 */
/*04c0*/ ISETP.GE.U32.AND P1, PT, R13, c[0x0][0x168], PT ; /* 0x00005a000d007a0c */
/* 0x000fda0003f26070 */
/*04d0*/ @P1 IADD3 R13, R13, -c[0x0][0x168], RZ ; /* 0x80005a000d0d1a10 */
/* 0x000fe40007ffe0ff */
/*04e0*/ @!P2 LOP3.LUT R13, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff0daa12 */
/* 0x000fca00078e33ff */
/*04f0*/ IMAD.IADD R14, R0, 0x1, -R13 ; /* 0x00000001000e7824 */
/* 0x000fe200078e0a0d */
/*0500*/ @P0 F2F.F64.F32 R6, R10 ; /* 0x0000000a00060310 */
/* 0x004ea20000201800 */
/*0510*/ ISETP.GE.AND P0, PT, R11, 0x2, PT ; /* 0x000000020b00780c */
/* 0x000fe20003f06270 */
/*0520*/ STS.64 [R0.X8], R6 ; /* 0x0000000600007388 */
/* 0x0041e80000008a00 */
/*0530*/ STS.64 [R0.X8+0x1f40], R6 ; /* 0x001f400600007388 */
/* 0x0001e80000008a00 */
/*0540*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0550*/ @!P0 BRA 0x640 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0560*/ IMAD.SHL.U32 R6, R0, 0x8, RZ ; /* 0x0000000800067824 */
/* 0x003fe400078e00ff */
/*0570*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0d7624 */
/* 0x000fc600078e00ff */
/*0580*/ IADD3 R12, R6, 0x1f40, RZ ; /* 0x00001f40060c7810 */
/* 0x000fe40007ffe0ff */
/*0590*/ SHF.R.S32.HI R15, RZ, 0x1, R13 ; /* 0x00000001ff0f7819 */
/* 0x000fc8000001140d */
/*05a0*/ ISETP.GE.AND P0, PT, R2, R15, PT ; /* 0x0000000f0200720c */
/* 0x000fda0003f06270 */
/*05b0*/ @!P0 IMAD R10, R15, 0x8, R12 ; /* 0x000000080f0a8824 */
/* 0x000fe200078e020c */
/*05c0*/ @!P0 LDS.64 R6, [R0.X8+0x1f40] ; /* 0x001f400000068984 */
/* 0x000fea0000008a00 */
/*05d0*/ @!P0 LDS.64 R10, [R10] ; /* 0x000000000a0a8984 */
/* 0x000e240000000a00 */
/*05e0*/ @!P0 DADD R6, R6, R10 ; /* 0x0000000006068229 */
/* 0x001e0e000000000a */
/*05f0*/ @!P0 STS.64 [R0.X8+0x1f40], R6 ; /* 0x001f400600008388 */
/* 0x0011e80000008a00 */
/*0600*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0610*/ ISETP.GT.AND P0, PT, R13, 0x3, PT ; /* 0x000000030d00780c */
/* 0x000fe20003f04270 */
/*0620*/ IMAD.MOV.U32 R13, RZ, RZ, R15 ; /* 0x000000ffff0d7224 */
/* 0x000fd800078e000f */
/*0630*/ @P0 BRA 0x590 ; /* 0xffffff5000000947 */
/* 0x001fea000383ffff */
/*0640*/ LDS.64 R6, [R14.X8+0x1f40] ; /* 0x001f40000e067984 */
/* 0x003e220000008a00 */
/*0650*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fe200078e00ff */
/*0660*/ BSSY B0, 0x760 ; /* 0x000000f000007945 */
/* 0x000fea0003800000 */
/*0670*/ DFMA R10, -R8, R2, 1 ; /* 0x3ff00000080a742b */
/* 0x000e4c0000000102 */
/*0680*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x002e4c000000000a */
/*0690*/ DFMA R10, R2, R10, R2 ; /* 0x0000000a020a722b */
/* 0x002e4c0000000002 */
/*06a0*/ DFMA R2, -R8, R10, 1 ; /* 0x3ff000000802742b */
/* 0x002e4c000000010a */
/*06b0*/ DFMA R2, R10, R2, R10 ; /* 0x000000020a02722b */
/* 0x002e0c000000000a */
/*06c0*/ DMUL R10, R6, R2 ; /* 0x00000002060a7228 */
/* 0x001e220000000000 */
/*06d0*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fca0003f2e200 */
/*06e0*/ DFMA R12, -R8, R10, R6 ; /* 0x0000000a080c722b */
/* 0x001e0c0000000106 */
/*06f0*/ DFMA R2, R2, R12, R10 ; /* 0x0000000c0202722b */
/* 0x001e14000000000a */
/*0700*/ FFMA R10, RZ, R9, R3 ; /* 0x00000009ff0a7223 */
/* 0x001fca0000000003 */
/*0710*/ FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ; /* 0x001000000a00780b */
/* 0x000fda0003f04200 */
/*0720*/ @P0 BRA P1, 0x750 ; /* 0x0000002000000947 */
/* 0x000fea0000800000 */
/*0730*/ MOV R12, 0x750 ; /* 0x00000750000c7802 */
/* 0x000fe40000000f00 */
/*0740*/ CALL.REL.NOINC 0x7c0 ; /* 0x0000007000007944 */
/* 0x000fea0003c00000 */
/*0750*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0760*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e240000008a00 */
/*0770*/ DADD R6, R6, -R2 ; /* 0x0000000006067229 */
/* 0x001e0c0000000802 */
/*0780*/ F2F.F32.F64 R3, R6 ; /* 0x0000000600037310 */
/* 0x001e220000301000 */
/*0790*/ STS.64 [R0.X8], R6 ; /* 0x0000000600007388 */
/* 0x000fe80000008a00 */
/*07a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x001fe2000c101904 */
/*07b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07c0*/ FSETP.GEU.AND P0, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f0e200 */
/*07d0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0e7424 */
/* 0x000fe200078e00ff */
/*07e0*/ LOP3.LUT R2, R9, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff09027812 */
/* 0x000fe200078ec0ff */
/*07f0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*0800*/ FSETP.GEU.AND P2, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f4e200 */
/*0810*/ BSSY B1, 0xd60 ; /* 0x0000054000017945 */
/* 0x000fe20003800000 */
/*0820*/ LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000002037812 */
/* 0x000fe200078efcff */
/*0830*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0008 */
/*0840*/ LOP3.LUT R13, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000070d7812 */
/* 0x000fc400078ec0ff */
/*0850*/ LOP3.LUT R18, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009127812 */
/* 0x000fc600078ec0ff */
/*0860*/ @!P0 DMUL R2, R8, 8.98846567431157953865e+307 ; /* 0x7fe0000008028828 */
/* 0x000e220000000000 */
/*0870*/ ISETP.GE.U32.AND P1, PT, R13, R18, PT ; /* 0x000000120d00720c */
/* 0x000fc60003f26070 */
/*0880*/ @!P2 LOP3.LUT R10, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090aa812 */
/* 0x000fe200078ec0ff */
/*0890*/ @!P2 IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff16a224 */
/* 0x000fe200078e00ff */
/*08a0*/ MUFU.RCP64H R17, R3 ; /* 0x0000000300117308 */
/* 0x001e220000001800 */
/*08b0*/ SEL R11, R14.reuse, 0x63400000, !P1 ; /* 0x634000000e0b7807 */
/* 0x040fe40004800000 */
/*08c0*/ @!P2 ISETP.GE.U32.AND P3, PT, R13, R10, PT ; /* 0x0000000a0d00a20c */
/* 0x000fe20003f66070 */
/*08d0*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0006 */
/*08e0*/ LOP3.LUT R11, R11, 0x800fffff, R7, 0xf8, !PT ; /* 0x800fffff0b0b7812 */
/* 0x000fe400078ef807 */
/*08f0*/ @!P2 SEL R15, R14, 0x63400000, !P3 ; /* 0x634000000e0fa807 */
/* 0x000fc80005800000 */
/*0900*/ @!P2 LOP3.LUT R15, R15, 0x80000000, R7, 0xf8, !PT ; /* 0x800000000f0fa812 */
/* 0x000fc800078ef807 */
/*0910*/ @!P2 LOP3.LUT R23, R15, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000f17a812 */
/* 0x000fe200078efcff */
/*0920*/ DFMA R20, R16, -R2, 1 ; /* 0x3ff000001014742b */
/* 0x001e220000000802 */
/*0930*/ IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e000d */
/*0940*/ @!P2 DFMA R10, R10, 2, -R22 ; /* 0x400000000a0aa82b */
/* 0x0003e40000000816 */
/*0950*/ IMAD.MOV.U32 R22, RZ, RZ, R18 ; /* 0x000000ffff167224 */
/* 0x002fe200078e0012 */
/*0960*/ @!P0 LOP3.LUT R22, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003168812 */
/* 0x000fe200078ec0ff */
/*0970*/ DFMA R20, R20, R20, R20 ; /* 0x000000141414722b */
/* 0x001e060000000014 */
/*0980*/ IADD3 R23, R22, -0x1, RZ ; /* 0xffffffff16177810 */
/* 0x000fc60007ffe0ff */
/*0990*/ DFMA R16, R16, R20, R16 ; /* 0x000000141010722b */
/* 0x001e220000000010 */
/*09a0*/ @!P2 LOP3.LUT R15, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b0fa812 */
/* 0x000fca00078ec0ff */
/*09b0*/ DFMA R20, R16, -R2, 1 ; /* 0x3ff000001014742b */
/* 0x001e0c0000000802 */
/*09c0*/ DFMA R16, R16, R20, R16 ; /* 0x000000141010722b */
/* 0x0010640000000010 */
/*09d0*/ IADD3 R20, R15, -0x1, RZ ; /* 0xffffffff0f147810 */
/* 0x001fc80007ffe0ff */
/*09e0*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fe20003f04070 */
/*09f0*/ DMUL R18, R16, R10 ; /* 0x0000000a10127228 */
/* 0x002e060000000000 */
/*0a00*/ ISETP.GT.U32.OR P0, PT, R23, 0x7feffffe, P0 ; /* 0x7feffffe1700780c */
/* 0x000fc60000704470 */
/*0a10*/ DFMA R20, R18, -R2, R10 ; /* 0x800000021214722b */
/* 0x001e0c000000000a */
/*0a20*/ DFMA R16, R16, R20, R18 ; /* 0x000000141010722b */
/* 0x0010480000000012 */
/*0a30*/ @P0 BRA 0xc00 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0a40*/ LOP3.LUT R18, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009127812 */
/* 0x003fc800078ec0ff */
/*0a50*/ ISETP.GE.U32.AND P0, PT, R13.reuse, R18, PT ; /* 0x000000120d00720c */
/* 0x040fe20003f06070 */
/*0a60*/ IMAD.IADD R6, R13, 0x1, -R18 ; /* 0x000000010d067824 */
/* 0x000fc600078e0a12 */
/*0a70*/ SEL R13, R14, 0x63400000, !P0 ; /* 0x634000000e0d7807 */
/* 0x000fe40004000000 */
/*0a80*/ IMNMX R6, R6, -0x46a00000, !PT ; /* 0xb960000006067817 */
/* 0x000fc80007800200 */
/*0a90*/ IMNMX R6, R6, 0x46a00000, PT ; /* 0x46a0000006067817 */
/* 0x000fca0003800200 */
/*0aa0*/ IMAD.IADD R13, R6, 0x1, -R13 ; /* 0x00000001060d7824 */
/* 0x000fe400078e0a0d */
/*0ab0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*0ac0*/ IADD3 R7, R13, 0x7fe00000, RZ ; /* 0x7fe000000d077810 */
/* 0x000fcc0007ffe0ff */
/*0ad0*/ DMUL R18, R16, R6 ; /* 0x0000000610127228 */
/* 0x000e140000000000 */
/*0ae0*/ FSETP.GTU.AND P0, PT, |R19|, 1.469367938527859385e-39, PT ; /* 0x001000001300780b */
/* 0x001fda0003f0c200 */
/*0af0*/ @P0 BRA 0xd50 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0b00*/ DFMA R2, R16, -R2, R10 ; /* 0x800000021002722b */
/* 0x000e22000000000a */
/*0b10*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fd200078e00ff */
/*0b20*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*0b30*/ LOP3.LUT R9, R3, 0x80000000, R9, 0x48, !PT ; /* 0x8000000003097812 */
/* 0x000fc800078e4809 */
/*0b40*/ LOP3.LUT R7, R9, R7, RZ, 0xfc, !PT ; /* 0x0000000709077212 */
/* 0x000fce00078efcff */
/*0b50*/ @!P0 BRA 0xd50 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0b60*/ IMAD.MOV R3, RZ, RZ, -R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0d */
/*0b70*/ DMUL.RP R6, R16, R6 ; /* 0x0000000610067228 */
/* 0x000e220000008000 */
/*0b80*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*0b90*/ IADD3 R13, -R13, -0x43300000, RZ ; /* 0xbcd000000d0d7810 */
/* 0x000fca0007ffe1ff */
/*0ba0*/ DFMA R2, R18, -R2, R16 ; /* 0x800000021202722b */
/* 0x000e460000000010 */
/*0bb0*/ LOP3.LUT R9, R7, R9, RZ, 0x3c, !PT ; /* 0x0000000907097212 */
/* 0x001fce00078e3cff */
/*0bc0*/ FSETP.NEU.AND P0, PT, |R3|, R13, PT ; /* 0x0000000d0300720b */
/* 0x002fc80003f0d200 */
/*0bd0*/ FSEL R18, R6, R18, !P0 ; /* 0x0000001206127208 */
/* 0x000fe40004000000 */
/*0be0*/ FSEL R19, R9, R19, !P0 ; /* 0x0000001309137208 */
/* 0x000fe20004000000 */
/*0bf0*/ BRA 0xd50 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0c00*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x003e1c0003f08000 */
/*0c10*/ @P0 BRA 0xd30 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0c20*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e1c0003f08000 */
/*0c30*/ @P0 BRA 0xd00 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0c40*/ ISETP.NE.AND P0, PT, R15, R22, PT ; /* 0x000000160f00720c */
/* 0x000fe20003f05270 */
/*0c50*/ IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; /* 0x00000000ff127424 */
/* 0x000fe400078e00ff */
/*0c60*/ IMAD.MOV.U32 R19, RZ, RZ, -0x80000 ; /* 0xfff80000ff137424 */
/* 0x000fd400078e00ff */
/*0c70*/ @!P0 BRA 0xd50 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0c80*/ ISETP.NE.AND P0, PT, R15, 0x7ff00000, PT ; /* 0x7ff000000f00780c */
/* 0x000fe40003f05270 */
/*0c90*/ LOP3.LUT R19, R7, 0x80000000, R9, 0x48, !PT ; /* 0x8000000007137812 */
/* 0x000fe400078e4809 */
/*0ca0*/ ISETP.EQ.OR P0, PT, R22, RZ, !P0 ; /* 0x000000ff1600720c */
/* 0x000fda0004702670 */
/*0cb0*/ @P0 LOP3.LUT R2, R19, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000013020812 */
/* 0x000fe200078efcff */
/*0cc0*/ @!P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff128224 */
/* 0x000fe400078e00ff */
/*0cd0*/ @P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff120224 */
/* 0x000fe400078e00ff */
/*0ce0*/ @P0 IMAD.MOV.U32 R19, RZ, RZ, R2 ; /* 0x000000ffff130224 */
/* 0x000fe200078e0002 */
/*0cf0*/ BRA 0xd50 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0d00*/ LOP3.LUT R19, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000009137812 */
/* 0x000fe200078efcff */
/*0d10*/ IMAD.MOV.U32 R18, RZ, RZ, R8 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0008 */
/*0d20*/ BRA 0xd50 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0d30*/ LOP3.LUT R19, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000007137812 */
/* 0x000fe200078efcff */
/*0d40*/ IMAD.MOV.U32 R18, RZ, RZ, R6 ; /* 0x000000ffff127224 */
/* 0x000fe400078e0006 */
/*0d50*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0d60*/ IMAD.MOV.U32 R13, RZ, RZ, 0x0 ; /* 0x00000000ff0d7424 */
/* 0x000fe400078e00ff */
/*0d70*/ IMAD.MOV.U32 R2, RZ, RZ, R18 ; /* 0x000000ffff027224 */
/* 0x000fc400078e0012 */
/*0d80*/ IMAD.MOV.U32 R3, RZ, RZ, R19 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0013 */
/*0d90*/ RET.REL.NODEC R12 0x0 ; /* 0xfffff2600c007950 */
/* 0x000fec0003c3ffff */
/*0da0*/ BRA 0xda0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void ZeroMeanImpl(float* solutions, int rowSize, int matCount) {
const int matricesPerBlock = BLOCK_SIZE / rowSize;
const int matrixIdx = blockIdx.x * matricesPerBlock + threadIdx.x / rowSize;
const int tid = threadIdx.x;
const int col = threadIdx.x & (rowSize - 1);
const int inBlockOffset = threadIdx.x / rowSize;
__shared__ double beta[BLOCK_SIZE];
__shared__ double line[BLOCK_SIZE];
if (matrixIdx >= matCount) {
return;
}
solutions += matrixIdx * rowSize;
beta[tid] = col != (rowSize - 1) ? solutions[col] : 0;
line[tid] = beta[tid];
__syncthreads();
for (int s = rowSize >> 1; s > 0; s >>= 1) {
if (col < s) {
line[tid] += line[tid + s];
}
__syncthreads();
}
beta[tid] -= line[rowSize * inBlockOffset] / rowSize;
solutions[col] = beta[tid];
} | .file "tmpxft_000bb669_00000000-6_ZeroMeanImpl.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z12ZeroMeanImplPfiiPfii
.type _Z34__device_stub__Z12ZeroMeanImplPfiiPfii, @function
_Z34__device_stub__Z12ZeroMeanImplPfiiPfii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12ZeroMeanImplPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z12ZeroMeanImplPfiiPfii, .-_Z34__device_stub__Z12ZeroMeanImplPfiiPfii
.globl _Z12ZeroMeanImplPfii
.type _Z12ZeroMeanImplPfii, @function
_Z12ZeroMeanImplPfii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12ZeroMeanImplPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12ZeroMeanImplPfii, .-_Z12ZeroMeanImplPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12ZeroMeanImplPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12ZeroMeanImplPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void ZeroMeanImpl(float* solutions, int rowSize, int matCount) {
const int matricesPerBlock = BLOCK_SIZE / rowSize;
const int matrixIdx = blockIdx.x * matricesPerBlock + threadIdx.x / rowSize;
const int tid = threadIdx.x;
const int col = threadIdx.x & (rowSize - 1);
const int inBlockOffset = threadIdx.x / rowSize;
__shared__ double beta[BLOCK_SIZE];
__shared__ double line[BLOCK_SIZE];
if (matrixIdx >= matCount) {
return;
}
solutions += matrixIdx * rowSize;
beta[tid] = col != (rowSize - 1) ? solutions[col] : 0;
line[tid] = beta[tid];
__syncthreads();
for (int s = rowSize >> 1; s > 0; s >>= 1) {
if (col < s) {
line[tid] += line[tid + s];
}
__syncthreads();
}
beta[tid] -= line[rowSize * inBlockOffset] / rowSize;
solutions[col] = beta[tid];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ZeroMeanImpl(float* solutions, int rowSize, int matCount) {
const int matricesPerBlock = BLOCK_SIZE / rowSize;
const int matrixIdx = blockIdx.x * matricesPerBlock + threadIdx.x / rowSize;
const int tid = threadIdx.x;
const int col = threadIdx.x & (rowSize - 1);
const int inBlockOffset = threadIdx.x / rowSize;
__shared__ double beta[BLOCK_SIZE];
__shared__ double line[BLOCK_SIZE];
if (matrixIdx >= matCount) {
return;
}
solutions += matrixIdx * rowSize;
beta[tid] = col != (rowSize - 1) ? solutions[col] : 0;
line[tid] = beta[tid];
__syncthreads();
for (int s = rowSize >> 1; s > 0; s >>= 1) {
if (col < s) {
line[tid] += line[tid + s];
}
__syncthreads();
}
beta[tid] -= line[rowSize * inBlockOffset] / rowSize;
solutions[col] = beta[tid];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ZeroMeanImpl(float* solutions, int rowSize, int matCount) {
const int matricesPerBlock = BLOCK_SIZE / rowSize;
const int matrixIdx = blockIdx.x * matricesPerBlock + threadIdx.x / rowSize;
const int tid = threadIdx.x;
const int col = threadIdx.x & (rowSize - 1);
const int inBlockOffset = threadIdx.x / rowSize;
__shared__ double beta[BLOCK_SIZE];
__shared__ double line[BLOCK_SIZE];
if (matrixIdx >= matCount) {
return;
}
solutions += matrixIdx * rowSize;
beta[tid] = col != (rowSize - 1) ? solutions[col] : 0;
line[tid] = beta[tid];
__syncthreads();
for (int s = rowSize >> 1; s > 0; s >>= 1) {
if (col < s) {
line[tid] += line[tid + s];
}
__syncthreads();
}
beta[tid] -= line[rowSize * inBlockOffset] / rowSize;
solutions[col] = beta[tid];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12ZeroMeanImplPfii
.globl _Z12ZeroMeanImplPfii
.p2align 8
.type _Z12ZeroMeanImplPfii,@function
_Z12ZeroMeanImplPfii:
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s2, 31
v_cvt_f32_u32_e32 v2, s2
s_add_i32 s5, s2, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s5, s5, s4
v_cvt_f32_u32_e32 v1, s5
s_sub_i32 s7, 0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s6, v1
v_rcp_iflag_f32_e32 v1, v2
s_mul_i32 s7, s7, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s7, s6, s7
s_add_i32 s6, s6, s7
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_mul_hi_u32 s6, s6, 0x3e8
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s7, s6, s5
s_add_i32 s8, s6, 1
s_sub_i32 s7, 0x3e8, s7
v_cvt_u32_f32_e32 v1, v1
s_sub_i32 s9, s7, s5
s_cmp_ge_u32 s7, s5
s_cselect_b32 s6, s8, s6
s_cselect_b32 s7, s9, s7
s_add_i32 s8, s6, 1
s_cmp_ge_u32 s7, s5
s_cselect_b32 s5, s8, s6
s_sub_i32 s6, 0, s2
s_xor_b32 s5, s5, s4
v_mul_lo_u32 v2, s6, v1
s_sub_i32 s4, s5, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v1, v2
v_add_nc_u32_e32 v1, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v0, v1
v_mul_lo_u32 v2, v1, s2
v_add_nc_u32_e32 v3, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v0, v2
v_subrev_nc_u32_e32 v4, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v1, v1, v3
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, 1, v1
v_cndmask_b32_e32 v1, v1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s4, s15, v[1:2]
v_cmp_gt_i32_e32 vcc_lo, s3, v2
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_9
s_load_b64 s[0:1], s[0:1], 0x0
v_mul_lo_u32 v2, v2, s2
s_add_i32 s3, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v4, s3, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 2, v[2:3]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_mov_b32 s0, exec_lo
v_cmpx_ne_u32_e64 s3, v4
s_cbranch_execz .LBB0_3
v_lshlrev_b32_e32 v2, 2, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v2, vcc_lo, v5, v2
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v6, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[2:3], v2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s0
v_lshlrev_b32_e32 v7, 3, v0
s_ashr_i32 s0, s2, 1
ds_store_b64 v7, v[2:3]
ds_store_b64 v7, v[2:3] offset:8000
s_cmp_lt_i32 s0, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_8
v_add_nc_u32_e32 v2, 0x1f40, v7
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s1
s_lshr_b32 s1, s0, 1
s_cmp_lt_u32 s0, 2
s_mov_b32 s0, s1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_8
.LBB0_6:
s_mov_b32 s1, exec_lo
v_cmpx_gt_u32_e64 s0, v4
s_cbranch_execz .LBB0_5
v_add_lshl_u32 v3, s0, v0, 3
ds_load_b64 v[8:9], v3 offset:8000
ds_load_b64 v[10:11], v2
s_waitcnt lgkmcnt(0)
v_add_f64 v[8:9], v[8:9], v[10:11]
ds_store_b64 v2, v[8:9]
s_branch .LBB0_5
.LBB0_8:
v_cvt_f64_i32_e32 v[2:3], s2
v_mul_lo_u32 v0, v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v0, 3, v0
ds_load_b64 v[0:1], v0 offset:8000
ds_load_b64 v[8:9], v7
s_waitcnt lgkmcnt(1)
v_div_scale_f64 v[10:11], null, v[2:3], v[2:3], v[0:1]
v_rcp_f64_e32 v[12:13], v[10:11]
s_waitcnt_depctr 0xfff
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
v_div_scale_f64 v[14:15], vcc_lo, v[0:1], v[2:3], v[0:1]
v_mul_f64 v[16:17], v[14:15], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[10:11], v[16:17], v[14:15]
v_div_fmas_f64 v[10:11], v[10:11], v[12:13], v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[0:1], v[10:11], v[2:3], v[0:1]
v_lshlrev_b32_e32 v2, 2, v4
v_add_co_u32 v2, vcc_lo, v5, v2
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v6, vcc_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[8:9], -v[0:1]
v_cvt_f32_f64_e32 v8, v[0:1]
ds_store_b64 v7, v[0:1]
global_store_b32 v[2:3], v8, off
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12ZeroMeanImplPfii
.amdhsa_group_segment_fixed_size 16000
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12ZeroMeanImplPfii, .Lfunc_end0-_Z12ZeroMeanImplPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 16000
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12ZeroMeanImplPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12ZeroMeanImplPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ZeroMeanImpl(float* solutions, int rowSize, int matCount) {
const int matricesPerBlock = BLOCK_SIZE / rowSize;
const int matrixIdx = blockIdx.x * matricesPerBlock + threadIdx.x / rowSize;
const int tid = threadIdx.x;
const int col = threadIdx.x & (rowSize - 1);
const int inBlockOffset = threadIdx.x / rowSize;
__shared__ double beta[BLOCK_SIZE];
__shared__ double line[BLOCK_SIZE];
if (matrixIdx >= matCount) {
return;
}
solutions += matrixIdx * rowSize;
beta[tid] = col != (rowSize - 1) ? solutions[col] : 0;
line[tid] = beta[tid];
__syncthreads();
for (int s = rowSize >> 1; s > 0; s >>= 1) {
if (col < s) {
line[tid] += line[tid + s];
}
__syncthreads();
}
beta[tid] -= line[rowSize * inBlockOffset] / rowSize;
solutions[col] = beta[tid];
} | .text
.file "ZeroMeanImpl.hip"
.globl _Z27__device_stub__ZeroMeanImplPfii # -- Begin function _Z27__device_stub__ZeroMeanImplPfii
.p2align 4, 0x90
.type _Z27__device_stub__ZeroMeanImplPfii,@function
_Z27__device_stub__ZeroMeanImplPfii: # @_Z27__device_stub__ZeroMeanImplPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12ZeroMeanImplPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__ZeroMeanImplPfii, .Lfunc_end0-_Z27__device_stub__ZeroMeanImplPfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12ZeroMeanImplPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12ZeroMeanImplPfii,@object # @_Z12ZeroMeanImplPfii
.section .rodata,"a",@progbits
.globl _Z12ZeroMeanImplPfii
.p2align 3, 0x0
_Z12ZeroMeanImplPfii:
.quad _Z27__device_stub__ZeroMeanImplPfii
.size _Z12ZeroMeanImplPfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12ZeroMeanImplPfii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__ZeroMeanImplPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12ZeroMeanImplPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12ZeroMeanImplPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R9, c[0x0][0x168] ; /* 0x00005a0000097a13 */
/* 0x000fe20000000000 */
/*0020*/ I2F.U32.RP R7, c[0x0][0x168] ; /* 0x00005a0000077b06 */
/* 0x000e220000209000 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0040*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000eac0000002500 */
/*0050*/ I2F.RP R6, R9 ; /* 0x0000000900067306 */
/* 0x000ef00000209400 */
/*0060*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e300000001000 */
/*0070*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x008ee20000001000 */
/*0080*/ IADD3 R4, R7, 0xffffffe, RZ ; /* 0x0ffffffe07047810 */
/* 0x001fce0007ffe0ff */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000122000021f000 */
/*00a0*/ IADD3 R2, R6, 0xffffffe, RZ ; /* 0x0ffffffe06027810 */
/* 0x008fce0007ffe0ff */
/*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000762000021f000 */
/*00c0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*00d0*/ IMAD.MOV R6, RZ, RZ, -R5 ; /* 0x000000ffff067224 */
/* 0x010fe400078e0a05 */
/*00e0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x008fe400078e00ff */
/*00f0*/ IMAD R7, R6, c[0x0][0x168], RZ ; /* 0x00005a0006077a24 */
/* 0x000fe400078e02ff */
/*0100*/ IMAD.MOV R8, RZ, RZ, -R3 ; /* 0x000000ffff087224 */
/* 0x020fe400078e0a03 */
/*0110*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fc800078e0004 */
/*0120*/ IMAD R11, R8, R9, RZ ; /* 0x00000009080b7224 */
/* 0x000fe400078e02ff */
/*0130*/ IMAD.HI.U32 R5, R5, R0, RZ ; /* 0x0000000005057227 */
/* 0x002fc800078e00ff */
/*0140*/ IMAD.HI.U32 R3, R3, R11, R2 ; /* 0x0000000b03037227 */
/* 0x000fc800078e0002 */
/*0150*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0a05 */
/*0160*/ IMAD.HI.U32 R3, R3, 0x3e8, RZ ; /* 0x000003e803037827 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R2, RZ, RZ, -R3 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0a03 */
/*0180*/ IMAD R4, R7, c[0x0][0x168], R0 ; /* 0x00005a0007047a24 */
/* 0x000fe400078e0200 */
/*0190*/ IMAD R2, R9.reuse, R2, 0x3e8 ; /* 0x000003e809027424 */
/* 0x040fe400078e0202 */
/*01a0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0b7624 */
/* 0x000fe200078e00ff */
/*01b0*/ ISETP.GE.U32.AND P2, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fe40003f46070 */
/*01c0*/ ISETP.GT.U32.AND P4, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fd60003f84070 */
/*01d0*/ @P2 IADD3 R4, R4, -c[0x0][0x168], RZ ; /* 0x80005a0004042a10 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P4 IMAD.IADD R2, R2, 0x1, -R9 ; /* 0x000000010202c824 */
/* 0x000fe200078e0a09 */
/*01f0*/ @!P4 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303c810 */
/* 0x000fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fe40003f26070 */
/*0210*/ ISETP.GE.U32.AND P3, PT, R2, R9, PT ; /* 0x000000090200720c */
/* 0x000fe40003f66070 */
/*0220*/ LOP3.LUT R2, R11, 0x3e8, RZ, 0x3c, !PT ; /* 0x000003e80b027812 */
/* 0x000fe400078e3cff */
/*0230*/ @P2 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105052810 */
/* 0x000fc40007ffe0ff */
/*0240*/ ISETP.GE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f06270 */
/*0250*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe40003f45070 */
/*0260*/ LOP3.LUT R2, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff027a12 */
/* 0x000fe400078e33ff */
/*0270*/ @P1 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105051810 */
/* 0x000fe40007ffe0ff */
/*0280*/ @P3 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103033810 */
/* 0x000fe40007ffe0ff */
/*0290*/ ISETP.NE.AND P3, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fc40003f65270 */
/*02a0*/ SEL R5, R2, R5, !P2 ; /* 0x0000000502057207 */
/* 0x000fe20005000000 */
/*02b0*/ @!P0 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff038224 */
/* 0x000fca00078e0a03 */
/*02c0*/ SEL R2, R2, R3, !P3 ; /* 0x0000000302027207 */
/* 0x000fca0005800000 */
/*02d0*/ IMAD R5, R2, UR4, R5 ; /* 0x0000000402057c24 */
/* 0x004fca000f8e0205 */
/*02e0*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x16c], PT ; /* 0x00005b0005007a0c */
/* 0x000fda0003f06270 */
/*02f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0300*/ IADD3 R3, R11, -0x1, RZ ; /* 0xffffffff0b037810 */
/* 0x000fe20007ffe0ff */
/*0310*/ IMAD R5, R5, c[0x0][0x168], RZ ; /* 0x00005a0005057a24 */
/* 0x000fe200078e02ff */
/*0320*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0330*/ LOP3.LUT R2, R3, R0, RZ, 0xc0, !PT ; /* 0x0000000003027212 */
/* 0x000fc800078ec0ff */
/*0340*/ SHF.R.S32.HI R4, RZ, 0x1f, R2 ; /* 0x0000001fff047819 */
/* 0x000fe40000011402 */
/*0350*/ IADD3 R6, P1, R2.reuse, R5, RZ ; /* 0x0000000502067210 */
/* 0x040fe40007f3e0ff */
/*0360*/ ISETP.NE.AND P0, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fe40003f05270 */
/*0370*/ LEA.HI.X.SX32 R5, R5, R4, 0x1, P1 ; /* 0x0000000405057211 */
/* 0x000fe400008f0eff */
/*0380*/ LEA R4, P1, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006047a11 */
/* 0x000fc800078210ff */
/*0390*/ LEA.HI.X R5, R6, c[0x0][0x164], R5, 0x2, P1 ; /* 0x0000590006057a11 */
/* 0x000fca00008f1405 */
/*03a0*/ @P0 LDG.E R10, [R4.64] ; /* 0x00000004040a0981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ I2F.U32.RP R3, c[0x0][0x168] ; /* 0x00005a0000037b06 */
/* 0x000e220000209000 */
/*03c0*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fce0003f45070 */
/*03d0*/ MUFU.RCP R3, R3 ; /* 0x0000000300037308 */
/* 0x001e240000001000 */
/*03e0*/ IADD3 R6, R3, 0xffffffe, RZ ; /* 0x0ffffffe03067810 */
/* 0x001fcc0007ffe0ff */
/*03f0*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0400*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0410*/ IMAD.MOV R9, RZ, RZ, -R7 ; /* 0x000000ffff097224 */
/* 0x002fc800078e0a07 */
/*0420*/ IMAD R9, R9, c[0x0][0x168], RZ ; /* 0x00005a0009097a24 */
/* 0x000fc800078e02ff */
/*0430*/ IMAD.HI.U32 R9, R7, R9, R6 ; /* 0x0000000907097227 */
/* 0x000fe400078e0006 */
/*0440*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fc8000001ff00 */
/*0450*/ IMAD.HI.U32 R9, R9, R0, RZ ; /* 0x0000000009097227 */
/* 0x000fc800078e00ff */
/*0460*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fc800078e0a09 */
/*0470*/ IMAD R13, R9, c[0x0][0x168], R0 ; /* 0x00005a00090d7a24 */
/* 0x000fe400078e0200 */
/*0480*/ I2F.F64 R8, c[0x0][0x168] ; /* 0x00005a0000087b12 */
/* 0x000e260000201c00 */
/*0490*/ ISETP.GE.U32.AND P1, PT, R13, c[0x0][0x168], PT ; /* 0x00005a000d007a0c */
/* 0x000fda0003f26070 */
/*04a0*/ @P1 IADD3 R13, R13, -c[0x0][0x168], RZ ; /* 0x80005a000d0d1a10 */
/* 0x000fe20007ffe0ff */
/*04b0*/ MUFU.RCP64H R3, R9 ; /* 0x0000000900037308 */
/* 0x0010660000001800 */
/*04c0*/ ISETP.GE.U32.AND P1, PT, R13, c[0x0][0x168], PT ; /* 0x00005a000d007a0c */
/* 0x000fda0003f26070 */
/*04d0*/ @P1 IADD3 R13, R13, -c[0x0][0x168], RZ ; /* 0x80005a000d0d1a10 */
/* 0x000fe40007ffe0ff */
/*04e0*/ @!P2 LOP3.LUT R13, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff0daa12 */
/* 0x000fca00078e33ff */
/*04f0*/ IMAD.IADD R14, R0, 0x1, -R13 ; /* 0x00000001000e7824 */
/* 0x000fe200078e0a0d */
/*0500*/ @P0 F2F.F64.F32 R6, R10 ; /* 0x0000000a00060310 */
/* 0x004ea20000201800 */
/*0510*/ ISETP.GE.AND P0, PT, R11, 0x2, PT ; /* 0x000000020b00780c */
/* 0x000fe20003f06270 */
/*0520*/ STS.64 [R0.X8], R6 ; /* 0x0000000600007388 */
/* 0x0041e80000008a00 */
/*0530*/ STS.64 [R0.X8+0x1f40], R6 ; /* 0x001f400600007388 */
/* 0x0001e80000008a00 */
/*0540*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0550*/ @!P0 BRA 0x640 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0560*/ IMAD.SHL.U32 R6, R0, 0x8, RZ ; /* 0x0000000800067824 */
/* 0x003fe400078e00ff */
/*0570*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0d7624 */
/* 0x000fc600078e00ff */
/*0580*/ IADD3 R12, R6, 0x1f40, RZ ; /* 0x00001f40060c7810 */
/* 0x000fe40007ffe0ff */
/*0590*/ SHF.R.S32.HI R15, RZ, 0x1, R13 ; /* 0x00000001ff0f7819 */
/* 0x000fc8000001140d */
/*05a0*/ ISETP.GE.AND P0, PT, R2, R15, PT ; /* 0x0000000f0200720c */
/* 0x000fda0003f06270 */
/*05b0*/ @!P0 IMAD R10, R15, 0x8, R12 ; /* 0x000000080f0a8824 */
/* 0x000fe200078e020c */
/*05c0*/ @!P0 LDS.64 R6, [R0.X8+0x1f40] ; /* 0x001f400000068984 */
/* 0x000fea0000008a00 */
/*05d0*/ @!P0 LDS.64 R10, [R10] ; /* 0x000000000a0a8984 */
/* 0x000e240000000a00 */
/*05e0*/ @!P0 DADD R6, R6, R10 ; /* 0x0000000006068229 */
/* 0x001e0e000000000a */
/*05f0*/ @!P0 STS.64 [R0.X8+0x1f40], R6 ; /* 0x001f400600008388 */
/* 0x0011e80000008a00 */
/*0600*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0610*/ ISETP.GT.AND P0, PT, R13, 0x3, PT ; /* 0x000000030d00780c */
/* 0x000fe20003f04270 */
/*0620*/ IMAD.MOV.U32 R13, RZ, RZ, R15 ; /* 0x000000ffff0d7224 */
/* 0x000fd800078e000f */
/*0630*/ @P0 BRA 0x590 ; /* 0xffffff5000000947 */
/* 0x001fea000383ffff */
/*0640*/ LDS.64 R6, [R14.X8+0x1f40] ; /* 0x001f40000e067984 */
/* 0x003e220000008a00 */
/*0650*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fe200078e00ff */
/*0660*/ BSSY B0, 0x760 ; /* 0x000000f000007945 */
/* 0x000fea0003800000 */
/*0670*/ DFMA R10, -R8, R2, 1 ; /* 0x3ff00000080a742b */
/* 0x000e4c0000000102 */
/*0680*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x002e4c000000000a */
/*0690*/ DFMA R10, R2, R10, R2 ; /* 0x0000000a020a722b */
/* 0x002e4c0000000002 */
/*06a0*/ DFMA R2, -R8, R10, 1 ; /* 0x3ff000000802742b */
/* 0x002e4c000000010a */
/*06b0*/ DFMA R2, R10, R2, R10 ; /* 0x000000020a02722b */
/* 0x002e0c000000000a */
/*06c0*/ DMUL R10, R6, R2 ; /* 0x00000002060a7228 */
/* 0x001e220000000000 */
/*06d0*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fca0003f2e200 */
/*06e0*/ DFMA R12, -R8, R10, R6 ; /* 0x0000000a080c722b */
/* 0x001e0c0000000106 */
/*06f0*/ DFMA R2, R2, R12, R10 ; /* 0x0000000c0202722b */
/* 0x001e14000000000a */
/*0700*/ FFMA R10, RZ, R9, R3 ; /* 0x00000009ff0a7223 */
/* 0x001fca0000000003 */
/*0710*/ FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ; /* 0x001000000a00780b */
/* 0x000fda0003f04200 */
/*0720*/ @P0 BRA P1, 0x750 ; /* 0x0000002000000947 */
/* 0x000fea0000800000 */
/*0730*/ MOV R12, 0x750 ; /* 0x00000750000c7802 */
/* 0x000fe40000000f00 */
/*0740*/ CALL.REL.NOINC 0x7c0 ; /* 0x0000007000007944 */
/* 0x000fea0003c00000 */
/*0750*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0760*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e240000008a00 */
/*0770*/ DADD R6, R6, -R2 ; /* 0x0000000006067229 */
/* 0x001e0c0000000802 */
/*0780*/ F2F.F32.F64 R3, R6 ; /* 0x0000000600037310 */
/* 0x001e220000301000 */
/*0790*/ STS.64 [R0.X8], R6 ; /* 0x0000000600007388 */
/* 0x000fe80000008a00 */
/*07a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x001fe2000c101904 */
/*07b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07c0*/ FSETP.GEU.AND P0, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f0e200 */
/*07d0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0e7424 */
/* 0x000fe200078e00ff */
/*07e0*/ LOP3.LUT R2, R9, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff09027812 */
/* 0x000fe200078ec0ff */
/*07f0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*0800*/ FSETP.GEU.AND P2, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f4e200 */
/*0810*/ BSSY B1, 0xd60 ; /* 0x0000054000017945 */
/* 0x000fe20003800000 */
/*0820*/ LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000002037812 */
/* 0x000fe200078efcff */
/*0830*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0008 */
/*0840*/ LOP3.LUT R13, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000070d7812 */
/* 0x000fc400078ec0ff */
/*0850*/ LOP3.LUT R18, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009127812 */
/* 0x000fc600078ec0ff */
/*0860*/ @!P0 DMUL R2, R8, 8.98846567431157953865e+307 ; /* 0x7fe0000008028828 */
/* 0x000e220000000000 */
/*0870*/ ISETP.GE.U32.AND P1, PT, R13, R18, PT ; /* 0x000000120d00720c */
/* 0x000fc60003f26070 */
/*0880*/ @!P2 LOP3.LUT R10, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090aa812 */
/* 0x000fe200078ec0ff */
/*0890*/ @!P2 IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff16a224 */
/* 0x000fe200078e00ff */
/*08a0*/ MUFU.RCP64H R17, R3 ; /* 0x0000000300117308 */
/* 0x001e220000001800 */
/*08b0*/ SEL R11, R14.reuse, 0x63400000, !P1 ; /* 0x634000000e0b7807 */
/* 0x040fe40004800000 */
/*08c0*/ @!P2 ISETP.GE.U32.AND P3, PT, R13, R10, PT ; /* 0x0000000a0d00a20c */
/* 0x000fe20003f66070 */
/*08d0*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0006 */
/*08e0*/ LOP3.LUT R11, R11, 0x800fffff, R7, 0xf8, !PT ; /* 0x800fffff0b0b7812 */
/* 0x000fe400078ef807 */
/*08f0*/ @!P2 SEL R15, R14, 0x63400000, !P3 ; /* 0x634000000e0fa807 */
/* 0x000fc80005800000 */
/*0900*/ @!P2 LOP3.LUT R15, R15, 0x80000000, R7, 0xf8, !PT ; /* 0x800000000f0fa812 */
/* 0x000fc800078ef807 */
/*0910*/ @!P2 LOP3.LUT R23, R15, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000f17a812 */
/* 0x000fe200078efcff */
/*0920*/ DFMA R20, R16, -R2, 1 ; /* 0x3ff000001014742b */
/* 0x001e220000000802 */
/*0930*/ IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e000d */
/*0940*/ @!P2 DFMA R10, R10, 2, -R22 ; /* 0x400000000a0aa82b */
/* 0x0003e40000000816 */
/*0950*/ IMAD.MOV.U32 R22, RZ, RZ, R18 ; /* 0x000000ffff167224 */
/* 0x002fe200078e0012 */
/*0960*/ @!P0 LOP3.LUT R22, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003168812 */
/* 0x000fe200078ec0ff */
/*0970*/ DFMA R20, R20, R20, R20 ; /* 0x000000141414722b */
/* 0x001e060000000014 */
/*0980*/ IADD3 R23, R22, -0x1, RZ ; /* 0xffffffff16177810 */
/* 0x000fc60007ffe0ff */
/*0990*/ DFMA R16, R16, R20, R16 ; /* 0x000000141010722b */
/* 0x001e220000000010 */
/*09a0*/ @!P2 LOP3.LUT R15, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b0fa812 */
/* 0x000fca00078ec0ff */
/*09b0*/ DFMA R20, R16, -R2, 1 ; /* 0x3ff000001014742b */
/* 0x001e0c0000000802 */
/*09c0*/ DFMA R16, R16, R20, R16 ; /* 0x000000141010722b */
/* 0x0010640000000010 */
/*09d0*/ IADD3 R20, R15, -0x1, RZ ; /* 0xffffffff0f147810 */
/* 0x001fc80007ffe0ff */
/*09e0*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fe20003f04070 */
/*09f0*/ DMUL R18, R16, R10 ; /* 0x0000000a10127228 */
/* 0x002e060000000000 */
/*0a00*/ ISETP.GT.U32.OR P0, PT, R23, 0x7feffffe, P0 ; /* 0x7feffffe1700780c */
/* 0x000fc60000704470 */
/*0a10*/ DFMA R20, R18, -R2, R10 ; /* 0x800000021214722b */
/* 0x001e0c000000000a */
/*0a20*/ DFMA R16, R16, R20, R18 ; /* 0x000000141010722b */
/* 0x0010480000000012 */
/*0a30*/ @P0 BRA 0xc00 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0a40*/ LOP3.LUT R18, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009127812 */
/* 0x003fc800078ec0ff */
/*0a50*/ ISETP.GE.U32.AND P0, PT, R13.reuse, R18, PT ; /* 0x000000120d00720c */
/* 0x040fe20003f06070 */
/*0a60*/ IMAD.IADD R6, R13, 0x1, -R18 ; /* 0x000000010d067824 */
/* 0x000fc600078e0a12 */
/*0a70*/ SEL R13, R14, 0x63400000, !P0 ; /* 0x634000000e0d7807 */
/* 0x000fe40004000000 */
/*0a80*/ IMNMX R6, R6, -0x46a00000, !PT ; /* 0xb960000006067817 */
/* 0x000fc80007800200 */
/*0a90*/ IMNMX R6, R6, 0x46a00000, PT ; /* 0x46a0000006067817 */
/* 0x000fca0003800200 */
/*0aa0*/ IMAD.IADD R13, R6, 0x1, -R13 ; /* 0x00000001060d7824 */
/* 0x000fe400078e0a0d */
/*0ab0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*0ac0*/ IADD3 R7, R13, 0x7fe00000, RZ ; /* 0x7fe000000d077810 */
/* 0x000fcc0007ffe0ff */
/*0ad0*/ DMUL R18, R16, R6 ; /* 0x0000000610127228 */
/* 0x000e140000000000 */
/*0ae0*/ FSETP.GTU.AND P0, PT, |R19|, 1.469367938527859385e-39, PT ; /* 0x001000001300780b */
/* 0x001fda0003f0c200 */
/*0af0*/ @P0 BRA 0xd50 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0b00*/ DFMA R2, R16, -R2, R10 ; /* 0x800000021002722b */
/* 0x000e22000000000a */
/*0b10*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fd200078e00ff */
/*0b20*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*0b30*/ LOP3.LUT R9, R3, 0x80000000, R9, 0x48, !PT ; /* 0x8000000003097812 */
/* 0x000fc800078e4809 */
/*0b40*/ LOP3.LUT R7, R9, R7, RZ, 0xfc, !PT ; /* 0x0000000709077212 */
/* 0x000fce00078efcff */
/*0b50*/ @!P0 BRA 0xd50 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0b60*/ IMAD.MOV R3, RZ, RZ, -R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0d */
/*0b70*/ DMUL.RP R6, R16, R6 ; /* 0x0000000610067228 */
/* 0x000e220000008000 */
/*0b80*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*0b90*/ IADD3 R13, -R13, -0x43300000, RZ ; /* 0xbcd000000d0d7810 */
/* 0x000fca0007ffe1ff */
/*0ba0*/ DFMA R2, R18, -R2, R16 ; /* 0x800000021202722b */
/* 0x000e460000000010 */
/*0bb0*/ LOP3.LUT R9, R7, R9, RZ, 0x3c, !PT ; /* 0x0000000907097212 */
/* 0x001fce00078e3cff */
/*0bc0*/ FSETP.NEU.AND P0, PT, |R3|, R13, PT ; /* 0x0000000d0300720b */
/* 0x002fc80003f0d200 */
/*0bd0*/ FSEL R18, R6, R18, !P0 ; /* 0x0000001206127208 */
/* 0x000fe40004000000 */
/*0be0*/ FSEL R19, R9, R19, !P0 ; /* 0x0000001309137208 */
/* 0x000fe20004000000 */
/*0bf0*/ BRA 0xd50 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0c00*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x003e1c0003f08000 */
/*0c10*/ @P0 BRA 0xd30 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0c20*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e1c0003f08000 */
/*0c30*/ @P0 BRA 0xd00 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0c40*/ ISETP.NE.AND P0, PT, R15, R22, PT ; /* 0x000000160f00720c */
/* 0x000fe20003f05270 */
/*0c50*/ IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; /* 0x00000000ff127424 */
/* 0x000fe400078e00ff */
/*0c60*/ IMAD.MOV.U32 R19, RZ, RZ, -0x80000 ; /* 0xfff80000ff137424 */
/* 0x000fd400078e00ff */
/*0c70*/ @!P0 BRA 0xd50 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0c80*/ ISETP.NE.AND P0, PT, R15, 0x7ff00000, PT ; /* 0x7ff000000f00780c */
/* 0x000fe40003f05270 */
/*0c90*/ LOP3.LUT R19, R7, 0x80000000, R9, 0x48, !PT ; /* 0x8000000007137812 */
/* 0x000fe400078e4809 */
/*0ca0*/ ISETP.EQ.OR P0, PT, R22, RZ, !P0 ; /* 0x000000ff1600720c */
/* 0x000fda0004702670 */
/*0cb0*/ @P0 LOP3.LUT R2, R19, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000013020812 */
/* 0x000fe200078efcff */
/*0cc0*/ @!P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff128224 */
/* 0x000fe400078e00ff */
/*0cd0*/ @P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff120224 */
/* 0x000fe400078e00ff */
/*0ce0*/ @P0 IMAD.MOV.U32 R19, RZ, RZ, R2 ; /* 0x000000ffff130224 */
/* 0x000fe200078e0002 */
/*0cf0*/ BRA 0xd50 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0d00*/ LOP3.LUT R19, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000009137812 */
/* 0x000fe200078efcff */
/*0d10*/ IMAD.MOV.U32 R18, RZ, RZ, R8 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0008 */
/*0d20*/ BRA 0xd50 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0d30*/ LOP3.LUT R19, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000007137812 */
/* 0x000fe200078efcff */
/*0d40*/ IMAD.MOV.U32 R18, RZ, RZ, R6 ; /* 0x000000ffff127224 */
/* 0x000fe400078e0006 */
/*0d50*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0d60*/ IMAD.MOV.U32 R13, RZ, RZ, 0x0 ; /* 0x00000000ff0d7424 */
/* 0x000fe400078e00ff */
/*0d70*/ IMAD.MOV.U32 R2, RZ, RZ, R18 ; /* 0x000000ffff027224 */
/* 0x000fc400078e0012 */
/*0d80*/ IMAD.MOV.U32 R3, RZ, RZ, R19 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0013 */
/*0d90*/ RET.REL.NODEC R12 0x0 ; /* 0xfffff2600c007950 */
/* 0x000fec0003c3ffff */
/*0da0*/ BRA 0xda0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12ZeroMeanImplPfii
.globl _Z12ZeroMeanImplPfii
.p2align 8
.type _Z12ZeroMeanImplPfii,@function
_Z12ZeroMeanImplPfii:
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s2, 31
v_cvt_f32_u32_e32 v2, s2
s_add_i32 s5, s2, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s5, s5, s4
v_cvt_f32_u32_e32 v1, s5
s_sub_i32 s7, 0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s6, v1
v_rcp_iflag_f32_e32 v1, v2
s_mul_i32 s7, s7, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s7, s6, s7
s_add_i32 s6, s6, s7
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_mul_hi_u32 s6, s6, 0x3e8
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s7, s6, s5
s_add_i32 s8, s6, 1
s_sub_i32 s7, 0x3e8, s7
v_cvt_u32_f32_e32 v1, v1
s_sub_i32 s9, s7, s5
s_cmp_ge_u32 s7, s5
s_cselect_b32 s6, s8, s6
s_cselect_b32 s7, s9, s7
s_add_i32 s8, s6, 1
s_cmp_ge_u32 s7, s5
s_cselect_b32 s5, s8, s6
s_sub_i32 s6, 0, s2
s_xor_b32 s5, s5, s4
v_mul_lo_u32 v2, s6, v1
s_sub_i32 s4, s5, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v1, v2
v_add_nc_u32_e32 v1, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v0, v1
v_mul_lo_u32 v2, v1, s2
v_add_nc_u32_e32 v3, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v0, v2
v_subrev_nc_u32_e32 v4, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v1, v1, v3
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, 1, v1
v_cndmask_b32_e32 v1, v1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s4, s15, v[1:2]
v_cmp_gt_i32_e32 vcc_lo, s3, v2
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_9
s_load_b64 s[0:1], s[0:1], 0x0
v_mul_lo_u32 v2, v2, s2
s_add_i32 s3, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v4, s3, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 2, v[2:3]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_mov_b32 s0, exec_lo
v_cmpx_ne_u32_e64 s3, v4
s_cbranch_execz .LBB0_3
v_lshlrev_b32_e32 v2, 2, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v2, vcc_lo, v5, v2
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v6, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[2:3], v2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s0
v_lshlrev_b32_e32 v7, 3, v0
s_ashr_i32 s0, s2, 1
ds_store_b64 v7, v[2:3]
ds_store_b64 v7, v[2:3] offset:8000
s_cmp_lt_i32 s0, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_8
v_add_nc_u32_e32 v2, 0x1f40, v7
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s1
s_lshr_b32 s1, s0, 1
s_cmp_lt_u32 s0, 2
s_mov_b32 s0, s1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_8
.LBB0_6:
s_mov_b32 s1, exec_lo
v_cmpx_gt_u32_e64 s0, v4
s_cbranch_execz .LBB0_5
v_add_lshl_u32 v3, s0, v0, 3
ds_load_b64 v[8:9], v3 offset:8000
ds_load_b64 v[10:11], v2
s_waitcnt lgkmcnt(0)
v_add_f64 v[8:9], v[8:9], v[10:11]
ds_store_b64 v2, v[8:9]
s_branch .LBB0_5
.LBB0_8:
v_cvt_f64_i32_e32 v[2:3], s2
v_mul_lo_u32 v0, v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v0, 3, v0
ds_load_b64 v[0:1], v0 offset:8000
ds_load_b64 v[8:9], v7
s_waitcnt lgkmcnt(1)
v_div_scale_f64 v[10:11], null, v[2:3], v[2:3], v[0:1]
v_rcp_f64_e32 v[12:13], v[10:11]
s_waitcnt_depctr 0xfff
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
v_div_scale_f64 v[14:15], vcc_lo, v[0:1], v[2:3], v[0:1]
v_mul_f64 v[16:17], v[14:15], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[10:11], v[16:17], v[14:15]
v_div_fmas_f64 v[10:11], v[10:11], v[12:13], v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[0:1], v[10:11], v[2:3], v[0:1]
v_lshlrev_b32_e32 v2, 2, v4
v_add_co_u32 v2, vcc_lo, v5, v2
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v6, vcc_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[8:9], -v[0:1]
v_cvt_f32_f64_e32 v8, v[0:1]
ds_store_b64 v7, v[0:1]
global_store_b32 v[2:3], v8, off
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12ZeroMeanImplPfii
.amdhsa_group_segment_fixed_size 16000
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12ZeroMeanImplPfii, .Lfunc_end0-_Z12ZeroMeanImplPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 16000
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12ZeroMeanImplPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12ZeroMeanImplPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bb669_00000000-6_ZeroMeanImpl.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z12ZeroMeanImplPfiiPfii
.type _Z34__device_stub__Z12ZeroMeanImplPfiiPfii, @function
_Z34__device_stub__Z12ZeroMeanImplPfiiPfii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12ZeroMeanImplPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z12ZeroMeanImplPfiiPfii, .-_Z34__device_stub__Z12ZeroMeanImplPfiiPfii
.globl _Z12ZeroMeanImplPfii
.type _Z12ZeroMeanImplPfii, @function
_Z12ZeroMeanImplPfii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12ZeroMeanImplPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12ZeroMeanImplPfii, .-_Z12ZeroMeanImplPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12ZeroMeanImplPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12ZeroMeanImplPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ZeroMeanImpl.hip"
.globl _Z27__device_stub__ZeroMeanImplPfii # -- Begin function _Z27__device_stub__ZeroMeanImplPfii
.p2align 4, 0x90
.type _Z27__device_stub__ZeroMeanImplPfii,@function
_Z27__device_stub__ZeroMeanImplPfii: # @_Z27__device_stub__ZeroMeanImplPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12ZeroMeanImplPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__ZeroMeanImplPfii, .Lfunc_end0-_Z27__device_stub__ZeroMeanImplPfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12ZeroMeanImplPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12ZeroMeanImplPfii,@object # @_Z12ZeroMeanImplPfii
.section .rodata,"a",@progbits
.globl _Z12ZeroMeanImplPfii
.p2align 3, 0x0
_Z12ZeroMeanImplPfii:
.quad _Z27__device_stub__ZeroMeanImplPfii
.size _Z12ZeroMeanImplPfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12ZeroMeanImplPfii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__ZeroMeanImplPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12ZeroMeanImplPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/* Copyright (C) 2012 Ward Poelmans
This file is part of Hubbard-GPU.
Hubbard-GPU is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
Hubbard-GPU is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with Hubbard-GPU. If not, see <http://www.gnu.org/licenses/>.
*/
// number of threads in a block (must be multiple of 32)
#define NUMTHREADS 128
// the maximum size of the grid
#define GRIDSIZE 65535
// Helper macro to check CUDA return values
__global__ void gpu_mvprod(double *x, double *y, double alpha, int NumUp, int NumDown, int dim, double *Umat, double *Down_data,unsigned int *Down_ind, int size_Down, double *Up_data, unsigned int *Up_ind, int size_Up, int rows_shared)
{
int index = threadIdx.x + blockDim.x * blockIdx.x + blockIdx.y * blockDim.x * gridDim.x;
if(index < dim)
{
double result = Umat[index] * x[index];
int sv = index / NumDown; //__fdividef(index,NumDown);
int id = index % NumDown; // index - sv*NumDown;
extern __shared__ double shared[];
unsigned int *shared_ind = (unsigned int *) &shared[size_Up * rows_shared];
int s_sv = (blockDim.x * blockIdx.x + blockIdx.y * blockDim.x * gridDim.x)/NumDown;
if(threadIdx.x < rows_shared && (s_sv + threadIdx.x) < NumUp)
for(int i=0;i<size_Up;i++)
{
shared[i*rows_shared+threadIdx.x] = Up_data[s_sv + threadIdx.x + i*NumUp];
shared_ind[i*rows_shared+threadIdx.x] = Up_ind[s_sv + threadIdx.x + i*NumUp];
}
__syncthreads();
for(int i=0;i<size_Up;i++)
// result += Up_data[sv+i*NumUp] * x[id + NumDown*Up_ind[sv+i*NumUp]];
result += shared[sv-s_sv+i*rows_shared] * x[id + NumDown*shared_ind[sv-s_sv+i*rows_shared]];
for(int i=0;i<size_Down;i++)
result += Down_data[id+i*NumDown] * x[sv*NumDown + Down_ind[id+i*NumDown]];
y[index] = alpha * y[index] + result;
}
} | .file "tmpxft_000ae64e_00000000-6_gpu_mvprod.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_iiPdS_diiiS_S_PjiS_S0_ii
.type _Z50__device_stub__Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_iiPdS_diiiS_S_PjiS_S0_ii, @function
_Z50__device_stub__Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_iiPdS_diiiS_S_PjiS_S0_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movsd %xmm0, 56(%rsp)
movl %edx, 52(%rsp)
movl %ecx, 48(%rsp)
movl %r8d, 44(%rsp)
movq %r9, 32(%rsp)
movq 288(%rsp), %rax
movq %rax, 24(%rsp)
movq 296(%rsp), %rax
movq %rax, 16(%rsp)
movq 312(%rsp), %rax
movq %rax, 8(%rsp)
movq 320(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 52(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rax
movq %rax, 176(%rsp)
leaq 44(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 24(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 304(%rsp), %rax
movq %rax, 216(%rsp)
leaq 8(%rsp), %rax
movq %rax, 224(%rsp)
movq %rsp, %rax
movq %rax, 232(%rsp)
leaq 328(%rsp), %rax
movq %rax, 240(%rsp)
leaq 336(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 296
pushq 88(%rsp)
.cfi_def_cfa_offset 304
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_iiPdS_diiiS_S_PjiS_S0_ii, .-_Z50__device_stub__Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_iiPdS_diiiS_S_PjiS_S0_ii
.globl _Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii
.type _Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii, @function
_Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 72(%rsp)
.cfi_def_cfa_offset 48
pushq 72(%rsp)
.cfi_def_cfa_offset 56
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
pushq 72(%rsp)
.cfi_def_cfa_offset 72
pushq 72(%rsp)
.cfi_def_cfa_offset 80
call _Z50__device_stub__Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_iiPdS_diiiS_S_PjiS_S0_ii
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii, .-_Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/* Copyright (C) 2012 Ward Poelmans
This file is part of Hubbard-GPU.
Hubbard-GPU is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
Hubbard-GPU is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with Hubbard-GPU. If not, see <http://www.gnu.org/licenses/>.
*/
// number of threads in a block (must be multiple of 32)
#define NUMTHREADS 128
// the maximum size of the grid
#define GRIDSIZE 65535
// Helper macro to check CUDA return values
__global__ void gpu_mvprod(double *x, double *y, double alpha, int NumUp, int NumDown, int dim, double *Umat, double *Down_data,unsigned int *Down_ind, int size_Down, double *Up_data, unsigned int *Up_ind, int size_Up, int rows_shared)
{
int index = threadIdx.x + blockDim.x * blockIdx.x + blockIdx.y * blockDim.x * gridDim.x;
if(index < dim)
{
double result = Umat[index] * x[index];
int sv = index / NumDown; //__fdividef(index,NumDown);
int id = index % NumDown; // index - sv*NumDown;
extern __shared__ double shared[];
unsigned int *shared_ind = (unsigned int *) &shared[size_Up * rows_shared];
int s_sv = (blockDim.x * blockIdx.x + blockIdx.y * blockDim.x * gridDim.x)/NumDown;
if(threadIdx.x < rows_shared && (s_sv + threadIdx.x) < NumUp)
for(int i=0;i<size_Up;i++)
{
shared[i*rows_shared+threadIdx.x] = Up_data[s_sv + threadIdx.x + i*NumUp];
shared_ind[i*rows_shared+threadIdx.x] = Up_ind[s_sv + threadIdx.x + i*NumUp];
}
__syncthreads();
for(int i=0;i<size_Up;i++)
// result += Up_data[sv+i*NumUp] * x[id + NumDown*Up_ind[sv+i*NumUp]];
result += shared[sv-s_sv+i*rows_shared] * x[id + NumDown*shared_ind[sv-s_sv+i*rows_shared]];
for(int i=0;i<size_Down;i++)
result += Down_data[id+i*NumDown] * x[sv*NumDown + Down_ind[id+i*NumDown]];
y[index] = alpha * y[index] + result;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
/* Copyright (C) 2012 Ward Poelmans
This file is part of Hubbard-GPU.
Hubbard-GPU is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
Hubbard-GPU is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with Hubbard-GPU. If not, see <http://www.gnu.org/licenses/>.
*/
// number of threads in a block (must be multiple of 32)
#define NUMTHREADS 128
// the maximum size of the grid
#define GRIDSIZE 65535
// Helper macro to check CUDA return values
__global__ void gpu_mvprod(double *x, double *y, double alpha, int NumUp, int NumDown, int dim, double *Umat, double *Down_data,unsigned int *Down_ind, int size_Down, double *Up_data, unsigned int *Up_ind, int size_Up, int rows_shared)
{
int index = threadIdx.x + blockDim.x * blockIdx.x + blockIdx.y * blockDim.x * gridDim.x;
if(index < dim)
{
double result = Umat[index] * x[index];
int sv = index / NumDown; //__fdividef(index,NumDown);
int id = index % NumDown; // index - sv*NumDown;
extern __shared__ double shared[];
unsigned int *shared_ind = (unsigned int *) &shared[size_Up * rows_shared];
int s_sv = (blockDim.x * blockIdx.x + blockIdx.y * blockDim.x * gridDim.x)/NumDown;
if(threadIdx.x < rows_shared && (s_sv + threadIdx.x) < NumUp)
for(int i=0;i<size_Up;i++)
{
shared[i*rows_shared+threadIdx.x] = Up_data[s_sv + threadIdx.x + i*NumUp];
shared_ind[i*rows_shared+threadIdx.x] = Up_ind[s_sv + threadIdx.x + i*NumUp];
}
__syncthreads();
for(int i=0;i<size_Up;i++)
// result += Up_data[sv+i*NumUp] * x[id + NumDown*Up_ind[sv+i*NumUp]];
result += shared[sv-s_sv+i*rows_shared] * x[id + NumDown*shared_ind[sv-s_sv+i*rows_shared]];
for(int i=0;i<size_Down;i++)
result += Down_data[id+i*NumDown] * x[sv*NumDown + Down_ind[id+i*NumDown]];
y[index] = alpha * y[index] + result;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/* Copyright (C) 2012 Ward Poelmans
This file is part of Hubbard-GPU.
Hubbard-GPU is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
Hubbard-GPU is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with Hubbard-GPU. If not, see <http://www.gnu.org/licenses/>.
*/
// number of threads in a block (must be multiple of 32)
#define NUMTHREADS 128
// the maximum size of the grid
#define GRIDSIZE 65535
// Helper macro to check CUDA return values
__global__ void gpu_mvprod(double *x, double *y, double alpha, int NumUp, int NumDown, int dim, double *Umat, double *Down_data,unsigned int *Down_ind, int size_Down, double *Up_data, unsigned int *Up_ind, int size_Up, int rows_shared)
{
int index = threadIdx.x + blockDim.x * blockIdx.x + blockIdx.y * blockDim.x * gridDim.x;
if(index < dim)
{
double result = Umat[index] * x[index];
int sv = index / NumDown; //__fdividef(index,NumDown);
int id = index % NumDown; // index - sv*NumDown;
extern __shared__ double shared[];
unsigned int *shared_ind = (unsigned int *) &shared[size_Up * rows_shared];
int s_sv = (blockDim.x * blockIdx.x + blockIdx.y * blockDim.x * gridDim.x)/NumDown;
if(threadIdx.x < rows_shared && (s_sv + threadIdx.x) < NumUp)
for(int i=0;i<size_Up;i++)
{
shared[i*rows_shared+threadIdx.x] = Up_data[s_sv + threadIdx.x + i*NumUp];
shared_ind[i*rows_shared+threadIdx.x] = Up_ind[s_sv + threadIdx.x + i*NumUp];
}
__syncthreads();
for(int i=0;i<size_Up;i++)
// result += Up_data[sv+i*NumUp] * x[id + NumDown*Up_ind[sv+i*NumUp]];
result += shared[sv-s_sv+i*rows_shared] * x[id + NumDown*shared_ind[sv-s_sv+i*rows_shared]];
for(int i=0;i<size_Down;i++)
result += Down_data[id+i*NumDown] * x[sv*NumDown + Down_ind[id+i*NumDown]];
y[index] = alpha * y[index] + result;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii
.globl _Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii
.p2align 8
.type _Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii,@function
_Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x6c
s_load_b32 s3, s[0:1], 0x60
s_load_b32 s5, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_mul_i32 s4, s3, s15
s_mul_i32 s14, s14, s2
s_mul_i32 s4, s4, s2
s_mov_b32 s2, exec_lo
v_add3_u32 v1, s4, s14, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_12
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x28
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_clause 0x1
s_load_b32 s10, s[0:1], 0x1c
s_load_b64 s[8:9], s[0:1], 0x58
v_ashrrev_i32_e32 v11, 31, v1
s_add_i32 s4, s4, s14
s_mov_b32 s14, exec_lo
v_lshlrev_b64 v[3:4], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v4, vcc_lo
s_ashr_i32 s11, s10, 31
global_load_b64 v[3:4], v[5:6], off
global_load_b64 v[5:6], v[7:8], off
s_add_i32 s5, s10, s11
v_cvt_f32_u32_e32 v8, s10
s_xor_b32 s12, s5, s11
s_sub_i32 s6, 0, s10
v_cvt_f32_u32_e32 v7, s12
s_sub_i32 s5, 0, s12
v_rcp_iflag_f32_e32 v8, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v7, v7
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v8, 0x4f7ffffe, v8 :: v_dual_mul_f32 v7, 0x4f7ffffe, v7
v_cvt_u32_f32_e32 v8, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v7, v7
v_mul_lo_u32 v9, s5, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s5, v8
v_add_nc_u32_e32 v8, v1, v11
s_mul_i32 s6, s6, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v12, v8, v11
v_mul_hi_u32 v9, v7, v9
s_mul_hi_u32 s6, s5, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s5, s6
s_mul_hi_u32 s5, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s6, s5, s10
v_add_nc_u32_e32 v9, v7, v9
s_sub_i32 s4, s4, s6
s_add_i32 s6, s5, 1
s_sub_i32 s7, s4, s10
s_cmp_ge_u32 s4, s10
v_mad_u64_u32 v[7:8], null, v12, v9, 0
s_cselect_b32 s5, s6, s5
s_cselect_b32 s4, s7, s4
s_add_i32 s6, s5, 1
s_cmp_ge_u32 s4, s10
s_cselect_b32 s13, s6, s5
v_cmpx_gt_u32_e64 s9, v0
s_cbranch_execz .LBB0_5
s_load_b32 s15, s[0:1], 0x18
v_add_nc_u32_e32 v9, s13, v0
s_cmp_gt_i32 s8, 0
s_cselect_b32 s4, -1, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s15, v9
s_and_b32 s4, vcc_lo, s4
s_and_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x48
v_dual_mov_b32 v10, 0 :: v_dual_lshlrev_b32 v7, 2, v0
s_mul_i32 s16, s9, s8
v_lshl_add_u32 v0, v0, 3, 0
s_lshl_b32 s16, s16, 3
s_lshl_b32 s17, s9, 3
v_add3_u32 v7, 0, s16, v7
s_lshl_b32 s16, s9, 2
s_mov_b32 s18, s8
.p2align 6
.LBB0_4:
v_lshlrev_b64 v[13:14], 3, v[9:10]
v_lshlrev_b64 v[15:16], 2, v[9:10]
v_add_nc_u32_e32 v9, s15, v9
s_add_i32 s18, s18, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s18, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v13, vcc_lo, s4, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
v_add_co_u32 v15, vcc_lo, s6, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s7, v16, vcc_lo
global_load_b64 v[13:14], v[13:14], off
global_load_b32 v15, v[15:16], off
s_waitcnt vmcnt(1)
ds_store_b64 v0, v[13:14]
s_waitcnt vmcnt(0)
ds_store_b32 v7, v15
v_add_nc_u32_e32 v7, s16, v7
v_add_nc_u32_e32 v0, s17, v0
s_cbranch_scc1 .LBB0_4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s14
v_mul_lo_u32 v0, v8, s12
s_waitcnt vmcnt(0)
v_mul_f64 v[3:4], v[3:4], v[5:6]
s_cmp_lt_i32 s8, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_sub_nc_u32_e32 v0, v12, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s12, v0
v_cmp_le_u32_e32 vcc_lo, s12, v0
v_dual_cndmask_b32 v0, v0, v5 :: v_dual_add_nc_u32 v7, 1, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v6, v8, v7, vcc_lo
v_xor_b32_e32 v7, s11, v11
v_cmp_le_u32_e32 vcc_lo, s12, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, 1, v6
v_cndmask_b32_e32 v0, v6, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v7
v_sub_nc_u32_e32 v6, v0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v6, s10
v_sub_nc_u32_e32 v5, v1, v0
s_cbranch_scc1 .LBB0_8
v_subrev_nc_u32_e32 v6, s13, v6
s_mul_i32 s4, s9, s8
s_lshl_b32 s5, s9, 3
s_lshl_b32 s4, s4, 3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mov_b32 v8, 0 :: v_dual_lshlrev_b32 v7, 2, v6
v_lshl_add_u32 v6, v6, 3, 0
v_add3_u32 v7, 0, s4, v7
s_lshl_b32 s4, s9, 2
.p2align 6
.LBB0_7:
ds_load_b32 v11, v7
s_add_i32 s8, s8, -1
v_add_nc_u32_e32 v7, s4, v7
s_cmp_eq_u32 s8, 0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[9:10], null, v11, s10, v[5:6]
v_mov_b32_e32 v10, v8
ds_load_b64 v[11:12], v6
v_add_nc_u32_e32 v6, s5, v6
v_lshlrev_b64 v[9:10], 3, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s2, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
global_load_b64 v[9:10], v[9:10], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[3:4], v[11:12], v[9:10], v[3:4]
s_cbranch_scc0 .LBB0_7
.LBB0_8:
s_load_b32 s8, s[0:1], 0x40
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_11
s_load_b128 s[4:7], s[0:1], 0x30
v_mov_b32_e32 v8, 0
.p2align 6
.LBB0_10:
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s8, s8, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s8, 0
v_lshlrev_b64 v[9:10], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v7, v[9:10], off
v_lshlrev_b64 v[9:10], 3, v[5:6]
v_add_nc_u32_e32 v5, s10, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v7, v7, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 3, v[7:8]
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b64 v[9:10], v[9:10], off
global_load_b64 v[6:7], v[6:7], off
s_waitcnt vmcnt(0)
v_fma_f64 v[3:4], v[9:10], v[6:7], v[3:4]
s_cbranch_scc0 .LBB0_10
.LBB0_11:
s_load_b128 s[0:3], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[5:6], v[0:1], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[5:6], s[2:3], v[3:4]
global_store_b64 v[0:1], v[2:3], off
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 352
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 19
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii, .Lfunc_end0-_Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
- .offset: 88
.size: 4
.value_kind: by_value
- .offset: 92
.size: 4
.value_kind: by_value
- .offset: 96
.size: 4
.value_kind: hidden_block_count_x
- .offset: 100
.size: 4
.value_kind: hidden_block_count_y
- .offset: 104
.size: 4
.value_kind: hidden_block_count_z
- .offset: 108
.size: 2
.value_kind: hidden_group_size_x
- .offset: 110
.size: 2
.value_kind: hidden_group_size_y
- .offset: 112
.size: 2
.value_kind: hidden_group_size_z
- .offset: 114
.size: 2
.value_kind: hidden_remainder_x
- .offset: 116
.size: 2
.value_kind: hidden_remainder_y
- .offset: 118
.size: 2
.value_kind: hidden_remainder_z
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 152
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 160
.size: 2
.value_kind: hidden_grid_dims
- .offset: 216
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 352
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii
.private_segment_fixed_size: 0
.sgpr_count: 21
.sgpr_spill_count: 0
.symbol: _Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/* Copyright (C) 2012 Ward Poelmans
This file is part of Hubbard-GPU.
Hubbard-GPU is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
Hubbard-GPU is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with Hubbard-GPU. If not, see <http://www.gnu.org/licenses/>.
*/
// number of threads in a block (must be multiple of 32)
#define NUMTHREADS 128
// the maximum size of the grid
#define GRIDSIZE 65535
// Helper macro to check CUDA return values
__global__ void gpu_mvprod(double *x, double *y, double alpha, int NumUp, int NumDown, int dim, double *Umat, double *Down_data,unsigned int *Down_ind, int size_Down, double *Up_data, unsigned int *Up_ind, int size_Up, int rows_shared)
{
int index = threadIdx.x + blockDim.x * blockIdx.x + blockIdx.y * blockDim.x * gridDim.x;
if(index < dim)
{
double result = Umat[index] * x[index];
int sv = index / NumDown; //__fdividef(index,NumDown);
int id = index % NumDown; // index - sv*NumDown;
extern __shared__ double shared[];
unsigned int *shared_ind = (unsigned int *) &shared[size_Up * rows_shared];
int s_sv = (blockDim.x * blockIdx.x + blockIdx.y * blockDim.x * gridDim.x)/NumDown;
if(threadIdx.x < rows_shared && (s_sv + threadIdx.x) < NumUp)
for(int i=0;i<size_Up;i++)
{
shared[i*rows_shared+threadIdx.x] = Up_data[s_sv + threadIdx.x + i*NumUp];
shared_ind[i*rows_shared+threadIdx.x] = Up_ind[s_sv + threadIdx.x + i*NumUp];
}
__syncthreads();
for(int i=0;i<size_Up;i++)
// result += Up_data[sv+i*NumUp] * x[id + NumDown*Up_ind[sv+i*NumUp]];
result += shared[sv-s_sv+i*rows_shared] * x[id + NumDown*shared_ind[sv-s_sv+i*rows_shared]];
for(int i=0;i<size_Down;i++)
result += Down_data[id+i*NumDown] * x[sv*NumDown + Down_ind[id+i*NumDown]];
y[index] = alpha * y[index] + result;
}
} | .text
.file "gpu_mvprod.hip"
.globl _Z25__device_stub__gpu_mvprodPdS_diiiS_S_PjiS_S0_ii # -- Begin function _Z25__device_stub__gpu_mvprodPdS_diiiS_S_PjiS_S0_ii
.p2align 4, 0x90
.type _Z25__device_stub__gpu_mvprodPdS_diiiS_S_PjiS_S0_ii,@function
_Z25__device_stub__gpu_mvprodPdS_diiiS_S_PjiS_S0_ii: # @_Z25__device_stub__gpu_mvprodPdS_diiiS_S_PjiS_S0_ii
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movsd %xmm0, 72(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rax
movq %rax, 144(%rsp)
leaq 224(%rsp), %rax
movq %rax, 152(%rsp)
leaq 232(%rsp), %rax
movq %rax, 160(%rsp)
leaq 240(%rsp), %rax
movq %rax, 168(%rsp)
leaq 248(%rsp), %rax
movq %rax, 176(%rsp)
leaq 256(%rsp), %rax
movq %rax, 184(%rsp)
leaq 264(%rsp), %rax
movq %rax, 192(%rsp)
leaq 272(%rsp), %rax
movq %rax, 200(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z25__device_stub__gpu_mvprodPdS_diiiS_S_PjiS_S0_ii, .Lfunc_end0-_Z25__device_stub__gpu_mvprodPdS_diiiS_S_PjiS_S0_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii,@object # @_Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii
.section .rodata,"a",@progbits
.globl _Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii
.p2align 3, 0x0
_Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii:
.quad _Z25__device_stub__gpu_mvprodPdS_diiiS_S_PjiS_S0_ii
.size _Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__gpu_mvprodPdS_diiiS_S_PjiS_S0_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ae64e_00000000-6_gpu_mvprod.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_iiPdS_diiiS_S_PjiS_S0_ii
.type _Z50__device_stub__Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_iiPdS_diiiS_S_PjiS_S0_ii, @function
_Z50__device_stub__Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_iiPdS_diiiS_S_PjiS_S0_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movsd %xmm0, 56(%rsp)
movl %edx, 52(%rsp)
movl %ecx, 48(%rsp)
movl %r8d, 44(%rsp)
movq %r9, 32(%rsp)
movq 288(%rsp), %rax
movq %rax, 24(%rsp)
movq 296(%rsp), %rax
movq %rax, 16(%rsp)
movq 312(%rsp), %rax
movq %rax, 8(%rsp)
movq 320(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 52(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rax
movq %rax, 176(%rsp)
leaq 44(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 24(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 304(%rsp), %rax
movq %rax, 216(%rsp)
leaq 8(%rsp), %rax
movq %rax, 224(%rsp)
movq %rsp, %rax
movq %rax, 232(%rsp)
leaq 328(%rsp), %rax
movq %rax, 240(%rsp)
leaq 336(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 296
pushq 88(%rsp)
.cfi_def_cfa_offset 304
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_iiPdS_diiiS_S_PjiS_S0_ii, .-_Z50__device_stub__Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_iiPdS_diiiS_S_PjiS_S0_ii
.globl _Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii
.type _Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii, @function
_Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 72(%rsp)
.cfi_def_cfa_offset 48
pushq 72(%rsp)
.cfi_def_cfa_offset 56
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
pushq 72(%rsp)
.cfi_def_cfa_offset 72
pushq 72(%rsp)
.cfi_def_cfa_offset 80
call _Z50__device_stub__Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_iiPdS_diiiS_S_PjiS_S0_ii
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii, .-_Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_mvprod.hip"
.globl _Z25__device_stub__gpu_mvprodPdS_diiiS_S_PjiS_S0_ii # -- Begin function _Z25__device_stub__gpu_mvprodPdS_diiiS_S_PjiS_S0_ii
.p2align 4, 0x90
.type _Z25__device_stub__gpu_mvprodPdS_diiiS_S_PjiS_S0_ii,@function
_Z25__device_stub__gpu_mvprodPdS_diiiS_S_PjiS_S0_ii: # @_Z25__device_stub__gpu_mvprodPdS_diiiS_S_PjiS_S0_ii
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movsd %xmm0, 72(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rax
movq %rax, 144(%rsp)
leaq 224(%rsp), %rax
movq %rax, 152(%rsp)
leaq 232(%rsp), %rax
movq %rax, 160(%rsp)
leaq 240(%rsp), %rax
movq %rax, 168(%rsp)
leaq 248(%rsp), %rax
movq %rax, 176(%rsp)
leaq 256(%rsp), %rax
movq %rax, 184(%rsp)
leaq 264(%rsp), %rax
movq %rax, 192(%rsp)
leaq 272(%rsp), %rax
movq %rax, 200(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z25__device_stub__gpu_mvprodPdS_diiiS_S_PjiS_S0_ii, .Lfunc_end0-_Z25__device_stub__gpu_mvprodPdS_diiiS_S_PjiS_S0_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii,@object # @_Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii
.section .rodata,"a",@progbits
.globl _Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii
.p2align 3, 0x0
_Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii:
.quad _Z25__device_stub__gpu_mvprodPdS_diiiS_S_PjiS_S0_ii
.size _Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__gpu_mvprodPdS_diiiS_S_PjiS_S0_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10gpu_mvprodPdS_diiiS_S_PjiS_S0_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //xfail:BOOGIE_ERROR
//--gridDim=1 --blockDim=4 --no-inline
//attempt to modify constant memory
#include <stdio.h>
#include <cuda.h>
#define N 2//4
__constant__ int global_constant[N]; //= {0, 1, 2, 3};
__global__ void foo(int *in) {
global_constant[threadIdx.x] = in[threadIdx.x];
__syncthreads();
in[threadIdx.x] = global_constant[threadIdx.x];
} | code for sm_80
Function : _Z3fooPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ BPT.TRAP 0x1 ; /* 0x000000040000795c */
/* 0x000fea0000300000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //xfail:BOOGIE_ERROR
//--gridDim=1 --blockDim=4 --no-inline
//attempt to modify constant memory
#include <stdio.h>
#include <cuda.h>
#define N 2//4
__constant__ int global_constant[N]; //= {0, 1, 2, 3};
__global__ void foo(int *in) {
global_constant[threadIdx.x] = in[threadIdx.x];
__syncthreads();
in[threadIdx.x] = global_constant[threadIdx.x];
} | .file "tmpxft_0013e380_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z3fooPiPi
.type _Z22__device_stub__Z3fooPiPi, @function
_Z22__device_stub__Z3fooPiPi:
.LFB2081:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3fooPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z22__device_stub__Z3fooPiPi, .-_Z22__device_stub__Z3fooPiPi
.globl _Z3fooPi
.type _Z3fooPi, @function
_Z3fooPi:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3fooPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z3fooPi, .-_Z3fooPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3fooPi"
.LC1:
.string "global_constant"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3fooPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL15global_constant(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL15global_constant
.comm _ZL15global_constant,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //xfail:BOOGIE_ERROR
//--gridDim=1 --blockDim=4 --no-inline
//attempt to modify constant memory
#include <stdio.h>
#include <cuda.h>
#define N 2//4
__constant__ int global_constant[N]; //= {0, 1, 2, 3};
__global__ void foo(int *in) {
global_constant[threadIdx.x] = in[threadIdx.x];
__syncthreads();
in[threadIdx.x] = global_constant[threadIdx.x];
} | //xfail:BOOGIE_ERROR
//--gridDim=1 --blockDim=4 --no-inline
//attempt to modify constant memory
#include <stdio.h>
#include <hip/hip_runtime.h>
#define N 2//4
__constant__ int global_constant[N]; //= {0, 1, 2, 3};
__global__ void foo(int *in) {
global_constant[threadIdx.x] = in[threadIdx.x];
__syncthreads();
in[threadIdx.x] = global_constant[threadIdx.x];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //xfail:BOOGIE_ERROR
//--gridDim=1 --blockDim=4 --no-inline
//attempt to modify constant memory
#include <stdio.h>
#include <hip/hip_runtime.h>
#define N 2//4
__constant__ int global_constant[N]; //= {0, 1, 2, 3};
__global__ void foo(int *in) {
global_constant[threadIdx.x] = in[threadIdx.x];
__syncthreads();
in[threadIdx.x] = global_constant[threadIdx.x];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3fooPi
.globl _Z3fooPi
.p2align 8
.type _Z3fooPi,@function
_Z3fooPi:
v_lshlrev_b32_e32 v0, 2, v0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, global_constant@rel32@lo+4
s_addc_u32 s3, s3, global_constant@rel32@hi+12
s_barrier
buffer_gl0_inv
global_load_b32 v1, v0, s[2:3]
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3fooPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3fooPi, .Lfunc_end0-_Z3fooPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected global_constant
.type global_constant,@object
.section .bss,"aw",@nobits
.globl global_constant
.p2align 2, 0x0
global_constant:
.zero 8
.size global_constant, 8
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym global_constant
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3fooPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3fooPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //xfail:BOOGIE_ERROR
//--gridDim=1 --blockDim=4 --no-inline
//attempt to modify constant memory
#include <stdio.h>
#include <hip/hip_runtime.h>
#define N 2//4
__constant__ int global_constant[N]; //= {0, 1, 2, 3};
__global__ void foo(int *in) {
global_constant[threadIdx.x] = in[threadIdx.x];
__syncthreads();
in[threadIdx.x] = global_constant[threadIdx.x];
} | .text
.file "main.hip"
.globl _Z18__device_stub__fooPi # -- Begin function _Z18__device_stub__fooPi
.p2align 4, 0x90
.type _Z18__device_stub__fooPi,@function
_Z18__device_stub__fooPi: # @_Z18__device_stub__fooPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3fooPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z18__device_stub__fooPi, .Lfunc_end0-_Z18__device_stub__fooPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3fooPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $global_constant, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type global_constant,@object # @global_constant
.local global_constant
.comm global_constant,8,4
.type _Z3fooPi,@object # @_Z3fooPi
.section .rodata,"a",@progbits
.globl _Z3fooPi
.p2align 3, 0x0
_Z3fooPi:
.quad _Z18__device_stub__fooPi
.size _Z3fooPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3fooPi"
.size .L__unnamed_1, 9
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "global_constant"
.size .L__unnamed_2, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__fooPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym global_constant
.addrsig_sym _Z3fooPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3fooPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ BPT.TRAP 0x1 ; /* 0x000000040000795c */
/* 0x000fea0000300000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3fooPi
.globl _Z3fooPi
.p2align 8
.type _Z3fooPi,@function
_Z3fooPi:
v_lshlrev_b32_e32 v0, 2, v0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, global_constant@rel32@lo+4
s_addc_u32 s3, s3, global_constant@rel32@hi+12
s_barrier
buffer_gl0_inv
global_load_b32 v1, v0, s[2:3]
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3fooPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3fooPi, .Lfunc_end0-_Z3fooPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected global_constant
.type global_constant,@object
.section .bss,"aw",@nobits
.globl global_constant
.p2align 2, 0x0
global_constant:
.zero 8
.size global_constant, 8
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym global_constant
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3fooPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3fooPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013e380_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z3fooPiPi
.type _Z22__device_stub__Z3fooPiPi, @function
_Z22__device_stub__Z3fooPiPi:
.LFB2081:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3fooPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z22__device_stub__Z3fooPiPi, .-_Z22__device_stub__Z3fooPiPi
.globl _Z3fooPi
.type _Z3fooPi, @function
_Z3fooPi:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3fooPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z3fooPi, .-_Z3fooPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3fooPi"
.LC1:
.string "global_constant"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3fooPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL15global_constant(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL15global_constant
.comm _ZL15global_constant,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z18__device_stub__fooPi # -- Begin function _Z18__device_stub__fooPi
.p2align 4, 0x90
.type _Z18__device_stub__fooPi,@function
_Z18__device_stub__fooPi: # @_Z18__device_stub__fooPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3fooPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z18__device_stub__fooPi, .Lfunc_end0-_Z18__device_stub__fooPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3fooPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $global_constant, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type global_constant,@object # @global_constant
.local global_constant
.comm global_constant,8,4
.type _Z3fooPi,@object # @_Z3fooPi
.section .rodata,"a",@progbits
.globl _Z3fooPi
.p2align 3, 0x0
_Z3fooPi:
.quad _Z18__device_stub__fooPi
.size _Z3fooPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3fooPi"
.size .L__unnamed_1, 9
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "global_constant"
.size .L__unnamed_2, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__fooPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym global_constant
.addrsig_sym _Z3fooPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdio>
#define cudaCheckError() { \
cudaError_t e=cudaGetLastError(); \
if(e!=cudaSuccess) { \
printf("Cuda failure %s:%d: '%s'\n",__FILE__,__LINE__,cudaGetErrorString(e)); \
exit(EXIT_FAILURE); \
} \
}
// Simple vector initialization; element at index i receives value i.
// This is a good alternative to cudaMemset which write bytes only.
__global__ void vecinit(int *a, int N) {
int i = blockDim.x * blockIdx.x + threadIdx.x; // FIXME derive from block and thread info the index of the value to set
if (i < N) // FIXME check we stay within buffer's bound
a[i] = i; // keep this line
}
int main() {
int N=4097;
int threads=128;
int blocks=(N+threads-1)/threads; //
int *a;
// The "managed" allocation below allows the same pointer to be used by
// device and host code. Available since CUDA 6, Unified Memory is supported
// starting with the Kepler GPU architecture (Compute Capability 3.0 or higher).
// More details: https://devblogs.nvidia.com/unified-memory-in-cuda-6/
cudaMallocManaged(&a,N*sizeof(int));
vecinit<<<blocks,threads>>>(a, N);
cudaDeviceSynchronize(); // This is still needed when using Unified Memory
bool error = false;
for(int i=0;i<N;i++)
if (error = a[i] != i) {
printf("ERROR at index %d: expected %d, got %d\n", i, i, a[i]);
break;
}
cudaCheckError();
if (!error) {
printf("Test completed successfully.\n");
return 0;
} else {
printf("WARNING there were some errors.\n");
return 1;
}
} | code for sm_80
Function : _Z7vecinitPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fca00078e0202 */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
#define cudaCheckError() { \
cudaError_t e=cudaGetLastError(); \
if(e!=cudaSuccess) { \
printf("Cuda failure %s:%d: '%s'\n",__FILE__,__LINE__,cudaGetErrorString(e)); \
exit(EXIT_FAILURE); \
} \
}
// Simple vector initialization; element at index i receives value i.
// This is a good alternative to cudaMemset which write bytes only.
__global__ void vecinit(int *a, int N) {
int i = blockDim.x * blockIdx.x + threadIdx.x; // FIXME derive from block and thread info the index of the value to set
if (i < N) // FIXME check we stay within buffer's bound
a[i] = i; // keep this line
}
int main() {
int N=4097;
int threads=128;
int blocks=(N+threads-1)/threads; //
int *a;
// The "managed" allocation below allows the same pointer to be used by
// device and host code. Available since CUDA 6, Unified Memory is supported
// starting with the Kepler GPU architecture (Compute Capability 3.0 or higher).
// More details: https://devblogs.nvidia.com/unified-memory-in-cuda-6/
cudaMallocManaged(&a,N*sizeof(int));
vecinit<<<blocks,threads>>>(a, N);
cudaDeviceSynchronize(); // This is still needed when using Unified Memory
bool error = false;
for(int i=0;i<N;i++)
if (error = a[i] != i) {
printf("ERROR at index %d: expected %d, got %d\n", i, i, a[i]);
break;
}
cudaCheckError();
if (!error) {
printf("Test completed successfully.\n");
return 0;
} else {
printf("WARNING there were some errors.\n");
return 1;
}
} | .file "tmpxft_0003c5c8_00000000-6_1-vec_init.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z7vecinitPiiPii
.type _Z27__device_stub__Z7vecinitPiiPii, @function
_Z27__device_stub__Z7vecinitPiiPii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7vecinitPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z7vecinitPiiPii, .-_Z27__device_stub__Z7vecinitPiiPii
.globl _Z7vecinitPii
.type _Z7vecinitPii, @function
_Z7vecinitPii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7vecinitPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7vecinitPii, .-_Z7vecinitPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "ERROR at index %d: expected %d, got %d\n"
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/Shubh023/IRGPU/main/Part1/TP_0.4_-_Kernel_programming/student_resources/1-vec_init.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Cuda failure %s:%d: '%s'\n"
.LC3:
.string "Test completed successfully.\n"
.section .rodata.str1.8
.align 8
.LC4:
.string "WARNING there were some errors.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $16388, %esi
call cudaMallocManaged@PLT
movl $128, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $33, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L12:
call cudaDeviceSynchronize@PLT
movq 8(%rsp), %rax
movl $0, %edx
.L16:
movl (%rax,%rdx,4), %r8d
cmpl %edx, %r8d
jne .L24
addq $1, %rdx
cmpq $4097, %rdx
jne .L16
call cudaGetLastError@PLT
testl %eax, %eax
jne .L14
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L11:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L25
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $4097, %esi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z7vecinitPiiPii
jmp .L12
.L24:
movl %edx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L14
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L11
.L14:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $40, %ecx
leaq .LC1(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z7vecinitPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z7vecinitPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#define cudaCheckError() { \
cudaError_t e=cudaGetLastError(); \
if(e!=cudaSuccess) { \
printf("Cuda failure %s:%d: '%s'\n",__FILE__,__LINE__,cudaGetErrorString(e)); \
exit(EXIT_FAILURE); \
} \
}
// Simple vector initialization; element at index i receives value i.
// This is a good alternative to cudaMemset which write bytes only.
__global__ void vecinit(int *a, int N) {
int i = blockDim.x * blockIdx.x + threadIdx.x; // FIXME derive from block and thread info the index of the value to set
if (i < N) // FIXME check we stay within buffer's bound
a[i] = i; // keep this line
}
int main() {
int N=4097;
int threads=128;
int blocks=(N+threads-1)/threads; //
int *a;
// The "managed" allocation below allows the same pointer to be used by
// device and host code. Available since CUDA 6, Unified Memory is supported
// starting with the Kepler GPU architecture (Compute Capability 3.0 or higher).
// More details: https://devblogs.nvidia.com/unified-memory-in-cuda-6/
cudaMallocManaged(&a,N*sizeof(int));
vecinit<<<blocks,threads>>>(a, N);
cudaDeviceSynchronize(); // This is still needed when using Unified Memory
bool error = false;
for(int i=0;i<N;i++)
if (error = a[i] != i) {
printf("ERROR at index %d: expected %d, got %d\n", i, i, a[i]);
break;
}
cudaCheckError();
if (!error) {
printf("Test completed successfully.\n");
return 0;
} else {
printf("WARNING there were some errors.\n");
return 1;
}
} | #include <hip/hip_runtime.h>
#include <cstdio>
#define cudaCheckError() { \
hipError_t e=hipGetLastError(); \
if(e!=hipSuccess) { \
printf("Cuda failure %s:%d: '%s'\n",__FILE__,__LINE__,hipGetErrorString(e)); \
exit(EXIT_FAILURE); \
} \
}
// Simple vector initialization; element at index i receives value i.
// This is a good alternative to cudaMemset which write bytes only.
__global__ void vecinit(int *a, int N) {
int i = blockDim.x * blockIdx.x + threadIdx.x; // FIXME derive from block and thread info the index of the value to set
if (i < N) // FIXME check we stay within buffer's bound
a[i] = i; // keep this line
}
int main() {
int N=4097;
int threads=128;
int blocks=(N+threads-1)/threads; //
int *a;
// The "managed" allocation below allows the same pointer to be used by
// device and host code. Available since CUDA 6, Unified Memory is supported
// starting with the Kepler GPU architecture (Compute Capability 3.0 or higher).
// More details: https://devblogs.nvidia.com/unified-memory-in-cuda-6/
hipMallocManaged(&a,N*sizeof(int));
vecinit<<<blocks,threads>>>(a, N);
hipDeviceSynchronize(); // This is still needed when using Unified Memory
bool error = false;
for(int i=0;i<N;i++)
if (error = a[i] != i) {
printf("ERROR at index %d: expected %d, got %d\n", i, i, a[i]);
break;
}
cudaCheckError();
if (!error) {
printf("Test completed successfully.\n");
return 0;
} else {
printf("WARNING there were some errors.\n");
return 1;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#define cudaCheckError() { \
hipError_t e=hipGetLastError(); \
if(e!=hipSuccess) { \
printf("Cuda failure %s:%d: '%s'\n",__FILE__,__LINE__,hipGetErrorString(e)); \
exit(EXIT_FAILURE); \
} \
}
// Simple vector initialization; element at index i receives value i.
// This is a good alternative to cudaMemset which write bytes only.
__global__ void vecinit(int *a, int N) {
int i = blockDim.x * blockIdx.x + threadIdx.x; // FIXME derive from block and thread info the index of the value to set
if (i < N) // FIXME check we stay within buffer's bound
a[i] = i; // keep this line
}
int main() {
int N=4097;
int threads=128;
int blocks=(N+threads-1)/threads; //
int *a;
// The "managed" allocation below allows the same pointer to be used by
// device and host code. Available since CUDA 6, Unified Memory is supported
// starting with the Kepler GPU architecture (Compute Capability 3.0 or higher).
// More details: https://devblogs.nvidia.com/unified-memory-in-cuda-6/
hipMallocManaged(&a,N*sizeof(int));
vecinit<<<blocks,threads>>>(a, N);
hipDeviceSynchronize(); // This is still needed when using Unified Memory
bool error = false;
for(int i=0;i<N;i++)
if (error = a[i] != i) {
printf("ERROR at index %d: expected %d, got %d\n", i, i, a[i]);
break;
}
cudaCheckError();
if (!error) {
printf("Test completed successfully.\n");
return 0;
} else {
printf("WARNING there were some errors.\n");
return 1;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7vecinitPii
.globl _Z7vecinitPii
.p2align 8
.type _Z7vecinitPii,@function
_Z7vecinitPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7vecinitPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7vecinitPii, .Lfunc_end0-_Z7vecinitPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7vecinitPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7vecinitPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#define cudaCheckError() { \
hipError_t e=hipGetLastError(); \
if(e!=hipSuccess) { \
printf("Cuda failure %s:%d: '%s'\n",__FILE__,__LINE__,hipGetErrorString(e)); \
exit(EXIT_FAILURE); \
} \
}
// Simple vector initialization; element at index i receives value i.
// This is a good alternative to cudaMemset which write bytes only.
__global__ void vecinit(int *a, int N) {
int i = blockDim.x * blockIdx.x + threadIdx.x; // FIXME derive from block and thread info the index of the value to set
if (i < N) // FIXME check we stay within buffer's bound
a[i] = i; // keep this line
}
int main() {
int N=4097;
int threads=128;
int blocks=(N+threads-1)/threads; //
int *a;
// The "managed" allocation below allows the same pointer to be used by
// device and host code. Available since CUDA 6, Unified Memory is supported
// starting with the Kepler GPU architecture (Compute Capability 3.0 or higher).
// More details: https://devblogs.nvidia.com/unified-memory-in-cuda-6/
hipMallocManaged(&a,N*sizeof(int));
vecinit<<<blocks,threads>>>(a, N);
hipDeviceSynchronize(); // This is still needed when using Unified Memory
bool error = false;
for(int i=0;i<N;i++)
if (error = a[i] != i) {
printf("ERROR at index %d: expected %d, got %d\n", i, i, a[i]);
break;
}
cudaCheckError();
if (!error) {
printf("Test completed successfully.\n");
return 0;
} else {
printf("WARNING there were some errors.\n");
return 1;
}
} | .text
.file "1-vec_init.hip"
.globl _Z22__device_stub__vecinitPii # -- Begin function _Z22__device_stub__vecinitPii
.p2align 4, 0x90
.type _Z22__device_stub__vecinitPii,@function
_Z22__device_stub__vecinitPii: # @_Z22__device_stub__vecinitPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7vecinitPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__vecinitPii, .Lfunc_end0-_Z22__device_stub__vecinitPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 16(%rsp), %rdi
movl $16388, %esi # imm = 0x4004
movl $1, %edx
callq hipMallocManaged
movabsq $4294967329, %rdi # imm = 0x100000021
leaq 95(%rdi), %rdx
xorl %ebx, %ebx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $4097, 12(%rsp) # imm = 0x1001
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7vecinitPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq 16(%rsp), %rax
movl (%rax), %ecx
movb $1, %bpl
testl %ecx, %ecx
jne .LBB1_7
# %bb.3: # %.lr.ph.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpq $4096, %rbx # imm = 0x1000
je .LBB1_8
# %bb.5: # in Loop: Header=BB1_4 Depth=1
movl 4(%rax,%rbx,4), %ecx
incq %rbx
cmpq %rcx, %rbx
je .LBB1_4
# %bb.6: # %._crit_edge
leaq -1(%rbx), %rax
cmpq $4096, %rax # imm = 0x1000
setb %bpl
.LBB1_7:
movl $.L.str, %edi
movl %ebx, %esi
movl %ebx, %edx
# kill: def $ecx killed $ecx killed $rcx
xorl %eax, %eax
callq printf
.LBB1_9: # %.loopexit
callq hipGetLastError
testl %eax, %eax
jne .LBB1_11
# %bb.10:
movl $.Lstr.1, %eax
movl $.Lstr, %edi
testb %bpl, %bpl
cmovneq %rax, %rdi
movzbl %bpl, %ebx
callq puts@PLT
movl %ebx, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_8: # %.loopexit.loopexit
.cfi_def_cfa_offset 128
setb %bpl
jmp .LBB1_9
.LBB1_11:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movl $.L.str.2, %esi
movl $42, %edx
movq %rax, %rcx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7vecinitPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7vecinitPii,@object # @_Z7vecinitPii
.section .rodata,"a",@progbits
.globl _Z7vecinitPii
.p2align 3, 0x0
_Z7vecinitPii:
.quad _Z22__device_stub__vecinitPii
.size _Z7vecinitPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "ERROR at index %d: expected %d, got %d\n"
.size .L.str, 40
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Cuda failure %s:%d: '%s'\n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/Shubh023/IRGPU/main/Part1/TP_0.4_-_Kernel_programming/student_resources/1-vec_init.hip"
.size .L.str.2, 144
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7vecinitPii"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Test completed successfully."
.size .Lstr, 29
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "WARNING there were some errors."
.size .Lstr.1, 32
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__vecinitPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7vecinitPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7vecinitPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fca00078e0202 */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7vecinitPii
.globl _Z7vecinitPii
.p2align 8
.type _Z7vecinitPii,@function
_Z7vecinitPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7vecinitPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7vecinitPii, .Lfunc_end0-_Z7vecinitPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7vecinitPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7vecinitPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003c5c8_00000000-6_1-vec_init.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z7vecinitPiiPii
.type _Z27__device_stub__Z7vecinitPiiPii, @function
_Z27__device_stub__Z7vecinitPiiPii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7vecinitPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z7vecinitPiiPii, .-_Z27__device_stub__Z7vecinitPiiPii
.globl _Z7vecinitPii
.type _Z7vecinitPii, @function
_Z7vecinitPii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7vecinitPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7vecinitPii, .-_Z7vecinitPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "ERROR at index %d: expected %d, got %d\n"
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/Shubh023/IRGPU/main/Part1/TP_0.4_-_Kernel_programming/student_resources/1-vec_init.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Cuda failure %s:%d: '%s'\n"
.LC3:
.string "Test completed successfully.\n"
.section .rodata.str1.8
.align 8
.LC4:
.string "WARNING there were some errors.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $16388, %esi
call cudaMallocManaged@PLT
movl $128, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $33, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L12:
call cudaDeviceSynchronize@PLT
movq 8(%rsp), %rax
movl $0, %edx
.L16:
movl (%rax,%rdx,4), %r8d
cmpl %edx, %r8d
jne .L24
addq $1, %rdx
cmpq $4097, %rdx
jne .L16
call cudaGetLastError@PLT
testl %eax, %eax
jne .L14
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L11:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L25
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $4097, %esi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z7vecinitPiiPii
jmp .L12
.L24:
movl %edx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L14
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L11
.L14:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $40, %ecx
leaq .LC1(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z7vecinitPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z7vecinitPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "1-vec_init.hip"
.globl _Z22__device_stub__vecinitPii # -- Begin function _Z22__device_stub__vecinitPii
.p2align 4, 0x90
.type _Z22__device_stub__vecinitPii,@function
_Z22__device_stub__vecinitPii: # @_Z22__device_stub__vecinitPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7vecinitPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__vecinitPii, .Lfunc_end0-_Z22__device_stub__vecinitPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 16(%rsp), %rdi
movl $16388, %esi # imm = 0x4004
movl $1, %edx
callq hipMallocManaged
movabsq $4294967329, %rdi # imm = 0x100000021
leaq 95(%rdi), %rdx
xorl %ebx, %ebx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $4097, 12(%rsp) # imm = 0x1001
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7vecinitPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq 16(%rsp), %rax
movl (%rax), %ecx
movb $1, %bpl
testl %ecx, %ecx
jne .LBB1_7
# %bb.3: # %.lr.ph.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpq $4096, %rbx # imm = 0x1000
je .LBB1_8
# %bb.5: # in Loop: Header=BB1_4 Depth=1
movl 4(%rax,%rbx,4), %ecx
incq %rbx
cmpq %rcx, %rbx
je .LBB1_4
# %bb.6: # %._crit_edge
leaq -1(%rbx), %rax
cmpq $4096, %rax # imm = 0x1000
setb %bpl
.LBB1_7:
movl $.L.str, %edi
movl %ebx, %esi
movl %ebx, %edx
# kill: def $ecx killed $ecx killed $rcx
xorl %eax, %eax
callq printf
.LBB1_9: # %.loopexit
callq hipGetLastError
testl %eax, %eax
jne .LBB1_11
# %bb.10:
movl $.Lstr.1, %eax
movl $.Lstr, %edi
testb %bpl, %bpl
cmovneq %rax, %rdi
movzbl %bpl, %ebx
callq puts@PLT
movl %ebx, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_8: # %.loopexit.loopexit
.cfi_def_cfa_offset 128
setb %bpl
jmp .LBB1_9
.LBB1_11:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movl $.L.str.2, %esi
movl $42, %edx
movq %rax, %rcx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7vecinitPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7vecinitPii,@object # @_Z7vecinitPii
.section .rodata,"a",@progbits
.globl _Z7vecinitPii
.p2align 3, 0x0
_Z7vecinitPii:
.quad _Z22__device_stub__vecinitPii
.size _Z7vecinitPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "ERROR at index %d: expected %d, got %d\n"
.size .L.str, 40
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Cuda failure %s:%d: '%s'\n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/Shubh023/IRGPU/main/Part1/TP_0.4_-_Kernel_programming/student_resources/1-vec_init.hip"
.size .L.str.2, 144
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7vecinitPii"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Test completed successfully."
.size .Lstr, 29
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "WARNING there were some errors."
.size .Lstr.1, 32
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__vecinitPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7vecinitPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/* This code will generate a fractal image. Uses OpenCV, to compile:
nvcc CudaFinal.cu `pkg-config --cflags --libs opencv` */
typedef enum color {BLUE, GREEN, RED} Color;
__global__ void convert_to_hsv(unsigned char *src, float *hsv, int width, int heigth, int step, int channels) {
float r, g, b;
float h, s, v;
int ren,col;
ren = blockIdx.x;
col = threadIdx.x;
r = src[(ren * step) + (col * channels) + RED] / 255.0f;
g = src[(ren * step) + (col * channels) + GREEN] / 255.0f;
b = src[(ren * step) + (col * channels) + BLUE] / 255.0f;
float max = fmax(r, fmax(g, b));
float min = fmin(r, fmin(g, b));
float diff = max - min;
v = max;
if(v == 0.0f) { // black
h = s = 0.0f;
} else {
s = diff / v;
if(diff < 0.001f) { // grey
h = 0.0f;
} else { // color
if(max == r) {
h = 60.0f * (g - b)/diff;
if(h < 0.0f) { h += 360.0f; }
} else if(max == g) {
h = 60.0f * (2 + (b - r)/diff);
} else {
h = 60.0f * (4 + (r - g)/diff);
}
}
}
// confusion line
float minh=40.0f;
float maxh=200.0f;
float minis = 0;
float maxs = 100;
float miniv = 0;
float maxv = 100;
// if conditionals to check the color blindness line, if the pixel is in this line i change the color to other color base shifting the h
if (h > minh && h < maxh && s > minis && s < maxs && v > miniv && v < maxv){
hsv[(ren * step) + (col * channels) + RED] = (float) (h + 140.0f);
hsv[(ren * step) + (col * channels) + GREEN] = (float) (s);
hsv[(ren * step) + (col * channels) + BLUE] = (float) (v);
} else { // this keep the pixel if it is out of the color blindnessline
hsv[(ren * step) + (col * channels) + RED] = (float) (h);
hsv[(ren * step) + (col * channels) + GREEN] = (float) (s);
hsv[(ren * step) + (col * channels) + BLUE] = (float) (v);
}
} | code for sm_80
Function : _Z14convert_to_hsvPhPfiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x178], RZ ; /* 0x00005e0000007a24 */
/* 0x001fc800078e02ff */
/*0050*/ IMAD R0, R3, c[0x0][0x17c], R0 ; /* 0x00005f0003007a24 */
/* 0x002fca00078e0200 */
/*0060*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f1e0ff */
/*0070*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f0eff */
/*0080*/ LDG.E.U8 R5, [R2.64+0x2] ; /* 0x0000020402057981 */
/* 0x000ea2000c1e1100 */
/*0090*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3b808081 ; /* 0x3b808081ff077424 */
/* 0x000fe200078e00ff */
/*00a0*/ BSSY B0, 0x1a0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*00b0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x437f0000 ; /* 0x437f0000ff047424 */
/* 0x000fc800078e00ff */
/*00c0*/ FFMA R4, R7, -R4, 1 ; /* 0x3f80000007047423 */
/* 0x000fc80000000804 */
/*00d0*/ FFMA R4, R4, R7, 0.0039215688593685626984 ; /* 0x3b80808104047423 */
/* 0x000fe20000000007 */
/*00e0*/ I2F.U16 R5, R5 ; /* 0x0000000500057306 */
/* 0x004e300000101000 */
/*00f0*/ FCHK P0, R5, 255 ; /* 0x437f000005007902 */
/* 0x001e220000000000 */
/*0100*/ FFMA R6, R5, R4, RZ ; /* 0x0000000405067223 */
/* 0x000fc800000000ff */
/*0110*/ FFMA R7, R6, -255, R5 ; /* 0xc37f000006077823 */
/* 0x000fc80000000005 */
/*0120*/ FFMA R4, R4, R7, R6 ; /* 0x0000000704047223 */
/* 0x000fe20000000006 */
/*0130*/ @!P0 BRA 0x190 ; /* 0x0000005000008947 */
/* 0x001fea0003800000 */
/*0140*/ MOV R13, R5 ; /* 0x00000005000d7202 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD.MOV.U32 R14, RZ, RZ, 0x437f0000 ; /* 0x437f0000ff0e7424 */
/* 0x000fe200078e00ff */
/*0160*/ MOV R10, 0x180 ; /* 0x00000180000a7802 */
/* 0x000fe40000000f00 */
/*0170*/ CALL.REL.NOINC 0xa10 ; /* 0x0000089000007944 */
/* 0x000fea0003c00000 */
/*0180*/ IMAD.MOV.U32 R4, RZ, RZ, R9 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0009 */
/*0190*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01a0*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*01b0*/ HFMA2.MMA R5, -RZ, RZ, 0.9375, -7.688999176025390625e-06 ; /* 0x3b808081ff057435 */
/* 0x000fe200000001ff */
/*01c0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x437f0000 ; /* 0x437f0000ff087424 */
/* 0x000fe200078e00ff */
/*01d0*/ BSSY B0, 0x2c0 ; /* 0x000000e000007945 */
/* 0x000ff00003800000 */
/*01e0*/ FFMA R8, R5, -R8, 1 ; /* 0x3f80000005087423 */
/* 0x000fc80000000808 */
/*01f0*/ FFMA R7, R8, R5, 0.0039215688593685626984 ; /* 0x3b80808108077423 */
/* 0x000fe20000000005 */
/*0200*/ I2F.U16 R6, R6 ; /* 0x0000000600067306 */
/* 0x004e300000101000 */
/*0210*/ FCHK P0, R6, 255 ; /* 0x437f000006007902 */
/* 0x001e220000000000 */
/*0220*/ FFMA R5, R7, R6, RZ ; /* 0x0000000607057223 */
/* 0x000fc800000000ff */
/*0230*/ FFMA R8, R5, -255, R6 ; /* 0xc37f000005087823 */
/* 0x000fc80000000006 */
/*0240*/ FFMA R5, R7, R8, R5 ; /* 0x0000000807057223 */
/* 0x000fe20000000005 */
/*0250*/ @!P0 BRA 0x2b0 ; /* 0x0000005000008947 */
/* 0x001fea0003800000 */
/*0260*/ IMAD.MOV.U32 R13, RZ, RZ, R6 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0006 */
/*0270*/ MOV R14, 0x437f0000 ; /* 0x437f0000000e7802 */
/* 0x000fe40000000f00 */
/*0280*/ MOV R10, 0x2a0 ; /* 0x000002a0000a7802 */
/* 0x000fe40000000f00 */
/*0290*/ CALL.REL.NOINC 0xa10 ; /* 0x0000077000007944 */
/* 0x000fea0003c00000 */
/*02a0*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x001fe400078e0009 */
/*02b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02c0*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1100 */
/*02d0*/ MOV R8, 0x437f0000 ; /* 0x437f000000087802 */
/* 0x000fe20000000f00 */
/*02e0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3b808081 ; /* 0x3b808081ff077424 */
/* 0x000fe200078e00ff */
/*02f0*/ BSSY B0, 0x3e0 ; /* 0x000000e000007945 */
/* 0x000fe60003800000 */
/*0300*/ FFMA R8, R7, -R8, 1 ; /* 0x3f80000007087423 */
/* 0x000fc80000000808 */
/*0310*/ FFMA R9, R8, R7, 0.0039215688593685626984 ; /* 0x3b80808108097423 */
/* 0x000fe20000000007 */
/*0320*/ I2F.U16 R6, R2 ; /* 0x0000000200067306 */
/* 0x004e300000101000 */
/*0330*/ FCHK P0, R6, 255 ; /* 0x437f000006007902 */
/* 0x001e220000000000 */
/*0340*/ FFMA R7, R9, R6, RZ ; /* 0x0000000609077223 */
/* 0x000fc800000000ff */
/*0350*/ FFMA R8, R7, -255, R6 ; /* 0xc37f000007087823 */
/* 0x000fc80000000006 */
/*0360*/ FFMA R8, R9, R8, R7 ; /* 0x0000000809087223 */
/* 0x000fe20000000007 */
/*0370*/ @!P0 BRA 0x3d0 ; /* 0x0000005000008947 */
/* 0x001fea0003800000 */
/*0380*/ IMAD.MOV.U32 R13, RZ, RZ, R6 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0006 */
/*0390*/ MOV R10, 0x3c0 ; /* 0x000003c0000a7802 */
/* 0x000fe20000000f00 */
/*03a0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x437f0000 ; /* 0x437f0000ff0e7424 */
/* 0x000fe400078e00ff */
/*03b0*/ CALL.REL.NOINC 0xa10 ; /* 0x0000065000007944 */
/* 0x000fea0003c00000 */
/*03c0*/ MOV R8, R9 ; /* 0x0000000900087202 */
/* 0x001fe40000000f00 */
/*03d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03e0*/ FMNMX R3, R8, R5, !PT ; /* 0x0000000508037209 */
/* 0x000fe20007800000 */
/*03f0*/ BSSY B0, 0x930 ; /* 0x0000053000007945 */
/* 0x000fe20003800000 */
/*0400*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe4000001ff00 */
/*0410*/ FMNMX R2, R3, R4, !PT ; /* 0x0000000403027209 */
/* 0x000fc80007800000 */
/*0420*/ FSETP.NEU.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x000fda0003f0d000 */
/*0430*/ @!P0 BRA 0x920 ; /* 0x000004e000008947 */
/* 0x000fea0003800000 */
/*0440*/ MUFU.RCP R9, R2 ; /* 0x0000000200097308 */
/* 0x000e220000001000 */
/*0450*/ FMNMX R3, R8, R5, PT ; /* 0x0000000508037209 */
/* 0x000fe20003800000 */
/*0460*/ BSSY B1, 0x560 ; /* 0x000000f000017945 */
/* 0x000fe60003800000 */
/*0470*/ FMNMX R3, R3, R4, PT ; /* 0x0000000403037209 */
/* 0x000fca0003800000 */
/*0480*/ FADD R3, R2, -R3 ; /* 0x8000000302037221 */
/* 0x000fc80000000000 */
/*0490*/ FCHK P0, R3, R2 ; /* 0x0000000203007302 */
/* 0x000e620000000000 */
/*04a0*/ FFMA R6, -R2, R9, 1 ; /* 0x3f80000002067423 */
/* 0x001fc80000000109 */
/*04b0*/ FFMA R6, R9, R6, R9 ; /* 0x0000000609067223 */
/* 0x000fc80000000009 */
/*04c0*/ FFMA R9, R3, R6, RZ ; /* 0x0000000603097223 */
/* 0x000fc800000000ff */
/*04d0*/ FFMA R10, -R2, R9, R3 ; /* 0x00000009020a7223 */
/* 0x000fc80000000103 */
/*04e0*/ FFMA R6, R6, R10, R9 ; /* 0x0000000a06067223 */
/* 0x000fe20000000009 */
/*04f0*/ @!P0 BRA 0x550 ; /* 0x0000005000008947 */
/* 0x002fea0003800000 */
/*0500*/ IMAD.MOV.U32 R13, RZ, RZ, R3 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0003 */
/*0510*/ MOV R10, 0x540 ; /* 0x00000540000a7802 */
/* 0x000fe20000000f00 */
/*0520*/ IMAD.MOV.U32 R14, RZ, RZ, R2 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0002 */
/*0530*/ CALL.REL.NOINC 0xa10 ; /* 0x000004d000007944 */
/* 0x000fea0003c00000 */
/*0540*/ MOV R6, R9 ; /* 0x0000000900067202 */
/* 0x001fe40000000f00 */
/*0550*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0560*/ FSETP.GEU.AND P0, PT, R3, 0.0010000000474974513054, PT ; /* 0x3a83126f0300780b */
/* 0x000fda0003f0e000 */
/*0570*/ @!P0 BRA 0x920 ; /* 0x000003a000008947 */
/* 0x000fea0003800000 */
/*0580*/ FSETP.NEU.AND P0, PT, R2, R4, PT ; /* 0x000000040200720b */
/* 0x000fda0003f0d000 */
/*0590*/ @!P0 BRA 0x800 ; /* 0x0000026000008947 */
/* 0x000fea0003800000 */
/*05a0*/ FSETP.NEU.AND P0, PT, R2, R5, PT ; /* 0x000000050200720b */
/* 0x000fda0003f0d000 */
/*05b0*/ @!P0 BRA 0x6e0 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*05c0*/ MUFU.RCP R8, R3 ; /* 0x0000000300087308 */
/* 0x000e220000001000 */
/*05d0*/ FADD R13, -R5, R4 ; /* 0x00000004050d7221 */
/* 0x000fe20000000100 */
/*05e0*/ BSSY B1, 0x6b0 ; /* 0x000000c000017945 */
/* 0x000fec0003800000 */
/*05f0*/ FCHK P0, R13, R3 ; /* 0x000000030d007302 */
/* 0x000e620000000000 */
/*0600*/ FFMA R7, -R3, R8, 1 ; /* 0x3f80000003077423 */
/* 0x001fc80000000108 */
/*0610*/ FFMA R7, R8, R7, R8 ; /* 0x0000000708077223 */
/* 0x000fc80000000008 */
/*0620*/ FFMA R4, R13, R7, RZ ; /* 0x000000070d047223 */
/* 0x000fc800000000ff */
/*0630*/ FFMA R5, -R3, R4, R13 ; /* 0x0000000403057223 */
/* 0x000fc8000000010d */
/*0640*/ FFMA R4, R7, R5, R4 ; /* 0x0000000507047223 */
/* 0x000fe20000000004 */
/*0650*/ @!P0 BRA 0x6a0 ; /* 0x0000004000008947 */
/* 0x002fea0003800000 */
/*0660*/ IMAD.MOV.U32 R14, RZ, RZ, R3 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0003 */
/*0670*/ MOV R10, 0x690 ; /* 0x00000690000a7802 */
/* 0x000fe40000000f00 */
/*0680*/ CALL.REL.NOINC 0xa10 ; /* 0x0000038000007944 */
/* 0x000fea0003c00000 */
/*0690*/ IMAD.MOV.U32 R4, RZ, RZ, R9 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0009 */
/*06a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*06b0*/ FADD R4, R4, 4 ; /* 0x4080000004047421 */
/* 0x000fc80000000000 */
/*06c0*/ FMUL R7, R4, 60 ; /* 0x4270000004077820 */
/* 0x000fe20000400000 */
/*06d0*/ BRA 0x920 ; /* 0x0000024000007947 */
/* 0x000fea0003800000 */
/*06e0*/ MUFU.RCP R10, R3 ; /* 0x00000003000a7308 */
/* 0x000e220000001000 */
/*06f0*/ FADD R13, R8, -R4 ; /* 0x80000004080d7221 */
/* 0x000fe20000000000 */
/*0700*/ BSSY B1, 0x7d0 ; /* 0x000000c000017945 */
/* 0x000fec0003800000 */
/*0710*/ FCHK P0, R13, R3 ; /* 0x000000030d007302 */
/* 0x000e620000000000 */
/*0720*/ FFMA R5, -R3, R10, 1 ; /* 0x3f80000003057423 */
/* 0x001fc8000000010a */
/*0730*/ FFMA R10, R10, R5, R10 ; /* 0x000000050a0a7223 */
/* 0x000fc8000000000a */
/*0740*/ FFMA R4, R13, R10, RZ ; /* 0x0000000a0d047223 */
/* 0x000fc800000000ff */
/*0750*/ FFMA R5, -R3, R4, R13 ; /* 0x0000000403057223 */
/* 0x000fc8000000010d */
/*0760*/ FFMA R4, R5, R10, R4 ; /* 0x0000000a05047223 */
/* 0x000fe20000000004 */
/*0770*/ @!P0 BRA 0x7c0 ; /* 0x0000004000008947 */
/* 0x002fea0003800000 */
/*0780*/ MOV R14, R3 ; /* 0x00000003000e7202 */
/* 0x000fe40000000f00 */
/*0790*/ MOV R10, 0x7b0 ; /* 0x000007b0000a7802 */
/* 0x000fe40000000f00 */
/*07a0*/ CALL.REL.NOINC 0xa10 ; /* 0x0000026000007944 */
/* 0x000fea0003c00000 */
/*07b0*/ IMAD.MOV.U32 R4, RZ, RZ, R9 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0009 */
/*07c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*07d0*/ FADD R4, R4, 2 ; /* 0x4000000004047421 */
/* 0x000fc80000000000 */
/*07e0*/ FMUL R7, R4, 60 ; /* 0x4270000004077820 */
/* 0x000fe20000400000 */
/*07f0*/ BRA 0x920 ; /* 0x0000012000007947 */
/* 0x000fea0003800000 */
/*0800*/ MUFU.RCP R4, R3 ; /* 0x0000000300047308 */
/* 0x000e220000001000 */
/*0810*/ FADD R5, -R8, R5 ; /* 0x0000000508057221 */
/* 0x000fe20000000100 */
/*0820*/ BSSY B1, 0x900 ; /* 0x000000d000017945 */
/* 0x000fe60003800000 */
/*0830*/ FMUL R13, R5, 60 ; /* 0x42700000050d7820 */
/* 0x000fc80000400000 */
/*0840*/ FCHK P0, R13, R3 ; /* 0x000000030d007302 */
/* 0x000e620000000000 */
/*0850*/ FFMA R7, -R3, R4, 1 ; /* 0x3f80000003077423 */
/* 0x001fc80000000104 */
/*0860*/ FFMA R8, R4, R7, R4 ; /* 0x0000000704087223 */
/* 0x000fc80000000004 */
/*0870*/ FFMA R4, R13, R8, RZ ; /* 0x000000080d047223 */
/* 0x000fc800000000ff */
/*0880*/ FFMA R5, -R3, R4, R13 ; /* 0x0000000403057223 */
/* 0x000fc8000000010d */
/*0890*/ FFMA R7, R5, R8, R4 ; /* 0x0000000805077223 */
/* 0x000fe20000000004 */
/*08a0*/ @!P0 BRA 0x8f0 ; /* 0x0000004000008947 */
/* 0x002fea0003800000 */
/*08b0*/ IMAD.MOV.U32 R14, RZ, RZ, R3 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0003 */
/*08c0*/ MOV R10, 0x8e0 ; /* 0x000008e0000a7802 */
/* 0x000fe40000000f00 */
/*08d0*/ CALL.REL.NOINC 0xa10 ; /* 0x0000013000007944 */
/* 0x000fea0003c00000 */
/*08e0*/ MOV R7, R9 ; /* 0x0000000900077202 */
/* 0x001fe40000000f00 */
/*08f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0900*/ FSETP.GEU.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720b */
/* 0x000fda0003f0e000 */
/*0910*/ @!P0 FADD R7, R7, 360 ; /* 0x43b4000007078421 */
/* 0x000fe40000000000 */
/*0920*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0930*/ FSETP.GEU.AND P0, PT, R7.reuse, 200, PT ; /* 0x434800000700780b */
/* 0x040fe20003f0e000 */
/*0940*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0950*/ IADD3 R4, R0, 0x2, RZ ; /* 0x0000000200047810 */
/* 0x000fe40007ffe0ff */
/*0960*/ FSETP.GT.AND P0, PT, R7, 40, !P0 ; /* 0x422000000700780b */
/* 0x000fc60004704000 */
/*0970*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0205 */
/*0980*/ FSETP.GT.AND P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720b */
/* 0x000fc80000704000 */
/*0990*/ FSETP.LT.AND P0, PT, R6, 100, P0 ; /* 0x42c800000600780b */
/* 0x000fe20000701000 */
/*09a0*/ STG.E [R4.64+-0x4], R6 ; /* 0xfffffc0604007986 */
/* 0x000fe6000c101904 */
/*09b0*/ FSETP.GT.AND P0, PT, R2.reuse, RZ, P0 ; /* 0x000000ff0200720b */
/* 0x040fe20000704000 */
/*09c0*/ STG.E [R4.64+-0x8], R2 ; /* 0xfffff80204007986 */
/* 0x000fe6000c101904 */
/*09d0*/ FSETP.LT.AND P0, PT, R2, 100, P0 ; /* 0x42c800000200780b */
/* 0x000fda0000701000 */
/*09e0*/ @P0 FADD R7, R7, 140 ; /* 0x430c000007070421 */
/* 0x000fca0000000000 */
/*09f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0a00*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a10*/ SHF.R.U32.HI R12, RZ, 0x17, R14 ; /* 0x00000017ff0c7819 */
/* 0x000fe2000001160e */
/*0a20*/ BSSY B2, 0x1060 ; /* 0x0000063000027945 */
/* 0x000fe20003800000 */
/*0a30*/ SHF.R.U32.HI R9, RZ, 0x17, R13.reuse ; /* 0x00000017ff097819 */
/* 0x100fe4000001160d */
/*0a40*/ LOP3.LUT R12, R12, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0c0c7812 */
/* 0x000fe400078ec0ff */
/*0a50*/ LOP3.LUT R16, R9, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff09107812 */
/* 0x000fe200078ec0ff */
/*0a60*/ IMAD.MOV.U32 R9, RZ, RZ, R13 ; /* 0x000000ffff097224 */
/* 0x000fe200078e000d */
/*0a70*/ IADD3 R17, R12, -0x1, RZ ; /* 0xffffffff0c117810 */
/* 0x000fe40007ffe0ff */
/*0a80*/ IADD3 R15, R16, -0x1, RZ ; /* 0xffffffff100f7810 */
/* 0x000fc40007ffe0ff */
/*0a90*/ ISETP.GT.U32.AND P0, PT, R17, 0xfd, PT ; /* 0x000000fd1100780c */
/* 0x000fc80003f04070 */
/*0aa0*/ ISETP.GT.U32.OR P0, PT, R15, 0xfd, P0 ; /* 0x000000fd0f00780c */
/* 0x000fda0000704470 */
/*0ab0*/ @!P0 MOV R11, RZ ; /* 0x000000ff000b8202 */
/* 0x000fe20000000f00 */
/*0ac0*/ @!P0 BRA 0xc40 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0ad0*/ FSETP.GTU.FTZ.AND P0, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe40003f1c200 */
/*0ae0*/ FSETP.GTU.FTZ.AND P1, PT, |R14|, +INF , PT ; /* 0x7f8000000e00780b */
/* 0x000fc80003f3c200 */
/*0af0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0b00*/ @P0 BRA 0x1040 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0b10*/ LOP3.LUT P0, RZ, R14, 0x7fffffff, R9, 0xc8, !PT ; /* 0x7fffffff0eff7812 */
/* 0x000fda000780c809 */
/*0b20*/ @!P0 BRA 0x1020 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0b30*/ FSETP.NEU.FTZ.AND P2, PT, |R13|.reuse, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x040fe40003f5d200 */
/*0b40*/ FSETP.NEU.FTZ.AND P1, PT, |R14|, +INF , PT ; /* 0x7f8000000e00780b */
/* 0x000fe40003f3d200 */
/*0b50*/ FSETP.NEU.FTZ.AND P0, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fd60003f1d200 */
/*0b60*/ @!P1 BRA !P2, 0x1020 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0b70*/ LOP3.LUT P2, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000784c0ff */
/*0b80*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0b90*/ @P1 BRA 0x1000 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0ba0*/ LOP3.LUT P1, RZ, R14, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0eff7812 */
/* 0x000fc8000782c0ff */
/*0bb0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0bc0*/ @P0 BRA 0xfd0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0bd0*/ ISETP.GE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe40003f06270 */
/*0be0*/ ISETP.GE.AND P1, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fd60003f26270 */
/*0bf0*/ @P0 IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b0224 */
/* 0x000fe400078e00ff */
/*0c00*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, -0x40 ; /* 0xffffffc0ff0b8424 */
/* 0x000fe400078e00ff */
/*0c10*/ @!P0 FFMA R9, R13, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000d098823 */
/* 0x000fe400000000ff */
/*0c20*/ @!P1 FFMA R14, R14, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000e0e9823 */
/* 0x000fe200000000ff */
/*0c30*/ @!P1 IADD3 R11, R11, 0x40, RZ ; /* 0x000000400b0b9810 */
/* 0x000fe40007ffe0ff */
/*0c40*/ LEA R13, R12, 0xc0800000, 0x17 ; /* 0xc08000000c0d7811 */
/* 0x000fe200078eb8ff */
/*0c50*/ BSSY B3, 0xfc0 ; /* 0x0000036000037945 */
/* 0x000fe60003800000 */
/*0c60*/ IADD3 R15, -R13, R14, RZ ; /* 0x0000000e0d0f7210 */
/* 0x000fc40007ffe1ff */
/*0c70*/ IADD3 R14, R16, -0x7f, RZ ; /* 0xffffff81100e7810 */
/* 0x000fe40007ffe0ff */
/*0c80*/ MUFU.RCP R13, R15 ; /* 0x0000000f000d7308 */
/* 0x000e220000001000 */
/*0c90*/ FADD.FTZ R17, -R15, -RZ ; /* 0x800000ff0f117221 */
/* 0x000fe40000010100 */
/*0ca0*/ IMAD R16, R14.reuse, -0x800000, R9 ; /* 0xff8000000e107824 */
/* 0x040fe200078e0209 */
/*0cb0*/ IADD3 R14, R14, 0x7f, -R12 ; /* 0x0000007f0e0e7810 */
/* 0x000fca0007ffe80c */
/*0cc0*/ IMAD.IADD R14, R14, 0x1, R11 ; /* 0x000000010e0e7824 */
/* 0x000fe400078e020b */
/*0cd0*/ FFMA R18, R13, R17, 1 ; /* 0x3f8000000d127423 */
/* 0x001fc80000000011 */
/*0ce0*/ FFMA R13, R13, R18, R13 ; /* 0x000000120d0d7223 */
/* 0x000fc8000000000d */
/*0cf0*/ FFMA R18, R16, R13, RZ ; /* 0x0000000d10127223 */
/* 0x000fc800000000ff */
/*0d00*/ FFMA R9, R17, R18, R16 ; /* 0x0000001211097223 */
/* 0x000fc80000000010 */
/*0d10*/ FFMA R18, R13, R9, R18 ; /* 0x000000090d127223 */
/* 0x000fc80000000012 */
/*0d20*/ FFMA R16, R17, R18, R16 ; /* 0x0000001211107223 */
/* 0x000fc80000000010 */
/*0d30*/ FFMA R9, R13, R16, R18 ; /* 0x000000100d097223 */
/* 0x000fca0000000012 */
/*0d40*/ SHF.R.U32.HI R12, RZ, 0x17, R9 ; /* 0x00000017ff0c7819 */
/* 0x000fc80000011609 */
/*0d50*/ LOP3.LUT R12, R12, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0c0c7812 */
/* 0x000fca00078ec0ff */
/*0d60*/ IMAD.IADD R15, R12, 0x1, R14 ; /* 0x000000010c0f7824 */
/* 0x000fca00078e020e */
/*0d70*/ IADD3 R11, R15, -0x1, RZ ; /* 0xffffffff0f0b7810 */
/* 0x000fc80007ffe0ff */
/*0d80*/ ISETP.GE.U32.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f06070 */
/*0d90*/ @!P0 BRA 0xfa0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0da0*/ ISETP.GT.AND P0, PT, R15, 0xfe, PT ; /* 0x000000fe0f00780c */
/* 0x000fda0003f04270 */
/*0db0*/ @P0 BRA 0xf70 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0dc0*/ ISETP.GE.AND P0, PT, R15, 0x1, PT ; /* 0x000000010f00780c */
/* 0x000fda0003f06270 */
/*0dd0*/ @P0 BRA 0xfb0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0de0*/ ISETP.GE.AND P0, PT, R15, -0x18, PT ; /* 0xffffffe80f00780c */
/* 0x000fe40003f06270 */
/*0df0*/ LOP3.LUT R9, R9, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000009097812 */
/* 0x000fd600078ec0ff */
/*0e00*/ @!P0 BRA 0xfb0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0e10*/ FFMA.RZ R11, R13, R16.reuse, R18.reuse ; /* 0x000000100d0b7223 */
/* 0x180fe2000000c012 */
/*0e20*/ ISETP.NE.AND P2, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe20003f45270 */
/*0e30*/ FFMA.RM R12, R13, R16.reuse, R18.reuse ; /* 0x000000100d0c7223 */
/* 0x180fe20000004012 */
/*0e40*/ ISETP.NE.AND P1, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe40003f25270 */
/*0e50*/ LOP3.LUT R14, R11, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0b0e7812 */
/* 0x000fe200078ec0ff */
/*0e60*/ FFMA.RP R11, R13, R16, R18 ; /* 0x000000100d0b7223 */
/* 0x000fe20000008012 */
/*0e70*/ IADD3 R13, R15.reuse, 0x20, RZ ; /* 0x000000200f0d7810 */
/* 0x040fe40007ffe0ff */
/*0e80*/ LOP3.LUT R14, R14, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000e0e7812 */
/* 0x000fe400078efcff */
/*0e90*/ IADD3 R15, -R15, RZ, RZ ; /* 0x000000ff0f0f7210 */
/* 0x000fc40007ffe1ff */
/*0ea0*/ SHF.L.U32 R13, R14, R13, RZ ; /* 0x0000000d0e0d7219 */
/* 0x000fe400000006ff */
/*0eb0*/ FSETP.NEU.FTZ.AND P0, PT, R11, R12, PT ; /* 0x0000000c0b00720b */
/* 0x000fe40003f1d000 */
/*0ec0*/ SEL R11, R15, RZ, P2 ; /* 0x000000ff0f0b7207 */
/* 0x000fe40001000000 */
/*0ed0*/ ISETP.NE.AND P1, PT, R13, RZ, P1 ; /* 0x000000ff0d00720c */
/* 0x000fe40000f25270 */
/*0ee0*/ SHF.R.U32.HI R11, RZ, R11, R14 ; /* 0x0000000bff0b7219 */
/* 0x000fe4000001160e */
/*0ef0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0f00*/ SHF.R.U32.HI R13, RZ, 0x1, R11 ; /* 0x00000001ff0d7819 */
/* 0x000fe4000001160b */
/*0f10*/ SEL R12, RZ, 0x1, !P0 ; /* 0x00000001ff0c7807 */
/* 0x000fc80004000000 */
/*0f20*/ LOP3.LUT R12, R12, 0x1, R13, 0xf8, !PT ; /* 0x000000010c0c7812 */
/* 0x000fc800078ef80d */
/*0f30*/ LOP3.LUT R12, R12, R11, RZ, 0xc0, !PT ; /* 0x0000000b0c0c7212 */
/* 0x000fca00078ec0ff */
/*0f40*/ IMAD.IADD R12, R13, 0x1, R12 ; /* 0x000000010d0c7824 */
/* 0x000fca00078e020c */
/*0f50*/ LOP3.LUT R9, R12, R9, RZ, 0xfc, !PT ; /* 0x000000090c097212 */
/* 0x000fe200078efcff */
/*0f60*/ BRA 0xfb0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0f70*/ LOP3.LUT R9, R9, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000009097812 */
/* 0x000fc800078ec0ff */
/*0f80*/ LOP3.LUT R9, R9, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000009097812 */
/* 0x000fe200078efcff */
/*0f90*/ BRA 0xfb0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0fa0*/ IMAD R9, R14, 0x800000, R9 ; /* 0x008000000e097824 */
/* 0x000fe400078e0209 */
/*0fb0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0fc0*/ BRA 0x1050 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0fd0*/ LOP3.LUT R9, R14, 0x80000000, R9, 0x48, !PT ; /* 0x800000000e097812 */
/* 0x000fc800078e4809 */
/*0fe0*/ LOP3.LUT R9, R9, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000009097812 */
/* 0x000fe200078efcff */
/*0ff0*/ BRA 0x1050 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*1000*/ LOP3.LUT R9, R14, 0x80000000, R9, 0x48, !PT ; /* 0x800000000e097812 */
/* 0x000fe200078e4809 */
/*1010*/ BRA 0x1050 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*1020*/ MUFU.RSQ R9, -QNAN ; /* 0xffc0000000097908 */
/* 0x000e220000001400 */
/*1030*/ BRA 0x1050 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1040*/ FADD.FTZ R9, R13, R14 ; /* 0x0000000e0d097221 */
/* 0x000fe40000010000 */
/*1050*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*1060*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fcc00000001ff */
/*1070*/ RET.REL.NODEC R10 0x0 ; /* 0xffffef800a007950 */
/* 0x000fea0003c3ffff */
/*1080*/ BRA 0x1080; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/* This code will generate a fractal image. Uses OpenCV, to compile:
nvcc CudaFinal.cu `pkg-config --cflags --libs opencv` */
typedef enum color {BLUE, GREEN, RED} Color;
__global__ void convert_to_hsv(unsigned char *src, float *hsv, int width, int heigth, int step, int channels) {
float r, g, b;
float h, s, v;
int ren,col;
ren = blockIdx.x;
col = threadIdx.x;
r = src[(ren * step) + (col * channels) + RED] / 255.0f;
g = src[(ren * step) + (col * channels) + GREEN] / 255.0f;
b = src[(ren * step) + (col * channels) + BLUE] / 255.0f;
float max = fmax(r, fmax(g, b));
float min = fmin(r, fmin(g, b));
float diff = max - min;
v = max;
if(v == 0.0f) { // black
h = s = 0.0f;
} else {
s = diff / v;
if(diff < 0.001f) { // grey
h = 0.0f;
} else { // color
if(max == r) {
h = 60.0f * (g - b)/diff;
if(h < 0.0f) { h += 360.0f; }
} else if(max == g) {
h = 60.0f * (2 + (b - r)/diff);
} else {
h = 60.0f * (4 + (r - g)/diff);
}
}
}
// confusion line
float minh=40.0f;
float maxh=200.0f;
float minis = 0;
float maxs = 100;
float miniv = 0;
float maxv = 100;
// if conditionals to check the color blindness line, if the pixel is in this line i change the color to other color base shifting the h
if (h > minh && h < maxh && s > minis && s < maxs && v > miniv && v < maxv){
hsv[(ren * step) + (col * channels) + RED] = (float) (h + 140.0f);
hsv[(ren * step) + (col * channels) + GREEN] = (float) (s);
hsv[(ren * step) + (col * channels) + BLUE] = (float) (v);
} else { // this keep the pixel if it is out of the color blindnessline
hsv[(ren * step) + (col * channels) + RED] = (float) (h);
hsv[(ren * step) + (col * channels) + GREEN] = (float) (s);
hsv[(ren * step) + (col * channels) + BLUE] = (float) (v);
}
} | .file "tmpxft_0007e8e3_00000000-6_convert_to_hsv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z14convert_to_hsvPhPfiiiiPhPfiiii
.type _Z40__device_stub__Z14convert_to_hsvPhPfiiiiPhPfiiii, @function
_Z40__device_stub__Z14convert_to_hsvPhPfiiiiPhPfiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14convert_to_hsvPhPfiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z14convert_to_hsvPhPfiiiiPhPfiiii, .-_Z40__device_stub__Z14convert_to_hsvPhPfiiiiPhPfiiii
.globl _Z14convert_to_hsvPhPfiiii
.type _Z14convert_to_hsvPhPfiiii, @function
_Z14convert_to_hsvPhPfiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z14convert_to_hsvPhPfiiiiPhPfiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14convert_to_hsvPhPfiiii, .-_Z14convert_to_hsvPhPfiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14convert_to_hsvPhPfiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14convert_to_hsvPhPfiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
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