system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010903f_00000000-6_exercise_2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4248:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4248:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10host_saxpyPfS_f
.type _Z10host_saxpyPfS_f, @function
_Z10host_saxpyPfS_f:
.LFB4240:
.cfi_startproc
endbr64
movl $0, %eax
.L4:
movaps %xmm0, %xmm1
mulss (%rdi,%rax), %xmm1
addss (%rsi,%rax), %xmm1
movss %xmm1, (%rsi,%rax)
addq $4, %rax
cmpq $40000000, %rax
jne .L4
ret
.cfi_endproc
.LFE4240:
.size _Z10host_saxpyPfS_f, .-_Z10host_saxpyPfS_f
.globl _Z35__device_stub__Z12device_saxpyPfS_fPfS_f
.type _Z35__device_stub__Z12device_saxpyPfS_fPfS_f, @function
_Z35__device_stub__Z12device_saxpyPfS_fPfS_f:
.LFB4270:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12device_saxpyPfS_f(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4270:
.size _Z35__device_stub__Z12device_saxpyPfS_fPfS_f, .-_Z35__device_stub__Z12device_saxpyPfS_fPfS_f
.globl _Z12device_saxpyPfS_f
.type _Z12device_saxpyPfS_f, @function
_Z12device_saxpyPfS_f:
.LFB4271:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12device_saxpyPfS_fPfS_f
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4271:
.size _Z12device_saxpyPfS_f, .-_Z12device_saxpyPfS_f
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12device_saxpyPfS_f"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4273:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12device_saxpyPfS_f(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4273:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZSt18generate_canonicalIfLm24ESt26linear_congruential_engineImLm16807ELm0ELm2147483647EEET_RT1_,"axG",@progbits,_ZSt18generate_canonicalIfLm24ESt26linear_congruential_engineImLm16807ELm0ELm2147483647EEET_RT1_,comdat
.weak _ZSt18generate_canonicalIfLm24ESt26linear_congruential_engineImLm16807ELm0ELm2147483647EEET_RT1_
.type _ZSt18generate_canonicalIfLm24ESt26linear_congruential_engineImLm16807ELm0ELm2147483647EEET_RT1_, @function
_ZSt18generate_canonicalIfLm24ESt26linear_congruential_engineImLm16807ELm0ELm2147483647EEET_RT1_:
.LFB4958:
.cfi_startproc
endbr64
imulq $16807, (%rdi), %rcx
movabsq $8589934597, %rdx
movq %rcx, %rax
mulq %rdx
movq %rcx, %rax
subq %rdx, %rax
shrq %rax
addq %rax, %rdx
shrq $30, %rdx
movq %rdx, %rax
salq $31, %rax
subq %rdx, %rax
subq %rax, %rcx
movq %rcx, %rdx
movq %rcx, (%rdi)
subq $1, %rdx
js .L17
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
.L18:
pxor %xmm1, %xmm1
addss %xmm1, %xmm0
mulss .LC3(%rip), %xmm0
comiss .LC4(%rip), %xmm0
jnb .L21
.L16:
ret
.L17:
movq %rdx, %rax
shrq %rax
andl $1, %edx
orq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
addss %xmm0, %xmm0
jmp .L18
.L21:
movss .LC1(%rip), %xmm0
ret
.cfi_endproc
.LFE4958:
.size _ZSt18generate_canonicalIfLm24ESt26linear_congruential_engineImLm16807ELm0ELm2147483647EEET_RT1_, .-_ZSt18generate_canonicalIfLm24ESt26linear_congruential_engineImLm16807ELm0ELm2147483647EEET_RT1_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "Computing SAXPY on the GPU... "
.section .rodata.str1.1
.LC8:
.string "Done in %f ms!\n\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "Computing SAXPY on the CPU... "
.align 8
.LC10:
.string "Comparing the output for each implementation... "
.section .rodata.str1.1
.LC13:
.string "Correct!\n"
.LC14:
.string "Incorrect!\n"
.text
.globl main
.type main, @function
main:
.LFB4241:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq $1, 8(%rsp)
movl $40000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $40000000, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %ebx
.L23:
leaq 8(%rsp), %r13
movq %r13, %rdi
call _ZSt18generate_canonicalIfLm24ESt26linear_congruential_engineImLm16807ELm0ELm2147483647EEET_RT1_
mulss .LC5(%rip), %xmm0
pxor %xmm3, %xmm3
addss %xmm3, %xmm0
movss %xmm0, 0(%rbp,%rbx)
movq %r13, %rdi
call _ZSt18generate_canonicalIfLm24ESt26linear_congruential_engineImLm16807ELm0ELm2147483647EEET_RT1_
mulss .LC5(%rip), %xmm0
pxor %xmm4, %xmm4
addss %xmm4, %xmm0
movss %xmm0, (%r12,%rbx)
addq $4, %rbx
cmpq $40000000, %rbx
jne .L23
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movq $0, 16(%rsp)
movq $0, 24(%rsp)
leaq 16(%rsp), %rdi
movl $40000000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $40000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40000000, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40000000, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $39063, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L24:
call cudaDeviceSynchronize@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbx, %rax
imulq $1000, %rax, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC7(%rip), %xmm0
leaq .LC8(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r13
movss .LC4(%rip), %xmm0
movq %r12, %rsi
movq %rbp, %rdi
call _Z10host_saxpyPfS_f
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %r13, %rax
imulq $1000, %rax, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC7(%rip), %xmm0
movq %rbx, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $40000000, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
movss .LC11(%rip), %xmm2
movsd .LC12(%rip), %xmm1
.L26:
movss 0(%rbp,%rax), %xmm0
subss (%r12,%rax), %xmm0
andps %xmm2, %xmm0
cvtss2sd %xmm0, %xmm0
comisd %xmm1, %xmm0
ja .L25
addq $4, %rax
cmpq $40000000, %rax
jne .L26
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L28:
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movss .LC4(%rip), %xmm0
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z35__device_stub__Z12device_saxpyPfS_fPfS_f
jmp .L24
.L25:
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L28
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4241:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353215
.align 4
.LC3:
.long 805306368
.align 4
.LC4:
.long 1065353216
.align 4
.LC5:
.long 1084227584
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long 0
.long 1104006501
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC11:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC12:
.long -350469331
.long 1058682594
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "exercise_2.hip"
.globl _Z27__device_stub__device_saxpyPfS_f # -- Begin function _Z27__device_stub__device_saxpyPfS_f
.p2align 4, 0x90
.type _Z27__device_stub__device_saxpyPfS_f,@function
_Z27__device_stub__device_saxpyPfS_f: # @_Z27__device_stub__device_saxpyPfS_f
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12device_saxpyPfS_f, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__device_saxpyPfS_f, .Lfunc_end0-_Z27__device_stub__device_saxpyPfS_f
.cfi_endproc
# -- End function
.globl _Z10host_saxpyPfS_f # -- Begin function _Z10host_saxpyPfS_f
.p2align 4, 0x90
.type _Z10host_saxpyPfS_f,@function
_Z10host_saxpyPfS_f: # @_Z10host_saxpyPfS_f
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss (%rdi,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
addss (%rsi,%rax,4), %xmm1
movss %xmm1, (%rsi,%rax,4)
incq %rax
cmpq $10000000, %rax # imm = 0x989680
jne .LBB1_1
# %bb.2:
retq
.Lfunc_end1:
.size _Z10host_saxpyPfS_f, .Lfunc_end1-_Z10host_saxpyPfS_f
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x41dfffffff800000 # double 2147483646
.LCPI2_5:
.quad 0x41cdcd6500000000 # double 1.0E+9
.LCPI2_7:
.quad 0x3f1a36e2eb1c432d # double 1.0E-4
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_1:
.long 0x40000000 # float 2
.LCPI2_2:
.long 0x5f000000 # float 9.22337203E+18
.LCPI2_3:
.long 0x3f800000 # float 1
.LCPI2_4:
.long 0x40a00000 # float 5
.LCPI2_8:
.long 0x00000000 # float 0
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI2_6:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $192, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, %rbx
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, %r14
movl $1, %r15d
xorl %r12d, %r12d
movabsq $8589934597, %r13 # imm = 0x200000005
.p2align 4, 0x90
.LBB2_1: # =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
# Child Loop BB2_9 Depth 2
fldl .LCPI2_0(%rip)
fstpt (%rsp)
callq logl
fstpt 68(%rsp) # 10-byte Folded Spill
flds .LCPI2_1(%rip)
fstpt (%rsp)
callq logl
fldt 68(%rsp) # 10-byte Folded Reload
fdivp %st, %st(1)
flds .LCPI2_2(%rip)
xorl %ecx, %ecx
fxch %st(1)
fucomi %st(1), %st
fldz
fcmovnb %st(2), %st
fstp %st(2)
fsubp %st, %st(1)
setae %cl
fnstcw 26(%rsp)
movzwl 26(%rsp), %eax
orl $3072, %eax # imm = 0xC00
movw %ax, 30(%rsp)
fldcw 30(%rsp)
fistpll 88(%rsp)
fldcw 26(%rsp)
shlq $63, %rcx
xorq 88(%rsp), %rcx
leaq 23(%rcx), %rax
xorl %edx, %edx
divq %rcx
movq %rax, %rcx
cmpq $1, %rax
adcq $0, %rcx
movss .LCPI2_3(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movaps %xmm3, %xmm1
xorps %xmm0, %xmm0
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_2 Depth=2
xorps %xmm2, %xmm2
cvtsi2ss %rdx, %xmm2
.LBB2_5: # in Loop: Header=BB2_2 Depth=2
addq %rax, %r15
mulss %xmm1, %xmm2
movss %xmm1, 60(%rsp)
flds 60(%rsp)
fmull .LCPI2_0(%rip)
addss %xmm2, %xmm0
fstps 56(%rsp)
movss 56(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
decq %rcx
je .LBB2_6
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
imulq $16807, %r15, %r15 # imm = 0x41A7
movq %r15, %rax
mulq %r13
movq %r15, %rax
subq %rdx, %rax
shrq %rax
addq %rdx, %rax
shrq $30, %rax
movq %rax, %rdx
shlq $31, %rdx
subq %rdx, %rax
leaq (%r15,%rax), %rdx
decq %rdx
testq %rdx, %rdx
jns .LBB2_4
# %bb.3: # in Loop: Header=BB2_2 Depth=2
movq %rdx, %rsi
shrq %rsi
andl $1, %edx
orq %rsi, %rdx
xorps %xmm2, %xmm2
cvtsi2ss %rdx, %xmm2
addss %xmm2, %xmm2
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_1 Depth=1
divss %xmm1, %xmm0
ucomiss %xmm3, %xmm0
jae .LBB2_7
.LBB2_8: # %_ZNSt25uniform_real_distributionIfEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEfRT_.exit
# in Loop: Header=BB2_1 Depth=1
mulss .LCPI2_4(%rip), %xmm0
xorps %xmm1, %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%rbx,%r12,4)
fldl .LCPI2_0(%rip)
fstpt (%rsp)
callq logl
fstpt 68(%rsp) # 10-byte Folded Spill
flds .LCPI2_1(%rip)
fstpt (%rsp)
callq logl
xorps %xmm0, %xmm0
fldt 68(%rsp) # 10-byte Folded Reload
fdivp %st, %st(1)
flds .LCPI2_2(%rip)
xorl %ecx, %ecx
fxch %st(1)
fucomi %st(1), %st
fldz
fcmovnb %st(2), %st
fstp %st(2)
fsubp %st, %st(1)
setae %cl
fnstcw 24(%rsp)
movzwl 24(%rsp), %eax
orl $3072, %eax # imm = 0xC00
movw %ax, 28(%rsp)
fldcw 28(%rsp)
fistpll 80(%rsp)
fldcw 24(%rsp)
shlq $63, %rcx
xorq 80(%rsp), %rcx
leaq 23(%rcx), %rax
xorl %edx, %edx
divq %rcx
movq %rax, %rcx
cmpq $1, %rax
adcq $0, %rcx
movss .LCPI2_3(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movaps %xmm2, %xmm3
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_11: # in Loop: Header=BB2_9 Depth=2
xorps %xmm1, %xmm1
cvtsi2ss %rdx, %xmm1
.LBB2_12: # in Loop: Header=BB2_9 Depth=2
addq %rax, %r15
mulss %xmm3, %xmm1
movss %xmm3, 52(%rsp)
flds 52(%rsp)
fmull .LCPI2_0(%rip)
addss %xmm1, %xmm0
fstps 48(%rsp)
movss 48(%rsp), %xmm3 # xmm3 = mem[0],zero,zero,zero
decq %rcx
je .LBB2_13
.LBB2_9: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
imulq $16807, %r15, %r15 # imm = 0x41A7
movq %r15, %rax
mulq %r13
movq %r15, %rax
subq %rdx, %rax
shrq %rax
addq %rdx, %rax
shrq $30, %rax
movq %rax, %rdx
shlq $31, %rdx
subq %rdx, %rax
leaq (%r15,%rax), %rdx
decq %rdx
testq %rdx, %rdx
jns .LBB2_11
# %bb.10: # in Loop: Header=BB2_9 Depth=2
movq %rdx, %rsi
shrq %rsi
andl $1, %edx
orq %rsi, %rdx
xorps %xmm1, %xmm1
cvtsi2ss %rdx, %xmm1
addss %xmm1, %xmm1
jmp .LBB2_12
.p2align 4, 0x90
.LBB2_13: # in Loop: Header=BB2_1 Depth=1
divss %xmm3, %xmm0
ucomiss %xmm2, %xmm0
jae .LBB2_14
.LBB2_15: # %_ZNSt25uniform_real_distributionIfEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEfRT_.exit34
# in Loop: Header=BB2_1 Depth=1
mulss .LCPI2_4(%rip), %xmm0
addss .LCPI2_8(%rip), %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq $10000000, %r12 # imm = 0x989680
jne .LBB2_1
jmp .LBB2_16
.LBB2_7: # in Loop: Header=BB2_1 Depth=1
xorps %xmm1, %xmm1
movss .LCPI2_3(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq nextafterf
jmp .LBB2_8
.LBB2_14: # in Loop: Header=BB2_1 Depth=1
xorps %xmm1, %xmm1
movss .LCPI2_3(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq nextafterf
jmp .LBB2_15
.LBB2_16:
movl $.L.str, %edi
xorl %eax, %eax
callq printf
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
movq $0, 40(%rsp)
movq $0, 32(%rsp)
leaq 40(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
callq hipMalloc
leaq 32(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
callq hipMalloc
movq 40(%rsp), %rdi
movl $40000000, %edx # imm = 0x2625A00
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $40000000, %edx # imm = 0x2625A00
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 38807(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_18
# %bb.17:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movl $1065353216, 64(%rsp) # imm = 0x3F800000
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 64(%rsp), %rax
movq %rax, 176(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rax
movq 96(%rsp), %rdi
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
movq %rdi, 8(%rsp)
movq %rax, (%rsp)
leaq 160(%rsp), %r9
movl $_Z12device_saxpyPfS_f, %edi
callq hipLaunchKernel
.LBB2_18:
callq hipDeviceSynchronize
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %r15, %rax
imulq $1000, %rax, %rax # imm = 0x3E8
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_5(%rip), %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
xorl %r12d, %r12d
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
.p2align 4, 0x90
.LBB2_19: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r14,%r12,4), %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq $10000000, %r12 # imm = 0x989680
jne .LBB2_19
# %bb.20: # %_Z10host_saxpyPfS_f.exit
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %r15, %rax
imulq $1000, %rax, %rax # imm = 0x3E8
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_5(%rip), %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rsi
movl $40000000, %edx # imm = 0x2625A00
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movaps .LCPI2_6(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI2_7(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB2_21: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss (%r14,%r15,4), %xmm2
andps %xmm0, %xmm2
cvtss2sd %xmm2, %xmm2
ucomisd %xmm1, %xmm2
ja .LBB2_24
# %bb.22: # in Loop: Header=BB2_21 Depth=1
incq %r15
cmpq $10000000, %r15 # imm = 0x989680
jne .LBB2_21
# %bb.23:
movl $.Lstr.1, %edi
jmp .LBB2_25
.LBB2_24:
movl $.Lstr, %edi
.LBB2_25: # %.critedge
callq puts@PLT
movq %r14, %rdi
callq free
movq %rbx, %rdi
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $192, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12device_saxpyPfS_f, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12device_saxpyPfS_f,@object # @_Z12device_saxpyPfS_f
.section .rodata,"a",@progbits
.globl _Z12device_saxpyPfS_f
.p2align 3, 0x0
_Z12device_saxpyPfS_f:
.quad _Z27__device_stub__device_saxpyPfS_f
.size _Z12device_saxpyPfS_f, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Computing SAXPY on the GPU... "
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Done in %f ms!\n\n"
.size .L.str.1, 17
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Computing SAXPY on the CPU... "
.size .L.str.2, 31
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Comparing the output for each implementation... "
.size .L.str.3, 49
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12device_saxpyPfS_f"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Incorrect!"
.size .Lstr, 11
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Correct!"
.size .Lstr.1, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__device_saxpyPfS_f
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12device_saxpyPfS_f
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void addKernel(int * dev_a, int * dev_b, int * dev_c)
{
int i = threadIdx.x;
dev_c[i] = dev_a[i] + dev_b[i];
} | code for sm_80
Function : _Z9addKernelPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void addKernel(int * dev_a, int * dev_b, int * dev_c)
{
int i = threadIdx.x;
dev_c[i] = dev_a[i] + dev_b[i];
} | .file "tmpxft_000096a9_00000000-6_addKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9addKernelPiS_S_PiS_S_
.type _Z32__device_stub__Z9addKernelPiS_S_PiS_S_, @function
_Z32__device_stub__Z9addKernelPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addKernelPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z9addKernelPiS_S_PiS_S_, .-_Z32__device_stub__Z9addKernelPiS_S_PiS_S_
.globl _Z9addKernelPiS_S_
.type _Z9addKernelPiS_S_, @function
_Z9addKernelPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9addKernelPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9addKernelPiS_S_, .-_Z9addKernelPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9addKernelPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void addKernel(int * dev_a, int * dev_b, int * dev_c)
{
int i = threadIdx.x;
dev_c[i] = dev_a[i] + dev_b[i];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void addKernel(int * dev_a, int * dev_b, int * dev_c)
{
int i = threadIdx.x;
dev_c[i] = dev_a[i] + dev_b[i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void addKernel(int * dev_a, int * dev_b, int * dev_c)
{
int i = threadIdx.x;
dev_c[i] = dev_a[i] + dev_b[i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKernelPiS_S_
.globl _Z9addKernelPiS_S_
.p2align 8
.type _Z9addKernelPiS_S_,@function
_Z9addKernelPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKernelPiS_S_, .Lfunc_end0-_Z9addKernelPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9addKernelPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void addKernel(int * dev_a, int * dev_b, int * dev_c)
{
int i = threadIdx.x;
dev_c[i] = dev_a[i] + dev_b[i];
} | .text
.file "addKernel.hip"
.globl _Z24__device_stub__addKernelPiS_S_ # -- Begin function _Z24__device_stub__addKernelPiS_S_
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPiS_S_,@function
_Z24__device_stub__addKernelPiS_S_: # @_Z24__device_stub__addKernelPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernelPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__addKernelPiS_S_, .Lfunc_end0-_Z24__device_stub__addKernelPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addKernelPiS_S_,@object # @_Z9addKernelPiS_S_
.section .rodata,"a",@progbits
.globl _Z9addKernelPiS_S_
.p2align 3, 0x0
_Z9addKernelPiS_S_:
.quad _Z24__device_stub__addKernelPiS_S_
.size _Z9addKernelPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9addKernelPiS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKernelPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addKernelPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9addKernelPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKernelPiS_S_
.globl _Z9addKernelPiS_S_
.p2align 8
.type _Z9addKernelPiS_S_,@function
_Z9addKernelPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKernelPiS_S_, .Lfunc_end0-_Z9addKernelPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9addKernelPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000096a9_00000000-6_addKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9addKernelPiS_S_PiS_S_
.type _Z32__device_stub__Z9addKernelPiS_S_PiS_S_, @function
_Z32__device_stub__Z9addKernelPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addKernelPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z9addKernelPiS_S_PiS_S_, .-_Z32__device_stub__Z9addKernelPiS_S_PiS_S_
.globl _Z9addKernelPiS_S_
.type _Z9addKernelPiS_S_, @function
_Z9addKernelPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9addKernelPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9addKernelPiS_S_, .-_Z9addKernelPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9addKernelPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "addKernel.hip"
.globl _Z24__device_stub__addKernelPiS_S_ # -- Begin function _Z24__device_stub__addKernelPiS_S_
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPiS_S_,@function
_Z24__device_stub__addKernelPiS_S_: # @_Z24__device_stub__addKernelPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernelPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__addKernelPiS_S_, .Lfunc_end0-_Z24__device_stub__addKernelPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addKernelPiS_S_,@object # @_Z9addKernelPiS_S_
.section .rodata,"a",@progbits
.globl _Z9addKernelPiS_S_
.p2align 3, 0x0
_Z9addKernelPiS_S_:
.quad _Z24__device_stub__addKernelPiS_S_
.size _Z9addKernelPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9addKernelPiS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKernelPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addKernelPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <assert.h>
#include <string.h>
#include <cuda.h>
#define BLOCK_SIZE 4
void checkCudaError(cudaError_t errorCode)
{
if (errorCode != cudaSuccess)
fprintf(stderr, "Error %d\n", errorCode);
}
void incrementArrayOnHost(float *a, int size, int k)
{
int i;
for (i = 0; i < size; i++)
a[i] += k;
}
__global__ void kernel(float *a, int size)
{
int numBlockThread = blockDim.x*blockDim.y*blockDim.z;
int blockRowOffset = blockIdx.x*gridDim.y*gridDim.z*numBlockThread;
int blockColOffset = blockIdx.y*gridDim.z*numBlockThread;
int blockDepOffset = blockIdx.z*numBlockThread;
int blockPos = blockRowOffset + blockColOffset + blockDepOffset;
int threadRowOffset = threadIdx.x*blockDim.y*blockDim.z;
int threadColOffset = threadIdx.y*blockDim.z;
int threadDepOffset = threadIdx.z;
int threadPos = threadRowOffset + threadColOffset + threadDepOffset;
int idx = blockPos + threadPos;
if (idx < size)
a[idx] += 1.0;
}
int main(void)
{
float *ha, *hb; // host data
float *da; // device data
int N = 1000000;
int nbytes, i;
nbytes = N * sizeof(float);
ha = (float *) malloc(nbytes);
hb = (float *) malloc(nbytes);
checkCudaError(cudaMalloc((void **) &da, nbytes));
for (i = 0; i < N; i++)
ha[i] = 100.0 + i;
checkCudaError(cudaMemcpy(da, ha, nbytes, cudaMemcpyHostToDevice));
incrementArrayOnHost(ha, N, 1.0);
int nblocks = N/BLOCK_SIZE + (N%BLOCK_SIZE==0?0:1);
dim3 grid(nblocks);
dim3 block(BLOCK_SIZE);
kernel<<<grid, block>>>(da, N);
checkCudaError(cudaMemcpy(hb, da, nbytes, cudaMemcpyDeviceToHost));
for (i = 0; i < N; i++)
assert(ha[i] == hb[i]);
for (i = 0; i < 10; i++)
printf("%f %f\n", ha[i], hb[i]);
return 0;
} | code for sm_80
Function : _Z6kernelPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0030*/ S2R R5, SR_CTAID.Z ; /* 0x0000000000057919 */
/* 0x000e680000002700 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea80000002100 */
/*0050*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000ee80000002200 */
/*0060*/ S2R R11, SR_TID.Z ; /* 0x00000000000b7919 */
/* 0x000f220000002300 */
/*0070*/ IMAD R0, R0, c[0x0][0x10], R3 ; /* 0x0000040000007a24 */
/* 0x001fc800078e0203 */
/*0080*/ IMAD R0, R0, c[0x0][0x14], R5 ; /* 0x0000050000007a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fc800078e0207 */
/*00a0*/ IMAD R0, R0, c[0x0][0x4], R9 ; /* 0x0000010000007a24 */
/* 0x008fc800078e0209 */
/*00b0*/ IMAD R0, R0, c[0x0][0x8], R11 ; /* 0x0000020000007a24 */
/* 0x010fca00078e020b */
/*00c0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0100*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0110*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0120*/ FADD R5, R0, 1 ; /* 0x3f80000000057421 */
/* 0x004fca0000000000 */
/*0130*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <assert.h>
#include <string.h>
#include <cuda.h>
#define BLOCK_SIZE 4
void checkCudaError(cudaError_t errorCode)
{
if (errorCode != cudaSuccess)
fprintf(stderr, "Error %d\n", errorCode);
}
void incrementArrayOnHost(float *a, int size, int k)
{
int i;
for (i = 0; i < size; i++)
a[i] += k;
}
__global__ void kernel(float *a, int size)
{
int numBlockThread = blockDim.x*blockDim.y*blockDim.z;
int blockRowOffset = blockIdx.x*gridDim.y*gridDim.z*numBlockThread;
int blockColOffset = blockIdx.y*gridDim.z*numBlockThread;
int blockDepOffset = blockIdx.z*numBlockThread;
int blockPos = blockRowOffset + blockColOffset + blockDepOffset;
int threadRowOffset = threadIdx.x*blockDim.y*blockDim.z;
int threadColOffset = threadIdx.y*blockDim.z;
int threadDepOffset = threadIdx.z;
int threadPos = threadRowOffset + threadColOffset + threadDepOffset;
int idx = blockPos + threadPos;
if (idx < size)
a[idx] += 1.0;
}
int main(void)
{
float *ha, *hb; // host data
float *da; // device data
int N = 1000000;
int nbytes, i;
nbytes = N * sizeof(float);
ha = (float *) malloc(nbytes);
hb = (float *) malloc(nbytes);
checkCudaError(cudaMalloc((void **) &da, nbytes));
for (i = 0; i < N; i++)
ha[i] = 100.0 + i;
checkCudaError(cudaMemcpy(da, ha, nbytes, cudaMemcpyHostToDevice));
incrementArrayOnHost(ha, N, 1.0);
int nblocks = N/BLOCK_SIZE + (N%BLOCK_SIZE==0?0:1);
dim3 grid(nblocks);
dim3 block(BLOCK_SIZE);
kernel<<<grid, block>>>(da, N);
checkCudaError(cudaMemcpy(hb, da, nbytes, cudaMemcpyDeviceToHost));
for (i = 0; i < N; i++)
assert(ha[i] == hb[i]);
for (i = 0; i < 10; i++)
printf("%f %f\n", ha[i], hb[i]);
return 0;
} | .file "tmpxft_000958ff_00000000-6_topic2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Error %d\n"
.text
.globl _Z14checkCudaError9cudaError
.type _Z14checkCudaError9cudaError, @function
_Z14checkCudaError9cudaError:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
subq $8, %rsp
.cfi_def_cfa_offset 16
movl %edi, %ecx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z14checkCudaError9cudaError, .-_Z14checkCudaError9cudaError
.globl _Z20incrementArrayOnHostPfii
.type _Z20incrementArrayOnHostPfii, @function
_Z20incrementArrayOnHostPfii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L10
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rcx
pxor %xmm1, %xmm1
cvtsi2ssl %edx, %xmm1
.L12:
movaps %xmm1, %xmm0
addss (%rax), %xmm0
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L12
.L10:
ret
.cfi_endproc
.LFE2058:
.size _Z20incrementArrayOnHostPfii, .-_Z20incrementArrayOnHostPfii
.globl _Z26__device_stub__Z6kernelPfiPfi
.type _Z26__device_stub__Z6kernelPfiPfi, @function
_Z26__device_stub__Z6kernelPfiPfi:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z26__device_stub__Z6kernelPfiPfi, .-_Z26__device_stub__Z6kernelPfiPfi
.globl _Z6kernelPfi
.type _Z6kernelPfi, @function
_Z6kernelPfi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6kernelPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6kernelPfi, .-_Z6kernelPfi
.section .rodata.str1.1
.LC2:
.string "%f %f\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $4000000, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z14checkCudaError9cudaError
movl $0, %eax
movsd .LC1(%rip), %xmm1
.L23:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $1000000, %rax
jne .L23
movl $1, %ecx
movl $4000000, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z14checkCudaError9cudaError
movl $1, %edx
movl $1000000, %esi
movq %rbx, %rdi
call _Z20incrementArrayOnHostPfii
movl $250000, 16(%rsp)
movl $1, 20(%rsp)
movl $4, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L24:
movl $2, %ecx
movl $4000000, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z14checkCudaError9cudaError
movl $1000000, %eax
.L25:
subl $1, %eax
jne .L25
movl $0, %r12d
leaq .LC2(%rip), %r13
.L26:
pxor %xmm0, %xmm0
cvtss2sd (%rbx,%r12), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 0(%rbp,%r12), %xmm1
movq %r13, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $4, %r12
cmpq $40, %r12
jne .L26
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movl $1000000, %esi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z6kernelPfiPfi
jmp .L24
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z6kernelPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1079574528
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <assert.h>
#include <string.h>
#include <cuda.h>
#define BLOCK_SIZE 4
void checkCudaError(cudaError_t errorCode)
{
if (errorCode != cudaSuccess)
fprintf(stderr, "Error %d\n", errorCode);
}
void incrementArrayOnHost(float *a, int size, int k)
{
int i;
for (i = 0; i < size; i++)
a[i] += k;
}
__global__ void kernel(float *a, int size)
{
int numBlockThread = blockDim.x*blockDim.y*blockDim.z;
int blockRowOffset = blockIdx.x*gridDim.y*gridDim.z*numBlockThread;
int blockColOffset = blockIdx.y*gridDim.z*numBlockThread;
int blockDepOffset = blockIdx.z*numBlockThread;
int blockPos = blockRowOffset + blockColOffset + blockDepOffset;
int threadRowOffset = threadIdx.x*blockDim.y*blockDim.z;
int threadColOffset = threadIdx.y*blockDim.z;
int threadDepOffset = threadIdx.z;
int threadPos = threadRowOffset + threadColOffset + threadDepOffset;
int idx = blockPos + threadPos;
if (idx < size)
a[idx] += 1.0;
}
int main(void)
{
float *ha, *hb; // host data
float *da; // device data
int N = 1000000;
int nbytes, i;
nbytes = N * sizeof(float);
ha = (float *) malloc(nbytes);
hb = (float *) malloc(nbytes);
checkCudaError(cudaMalloc((void **) &da, nbytes));
for (i = 0; i < N; i++)
ha[i] = 100.0 + i;
checkCudaError(cudaMemcpy(da, ha, nbytes, cudaMemcpyHostToDevice));
incrementArrayOnHost(ha, N, 1.0);
int nblocks = N/BLOCK_SIZE + (N%BLOCK_SIZE==0?0:1);
dim3 grid(nblocks);
dim3 block(BLOCK_SIZE);
kernel<<<grid, block>>>(da, N);
checkCudaError(cudaMemcpy(hb, da, nbytes, cudaMemcpyDeviceToHost));
for (i = 0; i < N; i++)
assert(ha[i] == hb[i]);
for (i = 0; i < 10; i++)
printf("%f %f\n", ha[i], hb[i]);
return 0;
} | #include <stdio.h>
#include <assert.h>
#include <string.h>
#include <hip/hip_runtime.h>
#define BLOCK_SIZE 4
void checkCudaError(hipError_t errorCode)
{
if (errorCode != hipSuccess)
fprintf(stderr, "Error %d\n", errorCode);
}
void incrementArrayOnHost(float *a, int size, int k)
{
int i;
for (i = 0; i < size; i++)
a[i] += k;
}
__global__ void kernel(float *a, int size)
{
int numBlockThread = blockDim.x*blockDim.y*blockDim.z;
int blockRowOffset = blockIdx.x*gridDim.y*gridDim.z*numBlockThread;
int blockColOffset = blockIdx.y*gridDim.z*numBlockThread;
int blockDepOffset = blockIdx.z*numBlockThread;
int blockPos = blockRowOffset + blockColOffset + blockDepOffset;
int threadRowOffset = threadIdx.x*blockDim.y*blockDim.z;
int threadColOffset = threadIdx.y*blockDim.z;
int threadDepOffset = threadIdx.z;
int threadPos = threadRowOffset + threadColOffset + threadDepOffset;
int idx = blockPos + threadPos;
if (idx < size)
a[idx] += 1.0;
}
int main(void)
{
float *ha, *hb; // host data
float *da; // device data
int N = 1000000;
int nbytes, i;
nbytes = N * sizeof(float);
ha = (float *) malloc(nbytes);
hb = (float *) malloc(nbytes);
checkCudaError(hipMalloc((void **) &da, nbytes));
for (i = 0; i < N; i++)
ha[i] = 100.0 + i;
checkCudaError(hipMemcpy(da, ha, nbytes, hipMemcpyHostToDevice));
incrementArrayOnHost(ha, N, 1.0);
int nblocks = N/BLOCK_SIZE + (N%BLOCK_SIZE==0?0:1);
dim3 grid(nblocks);
dim3 block(BLOCK_SIZE);
kernel<<<grid, block>>>(da, N);
checkCudaError(hipMemcpy(hb, da, nbytes, hipMemcpyDeviceToHost));
for (i = 0; i < N; i++)
assert(ha[i] == hb[i]);
for (i = 0; i < 10; i++)
printf("%f %f\n", ha[i], hb[i]);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <assert.h>
#include <string.h>
#include <hip/hip_runtime.h>
#define BLOCK_SIZE 4
void checkCudaError(hipError_t errorCode)
{
if (errorCode != hipSuccess)
fprintf(stderr, "Error %d\n", errorCode);
}
void incrementArrayOnHost(float *a, int size, int k)
{
int i;
for (i = 0; i < size; i++)
a[i] += k;
}
__global__ void kernel(float *a, int size)
{
int numBlockThread = blockDim.x*blockDim.y*blockDim.z;
int blockRowOffset = blockIdx.x*gridDim.y*gridDim.z*numBlockThread;
int blockColOffset = blockIdx.y*gridDim.z*numBlockThread;
int blockDepOffset = blockIdx.z*numBlockThread;
int blockPos = blockRowOffset + blockColOffset + blockDepOffset;
int threadRowOffset = threadIdx.x*blockDim.y*blockDim.z;
int threadColOffset = threadIdx.y*blockDim.z;
int threadDepOffset = threadIdx.z;
int threadPos = threadRowOffset + threadColOffset + threadDepOffset;
int idx = blockPos + threadPos;
if (idx < size)
a[idx] += 1.0;
}
int main(void)
{
float *ha, *hb; // host data
float *da; // device data
int N = 1000000;
int nbytes, i;
nbytes = N * sizeof(float);
ha = (float *) malloc(nbytes);
hb = (float *) malloc(nbytes);
checkCudaError(hipMalloc((void **) &da, nbytes));
for (i = 0; i < N; i++)
ha[i] = 100.0 + i;
checkCudaError(hipMemcpy(da, ha, nbytes, hipMemcpyHostToDevice));
incrementArrayOnHost(ha, N, 1.0);
int nblocks = N/BLOCK_SIZE + (N%BLOCK_SIZE==0?0:1);
dim3 grid(nblocks);
dim3 block(BLOCK_SIZE);
kernel<<<grid, block>>>(da, N);
checkCudaError(hipMemcpy(hb, da, nbytes, hipMemcpyDeviceToHost));
for (i = 0; i < N; i++)
assert(ha[i] == hb[i]);
for (i = 0; i < 10; i++)
printf("%f %f\n", ha[i], hb[i]);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPfi
.globl _Z6kernelPfi
.p2align 8
.type _Z6kernelPfi,@function
_Z6kernelPfi:
s_load_b128 s[4:7], s[0:1], 0x14
v_and_b32_e32 v1, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s4, s13
s_and_b32 s3, s6, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s2, s2, s5
s_add_i32 s2, s2, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s2, s3, v[1:2]
v_bfe_u32 v1, v0, 10, 10
s_load_b32 s2, s[0:1], 0x8
s_lshr_b32 s3, s6, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, v2, s3, v[1:2]
v_bfe_u32 v2, v0, 20, 10
s_and_b32 s3, s7, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, v3, s3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, 1.0, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPfi, .Lfunc_end0-_Z6kernelPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <assert.h>
#include <string.h>
#include <hip/hip_runtime.h>
#define BLOCK_SIZE 4
void checkCudaError(hipError_t errorCode)
{
if (errorCode != hipSuccess)
fprintf(stderr, "Error %d\n", errorCode);
}
void incrementArrayOnHost(float *a, int size, int k)
{
int i;
for (i = 0; i < size; i++)
a[i] += k;
}
__global__ void kernel(float *a, int size)
{
int numBlockThread = blockDim.x*blockDim.y*blockDim.z;
int blockRowOffset = blockIdx.x*gridDim.y*gridDim.z*numBlockThread;
int blockColOffset = blockIdx.y*gridDim.z*numBlockThread;
int blockDepOffset = blockIdx.z*numBlockThread;
int blockPos = blockRowOffset + blockColOffset + blockDepOffset;
int threadRowOffset = threadIdx.x*blockDim.y*blockDim.z;
int threadColOffset = threadIdx.y*blockDim.z;
int threadDepOffset = threadIdx.z;
int threadPos = threadRowOffset + threadColOffset + threadDepOffset;
int idx = blockPos + threadPos;
if (idx < size)
a[idx] += 1.0;
}
int main(void)
{
float *ha, *hb; // host data
float *da; // device data
int N = 1000000;
int nbytes, i;
nbytes = N * sizeof(float);
ha = (float *) malloc(nbytes);
hb = (float *) malloc(nbytes);
checkCudaError(hipMalloc((void **) &da, nbytes));
for (i = 0; i < N; i++)
ha[i] = 100.0 + i;
checkCudaError(hipMemcpy(da, ha, nbytes, hipMemcpyHostToDevice));
incrementArrayOnHost(ha, N, 1.0);
int nblocks = N/BLOCK_SIZE + (N%BLOCK_SIZE==0?0:1);
dim3 grid(nblocks);
dim3 block(BLOCK_SIZE);
kernel<<<grid, block>>>(da, N);
checkCudaError(hipMemcpy(hb, da, nbytes, hipMemcpyDeviceToHost));
for (i = 0; i < N; i++)
assert(ha[i] == hb[i]);
for (i = 0; i < 10; i++)
printf("%f %f\n", ha[i], hb[i]);
return 0;
} | .text
.file "topic2.hip"
.globl _Z14checkCudaError10hipError_t # -- Begin function _Z14checkCudaError10hipError_t
.p2align 4, 0x90
.type _Z14checkCudaError10hipError_t,@function
_Z14checkCudaError10hipError_t: # @_Z14checkCudaError10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
retq
.LBB0_2:
movl %edi, %edx
movq stderr(%rip), %rdi
movl $.L.str, %esi
xorl %eax, %eax
jmp fprintf # TAILCALL
.Lfunc_end0:
.size _Z14checkCudaError10hipError_t, .Lfunc_end0-_Z14checkCudaError10hipError_t
.cfi_endproc
# -- End function
.globl _Z20incrementArrayOnHostPfii # -- Begin function _Z20incrementArrayOnHostPfii
.p2align 4, 0x90
.type _Z20incrementArrayOnHostPfii,@function
_Z20incrementArrayOnHostPfii: # @_Z20incrementArrayOnHostPfii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph
cvtsi2ss %edx, %xmm0
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
movss (%rdi,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm0, %xmm1
movss %xmm1, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z20incrementArrayOnHostPfii, .Lfunc_end1-_Z20incrementArrayOnHostPfii
.cfi_endproc
# -- End function
.globl _Z21__device_stub__kernelPfi # -- Begin function _Z21__device_stub__kernelPfi
.p2align 4, 0x90
.type _Z21__device_stub__kernelPfi,@function
_Z21__device_stub__kernelPfi: # @_Z21__device_stub__kernelPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z21__device_stub__kernelPfi, .Lfunc_end2-_Z21__device_stub__kernelPfi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x3f800000 # float 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %rbx
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
testl %eax, %eax
jne .LBB3_1
.LBB3_2: # %_Z14checkCudaError10hipError_t.exit.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_3: # %_Z14checkCudaError10hipError_t.exit
# =>This Inner Loop Header: Depth=1
leal 100(%rax), %ecx
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $1000000, %rax # imm = 0xF4240
jne .LBB3_3
# %bb.4:
movq 8(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_5
.LBB3_6: # %_Z14checkCudaError10hipError_t.exit35.preheader
xorl %eax, %eax
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB3_7: # %_Z14checkCudaError10hipError_t.exit35
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm0, %xmm1
movss %xmm1, (%rbx,%rax,4)
incq %rax
cmpq $1000000, %rax # imm = 0xF4240
jne .LBB3_7
# %bb.8: # %_Z20incrementArrayOnHostPfii.exit
movabsq $4294967300, %rdx # imm = 0x100000004
leaq 249996(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_10
# %bb.9:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $1000000, 20(%rsp) # imm = 0xF4240
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPfi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_10:
movq 8(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_11
.LBB3_12: # %.preheader.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_13: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%r14,%r15,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.1, %edi
movb $2, %al
callq printf
incq %r15
cmpq $10, %r15
jne .LBB3_13
# %bb.14:
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_1:
.cfi_def_cfa_offset 128
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB3_2
.LBB3_5:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB3_6
.LBB3_11:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB3_12
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error %d\n"
.size .L.str, 10
.type _Z6kernelPfi,@object # @_Z6kernelPfi
.section .rodata,"a",@progbits
.globl _Z6kernelPfi
.p2align 3, 0x0
_Z6kernelPfi:
.quad _Z21__device_stub__kernelPfi
.size _Z6kernelPfi, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%f %f\n"
.size .L.str.1, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPfi"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0030*/ S2R R5, SR_CTAID.Z ; /* 0x0000000000057919 */
/* 0x000e680000002700 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea80000002100 */
/*0050*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000ee80000002200 */
/*0060*/ S2R R11, SR_TID.Z ; /* 0x00000000000b7919 */
/* 0x000f220000002300 */
/*0070*/ IMAD R0, R0, c[0x0][0x10], R3 ; /* 0x0000040000007a24 */
/* 0x001fc800078e0203 */
/*0080*/ IMAD R0, R0, c[0x0][0x14], R5 ; /* 0x0000050000007a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fc800078e0207 */
/*00a0*/ IMAD R0, R0, c[0x0][0x4], R9 ; /* 0x0000010000007a24 */
/* 0x008fc800078e0209 */
/*00b0*/ IMAD R0, R0, c[0x0][0x8], R11 ; /* 0x0000020000007a24 */
/* 0x010fca00078e020b */
/*00c0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0100*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0110*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0120*/ FADD R5, R0, 1 ; /* 0x3f80000000057421 */
/* 0x004fca0000000000 */
/*0130*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPfi
.globl _Z6kernelPfi
.p2align 8
.type _Z6kernelPfi,@function
_Z6kernelPfi:
s_load_b128 s[4:7], s[0:1], 0x14
v_and_b32_e32 v1, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s4, s13
s_and_b32 s3, s6, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s2, s2, s5
s_add_i32 s2, s2, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s2, s3, v[1:2]
v_bfe_u32 v1, v0, 10, 10
s_load_b32 s2, s[0:1], 0x8
s_lshr_b32 s3, s6, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, v2, s3, v[1:2]
v_bfe_u32 v2, v0, 20, 10
s_and_b32 s3, s7, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, v3, s3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, 1.0, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPfi, .Lfunc_end0-_Z6kernelPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000958ff_00000000-6_topic2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Error %d\n"
.text
.globl _Z14checkCudaError9cudaError
.type _Z14checkCudaError9cudaError, @function
_Z14checkCudaError9cudaError:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
subq $8, %rsp
.cfi_def_cfa_offset 16
movl %edi, %ecx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z14checkCudaError9cudaError, .-_Z14checkCudaError9cudaError
.globl _Z20incrementArrayOnHostPfii
.type _Z20incrementArrayOnHostPfii, @function
_Z20incrementArrayOnHostPfii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L10
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rcx
pxor %xmm1, %xmm1
cvtsi2ssl %edx, %xmm1
.L12:
movaps %xmm1, %xmm0
addss (%rax), %xmm0
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L12
.L10:
ret
.cfi_endproc
.LFE2058:
.size _Z20incrementArrayOnHostPfii, .-_Z20incrementArrayOnHostPfii
.globl _Z26__device_stub__Z6kernelPfiPfi
.type _Z26__device_stub__Z6kernelPfiPfi, @function
_Z26__device_stub__Z6kernelPfiPfi:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z26__device_stub__Z6kernelPfiPfi, .-_Z26__device_stub__Z6kernelPfiPfi
.globl _Z6kernelPfi
.type _Z6kernelPfi, @function
_Z6kernelPfi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6kernelPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6kernelPfi, .-_Z6kernelPfi
.section .rodata.str1.1
.LC2:
.string "%f %f\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $4000000, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z14checkCudaError9cudaError
movl $0, %eax
movsd .LC1(%rip), %xmm1
.L23:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $1000000, %rax
jne .L23
movl $1, %ecx
movl $4000000, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z14checkCudaError9cudaError
movl $1, %edx
movl $1000000, %esi
movq %rbx, %rdi
call _Z20incrementArrayOnHostPfii
movl $250000, 16(%rsp)
movl $1, 20(%rsp)
movl $4, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L24:
movl $2, %ecx
movl $4000000, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z14checkCudaError9cudaError
movl $1000000, %eax
.L25:
subl $1, %eax
jne .L25
movl $0, %r12d
leaq .LC2(%rip), %r13
.L26:
pxor %xmm0, %xmm0
cvtss2sd (%rbx,%r12), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 0(%rbp,%r12), %xmm1
movq %r13, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $4, %r12
cmpq $40, %r12
jne .L26
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movl $1000000, %esi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z6kernelPfiPfi
jmp .L24
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z6kernelPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1079574528
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "topic2.hip"
.globl _Z14checkCudaError10hipError_t # -- Begin function _Z14checkCudaError10hipError_t
.p2align 4, 0x90
.type _Z14checkCudaError10hipError_t,@function
_Z14checkCudaError10hipError_t: # @_Z14checkCudaError10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
retq
.LBB0_2:
movl %edi, %edx
movq stderr(%rip), %rdi
movl $.L.str, %esi
xorl %eax, %eax
jmp fprintf # TAILCALL
.Lfunc_end0:
.size _Z14checkCudaError10hipError_t, .Lfunc_end0-_Z14checkCudaError10hipError_t
.cfi_endproc
# -- End function
.globl _Z20incrementArrayOnHostPfii # -- Begin function _Z20incrementArrayOnHostPfii
.p2align 4, 0x90
.type _Z20incrementArrayOnHostPfii,@function
_Z20incrementArrayOnHostPfii: # @_Z20incrementArrayOnHostPfii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph
cvtsi2ss %edx, %xmm0
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
movss (%rdi,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm0, %xmm1
movss %xmm1, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z20incrementArrayOnHostPfii, .Lfunc_end1-_Z20incrementArrayOnHostPfii
.cfi_endproc
# -- End function
.globl _Z21__device_stub__kernelPfi # -- Begin function _Z21__device_stub__kernelPfi
.p2align 4, 0x90
.type _Z21__device_stub__kernelPfi,@function
_Z21__device_stub__kernelPfi: # @_Z21__device_stub__kernelPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z21__device_stub__kernelPfi, .Lfunc_end2-_Z21__device_stub__kernelPfi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x3f800000 # float 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %rbx
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
testl %eax, %eax
jne .LBB3_1
.LBB3_2: # %_Z14checkCudaError10hipError_t.exit.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_3: # %_Z14checkCudaError10hipError_t.exit
# =>This Inner Loop Header: Depth=1
leal 100(%rax), %ecx
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $1000000, %rax # imm = 0xF4240
jne .LBB3_3
# %bb.4:
movq 8(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_5
.LBB3_6: # %_Z14checkCudaError10hipError_t.exit35.preheader
xorl %eax, %eax
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB3_7: # %_Z14checkCudaError10hipError_t.exit35
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm0, %xmm1
movss %xmm1, (%rbx,%rax,4)
incq %rax
cmpq $1000000, %rax # imm = 0xF4240
jne .LBB3_7
# %bb.8: # %_Z20incrementArrayOnHostPfii.exit
movabsq $4294967300, %rdx # imm = 0x100000004
leaq 249996(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_10
# %bb.9:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $1000000, 20(%rsp) # imm = 0xF4240
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPfi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_10:
movq 8(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_11
.LBB3_12: # %.preheader.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_13: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%r14,%r15,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.1, %edi
movb $2, %al
callq printf
incq %r15
cmpq $10, %r15
jne .LBB3_13
# %bb.14:
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_1:
.cfi_def_cfa_offset 128
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB3_2
.LBB3_5:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB3_6
.LBB3_11:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB3_12
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error %d\n"
.size .L.str, 10
.type _Z6kernelPfi,@object # @_Z6kernelPfi
.section .rodata,"a",@progbits
.globl _Z6kernelPfi
.p2align 3, 0x0
_Z6kernelPfi:
.quad _Z21__device_stub__kernelPfi
.size _Z6kernelPfi, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%f %f\n"
.size .L.str.1, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPfi"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
File name: graph_to_csr.cu
Author: Yuede Ji
Last update: 15:52 10-09-2015
Description: convert current normal graph file to scr and begin position stored file
**/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#define N 65536 // vertex number
//Using arrays to implement queue
/**
char filein[] = "/home/yuede/dataset/kron_16_16.dat";
char fileout[] = "/home/yuede/dataset/kron_16_16.cpu.as.result";
char file_beg_pos[] = "/home/yuede/dataset/kron_16_16.beg.pos";
char file_csr[] = "/home/yuede/dataset/kron_16_16.csr";
char file_v_e[] = "/home/yuede/dataset/kron_16_16.v_e";
**/
char filein[] = "/home/yuede/dataset/kron_10_4.dat";
char fileout[] = "/home/yuede/dataset/kron_10_4.cpu.as.result";
char file_beg_pos[] = "/home/yuede/dataset/kron_10_4.beg.pos";
char file_csr[] = "/home/yuede/dataset/kron_10_4.csr";
char file_v_e[] = "/home/yuede/dataset/kron_10_4.v_e";
const int INF = 0x7FFFFFFF;
int v_num = 0;
int e_num = 0;
void empty_file(char * filename)
{
FILE * fp = fopen(filename, "w");
fclose(fp);
}
//load from .dat files, and store in array csr[N*N], beg_pos[N]
void csr_begin(char *filename)
{
empty_file(file_beg_pos);
empty_file(file_csr);
FILE * fp_in = fopen(filein, "r");
FILE * fp_csr = fopen(file_csr, "a");
FILE * fp_beg_pos = fopen(file_beg_pos, "a");
int v, n;//v denotes current vertex, n denotes no. of adjacent node
int j = 0;// j denotes the index in csr[N*N];
int begin = 0;
fprintf(fp_beg_pos, "%d\n", begin);
while(fscanf(fp_in, "%d%d", &v, &n)!=EOF)
{
//printf("%d %d\n", v, n);
begin += n;
fprintf(fp_beg_pos, "%d\n", begin);
for(int i=0; i<n; ++i)
{
fscanf(fp_in, "%d", &j);
fprintf(fp_csr, "%d\n", j);
}
}
fclose(fp_beg_pos);
fclose(fp_csr);
e_num = begin+1;
v_num = v+1;
printf("v_num = %d, e_num = %d\n", v_num, e_num);
FILE *fp_v_e = fopen(file_v_e, "w");
fprintf(fp_v_e, "%d %d\n", v_num, e_num);
fclose(fp_v_e);
}
int main()
{
csr_begin(filein);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
File name: graph_to_csr.cu
Author: Yuede Ji
Last update: 15:52 10-09-2015
Description: convert current normal graph file to scr and begin position stored file
**/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#define N 65536 // vertex number
//Using arrays to implement queue
/**
char filein[] = "/home/yuede/dataset/kron_16_16.dat";
char fileout[] = "/home/yuede/dataset/kron_16_16.cpu.as.result";
char file_beg_pos[] = "/home/yuede/dataset/kron_16_16.beg.pos";
char file_csr[] = "/home/yuede/dataset/kron_16_16.csr";
char file_v_e[] = "/home/yuede/dataset/kron_16_16.v_e";
**/
char filein[] = "/home/yuede/dataset/kron_10_4.dat";
char fileout[] = "/home/yuede/dataset/kron_10_4.cpu.as.result";
char file_beg_pos[] = "/home/yuede/dataset/kron_10_4.beg.pos";
char file_csr[] = "/home/yuede/dataset/kron_10_4.csr";
char file_v_e[] = "/home/yuede/dataset/kron_10_4.v_e";
const int INF = 0x7FFFFFFF;
int v_num = 0;
int e_num = 0;
void empty_file(char * filename)
{
FILE * fp = fopen(filename, "w");
fclose(fp);
}
//load from .dat files, and store in array csr[N*N], beg_pos[N]
void csr_begin(char *filename)
{
empty_file(file_beg_pos);
empty_file(file_csr);
FILE * fp_in = fopen(filein, "r");
FILE * fp_csr = fopen(file_csr, "a");
FILE * fp_beg_pos = fopen(file_beg_pos, "a");
int v, n;//v denotes current vertex, n denotes no. of adjacent node
int j = 0;// j denotes the index in csr[N*N];
int begin = 0;
fprintf(fp_beg_pos, "%d\n", begin);
while(fscanf(fp_in, "%d%d", &v, &n)!=EOF)
{
//printf("%d %d\n", v, n);
begin += n;
fprintf(fp_beg_pos, "%d\n", begin);
for(int i=0; i<n; ++i)
{
fscanf(fp_in, "%d", &j);
fprintf(fp_csr, "%d\n", j);
}
}
fclose(fp_beg_pos);
fclose(fp_csr);
e_num = begin+1;
v_num = v+1;
printf("v_num = %d, e_num = %d\n", v_num, e_num);
FILE *fp_v_e = fopen(file_v_e, "w");
fprintf(fp_v_e, "%d %d\n", v_num, e_num);
fclose(fp_v_e);
}
int main()
{
csr_begin(filein);
return 0;
} | .file "tmpxft_0017daf1_00000000-6_graph_to_csr.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "w"
.text
.globl _Z10empty_filePc
.type _Z10empty_filePc, @function
_Z10empty_filePc:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %rdi
call fclose@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10empty_filePc, .-_Z10empty_filePc
.section .rodata.str1.1
.LC1:
.string "r"
.LC2:
.string "a"
.LC3:
.string "%d\n"
.LC4:
.string "%d"
.LC5:
.string "%d%d"
.LC6:
.string "v_num = %d, e_num = %d\n"
.LC7:
.string "%d %d\n"
.text
.globl _Z9csr_beginPc
.type _Z9csr_beginPc, @function
_Z9csr_beginPc:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq file_beg_pos(%rip), %rbx
movq %rbx, %rdi
call _Z10empty_filePc
leaq file_csr(%rip), %r13
movq %r13, %rdi
call _Z10empty_filePc
leaq .LC1(%rip), %rsi
leaq filein(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
leaq .LC2(%rip), %r12
movq %r12, %rsi
movq %r13, %rdi
call fopen@PLT
movq %rax, %r14
movq %r12, %rsi
movq %rbx, %rdi
call fopen@PLT
movq %rax, 16(%rsp)
movl $0, 52(%rsp)
movl $0, %ecx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, 12(%rsp)
leaq 48(%rsp), %rax
movq %rax, 24(%rsp)
leaq .LC3(%rip), %r12
leaq .LC4(%rip), %r15
.L6:
leaq 44(%rsp), %rdx
movq 24(%rsp), %rcx
leaq .LC5(%rip), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $-1, %eax
je .L13
movl 12(%rsp), %ecx
addl 48(%rsp), %ecx
movl %ecx, 12(%rsp)
movq %r12, %rdx
movl $2, %esi
movq 16(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
cmpl $0, 48(%rsp)
jle .L6
movl $0, %ebx
leaq 52(%rsp), %r13
.L8:
movq %r13, %rdx
movq %r15, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 52(%rsp), %ecx
movq %r12, %rdx
movl $2, %esi
movq %r14, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %ebx
cmpl %ebx, 48(%rsp)
jg .L8
jmp .L6
.L13:
movq 16(%rsp), %rdi
call fclose@PLT
movq %r14, %rdi
call fclose@PLT
movl 12(%rsp), %ecx
addl $1, %ecx
movl %ecx, e_num(%rip)
movl 44(%rsp), %eax
leal 1(%rax), %edx
movl %edx, v_num(%rip)
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC0(%rip), %rsi
leaq file_v_e(%rip), %rdi
call fopen@PLT
movq %rax, %rbx
movl e_num(%rip), %r8d
movl v_num(%rip), %ecx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rbx, %rdi
call fclose@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z9csr_beginPc, .-_Z9csr_beginPc
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq filein(%rip), %rdi
call _Z9csr_beginPc
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl e_num
.bss
.align 4
.type e_num, @object
.size e_num, 4
e_num:
.zero 4
.globl v_num
.align 4
.type v_num, @object
.size v_num, 4
v_num:
.zero 4
.globl file_v_e
.data
.align 32
.type file_v_e, @object
.size file_v_e, 34
file_v_e:
.string "/home/yuede/dataset/kron_10_4.v_e"
.globl file_csr
.align 32
.type file_csr, @object
.size file_csr, 34
file_csr:
.string "/home/yuede/dataset/kron_10_4.csr"
.globl file_beg_pos
.align 32
.type file_beg_pos, @object
.size file_beg_pos, 38
file_beg_pos:
.string "/home/yuede/dataset/kron_10_4.beg.pos"
.globl fileout
.align 32
.type fileout, @object
.size fileout, 44
fileout:
.string "/home/yuede/dataset/kron_10_4.cpu.as.result"
.globl filein
.align 32
.type filein, @object
.size filein, 34
filein:
.string "/home/yuede/dataset/kron_10_4.dat"
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
File name: graph_to_csr.cu
Author: Yuede Ji
Last update: 15:52 10-09-2015
Description: convert current normal graph file to scr and begin position stored file
**/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#define N 65536 // vertex number
//Using arrays to implement queue
/**
char filein[] = "/home/yuede/dataset/kron_16_16.dat";
char fileout[] = "/home/yuede/dataset/kron_16_16.cpu.as.result";
char file_beg_pos[] = "/home/yuede/dataset/kron_16_16.beg.pos";
char file_csr[] = "/home/yuede/dataset/kron_16_16.csr";
char file_v_e[] = "/home/yuede/dataset/kron_16_16.v_e";
**/
char filein[] = "/home/yuede/dataset/kron_10_4.dat";
char fileout[] = "/home/yuede/dataset/kron_10_4.cpu.as.result";
char file_beg_pos[] = "/home/yuede/dataset/kron_10_4.beg.pos";
char file_csr[] = "/home/yuede/dataset/kron_10_4.csr";
char file_v_e[] = "/home/yuede/dataset/kron_10_4.v_e";
const int INF = 0x7FFFFFFF;
int v_num = 0;
int e_num = 0;
void empty_file(char * filename)
{
FILE * fp = fopen(filename, "w");
fclose(fp);
}
//load from .dat files, and store in array csr[N*N], beg_pos[N]
void csr_begin(char *filename)
{
empty_file(file_beg_pos);
empty_file(file_csr);
FILE * fp_in = fopen(filein, "r");
FILE * fp_csr = fopen(file_csr, "a");
FILE * fp_beg_pos = fopen(file_beg_pos, "a");
int v, n;//v denotes current vertex, n denotes no. of adjacent node
int j = 0;// j denotes the index in csr[N*N];
int begin = 0;
fprintf(fp_beg_pos, "%d\n", begin);
while(fscanf(fp_in, "%d%d", &v, &n)!=EOF)
{
//printf("%d %d\n", v, n);
begin += n;
fprintf(fp_beg_pos, "%d\n", begin);
for(int i=0; i<n; ++i)
{
fscanf(fp_in, "%d", &j);
fprintf(fp_csr, "%d\n", j);
}
}
fclose(fp_beg_pos);
fclose(fp_csr);
e_num = begin+1;
v_num = v+1;
printf("v_num = %d, e_num = %d\n", v_num, e_num);
FILE *fp_v_e = fopen(file_v_e, "w");
fprintf(fp_v_e, "%d %d\n", v_num, e_num);
fclose(fp_v_e);
}
int main()
{
csr_begin(filein);
return 0;
} | /**
File name: graph_to_csr.cu
Author: Yuede Ji
Last update: 15:52 10-09-2015
Description: convert current normal graph file to scr and begin position stored file
**/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#define N 65536 // vertex number
//Using arrays to implement queue
/**
char filein[] = "/home/yuede/dataset/kron_16_16.dat";
char fileout[] = "/home/yuede/dataset/kron_16_16.cpu.as.result";
char file_beg_pos[] = "/home/yuede/dataset/kron_16_16.beg.pos";
char file_csr[] = "/home/yuede/dataset/kron_16_16.csr";
char file_v_e[] = "/home/yuede/dataset/kron_16_16.v_e";
**/
char filein[] = "/home/yuede/dataset/kron_10_4.dat";
char fileout[] = "/home/yuede/dataset/kron_10_4.cpu.as.result";
char file_beg_pos[] = "/home/yuede/dataset/kron_10_4.beg.pos";
char file_csr[] = "/home/yuede/dataset/kron_10_4.csr";
char file_v_e[] = "/home/yuede/dataset/kron_10_4.v_e";
const int INF = 0x7FFFFFFF;
int v_num = 0;
int e_num = 0;
void empty_file(char * filename)
{
FILE * fp = fopen(filename, "w");
fclose(fp);
}
//load from .dat files, and store in array csr[N*N], beg_pos[N]
void csr_begin(char *filename)
{
empty_file(file_beg_pos);
empty_file(file_csr);
FILE * fp_in = fopen(filein, "r");
FILE * fp_csr = fopen(file_csr, "a");
FILE * fp_beg_pos = fopen(file_beg_pos, "a");
int v, n;//v denotes current vertex, n denotes no. of adjacent node
int j = 0;// j denotes the index in csr[N*N];
int begin = 0;
fprintf(fp_beg_pos, "%d\n", begin);
while(fscanf(fp_in, "%d%d", &v, &n)!=EOF)
{
//printf("%d %d\n", v, n);
begin += n;
fprintf(fp_beg_pos, "%d\n", begin);
for(int i=0; i<n; ++i)
{
fscanf(fp_in, "%d", &j);
fprintf(fp_csr, "%d\n", j);
}
}
fclose(fp_beg_pos);
fclose(fp_csr);
e_num = begin+1;
v_num = v+1;
printf("v_num = %d, e_num = %d\n", v_num, e_num);
FILE *fp_v_e = fopen(file_v_e, "w");
fprintf(fp_v_e, "%d %d\n", v_num, e_num);
fclose(fp_v_e);
}
int main()
{
csr_begin(filein);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
File name: graph_to_csr.cu
Author: Yuede Ji
Last update: 15:52 10-09-2015
Description: convert current normal graph file to scr and begin position stored file
**/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#define N 65536 // vertex number
//Using arrays to implement queue
/**
char filein[] = "/home/yuede/dataset/kron_16_16.dat";
char fileout[] = "/home/yuede/dataset/kron_16_16.cpu.as.result";
char file_beg_pos[] = "/home/yuede/dataset/kron_16_16.beg.pos";
char file_csr[] = "/home/yuede/dataset/kron_16_16.csr";
char file_v_e[] = "/home/yuede/dataset/kron_16_16.v_e";
**/
char filein[] = "/home/yuede/dataset/kron_10_4.dat";
char fileout[] = "/home/yuede/dataset/kron_10_4.cpu.as.result";
char file_beg_pos[] = "/home/yuede/dataset/kron_10_4.beg.pos";
char file_csr[] = "/home/yuede/dataset/kron_10_4.csr";
char file_v_e[] = "/home/yuede/dataset/kron_10_4.v_e";
const int INF = 0x7FFFFFFF;
int v_num = 0;
int e_num = 0;
void empty_file(char * filename)
{
FILE * fp = fopen(filename, "w");
fclose(fp);
}
//load from .dat files, and store in array csr[N*N], beg_pos[N]
void csr_begin(char *filename)
{
empty_file(file_beg_pos);
empty_file(file_csr);
FILE * fp_in = fopen(filein, "r");
FILE * fp_csr = fopen(file_csr, "a");
FILE * fp_beg_pos = fopen(file_beg_pos, "a");
int v, n;//v denotes current vertex, n denotes no. of adjacent node
int j = 0;// j denotes the index in csr[N*N];
int begin = 0;
fprintf(fp_beg_pos, "%d\n", begin);
while(fscanf(fp_in, "%d%d", &v, &n)!=EOF)
{
//printf("%d %d\n", v, n);
begin += n;
fprintf(fp_beg_pos, "%d\n", begin);
for(int i=0; i<n; ++i)
{
fscanf(fp_in, "%d", &j);
fprintf(fp_csr, "%d\n", j);
}
}
fclose(fp_beg_pos);
fclose(fp_csr);
e_num = begin+1;
v_num = v+1;
printf("v_num = %d, e_num = %d\n", v_num, e_num);
FILE *fp_v_e = fopen(file_v_e, "w");
fprintf(fp_v_e, "%d %d\n", v_num, e_num);
fclose(fp_v_e);
}
int main()
{
csr_begin(filein);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
File name: graph_to_csr.cu
Author: Yuede Ji
Last update: 15:52 10-09-2015
Description: convert current normal graph file to scr and begin position stored file
**/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#define N 65536 // vertex number
//Using arrays to implement queue
/**
char filein[] = "/home/yuede/dataset/kron_16_16.dat";
char fileout[] = "/home/yuede/dataset/kron_16_16.cpu.as.result";
char file_beg_pos[] = "/home/yuede/dataset/kron_16_16.beg.pos";
char file_csr[] = "/home/yuede/dataset/kron_16_16.csr";
char file_v_e[] = "/home/yuede/dataset/kron_16_16.v_e";
**/
char filein[] = "/home/yuede/dataset/kron_10_4.dat";
char fileout[] = "/home/yuede/dataset/kron_10_4.cpu.as.result";
char file_beg_pos[] = "/home/yuede/dataset/kron_10_4.beg.pos";
char file_csr[] = "/home/yuede/dataset/kron_10_4.csr";
char file_v_e[] = "/home/yuede/dataset/kron_10_4.v_e";
const int INF = 0x7FFFFFFF;
int v_num = 0;
int e_num = 0;
void empty_file(char * filename)
{
FILE * fp = fopen(filename, "w");
fclose(fp);
}
//load from .dat files, and store in array csr[N*N], beg_pos[N]
void csr_begin(char *filename)
{
empty_file(file_beg_pos);
empty_file(file_csr);
FILE * fp_in = fopen(filein, "r");
FILE * fp_csr = fopen(file_csr, "a");
FILE * fp_beg_pos = fopen(file_beg_pos, "a");
int v, n;//v denotes current vertex, n denotes no. of adjacent node
int j = 0;// j denotes the index in csr[N*N];
int begin = 0;
fprintf(fp_beg_pos, "%d\n", begin);
while(fscanf(fp_in, "%d%d", &v, &n)!=EOF)
{
//printf("%d %d\n", v, n);
begin += n;
fprintf(fp_beg_pos, "%d\n", begin);
for(int i=0; i<n; ++i)
{
fscanf(fp_in, "%d", &j);
fprintf(fp_csr, "%d\n", j);
}
}
fclose(fp_beg_pos);
fclose(fp_csr);
e_num = begin+1;
v_num = v+1;
printf("v_num = %d, e_num = %d\n", v_num, e_num);
FILE *fp_v_e = fopen(file_v_e, "w");
fprintf(fp_v_e, "%d %d\n", v_num, e_num);
fclose(fp_v_e);
}
int main()
{
csr_begin(filein);
return 0;
} | .text
.file "graph_to_csr.hip"
.globl _Z10empty_filePc # -- Begin function _Z10empty_filePc
.p2align 4, 0x90
.type _Z10empty_filePc,@function
_Z10empty_filePc: # @_Z10empty_filePc
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.L.str, %esi
callq fopen
movq %rax, %rdi
popq %rax
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end0:
.size _Z10empty_filePc, .Lfunc_end0-_Z10empty_filePc
.cfi_endproc
# -- End function
.globl _Z9csr_beginPc # -- Begin function _Z9csr_beginPc
.p2align 4, 0x90
.type _Z9csr_beginPc,@function
_Z9csr_beginPc: # @_Z9csr_beginPc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $file_beg_pos, %edi
movl $.L.str, %esi
callq fopen
movq %rax, %rdi
callq fclose
movl $file_csr, %edi
movl $.L.str, %esi
callq fopen
movq %rax, %rdi
callq fclose
movl $filein, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r14
movl $file_csr, %edi
movl $.L.str.2, %esi
callq fopen
movq %rax, %rbx
movl $file_beg_pos, %edi
movl $.L.str.2, %esi
callq fopen
movq %rax, %r15
movl $0, 16(%rsp)
movl $.L.str.3, %esi
movq %rax, %rdi
xorl %edx, %edx
xorl %eax, %eax
callq fprintf
leaq 20(%rsp), %rdx
leaq 12(%rsp), %rcx
movl $.L.str.4, %esi
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
je .LBB1_1
# %bb.2: # %.lr.ph18.preheader
leaq 16(%rsp), %r12
xorl %ebp, %ebp
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_3: # %.loopexit
# in Loop: Header=BB1_4 Depth=1
movl $.L.str.4, %esi
movq %r14, %rdi
leaq 20(%rsp), %rdx
leaq 12(%rsp), %rcx
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
je .LBB1_7
.LBB1_4: # %.lr.ph18
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
addl 12(%rsp), %ebp
movl $.L.str.3, %esi
movq %r15, %rdi
movl %ebp, %edx
xorl %eax, %eax
callq fprintf
cmpl $0, 12(%rsp)
jle .LBB1_3
# %bb.5: # %.lr.ph.preheader
# in Loop: Header=BB1_4 Depth=1
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# Parent Loop BB1_4 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.5, %esi
movq %r14, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl 16(%rsp), %edx
movl $.L.str.3, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
incl %r13d
cmpl 12(%rsp), %r13d
jl .LBB1_6
jmp .LBB1_3
.LBB1_7: # %._crit_edge.loopexit
incl %ebp
jmp .LBB1_8
.LBB1_1:
movl $1, %ebp
.LBB1_8: # %._crit_edge
movq %r15, %rdi
callq fclose
movq %rbx, %rdi
callq fclose
movl %ebp, e_num(%rip)
movl 20(%rsp), %esi
incl %esi
movl %esi, v_num(%rip)
movl $.L.str.6, %edi
movl %ebp, %edx
xorl %eax, %eax
callq printf
movl $file_v_e, %edi
movl $.L.str, %esi
callq fopen
movq %rax, %rbx
movl v_num(%rip), %edx
movl e_num(%rip), %ecx
movl $.L.str.7, %esi
movq %rax, %rdi
xorl %eax, %eax
callq fprintf
movq %rbx, %rdi
callq fclose
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9csr_beginPc, .Lfunc_end1-_Z9csr_beginPc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z9csr_beginPc
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.type filein,@object # @filein
.data
.globl filein
.p2align 4, 0x0
filein:
.asciz "/home/yuede/dataset/kron_10_4.dat"
.size filein, 34
.type fileout,@object # @fileout
.globl fileout
.p2align 4, 0x0
fileout:
.asciz "/home/yuede/dataset/kron_10_4.cpu.as.result"
.size fileout, 44
.type file_beg_pos,@object # @file_beg_pos
.globl file_beg_pos
.p2align 4, 0x0
file_beg_pos:
.asciz "/home/yuede/dataset/kron_10_4.beg.pos"
.size file_beg_pos, 38
.type file_csr,@object # @file_csr
.globl file_csr
.p2align 4, 0x0
file_csr:
.asciz "/home/yuede/dataset/kron_10_4.csr"
.size file_csr, 34
.type file_v_e,@object # @file_v_e
.globl file_v_e
.p2align 4, 0x0
file_v_e:
.asciz "/home/yuede/dataset/kron_10_4.v_e"
.size file_v_e, 34
.type v_num,@object # @v_num
.bss
.globl v_num
.p2align 2, 0x0
v_num:
.long 0 # 0x0
.size v_num, 4
.type e_num,@object # @e_num
.globl e_num
.p2align 2, 0x0
e_num:
.long 0 # 0x0
.size e_num, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "w"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "a"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d\n"
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d%d"
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "v_num = %d, e_num = %d\n"
.size .L.str.6, 24
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d %d\n"
.size .L.str.7, 7
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym filein
.addrsig_sym file_beg_pos
.addrsig_sym file_csr
.addrsig_sym file_v_e
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017daf1_00000000-6_graph_to_csr.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "w"
.text
.globl _Z10empty_filePc
.type _Z10empty_filePc, @function
_Z10empty_filePc:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %rdi
call fclose@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10empty_filePc, .-_Z10empty_filePc
.section .rodata.str1.1
.LC1:
.string "r"
.LC2:
.string "a"
.LC3:
.string "%d\n"
.LC4:
.string "%d"
.LC5:
.string "%d%d"
.LC6:
.string "v_num = %d, e_num = %d\n"
.LC7:
.string "%d %d\n"
.text
.globl _Z9csr_beginPc
.type _Z9csr_beginPc, @function
_Z9csr_beginPc:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq file_beg_pos(%rip), %rbx
movq %rbx, %rdi
call _Z10empty_filePc
leaq file_csr(%rip), %r13
movq %r13, %rdi
call _Z10empty_filePc
leaq .LC1(%rip), %rsi
leaq filein(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
leaq .LC2(%rip), %r12
movq %r12, %rsi
movq %r13, %rdi
call fopen@PLT
movq %rax, %r14
movq %r12, %rsi
movq %rbx, %rdi
call fopen@PLT
movq %rax, 16(%rsp)
movl $0, 52(%rsp)
movl $0, %ecx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, 12(%rsp)
leaq 48(%rsp), %rax
movq %rax, 24(%rsp)
leaq .LC3(%rip), %r12
leaq .LC4(%rip), %r15
.L6:
leaq 44(%rsp), %rdx
movq 24(%rsp), %rcx
leaq .LC5(%rip), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $-1, %eax
je .L13
movl 12(%rsp), %ecx
addl 48(%rsp), %ecx
movl %ecx, 12(%rsp)
movq %r12, %rdx
movl $2, %esi
movq 16(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
cmpl $0, 48(%rsp)
jle .L6
movl $0, %ebx
leaq 52(%rsp), %r13
.L8:
movq %r13, %rdx
movq %r15, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 52(%rsp), %ecx
movq %r12, %rdx
movl $2, %esi
movq %r14, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %ebx
cmpl %ebx, 48(%rsp)
jg .L8
jmp .L6
.L13:
movq 16(%rsp), %rdi
call fclose@PLT
movq %r14, %rdi
call fclose@PLT
movl 12(%rsp), %ecx
addl $1, %ecx
movl %ecx, e_num(%rip)
movl 44(%rsp), %eax
leal 1(%rax), %edx
movl %edx, v_num(%rip)
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC0(%rip), %rsi
leaq file_v_e(%rip), %rdi
call fopen@PLT
movq %rax, %rbx
movl e_num(%rip), %r8d
movl v_num(%rip), %ecx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rbx, %rdi
call fclose@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z9csr_beginPc, .-_Z9csr_beginPc
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq filein(%rip), %rdi
call _Z9csr_beginPc
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl e_num
.bss
.align 4
.type e_num, @object
.size e_num, 4
e_num:
.zero 4
.globl v_num
.align 4
.type v_num, @object
.size v_num, 4
v_num:
.zero 4
.globl file_v_e
.data
.align 32
.type file_v_e, @object
.size file_v_e, 34
file_v_e:
.string "/home/yuede/dataset/kron_10_4.v_e"
.globl file_csr
.align 32
.type file_csr, @object
.size file_csr, 34
file_csr:
.string "/home/yuede/dataset/kron_10_4.csr"
.globl file_beg_pos
.align 32
.type file_beg_pos, @object
.size file_beg_pos, 38
file_beg_pos:
.string "/home/yuede/dataset/kron_10_4.beg.pos"
.globl fileout
.align 32
.type fileout, @object
.size fileout, 44
fileout:
.string "/home/yuede/dataset/kron_10_4.cpu.as.result"
.globl filein
.align 32
.type filein, @object
.size filein, 34
filein:
.string "/home/yuede/dataset/kron_10_4.dat"
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "graph_to_csr.hip"
.globl _Z10empty_filePc # -- Begin function _Z10empty_filePc
.p2align 4, 0x90
.type _Z10empty_filePc,@function
_Z10empty_filePc: # @_Z10empty_filePc
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.L.str, %esi
callq fopen
movq %rax, %rdi
popq %rax
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end0:
.size _Z10empty_filePc, .Lfunc_end0-_Z10empty_filePc
.cfi_endproc
# -- End function
.globl _Z9csr_beginPc # -- Begin function _Z9csr_beginPc
.p2align 4, 0x90
.type _Z9csr_beginPc,@function
_Z9csr_beginPc: # @_Z9csr_beginPc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $file_beg_pos, %edi
movl $.L.str, %esi
callq fopen
movq %rax, %rdi
callq fclose
movl $file_csr, %edi
movl $.L.str, %esi
callq fopen
movq %rax, %rdi
callq fclose
movl $filein, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r14
movl $file_csr, %edi
movl $.L.str.2, %esi
callq fopen
movq %rax, %rbx
movl $file_beg_pos, %edi
movl $.L.str.2, %esi
callq fopen
movq %rax, %r15
movl $0, 16(%rsp)
movl $.L.str.3, %esi
movq %rax, %rdi
xorl %edx, %edx
xorl %eax, %eax
callq fprintf
leaq 20(%rsp), %rdx
leaq 12(%rsp), %rcx
movl $.L.str.4, %esi
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
je .LBB1_1
# %bb.2: # %.lr.ph18.preheader
leaq 16(%rsp), %r12
xorl %ebp, %ebp
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_3: # %.loopexit
# in Loop: Header=BB1_4 Depth=1
movl $.L.str.4, %esi
movq %r14, %rdi
leaq 20(%rsp), %rdx
leaq 12(%rsp), %rcx
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
je .LBB1_7
.LBB1_4: # %.lr.ph18
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
addl 12(%rsp), %ebp
movl $.L.str.3, %esi
movq %r15, %rdi
movl %ebp, %edx
xorl %eax, %eax
callq fprintf
cmpl $0, 12(%rsp)
jle .LBB1_3
# %bb.5: # %.lr.ph.preheader
# in Loop: Header=BB1_4 Depth=1
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# Parent Loop BB1_4 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.5, %esi
movq %r14, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl 16(%rsp), %edx
movl $.L.str.3, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
incl %r13d
cmpl 12(%rsp), %r13d
jl .LBB1_6
jmp .LBB1_3
.LBB1_7: # %._crit_edge.loopexit
incl %ebp
jmp .LBB1_8
.LBB1_1:
movl $1, %ebp
.LBB1_8: # %._crit_edge
movq %r15, %rdi
callq fclose
movq %rbx, %rdi
callq fclose
movl %ebp, e_num(%rip)
movl 20(%rsp), %esi
incl %esi
movl %esi, v_num(%rip)
movl $.L.str.6, %edi
movl %ebp, %edx
xorl %eax, %eax
callq printf
movl $file_v_e, %edi
movl $.L.str, %esi
callq fopen
movq %rax, %rbx
movl v_num(%rip), %edx
movl e_num(%rip), %ecx
movl $.L.str.7, %esi
movq %rax, %rdi
xorl %eax, %eax
callq fprintf
movq %rbx, %rdi
callq fclose
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9csr_beginPc, .Lfunc_end1-_Z9csr_beginPc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z9csr_beginPc
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.type filein,@object # @filein
.data
.globl filein
.p2align 4, 0x0
filein:
.asciz "/home/yuede/dataset/kron_10_4.dat"
.size filein, 34
.type fileout,@object # @fileout
.globl fileout
.p2align 4, 0x0
fileout:
.asciz "/home/yuede/dataset/kron_10_4.cpu.as.result"
.size fileout, 44
.type file_beg_pos,@object # @file_beg_pos
.globl file_beg_pos
.p2align 4, 0x0
file_beg_pos:
.asciz "/home/yuede/dataset/kron_10_4.beg.pos"
.size file_beg_pos, 38
.type file_csr,@object # @file_csr
.globl file_csr
.p2align 4, 0x0
file_csr:
.asciz "/home/yuede/dataset/kron_10_4.csr"
.size file_csr, 34
.type file_v_e,@object # @file_v_e
.globl file_v_e
.p2align 4, 0x0
file_v_e:
.asciz "/home/yuede/dataset/kron_10_4.v_e"
.size file_v_e, 34
.type v_num,@object # @v_num
.bss
.globl v_num
.p2align 2, 0x0
v_num:
.long 0 # 0x0
.size v_num, 4
.type e_num,@object # @e_num
.globl e_num
.p2align 2, 0x0
e_num:
.long 0 # 0x0
.size e_num, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "w"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "a"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d\n"
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d%d"
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "v_num = %d, e_num = %d\n"
.size .L.str.6, 24
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d %d\n"
.size .L.str.7, 7
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym filein
.addrsig_sym file_beg_pos
.addrsig_sym file_csr
.addrsig_sym file_v_e
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void _InitI(int *res,int val,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if (x < rows && y < columns){
int pos = x*columns + y;
res[pos] = val;
}
}
__global__ void _AddI(int *res,int *arr,int arrRows,int arrColumns,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if (x < rows && y < columns){
int pos = x*columns + y;
int _x = x % arrRows;
int _y = y % arrColumns;
int _pos = _x * arrColumns + _y;
res[pos] += arr[_pos];
}
}
__global__ void _LAddI(int *res,int *arr,int lamda,int arrRows,int arrColumns,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if (x < rows && y < columns){
int pos = x*columns + y;
int _x = x % arrRows;
int _y = y % arrColumns;
int _pos = _x * arrColumns + _y;
res[pos] += lamda*arr[_pos];
}
}
__global__ void _MulI(int *res,int *a,int *b,int cDim,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if (x < rows && y < columns){
int sum = 0;
for (int i=0; i<cDim; i++){
sum += a[x*cDim + i] * b[i*cDim + y];
}
res[x*columns + y] = sum;
}
}
__global__ void _InitD(double *res,double val,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x*columns + y;
res[pos] = val;
}
}
__global__ void _AddD(double *res,double *arr,int arrRows,int arrColumns,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x*columns + y;
int _x = x % arrRows;
int _y = y % arrColumns;
int _pos = _x * arrColumns + _y;
res[pos] += arr[_pos];
}
}
__global__ void _2AddD(double *res,double *a,double *b,int bRows,int bColumns,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x*columns + y;
int _x = x % bRows;
int _y = y % bColumns;
int _pos = _x * bColumns + _y;
res[pos] = a[pos] + b[_pos];
}
}
__global__ void _LAddD(double *res,double *arr,double lamda,int arrRows,int arrColumns,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x*columns + y;
int _x = x % arrRows;
int _y = y % arrColumns;
int _pos = _x * arrColumns + _y;
res[pos] += lamda*arr[_pos];
}
}
__global__ void _MulD(double *res,double *a,double *b,int cDim,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
double sum = 0.0;
for (int i=0; i<cDim; i++){
sum += a[x*cDim + i] * b[i*columns + y];
}
res[x*columns + y] = sum;
}
}
__global__ void _SMulD(double *res,double val,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x * columns + y;
res[pos] = res[pos]*val;
}
}
__global__ void _2SMulD(double *res,double *a,double val,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x * columns + y;
res[pos] = a[pos]*val;
}
}
__global__ void _DivD(double *res,double val,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x * columns + y;
res[pos] = res[pos]/val;
}
}
__global__ void _TransposeD(double *res,double *a,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos1 = x * columns + y;
int pos2 = y * rows + x;
res[pos1] = a[pos2];
}
}
__global__ void _GetDiagonalD(double *res,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
if (x != y){
res[x*columns + y] = 0.0;
}
}
}
__global__ void _DotD(double *res,double *a,double *b,int bRows,int bColumns,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x * columns + y;
int _x = x % bRows;
int _y = y % bColumns;
int _pos = _x * bColumns + _y;
res[pos] = a[pos] * b[_pos];
}
}
__global__ void _ColAddD(double *res,int col,double val,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x*columns + y;
if (y == col){
res[pos] += val;
}
}
} | .file "tmpxft_000145b8_00000000-6_GpuArrayKernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z6_InitIPiiiiPiiii
.type _Z28__device_stub__Z6_InitIPiiiiPiiii, @function
_Z28__device_stub__Z6_InitIPiiiiPiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6_InitIPiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z6_InitIPiiiiPiiii, .-_Z28__device_stub__Z6_InitIPiiiiPiiii
.globl _Z6_InitIPiiii
.type _Z6_InitIPiiii, @function
_Z6_InitIPiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6_InitIPiiiiPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6_InitIPiiii, .-_Z6_InitIPiiii
.globl _Z30__device_stub__Z5_AddIPiS_iiiiPiS_iiii
.type _Z30__device_stub__Z5_AddIPiS_iiiiPiS_iiii, @function
_Z30__device_stub__Z5_AddIPiS_iiiiPiS_iiii:
.LFB2053:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5_AddIPiS_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z30__device_stub__Z5_AddIPiS_iiiiPiS_iiii, .-_Z30__device_stub__Z5_AddIPiS_iiiiPiS_iiii
.globl _Z5_AddIPiS_iiii
.type _Z5_AddIPiS_iiii, @function
_Z5_AddIPiS_iiii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z5_AddIPiS_iiiiPiS_iiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z5_AddIPiS_iiii, .-_Z5_AddIPiS_iiii
.globl _Z32__device_stub__Z6_LAddIPiS_iiiiiPiS_iiiii
.type _Z32__device_stub__Z6_LAddIPiS_iiiiiPiS_iiiii, @function
_Z32__device_stub__Z6_LAddIPiS_iiiiiPiS_iiiii:
.LFB2055:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6_LAddIPiS_iiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z32__device_stub__Z6_LAddIPiS_iiiiiPiS_iiiii, .-_Z32__device_stub__Z6_LAddIPiS_iiiiiPiS_iiiii
.globl _Z6_LAddIPiS_iiiii
.type _Z6_LAddIPiS_iiiii, @function
_Z6_LAddIPiS_iiiii:
.LFB2056:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z32__device_stub__Z6_LAddIPiS_iiiiiPiS_iiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z6_LAddIPiS_iiiii, .-_Z6_LAddIPiS_iiiii
.globl _Z31__device_stub__Z5_MulIPiS_S_iiiPiS_S_iii
.type _Z31__device_stub__Z5_MulIPiS_S_iiiPiS_S_iii, @function
_Z31__device_stub__Z5_MulIPiS_S_iiiPiS_S_iii:
.LFB2057:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z5_MulIPiS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z31__device_stub__Z5_MulIPiS_S_iiiPiS_S_iii, .-_Z31__device_stub__Z5_MulIPiS_S_iiiPiS_S_iii
.globl _Z5_MulIPiS_S_iii
.type _Z5_MulIPiS_S_iii, @function
_Z5_MulIPiS_S_iii:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z5_MulIPiS_S_iiiPiS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z5_MulIPiS_S_iii, .-_Z5_MulIPiS_S_iii
.globl _Z28__device_stub__Z6_InitDPddiiPddii
.type _Z28__device_stub__Z6_InitDPddiiPddii, @function
_Z28__device_stub__Z6_InitDPddiiPddii:
.LFB2059:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movsd %xmm0, 16(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6_InitDPddii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z28__device_stub__Z6_InitDPddiiPddii, .-_Z28__device_stub__Z6_InitDPddiiPddii
.globl _Z6_InitDPddii
.type _Z6_InitDPddii, @function
_Z6_InitDPddii:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6_InitDPddiiPddii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z6_InitDPddii, .-_Z6_InitDPddii
.globl _Z30__device_stub__Z5_AddDPdS_iiiiPdS_iiii
.type _Z30__device_stub__Z5_AddDPdS_iiiiPdS_iiii, @function
_Z30__device_stub__Z5_AddDPdS_iiiiPdS_iiii:
.LFB2061:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5_AddDPdS_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z30__device_stub__Z5_AddDPdS_iiiiPdS_iiii, .-_Z30__device_stub__Z5_AddDPdS_iiiiPdS_iiii
.globl _Z5_AddDPdS_iiii
.type _Z5_AddDPdS_iiii, @function
_Z5_AddDPdS_iiii:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z5_AddDPdS_iiiiPdS_iiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z5_AddDPdS_iiii, .-_Z5_AddDPdS_iiii
.globl _Z33__device_stub__Z6_2AddDPdS_S_iiiiPdS_S_iiii
.type _Z33__device_stub__Z6_2AddDPdS_S_iiiiPdS_S_iiii, @function
_Z33__device_stub__Z6_2AddDPdS_S_iiiiPdS_S_iiii:
.LFB2063:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L55
.L51:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L56
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6_2AddDPdS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L51
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z33__device_stub__Z6_2AddDPdS_S_iiiiPdS_S_iiii, .-_Z33__device_stub__Z6_2AddDPdS_S_iiiiPdS_S_iiii
.globl _Z6_2AddDPdS_S_iiii
.type _Z6_2AddDPdS_S_iiii, @function
_Z6_2AddDPdS_S_iiii:
.LFB2064:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z33__device_stub__Z6_2AddDPdS_S_iiiiPdS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _Z6_2AddDPdS_S_iiii, .-_Z6_2AddDPdS_S_iiii
.globl _Z32__device_stub__Z6_LAddDPdS_diiiiPdS_diiii
.type _Z32__device_stub__Z6_LAddDPdS_diiiiPdS_diiii, @function
_Z32__device_stub__Z6_LAddDPdS_diiiiPdS_diiii:
.LFB2065:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movsd %xmm0, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L63
.L59:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L64
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6_LAddDPdS_diiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L59
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2065:
.size _Z32__device_stub__Z6_LAddDPdS_diiiiPdS_diiii, .-_Z32__device_stub__Z6_LAddDPdS_diiiiPdS_diiii
.globl _Z6_LAddDPdS_diiii
.type _Z6_LAddDPdS_diiii, @function
_Z6_LAddDPdS_diiii:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6_LAddDPdS_diiiiPdS_diiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _Z6_LAddDPdS_diiii, .-_Z6_LAddDPdS_diiii
.globl _Z31__device_stub__Z5_MulDPdS_S_iiiPdS_S_iii
.type _Z31__device_stub__Z5_MulDPdS_S_iiiPdS_S_iii, @function
_Z31__device_stub__Z5_MulDPdS_S_iiiPdS_S_iii:
.LFB2067:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L71
.L67:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L72
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L71:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z5_MulDPdS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L67
.L72:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2067:
.size _Z31__device_stub__Z5_MulDPdS_S_iiiPdS_S_iii, .-_Z31__device_stub__Z5_MulDPdS_S_iiiPdS_S_iii
.globl _Z5_MulDPdS_S_iii
.type _Z5_MulDPdS_S_iii, @function
_Z5_MulDPdS_S_iii:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z5_MulDPdS_S_iiiPdS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _Z5_MulDPdS_S_iii, .-_Z5_MulDPdS_S_iii
.globl _Z28__device_stub__Z6_SMulDPddiiPddii
.type _Z28__device_stub__Z6_SMulDPddiiPddii, @function
_Z28__device_stub__Z6_SMulDPddiiPddii:
.LFB2069:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movsd %xmm0, 16(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L79
.L75:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L80
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L79:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6_SMulDPddii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L75
.L80:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2069:
.size _Z28__device_stub__Z6_SMulDPddiiPddii, .-_Z28__device_stub__Z6_SMulDPddiiPddii
.globl _Z6_SMulDPddii
.type _Z6_SMulDPddii, @function
_Z6_SMulDPddii:
.LFB2070:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6_SMulDPddiiPddii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2070:
.size _Z6_SMulDPddii, .-_Z6_SMulDPddii
.globl _Z31__device_stub__Z7_2SMulDPdS_diiPdS_dii
.type _Z31__device_stub__Z7_2SMulDPdS_diiPdS_dii, @function
_Z31__device_stub__Z7_2SMulDPdS_diiPdS_dii:
.LFB2071:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movsd %xmm0, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L87
.L83:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L88
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L87:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7_2SMulDPdS_dii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L83
.L88:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size _Z31__device_stub__Z7_2SMulDPdS_diiPdS_dii, .-_Z31__device_stub__Z7_2SMulDPdS_diiPdS_dii
.globl _Z7_2SMulDPdS_dii
.type _Z7_2SMulDPdS_dii, @function
_Z7_2SMulDPdS_dii:
.LFB2072:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7_2SMulDPdS_diiPdS_dii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2072:
.size _Z7_2SMulDPdS_dii, .-_Z7_2SMulDPdS_dii
.globl _Z27__device_stub__Z5_DivDPddiiPddii
.type _Z27__device_stub__Z5_DivDPddiiPddii, @function
_Z27__device_stub__Z5_DivDPddiiPddii:
.LFB2073:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movsd %xmm0, 16(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L95
.L91:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L96
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L95:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5_DivDPddii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L91
.L96:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2073:
.size _Z27__device_stub__Z5_DivDPddiiPddii, .-_Z27__device_stub__Z5_DivDPddiiPddii
.globl _Z5_DivDPddii
.type _Z5_DivDPddii, @function
_Z5_DivDPddii:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5_DivDPddiiPddii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _Z5_DivDPddii, .-_Z5_DivDPddii
.globl _Z35__device_stub__Z11_TransposeDPdS_iiPdS_ii
.type _Z35__device_stub__Z11_TransposeDPdS_iiPdS_ii, @function
_Z35__device_stub__Z11_TransposeDPdS_iiPdS_ii:
.LFB2075:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L103
.L99:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L104
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L103:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11_TransposeDPdS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L99
.L104:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2075:
.size _Z35__device_stub__Z11_TransposeDPdS_iiPdS_ii, .-_Z35__device_stub__Z11_TransposeDPdS_iiPdS_ii
.globl _Z11_TransposeDPdS_ii
.type _Z11_TransposeDPdS_ii, @function
_Z11_TransposeDPdS_ii:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11_TransposeDPdS_iiPdS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size _Z11_TransposeDPdS_ii, .-_Z11_TransposeDPdS_ii
.globl _Z35__device_stub__Z13_GetDiagonalDPdiiPdii
.type _Z35__device_stub__Z13_GetDiagonalDPdiiPdii, @function
_Z35__device_stub__Z13_GetDiagonalDPdiiPdii:
.LFB2077:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L111
.L107:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L112
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L111:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13_GetDiagonalDPdii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L107
.L112:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2077:
.size _Z35__device_stub__Z13_GetDiagonalDPdiiPdii, .-_Z35__device_stub__Z13_GetDiagonalDPdiiPdii
.globl _Z13_GetDiagonalDPdii
.type _Z13_GetDiagonalDPdii, @function
_Z13_GetDiagonalDPdii:
.LFB2078:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13_GetDiagonalDPdiiPdii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2078:
.size _Z13_GetDiagonalDPdii, .-_Z13_GetDiagonalDPdii
.globl _Z32__device_stub__Z5_DotDPdS_S_iiiiPdS_S_iiii
.type _Z32__device_stub__Z5_DotDPdS_S_iiiiPdS_S_iiii, @function
_Z32__device_stub__Z5_DotDPdS_S_iiiiPdS_S_iiii:
.LFB2079:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L119
.L115:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L120
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L119:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z5_DotDPdS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L115
.L120:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2079:
.size _Z32__device_stub__Z5_DotDPdS_S_iiiiPdS_S_iiii, .-_Z32__device_stub__Z5_DotDPdS_S_iiiiPdS_S_iiii
.globl _Z5_DotDPdS_S_iiii
.type _Z5_DotDPdS_S_iiii, @function
_Z5_DotDPdS_S_iiii:
.LFB2080:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z32__device_stub__Z5_DotDPdS_S_iiiiPdS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2080:
.size _Z5_DotDPdS_S_iiii, .-_Z5_DotDPdS_S_iiii
.globl _Z31__device_stub__Z8_ColAddDPdidiiPdidii
.type _Z31__device_stub__Z8_ColAddDPdidiiPdidii, @function
_Z31__device_stub__Z8_ColAddDPdidiiPdidii:
.LFB2081:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movsd %xmm0, 8(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L127
.L123:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L128
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L127:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8_ColAddDPdidii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L123
.L128:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z31__device_stub__Z8_ColAddDPdidiiPdidii, .-_Z31__device_stub__Z8_ColAddDPdidiiPdidii
.globl _Z8_ColAddDPdidii
.type _Z8_ColAddDPdidii, @function
_Z8_ColAddDPdidii:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8_ColAddDPdidiiPdidii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z8_ColAddDPdidii, .-_Z8_ColAddDPdidii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8_ColAddDPdidii"
.LC1:
.string "_Z5_DotDPdS_S_iiii"
.LC2:
.string "_Z13_GetDiagonalDPdii"
.LC3:
.string "_Z11_TransposeDPdS_ii"
.LC4:
.string "_Z5_DivDPddii"
.LC5:
.string "_Z7_2SMulDPdS_dii"
.LC6:
.string "_Z6_SMulDPddii"
.LC7:
.string "_Z5_MulDPdS_S_iii"
.LC8:
.string "_Z6_LAddDPdS_diiii"
.LC9:
.string "_Z6_2AddDPdS_S_iiii"
.LC10:
.string "_Z5_AddDPdS_iiii"
.LC11:
.string "_Z6_InitDPddii"
.LC12:
.string "_Z5_MulIPiS_S_iii"
.LC13:
.string "_Z6_LAddIPiS_iiiii"
.LC14:
.string "_Z5_AddIPiS_iiii"
.LC15:
.string "_Z6_InitIPiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8_ColAddDPdidii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z5_DotDPdS_S_iiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13_GetDiagonalDPdii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z11_TransposeDPdS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z5_DivDPddii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z7_2SMulDPdS_dii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z6_SMulDPddii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z5_MulDPdS_S_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z6_LAddDPdS_diiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z6_2AddDPdS_S_iiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z5_AddDPdS_iiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z6_InitDPddii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z5_MulIPiS_S_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z6_LAddIPiS_iiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z5_AddIPiS_iiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z6_InitIPiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void _InitI(int *res,int val,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if (x < rows && y < columns){
int pos = x*columns + y;
res[pos] = val;
}
}
__global__ void _AddI(int *res,int *arr,int arrRows,int arrColumns,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if (x < rows && y < columns){
int pos = x*columns + y;
int _x = x % arrRows;
int _y = y % arrColumns;
int _pos = _x * arrColumns + _y;
res[pos] += arr[_pos];
}
}
__global__ void _LAddI(int *res,int *arr,int lamda,int arrRows,int arrColumns,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if (x < rows && y < columns){
int pos = x*columns + y;
int _x = x % arrRows;
int _y = y % arrColumns;
int _pos = _x * arrColumns + _y;
res[pos] += lamda*arr[_pos];
}
}
__global__ void _MulI(int *res,int *a,int *b,int cDim,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if (x < rows && y < columns){
int sum = 0;
for (int i=0; i<cDim; i++){
sum += a[x*cDim + i] * b[i*cDim + y];
}
res[x*columns + y] = sum;
}
}
__global__ void _InitD(double *res,double val,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x*columns + y;
res[pos] = val;
}
}
__global__ void _AddD(double *res,double *arr,int arrRows,int arrColumns,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x*columns + y;
int _x = x % arrRows;
int _y = y % arrColumns;
int _pos = _x * arrColumns + _y;
res[pos] += arr[_pos];
}
}
__global__ void _2AddD(double *res,double *a,double *b,int bRows,int bColumns,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x*columns + y;
int _x = x % bRows;
int _y = y % bColumns;
int _pos = _x * bColumns + _y;
res[pos] = a[pos] + b[_pos];
}
}
__global__ void _LAddD(double *res,double *arr,double lamda,int arrRows,int arrColumns,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x*columns + y;
int _x = x % arrRows;
int _y = y % arrColumns;
int _pos = _x * arrColumns + _y;
res[pos] += lamda*arr[_pos];
}
}
__global__ void _MulD(double *res,double *a,double *b,int cDim,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
double sum = 0.0;
for (int i=0; i<cDim; i++){
sum += a[x*cDim + i] * b[i*columns + y];
}
res[x*columns + y] = sum;
}
}
__global__ void _SMulD(double *res,double val,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x * columns + y;
res[pos] = res[pos]*val;
}
}
__global__ void _2SMulD(double *res,double *a,double val,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x * columns + y;
res[pos] = a[pos]*val;
}
}
__global__ void _DivD(double *res,double val,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x * columns + y;
res[pos] = res[pos]/val;
}
}
__global__ void _TransposeD(double *res,double *a,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos1 = x * columns + y;
int pos2 = y * rows + x;
res[pos1] = a[pos2];
}
}
__global__ void _GetDiagonalD(double *res,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
if (x != y){
res[x*columns + y] = 0.0;
}
}
}
__global__ void _DotD(double *res,double *a,double *b,int bRows,int bColumns,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x * columns + y;
int _x = x % bRows;
int _y = y % bColumns;
int _pos = _x * bColumns + _y;
res[pos] = a[pos] * b[_pos];
}
}
__global__ void _ColAddD(double *res,int col,double val,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x*columns + y;
if (y == col){
res[pos] += val;
}
}
} | #include <hip/hip_runtime.h>
__global__ void _InitI(int *res,int val,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if (x < rows && y < columns){
int pos = x*columns + y;
res[pos] = val;
}
}
__global__ void _AddI(int *res,int *arr,int arrRows,int arrColumns,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if (x < rows && y < columns){
int pos = x*columns + y;
int _x = x % arrRows;
int _y = y % arrColumns;
int _pos = _x * arrColumns + _y;
res[pos] += arr[_pos];
}
}
__global__ void _LAddI(int *res,int *arr,int lamda,int arrRows,int arrColumns,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if (x < rows && y < columns){
int pos = x*columns + y;
int _x = x % arrRows;
int _y = y % arrColumns;
int _pos = _x * arrColumns + _y;
res[pos] += lamda*arr[_pos];
}
}
__global__ void _MulI(int *res,int *a,int *b,int cDim,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if (x < rows && y < columns){
int sum = 0;
for (int i=0; i<cDim; i++){
sum += a[x*cDim + i] * b[i*cDim + y];
}
res[x*columns + y] = sum;
}
}
__global__ void _InitD(double *res,double val,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x*columns + y;
res[pos] = val;
}
}
__global__ void _AddD(double *res,double *arr,int arrRows,int arrColumns,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x*columns + y;
int _x = x % arrRows;
int _y = y % arrColumns;
int _pos = _x * arrColumns + _y;
res[pos] += arr[_pos];
}
}
__global__ void _2AddD(double *res,double *a,double *b,int bRows,int bColumns,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x*columns + y;
int _x = x % bRows;
int _y = y % bColumns;
int _pos = _x * bColumns + _y;
res[pos] = a[pos] + b[_pos];
}
}
__global__ void _LAddD(double *res,double *arr,double lamda,int arrRows,int arrColumns,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x*columns + y;
int _x = x % arrRows;
int _y = y % arrColumns;
int _pos = _x * arrColumns + _y;
res[pos] += lamda*arr[_pos];
}
}
__global__ void _MulD(double *res,double *a,double *b,int cDim,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
double sum = 0.0;
for (int i=0; i<cDim; i++){
sum += a[x*cDim + i] * b[i*columns + y];
}
res[x*columns + y] = sum;
}
}
__global__ void _SMulD(double *res,double val,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x * columns + y;
res[pos] = res[pos]*val;
}
}
__global__ void _2SMulD(double *res,double *a,double val,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x * columns + y;
res[pos] = a[pos]*val;
}
}
__global__ void _DivD(double *res,double val,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x * columns + y;
res[pos] = res[pos]/val;
}
}
__global__ void _TransposeD(double *res,double *a,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos1 = x * columns + y;
int pos2 = y * rows + x;
res[pos1] = a[pos2];
}
}
__global__ void _GetDiagonalD(double *res,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
if (x != y){
res[x*columns + y] = 0.0;
}
}
}
__global__ void _DotD(double *res,double *a,double *b,int bRows,int bColumns,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x * columns + y;
int _x = x % bRows;
int _y = y % bColumns;
int _pos = _x * bColumns + _y;
res[pos] = a[pos] * b[_pos];
}
}
__global__ void _ColAddD(double *res,int col,double val,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x*columns + y;
if (y == col){
res[pos] += val;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void _InitI(int *res,int val,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if (x < rows && y < columns){
int pos = x*columns + y;
res[pos] = val;
}
}
__global__ void _AddI(int *res,int *arr,int arrRows,int arrColumns,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if (x < rows && y < columns){
int pos = x*columns + y;
int _x = x % arrRows;
int _y = y % arrColumns;
int _pos = _x * arrColumns + _y;
res[pos] += arr[_pos];
}
}
__global__ void _LAddI(int *res,int *arr,int lamda,int arrRows,int arrColumns,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if (x < rows && y < columns){
int pos = x*columns + y;
int _x = x % arrRows;
int _y = y % arrColumns;
int _pos = _x * arrColumns + _y;
res[pos] += lamda*arr[_pos];
}
}
__global__ void _MulI(int *res,int *a,int *b,int cDim,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if (x < rows && y < columns){
int sum = 0;
for (int i=0; i<cDim; i++){
sum += a[x*cDim + i] * b[i*cDim + y];
}
res[x*columns + y] = sum;
}
}
__global__ void _InitD(double *res,double val,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x*columns + y;
res[pos] = val;
}
}
__global__ void _AddD(double *res,double *arr,int arrRows,int arrColumns,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x*columns + y;
int _x = x % arrRows;
int _y = y % arrColumns;
int _pos = _x * arrColumns + _y;
res[pos] += arr[_pos];
}
}
__global__ void _2AddD(double *res,double *a,double *b,int bRows,int bColumns,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x*columns + y;
int _x = x % bRows;
int _y = y % bColumns;
int _pos = _x * bColumns + _y;
res[pos] = a[pos] + b[_pos];
}
}
__global__ void _LAddD(double *res,double *arr,double lamda,int arrRows,int arrColumns,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x*columns + y;
int _x = x % arrRows;
int _y = y % arrColumns;
int _pos = _x * arrColumns + _y;
res[pos] += lamda*arr[_pos];
}
}
__global__ void _MulD(double *res,double *a,double *b,int cDim,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
double sum = 0.0;
for (int i=0; i<cDim; i++){
sum += a[x*cDim + i] * b[i*columns + y];
}
res[x*columns + y] = sum;
}
}
__global__ void _SMulD(double *res,double val,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x * columns + y;
res[pos] = res[pos]*val;
}
}
__global__ void _2SMulD(double *res,double *a,double val,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x * columns + y;
res[pos] = a[pos]*val;
}
}
__global__ void _DivD(double *res,double val,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x * columns + y;
res[pos] = res[pos]/val;
}
}
__global__ void _TransposeD(double *res,double *a,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos1 = x * columns + y;
int pos2 = y * rows + x;
res[pos1] = a[pos2];
}
}
__global__ void _GetDiagonalD(double *res,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
if (x != y){
res[x*columns + y] = 0.0;
}
}
}
__global__ void _DotD(double *res,double *a,double *b,int bRows,int bColumns,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x * columns + y;
int _x = x % bRows;
int _y = y % bColumns;
int _pos = _x * bColumns + _y;
res[pos] = a[pos] * b[_pos];
}
}
__global__ void _ColAddD(double *res,int col,double val,int rows,int columns){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//
if (x < rows && y < columns){
int pos = x*columns + y;
if (y == col){
res[pos] += val;
}
}
} | .text
.file "GpuArrayKernels.hip"
.globl _Z21__device_stub___InitIPiiii # -- Begin function _Z21__device_stub___InitIPiiii
.p2align 4, 0x90
.type _Z21__device_stub___InitIPiiii,@function
_Z21__device_stub___InitIPiiii: # @_Z21__device_stub___InitIPiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6_InitIPiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub___InitIPiiii, .Lfunc_end0-_Z21__device_stub___InitIPiiii
.cfi_endproc
# -- End function
.globl _Z20__device_stub___AddIPiS_iiii # -- Begin function _Z20__device_stub___AddIPiS_iiii
.p2align 4, 0x90
.type _Z20__device_stub___AddIPiS_iiii,@function
_Z20__device_stub___AddIPiS_iiii: # @_Z20__device_stub___AddIPiS_iiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5_AddIPiS_iiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z20__device_stub___AddIPiS_iiii, .Lfunc_end1-_Z20__device_stub___AddIPiS_iiii
.cfi_endproc
# -- End function
.globl _Z21__device_stub___LAddIPiS_iiiii # -- Begin function _Z21__device_stub___LAddIPiS_iiiii
.p2align 4, 0x90
.type _Z21__device_stub___LAddIPiS_iiiii,@function
_Z21__device_stub___LAddIPiS_iiiii: # @_Z21__device_stub___LAddIPiS_iiiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6_LAddIPiS_iiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end2:
.size _Z21__device_stub___LAddIPiS_iiiii, .Lfunc_end2-_Z21__device_stub___LAddIPiS_iiiii
.cfi_endproc
# -- End function
.globl _Z20__device_stub___MulIPiS_S_iii # -- Begin function _Z20__device_stub___MulIPiS_S_iii
.p2align 4, 0x90
.type _Z20__device_stub___MulIPiS_S_iii,@function
_Z20__device_stub___MulIPiS_S_iii: # @_Z20__device_stub___MulIPiS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5_MulIPiS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size _Z20__device_stub___MulIPiS_S_iii, .Lfunc_end3-_Z20__device_stub___MulIPiS_S_iii
.cfi_endproc
# -- End function
.globl _Z21__device_stub___InitDPddii # -- Begin function _Z21__device_stub___InitDPddii
.p2align 4, 0x90
.type _Z21__device_stub___InitDPddii,@function
_Z21__device_stub___InitDPddii: # @_Z21__device_stub___InitDPddii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movsd %xmm0, 64(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6_InitDPddii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z21__device_stub___InitDPddii, .Lfunc_end4-_Z21__device_stub___InitDPddii
.cfi_endproc
# -- End function
.globl _Z20__device_stub___AddDPdS_iiii # -- Begin function _Z20__device_stub___AddDPdS_iiii
.p2align 4, 0x90
.type _Z20__device_stub___AddDPdS_iiii,@function
_Z20__device_stub___AddDPdS_iiii: # @_Z20__device_stub___AddDPdS_iiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5_AddDPdS_iiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end5:
.size _Z20__device_stub___AddDPdS_iiii, .Lfunc_end5-_Z20__device_stub___AddDPdS_iiii
.cfi_endproc
# -- End function
.globl _Z21__device_stub___2AddDPdS_S_iiii # -- Begin function _Z21__device_stub___2AddDPdS_S_iiii
.p2align 4, 0x90
.type _Z21__device_stub___2AddDPdS_S_iiii,@function
_Z21__device_stub___2AddDPdS_S_iiii: # @_Z21__device_stub___2AddDPdS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6_2AddDPdS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end6:
.size _Z21__device_stub___2AddDPdS_S_iiii, .Lfunc_end6-_Z21__device_stub___2AddDPdS_S_iiii
.cfi_endproc
# -- End function
.globl _Z21__device_stub___LAddDPdS_diiii # -- Begin function _Z21__device_stub___LAddDPdS_diiii
.p2align 4, 0x90
.type _Z21__device_stub___LAddDPdS_diiii,@function
_Z21__device_stub___LAddDPdS_diiii: # @_Z21__device_stub___LAddDPdS_diiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movsd %xmm0, 72(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6_LAddDPdS_diiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end7:
.size _Z21__device_stub___LAddDPdS_diiii, .Lfunc_end7-_Z21__device_stub___LAddDPdS_diiii
.cfi_endproc
# -- End function
.globl _Z20__device_stub___MulDPdS_S_iii # -- Begin function _Z20__device_stub___MulDPdS_S_iii
.p2align 4, 0x90
.type _Z20__device_stub___MulDPdS_S_iii,@function
_Z20__device_stub___MulDPdS_S_iii: # @_Z20__device_stub___MulDPdS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5_MulDPdS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end8:
.size _Z20__device_stub___MulDPdS_S_iii, .Lfunc_end8-_Z20__device_stub___MulDPdS_S_iii
.cfi_endproc
# -- End function
.globl _Z21__device_stub___SMulDPddii # -- Begin function _Z21__device_stub___SMulDPddii
.p2align 4, 0x90
.type _Z21__device_stub___SMulDPddii,@function
_Z21__device_stub___SMulDPddii: # @_Z21__device_stub___SMulDPddii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movsd %xmm0, 64(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6_SMulDPddii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end9:
.size _Z21__device_stub___SMulDPddii, .Lfunc_end9-_Z21__device_stub___SMulDPddii
.cfi_endproc
# -- End function
.globl _Z22__device_stub___2SMulDPdS_dii # -- Begin function _Z22__device_stub___2SMulDPdS_dii
.p2align 4, 0x90
.type _Z22__device_stub___2SMulDPdS_dii,@function
_Z22__device_stub___2SMulDPdS_dii: # @_Z22__device_stub___2SMulDPdS_dii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movsd %xmm0, 56(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7_2SMulDPdS_dii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end10:
.size _Z22__device_stub___2SMulDPdS_dii, .Lfunc_end10-_Z22__device_stub___2SMulDPdS_dii
.cfi_endproc
# -- End function
.globl _Z20__device_stub___DivDPddii # -- Begin function _Z20__device_stub___DivDPddii
.p2align 4, 0x90
.type _Z20__device_stub___DivDPddii,@function
_Z20__device_stub___DivDPddii: # @_Z20__device_stub___DivDPddii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movsd %xmm0, 64(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5_DivDPddii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end11:
.size _Z20__device_stub___DivDPddii, .Lfunc_end11-_Z20__device_stub___DivDPddii
.cfi_endproc
# -- End function
.globl _Z26__device_stub___TransposeDPdS_ii # -- Begin function _Z26__device_stub___TransposeDPdS_ii
.p2align 4, 0x90
.type _Z26__device_stub___TransposeDPdS_ii,@function
_Z26__device_stub___TransposeDPdS_ii: # @_Z26__device_stub___TransposeDPdS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11_TransposeDPdS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end12:
.size _Z26__device_stub___TransposeDPdS_ii, .Lfunc_end12-_Z26__device_stub___TransposeDPdS_ii
.cfi_endproc
# -- End function
.globl _Z28__device_stub___GetDiagonalDPdii # -- Begin function _Z28__device_stub___GetDiagonalDPdii
.p2align 4, 0x90
.type _Z28__device_stub___GetDiagonalDPdii,@function
_Z28__device_stub___GetDiagonalDPdii: # @_Z28__device_stub___GetDiagonalDPdii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13_GetDiagonalDPdii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end13:
.size _Z28__device_stub___GetDiagonalDPdii, .Lfunc_end13-_Z28__device_stub___GetDiagonalDPdii
.cfi_endproc
# -- End function
.globl _Z20__device_stub___DotDPdS_S_iiii # -- Begin function _Z20__device_stub___DotDPdS_S_iiii
.p2align 4, 0x90
.type _Z20__device_stub___DotDPdS_S_iiii,@function
_Z20__device_stub___DotDPdS_S_iiii: # @_Z20__device_stub___DotDPdS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5_DotDPdS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end14:
.size _Z20__device_stub___DotDPdS_S_iiii, .Lfunc_end14-_Z20__device_stub___DotDPdS_S_iiii
.cfi_endproc
# -- End function
.globl _Z23__device_stub___ColAddDPdidii # -- Begin function _Z23__device_stub___ColAddDPdidii
.p2align 4, 0x90
.type _Z23__device_stub___ColAddDPdidii,@function
_Z23__device_stub___ColAddDPdidii: # @_Z23__device_stub___ColAddDPdidii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movsd %xmm0, 64(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8_ColAddDPdidii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end15:
.size _Z23__device_stub___ColAddDPdidii, .Lfunc_end15-_Z23__device_stub___ColAddDPdidii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB16_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB16_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6_InitIPiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5_AddIPiS_iiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6_LAddIPiS_iiiii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5_MulIPiS_S_iii, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6_InitDPddii, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5_AddDPdS_iiii, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6_2AddDPdS_S_iiii, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6_LAddDPdS_diiii, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5_MulDPdS_S_iii, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6_SMulDPddii, %esi
movl $.L__unnamed_10, %edx
movl $.L__unnamed_10, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7_2SMulDPdS_dii, %esi
movl $.L__unnamed_11, %edx
movl $.L__unnamed_11, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5_DivDPddii, %esi
movl $.L__unnamed_12, %edx
movl $.L__unnamed_12, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11_TransposeDPdS_ii, %esi
movl $.L__unnamed_13, %edx
movl $.L__unnamed_13, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13_GetDiagonalDPdii, %esi
movl $.L__unnamed_14, %edx
movl $.L__unnamed_14, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5_DotDPdS_S_iiii, %esi
movl $.L__unnamed_15, %edx
movl $.L__unnamed_15, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8_ColAddDPdidii, %esi
movl $.L__unnamed_16, %edx
movl $.L__unnamed_16, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end16:
.size __hip_module_ctor, .Lfunc_end16-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB17_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB17_2:
retq
.Lfunc_end17:
.size __hip_module_dtor, .Lfunc_end17-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6_InitIPiiii,@object # @_Z6_InitIPiiii
.section .rodata,"a",@progbits
.globl _Z6_InitIPiiii
.p2align 3, 0x0
_Z6_InitIPiiii:
.quad _Z21__device_stub___InitIPiiii
.size _Z6_InitIPiiii, 8
.type _Z5_AddIPiS_iiii,@object # @_Z5_AddIPiS_iiii
.globl _Z5_AddIPiS_iiii
.p2align 3, 0x0
_Z5_AddIPiS_iiii:
.quad _Z20__device_stub___AddIPiS_iiii
.size _Z5_AddIPiS_iiii, 8
.type _Z6_LAddIPiS_iiiii,@object # @_Z6_LAddIPiS_iiiii
.globl _Z6_LAddIPiS_iiiii
.p2align 3, 0x0
_Z6_LAddIPiS_iiiii:
.quad _Z21__device_stub___LAddIPiS_iiiii
.size _Z6_LAddIPiS_iiiii, 8
.type _Z5_MulIPiS_S_iii,@object # @_Z5_MulIPiS_S_iii
.globl _Z5_MulIPiS_S_iii
.p2align 3, 0x0
_Z5_MulIPiS_S_iii:
.quad _Z20__device_stub___MulIPiS_S_iii
.size _Z5_MulIPiS_S_iii, 8
.type _Z6_InitDPddii,@object # @_Z6_InitDPddii
.globl _Z6_InitDPddii
.p2align 3, 0x0
_Z6_InitDPddii:
.quad _Z21__device_stub___InitDPddii
.size _Z6_InitDPddii, 8
.type _Z5_AddDPdS_iiii,@object # @_Z5_AddDPdS_iiii
.globl _Z5_AddDPdS_iiii
.p2align 3, 0x0
_Z5_AddDPdS_iiii:
.quad _Z20__device_stub___AddDPdS_iiii
.size _Z5_AddDPdS_iiii, 8
.type _Z6_2AddDPdS_S_iiii,@object # @_Z6_2AddDPdS_S_iiii
.globl _Z6_2AddDPdS_S_iiii
.p2align 3, 0x0
_Z6_2AddDPdS_S_iiii:
.quad _Z21__device_stub___2AddDPdS_S_iiii
.size _Z6_2AddDPdS_S_iiii, 8
.type _Z6_LAddDPdS_diiii,@object # @_Z6_LAddDPdS_diiii
.globl _Z6_LAddDPdS_diiii
.p2align 3, 0x0
_Z6_LAddDPdS_diiii:
.quad _Z21__device_stub___LAddDPdS_diiii
.size _Z6_LAddDPdS_diiii, 8
.type _Z5_MulDPdS_S_iii,@object # @_Z5_MulDPdS_S_iii
.globl _Z5_MulDPdS_S_iii
.p2align 3, 0x0
_Z5_MulDPdS_S_iii:
.quad _Z20__device_stub___MulDPdS_S_iii
.size _Z5_MulDPdS_S_iii, 8
.type _Z6_SMulDPddii,@object # @_Z6_SMulDPddii
.globl _Z6_SMulDPddii
.p2align 3, 0x0
_Z6_SMulDPddii:
.quad _Z21__device_stub___SMulDPddii
.size _Z6_SMulDPddii, 8
.type _Z7_2SMulDPdS_dii,@object # @_Z7_2SMulDPdS_dii
.globl _Z7_2SMulDPdS_dii
.p2align 3, 0x0
_Z7_2SMulDPdS_dii:
.quad _Z22__device_stub___2SMulDPdS_dii
.size _Z7_2SMulDPdS_dii, 8
.type _Z5_DivDPddii,@object # @_Z5_DivDPddii
.globl _Z5_DivDPddii
.p2align 3, 0x0
_Z5_DivDPddii:
.quad _Z20__device_stub___DivDPddii
.size _Z5_DivDPddii, 8
.type _Z11_TransposeDPdS_ii,@object # @_Z11_TransposeDPdS_ii
.globl _Z11_TransposeDPdS_ii
.p2align 3, 0x0
_Z11_TransposeDPdS_ii:
.quad _Z26__device_stub___TransposeDPdS_ii
.size _Z11_TransposeDPdS_ii, 8
.type _Z13_GetDiagonalDPdii,@object # @_Z13_GetDiagonalDPdii
.globl _Z13_GetDiagonalDPdii
.p2align 3, 0x0
_Z13_GetDiagonalDPdii:
.quad _Z28__device_stub___GetDiagonalDPdii
.size _Z13_GetDiagonalDPdii, 8
.type _Z5_DotDPdS_S_iiii,@object # @_Z5_DotDPdS_S_iiii
.globl _Z5_DotDPdS_S_iiii
.p2align 3, 0x0
_Z5_DotDPdS_S_iiii:
.quad _Z20__device_stub___DotDPdS_S_iiii
.size _Z5_DotDPdS_S_iiii, 8
.type _Z8_ColAddDPdidii,@object # @_Z8_ColAddDPdidii
.globl _Z8_ColAddDPdidii
.p2align 3, 0x0
_Z8_ColAddDPdidii:
.quad _Z23__device_stub___ColAddDPdidii
.size _Z8_ColAddDPdidii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6_InitIPiiii"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5_AddIPiS_iiii"
.size .L__unnamed_2, 17
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z6_LAddIPiS_iiiii"
.size .L__unnamed_3, 19
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z5_MulIPiS_S_iii"
.size .L__unnamed_4, 18
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z6_InitDPddii"
.size .L__unnamed_5, 15
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z5_AddDPdS_iiii"
.size .L__unnamed_6, 17
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "_Z6_2AddDPdS_S_iiii"
.size .L__unnamed_7, 20
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "_Z6_LAddDPdS_diiii"
.size .L__unnamed_8, 19
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "_Z5_MulDPdS_S_iii"
.size .L__unnamed_9, 18
.type .L__unnamed_10,@object # @9
.L__unnamed_10:
.asciz "_Z6_SMulDPddii"
.size .L__unnamed_10, 15
.type .L__unnamed_11,@object # @10
.L__unnamed_11:
.asciz "_Z7_2SMulDPdS_dii"
.size .L__unnamed_11, 18
.type .L__unnamed_12,@object # @11
.L__unnamed_12:
.asciz "_Z5_DivDPddii"
.size .L__unnamed_12, 14
.type .L__unnamed_13,@object # @12
.L__unnamed_13:
.asciz "_Z11_TransposeDPdS_ii"
.size .L__unnamed_13, 22
.type .L__unnamed_14,@object # @13
.L__unnamed_14:
.asciz "_Z13_GetDiagonalDPdii"
.size .L__unnamed_14, 22
.type .L__unnamed_15,@object # @14
.L__unnamed_15:
.asciz "_Z5_DotDPdS_S_iiii"
.size .L__unnamed_15, 19
.type .L__unnamed_16,@object # @15
.L__unnamed_16:
.asciz "_Z8_ColAddDPdidii"
.size .L__unnamed_16, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub___InitIPiiii
.addrsig_sym _Z20__device_stub___AddIPiS_iiii
.addrsig_sym _Z21__device_stub___LAddIPiS_iiiii
.addrsig_sym _Z20__device_stub___MulIPiS_S_iii
.addrsig_sym _Z21__device_stub___InitDPddii
.addrsig_sym _Z20__device_stub___AddDPdS_iiii
.addrsig_sym _Z21__device_stub___2AddDPdS_S_iiii
.addrsig_sym _Z21__device_stub___LAddDPdS_diiii
.addrsig_sym _Z20__device_stub___MulDPdS_S_iii
.addrsig_sym _Z21__device_stub___SMulDPddii
.addrsig_sym _Z22__device_stub___2SMulDPdS_dii
.addrsig_sym _Z20__device_stub___DivDPddii
.addrsig_sym _Z26__device_stub___TransposeDPdS_ii
.addrsig_sym _Z28__device_stub___GetDiagonalDPdii
.addrsig_sym _Z20__device_stub___DotDPdS_S_iiii
.addrsig_sym _Z23__device_stub___ColAddDPdidii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6_InitIPiiii
.addrsig_sym _Z5_AddIPiS_iiii
.addrsig_sym _Z6_LAddIPiS_iiiii
.addrsig_sym _Z5_MulIPiS_S_iii
.addrsig_sym _Z6_InitDPddii
.addrsig_sym _Z5_AddDPdS_iiii
.addrsig_sym _Z6_2AddDPdS_S_iiii
.addrsig_sym _Z6_LAddDPdS_diiii
.addrsig_sym _Z5_MulDPdS_S_iii
.addrsig_sym _Z6_SMulDPddii
.addrsig_sym _Z7_2SMulDPdS_dii
.addrsig_sym _Z5_DivDPddii
.addrsig_sym _Z11_TransposeDPdS_ii
.addrsig_sym _Z13_GetDiagonalDPdii
.addrsig_sym _Z5_DotDPdS_S_iiii
.addrsig_sym _Z8_ColAddDPdidii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void analyze(const float *input, float *sum, int numElements) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < numElements) {
atomicAdd(sum + i, input[i]);
}
} | code for sm_80
Function : _Z7analyzePKfPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R2, R3, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fcc00078e0203 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*00b0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x004fe2000c10e784 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void analyze(const float *input, float *sum, int numElements) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < numElements) {
atomicAdd(sum + i, input[i]);
}
} | .file "tmpxft_001316ec_00000000-6_analyze.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z7analyzePKfPfiPKfPfi
.type _Z30__device_stub__Z7analyzePKfPfiPKfPfi, @function
_Z30__device_stub__Z7analyzePKfPfiPKfPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7analyzePKfPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z7analyzePKfPfiPKfPfi, .-_Z30__device_stub__Z7analyzePKfPfiPKfPfi
.globl _Z7analyzePKfPfi
.type _Z7analyzePKfPfi, @function
_Z7analyzePKfPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7analyzePKfPfiPKfPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7analyzePKfPfi, .-_Z7analyzePKfPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7analyzePKfPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7analyzePKfPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void analyze(const float *input, float *sum, int numElements) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < numElements) {
atomicAdd(sum + i, input[i]);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void analyze(const float *input, float *sum, int numElements) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < numElements) {
atomicAdd(sum + i, input[i]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void analyze(const float *input, float *sum, int numElements) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < numElements) {
atomicAdd(sum + i, input[i]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7analyzePKfPfi
.globl _Z7analyzePKfPfi
.p2align 8
.type _Z7analyzePKfPfi,@function
_Z7analyzePKfPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_mov_b32 s0, 0
global_load_b32 v4, v[2:3], off
global_load_b32 v3, v[0:1], off
.LBB0_2:
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v3, v4
global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v2, v3
v_mov_b32_e32 v3, v2
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7analyzePKfPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7analyzePKfPfi, .Lfunc_end0-_Z7analyzePKfPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7analyzePKfPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7analyzePKfPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void analyze(const float *input, float *sum, int numElements) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < numElements) {
atomicAdd(sum + i, input[i]);
}
} | .text
.file "analyze.hip"
.globl _Z22__device_stub__analyzePKfPfi # -- Begin function _Z22__device_stub__analyzePKfPfi
.p2align 4, 0x90
.type _Z22__device_stub__analyzePKfPfi,@function
_Z22__device_stub__analyzePKfPfi: # @_Z22__device_stub__analyzePKfPfi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7analyzePKfPfi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__analyzePKfPfi, .Lfunc_end0-_Z22__device_stub__analyzePKfPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7analyzePKfPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7analyzePKfPfi,@object # @_Z7analyzePKfPfi
.section .rodata,"a",@progbits
.globl _Z7analyzePKfPfi
.p2align 3, 0x0
_Z7analyzePKfPfi:
.quad _Z22__device_stub__analyzePKfPfi
.size _Z7analyzePKfPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7analyzePKfPfi"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__analyzePKfPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7analyzePKfPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7analyzePKfPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R2, R3, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fcc00078e0203 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*00b0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x004fe2000c10e784 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7analyzePKfPfi
.globl _Z7analyzePKfPfi
.p2align 8
.type _Z7analyzePKfPfi,@function
_Z7analyzePKfPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_mov_b32 s0, 0
global_load_b32 v4, v[2:3], off
global_load_b32 v3, v[0:1], off
.LBB0_2:
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v3, v4
global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v2, v3
v_mov_b32_e32 v3, v2
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7analyzePKfPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7analyzePKfPfi, .Lfunc_end0-_Z7analyzePKfPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7analyzePKfPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7analyzePKfPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001316ec_00000000-6_analyze.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z7analyzePKfPfiPKfPfi
.type _Z30__device_stub__Z7analyzePKfPfiPKfPfi, @function
_Z30__device_stub__Z7analyzePKfPfiPKfPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7analyzePKfPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z7analyzePKfPfiPKfPfi, .-_Z30__device_stub__Z7analyzePKfPfiPKfPfi
.globl _Z7analyzePKfPfi
.type _Z7analyzePKfPfi, @function
_Z7analyzePKfPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7analyzePKfPfiPKfPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7analyzePKfPfi, .-_Z7analyzePKfPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7analyzePKfPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7analyzePKfPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "analyze.hip"
.globl _Z22__device_stub__analyzePKfPfi # -- Begin function _Z22__device_stub__analyzePKfPfi
.p2align 4, 0x90
.type _Z22__device_stub__analyzePKfPfi,@function
_Z22__device_stub__analyzePKfPfi: # @_Z22__device_stub__analyzePKfPfi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7analyzePKfPfi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__analyzePKfPfi, .Lfunc_end0-_Z22__device_stub__analyzePKfPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7analyzePKfPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7analyzePKfPfi,@object # @_Z7analyzePKfPfi
.section .rodata,"a",@progbits
.globl _Z7analyzePKfPfi
.p2align 3, 0x0
_Z7analyzePKfPfi:
.quad _Z22__device_stub__analyzePKfPfi
.size _Z7analyzePKfPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7analyzePKfPfi"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__analyzePKfPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7analyzePKfPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <string>
#include <iostream>
#include <iomanip>
#include <fstream>
#include <vector>
#include <locale>
#include <algorithm>
#include <cstdio>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
using namespace std;
const int maxWordLength = 10;
const int arrayCount = 5;
const int inArrayCount = 11;
class Stud {
public:
char name[maxWordLength * arrayCount] = {};
int grades = 0;
double average = 0;
__host__ __device__ Stud() {}
__host__ __device__ Stud(char name[], int grades, double average) {
for (int i = 0; i < maxWordLength * arrayCount; i++) {
this->name[i] = name[i];
if (name[i] == NULL)
{
break;
}
}
//strcpy(this->name, name);
this->grades = grades;
this->average = average;
}
};
//struct is_good {
// const int index;
//
// is_good(int _index) : index(_index) {}
//
// __device__
// bool operator()() {
// return index % inArrayCount == 0;
// }
// /*__device__ bool operator ()(int index) {
// return index % inArrayCount == 0;
// }*/
//};
struct sum_func {
__device__ Stud operator ()(Stud accumulator, Stud item) {
for (int i = 0; i < maxWordLength * arrayCount; i++) {
if (accumulator.name[i] == NULL) {
int index = i;
int tempi = 0;
while (item.name[tempi] != NULL)
{
accumulator.name[index] = item.name[tempi];
tempi++;
index++;
}
break;
}
}
accumulator.grades += item.grades;
accumulator.average += item.average;
return accumulator;
}
};
thrust::host_vector<Stud> Read(std::string fileName)
{
//thrust::host_vector<thrust::host_vector<Stud>> A;
thrust::host_vector<Stud> A;
std::ifstream in;
in.open(fileName);
while (!in.eof())
{
int len;
in >> len;
//thrust::host_vector<Stud> temp;
//std::vector<Stud> temp;
for (size_t i = 0; i < len; i++)
{
std::string name;
in >> name;
int nmb;
in >> nmb;
double average;
in >> average;
char tempWord[maxWordLength] = {};
std::transform(name.begin(), name.end(), name.begin(), ::tolower);//change string letters to lower cases
strcpy(tempWord, name.c_str());//put string to chars
A.push_back(Stud(tempWord, nmb, average));
}
//A.push_back(temp);
}
in.close();
return A;
}
void Write(std::string fileName, thrust::host_vector<Stud> dataArray, thrust::host_vector<Stud> Ans)
{
std::ofstream out;
out.open(fileName);
int a = 0;
out << "Pradiniai duomenys" << std::endl;
for (int i = 0; i < arrayCount; i++)//5
{
out << "Nr. Vardas Pazymiu_skaicius Vidurkis" << std::endl;
int s = 0;
for (int j = 0; j < inArrayCount; j++)//11
{
out << std::left << std::setw(4) << j + 1 << std::setw(10) << static_cast<Stud>(dataArray[j]).name << std::setw(18) << static_cast<Stud>(dataArray[j]).grades << static_cast<Stud>(dataArray[j]).average << std::endl;
}
}
out << std::endl;
out << "Rezultatas" << std::endl;
out << std::left << std::setw(40) << "Vardai" << std::setw(10) << "Pazymiai" << "Vidurkiai" << std::endl;
for (int i = 0; i < inArrayCount; i++)
{
out << std::left << std::setw(40) << static_cast<Stud>(Ans[i]).name << std::setw(10) << static_cast<Stud>(Ans[i]).grades << static_cast<Stud>(Ans[i]).average << std::endl;
}
out << std::endl;
out.close();
}
// Pagrindinë programa
int main()
{
thrust::host_vector<Stud> data;
thrust::device_vector<Stud> dev_data;
//thrust::device_vector<Stud> rez_temp(arrayCount);
thrust::device_vector<Stud> dev_rez(inArrayCount);
//dev_rez[0] = rez_temp[2];
data = Read("IFF68_LaurinaitisTadas_L4.txt");
//int i = 0;
dev_data = data;
//copy_if(dev_data.begin + i, dev_data.end, rez_temp, is_good());
int begin = 0;
for (int i = 0; i < inArrayCount; i++)//11
{
thrust::device_vector<Stud> dev_temp;
for (int j = 0; j < inArrayCount * arrayCount; j++)//55
{
if ((j + begin) % inArrayCount == 0) {
Stud tmp = static_cast<Stud>(dev_data[j]);
dev_temp.push_back(tmp);
}
}
Stud temp;
dev_rez[i] = thrust::reduce(dev_temp.begin(), dev_temp.end(), temp, sum_func());
begin--;
}
/*for (int i = 0; i < inArrayCount; i++)
{
std::cout << static_cast<Stud>(dev_rez[i]).name << static_cast<Stud>(dev_rez[i]).grades << static_cast<Stud>(dev_rez[i]).average << std::endl;
}*/
thrust::host_vector<Stud> rez;
rez = dev_rez;
Write("IFF68_LaurinaitisTadas_L4_rez.txt", data, rez);
return 0;
} | #include "hip/hip_runtime.h"
#include <string>
#include <iostream>
#include <iomanip>
#include <fstream>
#include <vector>
#include <locale>
#include <algorithm>
#include <cstdio>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
using namespace std;
const int maxWordLength = 10;
const int arrayCount = 5;
const int inArrayCount = 11;
class Stud {
public:
char name[maxWordLength * arrayCount] = {};
int grades = 0;
double average = 0;
__host__ __device__ Stud() {}
__host__ __device__ Stud(char name[], int grades, double average) {
for (int i = 0; i < maxWordLength * arrayCount; i++) {
this->name[i] = name[i];
if (name[i] == NULL)
{
break;
}
}
//strcpy(this->name, name);
this->grades = grades;
this->average = average;
}
};
//struct is_good {
// const int index;
//
// is_good(int _index) : index(_index) {}
//
// __device__
// bool operator()() {
// return index % inArrayCount == 0;
// }
// /*__device__ bool operator ()(int index) {
// return index % inArrayCount == 0;
// }*/
//};
struct sum_func {
__device__ Stud operator ()(Stud accumulator, Stud item) {
for (int i = 0; i < maxWordLength * arrayCount; i++) {
if (accumulator.name[i] == NULL) {
int index = i;
int tempi = 0;
while (item.name[tempi] != NULL)
{
accumulator.name[index] = item.name[tempi];
tempi++;
index++;
}
break;
}
}
accumulator.grades += item.grades;
accumulator.average += item.average;
return accumulator;
}
};
thrust::host_vector<Stud> Read(std::string fileName)
{
//thrust::host_vector<thrust::host_vector<Stud>> A;
thrust::host_vector<Stud> A;
std::ifstream in;
in.open(fileName);
while (!in.eof())
{
int len;
in >> len;
//thrust::host_vector<Stud> temp;
//std::vector<Stud> temp;
for (size_t i = 0; i < len; i++)
{
std::string name;
in >> name;
int nmb;
in >> nmb;
double average;
in >> average;
char tempWord[maxWordLength] = {};
std::transform(name.begin(), name.end(), name.begin(), ::tolower);//change string letters to lower cases
strcpy(tempWord, name.c_str());//put string to chars
A.push_back(Stud(tempWord, nmb, average));
}
//A.push_back(temp);
}
in.close();
return A;
}
void Write(std::string fileName, thrust::host_vector<Stud> dataArray, thrust::host_vector<Stud> Ans)
{
std::ofstream out;
out.open(fileName);
int a = 0;
out << "Pradiniai duomenys" << std::endl;
for (int i = 0; i < arrayCount; i++)//5
{
out << "Nr. Vardas Pazymiu_skaicius Vidurkis" << std::endl;
int s = 0;
for (int j = 0; j < inArrayCount; j++)//11
{
out << std::left << std::setw(4) << j + 1 << std::setw(10) << static_cast<Stud>(dataArray[j]).name << std::setw(18) << static_cast<Stud>(dataArray[j]).grades << static_cast<Stud>(dataArray[j]).average << std::endl;
}
}
out << std::endl;
out << "Rezultatas" << std::endl;
out << std::left << std::setw(40) << "Vardai" << std::setw(10) << "Pazymiai" << "Vidurkiai" << std::endl;
for (int i = 0; i < inArrayCount; i++)
{
out << std::left << std::setw(40) << static_cast<Stud>(Ans[i]).name << std::setw(10) << static_cast<Stud>(Ans[i]).grades << static_cast<Stud>(Ans[i]).average << std::endl;
}
out << std::endl;
out.close();
}
// Pagrindinë programa
int main()
{
thrust::host_vector<Stud> data;
thrust::device_vector<Stud> dev_data;
//thrust::device_vector<Stud> rez_temp(arrayCount);
thrust::device_vector<Stud> dev_rez(inArrayCount);
//dev_rez[0] = rez_temp[2];
data = Read("IFF68_LaurinaitisTadas_L4.txt");
//int i = 0;
dev_data = data;
//copy_if(dev_data.begin + i, dev_data.end, rez_temp, is_good());
int begin = 0;
for (int i = 0; i < inArrayCount; i++)//11
{
thrust::device_vector<Stud> dev_temp;
for (int j = 0; j < inArrayCount * arrayCount; j++)//55
{
if ((j + begin) % inArrayCount == 0) {
Stud tmp = static_cast<Stud>(dev_data[j]);
dev_temp.push_back(tmp);
}
}
Stud temp;
dev_rez[i] = thrust::reduce(dev_temp.begin(), dev_temp.end(), temp, sum_func());
begin--;
}
/*for (int i = 0; i < inArrayCount; i++)
{
std::cout << static_cast<Stud>(dev_rez[i]).name << static_cast<Stud>(dev_rez[i]).grades << static_cast<Stud>(dev_rez[i]).average << std::endl;
}*/
thrust::host_vector<Stud> rez;
rez = dev_rez;
Write("IFF68_LaurinaitisTadas_L4_rez.txt", data, rez);
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdint.h>
#include <assert.h>
// #define DEBUG
#define UINT uint32_t
#define TOPM 26
#define MAXN 1024
#define MULSIDE 16 // each block has size SIDE x SIDE
#define MULBLK (MAXN / MULSIDE) // divide C into BLK x BLK blocks
#define ADDSIDE 256
#define ADDBLK (MAXN*(MAXN / ADDSIDE))
// function for debugging.
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__device__ static inline UINT get(int N, UINT* M, int x, int y){
return (x < N && y < N) ? M[x*N + y] : 0;
}
__device__ static inline void set(int N, UINT* M, int x, int y, UINT v){
if (x < N && y < N)
M[x*N + y] = v;
return;
}
__global__ void mul_kernel(int N, UINT* A, UINT* B, UINT* C){
__shared__ UINT left[MULSIDE][MULSIDE];
__shared__ UINT right[MULSIDE][MULSIDE];
int localx = threadIdx.x;
int localy = threadIdx.y;
int globalx = blockIdx.x * MULSIDE + localx;//x for C
int globaly = blockIdx.y * MULSIDE + localy;//y for C
UINT result = 0;
for(int block = 0; block < MULBLK; block++){
left[localx][localy] = get(N, A, globalx, (block*MULSIDE + localy));
right[localy][localx] = get(N, B, block*MULSIDE + localx, globaly);
__syncthreads();
for(int k = 0; k < MULSIDE; k++){
result += left[localx][k] * right[localy][k];
}
__syncthreads();
}
set(N, C, globalx, globaly, result);
}
__global__ void add_kernel(int N, UINT* A, UINT* B, UINT* C){
int index = blockIdx.x * ADDSIDE + threadIdx.x;
if (index < N)
C[index] = A[index] + B[index];
}
void rand_gen(UINT c, int N, UINT* A) {
UINT x = 2, n = N*N;
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
x = (x * x + c + i + j)%n;
A[i*N + j] = x;
}
}
}
void print_matrix(int N, UINT* A) {
for (int i = 0; i < N; i++) {
fprintf(stderr, "[");
for (int j = 0; j < N; j++)
fprintf(stderr, " %u", A[i*N + j]);
fprintf(stderr, " ]\n");
}
}
UINT signature(int N, UINT* A) {
UINT h = 0;
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++)
h = (h + A[i*N + j]) * 2654435761LU;
}
return h;
}
UINT hostIN[TOPM][MAXN*MAXN], hostTMP[MAXN*MAXN];
int main() {
int M, N, S[TOPM], s;
s = scanf("%d %d", &M, &N);
for (int i = 0; i < M; i++) {
s = scanf("%d", &S[i]);
rand_gen(S[i], N, hostIN[i]);
}
UINT *IN[TOPM];
UINT *TMP[TOPM];
size_t matsz = sizeof(UINT) * N * N;
for (int i = 0; i < M; i++){
gpuErrchk(cudaMalloc(&IN[i], matsz));
gpuErrchk(cudaMemcpy(IN[i], hostIN[i], matsz, cudaMemcpyHostToDevice));
}
for (int i = 0; i < TOPM; i++)
gpuErrchk(cudaMalloc(&TMP[i], matsz));
int Q;
char E[26];
s = scanf("%d", &Q);
for (int i = 0; i < Q; i++) {
s = scanf("%s", E);
UINT *addbuf = NULL, *mulbuf = NULL, *r_operand;
for (int j = 0, tmp_id = 0; j < 27; j++){
// fprintf(stderr, "j=%d, \'%c\', tmp=%d\n", j, E[j]=='\0' ? '#' : E[j], tmp_id);
if(j < 26 && E[j] != '\0' && E[j] != '+'){
// before +
if (mulbuf == NULL){
// first operand
mulbuf = IN[E[j]-'A'];
}
else{
// right operand
r_operand = IN[E[j]-'A'];
mul_kernel <<< dim3(MULBLK,MULBLK), dim3(MULSIDE,MULSIDE) >>>
(N, mulbuf, r_operand, TMP[tmp_id]);
mulbuf = TMP[tmp_id++];
}
}
else if(addbuf == NULL){
// first segment e.g. "ABCD"+EF...
addbuf = mulbuf;
mulbuf = NULL;
}
else{
// new segment e.g. ABCD+"EF"...
add_kernel <<< ADDBLK, ADDSIDE >>> (N*N, addbuf, mulbuf, TMP[tmp_id]);
addbuf = TMP[tmp_id++];
mulbuf = NULL;
}
if (j >= 26 || E[j] == '\0')
break;
gpuErrchk(cudaPeekAtLastError());
gpuErrchk(cudaDeviceSynchronize());
}
gpuErrchk(cudaMemcpy(hostTMP, addbuf, matsz, cudaMemcpyDeviceToHost));
printf("%u\n", signature(N, hostTMP));
}
assert(s>0);
for (int i = 0; i < M; i++){
gpuErrchk(cudaFree(IN[i]));
}
for (int i = 0; i < TOPM; i++){
gpuErrchk(cudaFree(TMP[i]));
}
return 0;
} | code for sm_80
Function : _Z10add_kerneliPjS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ LEA R6, R6, R3, 0x8 ; /* 0x0000000306067211 */
/* 0x001fc800078e40ff */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10mul_kerneliPjS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R23, SR_TID.X ; /* 0x0000000000177919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R20, RZ ; /* 0x000000ff00147202 */
/* 0x000fe20000000f00 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0070*/ S2R R22, SR_TID.Y ; /* 0x0000000000167919 */
/* 0x000ea80000002200 */
/*0080*/ S2R R28, SR_CTAID.Y ; /* 0x00000000001c7919 */
/* 0x000ee20000002600 */
/*0090*/ SHF.L.U32 R27, R23.reuse, 0x6, RZ ; /* 0x00000006171b7819 */
/* 0x041fe400000006ff */
/*00a0*/ LEA R29, R0, R23, 0x4 ; /* 0x00000017001d7211 */
/* 0x002fe200078e20ff */
/*00b0*/ IMAD R21, R23, c[0x0][0x160], R22 ; /* 0x0000580017157a24 */
/* 0x004fe200078e0216 */
/*00c0*/ LEA R26, R22, 0x400, 0x6 ; /* 0x00000400161a7811 */
/* 0x000fc600078e30ff */
/*00d0*/ IMAD R2, R29.reuse, c[0x0][0x160], R22.reuse ; /* 0x000058001d027a24 */
/* 0x140fe200078e0216 */
/*00e0*/ ISETP.GE.AND P1, PT, R29, c[0x0][0x160], PT ; /* 0x000058001d007a0c */
/* 0x000fe40003f26270 */
/*00f0*/ LEA R21, R28, R21, 0x4 ; /* 0x000000151c157211 */
/* 0x008fe200078e20ff */
/*0100*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe200078e0203 */
/*0110*/ LEA R25, R22, R27, 0x2 ; /* 0x0000001b16197211 */
/* 0x000fe400078e10ff */
/*0120*/ LEA R24, R23, R26, 0x2 ; /* 0x0000001a17187211 */
/* 0x000fe200078e10ff */
/*0130*/ IMAD R28, R28, 0x10, R22 ; /* 0x000000101c1c7824 */
/* 0x000fca00078e0216 */
/*0140*/ ISETP.GE.AND P0, PT, R28, c[0x0][0x160], PT ; /* 0x000058001c007a0c */
/* 0x000fe20003f06270 */
/*0150*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0160*/ ISETP.GE.OR P2, PT, R22, c[0x0][0x160], P1 ; /* 0x0000580016007a0c */
/* 0x000fc40000f46670 */
/*0170*/ ISETP.GE.OR P3, PT, R23, c[0x0][0x160], P0 ; /* 0x0000580017007a0c */
/* 0x000fe40000766670 */
/*0180*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fd20000000f00 */
/*0190*/ @!P2 LDG.E R6, [R2.64] ; /* 0x000000040206a981 */
/* 0x0000a4000c1e1900 */
/*01a0*/ @!P3 MOV R4, 0x4 ; /* 0x000000040004b802 */
/* 0x000fca0000000f00 */
/*01b0*/ @!P3 IMAD.WIDE R4, R21, R4, c[0x0][0x170] ; /* 0x00005c001504b625 */
/* 0x000fca00078e0204 */
/*01c0*/ @!P3 LDG.E R9, [R4.64] ; /* 0x000000040409b981 */
/* 0x000ee2000c1e1900 */
/*01d0*/ IADD3 R20, R20, 0x1, RZ ; /* 0x0000000114147810 */
/* 0x000fc80007ffe0ff */
/*01e0*/ ISETP.NE.AND P2, PT, R20, 0x40, PT ; /* 0x000000401400780c */
/* 0x000fe40003f45270 */
/*01f0*/ IADD3 R2, P3, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x001fe40007f7e0ff */
/*0200*/ IADD3 R22, R22, 0x10, RZ ; /* 0x0000001016167810 */
/* 0x000fe40007ffe0ff */
/*0210*/ IADD3 R23, R23, 0x10, RZ ; /* 0x0000001017177810 */
/* 0x000fe40007ffe0ff */
/*0220*/ IADD3.X R3, RZ, R3, RZ, P3, !PT ; /* 0x00000003ff037210 */
/* 0x000fe20001ffe4ff */
/*0230*/ STS [R25], R6 ; /* 0x0000000619007388 */
/* 0x004fe80000000800 */
/*0240*/ STS [R24], R9 ; /* 0x0000000918007388 */
/* 0x008fe80000000800 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0260*/ LDS.128 R12, [R26] ; /* 0x000000001a0c7984 */
/* 0x000fe80000000c00 */
/*0270*/ LDS.128 R16, [R27] ; /* 0x000000001b107984 */
/* 0x000e280000000c00 */
/*0280*/ LDS.128 R8, [R26+0x10] ; /* 0x000010001a087984 */
/* 0x000fe20000000c00 */
/*0290*/ IMAD R12, R12, R16, R7 ; /* 0x000000100c0c7224 */
/* 0x001fc600078e0207 */
/*02a0*/ LDS.128 R4, [R27+0x10] ; /* 0x000010001b047984 */
/* 0x000e220000000c00 */
/*02b0*/ IMAD R13, R13, R17, R12 ; /* 0x000000110d0d7224 */
/* 0x000fc800078e020c */
/*02c0*/ IMAD R14, R14, R18, R13 ; /* 0x000000120e0e7224 */
/* 0x000fc800078e020d */
/*02d0*/ IMAD R15, R15, R19, R14 ; /* 0x000000130f0f7224 */
/* 0x000fe400078e020e */
/*02e0*/ LDS.128 R16, [R27+0x20] ; /* 0x000020001b107984 */
/* 0x000fe40000000c00 */
/*02f0*/ IMAD R4, R8, R4, R15 ; /* 0x0000000408047224 */
/* 0x001fe400078e020f */
/*0300*/ LDS.128 R12, [R26+0x20] ; /* 0x000020001a0c7984 */
/* 0x000e240000000c00 */
/*0310*/ IMAD R5, R9, R5, R4 ; /* 0x0000000509057224 */
/* 0x000fc800078e0204 */
/*0320*/ IMAD R6, R10, R6, R5 ; /* 0x000000060a067224 */
/* 0x000fc800078e0205 */
/*0330*/ IMAD R7, R11, R7, R6 ; /* 0x000000070b077224 */
/* 0x000fe400078e0206 */
/*0340*/ LDS.128 R8, [R27+0x30] ; /* 0x000030001b087984 */
/* 0x000fe40000000c00 */
/*0350*/ IMAD R12, R12, R16, R7 ; /* 0x000000100c0c7224 */
/* 0x001fe400078e0207 */
/*0360*/ LDS.128 R4, [R26+0x30] ; /* 0x000030001a047984 */
/* 0x000e240000000c00 */
/*0370*/ IMAD R13, R13, R17, R12 ; /* 0x000000110d0d7224 */
/* 0x000fc800078e020c */
/*0380*/ IMAD R14, R14, R18, R13 ; /* 0x000000120e0e7224 */
/* 0x000fc800078e020d */
/*0390*/ IMAD R15, R15, R19, R14 ; /* 0x000000130f0f7224 */
/* 0x000fc800078e020e */
/*03a0*/ IMAD R4, R4, R8, R15 ; /* 0x0000000804047224 */
/* 0x001fc800078e020f */
/*03b0*/ IMAD R5, R5, R9, R4 ; /* 0x0000000905057224 */
/* 0x000fe200078e0204 */
/*03c0*/ MOV R4, 0x10 ; /* 0x0000001000047802 */
/* 0x000fc60000000f00 */
/*03d0*/ IMAD R6, R6, R10, R5 ; /* 0x0000000a06067224 */
/* 0x000fe400078e0205 */
/*03e0*/ IMAD R21, R4, c[0x0][0x160], R21 ; /* 0x0000580004157a24 */
/* 0x000fe400078e0215 */
/*03f0*/ IMAD R7, R7, R11, R6 ; /* 0x0000000b07077224 */
/* 0x000fe200078e0206 */
/*0400*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0410*/ @P2 BRA 0x140 ; /* 0xfffffd2000002947 */
/* 0x000fea000383ffff */
/*0420*/ ISETP.GE.OR P0, PT, R29, c[0x0][0x160], P0 ; /* 0x000058001d007a0c */
/* 0x000fda0000706670 */
/*0430*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0440*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0450*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0460*/ LEA R3, R0, R3, 0x4 ; /* 0x0000000300037211 */
/* 0x001fca00078e20ff */
/*0470*/ IMAD R2, R3, c[0x0][0x160], R28 ; /* 0x0000580003027a24 */
/* 0x000fc800078e021c */
/*0480*/ IMAD.WIDE R2, R2, R5, c[0x0][0x178] ; /* 0x00005e0002027625 */
/* 0x000fca00078e0205 */
/*0490*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*04a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04b0*/ BRA 0x4b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdint.h>
#include <assert.h>
// #define DEBUG
#define UINT uint32_t
#define TOPM 26
#define MAXN 1024
#define MULSIDE 16 // each block has size SIDE x SIDE
#define MULBLK (MAXN / MULSIDE) // divide C into BLK x BLK blocks
#define ADDSIDE 256
#define ADDBLK (MAXN*(MAXN / ADDSIDE))
// function for debugging.
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__device__ static inline UINT get(int N, UINT* M, int x, int y){
return (x < N && y < N) ? M[x*N + y] : 0;
}
__device__ static inline void set(int N, UINT* M, int x, int y, UINT v){
if (x < N && y < N)
M[x*N + y] = v;
return;
}
__global__ void mul_kernel(int N, UINT* A, UINT* B, UINT* C){
__shared__ UINT left[MULSIDE][MULSIDE];
__shared__ UINT right[MULSIDE][MULSIDE];
int localx = threadIdx.x;
int localy = threadIdx.y;
int globalx = blockIdx.x * MULSIDE + localx;//x for C
int globaly = blockIdx.y * MULSIDE + localy;//y for C
UINT result = 0;
for(int block = 0; block < MULBLK; block++){
left[localx][localy] = get(N, A, globalx, (block*MULSIDE + localy));
right[localy][localx] = get(N, B, block*MULSIDE + localx, globaly);
__syncthreads();
for(int k = 0; k < MULSIDE; k++){
result += left[localx][k] * right[localy][k];
}
__syncthreads();
}
set(N, C, globalx, globaly, result);
}
__global__ void add_kernel(int N, UINT* A, UINT* B, UINT* C){
int index = blockIdx.x * ADDSIDE + threadIdx.x;
if (index < N)
C[index] = A[index] + B[index];
}
void rand_gen(UINT c, int N, UINT* A) {
UINT x = 2, n = N*N;
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
x = (x * x + c + i + j)%n;
A[i*N + j] = x;
}
}
}
void print_matrix(int N, UINT* A) {
for (int i = 0; i < N; i++) {
fprintf(stderr, "[");
for (int j = 0; j < N; j++)
fprintf(stderr, " %u", A[i*N + j]);
fprintf(stderr, " ]\n");
}
}
UINT signature(int N, UINT* A) {
UINT h = 0;
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++)
h = (h + A[i*N + j]) * 2654435761LU;
}
return h;
}
UINT hostIN[TOPM][MAXN*MAXN], hostTMP[MAXN*MAXN];
int main() {
int M, N, S[TOPM], s;
s = scanf("%d %d", &M, &N);
for (int i = 0; i < M; i++) {
s = scanf("%d", &S[i]);
rand_gen(S[i], N, hostIN[i]);
}
UINT *IN[TOPM];
UINT *TMP[TOPM];
size_t matsz = sizeof(UINT) * N * N;
for (int i = 0; i < M; i++){
gpuErrchk(cudaMalloc(&IN[i], matsz));
gpuErrchk(cudaMemcpy(IN[i], hostIN[i], matsz, cudaMemcpyHostToDevice));
}
for (int i = 0; i < TOPM; i++)
gpuErrchk(cudaMalloc(&TMP[i], matsz));
int Q;
char E[26];
s = scanf("%d", &Q);
for (int i = 0; i < Q; i++) {
s = scanf("%s", E);
UINT *addbuf = NULL, *mulbuf = NULL, *r_operand;
for (int j = 0, tmp_id = 0; j < 27; j++){
// fprintf(stderr, "j=%d, \'%c\', tmp=%d\n", j, E[j]=='\0' ? '#' : E[j], tmp_id);
if(j < 26 && E[j] != '\0' && E[j] != '+'){
// before +
if (mulbuf == NULL){
// first operand
mulbuf = IN[E[j]-'A'];
}
else{
// right operand
r_operand = IN[E[j]-'A'];
mul_kernel <<< dim3(MULBLK,MULBLK), dim3(MULSIDE,MULSIDE) >>>
(N, mulbuf, r_operand, TMP[tmp_id]);
mulbuf = TMP[tmp_id++];
}
}
else if(addbuf == NULL){
// first segment e.g. "ABCD"+EF...
addbuf = mulbuf;
mulbuf = NULL;
}
else{
// new segment e.g. ABCD+"EF"...
add_kernel <<< ADDBLK, ADDSIDE >>> (N*N, addbuf, mulbuf, TMP[tmp_id]);
addbuf = TMP[tmp_id++];
mulbuf = NULL;
}
if (j >= 26 || E[j] == '\0')
break;
gpuErrchk(cudaPeekAtLastError());
gpuErrchk(cudaDeviceSynchronize());
}
gpuErrchk(cudaMemcpy(hostTMP, addbuf, matsz, cudaMemcpyDeviceToHost));
printf("%u\n", signature(N, hostTMP));
}
assert(s>0);
for (int i = 0; i < M; i++){
gpuErrchk(cudaFree(IN[i]));
}
for (int i = 0; i < TOPM; i++){
gpuErrchk(cudaFree(TMP[i]));
}
return 0;
} | .file "tmpxft_00107c8e_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8rand_genjiPj
.type _Z8rand_genjiPj, @function
_Z8rand_genjiPj:
.LFB2060:
.cfi_startproc
endbr64
movl %edi, %r8d
movl %esi, %edi
imull %esi, %edi
testl %esi, %esi
jle .L3
movslq %esi, %r10
leaq 0(,%r10,4), %r11
movq %rdx, %r9
addl %r8d, %esi
movl $2, %eax
.L5:
movl $0, %ecx
.L6:
imull %eax, %eax
addl %r8d, %eax
addl %ecx, %eax
movl $0, %edx
divl %edi
movl %edx, %eax
movl %edx, (%r9,%rcx,4)
addq $1, %rcx
cmpq %r10, %rcx
jne .L6
addl $1, %r8d
addq %r11, %r9
cmpl %esi, %r8d
jne .L5
.L3:
ret
.cfi_endproc
.LFE2060:
.size _Z8rand_genjiPj, .-_Z8rand_genjiPj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "["
.LC1:
.string " %u"
.LC2:
.string " ]\n"
.text
.globl _Z12print_matrixiPj
.type _Z12print_matrixiPj, @function
_Z12print_matrixiPj:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
testl %edi, %edi
jle .L8
movslq %edi, %r14
leaq 0(,%r14,4), %r15
leaq (%rsi,%r15), %rbp
negq %r14
salq $2, %r14
movl $0, %r13d
leaq .LC1(%rip), %r12
.L11:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq 0(%rbp,%r14), %rbx
.L10:
movl (%rbx), %ecx
movq %r12, %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L10
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L11
.L8:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z12print_matrixiPj, .-_Z12print_matrixiPj
.globl _Z9signatureiPj
.type _Z9signatureiPj, @function
_Z9signatureiPj:
.LFB2062:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L19
movslq %edi, %r8
leaq 0(,%r8,4), %r9
leaq (%rsi,%r9), %rcx
negq %r8
salq $2, %r8
movl $0, %esi
movl $0, %eax
.L17:
leaq (%rcx,%r8), %rdx
.L18:
addl (%rdx), %eax
imull $-1640531535, %eax, %eax
addq $4, %rdx
cmpq %rcx, %rdx
jne .L18
addl $1, %esi
addq %r9, %rcx
cmpl %esi, %edi
jne .L17
.L15:
ret
.L19:
movl $0, %eax
ret
.cfi_endproc
.LFE2062:
.size _Z9signatureiPj, .-_Z9signatureiPj
.globl _Z35__device_stub__Z10mul_kerneliPjS_S_iPjS_S_
.type _Z35__device_stub__Z10mul_kerneliPjS_S_iPjS_S_, @function
_Z35__device_stub__Z10mul_kerneliPjS_S_iPjS_S_:
.LFB2088:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10mul_kerneliPjS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z35__device_stub__Z10mul_kerneliPjS_S_iPjS_S_, .-_Z35__device_stub__Z10mul_kerneliPjS_S_iPjS_S_
.globl _Z10mul_kerneliPjS_S_
.type _Z10mul_kerneliPjS_S_, @function
_Z10mul_kerneliPjS_S_:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10mul_kerneliPjS_S_iPjS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z10mul_kerneliPjS_S_, .-_Z10mul_kerneliPjS_S_
.globl _Z35__device_stub__Z10add_kerneliPjS_S_iPjS_S_
.type _Z35__device_stub__Z10add_kerneliPjS_S_iPjS_S_, @function
_Z35__device_stub__Z10add_kerneliPjS_S_iPjS_S_:
.LFB2090:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10add_kerneliPjS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z35__device_stub__Z10add_kerneliPjS_S_iPjS_S_, .-_Z35__device_stub__Z10add_kerneliPjS_S_iPjS_S_
.globl _Z10add_kerneliPjS_S_
.type _Z10add_kerneliPjS_S_, @function
_Z10add_kerneliPjS_S_:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10add_kerneliPjS_S_iPjS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z10add_kerneliPjS_S_, .-_Z10add_kerneliPjS_S_
.section .rodata.str1.1
.LC3:
.string "%d %d"
.LC4:
.string "%d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "/home/ubuntu/Datasets/stackv2/train-structured/George0828Zhang/cuda-practice/main/AdvancedMatrixCalculator/main.cu"
.section .rodata.str1.1
.LC6:
.string "GPUassert: %s %s %d\n"
.LC7:
.string "%s"
.LC8:
.string "%u\n"
.text
.globl main
.type main, @function
main:
.LFB2063:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $664, %rsp
.cfi_def_cfa_offset 720
movq %fs:40, %rax
movq %rax, 648(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq .LC3(%rip), %rdi
call __isoc23_scanf@PLT
cmpl $0, 44(%rsp)
jle .L38
leaq 80(%rsp), %rbp
movl $0, %ebx
leaq .LC4(%rip), %r13
leaq hostIN(%rip), %r12
.L39:
movq %rbp, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq %rbx, %rdx
salq $22, %rdx
addq %r12, %rdx
movl 0(%rbp), %edi
movl 48(%rsp), %esi
call _Z8rand_genjiPj
movl 44(%rsp), %eax
addq $1, %rbx
addq $4, %rbp
cmpl %ebx, %eax
jg .L39
movslq 48(%rsp), %rbx
imulq %rbx, %rbx
salq $2, %rbx
testl %eax, %eax
jle .L40
movl $0, %r13d
leaq 192(%rsp), %r14
.L43:
leaq (%r14,%r13,8), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L79
movq %r13, %rsi
salq $22, %rsi
addq %r12, %rsi
movq (%r14,%r13,8), %rdi
movl $1, %ecx
movq %rbx, %rdx
call cudaMemcpy@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L80
addq $1, %r13
cmpl %r13d, 44(%rsp)
jg .L43
jmp .L40
.L79:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $102, %r9d
leaq .LC5(%rip), %r8
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L80:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $103, %r9d
leaq .LC5(%rip), %r8
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L88:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $106, %r9d
leaq .LC5(%rip), %r8
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L90:
testq %r13, %r13
je .L81
movsbl %al, %eax
subl $65, %eax
cltq
movq 192(%rsp,%rax,8), %rax
movq %rax, 16(%rsp)
movl $16, 68(%rsp)
movl $16, 72(%rsp)
movl $1, 76(%rsp)
movl $64, 56(%rsp)
movl $64, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L82
.L51:
leal 1(%rbp), %eax
movslq %ebp, %rbp
movq %r14, %r13
movq 400(%rsp,%rbp,8), %r14
jmp .L52
.L81:
movsbl %al, %eax
subl $65, %eax
cltq
movq 192(%rsp,%rax,8), %r13
jmp .L50
.L82:
movslq %ebp, %rax
movq 400(%rsp,%rax,8), %rcx
movq 16(%rsp), %rdx
movq %r13, %rsi
movl 48(%rsp), %edi
call _Z35__device_stub__Z10mul_kerneliPjS_S_iPjS_S_
jmp .L51
.L65:
movl 48(%rsp), %edi
movslq %ebp, %rax
movq %rax, 24(%rsp)
movq 400(%rsp,%rax,8), %rcx
imull %edi, %edi
movq %r13, %rdx
movq %r14, %rsi
call _Z35__device_stub__Z10add_kerneliPjS_S_iPjS_S_
leal 1(%rbp), %eax
movq 24(%rsp), %rcx
movq 400(%rsp,%rcx,8), %r13
cmpl $25, 16(%rsp)
jg .L53
movl $0, %r14d
jmp .L52
.L91:
movl %ebp, %eax
.L52:
cmpb $0, (%r12,%r15)
je .L53
movq %r13, %rdx
movq %r14, %r13
movq %rdx, %r14
movl %eax, %ebp
.L50:
call cudaPeekAtLastError@PLT
movl %eax, %edi
testl %eax, %eax
jne .L83
call cudaDeviceSynchronize@PLT
movl %eax, %edi
addq $1, %r12
testl %eax, %eax
je .L55
movl %eax, %ebx
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $146, %r9d
leaq .LC5(%rip), %r8
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L83:
movl %eax, %ebx
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $145, %r9d
leaq .LC5(%rip), %r8
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L87:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $148, %r9d
leaq .LC5(%rip), %r8
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L89:
movl $0, %ebp
.L58:
cmpl %ebp, 44(%rsp)
jle .L84
movq 192(%rsp,%rbp,8), %rdi
call cudaFree@PLT
movl %eax, %ebx
addq $1, %rbp
testl %eax, %eax
je .L58
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $154, %r9d
leaq .LC5(%rip), %r8
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L84:
movl $0, %ebp
.L61:
movq 400(%rsp,%rbp,8), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L85
addq $1, %rbp
cmpq $26, %rbp
jne .L61
movq 648(%rsp), %rax
subq %fs:40, %rax
jne .L86
movl $0, %eax
addq $664, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L85:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $157, %r9d
leaq .LC5(%rip), %r8
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L47:
testq %r14, %r14
je .L53
movl $256, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $4096, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
movslq %ebp, %rbp
movq 400(%rsp,%rbp,8), %r13
.L53:
movl $2, %ecx
movq %rbx, %rdx
movq %r13, %rsi
leaq hostTMP(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L87
leaq hostTMP(%rip), %rsi
movl 48(%rsp), %edi
call _Z9signatureiPj
movl %eax, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, 12(%rsp)
jmp .L46
.L38:
movslq 48(%rsp), %rbx
imulq %rbx, %rbx
salq $2, %rbx
.L40:
leaq 400(%rsp), %r12
leaq 608(%rsp), %r13
.L45:
movq %rbx, %rsi
movq %r12, %rdi
call cudaMalloc@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L88
addq $8, %r12
cmpq %r13, %r12
jne .L45
leaq 52(%rsp), %rsi
leaq .LC4(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $0, 12(%rsp)
.L46:
movl 12(%rsp), %eax
cmpl %eax, 52(%rsp)
jle .L89
leaq 608(%rsp), %rsi
leaq .LC7(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $0, %r12d
movl $0, %ebp
movl $0, %r13d
movl $0, %r14d
leaq 608(%rsp), %r15
.L55:
movl %r12d, 16(%rsp)
cmpl $25, %r12d
jg .L47
movzbl (%r12,%r15), %eax
cmpb $43, %al
je .L48
testb %al, %al
jne .L90
.L48:
testq %r14, %r14
je .L91
movl $256, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $4096, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
leal 1(%rbp), %eax
movslq %ebp, %rbp
movq 400(%rsp,%rbp,8), %r13
movl $0, %r14d
jmp .L52
.L86:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z10add_kerneliPjS_S_"
.LC10:
.string "_Z10mul_kerneliPjS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z10add_kerneliPjS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z10mul_kerneliPjS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl hostTMP
.bss
.align 32
.type hostTMP, @object
.size hostTMP, 4194304
hostTMP:
.zero 4194304
.globl hostIN
.align 32
.type hostIN, @object
.size hostIN, 109051904
hostIN:
.zero 109051904
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdint.h>
#include <assert.h>
// #define DEBUG
#define UINT uint32_t
#define TOPM 26
#define MAXN 1024
#define MULSIDE 16 // each block has size SIDE x SIDE
#define MULBLK (MAXN / MULSIDE) // divide C into BLK x BLK blocks
#define ADDSIDE 256
#define ADDBLK (MAXN*(MAXN / ADDSIDE))
// function for debugging.
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__device__ static inline UINT get(int N, UINT* M, int x, int y){
return (x < N && y < N) ? M[x*N + y] : 0;
}
__device__ static inline void set(int N, UINT* M, int x, int y, UINT v){
if (x < N && y < N)
M[x*N + y] = v;
return;
}
__global__ void mul_kernel(int N, UINT* A, UINT* B, UINT* C){
__shared__ UINT left[MULSIDE][MULSIDE];
__shared__ UINT right[MULSIDE][MULSIDE];
int localx = threadIdx.x;
int localy = threadIdx.y;
int globalx = blockIdx.x * MULSIDE + localx;//x for C
int globaly = blockIdx.y * MULSIDE + localy;//y for C
UINT result = 0;
for(int block = 0; block < MULBLK; block++){
left[localx][localy] = get(N, A, globalx, (block*MULSIDE + localy));
right[localy][localx] = get(N, B, block*MULSIDE + localx, globaly);
__syncthreads();
for(int k = 0; k < MULSIDE; k++){
result += left[localx][k] * right[localy][k];
}
__syncthreads();
}
set(N, C, globalx, globaly, result);
}
__global__ void add_kernel(int N, UINT* A, UINT* B, UINT* C){
int index = blockIdx.x * ADDSIDE + threadIdx.x;
if (index < N)
C[index] = A[index] + B[index];
}
void rand_gen(UINT c, int N, UINT* A) {
UINT x = 2, n = N*N;
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
x = (x * x + c + i + j)%n;
A[i*N + j] = x;
}
}
}
void print_matrix(int N, UINT* A) {
for (int i = 0; i < N; i++) {
fprintf(stderr, "[");
for (int j = 0; j < N; j++)
fprintf(stderr, " %u", A[i*N + j]);
fprintf(stderr, " ]\n");
}
}
UINT signature(int N, UINT* A) {
UINT h = 0;
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++)
h = (h + A[i*N + j]) * 2654435761LU;
}
return h;
}
UINT hostIN[TOPM][MAXN*MAXN], hostTMP[MAXN*MAXN];
int main() {
int M, N, S[TOPM], s;
s = scanf("%d %d", &M, &N);
for (int i = 0; i < M; i++) {
s = scanf("%d", &S[i]);
rand_gen(S[i], N, hostIN[i]);
}
UINT *IN[TOPM];
UINT *TMP[TOPM];
size_t matsz = sizeof(UINT) * N * N;
for (int i = 0; i < M; i++){
gpuErrchk(cudaMalloc(&IN[i], matsz));
gpuErrchk(cudaMemcpy(IN[i], hostIN[i], matsz, cudaMemcpyHostToDevice));
}
for (int i = 0; i < TOPM; i++)
gpuErrchk(cudaMalloc(&TMP[i], matsz));
int Q;
char E[26];
s = scanf("%d", &Q);
for (int i = 0; i < Q; i++) {
s = scanf("%s", E);
UINT *addbuf = NULL, *mulbuf = NULL, *r_operand;
for (int j = 0, tmp_id = 0; j < 27; j++){
// fprintf(stderr, "j=%d, \'%c\', tmp=%d\n", j, E[j]=='\0' ? '#' : E[j], tmp_id);
if(j < 26 && E[j] != '\0' && E[j] != '+'){
// before +
if (mulbuf == NULL){
// first operand
mulbuf = IN[E[j]-'A'];
}
else{
// right operand
r_operand = IN[E[j]-'A'];
mul_kernel <<< dim3(MULBLK,MULBLK), dim3(MULSIDE,MULSIDE) >>>
(N, mulbuf, r_operand, TMP[tmp_id]);
mulbuf = TMP[tmp_id++];
}
}
else if(addbuf == NULL){
// first segment e.g. "ABCD"+EF...
addbuf = mulbuf;
mulbuf = NULL;
}
else{
// new segment e.g. ABCD+"EF"...
add_kernel <<< ADDBLK, ADDSIDE >>> (N*N, addbuf, mulbuf, TMP[tmp_id]);
addbuf = TMP[tmp_id++];
mulbuf = NULL;
}
if (j >= 26 || E[j] == '\0')
break;
gpuErrchk(cudaPeekAtLastError());
gpuErrchk(cudaDeviceSynchronize());
}
gpuErrchk(cudaMemcpy(hostTMP, addbuf, matsz, cudaMemcpyDeviceToHost));
printf("%u\n", signature(N, hostTMP));
}
assert(s>0);
for (int i = 0; i < M; i++){
gpuErrchk(cudaFree(IN[i]));
}
for (int i = 0; i < TOPM; i++){
gpuErrchk(cudaFree(TMP[i]));
}
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdint.h>
#include <assert.h>
// #define DEBUG
#define UINT uint32_t
#define TOPM 26
#define MAXN 1024
#define MULSIDE 16 // each block has size SIDE x SIDE
#define MULBLK (MAXN / MULSIDE) // divide C into BLK x BLK blocks
#define ADDSIDE 256
#define ADDBLK (MAXN*(MAXN / ADDSIDE))
// function for debugging.
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__device__ static inline UINT get(int N, UINT* M, int x, int y){
return (x < N && y < N) ? M[x*N + y] : 0;
}
__device__ static inline void set(int N, UINT* M, int x, int y, UINT v){
if (x < N && y < N)
M[x*N + y] = v;
return;
}
__global__ void mul_kernel(int N, UINT* A, UINT* B, UINT* C){
__shared__ UINT left[MULSIDE][MULSIDE];
__shared__ UINT right[MULSIDE][MULSIDE];
int localx = threadIdx.x;
int localy = threadIdx.y;
int globalx = blockIdx.x * MULSIDE + localx;//x for C
int globaly = blockIdx.y * MULSIDE + localy;//y for C
UINT result = 0;
for(int block = 0; block < MULBLK; block++){
left[localx][localy] = get(N, A, globalx, (block*MULSIDE + localy));
right[localy][localx] = get(N, B, block*MULSIDE + localx, globaly);
__syncthreads();
for(int k = 0; k < MULSIDE; k++){
result += left[localx][k] * right[localy][k];
}
__syncthreads();
}
set(N, C, globalx, globaly, result);
}
__global__ void add_kernel(int N, UINT* A, UINT* B, UINT* C){
int index = blockIdx.x * ADDSIDE + threadIdx.x;
if (index < N)
C[index] = A[index] + B[index];
}
void rand_gen(UINT c, int N, UINT* A) {
UINT x = 2, n = N*N;
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
x = (x * x + c + i + j)%n;
A[i*N + j] = x;
}
}
}
void print_matrix(int N, UINT* A) {
for (int i = 0; i < N; i++) {
fprintf(stderr, "[");
for (int j = 0; j < N; j++)
fprintf(stderr, " %u", A[i*N + j]);
fprintf(stderr, " ]\n");
}
}
UINT signature(int N, UINT* A) {
UINT h = 0;
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++)
h = (h + A[i*N + j]) * 2654435761LU;
}
return h;
}
UINT hostIN[TOPM][MAXN*MAXN], hostTMP[MAXN*MAXN];
int main() {
int M, N, S[TOPM], s;
s = scanf("%d %d", &M, &N);
for (int i = 0; i < M; i++) {
s = scanf("%d", &S[i]);
rand_gen(S[i], N, hostIN[i]);
}
UINT *IN[TOPM];
UINT *TMP[TOPM];
size_t matsz = sizeof(UINT) * N * N;
for (int i = 0; i < M; i++){
gpuErrchk(hipMalloc(&IN[i], matsz));
gpuErrchk(hipMemcpy(IN[i], hostIN[i], matsz, hipMemcpyHostToDevice));
}
for (int i = 0; i < TOPM; i++)
gpuErrchk(hipMalloc(&TMP[i], matsz));
int Q;
char E[26];
s = scanf("%d", &Q);
for (int i = 0; i < Q; i++) {
s = scanf("%s", E);
UINT *addbuf = NULL, *mulbuf = NULL, *r_operand;
for (int j = 0, tmp_id = 0; j < 27; j++){
// fprintf(stderr, "j=%d, \'%c\', tmp=%d\n", j, E[j]=='\0' ? '#' : E[j], tmp_id);
if(j < 26 && E[j] != '\0' && E[j] != '+'){
// before +
if (mulbuf == NULL){
// first operand
mulbuf = IN[E[j]-'A'];
}
else{
// right operand
r_operand = IN[E[j]-'A'];
mul_kernel <<< dim3(MULBLK,MULBLK), dim3(MULSIDE,MULSIDE) >>>
(N, mulbuf, r_operand, TMP[tmp_id]);
mulbuf = TMP[tmp_id++];
}
}
else if(addbuf == NULL){
// first segment e.g. "ABCD"+EF...
addbuf = mulbuf;
mulbuf = NULL;
}
else{
// new segment e.g. ABCD+"EF"...
add_kernel <<< ADDBLK, ADDSIDE >>> (N*N, addbuf, mulbuf, TMP[tmp_id]);
addbuf = TMP[tmp_id++];
mulbuf = NULL;
}
if (j >= 26 || E[j] == '\0')
break;
gpuErrchk(hipPeekAtLastError());
gpuErrchk(hipDeviceSynchronize());
}
gpuErrchk(hipMemcpy(hostTMP, addbuf, matsz, hipMemcpyDeviceToHost));
printf("%u\n", signature(N, hostTMP));
}
assert(s>0);
for (int i = 0; i < M; i++){
gpuErrchk(hipFree(IN[i]));
}
for (int i = 0; i < TOPM; i++){
gpuErrchk(hipFree(TMP[i]));
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdint.h>
#include <assert.h>
// #define DEBUG
#define UINT uint32_t
#define TOPM 26
#define MAXN 1024
#define MULSIDE 16 // each block has size SIDE x SIDE
#define MULBLK (MAXN / MULSIDE) // divide C into BLK x BLK blocks
#define ADDSIDE 256
#define ADDBLK (MAXN*(MAXN / ADDSIDE))
// function for debugging.
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__device__ static inline UINT get(int N, UINT* M, int x, int y){
return (x < N && y < N) ? M[x*N + y] : 0;
}
__device__ static inline void set(int N, UINT* M, int x, int y, UINT v){
if (x < N && y < N)
M[x*N + y] = v;
return;
}
__global__ void mul_kernel(int N, UINT* A, UINT* B, UINT* C){
__shared__ UINT left[MULSIDE][MULSIDE];
__shared__ UINT right[MULSIDE][MULSIDE];
int localx = threadIdx.x;
int localy = threadIdx.y;
int globalx = blockIdx.x * MULSIDE + localx;//x for C
int globaly = blockIdx.y * MULSIDE + localy;//y for C
UINT result = 0;
for(int block = 0; block < MULBLK; block++){
left[localx][localy] = get(N, A, globalx, (block*MULSIDE + localy));
right[localy][localx] = get(N, B, block*MULSIDE + localx, globaly);
__syncthreads();
for(int k = 0; k < MULSIDE; k++){
result += left[localx][k] * right[localy][k];
}
__syncthreads();
}
set(N, C, globalx, globaly, result);
}
__global__ void add_kernel(int N, UINT* A, UINT* B, UINT* C){
int index = blockIdx.x * ADDSIDE + threadIdx.x;
if (index < N)
C[index] = A[index] + B[index];
}
void rand_gen(UINT c, int N, UINT* A) {
UINT x = 2, n = N*N;
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
x = (x * x + c + i + j)%n;
A[i*N + j] = x;
}
}
}
void print_matrix(int N, UINT* A) {
for (int i = 0; i < N; i++) {
fprintf(stderr, "[");
for (int j = 0; j < N; j++)
fprintf(stderr, " %u", A[i*N + j]);
fprintf(stderr, " ]\n");
}
}
UINT signature(int N, UINT* A) {
UINT h = 0;
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++)
h = (h + A[i*N + j]) * 2654435761LU;
}
return h;
}
UINT hostIN[TOPM][MAXN*MAXN], hostTMP[MAXN*MAXN];
int main() {
int M, N, S[TOPM], s;
s = scanf("%d %d", &M, &N);
for (int i = 0; i < M; i++) {
s = scanf("%d", &S[i]);
rand_gen(S[i], N, hostIN[i]);
}
UINT *IN[TOPM];
UINT *TMP[TOPM];
size_t matsz = sizeof(UINT) * N * N;
for (int i = 0; i < M; i++){
gpuErrchk(hipMalloc(&IN[i], matsz));
gpuErrchk(hipMemcpy(IN[i], hostIN[i], matsz, hipMemcpyHostToDevice));
}
for (int i = 0; i < TOPM; i++)
gpuErrchk(hipMalloc(&TMP[i], matsz));
int Q;
char E[26];
s = scanf("%d", &Q);
for (int i = 0; i < Q; i++) {
s = scanf("%s", E);
UINT *addbuf = NULL, *mulbuf = NULL, *r_operand;
for (int j = 0, tmp_id = 0; j < 27; j++){
// fprintf(stderr, "j=%d, \'%c\', tmp=%d\n", j, E[j]=='\0' ? '#' : E[j], tmp_id);
if(j < 26 && E[j] != '\0' && E[j] != '+'){
// before +
if (mulbuf == NULL){
// first operand
mulbuf = IN[E[j]-'A'];
}
else{
// right operand
r_operand = IN[E[j]-'A'];
mul_kernel <<< dim3(MULBLK,MULBLK), dim3(MULSIDE,MULSIDE) >>>
(N, mulbuf, r_operand, TMP[tmp_id]);
mulbuf = TMP[tmp_id++];
}
}
else if(addbuf == NULL){
// first segment e.g. "ABCD"+EF...
addbuf = mulbuf;
mulbuf = NULL;
}
else{
// new segment e.g. ABCD+"EF"...
add_kernel <<< ADDBLK, ADDSIDE >>> (N*N, addbuf, mulbuf, TMP[tmp_id]);
addbuf = TMP[tmp_id++];
mulbuf = NULL;
}
if (j >= 26 || E[j] == '\0')
break;
gpuErrchk(hipPeekAtLastError());
gpuErrchk(hipDeviceSynchronize());
}
gpuErrchk(hipMemcpy(hostTMP, addbuf, matsz, hipMemcpyDeviceToHost));
printf("%u\n", signature(N, hostTMP));
}
assert(s>0);
for (int i = 0; i < M; i++){
gpuErrchk(hipFree(IN[i]));
}
for (int i = 0; i < TOPM; i++){
gpuErrchk(hipFree(TMP[i]));
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10mul_kerneliPjS_S_
.globl _Z10mul_kerneliPjS_S_
.p2align 8
.type _Z10mul_kerneliPjS_S_,@function
_Z10mul_kerneliPjS_S_:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v4, 0x3ff, v0
v_bfe_u32 v5, v0, 10, 10
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshl_add_u32 v3, s14, 4, v4
v_lshlrev_b32_e32 v6, 6, v4
v_lshl_add_u32 v0, s15, 4, v5
v_lshl_add_u32 v7, v5, 6, 0x400
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v8, v5, 2, v6
v_lshl_add_u32 v10, v4, 2, v7
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v9, v3, s8
v_cmp_gt_i32_e32 vcc_lo, s8, v3
v_cmp_gt_i32_e64 s2, s8, v0
.LBB0_1:
s_lshl_b32 s10, s9, 4
v_mov_b32_e32 v2, 0
v_dual_mov_b32 v11, 0 :: v_dual_add_nc_u32 v12, s10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s3, s8, v12
s_and_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s11, s3
s_cbranch_execz .LBB0_3
v_add_nc_u32_e32 v11, v12, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v11, s3, s4, v11
v_add_co_ci_u32_e64 v12, s3, s5, v12, s3
global_load_b32 v11, v[11:12], off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s11
v_add_nc_u32_e32 v12, s10, v4
s_waitcnt vmcnt(0)
ds_store_b32 v8, v11
v_cmp_gt_i32_e64 s3, s8, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, s3
s_and_saveexec_b32 s10, s3
s_cbranch_execz .LBB0_5
v_mad_u64_u32 v[13:14], null, v12, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[11:12], 2, v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v11, s3, s6, v11
v_add_co_ci_u32_e64 v12, s3, s7, v12, s3
global_load_b32 v2, v[11:12], off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s10
s_mov_b32 s3, 0
s_waitcnt vmcnt(0)
ds_store_b32 v10, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_6:
v_add_nc_u32_e32 v2, s3, v6
v_add_nc_u32_e32 v11, s3, v7
s_add_i32 s3, s3, 4
ds_load_b32 v12, v2
ds_load_b32 v13, v11
v_mov_b32_e32 v11, v1
s_cmp_eq_u32 s3, 64
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v13, v12, v[11:12]
s_cbranch_scc0 .LBB0_6
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, 64
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_1
v_max_i32_e32 v2, v3, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v2
s_cbranch_execz .LBB0_10
s_load_b64 s[0:1], s[0:1], 0x18
v_mad_u64_u32 v[4:5], null, v3, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[2:3], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10mul_kerneliPjS_S_
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10mul_kerneliPjS_S_, .Lfunc_end0-_Z10mul_kerneliPjS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10add_kerneliPjS_S_
.globl _Z10add_kerneliPjS_S_
.p2align 8
.type _Z10add_kerneliPjS_S_,@function
_Z10add_kerneliPjS_S_:
s_load_b32 s2, s[0:1], 0x0
v_lshl_add_u32 v0, s15, 8, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v1, 31, v0
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10add_kerneliPjS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10add_kerneliPjS_S_, .Lfunc_end1-_Z10add_kerneliPjS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10mul_kerneliPjS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10mul_kerneliPjS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10add_kerneliPjS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10add_kerneliPjS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdint.h>
#include <assert.h>
// #define DEBUG
#define UINT uint32_t
#define TOPM 26
#define MAXN 1024
#define MULSIDE 16 // each block has size SIDE x SIDE
#define MULBLK (MAXN / MULSIDE) // divide C into BLK x BLK blocks
#define ADDSIDE 256
#define ADDBLK (MAXN*(MAXN / ADDSIDE))
// function for debugging.
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__device__ static inline UINT get(int N, UINT* M, int x, int y){
return (x < N && y < N) ? M[x*N + y] : 0;
}
__device__ static inline void set(int N, UINT* M, int x, int y, UINT v){
if (x < N && y < N)
M[x*N + y] = v;
return;
}
__global__ void mul_kernel(int N, UINT* A, UINT* B, UINT* C){
__shared__ UINT left[MULSIDE][MULSIDE];
__shared__ UINT right[MULSIDE][MULSIDE];
int localx = threadIdx.x;
int localy = threadIdx.y;
int globalx = blockIdx.x * MULSIDE + localx;//x for C
int globaly = blockIdx.y * MULSIDE + localy;//y for C
UINT result = 0;
for(int block = 0; block < MULBLK; block++){
left[localx][localy] = get(N, A, globalx, (block*MULSIDE + localy));
right[localy][localx] = get(N, B, block*MULSIDE + localx, globaly);
__syncthreads();
for(int k = 0; k < MULSIDE; k++){
result += left[localx][k] * right[localy][k];
}
__syncthreads();
}
set(N, C, globalx, globaly, result);
}
__global__ void add_kernel(int N, UINT* A, UINT* B, UINT* C){
int index = blockIdx.x * ADDSIDE + threadIdx.x;
if (index < N)
C[index] = A[index] + B[index];
}
void rand_gen(UINT c, int N, UINT* A) {
UINT x = 2, n = N*N;
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
x = (x * x + c + i + j)%n;
A[i*N + j] = x;
}
}
}
void print_matrix(int N, UINT* A) {
for (int i = 0; i < N; i++) {
fprintf(stderr, "[");
for (int j = 0; j < N; j++)
fprintf(stderr, " %u", A[i*N + j]);
fprintf(stderr, " ]\n");
}
}
UINT signature(int N, UINT* A) {
UINT h = 0;
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++)
h = (h + A[i*N + j]) * 2654435761LU;
}
return h;
}
UINT hostIN[TOPM][MAXN*MAXN], hostTMP[MAXN*MAXN];
int main() {
int M, N, S[TOPM], s;
s = scanf("%d %d", &M, &N);
for (int i = 0; i < M; i++) {
s = scanf("%d", &S[i]);
rand_gen(S[i], N, hostIN[i]);
}
UINT *IN[TOPM];
UINT *TMP[TOPM];
size_t matsz = sizeof(UINT) * N * N;
for (int i = 0; i < M; i++){
gpuErrchk(hipMalloc(&IN[i], matsz));
gpuErrchk(hipMemcpy(IN[i], hostIN[i], matsz, hipMemcpyHostToDevice));
}
for (int i = 0; i < TOPM; i++)
gpuErrchk(hipMalloc(&TMP[i], matsz));
int Q;
char E[26];
s = scanf("%d", &Q);
for (int i = 0; i < Q; i++) {
s = scanf("%s", E);
UINT *addbuf = NULL, *mulbuf = NULL, *r_operand;
for (int j = 0, tmp_id = 0; j < 27; j++){
// fprintf(stderr, "j=%d, \'%c\', tmp=%d\n", j, E[j]=='\0' ? '#' : E[j], tmp_id);
if(j < 26 && E[j] != '\0' && E[j] != '+'){
// before +
if (mulbuf == NULL){
// first operand
mulbuf = IN[E[j]-'A'];
}
else{
// right operand
r_operand = IN[E[j]-'A'];
mul_kernel <<< dim3(MULBLK,MULBLK), dim3(MULSIDE,MULSIDE) >>>
(N, mulbuf, r_operand, TMP[tmp_id]);
mulbuf = TMP[tmp_id++];
}
}
else if(addbuf == NULL){
// first segment e.g. "ABCD"+EF...
addbuf = mulbuf;
mulbuf = NULL;
}
else{
// new segment e.g. ABCD+"EF"...
add_kernel <<< ADDBLK, ADDSIDE >>> (N*N, addbuf, mulbuf, TMP[tmp_id]);
addbuf = TMP[tmp_id++];
mulbuf = NULL;
}
if (j >= 26 || E[j] == '\0')
break;
gpuErrchk(hipPeekAtLastError());
gpuErrchk(hipDeviceSynchronize());
}
gpuErrchk(hipMemcpy(hostTMP, addbuf, matsz, hipMemcpyDeviceToHost));
printf("%u\n", signature(N, hostTMP));
}
assert(s>0);
for (int i = 0; i < M; i++){
gpuErrchk(hipFree(IN[i]));
}
for (int i = 0; i < TOPM; i++){
gpuErrchk(hipFree(TMP[i]));
}
return 0;
} | .text
.file "main.hip"
.globl _Z25__device_stub__mul_kerneliPjS_S_ # -- Begin function _Z25__device_stub__mul_kerneliPjS_S_
.p2align 4, 0x90
.type _Z25__device_stub__mul_kerneliPjS_S_,@function
_Z25__device_stub__mul_kerneliPjS_S_: # @_Z25__device_stub__mul_kerneliPjS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10mul_kerneliPjS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__mul_kerneliPjS_S_, .Lfunc_end0-_Z25__device_stub__mul_kerneliPjS_S_
.cfi_endproc
# -- End function
.globl _Z25__device_stub__add_kerneliPjS_S_ # -- Begin function _Z25__device_stub__add_kerneliPjS_S_
.p2align 4, 0x90
.type _Z25__device_stub__add_kerneliPjS_S_,@function
_Z25__device_stub__add_kerneliPjS_S_: # @_Z25__device_stub__add_kerneliPjS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10add_kerneliPjS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z25__device_stub__add_kerneliPjS_S_, .Lfunc_end1-_Z25__device_stub__add_kerneliPjS_S_
.cfi_endproc
# -- End function
.globl _Z8rand_genjiPj # -- Begin function _Z8rand_genjiPj
.p2align 4, 0x90
.type _Z8rand_genjiPj,@function
_Z8rand_genjiPj: # @_Z8rand_genjiPj
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_6
# %bb.1: # %.preheader.lr.ph
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdx, %rcx
movl %esi, %r8d
imull %esi, %r8d
movl %esi, %r9d
movl %edi, %edi
movl $2, %edx
xorl %r10d, %r10d
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl %r10d, %eax
leaq (%rcx,%rax,4), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
imull %edx, %edx
addl %edi, %edx
addl %r14d, %edx
movl %edx, %eax
xorl %edx, %edx
divl %r8d
movl %edx, (%rbx,%r14,4)
incq %r14
cmpq %r14, %r9
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r11
addl %esi, %r10d
incq %rdi
cmpq %r9, %r11
jne .LBB2_2
# %bb.5:
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB2_6: # %._crit_edge25
retq
.Lfunc_end2:
.size _Z8rand_genjiPj, .Lfunc_end2-_Z8rand_genjiPj
.cfi_endproc
# -- End function
.globl _Z12print_matrixiPj # -- Begin function _Z12print_matrixiPj
.p2align 4, 0x90
.type _Z12print_matrixiPj,@function
_Z12print_matrixiPj: # @_Z12print_matrixiPj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, (%rsp) # 8-byte Spill
testl %edi, %edi
jle .LBB3_5
# %bb.1: # %.lr.ph14
movl %edi, %ebp
movl %edi, %r14d
xorl %r15d, %r15d
xorl %r12d, %r12d
.LBB3_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
movl %r15d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r13
movq stderr(%rip), %rsi
movl $91, %edi
callq fputc@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movq stderr(%rip), %rdi
movl (%r13,%rbx,4), %edx
movl $.L.str.1, %esi
xorl %eax, %eax
callq fprintf
incq %rbx
cmpq %rbx, %r14
jne .LBB3_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $3, %esi
movl $1, %edx
callq fwrite@PLT
incq %r12
addl %ebp, %r15d
cmpq %r14, %r12
jne .LBB3_2
.LBB3_5: # %._crit_edge15
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z12print_matrixiPj, .Lfunc_end3-_Z12print_matrixiPj
.cfi_endproc
# -- End function
.globl _Z9signatureiPj # -- Begin function _Z9signatureiPj
.p2align 4, 0x90
.type _Z9signatureiPj,@function
_Z9signatureiPj: # @_Z9signatureiPj
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB4_1
# %bb.2: # %.preheader.lr.ph
movl %edi, %ecx
xorl %edx, %edx
xorl %r8d, %r8d
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
movl %edx, %r9d
leaq (%rsi,%r9,4), %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB4_4: # Parent Loop BB4_3 Depth=1
# => This Inner Loop Header: Depth=2
addl (%r9,%r10,4), %eax
imull $-1640531535, %eax, %eax # imm = 0x9E3779B1
incq %r10
cmpq %r10, %rcx
jne .LBB4_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB4_3 Depth=1
incq %r8
addl %edi, %edx
cmpq %rcx, %r8
jne .LBB4_3
# %bb.6: # %._crit_edge18
retq
.LBB4_1:
xorl %eax, %eax
retq
.Lfunc_end4:
.size _Z9signatureiPj, .Lfunc_end4-_Z9signatureiPj
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $712, %rsp # imm = 0x2C8
.cfi_def_cfa_offset 768
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsp, %rsi
leaq 4(%rsp), %rdx
movl $.L.str.3, %edi
xorl %eax, %eax
callq __isoc23_scanf
cmpl $0, (%rsp)
jle .LBB5_8
# %bb.1: # %.lr.ph.preheader
movl $hostIN, %ebx
xorl %r14d, %r14d
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_7: # %_Z8rand_genjiPj.exit
# in Loop: Header=BB5_2 Depth=1
incq %r14
movslq (%rsp), %rax
addq $4194304, %rbx # imm = 0x400000
cmpq %rax, %r14
jge .LBB5_8
.LBB5_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB5_4 Depth 2
# Child Loop BB5_5 Depth 3
leaq (%rsp,%r14,4), %rsi
addq $384, %rsi # imm = 0x180
movl $.L.str.4, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 4(%rsp), %ecx
testl %ecx, %ecx
jle .LBB5_7
# %bb.3: # %.preheader.lr.ph.i
# in Loop: Header=BB5_2 Depth=1
movl 384(%rsp,%r14,4), %esi
movl %ecx, %edi
imull %ecx, %edi
movl $2, %edx
xorl %r8d, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB5_4: # %.preheader.i
# Parent Loop BB5_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB5_5 Depth 3
movl %r8d, %eax
leaq (%rbx,%rax,4), %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB5_5: # Parent Loop BB5_2 Depth=1
# Parent Loop BB5_4 Depth=2
# => This Inner Loop Header: Depth=3
imull %edx, %edx
addl %esi, %edx
addl %r11d, %edx
movl %edx, %eax
xorl %edx, %edx
divl %edi
movl %edx, (%r10,%r11,4)
incq %r11
cmpq %r11, %rcx
jne .LBB5_5
# %bb.6: # %._crit_edge.i
# in Loop: Header=BB5_4 Depth=2
incq %r9
addl %ecx, %r8d
incq %rsi
cmpq %rcx, %r9
jne .LBB5_4
jmp .LBB5_7
.LBB5_8: # %._crit_edge
movslq 4(%rsp), %r12
imulq %r12, %r12
shlq $2, %r12
cmpl $0, (%rsp)
jle .LBB5_27
# %bb.9: # %.lr.ph120.preheader
movl $hostIN, %r14d
leaq 496(%rsp), %r15
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB5_11: # %.lr.ph120
# =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB5_12
# %bb.14: # %_Z9gpuAssert10hipError_tPKcib.exit
# in Loop: Header=BB5_11 Depth=1
movq (%r15), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_15
# %bb.10: # in Loop: Header=BB5_11 Depth=1
incq %rbx
movslq (%rsp), %rax
addq $4194304, %r14 # imm = 0x400000
addq $8, %r15
cmpq %rax, %rbx
jl .LBB5_11
.LBB5_27: # %_Z9gpuAssert10hipError_tPKcib.exit71.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB5_28: # %_Z9gpuAssert10hipError_tPKcib.exit71
# =>This Inner Loop Header: Depth=1
leaq (%rsp,%rbx), %rdi
addq $176, %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB5_29
# %bb.16: # in Loop: Header=BB5_28 Depth=1
addq $8, %rbx
cmpq $208, %rbx
jne .LBB5_28
# %bb.17:
leaq 12(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq __isoc23_scanf
cmpl $0, 12(%rsp)
jle .LBB5_30
# %bb.18: # %.lr.ph130
movabsq $4294967552, %rax # imm = 0x100000100
addq $3840, %rax # imm = 0xF00
movq %rax, 136(%rsp) # 8-byte Spill
xorl %eax, %eax
movq %r12, 128(%rsp) # 8-byte Spill
jmp .LBB5_19
.p2align 4, 0x90
.LBB5_46: # in Loop: Header=BB5_19 Depth=1
xorl %esi, %esi
.LBB5_51: # %_Z9signatureiPj.exit
# in Loop: Header=BB5_19 Depth=1
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 92(%rsp), %eax # 4-byte Reload
incl %eax
cmpl 12(%rsp), %eax
jge .LBB5_30
.LBB5_19: # =>This Loop Header: Depth=1
# Child Loop BB5_20 Depth 2
# Child Loop BB5_48 Depth 2
# Child Loop BB5_49 Depth 3
movl %eax, 92(%rsp) # 4-byte Spill
xorl %ebx, %ebx
movl $.L.str.6, %edi
leaq 144(%rsp), %rsi
xorl %eax, %eax
callq __isoc23_scanf
xorl %ebp, %ebp
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_20: # Parent Loop BB5_19 Depth=1
# => This Inner Loop Header: Depth=2
cmpq $26, %rbx
je .LBB5_32
# %bb.21: # in Loop: Header=BB5_20 Depth=2
movzbl 144(%rsp,%rbx), %eax
testl %eax, %eax
je .LBB5_32
# %bb.22: # in Loop: Header=BB5_20 Depth=2
cmpl $43, %eax
jne .LBB5_23
.p2align 4, 0x90
.LBB5_32: # in Loop: Header=BB5_20 Depth=2
testq %rbp, %rbp
je .LBB5_33
# %bb.34: # in Loop: Header=BB5_20 Depth=2
movq 136(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_36
# %bb.35: # in Loop: Header=BB5_20 Depth=2
movl 4(%rsp), %eax
imull %eax, %eax
movslq %r14d, %rcx
movq 176(%rsp,%rcx,8), %rcx
movl %eax, 8(%rsp)
movq %rbp, 80(%rsp)
movq %r15, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z10add_kerneliPjS_S_, %edi
leaq 96(%rsp), %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_36: # in Loop: Header=BB5_20 Depth=2
movslq %r14d, %rax
incl %r14d
movq 176(%rsp,%rax,8), %rbp
xorl %r12d, %r12d
jmp .LBB5_37
.p2align 4, 0x90
.LBB5_33: # in Loop: Header=BB5_20 Depth=2
xorl %r12d, %r12d
movq %r15, %rbp
jmp .LBB5_37
.LBB5_23: # in Loop: Header=BB5_20 Depth=2
movsbq %al, %rax
movq -24(%rsp,%rax,8), %r12
testq %r15, %r15
je .LBB5_37
# %bb.24: # in Loop: Header=BB5_20 Depth=2
movabsq $274877907008, %rdi # imm = 0x4000000040
movl $1, %esi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
movslq %r14d, %r13
testl %eax, %eax
jne .LBB5_26
# %bb.25: # in Loop: Header=BB5_20 Depth=2
movl 4(%rsp), %eax
movq 176(%rsp,%r13,8), %rcx
movl %eax, 8(%rsp)
movq %r15, 80(%rsp)
movq %r12, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z10mul_kerneliPjS_S_, %edi
leaq 96(%rsp), %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_26: # in Loop: Header=BB5_20 Depth=2
leal 1(%r13), %r14d
movq 176(%rsp,%r13,8), %r12
.p2align 4, 0x90
.LBB5_37: # in Loop: Header=BB5_20 Depth=2
cmpq $26, %rbx
je .LBB5_43
# %bb.38: # in Loop: Header=BB5_20 Depth=2
cmpb $0, 144(%rsp,%rbx)
je .LBB5_43
# %bb.39: # in Loop: Header=BB5_20 Depth=2
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB5_40
# %bb.41: # %_Z9gpuAssert10hipError_tPKcib.exit79
# in Loop: Header=BB5_20 Depth=2
callq hipDeviceSynchronize
incq %rbx
movq %r12, %r15
testl %eax, %eax
je .LBB5_20
jmp .LBB5_42
.p2align 4, 0x90
.LBB5_43: # in Loop: Header=BB5_19 Depth=1
movl $hostTMP, %edi
movq %rbp, %rsi
movq 128(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_44
# %bb.45: # %_Z9gpuAssert10hipError_tPKcib.exit83
# in Loop: Header=BB5_19 Depth=1
movl 4(%rsp), %eax
testl %eax, %eax
jle .LBB5_46
# %bb.47: # %.preheader.lr.ph.i84
# in Loop: Header=BB5_19 Depth=1
xorl %edx, %edx
xorl %ecx, %ecx
xorl %esi, %esi
.p2align 4, 0x90
.LBB5_48: # %.preheader.i85
# Parent Loop BB5_19 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB5_49 Depth 3
movl %edx, %edx
xorl %edi, %edi
.p2align 4, 0x90
.LBB5_49: # Parent Loop BB5_19 Depth=1
# Parent Loop BB5_48 Depth=2
# => This Inner Loop Header: Depth=3
leaq (,%rdx,4), %r8
addl hostTMP(%r8,%rdi,4), %esi
imull $-1640531535, %esi, %esi # imm = 0x9E3779B1
incq %rdi
cmpq %rdi, %rax
jne .LBB5_49
# %bb.50: # %._crit_edge.i90
# in Loop: Header=BB5_48 Depth=2
incq %rcx
addl %eax, %edx
cmpq %rax, %rcx
jne .LBB5_48
jmp .LBB5_51
.LBB5_30: # %.preheader104
cmpl $0, (%rsp)
jle .LBB5_57
# %bb.31: # %_Z9gpuAssert10hipError_tPKcib.exit92.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB5_53: # %_Z9gpuAssert10hipError_tPKcib.exit92
# =>This Inner Loop Header: Depth=1
movq 496(%rsp,%rbx,8), %rdi
callq hipFree
testl %eax, %eax
jne .LBB5_54
# %bb.52: # in Loop: Header=BB5_53 Depth=1
incq %rbx
movslq (%rsp), %rax
cmpq %rax, %rbx
jl .LBB5_53
.LBB5_57: # %_Z9gpuAssert10hipError_tPKcib.exit94.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB5_58: # %_Z9gpuAssert10hipError_tPKcib.exit94
# =>This Inner Loop Header: Depth=1
movq 176(%rsp,%rbx,8), %rdi
callq hipFree
testl %eax, %eax
jne .LBB5_59
# %bb.55: # in Loop: Header=BB5_58 Depth=1
incq %rbx
cmpq $26, %rbx
jne .LBB5_58
# %bb.56:
xorl %eax, %eax
addq $712, %rsp # imm = 0x2C8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_42:
.cfi_def_cfa_offset 768
movl %eax, %r13d
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $148, %r8d
xorl %eax, %eax
callq fprintf
movl %r13d, %edi
callq exit
.LBB5_40:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $147, %r8d
.LBB5_13:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.LBB5_29:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $108, %r8d
jmp .LBB5_13
.LBB5_59:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $159, %r8d
jmp .LBB5_13
.LBB5_12:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $104, %r8d
jmp .LBB5_13
.LBB5_15:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $105, %r8d
jmp .LBB5_13
.LBB5_54:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $156, %r8d
jmp .LBB5_13
.LBB5_44:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $150, %r8d
jmp .LBB5_13
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10mul_kerneliPjS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10add_kerneliPjS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10mul_kerneliPjS_S_,@object # @_Z10mul_kerneliPjS_S_
.section .rodata,"a",@progbits
.globl _Z10mul_kerneliPjS_S_
.p2align 3, 0x0
_Z10mul_kerneliPjS_S_:
.quad _Z25__device_stub__mul_kerneliPjS_S_
.size _Z10mul_kerneliPjS_S_, 8
.type _Z10add_kerneliPjS_S_,@object # @_Z10add_kerneliPjS_S_
.globl _Z10add_kerneliPjS_S_
.p2align 3, 0x0
_Z10add_kerneliPjS_S_:
.quad _Z25__device_stub__add_kerneliPjS_S_
.size _Z10add_kerneliPjS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz " %u"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " ]\n"
.size .L.str.2, 4
.type hostIN,@object # @hostIN
.bss
.globl hostIN
.p2align 4, 0x0
hostIN:
.zero 109051904
.size hostIN, 109051904
.type hostTMP,@object # @hostTMP
.globl hostTMP
.p2align 4, 0x0
hostTMP:
.zero 4194304
.size hostTMP, 4194304
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "%d %d"
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/George0828Zhang/cuda-practice/main/AdvancedMatrixCalculator/main.hip"
.size .L.str.5, 126
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%s"
.size .L.str.6, 3
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%u\n"
.size .L.str.7, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.8, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10mul_kerneliPjS_S_"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10add_kerneliPjS_S_"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__mul_kerneliPjS_S_
.addrsig_sym _Z25__device_stub__add_kerneliPjS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10mul_kerneliPjS_S_
.addrsig_sym _Z10add_kerneliPjS_S_
.addrsig_sym hostIN
.addrsig_sym hostTMP
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10add_kerneliPjS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ LEA R6, R6, R3, 0x8 ; /* 0x0000000306067211 */
/* 0x001fc800078e40ff */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10mul_kerneliPjS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R23, SR_TID.X ; /* 0x0000000000177919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R20, RZ ; /* 0x000000ff00147202 */
/* 0x000fe20000000f00 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0070*/ S2R R22, SR_TID.Y ; /* 0x0000000000167919 */
/* 0x000ea80000002200 */
/*0080*/ S2R R28, SR_CTAID.Y ; /* 0x00000000001c7919 */
/* 0x000ee20000002600 */
/*0090*/ SHF.L.U32 R27, R23.reuse, 0x6, RZ ; /* 0x00000006171b7819 */
/* 0x041fe400000006ff */
/*00a0*/ LEA R29, R0, R23, 0x4 ; /* 0x00000017001d7211 */
/* 0x002fe200078e20ff */
/*00b0*/ IMAD R21, R23, c[0x0][0x160], R22 ; /* 0x0000580017157a24 */
/* 0x004fe200078e0216 */
/*00c0*/ LEA R26, R22, 0x400, 0x6 ; /* 0x00000400161a7811 */
/* 0x000fc600078e30ff */
/*00d0*/ IMAD R2, R29.reuse, c[0x0][0x160], R22.reuse ; /* 0x000058001d027a24 */
/* 0x140fe200078e0216 */
/*00e0*/ ISETP.GE.AND P1, PT, R29, c[0x0][0x160], PT ; /* 0x000058001d007a0c */
/* 0x000fe40003f26270 */
/*00f0*/ LEA R21, R28, R21, 0x4 ; /* 0x000000151c157211 */
/* 0x008fe200078e20ff */
/*0100*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe200078e0203 */
/*0110*/ LEA R25, R22, R27, 0x2 ; /* 0x0000001b16197211 */
/* 0x000fe400078e10ff */
/*0120*/ LEA R24, R23, R26, 0x2 ; /* 0x0000001a17187211 */
/* 0x000fe200078e10ff */
/*0130*/ IMAD R28, R28, 0x10, R22 ; /* 0x000000101c1c7824 */
/* 0x000fca00078e0216 */
/*0140*/ ISETP.GE.AND P0, PT, R28, c[0x0][0x160], PT ; /* 0x000058001c007a0c */
/* 0x000fe20003f06270 */
/*0150*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0160*/ ISETP.GE.OR P2, PT, R22, c[0x0][0x160], P1 ; /* 0x0000580016007a0c */
/* 0x000fc40000f46670 */
/*0170*/ ISETP.GE.OR P3, PT, R23, c[0x0][0x160], P0 ; /* 0x0000580017007a0c */
/* 0x000fe40000766670 */
/*0180*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fd20000000f00 */
/*0190*/ @!P2 LDG.E R6, [R2.64] ; /* 0x000000040206a981 */
/* 0x0000a4000c1e1900 */
/*01a0*/ @!P3 MOV R4, 0x4 ; /* 0x000000040004b802 */
/* 0x000fca0000000f00 */
/*01b0*/ @!P3 IMAD.WIDE R4, R21, R4, c[0x0][0x170] ; /* 0x00005c001504b625 */
/* 0x000fca00078e0204 */
/*01c0*/ @!P3 LDG.E R9, [R4.64] ; /* 0x000000040409b981 */
/* 0x000ee2000c1e1900 */
/*01d0*/ IADD3 R20, R20, 0x1, RZ ; /* 0x0000000114147810 */
/* 0x000fc80007ffe0ff */
/*01e0*/ ISETP.NE.AND P2, PT, R20, 0x40, PT ; /* 0x000000401400780c */
/* 0x000fe40003f45270 */
/*01f0*/ IADD3 R2, P3, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x001fe40007f7e0ff */
/*0200*/ IADD3 R22, R22, 0x10, RZ ; /* 0x0000001016167810 */
/* 0x000fe40007ffe0ff */
/*0210*/ IADD3 R23, R23, 0x10, RZ ; /* 0x0000001017177810 */
/* 0x000fe40007ffe0ff */
/*0220*/ IADD3.X R3, RZ, R3, RZ, P3, !PT ; /* 0x00000003ff037210 */
/* 0x000fe20001ffe4ff */
/*0230*/ STS [R25], R6 ; /* 0x0000000619007388 */
/* 0x004fe80000000800 */
/*0240*/ STS [R24], R9 ; /* 0x0000000918007388 */
/* 0x008fe80000000800 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0260*/ LDS.128 R12, [R26] ; /* 0x000000001a0c7984 */
/* 0x000fe80000000c00 */
/*0270*/ LDS.128 R16, [R27] ; /* 0x000000001b107984 */
/* 0x000e280000000c00 */
/*0280*/ LDS.128 R8, [R26+0x10] ; /* 0x000010001a087984 */
/* 0x000fe20000000c00 */
/*0290*/ IMAD R12, R12, R16, R7 ; /* 0x000000100c0c7224 */
/* 0x001fc600078e0207 */
/*02a0*/ LDS.128 R4, [R27+0x10] ; /* 0x000010001b047984 */
/* 0x000e220000000c00 */
/*02b0*/ IMAD R13, R13, R17, R12 ; /* 0x000000110d0d7224 */
/* 0x000fc800078e020c */
/*02c0*/ IMAD R14, R14, R18, R13 ; /* 0x000000120e0e7224 */
/* 0x000fc800078e020d */
/*02d0*/ IMAD R15, R15, R19, R14 ; /* 0x000000130f0f7224 */
/* 0x000fe400078e020e */
/*02e0*/ LDS.128 R16, [R27+0x20] ; /* 0x000020001b107984 */
/* 0x000fe40000000c00 */
/*02f0*/ IMAD R4, R8, R4, R15 ; /* 0x0000000408047224 */
/* 0x001fe400078e020f */
/*0300*/ LDS.128 R12, [R26+0x20] ; /* 0x000020001a0c7984 */
/* 0x000e240000000c00 */
/*0310*/ IMAD R5, R9, R5, R4 ; /* 0x0000000509057224 */
/* 0x000fc800078e0204 */
/*0320*/ IMAD R6, R10, R6, R5 ; /* 0x000000060a067224 */
/* 0x000fc800078e0205 */
/*0330*/ IMAD R7, R11, R7, R6 ; /* 0x000000070b077224 */
/* 0x000fe400078e0206 */
/*0340*/ LDS.128 R8, [R27+0x30] ; /* 0x000030001b087984 */
/* 0x000fe40000000c00 */
/*0350*/ IMAD R12, R12, R16, R7 ; /* 0x000000100c0c7224 */
/* 0x001fe400078e0207 */
/*0360*/ LDS.128 R4, [R26+0x30] ; /* 0x000030001a047984 */
/* 0x000e240000000c00 */
/*0370*/ IMAD R13, R13, R17, R12 ; /* 0x000000110d0d7224 */
/* 0x000fc800078e020c */
/*0380*/ IMAD R14, R14, R18, R13 ; /* 0x000000120e0e7224 */
/* 0x000fc800078e020d */
/*0390*/ IMAD R15, R15, R19, R14 ; /* 0x000000130f0f7224 */
/* 0x000fc800078e020e */
/*03a0*/ IMAD R4, R4, R8, R15 ; /* 0x0000000804047224 */
/* 0x001fc800078e020f */
/*03b0*/ IMAD R5, R5, R9, R4 ; /* 0x0000000905057224 */
/* 0x000fe200078e0204 */
/*03c0*/ MOV R4, 0x10 ; /* 0x0000001000047802 */
/* 0x000fc60000000f00 */
/*03d0*/ IMAD R6, R6, R10, R5 ; /* 0x0000000a06067224 */
/* 0x000fe400078e0205 */
/*03e0*/ IMAD R21, R4, c[0x0][0x160], R21 ; /* 0x0000580004157a24 */
/* 0x000fe400078e0215 */
/*03f0*/ IMAD R7, R7, R11, R6 ; /* 0x0000000b07077224 */
/* 0x000fe200078e0206 */
/*0400*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0410*/ @P2 BRA 0x140 ; /* 0xfffffd2000002947 */
/* 0x000fea000383ffff */
/*0420*/ ISETP.GE.OR P0, PT, R29, c[0x0][0x160], P0 ; /* 0x000058001d007a0c */
/* 0x000fda0000706670 */
/*0430*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0440*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0450*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0460*/ LEA R3, R0, R3, 0x4 ; /* 0x0000000300037211 */
/* 0x001fca00078e20ff */
/*0470*/ IMAD R2, R3, c[0x0][0x160], R28 ; /* 0x0000580003027a24 */
/* 0x000fc800078e021c */
/*0480*/ IMAD.WIDE R2, R2, R5, c[0x0][0x178] ; /* 0x00005e0002027625 */
/* 0x000fca00078e0205 */
/*0490*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*04a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04b0*/ BRA 0x4b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10mul_kerneliPjS_S_
.globl _Z10mul_kerneliPjS_S_
.p2align 8
.type _Z10mul_kerneliPjS_S_,@function
_Z10mul_kerneliPjS_S_:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v4, 0x3ff, v0
v_bfe_u32 v5, v0, 10, 10
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshl_add_u32 v3, s14, 4, v4
v_lshlrev_b32_e32 v6, 6, v4
v_lshl_add_u32 v0, s15, 4, v5
v_lshl_add_u32 v7, v5, 6, 0x400
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v8, v5, 2, v6
v_lshl_add_u32 v10, v4, 2, v7
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v9, v3, s8
v_cmp_gt_i32_e32 vcc_lo, s8, v3
v_cmp_gt_i32_e64 s2, s8, v0
.LBB0_1:
s_lshl_b32 s10, s9, 4
v_mov_b32_e32 v2, 0
v_dual_mov_b32 v11, 0 :: v_dual_add_nc_u32 v12, s10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s3, s8, v12
s_and_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s11, s3
s_cbranch_execz .LBB0_3
v_add_nc_u32_e32 v11, v12, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v11, s3, s4, v11
v_add_co_ci_u32_e64 v12, s3, s5, v12, s3
global_load_b32 v11, v[11:12], off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s11
v_add_nc_u32_e32 v12, s10, v4
s_waitcnt vmcnt(0)
ds_store_b32 v8, v11
v_cmp_gt_i32_e64 s3, s8, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, s3
s_and_saveexec_b32 s10, s3
s_cbranch_execz .LBB0_5
v_mad_u64_u32 v[13:14], null, v12, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[11:12], 2, v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v11, s3, s6, v11
v_add_co_ci_u32_e64 v12, s3, s7, v12, s3
global_load_b32 v2, v[11:12], off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s10
s_mov_b32 s3, 0
s_waitcnt vmcnt(0)
ds_store_b32 v10, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_6:
v_add_nc_u32_e32 v2, s3, v6
v_add_nc_u32_e32 v11, s3, v7
s_add_i32 s3, s3, 4
ds_load_b32 v12, v2
ds_load_b32 v13, v11
v_mov_b32_e32 v11, v1
s_cmp_eq_u32 s3, 64
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v13, v12, v[11:12]
s_cbranch_scc0 .LBB0_6
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, 64
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_1
v_max_i32_e32 v2, v3, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v2
s_cbranch_execz .LBB0_10
s_load_b64 s[0:1], s[0:1], 0x18
v_mad_u64_u32 v[4:5], null, v3, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[2:3], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10mul_kerneliPjS_S_
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10mul_kerneliPjS_S_, .Lfunc_end0-_Z10mul_kerneliPjS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10add_kerneliPjS_S_
.globl _Z10add_kerneliPjS_S_
.p2align 8
.type _Z10add_kerneliPjS_S_,@function
_Z10add_kerneliPjS_S_:
s_load_b32 s2, s[0:1], 0x0
v_lshl_add_u32 v0, s15, 8, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v1, 31, v0
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10add_kerneliPjS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10add_kerneliPjS_S_, .Lfunc_end1-_Z10add_kerneliPjS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10mul_kerneliPjS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10mul_kerneliPjS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10add_kerneliPjS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10add_kerneliPjS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00107c8e_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8rand_genjiPj
.type _Z8rand_genjiPj, @function
_Z8rand_genjiPj:
.LFB2060:
.cfi_startproc
endbr64
movl %edi, %r8d
movl %esi, %edi
imull %esi, %edi
testl %esi, %esi
jle .L3
movslq %esi, %r10
leaq 0(,%r10,4), %r11
movq %rdx, %r9
addl %r8d, %esi
movl $2, %eax
.L5:
movl $0, %ecx
.L6:
imull %eax, %eax
addl %r8d, %eax
addl %ecx, %eax
movl $0, %edx
divl %edi
movl %edx, %eax
movl %edx, (%r9,%rcx,4)
addq $1, %rcx
cmpq %r10, %rcx
jne .L6
addl $1, %r8d
addq %r11, %r9
cmpl %esi, %r8d
jne .L5
.L3:
ret
.cfi_endproc
.LFE2060:
.size _Z8rand_genjiPj, .-_Z8rand_genjiPj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "["
.LC1:
.string " %u"
.LC2:
.string " ]\n"
.text
.globl _Z12print_matrixiPj
.type _Z12print_matrixiPj, @function
_Z12print_matrixiPj:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
testl %edi, %edi
jle .L8
movslq %edi, %r14
leaq 0(,%r14,4), %r15
leaq (%rsi,%r15), %rbp
negq %r14
salq $2, %r14
movl $0, %r13d
leaq .LC1(%rip), %r12
.L11:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq 0(%rbp,%r14), %rbx
.L10:
movl (%rbx), %ecx
movq %r12, %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L10
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L11
.L8:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z12print_matrixiPj, .-_Z12print_matrixiPj
.globl _Z9signatureiPj
.type _Z9signatureiPj, @function
_Z9signatureiPj:
.LFB2062:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L19
movslq %edi, %r8
leaq 0(,%r8,4), %r9
leaq (%rsi,%r9), %rcx
negq %r8
salq $2, %r8
movl $0, %esi
movl $0, %eax
.L17:
leaq (%rcx,%r8), %rdx
.L18:
addl (%rdx), %eax
imull $-1640531535, %eax, %eax
addq $4, %rdx
cmpq %rcx, %rdx
jne .L18
addl $1, %esi
addq %r9, %rcx
cmpl %esi, %edi
jne .L17
.L15:
ret
.L19:
movl $0, %eax
ret
.cfi_endproc
.LFE2062:
.size _Z9signatureiPj, .-_Z9signatureiPj
.globl _Z35__device_stub__Z10mul_kerneliPjS_S_iPjS_S_
.type _Z35__device_stub__Z10mul_kerneliPjS_S_iPjS_S_, @function
_Z35__device_stub__Z10mul_kerneliPjS_S_iPjS_S_:
.LFB2088:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10mul_kerneliPjS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z35__device_stub__Z10mul_kerneliPjS_S_iPjS_S_, .-_Z35__device_stub__Z10mul_kerneliPjS_S_iPjS_S_
.globl _Z10mul_kerneliPjS_S_
.type _Z10mul_kerneliPjS_S_, @function
_Z10mul_kerneliPjS_S_:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10mul_kerneliPjS_S_iPjS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z10mul_kerneliPjS_S_, .-_Z10mul_kerneliPjS_S_
.globl _Z35__device_stub__Z10add_kerneliPjS_S_iPjS_S_
.type _Z35__device_stub__Z10add_kerneliPjS_S_iPjS_S_, @function
_Z35__device_stub__Z10add_kerneliPjS_S_iPjS_S_:
.LFB2090:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10add_kerneliPjS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z35__device_stub__Z10add_kerneliPjS_S_iPjS_S_, .-_Z35__device_stub__Z10add_kerneliPjS_S_iPjS_S_
.globl _Z10add_kerneliPjS_S_
.type _Z10add_kerneliPjS_S_, @function
_Z10add_kerneliPjS_S_:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10add_kerneliPjS_S_iPjS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z10add_kerneliPjS_S_, .-_Z10add_kerneliPjS_S_
.section .rodata.str1.1
.LC3:
.string "%d %d"
.LC4:
.string "%d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "/home/ubuntu/Datasets/stackv2/train-structured/George0828Zhang/cuda-practice/main/AdvancedMatrixCalculator/main.cu"
.section .rodata.str1.1
.LC6:
.string "GPUassert: %s %s %d\n"
.LC7:
.string "%s"
.LC8:
.string "%u\n"
.text
.globl main
.type main, @function
main:
.LFB2063:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $664, %rsp
.cfi_def_cfa_offset 720
movq %fs:40, %rax
movq %rax, 648(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq .LC3(%rip), %rdi
call __isoc23_scanf@PLT
cmpl $0, 44(%rsp)
jle .L38
leaq 80(%rsp), %rbp
movl $0, %ebx
leaq .LC4(%rip), %r13
leaq hostIN(%rip), %r12
.L39:
movq %rbp, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq %rbx, %rdx
salq $22, %rdx
addq %r12, %rdx
movl 0(%rbp), %edi
movl 48(%rsp), %esi
call _Z8rand_genjiPj
movl 44(%rsp), %eax
addq $1, %rbx
addq $4, %rbp
cmpl %ebx, %eax
jg .L39
movslq 48(%rsp), %rbx
imulq %rbx, %rbx
salq $2, %rbx
testl %eax, %eax
jle .L40
movl $0, %r13d
leaq 192(%rsp), %r14
.L43:
leaq (%r14,%r13,8), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L79
movq %r13, %rsi
salq $22, %rsi
addq %r12, %rsi
movq (%r14,%r13,8), %rdi
movl $1, %ecx
movq %rbx, %rdx
call cudaMemcpy@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L80
addq $1, %r13
cmpl %r13d, 44(%rsp)
jg .L43
jmp .L40
.L79:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $102, %r9d
leaq .LC5(%rip), %r8
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L80:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $103, %r9d
leaq .LC5(%rip), %r8
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L88:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $106, %r9d
leaq .LC5(%rip), %r8
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L90:
testq %r13, %r13
je .L81
movsbl %al, %eax
subl $65, %eax
cltq
movq 192(%rsp,%rax,8), %rax
movq %rax, 16(%rsp)
movl $16, 68(%rsp)
movl $16, 72(%rsp)
movl $1, 76(%rsp)
movl $64, 56(%rsp)
movl $64, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L82
.L51:
leal 1(%rbp), %eax
movslq %ebp, %rbp
movq %r14, %r13
movq 400(%rsp,%rbp,8), %r14
jmp .L52
.L81:
movsbl %al, %eax
subl $65, %eax
cltq
movq 192(%rsp,%rax,8), %r13
jmp .L50
.L82:
movslq %ebp, %rax
movq 400(%rsp,%rax,8), %rcx
movq 16(%rsp), %rdx
movq %r13, %rsi
movl 48(%rsp), %edi
call _Z35__device_stub__Z10mul_kerneliPjS_S_iPjS_S_
jmp .L51
.L65:
movl 48(%rsp), %edi
movslq %ebp, %rax
movq %rax, 24(%rsp)
movq 400(%rsp,%rax,8), %rcx
imull %edi, %edi
movq %r13, %rdx
movq %r14, %rsi
call _Z35__device_stub__Z10add_kerneliPjS_S_iPjS_S_
leal 1(%rbp), %eax
movq 24(%rsp), %rcx
movq 400(%rsp,%rcx,8), %r13
cmpl $25, 16(%rsp)
jg .L53
movl $0, %r14d
jmp .L52
.L91:
movl %ebp, %eax
.L52:
cmpb $0, (%r12,%r15)
je .L53
movq %r13, %rdx
movq %r14, %r13
movq %rdx, %r14
movl %eax, %ebp
.L50:
call cudaPeekAtLastError@PLT
movl %eax, %edi
testl %eax, %eax
jne .L83
call cudaDeviceSynchronize@PLT
movl %eax, %edi
addq $1, %r12
testl %eax, %eax
je .L55
movl %eax, %ebx
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $146, %r9d
leaq .LC5(%rip), %r8
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L83:
movl %eax, %ebx
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $145, %r9d
leaq .LC5(%rip), %r8
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L87:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $148, %r9d
leaq .LC5(%rip), %r8
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L89:
movl $0, %ebp
.L58:
cmpl %ebp, 44(%rsp)
jle .L84
movq 192(%rsp,%rbp,8), %rdi
call cudaFree@PLT
movl %eax, %ebx
addq $1, %rbp
testl %eax, %eax
je .L58
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $154, %r9d
leaq .LC5(%rip), %r8
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L84:
movl $0, %ebp
.L61:
movq 400(%rsp,%rbp,8), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L85
addq $1, %rbp
cmpq $26, %rbp
jne .L61
movq 648(%rsp), %rax
subq %fs:40, %rax
jne .L86
movl $0, %eax
addq $664, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L85:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $157, %r9d
leaq .LC5(%rip), %r8
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L47:
testq %r14, %r14
je .L53
movl $256, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $4096, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
movslq %ebp, %rbp
movq 400(%rsp,%rbp,8), %r13
.L53:
movl $2, %ecx
movq %rbx, %rdx
movq %r13, %rsi
leaq hostTMP(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L87
leaq hostTMP(%rip), %rsi
movl 48(%rsp), %edi
call _Z9signatureiPj
movl %eax, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, 12(%rsp)
jmp .L46
.L38:
movslq 48(%rsp), %rbx
imulq %rbx, %rbx
salq $2, %rbx
.L40:
leaq 400(%rsp), %r12
leaq 608(%rsp), %r13
.L45:
movq %rbx, %rsi
movq %r12, %rdi
call cudaMalloc@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L88
addq $8, %r12
cmpq %r13, %r12
jne .L45
leaq 52(%rsp), %rsi
leaq .LC4(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $0, 12(%rsp)
.L46:
movl 12(%rsp), %eax
cmpl %eax, 52(%rsp)
jle .L89
leaq 608(%rsp), %rsi
leaq .LC7(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $0, %r12d
movl $0, %ebp
movl $0, %r13d
movl $0, %r14d
leaq 608(%rsp), %r15
.L55:
movl %r12d, 16(%rsp)
cmpl $25, %r12d
jg .L47
movzbl (%r12,%r15), %eax
cmpb $43, %al
je .L48
testb %al, %al
jne .L90
.L48:
testq %r14, %r14
je .L91
movl $256, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $4096, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
leal 1(%rbp), %eax
movslq %ebp, %rbp
movq 400(%rsp,%rbp,8), %r13
movl $0, %r14d
jmp .L52
.L86:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z10add_kerneliPjS_S_"
.LC10:
.string "_Z10mul_kerneliPjS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z10add_kerneliPjS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z10mul_kerneliPjS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl hostTMP
.bss
.align 32
.type hostTMP, @object
.size hostTMP, 4194304
hostTMP:
.zero 4194304
.globl hostIN
.align 32
.type hostIN, @object
.size hostIN, 109051904
hostIN:
.zero 109051904
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z25__device_stub__mul_kerneliPjS_S_ # -- Begin function _Z25__device_stub__mul_kerneliPjS_S_
.p2align 4, 0x90
.type _Z25__device_stub__mul_kerneliPjS_S_,@function
_Z25__device_stub__mul_kerneliPjS_S_: # @_Z25__device_stub__mul_kerneliPjS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10mul_kerneliPjS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__mul_kerneliPjS_S_, .Lfunc_end0-_Z25__device_stub__mul_kerneliPjS_S_
.cfi_endproc
# -- End function
.globl _Z25__device_stub__add_kerneliPjS_S_ # -- Begin function _Z25__device_stub__add_kerneliPjS_S_
.p2align 4, 0x90
.type _Z25__device_stub__add_kerneliPjS_S_,@function
_Z25__device_stub__add_kerneliPjS_S_: # @_Z25__device_stub__add_kerneliPjS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10add_kerneliPjS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z25__device_stub__add_kerneliPjS_S_, .Lfunc_end1-_Z25__device_stub__add_kerneliPjS_S_
.cfi_endproc
# -- End function
.globl _Z8rand_genjiPj # -- Begin function _Z8rand_genjiPj
.p2align 4, 0x90
.type _Z8rand_genjiPj,@function
_Z8rand_genjiPj: # @_Z8rand_genjiPj
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_6
# %bb.1: # %.preheader.lr.ph
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdx, %rcx
movl %esi, %r8d
imull %esi, %r8d
movl %esi, %r9d
movl %edi, %edi
movl $2, %edx
xorl %r10d, %r10d
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl %r10d, %eax
leaq (%rcx,%rax,4), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
imull %edx, %edx
addl %edi, %edx
addl %r14d, %edx
movl %edx, %eax
xorl %edx, %edx
divl %r8d
movl %edx, (%rbx,%r14,4)
incq %r14
cmpq %r14, %r9
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r11
addl %esi, %r10d
incq %rdi
cmpq %r9, %r11
jne .LBB2_2
# %bb.5:
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB2_6: # %._crit_edge25
retq
.Lfunc_end2:
.size _Z8rand_genjiPj, .Lfunc_end2-_Z8rand_genjiPj
.cfi_endproc
# -- End function
.globl _Z12print_matrixiPj # -- Begin function _Z12print_matrixiPj
.p2align 4, 0x90
.type _Z12print_matrixiPj,@function
_Z12print_matrixiPj: # @_Z12print_matrixiPj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, (%rsp) # 8-byte Spill
testl %edi, %edi
jle .LBB3_5
# %bb.1: # %.lr.ph14
movl %edi, %ebp
movl %edi, %r14d
xorl %r15d, %r15d
xorl %r12d, %r12d
.LBB3_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
movl %r15d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r13
movq stderr(%rip), %rsi
movl $91, %edi
callq fputc@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movq stderr(%rip), %rdi
movl (%r13,%rbx,4), %edx
movl $.L.str.1, %esi
xorl %eax, %eax
callq fprintf
incq %rbx
cmpq %rbx, %r14
jne .LBB3_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $3, %esi
movl $1, %edx
callq fwrite@PLT
incq %r12
addl %ebp, %r15d
cmpq %r14, %r12
jne .LBB3_2
.LBB3_5: # %._crit_edge15
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z12print_matrixiPj, .Lfunc_end3-_Z12print_matrixiPj
.cfi_endproc
# -- End function
.globl _Z9signatureiPj # -- Begin function _Z9signatureiPj
.p2align 4, 0x90
.type _Z9signatureiPj,@function
_Z9signatureiPj: # @_Z9signatureiPj
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB4_1
# %bb.2: # %.preheader.lr.ph
movl %edi, %ecx
xorl %edx, %edx
xorl %r8d, %r8d
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
movl %edx, %r9d
leaq (%rsi,%r9,4), %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB4_4: # Parent Loop BB4_3 Depth=1
# => This Inner Loop Header: Depth=2
addl (%r9,%r10,4), %eax
imull $-1640531535, %eax, %eax # imm = 0x9E3779B1
incq %r10
cmpq %r10, %rcx
jne .LBB4_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB4_3 Depth=1
incq %r8
addl %edi, %edx
cmpq %rcx, %r8
jne .LBB4_3
# %bb.6: # %._crit_edge18
retq
.LBB4_1:
xorl %eax, %eax
retq
.Lfunc_end4:
.size _Z9signatureiPj, .Lfunc_end4-_Z9signatureiPj
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $712, %rsp # imm = 0x2C8
.cfi_def_cfa_offset 768
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsp, %rsi
leaq 4(%rsp), %rdx
movl $.L.str.3, %edi
xorl %eax, %eax
callq __isoc23_scanf
cmpl $0, (%rsp)
jle .LBB5_8
# %bb.1: # %.lr.ph.preheader
movl $hostIN, %ebx
xorl %r14d, %r14d
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_7: # %_Z8rand_genjiPj.exit
# in Loop: Header=BB5_2 Depth=1
incq %r14
movslq (%rsp), %rax
addq $4194304, %rbx # imm = 0x400000
cmpq %rax, %r14
jge .LBB5_8
.LBB5_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB5_4 Depth 2
# Child Loop BB5_5 Depth 3
leaq (%rsp,%r14,4), %rsi
addq $384, %rsi # imm = 0x180
movl $.L.str.4, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 4(%rsp), %ecx
testl %ecx, %ecx
jle .LBB5_7
# %bb.3: # %.preheader.lr.ph.i
# in Loop: Header=BB5_2 Depth=1
movl 384(%rsp,%r14,4), %esi
movl %ecx, %edi
imull %ecx, %edi
movl $2, %edx
xorl %r8d, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB5_4: # %.preheader.i
# Parent Loop BB5_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB5_5 Depth 3
movl %r8d, %eax
leaq (%rbx,%rax,4), %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB5_5: # Parent Loop BB5_2 Depth=1
# Parent Loop BB5_4 Depth=2
# => This Inner Loop Header: Depth=3
imull %edx, %edx
addl %esi, %edx
addl %r11d, %edx
movl %edx, %eax
xorl %edx, %edx
divl %edi
movl %edx, (%r10,%r11,4)
incq %r11
cmpq %r11, %rcx
jne .LBB5_5
# %bb.6: # %._crit_edge.i
# in Loop: Header=BB5_4 Depth=2
incq %r9
addl %ecx, %r8d
incq %rsi
cmpq %rcx, %r9
jne .LBB5_4
jmp .LBB5_7
.LBB5_8: # %._crit_edge
movslq 4(%rsp), %r12
imulq %r12, %r12
shlq $2, %r12
cmpl $0, (%rsp)
jle .LBB5_27
# %bb.9: # %.lr.ph120.preheader
movl $hostIN, %r14d
leaq 496(%rsp), %r15
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB5_11: # %.lr.ph120
# =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB5_12
# %bb.14: # %_Z9gpuAssert10hipError_tPKcib.exit
# in Loop: Header=BB5_11 Depth=1
movq (%r15), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_15
# %bb.10: # in Loop: Header=BB5_11 Depth=1
incq %rbx
movslq (%rsp), %rax
addq $4194304, %r14 # imm = 0x400000
addq $8, %r15
cmpq %rax, %rbx
jl .LBB5_11
.LBB5_27: # %_Z9gpuAssert10hipError_tPKcib.exit71.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB5_28: # %_Z9gpuAssert10hipError_tPKcib.exit71
# =>This Inner Loop Header: Depth=1
leaq (%rsp,%rbx), %rdi
addq $176, %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB5_29
# %bb.16: # in Loop: Header=BB5_28 Depth=1
addq $8, %rbx
cmpq $208, %rbx
jne .LBB5_28
# %bb.17:
leaq 12(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq __isoc23_scanf
cmpl $0, 12(%rsp)
jle .LBB5_30
# %bb.18: # %.lr.ph130
movabsq $4294967552, %rax # imm = 0x100000100
addq $3840, %rax # imm = 0xF00
movq %rax, 136(%rsp) # 8-byte Spill
xorl %eax, %eax
movq %r12, 128(%rsp) # 8-byte Spill
jmp .LBB5_19
.p2align 4, 0x90
.LBB5_46: # in Loop: Header=BB5_19 Depth=1
xorl %esi, %esi
.LBB5_51: # %_Z9signatureiPj.exit
# in Loop: Header=BB5_19 Depth=1
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 92(%rsp), %eax # 4-byte Reload
incl %eax
cmpl 12(%rsp), %eax
jge .LBB5_30
.LBB5_19: # =>This Loop Header: Depth=1
# Child Loop BB5_20 Depth 2
# Child Loop BB5_48 Depth 2
# Child Loop BB5_49 Depth 3
movl %eax, 92(%rsp) # 4-byte Spill
xorl %ebx, %ebx
movl $.L.str.6, %edi
leaq 144(%rsp), %rsi
xorl %eax, %eax
callq __isoc23_scanf
xorl %ebp, %ebp
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_20: # Parent Loop BB5_19 Depth=1
# => This Inner Loop Header: Depth=2
cmpq $26, %rbx
je .LBB5_32
# %bb.21: # in Loop: Header=BB5_20 Depth=2
movzbl 144(%rsp,%rbx), %eax
testl %eax, %eax
je .LBB5_32
# %bb.22: # in Loop: Header=BB5_20 Depth=2
cmpl $43, %eax
jne .LBB5_23
.p2align 4, 0x90
.LBB5_32: # in Loop: Header=BB5_20 Depth=2
testq %rbp, %rbp
je .LBB5_33
# %bb.34: # in Loop: Header=BB5_20 Depth=2
movq 136(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_36
# %bb.35: # in Loop: Header=BB5_20 Depth=2
movl 4(%rsp), %eax
imull %eax, %eax
movslq %r14d, %rcx
movq 176(%rsp,%rcx,8), %rcx
movl %eax, 8(%rsp)
movq %rbp, 80(%rsp)
movq %r15, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z10add_kerneliPjS_S_, %edi
leaq 96(%rsp), %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_36: # in Loop: Header=BB5_20 Depth=2
movslq %r14d, %rax
incl %r14d
movq 176(%rsp,%rax,8), %rbp
xorl %r12d, %r12d
jmp .LBB5_37
.p2align 4, 0x90
.LBB5_33: # in Loop: Header=BB5_20 Depth=2
xorl %r12d, %r12d
movq %r15, %rbp
jmp .LBB5_37
.LBB5_23: # in Loop: Header=BB5_20 Depth=2
movsbq %al, %rax
movq -24(%rsp,%rax,8), %r12
testq %r15, %r15
je .LBB5_37
# %bb.24: # in Loop: Header=BB5_20 Depth=2
movabsq $274877907008, %rdi # imm = 0x4000000040
movl $1, %esi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
movslq %r14d, %r13
testl %eax, %eax
jne .LBB5_26
# %bb.25: # in Loop: Header=BB5_20 Depth=2
movl 4(%rsp), %eax
movq 176(%rsp,%r13,8), %rcx
movl %eax, 8(%rsp)
movq %r15, 80(%rsp)
movq %r12, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z10mul_kerneliPjS_S_, %edi
leaq 96(%rsp), %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_26: # in Loop: Header=BB5_20 Depth=2
leal 1(%r13), %r14d
movq 176(%rsp,%r13,8), %r12
.p2align 4, 0x90
.LBB5_37: # in Loop: Header=BB5_20 Depth=2
cmpq $26, %rbx
je .LBB5_43
# %bb.38: # in Loop: Header=BB5_20 Depth=2
cmpb $0, 144(%rsp,%rbx)
je .LBB5_43
# %bb.39: # in Loop: Header=BB5_20 Depth=2
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB5_40
# %bb.41: # %_Z9gpuAssert10hipError_tPKcib.exit79
# in Loop: Header=BB5_20 Depth=2
callq hipDeviceSynchronize
incq %rbx
movq %r12, %r15
testl %eax, %eax
je .LBB5_20
jmp .LBB5_42
.p2align 4, 0x90
.LBB5_43: # in Loop: Header=BB5_19 Depth=1
movl $hostTMP, %edi
movq %rbp, %rsi
movq 128(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_44
# %bb.45: # %_Z9gpuAssert10hipError_tPKcib.exit83
# in Loop: Header=BB5_19 Depth=1
movl 4(%rsp), %eax
testl %eax, %eax
jle .LBB5_46
# %bb.47: # %.preheader.lr.ph.i84
# in Loop: Header=BB5_19 Depth=1
xorl %edx, %edx
xorl %ecx, %ecx
xorl %esi, %esi
.p2align 4, 0x90
.LBB5_48: # %.preheader.i85
# Parent Loop BB5_19 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB5_49 Depth 3
movl %edx, %edx
xorl %edi, %edi
.p2align 4, 0x90
.LBB5_49: # Parent Loop BB5_19 Depth=1
# Parent Loop BB5_48 Depth=2
# => This Inner Loop Header: Depth=3
leaq (,%rdx,4), %r8
addl hostTMP(%r8,%rdi,4), %esi
imull $-1640531535, %esi, %esi # imm = 0x9E3779B1
incq %rdi
cmpq %rdi, %rax
jne .LBB5_49
# %bb.50: # %._crit_edge.i90
# in Loop: Header=BB5_48 Depth=2
incq %rcx
addl %eax, %edx
cmpq %rax, %rcx
jne .LBB5_48
jmp .LBB5_51
.LBB5_30: # %.preheader104
cmpl $0, (%rsp)
jle .LBB5_57
# %bb.31: # %_Z9gpuAssert10hipError_tPKcib.exit92.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB5_53: # %_Z9gpuAssert10hipError_tPKcib.exit92
# =>This Inner Loop Header: Depth=1
movq 496(%rsp,%rbx,8), %rdi
callq hipFree
testl %eax, %eax
jne .LBB5_54
# %bb.52: # in Loop: Header=BB5_53 Depth=1
incq %rbx
movslq (%rsp), %rax
cmpq %rax, %rbx
jl .LBB5_53
.LBB5_57: # %_Z9gpuAssert10hipError_tPKcib.exit94.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB5_58: # %_Z9gpuAssert10hipError_tPKcib.exit94
# =>This Inner Loop Header: Depth=1
movq 176(%rsp,%rbx,8), %rdi
callq hipFree
testl %eax, %eax
jne .LBB5_59
# %bb.55: # in Loop: Header=BB5_58 Depth=1
incq %rbx
cmpq $26, %rbx
jne .LBB5_58
# %bb.56:
xorl %eax, %eax
addq $712, %rsp # imm = 0x2C8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_42:
.cfi_def_cfa_offset 768
movl %eax, %r13d
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $148, %r8d
xorl %eax, %eax
callq fprintf
movl %r13d, %edi
callq exit
.LBB5_40:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $147, %r8d
.LBB5_13:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.LBB5_29:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $108, %r8d
jmp .LBB5_13
.LBB5_59:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $159, %r8d
jmp .LBB5_13
.LBB5_12:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $104, %r8d
jmp .LBB5_13
.LBB5_15:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $105, %r8d
jmp .LBB5_13
.LBB5_54:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $156, %r8d
jmp .LBB5_13
.LBB5_44:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $150, %r8d
jmp .LBB5_13
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10mul_kerneliPjS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10add_kerneliPjS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10mul_kerneliPjS_S_,@object # @_Z10mul_kerneliPjS_S_
.section .rodata,"a",@progbits
.globl _Z10mul_kerneliPjS_S_
.p2align 3, 0x0
_Z10mul_kerneliPjS_S_:
.quad _Z25__device_stub__mul_kerneliPjS_S_
.size _Z10mul_kerneliPjS_S_, 8
.type _Z10add_kerneliPjS_S_,@object # @_Z10add_kerneliPjS_S_
.globl _Z10add_kerneliPjS_S_
.p2align 3, 0x0
_Z10add_kerneliPjS_S_:
.quad _Z25__device_stub__add_kerneliPjS_S_
.size _Z10add_kerneliPjS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz " %u"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " ]\n"
.size .L.str.2, 4
.type hostIN,@object # @hostIN
.bss
.globl hostIN
.p2align 4, 0x0
hostIN:
.zero 109051904
.size hostIN, 109051904
.type hostTMP,@object # @hostTMP
.globl hostTMP
.p2align 4, 0x0
hostTMP:
.zero 4194304
.size hostTMP, 4194304
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "%d %d"
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/George0828Zhang/cuda-practice/main/AdvancedMatrixCalculator/main.hip"
.size .L.str.5, 126
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%s"
.size .L.str.6, 3
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%u\n"
.size .L.str.7, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.8, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10mul_kerneliPjS_S_"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10add_kerneliPjS_S_"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__mul_kerneliPjS_S_
.addrsig_sym _Z25__device_stub__add_kerneliPjS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10mul_kerneliPjS_S_
.addrsig_sym _Z10add_kerneliPjS_S_
.addrsig_sym hostIN
.addrsig_sym hostTMP
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#define DIVERGENCE_HERE \
if(arr[id] %2 == 0) \
arr[id] = arr[id-1]; \
else \
arr[id] = arr[id+1];
__global__ void kernel_one(int *arr, int N) {
int id = threadIdx.x + blockDim.x * blockIdx.x;
if (id >= N);
DIVERGENCE_HERE;
}
__device__ void aux(int *arr, int id, int N) {
DIVERGENCE_HERE;
}
__global__ void kernel_two(int *arr, int N) {
int id = threadIdx.x + blockDim.x * blockIdx.x;
if (id >= N);
aux(arr, id, N);
} | code for sm_80
Function : _Z10kernel_twoPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0060*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1900 */
/*0080*/ LOP3.LUT R4, R4, 0x1, RZ, 0xc0, !PT ; /* 0x0000000104047812 */
/* 0x004fc800078ec0ff */
/*0090*/ ISETP.NE.U32.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe40003f05070 */
/*00a0*/ IADD3 R4, R0, 0x1, RZ ; /* 0x0000000100047810 */
/* 0x000fd60007ffe0ff */
/*00b0*/ @P0 IADD3 R4, R0, -0x1, RZ ; /* 0xffffffff00040810 */
/* 0x000fca0007ffe0ff */
/*00c0*/ IMAD.WIDE R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fcc00078e0204 */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10kernel_onePii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0060*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1900 */
/*0080*/ LOP3.LUT R4, R4, 0x1, RZ, 0xc0, !PT ; /* 0x0000000104047812 */
/* 0x004fc800078ec0ff */
/*0090*/ ISETP.NE.U32.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe40003f05070 */
/*00a0*/ IADD3 R4, R0, 0x1, RZ ; /* 0x0000000100047810 */
/* 0x000fd60007ffe0ff */
/*00b0*/ @P0 IADD3 R4, R0, -0x1, RZ ; /* 0xffffffff00040810 */
/* 0x000fca0007ffe0ff */
/*00c0*/ IMAD.WIDE R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fcc00078e0204 */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#define DIVERGENCE_HERE \
if(arr[id] %2 == 0) \
arr[id] = arr[id-1]; \
else \
arr[id] = arr[id+1];
__global__ void kernel_one(int *arr, int N) {
int id = threadIdx.x + blockDim.x * blockIdx.x;
if (id >= N);
DIVERGENCE_HERE;
}
__device__ void aux(int *arr, int id, int N) {
DIVERGENCE_HERE;
}
__global__ void kernel_two(int *arr, int N) {
int id = threadIdx.x + blockDim.x * blockIdx.x;
if (id >= N);
aux(arr, id, N);
} | .file "tmpxft_00073ae4_00000000-6_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3auxPiii
.type _Z3auxPiii, @function
_Z3auxPiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z3auxPiii, .-_Z3auxPiii
.globl _Z31__device_stub__Z10kernel_onePiiPii
.type _Z31__device_stub__Z10kernel_onePiiPii, @function
_Z31__device_stub__Z10kernel_onePiiPii:
.LFB2052:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10kernel_onePii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z31__device_stub__Z10kernel_onePiiPii, .-_Z31__device_stub__Z10kernel_onePiiPii
.globl _Z10kernel_onePii
.type _Z10kernel_onePii, @function
_Z10kernel_onePii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z10kernel_onePiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z10kernel_onePii, .-_Z10kernel_onePii
.globl _Z31__device_stub__Z10kernel_twoPiiPii
.type _Z31__device_stub__Z10kernel_twoPiiPii, @function
_Z31__device_stub__Z10kernel_twoPiiPii:
.LFB2054:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10kernel_twoPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z31__device_stub__Z10kernel_twoPiiPii, .-_Z31__device_stub__Z10kernel_twoPiiPii
.globl _Z10kernel_twoPii
.type _Z10kernel_twoPii, @function
_Z10kernel_twoPii:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z10kernel_twoPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z10kernel_twoPii, .-_Z10kernel_twoPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10kernel_twoPii"
.LC1:
.string "_Z10kernel_onePii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kernel_twoPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kernel_onePii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#define DIVERGENCE_HERE \
if(arr[id] %2 == 0) \
arr[id] = arr[id-1]; \
else \
arr[id] = arr[id+1];
__global__ void kernel_one(int *arr, int N) {
int id = threadIdx.x + blockDim.x * blockIdx.x;
if (id >= N);
DIVERGENCE_HERE;
}
__device__ void aux(int *arr, int id, int N) {
DIVERGENCE_HERE;
}
__global__ void kernel_two(int *arr, int N) {
int id = threadIdx.x + blockDim.x * blockIdx.x;
if (id >= N);
aux(arr, id, N);
} | #include <hip/hip_runtime.h>
#define DIVERGENCE_HERE \
if(arr[id] %2 == 0) \
arr[id] = arr[id-1]; \
else \
arr[id] = arr[id+1];
__global__ void kernel_one(int *arr, int N) {
int id = threadIdx.x + blockDim.x * blockIdx.x;
if (id >= N);
DIVERGENCE_HERE;
}
__device__ void aux(int *arr, int id, int N) {
DIVERGENCE_HERE;
}
__global__ void kernel_two(int *arr, int N) {
int id = threadIdx.x + blockDim.x * blockIdx.x;
if (id >= N);
aux(arr, id, N);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define DIVERGENCE_HERE \
if(arr[id] %2 == 0) \
arr[id] = arr[id-1]; \
else \
arr[id] = arr[id+1];
__global__ void kernel_one(int *arr, int N) {
int id = threadIdx.x + blockDim.x * blockIdx.x;
if (id >= N);
DIVERGENCE_HERE;
}
__device__ void aux(int *arr, int id, int N) {
DIVERGENCE_HERE;
}
__global__ void kernel_two(int *arr, int N) {
int id = threadIdx.x + blockDim.x * blockIdx.x;
if (id >= N);
aux(arr, id, N);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10kernel_onePii
.globl _Z10kernel_onePii
.p2align 8
.type _Z10kernel_onePii,@function
_Z10kernel_onePii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v2, 1, v2
v_cmp_eq_u32_e32 vcc_lo, 0, v2
v_cndmask_b32_e64 v2, 4, -4, vcc_lo
v_cndmask_b32_e64 v3, 0, -1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, v1, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10kernel_onePii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10kernel_onePii, .Lfunc_end0-_Z10kernel_onePii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10kernel_twoPii
.globl _Z10kernel_twoPii
.p2align 8
.type _Z10kernel_twoPii,@function
_Z10kernel_twoPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v2, 1, v2
v_cmp_eq_u32_e32 vcc_lo, 0, v2
v_cndmask_b32_e64 v2, 4, -4, vcc_lo
v_cndmask_b32_e64 v3, 0, -1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, v1, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10kernel_twoPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10kernel_twoPii, .Lfunc_end1-_Z10kernel_twoPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10kernel_onePii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10kernel_onePii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10kernel_twoPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10kernel_twoPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define DIVERGENCE_HERE \
if(arr[id] %2 == 0) \
arr[id] = arr[id-1]; \
else \
arr[id] = arr[id+1];
__global__ void kernel_one(int *arr, int N) {
int id = threadIdx.x + blockDim.x * blockIdx.x;
if (id >= N);
DIVERGENCE_HERE;
}
__device__ void aux(int *arr, int id, int N) {
DIVERGENCE_HERE;
}
__global__ void kernel_two(int *arr, int N) {
int id = threadIdx.x + blockDim.x * blockIdx.x;
if (id >= N);
aux(arr, id, N);
} | .text
.file "kernels.hip"
.globl _Z25__device_stub__kernel_onePii # -- Begin function _Z25__device_stub__kernel_onePii
.p2align 4, 0x90
.type _Z25__device_stub__kernel_onePii,@function
_Z25__device_stub__kernel_onePii: # @_Z25__device_stub__kernel_onePii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10kernel_onePii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__kernel_onePii, .Lfunc_end0-_Z25__device_stub__kernel_onePii
.cfi_endproc
# -- End function
.globl _Z25__device_stub__kernel_twoPii # -- Begin function _Z25__device_stub__kernel_twoPii
.p2align 4, 0x90
.type _Z25__device_stub__kernel_twoPii,@function
_Z25__device_stub__kernel_twoPii: # @_Z25__device_stub__kernel_twoPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10kernel_twoPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z25__device_stub__kernel_twoPii, .Lfunc_end1-_Z25__device_stub__kernel_twoPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10kernel_onePii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10kernel_twoPii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10kernel_onePii,@object # @_Z10kernel_onePii
.section .rodata,"a",@progbits
.globl _Z10kernel_onePii
.p2align 3, 0x0
_Z10kernel_onePii:
.quad _Z25__device_stub__kernel_onePii
.size _Z10kernel_onePii, 8
.type _Z10kernel_twoPii,@object # @_Z10kernel_twoPii
.globl _Z10kernel_twoPii
.p2align 3, 0x0
_Z10kernel_twoPii:
.quad _Z25__device_stub__kernel_twoPii
.size _Z10kernel_twoPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10kernel_onePii"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10kernel_twoPii"
.size .L__unnamed_2, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__kernel_onePii
.addrsig_sym _Z25__device_stub__kernel_twoPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10kernel_onePii
.addrsig_sym _Z10kernel_twoPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10kernel_twoPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0060*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1900 */
/*0080*/ LOP3.LUT R4, R4, 0x1, RZ, 0xc0, !PT ; /* 0x0000000104047812 */
/* 0x004fc800078ec0ff */
/*0090*/ ISETP.NE.U32.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe40003f05070 */
/*00a0*/ IADD3 R4, R0, 0x1, RZ ; /* 0x0000000100047810 */
/* 0x000fd60007ffe0ff */
/*00b0*/ @P0 IADD3 R4, R0, -0x1, RZ ; /* 0xffffffff00040810 */
/* 0x000fca0007ffe0ff */
/*00c0*/ IMAD.WIDE R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fcc00078e0204 */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10kernel_onePii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0060*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1900 */
/*0080*/ LOP3.LUT R4, R4, 0x1, RZ, 0xc0, !PT ; /* 0x0000000104047812 */
/* 0x004fc800078ec0ff */
/*0090*/ ISETP.NE.U32.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe40003f05070 */
/*00a0*/ IADD3 R4, R0, 0x1, RZ ; /* 0x0000000100047810 */
/* 0x000fd60007ffe0ff */
/*00b0*/ @P0 IADD3 R4, R0, -0x1, RZ ; /* 0xffffffff00040810 */
/* 0x000fca0007ffe0ff */
/*00c0*/ IMAD.WIDE R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fcc00078e0204 */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10kernel_onePii
.globl _Z10kernel_onePii
.p2align 8
.type _Z10kernel_onePii,@function
_Z10kernel_onePii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v2, 1, v2
v_cmp_eq_u32_e32 vcc_lo, 0, v2
v_cndmask_b32_e64 v2, 4, -4, vcc_lo
v_cndmask_b32_e64 v3, 0, -1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, v1, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10kernel_onePii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10kernel_onePii, .Lfunc_end0-_Z10kernel_onePii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10kernel_twoPii
.globl _Z10kernel_twoPii
.p2align 8
.type _Z10kernel_twoPii,@function
_Z10kernel_twoPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v2, 1, v2
v_cmp_eq_u32_e32 vcc_lo, 0, v2
v_cndmask_b32_e64 v2, 4, -4, vcc_lo
v_cndmask_b32_e64 v3, 0, -1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, v1, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10kernel_twoPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10kernel_twoPii, .Lfunc_end1-_Z10kernel_twoPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10kernel_onePii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10kernel_onePii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10kernel_twoPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10kernel_twoPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00073ae4_00000000-6_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3auxPiii
.type _Z3auxPiii, @function
_Z3auxPiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z3auxPiii, .-_Z3auxPiii
.globl _Z31__device_stub__Z10kernel_onePiiPii
.type _Z31__device_stub__Z10kernel_onePiiPii, @function
_Z31__device_stub__Z10kernel_onePiiPii:
.LFB2052:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10kernel_onePii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z31__device_stub__Z10kernel_onePiiPii, .-_Z31__device_stub__Z10kernel_onePiiPii
.globl _Z10kernel_onePii
.type _Z10kernel_onePii, @function
_Z10kernel_onePii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z10kernel_onePiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z10kernel_onePii, .-_Z10kernel_onePii
.globl _Z31__device_stub__Z10kernel_twoPiiPii
.type _Z31__device_stub__Z10kernel_twoPiiPii, @function
_Z31__device_stub__Z10kernel_twoPiiPii:
.LFB2054:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10kernel_twoPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z31__device_stub__Z10kernel_twoPiiPii, .-_Z31__device_stub__Z10kernel_twoPiiPii
.globl _Z10kernel_twoPii
.type _Z10kernel_twoPii, @function
_Z10kernel_twoPii:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z10kernel_twoPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z10kernel_twoPii, .-_Z10kernel_twoPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10kernel_twoPii"
.LC1:
.string "_Z10kernel_onePii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kernel_twoPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kernel_onePii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernels.hip"
.globl _Z25__device_stub__kernel_onePii # -- Begin function _Z25__device_stub__kernel_onePii
.p2align 4, 0x90
.type _Z25__device_stub__kernel_onePii,@function
_Z25__device_stub__kernel_onePii: # @_Z25__device_stub__kernel_onePii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10kernel_onePii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__kernel_onePii, .Lfunc_end0-_Z25__device_stub__kernel_onePii
.cfi_endproc
# -- End function
.globl _Z25__device_stub__kernel_twoPii # -- Begin function _Z25__device_stub__kernel_twoPii
.p2align 4, 0x90
.type _Z25__device_stub__kernel_twoPii,@function
_Z25__device_stub__kernel_twoPii: # @_Z25__device_stub__kernel_twoPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10kernel_twoPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z25__device_stub__kernel_twoPii, .Lfunc_end1-_Z25__device_stub__kernel_twoPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10kernel_onePii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10kernel_twoPii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10kernel_onePii,@object # @_Z10kernel_onePii
.section .rodata,"a",@progbits
.globl _Z10kernel_onePii
.p2align 3, 0x0
_Z10kernel_onePii:
.quad _Z25__device_stub__kernel_onePii
.size _Z10kernel_onePii, 8
.type _Z10kernel_twoPii,@object # @_Z10kernel_twoPii
.globl _Z10kernel_twoPii
.p2align 3, 0x0
_Z10kernel_twoPii:
.quad _Z25__device_stub__kernel_twoPii
.size _Z10kernel_twoPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10kernel_onePii"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10kernel_twoPii"
.size .L__unnamed_2, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__kernel_onePii
.addrsig_sym _Z25__device_stub__kernel_twoPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10kernel_onePii
.addrsig_sym _Z10kernel_twoPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
// ERROR CHECKING MACROS //////////////////////////////////////////////////////
__global__ void mmKernel(float* popsIn, float* popsOut, float* mmm, int patches) {
int ii = threadIdx.x;
if (ii < patches) {
extern __shared__ float s[];
s[ii] = 0.0;
for (int jj = 0; jj < patches; jj++) {
s[ii] += popsIn[ii]*mmm[ii*patches + jj];
}
__syncthreads();
popsOut[ii] = s[ii];
}
} | code for sm_80
Function : _Z8mmKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ STS [R0.X4], RZ ; /* 0x000000ff00007388 */
/* 0x0001e20000004800 */
/*0050*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f01270 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*0070*/ @!P0 BRA 0x7b0 ; /* 0x0000073000008947 */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff067624 */
/* 0x001fe200078e00ff */
/*0090*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fc800000001ff */
/*00a0*/ IADD3 R5, R6, -0x1, RZ ; /* 0xffffffff06057810 */
/* 0x000fc80007ffe0ff */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe40003f06070 */
/*00c0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe200078e0207 */
/*00d0*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*00e0*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fc60000000f00 */
/*00f0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000162000c1e1900 */
/*0100*/ LOP3.LUT R5, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306057812 */
/* 0x000fca00078ec0ff */
/*0110*/ @!P0 BRA 0x6d0 ; /* 0x000005b000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0130*/ IMAD R2, R0, c[0x0][0x178], RZ ; /* 0x00005e0000027a24 */
/* 0x001fe200078e02ff */
/*0140*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0160*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*0170*/ IMAD.WIDE R2, R2, R7, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fd800078e0207 */
/*0180*/ @!P0 BRA 0x5d0 ; /* 0x0000044000008947 */
/* 0x000fea0003800000 */
/*0190*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01b0*/ @!P1 BRA 0x430 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01d0*/ LDG.E R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x0000a8000c1e1900 */
/*01e0*/ LDG.E R14, [R2.64+0x4] ; /* 0x00000404020e7981 */
/* 0x0000e8000c1e1900 */
/*01f0*/ LDG.E R16, [R2.64+0x8] ; /* 0x0000080402107981 */
/* 0x000128000c1e1900 */
/*0200*/ LDG.E R18, [R2.64+0xc] ; /* 0x00000c0402127981 */
/* 0x000128000c1e1900 */
/*0210*/ LDG.E R20, [R2.64+0x10] ; /* 0x0000100402147981 */
/* 0x000128000c1e1900 */
/*0220*/ LDG.E R10, [R2.64+0x14] ; /* 0x00001404020a7981 */
/* 0x000128000c1e1900 */
/*0230*/ LDG.E R8, [R2.64+0x18] ; /* 0x0000180402087981 */
/* 0x000128000c1e1900 */
/*0240*/ LDG.E R29, [R2.64+0x1c] ; /* 0x00001c04021d7981 */
/* 0x000128000c1e1900 */
/*0250*/ LDG.E R27, [R2.64+0x20] ; /* 0x00002004021b7981 */
/* 0x000128000c1e1900 */
/*0260*/ LDG.E R25, [R2.64+0x24] ; /* 0x0000240402197981 */
/* 0x000128000c1e1900 */
/*0270*/ LDG.E R23, [R2.64+0x28] ; /* 0x0000280402177981 */
/* 0x000128000c1e1900 */
/*0280*/ LDG.E R21, [R2.64+0x2c] ; /* 0x00002c0402157981 */
/* 0x000128000c1e1900 */
/*0290*/ LDG.E R19, [R2.64+0x30] ; /* 0x0000300402137981 */
/* 0x000128000c1e1900 */
/*02a0*/ LDG.E R17, [R2.64+0x34] ; /* 0x0000340402117981 */
/* 0x000128000c1e1900 */
/*02b0*/ LDG.E R13, [R2.64+0x38] ; /* 0x00003804020d7981 */
/* 0x000128000c1e1900 */
/*02c0*/ LDG.E R15, [R2.64+0x3c] ; /* 0x00003c04020f7981 */
/* 0x000122000c1e1900 */
/*02d0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc40007ffe0ff */
/*02e0*/ IADD3 R11, R11, 0x10, RZ ; /* 0x000000100b0b7810 */
/* 0x000fe40007ffe0ff */
/*02f0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0300*/ IADD3 R2, P2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x001fc80007f5e0ff */
/*0310*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x000fe200017fe4ff */
/*0320*/ FFMA R9, R4, R12, R9 ; /* 0x0000000c04097223 */
/* 0x024fc80000000009 */
/*0330*/ FFMA R9, R4, R14, R9 ; /* 0x0000000e04097223 */
/* 0x008fc80000000009 */
/*0340*/ FFMA R9, R4, R16, R9 ; /* 0x0000001004097223 */
/* 0x010fc80000000009 */
/*0350*/ FFMA R9, R4, R18, R9 ; /* 0x0000001204097223 */
/* 0x000fc80000000009 */
/*0360*/ FFMA R9, R4, R20, R9 ; /* 0x0000001404097223 */
/* 0x000fc80000000009 */
/*0370*/ FFMA R9, R4, R10, R9 ; /* 0x0000000a04097223 */
/* 0x000fc80000000009 */
/*0380*/ FFMA R8, R4, R8, R9 ; /* 0x0000000804087223 */
/* 0x000fc80000000009 */
/*0390*/ FFMA R8, R4, R29, R8 ; /* 0x0000001d04087223 */
/* 0x000fc80000000008 */
/*03a0*/ FFMA R8, R4, R27, R8 ; /* 0x0000001b04087223 */
/* 0x000fc80000000008 */
/*03b0*/ FFMA R8, R4, R25, R8 ; /* 0x0000001904087223 */
/* 0x000fc80000000008 */
/*03c0*/ FFMA R8, R4, R23, R8 ; /* 0x0000001704087223 */
/* 0x000fc80000000008 */
/*03d0*/ FFMA R8, R4, R21, R8 ; /* 0x0000001504087223 */
/* 0x000fc80000000008 */
/*03e0*/ FFMA R8, R4, R19, R8 ; /* 0x0000001304087223 */
/* 0x000fc80000000008 */
/*03f0*/ FFMA R8, R4, R17, R8 ; /* 0x0000001104087223 */
/* 0x000fc80000000008 */
/*0400*/ FFMA R8, R4, R13, R8 ; /* 0x0000000d04087223 */
/* 0x000fc80000000008 */
/*0410*/ FFMA R9, R4, R15, R8 ; /* 0x0000000f04097223 */
/* 0x000fe20000000008 */
/*0420*/ @P1 BRA 0x1d0 ; /* 0xfffffda000001947 */
/* 0x000fea000383ffff */
/*0430*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0440*/ @!P1 BRA 0x5b0 ; /* 0x0000016000009947 */
/* 0x000fea0003800000 */
/*0450*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea8000c1e1900 */
/*0460*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x000ee8000c1e1900 */
/*0470*/ LDG.E R12, [R2.64+0x8] ; /* 0x00000804020c7981 */
/* 0x000128000c1e1900 */
/*0480*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c04020d7981 */
/* 0x000128000c1e1900 */
/*0490*/ LDG.E R14, [R2.64+0x10] ; /* 0x00001004020e7981 */
/* 0x000128000c1e1900 */
/*04a0*/ LDG.E R15, [R2.64+0x14] ; /* 0x00001404020f7981 */
/* 0x000128000c1e1900 */
/*04b0*/ LDG.E R16, [R2.64+0x18] ; /* 0x0000180402107981 */
/* 0x000128000c1e1900 */
/*04c0*/ LDG.E R17, [R2.64+0x1c] ; /* 0x00001c0402117981 */
/* 0x000122000c1e1900 */
/*04d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*04e0*/ IADD3 R11, R11, 0x8, RZ ; /* 0x000000080b0b7810 */
/* 0x000fe40007ffe0ff */
/*04f0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0500*/ FFMA R9, R4, R8, R9 ; /* 0x0000000804097223 */
/* 0x024fe20000000009 */
/*0510*/ IADD3 R8, P1, R2, 0x20, RZ ; /* 0x0000002002087810 */
/* 0x000fc60007f3e0ff */
/*0520*/ FFMA R9, R4.reuse, R10, R9 ; /* 0x0000000a04097223 */
/* 0x048fe20000000009 */
/*0530*/ MOV R2, R8 ; /* 0x0000000800027202 */
/* 0x001fe20000000f00 */
/*0540*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fe400008e0603 */
/*0550*/ FFMA R9, R4, R12, R9 ; /* 0x0000000c04097223 */
/* 0x010fc80000000009 */
/*0560*/ FFMA R9, R4, R13, R9 ; /* 0x0000000d04097223 */
/* 0x000fc80000000009 */
/*0570*/ FFMA R9, R4, R14, R9 ; /* 0x0000000e04097223 */
/* 0x000fc80000000009 */
/*0580*/ FFMA R9, R4, R15, R9 ; /* 0x0000000f04097223 */
/* 0x000fc80000000009 */
/*0590*/ FFMA R9, R4, R16, R9 ; /* 0x0000001004097223 */
/* 0x000fc80000000009 */
/*05a0*/ FFMA R9, R4, R17, R9 ; /* 0x0000001104097223 */
/* 0x000fe40000000009 */
/*05b0*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*05c0*/ @!P0 BRA 0x6d0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*05d0*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea8000c1e1900 */
/*05e0*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x000ee8000c1e1900 */
/*05f0*/ LDG.E R12, [R2.64+0x8] ; /* 0x00000804020c7981 */
/* 0x000128000c1e1900 */
/*0600*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c04020d7981 */
/* 0x000122000c1e1900 */
/*0610*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc40007ffe0ff */
/*0620*/ IADD3 R11, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fe40007ffe0ff */
/*0630*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0640*/ FFMA R9, R4, R8, R9 ; /* 0x0000000804097223 */
/* 0x024fe20000000009 */
/*0650*/ IADD3 R8, P1, R2, 0x10, RZ ; /* 0x0000001002087810 */
/* 0x000fc60007f3e0ff */
/*0660*/ FFMA R9, R4.reuse, R10, R9 ; /* 0x0000000a04097223 */
/* 0x048fe20000000009 */
/*0670*/ IADD3.X R15, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff0f7210 */
/* 0x000fe20000ffe4ff */
/*0680*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0008 */
/*0690*/ FFMA R9, R4, R12, R9 ; /* 0x0000000c04097223 */
/* 0x010fe20000000009 */
/*06a0*/ MOV R3, R15 ; /* 0x0000000f00037202 */
/* 0x000fc60000000f00 */
/*06b0*/ FFMA R9, R4, R13, R9 ; /* 0x0000000d04097223 */
/* 0x000fe20000000009 */
/*06c0*/ @P0 BRA 0x5d0 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*06d0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*06e0*/ @!P0 BRA 0x7a0 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*06f0*/ IMAD R2, R0, c[0x0][0x178], R11 ; /* 0x00005e0000027a24 */
/* 0x001fc800078e020b */
/*0700*/ IMAD.WIDE R2, R2, R7, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0207 */
/*0710*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fca0000000f00 */
/*0720*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fcc00078e0006 */
/*0730*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x0000a2000c1e1900 */
/*0740*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0750*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007f3e0ff */
/*0760*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f05270 */
/*0770*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x001fe20000ffe4ff */
/*0780*/ FFMA R9, R4, R2, R9 ; /* 0x0000000204097223 */
/* 0x024fd40000000009 */
/*0790*/ @P0 BRA 0x720 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*07a0*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0003e40000004800 */
/*07b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x001fe20000010000 */
/*07c0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*07d0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fe200078e0203 */
/*07e0*/ LDS R5, [R0.X4] ; /* 0x0000000000057984 */
/* 0x000e280000004800 */
/*07f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0800*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0810*/ BRA 0x810; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
// ERROR CHECKING MACROS //////////////////////////////////////////////////////
__global__ void mmKernel(float* popsIn, float* popsOut, float* mmm, int patches) {
int ii = threadIdx.x;
if (ii < patches) {
extern __shared__ float s[];
s[ii] = 0.0;
for (int jj = 0; jj < patches; jj++) {
s[ii] += popsIn[ii]*mmm[ii*patches + jj];
}
__syncthreads();
popsOut[ii] = s[ii];
}
} | .file "tmpxft_000c850a_00000000-6_mmKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8mmKernelPfS_S_iPfS_S_i
.type _Z32__device_stub__Z8mmKernelPfS_S_iPfS_S_i, @function
_Z32__device_stub__Z8mmKernelPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8mmKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z8mmKernelPfS_S_iPfS_S_i, .-_Z32__device_stub__Z8mmKernelPfS_S_iPfS_S_i
.globl _Z8mmKernelPfS_S_i
.type _Z8mmKernelPfS_S_i, @function
_Z8mmKernelPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8mmKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8mmKernelPfS_S_i, .-_Z8mmKernelPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8mmKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mmKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
// ERROR CHECKING MACROS //////////////////////////////////////////////////////
__global__ void mmKernel(float* popsIn, float* popsOut, float* mmm, int patches) {
int ii = threadIdx.x;
if (ii < patches) {
extern __shared__ float s[];
s[ii] = 0.0;
for (int jj = 0; jj < patches; jj++) {
s[ii] += popsIn[ii]*mmm[ii*patches + jj];
}
__syncthreads();
popsOut[ii] = s[ii];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
// ERROR CHECKING MACROS //////////////////////////////////////////////////////
__global__ void mmKernel(float* popsIn, float* popsOut, float* mmm, int patches) {
int ii = threadIdx.x;
if (ii < patches) {
extern __shared__ float s[];
s[ii] = 0.0;
for (int jj = 0; jj < patches; jj++) {
s[ii] += popsIn[ii]*mmm[ii*patches + jj];
}
__syncthreads();
popsOut[ii] = s[ii];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// ERROR CHECKING MACROS //////////////////////////////////////////////////////
__global__ void mmKernel(float* popsIn, float* popsOut, float* mmm, int patches) {
int ii = threadIdx.x;
if (ii < patches) {
extern __shared__ float s[];
s[ii] = 0.0;
for (int jj = 0; jj < patches; jj++) {
s[ii] += popsIn[ii]*mmm[ii*patches + jj];
}
__syncthreads();
popsOut[ii] = s[ii];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8mmKernelPfS_S_i
.globl _Z8mmKernelPfS_S_i
.p2align 8
.type _Z8mmKernelPfS_S_i,@function
_Z8mmKernelPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v2, 0
v_lshl_add_u32 v3, v0, 2, 0
s_cmp_lt_i32 s2, 1
ds_store_b32 v3, v2
s_cbranch_scc1 .LBB0_5
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x10
v_lshlrev_b32_e32 v1, 2, v0
ds_load_b32 v5, v3
s_waitcnt lgkmcnt(0)
global_load_b32 v4, v1, s[4:5]
v_mul_lo_u32 v1, v0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
.LBB0_3:
global_load_b32 v6, v[1:2], off
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v5, v4, v6
s_cbranch_scc0 .LBB0_3
ds_store_b32 v3, v5
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v3
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mmKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8mmKernelPfS_S_i, .Lfunc_end0-_Z8mmKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mmKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z8mmKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// ERROR CHECKING MACROS //////////////////////////////////////////////////////
__global__ void mmKernel(float* popsIn, float* popsOut, float* mmm, int patches) {
int ii = threadIdx.x;
if (ii < patches) {
extern __shared__ float s[];
s[ii] = 0.0;
for (int jj = 0; jj < patches; jj++) {
s[ii] += popsIn[ii]*mmm[ii*patches + jj];
}
__syncthreads();
popsOut[ii] = s[ii];
}
} | .text
.file "mmKernel.hip"
.globl _Z23__device_stub__mmKernelPfS_S_i # -- Begin function _Z23__device_stub__mmKernelPfS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__mmKernelPfS_S_i,@function
_Z23__device_stub__mmKernelPfS_S_i: # @_Z23__device_stub__mmKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8mmKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__mmKernelPfS_S_i, .Lfunc_end0-_Z23__device_stub__mmKernelPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mmKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8mmKernelPfS_S_i,@object # @_Z8mmKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z8mmKernelPfS_S_i
.p2align 3, 0x0
_Z8mmKernelPfS_S_i:
.quad _Z23__device_stub__mmKernelPfS_S_i
.size _Z8mmKernelPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8mmKernelPfS_S_i"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__mmKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8mmKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8mmKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ STS [R0.X4], RZ ; /* 0x000000ff00007388 */
/* 0x0001e20000004800 */
/*0050*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f01270 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*0070*/ @!P0 BRA 0x7b0 ; /* 0x0000073000008947 */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff067624 */
/* 0x001fe200078e00ff */
/*0090*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fc800000001ff */
/*00a0*/ IADD3 R5, R6, -0x1, RZ ; /* 0xffffffff06057810 */
/* 0x000fc80007ffe0ff */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe40003f06070 */
/*00c0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe200078e0207 */
/*00d0*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*00e0*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fc60000000f00 */
/*00f0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000162000c1e1900 */
/*0100*/ LOP3.LUT R5, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306057812 */
/* 0x000fca00078ec0ff */
/*0110*/ @!P0 BRA 0x6d0 ; /* 0x000005b000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0130*/ IMAD R2, R0, c[0x0][0x178], RZ ; /* 0x00005e0000027a24 */
/* 0x001fe200078e02ff */
/*0140*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0160*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*0170*/ IMAD.WIDE R2, R2, R7, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fd800078e0207 */
/*0180*/ @!P0 BRA 0x5d0 ; /* 0x0000044000008947 */
/* 0x000fea0003800000 */
/*0190*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01b0*/ @!P1 BRA 0x430 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01d0*/ LDG.E R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x0000a8000c1e1900 */
/*01e0*/ LDG.E R14, [R2.64+0x4] ; /* 0x00000404020e7981 */
/* 0x0000e8000c1e1900 */
/*01f0*/ LDG.E R16, [R2.64+0x8] ; /* 0x0000080402107981 */
/* 0x000128000c1e1900 */
/*0200*/ LDG.E R18, [R2.64+0xc] ; /* 0x00000c0402127981 */
/* 0x000128000c1e1900 */
/*0210*/ LDG.E R20, [R2.64+0x10] ; /* 0x0000100402147981 */
/* 0x000128000c1e1900 */
/*0220*/ LDG.E R10, [R2.64+0x14] ; /* 0x00001404020a7981 */
/* 0x000128000c1e1900 */
/*0230*/ LDG.E R8, [R2.64+0x18] ; /* 0x0000180402087981 */
/* 0x000128000c1e1900 */
/*0240*/ LDG.E R29, [R2.64+0x1c] ; /* 0x00001c04021d7981 */
/* 0x000128000c1e1900 */
/*0250*/ LDG.E R27, [R2.64+0x20] ; /* 0x00002004021b7981 */
/* 0x000128000c1e1900 */
/*0260*/ LDG.E R25, [R2.64+0x24] ; /* 0x0000240402197981 */
/* 0x000128000c1e1900 */
/*0270*/ LDG.E R23, [R2.64+0x28] ; /* 0x0000280402177981 */
/* 0x000128000c1e1900 */
/*0280*/ LDG.E R21, [R2.64+0x2c] ; /* 0x00002c0402157981 */
/* 0x000128000c1e1900 */
/*0290*/ LDG.E R19, [R2.64+0x30] ; /* 0x0000300402137981 */
/* 0x000128000c1e1900 */
/*02a0*/ LDG.E R17, [R2.64+0x34] ; /* 0x0000340402117981 */
/* 0x000128000c1e1900 */
/*02b0*/ LDG.E R13, [R2.64+0x38] ; /* 0x00003804020d7981 */
/* 0x000128000c1e1900 */
/*02c0*/ LDG.E R15, [R2.64+0x3c] ; /* 0x00003c04020f7981 */
/* 0x000122000c1e1900 */
/*02d0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc40007ffe0ff */
/*02e0*/ IADD3 R11, R11, 0x10, RZ ; /* 0x000000100b0b7810 */
/* 0x000fe40007ffe0ff */
/*02f0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0300*/ IADD3 R2, P2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x001fc80007f5e0ff */
/*0310*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x000fe200017fe4ff */
/*0320*/ FFMA R9, R4, R12, R9 ; /* 0x0000000c04097223 */
/* 0x024fc80000000009 */
/*0330*/ FFMA R9, R4, R14, R9 ; /* 0x0000000e04097223 */
/* 0x008fc80000000009 */
/*0340*/ FFMA R9, R4, R16, R9 ; /* 0x0000001004097223 */
/* 0x010fc80000000009 */
/*0350*/ FFMA R9, R4, R18, R9 ; /* 0x0000001204097223 */
/* 0x000fc80000000009 */
/*0360*/ FFMA R9, R4, R20, R9 ; /* 0x0000001404097223 */
/* 0x000fc80000000009 */
/*0370*/ FFMA R9, R4, R10, R9 ; /* 0x0000000a04097223 */
/* 0x000fc80000000009 */
/*0380*/ FFMA R8, R4, R8, R9 ; /* 0x0000000804087223 */
/* 0x000fc80000000009 */
/*0390*/ FFMA R8, R4, R29, R8 ; /* 0x0000001d04087223 */
/* 0x000fc80000000008 */
/*03a0*/ FFMA R8, R4, R27, R8 ; /* 0x0000001b04087223 */
/* 0x000fc80000000008 */
/*03b0*/ FFMA R8, R4, R25, R8 ; /* 0x0000001904087223 */
/* 0x000fc80000000008 */
/*03c0*/ FFMA R8, R4, R23, R8 ; /* 0x0000001704087223 */
/* 0x000fc80000000008 */
/*03d0*/ FFMA R8, R4, R21, R8 ; /* 0x0000001504087223 */
/* 0x000fc80000000008 */
/*03e0*/ FFMA R8, R4, R19, R8 ; /* 0x0000001304087223 */
/* 0x000fc80000000008 */
/*03f0*/ FFMA R8, R4, R17, R8 ; /* 0x0000001104087223 */
/* 0x000fc80000000008 */
/*0400*/ FFMA R8, R4, R13, R8 ; /* 0x0000000d04087223 */
/* 0x000fc80000000008 */
/*0410*/ FFMA R9, R4, R15, R8 ; /* 0x0000000f04097223 */
/* 0x000fe20000000008 */
/*0420*/ @P1 BRA 0x1d0 ; /* 0xfffffda000001947 */
/* 0x000fea000383ffff */
/*0430*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0440*/ @!P1 BRA 0x5b0 ; /* 0x0000016000009947 */
/* 0x000fea0003800000 */
/*0450*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea8000c1e1900 */
/*0460*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x000ee8000c1e1900 */
/*0470*/ LDG.E R12, [R2.64+0x8] ; /* 0x00000804020c7981 */
/* 0x000128000c1e1900 */
/*0480*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c04020d7981 */
/* 0x000128000c1e1900 */
/*0490*/ LDG.E R14, [R2.64+0x10] ; /* 0x00001004020e7981 */
/* 0x000128000c1e1900 */
/*04a0*/ LDG.E R15, [R2.64+0x14] ; /* 0x00001404020f7981 */
/* 0x000128000c1e1900 */
/*04b0*/ LDG.E R16, [R2.64+0x18] ; /* 0x0000180402107981 */
/* 0x000128000c1e1900 */
/*04c0*/ LDG.E R17, [R2.64+0x1c] ; /* 0x00001c0402117981 */
/* 0x000122000c1e1900 */
/*04d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*04e0*/ IADD3 R11, R11, 0x8, RZ ; /* 0x000000080b0b7810 */
/* 0x000fe40007ffe0ff */
/*04f0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0500*/ FFMA R9, R4, R8, R9 ; /* 0x0000000804097223 */
/* 0x024fe20000000009 */
/*0510*/ IADD3 R8, P1, R2, 0x20, RZ ; /* 0x0000002002087810 */
/* 0x000fc60007f3e0ff */
/*0520*/ FFMA R9, R4.reuse, R10, R9 ; /* 0x0000000a04097223 */
/* 0x048fe20000000009 */
/*0530*/ MOV R2, R8 ; /* 0x0000000800027202 */
/* 0x001fe20000000f00 */
/*0540*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fe400008e0603 */
/*0550*/ FFMA R9, R4, R12, R9 ; /* 0x0000000c04097223 */
/* 0x010fc80000000009 */
/*0560*/ FFMA R9, R4, R13, R9 ; /* 0x0000000d04097223 */
/* 0x000fc80000000009 */
/*0570*/ FFMA R9, R4, R14, R9 ; /* 0x0000000e04097223 */
/* 0x000fc80000000009 */
/*0580*/ FFMA R9, R4, R15, R9 ; /* 0x0000000f04097223 */
/* 0x000fc80000000009 */
/*0590*/ FFMA R9, R4, R16, R9 ; /* 0x0000001004097223 */
/* 0x000fc80000000009 */
/*05a0*/ FFMA R9, R4, R17, R9 ; /* 0x0000001104097223 */
/* 0x000fe40000000009 */
/*05b0*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*05c0*/ @!P0 BRA 0x6d0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*05d0*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea8000c1e1900 */
/*05e0*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x000ee8000c1e1900 */
/*05f0*/ LDG.E R12, [R2.64+0x8] ; /* 0x00000804020c7981 */
/* 0x000128000c1e1900 */
/*0600*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c04020d7981 */
/* 0x000122000c1e1900 */
/*0610*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc40007ffe0ff */
/*0620*/ IADD3 R11, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fe40007ffe0ff */
/*0630*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0640*/ FFMA R9, R4, R8, R9 ; /* 0x0000000804097223 */
/* 0x024fe20000000009 */
/*0650*/ IADD3 R8, P1, R2, 0x10, RZ ; /* 0x0000001002087810 */
/* 0x000fc60007f3e0ff */
/*0660*/ FFMA R9, R4.reuse, R10, R9 ; /* 0x0000000a04097223 */
/* 0x048fe20000000009 */
/*0670*/ IADD3.X R15, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff0f7210 */
/* 0x000fe20000ffe4ff */
/*0680*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0008 */
/*0690*/ FFMA R9, R4, R12, R9 ; /* 0x0000000c04097223 */
/* 0x010fe20000000009 */
/*06a0*/ MOV R3, R15 ; /* 0x0000000f00037202 */
/* 0x000fc60000000f00 */
/*06b0*/ FFMA R9, R4, R13, R9 ; /* 0x0000000d04097223 */
/* 0x000fe20000000009 */
/*06c0*/ @P0 BRA 0x5d0 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*06d0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*06e0*/ @!P0 BRA 0x7a0 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*06f0*/ IMAD R2, R0, c[0x0][0x178], R11 ; /* 0x00005e0000027a24 */
/* 0x001fc800078e020b */
/*0700*/ IMAD.WIDE R2, R2, R7, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0207 */
/*0710*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fca0000000f00 */
/*0720*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fcc00078e0006 */
/*0730*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x0000a2000c1e1900 */
/*0740*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0750*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007f3e0ff */
/*0760*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f05270 */
/*0770*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x001fe20000ffe4ff */
/*0780*/ FFMA R9, R4, R2, R9 ; /* 0x0000000204097223 */
/* 0x024fd40000000009 */
/*0790*/ @P0 BRA 0x720 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*07a0*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0003e40000004800 */
/*07b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x001fe20000010000 */
/*07c0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*07d0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fe200078e0203 */
/*07e0*/ LDS R5, [R0.X4] ; /* 0x0000000000057984 */
/* 0x000e280000004800 */
/*07f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0800*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0810*/ BRA 0x810; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8mmKernelPfS_S_i
.globl _Z8mmKernelPfS_S_i
.p2align 8
.type _Z8mmKernelPfS_S_i,@function
_Z8mmKernelPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v2, 0
v_lshl_add_u32 v3, v0, 2, 0
s_cmp_lt_i32 s2, 1
ds_store_b32 v3, v2
s_cbranch_scc1 .LBB0_5
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x10
v_lshlrev_b32_e32 v1, 2, v0
ds_load_b32 v5, v3
s_waitcnt lgkmcnt(0)
global_load_b32 v4, v1, s[4:5]
v_mul_lo_u32 v1, v0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
.LBB0_3:
global_load_b32 v6, v[1:2], off
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v5, v4, v6
s_cbranch_scc0 .LBB0_3
ds_store_b32 v3, v5
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v3
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mmKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8mmKernelPfS_S_i, .Lfunc_end0-_Z8mmKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mmKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z8mmKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c850a_00000000-6_mmKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8mmKernelPfS_S_iPfS_S_i
.type _Z32__device_stub__Z8mmKernelPfS_S_iPfS_S_i, @function
_Z32__device_stub__Z8mmKernelPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8mmKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z8mmKernelPfS_S_iPfS_S_i, .-_Z32__device_stub__Z8mmKernelPfS_S_iPfS_S_i
.globl _Z8mmKernelPfS_S_i
.type _Z8mmKernelPfS_S_i, @function
_Z8mmKernelPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8mmKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8mmKernelPfS_S_i, .-_Z8mmKernelPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8mmKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mmKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mmKernel.hip"
.globl _Z23__device_stub__mmKernelPfS_S_i # -- Begin function _Z23__device_stub__mmKernelPfS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__mmKernelPfS_S_i,@function
_Z23__device_stub__mmKernelPfS_S_i: # @_Z23__device_stub__mmKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8mmKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__mmKernelPfS_S_i, .Lfunc_end0-_Z23__device_stub__mmKernelPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mmKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8mmKernelPfS_S_i,@object # @_Z8mmKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z8mmKernelPfS_S_i
.p2align 3, 0x0
_Z8mmKernelPfS_S_i:
.quad _Z23__device_stub__mmKernelPfS_S_i
.size _Z8mmKernelPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8mmKernelPfS_S_i"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__mmKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8mmKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define BLOCK_SIZE 16
__global__ void kernel_shared(float * a, float * b, int n, float * c)
{
int bx = blockIdx.x, by = blockIdx.y;
int tx = threadIdx.x, ty = threadIdx.y;
int aBegin = n * BLOCK_SIZE * by;
int aEnd = aBegin + n - 1;
int bBegin = BLOCK_SIZE * bx;
int aStep = BLOCK_SIZE, bStep = BLOCK_SIZE * n;
float sum = 0.0f;
__shared__ float as[BLOCK_SIZE][BLOCK_SIZE + 1];
__shared__ float bs[BLOCK_SIZE][BLOCK_SIZE + 1];
for (int ia = aBegin, ib = bBegin; ia <= aEnd; ia += aStep, ib += bStep)
{
as[tx][ty] = a[ia + n * ty + tx];
bs[tx][ty] = b[ib + n * ty + tx];
__syncthreads(); // Synchronize to make sure the matrices are loaded
for (int k = 0; k < BLOCK_SIZE; k++) sum += as[k][ty] * bs[tx][k];
__syncthreads(); // Synchronize to make sure submatrices not needed
}
c[n * BLOCK_SIZE * by + BLOCK_SIZE * bx + n * ty + tx] = sum;
}
__global__ void kernel_shared_1(float * a, float * b, int n, float * c)
{
int bx = blockIdx.x, by = blockIdx.y;
int tx = threadIdx.x, ty = threadIdx.y;
int aBegin = n * BLOCK_SIZE * by;
int aEnd = aBegin + n - 1;
int bBegin = BLOCK_SIZE * bx;
int aStep = BLOCK_SIZE, bStep = BLOCK_SIZE * n;
float sum = 0.0f;
for (int ia = aBegin, ib = bBegin; ia <= aEnd; ia += aStep, ib += bStep)
{
__shared__ float as[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float bs[BLOCK_SIZE][BLOCK_SIZE];
as[ty][tx] = a[ia + n * ty + tx];
bs[ty][tx] = b[ib + n * ty + tx];
__syncthreads(); // Synchronize to make sure the matrices are loaded
for (int k = 0; k < BLOCK_SIZE; k++) sum += as[ty][k] * bs[k][tx];
__syncthreads(); // Synchronize to make sure submatrices not needed
}
c[n * BLOCK_SIZE * by + BLOCK_SIZE * bx + n * ty + tx] = sum;
}
__global__ void kernel_global(float * a, float * b, int n, float * c)
{
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
float sum = 0.0f;
int ia = n * BLOCK_SIZE * by + n * ty;
int ib = BLOCK_SIZE * bx + tx;
int ic = n * BLOCK_SIZE * by + BLOCK_SIZE * bx;
for (int k = 0; k < n; k++) sum += a[ia + k] * b[ib + k*n];
c[ic + n * ty + tx] = sum;
}
int main()
{
int N = 1024;
int m, n, k;
float CPUstart, CPUstop;
float timerValueGPU, timerValueCPU;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
int numBytes = N*N*sizeof(float);
float *devA, *devB, *devC, *a, *b, *c, *cc, *bT, *aT;
a = (float*)malloc(numBytes);
b = (float*)malloc(numBytes);
bT = (float*)malloc(numBytes);
aT = (float*)malloc(numBytes);
c = (float*)malloc(numBytes);
cc = (float*)malloc(numBytes);
for (n = 0; n<N; n++)
{
for (m = 0; m<N; m++)
{
a[m + n*N] = 2.0f*m + n;
b[m + n*N] = m - n;
aT[m + n*N] = m + n*2.0f;
bT[m + n*N] = n - m;
}
}
cudaMalloc((void**)&devA, numBytes); // allocate DRAM
cudaMalloc((void**)&devB, numBytes); // allocate DRAM
cudaMalloc((void**)&devC, numBytes); // allocate DRAM
dim3 threads(BLOCK_SIZE, BLOCK_SIZE);
dim3 blocks(N / threads.x, N / threads.y);
// DEVICE ------------------------------------------------------
cudaEventRecord(start, 0);
cudaMemcpy(devA, a, numBytes, cudaMemcpyHostToDevice);
cudaMemcpy(devB, b, numBytes, cudaMemcpyHostToDevice);
kernel_shared <<<blocks, threads >>> (devA, devB, N, devC);
//kernel_shared_1 << <blocks, threads >> > (devA, devB, N, devC);
//kernel_global <<< blocks, threads >>> ( devA, devB, N, devC );
cudaMemcpy(c, devC, numBytes, cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&timerValueGPU, start, stop);
printf("\n GPU calculation time %f msec\n", timerValueGPU);
//---------------------------------------------------------------
// HOST ---------------------------------------------------------
CPUstart = clock();
for (n = 0; n<N; n++)
{
for (m = 0; m<N; m++)
{
cc[m + n*N] = 0.f;
for (k = 0; k<N; k++) cc[m + n*N] += a[k + n*N] * bT[k + m*N]; // T
// for(k=0;k<N;k++) cc[m+n*N]+=a[k+n*N]*b[m+k*N]; //
}
}
CPUstop = clock();
timerValueCPU = 1000.*(CPUstop - CPUstart) / CLOCKS_PER_SEC;
printf("CPU time : %.3f ms\n", timerValueCPU);
printf("Rate : %.3f \n", timerValueCPU / timerValueGPU);
//---------------------------------------------------------------
cudaFree(devA);
cudaFree(devB);
cudaFree(devC);
free(a);
free(b);
free(bT);
free(aT);
free(c);
free(cc);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | .file "tmpxft_0005c3db_00000000-6_Example5.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z13kernel_sharedPfS_iS_PfS_iS_
.type _Z38__device_stub__Z13kernel_sharedPfS_iS_PfS_iS_, @function
_Z38__device_stub__Z13kernel_sharedPfS_iS_PfS_iS_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13kernel_sharedPfS_iS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z38__device_stub__Z13kernel_sharedPfS_iS_PfS_iS_, .-_Z38__device_stub__Z13kernel_sharedPfS_iS_PfS_iS_
.globl _Z13kernel_sharedPfS_iS_
.type _Z13kernel_sharedPfS_iS_, @function
_Z13kernel_sharedPfS_iS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13kernel_sharedPfS_iS_PfS_iS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z13kernel_sharedPfS_iS_, .-_Z13kernel_sharedPfS_iS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "\n GPU calculation time %f msec\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "CPU time : %.3f ms\n"
.LC5:
.string "Rate : %.3f \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %r13
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movl $4194304, %edi
call malloc@PLT
movq %rax, (%rsp)
movl $4194304, %edi
call malloc@PLT
movq %rax, %r15
movl $4194304, %edi
call malloc@PLT
movq %rax, %r14
movq %rbp, %rbx
movq %r13, %r8
movq (%rsp), %rdi
movq %r12, %rsi
movq %rbp, %rcx
movl $0, %r9d
.L12:
pxor %xmm2, %xmm2
cvtsi2ssl %r9d, %xmm2
movl %r9d, %edx
movaps %xmm2, %xmm3
addss %xmm2, %xmm3
movl $0, %eax
.L13:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movaps %xmm0, %xmm1
addss %xmm0, %xmm1
addss %xmm2, %xmm1
movss %xmm1, (%rcx,%rax,4)
movl %edx, %r10d
negl %r10d
pxor %xmm1, %xmm1
cvtsi2ssl %r10d, %xmm1
movss %xmm1, (%r8,%rax,4)
addss %xmm3, %xmm0
movss %xmm0, (%rdi,%rax,4)
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%rsi,%rax,4)
addq $1, %rax
subl $1, %edx
cmpq $1024, %rax
jne .L13
addl $1, %r9d
addq $4096, %rcx
addq $4096, %r8
addq $4096, %rdi
addq $4096, %rsi
cmpl $1024, %r9d
jne .L12
leaq 40(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $1, 72(%rsp)
movl $64, 76(%rsp)
movl $64, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %r13, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 64(%rsp)
movl $16, 68(%rsp)
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L15:
movl $2, %ecx
movl $4194304, %edx
movq 56(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call clock@PLT
pxor %xmm5, %xmm5
cvtsi2ssq %rax, %xmm5
movss %xmm5, 12(%rsp)
movq %r14, %r8
leaq 4194304(%rbp), %r9
jmp .L16
.L25:
movq 56(%rsp), %rcx
movl $1024, %edx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z38__device_stub__Z13kernel_sharedPfS_iS_PfS_iS_
jmp .L15
.L27:
movss %xmm1, (%rdi)
addq $4, %rsi
addl $1024, %ecx
addq $4096, %rdx
cmpl $1048576, %ecx
je .L26
.L18:
movq %rsi, %rdi
movl $0, %eax
pxor %xmm1, %xmm1
.L17:
movss (%rbx,%rax), %xmm0
mulss (%rdx,%rax), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
cmpq $4096, %rax
jne .L17
jmp .L27
.L26:
addq $4096, %rbx
addq $4096, %r8
cmpq %r9, %rbx
je .L19
.L16:
movq %r12, %rdx
movq %r8, %rsi
movl $0, %ecx
jmp .L18
.L19:
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
subss 12(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LC2(%rip), %xmm0
divsd .LC3(%rip), %xmm0
pxor %xmm4, %xmm4
cvtsd2ss %xmm0, %xmm4
movss %xmm4, 12(%rsp)
pxor %xmm0, %xmm0
cvtss2sd %xmm4, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 12(%rsp), %xmm4
divss 20(%rsp), %xmm4
pxor %xmm0, %xmm0
cvtss2sd %xmm4, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z40__device_stub__Z15kernel_shared_1PfS_iS_PfS_iS_
.type _Z40__device_stub__Z15kernel_shared_1PfS_iS_PfS_iS_, @function
_Z40__device_stub__Z15kernel_shared_1PfS_iS_PfS_iS_:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15kernel_shared_1PfS_iS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z40__device_stub__Z15kernel_shared_1PfS_iS_PfS_iS_, .-_Z40__device_stub__Z15kernel_shared_1PfS_iS_PfS_iS_
.globl _Z15kernel_shared_1PfS_iS_
.type _Z15kernel_shared_1PfS_iS_, @function
_Z15kernel_shared_1PfS_iS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15kernel_shared_1PfS_iS_PfS_iS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z15kernel_shared_1PfS_iS_, .-_Z15kernel_shared_1PfS_iS_
.globl _Z38__device_stub__Z13kernel_globalPfS_iS_PfS_iS_
.type _Z38__device_stub__Z13kernel_globalPfS_iS_PfS_iS_, @function
_Z38__device_stub__Z13kernel_globalPfS_iS_PfS_iS_:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13kernel_globalPfS_iS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z38__device_stub__Z13kernel_globalPfS_iS_PfS_iS_, .-_Z38__device_stub__Z13kernel_globalPfS_iS_PfS_iS_
.globl _Z13kernel_globalPfS_iS_
.type _Z13kernel_globalPfS_iS_, @function
_Z13kernel_globalPfS_iS_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13kernel_globalPfS_iS_PfS_iS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z13kernel_globalPfS_iS_, .-_Z13kernel_globalPfS_iS_
.section .rodata.str1.1
.LC6:
.string "_Z13kernel_globalPfS_iS_"
.LC7:
.string "_Z15kernel_shared_1PfS_iS_"
.LC8:
.string "_Z13kernel_sharedPfS_iS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kernel_globalPfS_iS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z15kernel_shared_1PfS_iS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kernel_sharedPfS_iS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1083129856
.align 8
.LC3:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define BLOCK_SIZE 16
__global__ void kernel_shared(float * a, float * b, int n, float * c)
{
int bx = blockIdx.x, by = blockIdx.y;
int tx = threadIdx.x, ty = threadIdx.y;
int aBegin = n * BLOCK_SIZE * by;
int aEnd = aBegin + n - 1;
int bBegin = BLOCK_SIZE * bx;
int aStep = BLOCK_SIZE, bStep = BLOCK_SIZE * n;
float sum = 0.0f;
__shared__ float as[BLOCK_SIZE][BLOCK_SIZE + 1];
__shared__ float bs[BLOCK_SIZE][BLOCK_SIZE + 1];
for (int ia = aBegin, ib = bBegin; ia <= aEnd; ia += aStep, ib += bStep)
{
as[tx][ty] = a[ia + n * ty + tx];
bs[tx][ty] = b[ib + n * ty + tx];
__syncthreads(); // Synchronize to make sure the matrices are loaded
for (int k = 0; k < BLOCK_SIZE; k++) sum += as[k][ty] * bs[tx][k];
__syncthreads(); // Synchronize to make sure submatrices not needed
}
c[n * BLOCK_SIZE * by + BLOCK_SIZE * bx + n * ty + tx] = sum;
}
__global__ void kernel_shared_1(float * a, float * b, int n, float * c)
{
int bx = blockIdx.x, by = blockIdx.y;
int tx = threadIdx.x, ty = threadIdx.y;
int aBegin = n * BLOCK_SIZE * by;
int aEnd = aBegin + n - 1;
int bBegin = BLOCK_SIZE * bx;
int aStep = BLOCK_SIZE, bStep = BLOCK_SIZE * n;
float sum = 0.0f;
for (int ia = aBegin, ib = bBegin; ia <= aEnd; ia += aStep, ib += bStep)
{
__shared__ float as[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float bs[BLOCK_SIZE][BLOCK_SIZE];
as[ty][tx] = a[ia + n * ty + tx];
bs[ty][tx] = b[ib + n * ty + tx];
__syncthreads(); // Synchronize to make sure the matrices are loaded
for (int k = 0; k < BLOCK_SIZE; k++) sum += as[ty][k] * bs[k][tx];
__syncthreads(); // Synchronize to make sure submatrices not needed
}
c[n * BLOCK_SIZE * by + BLOCK_SIZE * bx + n * ty + tx] = sum;
}
__global__ void kernel_global(float * a, float * b, int n, float * c)
{
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
float sum = 0.0f;
int ia = n * BLOCK_SIZE * by + n * ty;
int ib = BLOCK_SIZE * bx + tx;
int ic = n * BLOCK_SIZE * by + BLOCK_SIZE * bx;
for (int k = 0; k < n; k++) sum += a[ia + k] * b[ib + k*n];
c[ic + n * ty + tx] = sum;
}
int main()
{
int N = 1024;
int m, n, k;
float CPUstart, CPUstop;
float timerValueGPU, timerValueCPU;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
int numBytes = N*N*sizeof(float);
float *devA, *devB, *devC, *a, *b, *c, *cc, *bT, *aT;
a = (float*)malloc(numBytes);
b = (float*)malloc(numBytes);
bT = (float*)malloc(numBytes);
aT = (float*)malloc(numBytes);
c = (float*)malloc(numBytes);
cc = (float*)malloc(numBytes);
for (n = 0; n<N; n++)
{
for (m = 0; m<N; m++)
{
a[m + n*N] = 2.0f*m + n;
b[m + n*N] = m - n;
aT[m + n*N] = m + n*2.0f;
bT[m + n*N] = n - m;
}
}
cudaMalloc((void**)&devA, numBytes); // allocate DRAM
cudaMalloc((void**)&devB, numBytes); // allocate DRAM
cudaMalloc((void**)&devC, numBytes); // allocate DRAM
dim3 threads(BLOCK_SIZE, BLOCK_SIZE);
dim3 blocks(N / threads.x, N / threads.y);
// DEVICE ------------------------------------------------------
cudaEventRecord(start, 0);
cudaMemcpy(devA, a, numBytes, cudaMemcpyHostToDevice);
cudaMemcpy(devB, b, numBytes, cudaMemcpyHostToDevice);
kernel_shared <<<blocks, threads >>> (devA, devB, N, devC);
//kernel_shared_1 << <blocks, threads >> > (devA, devB, N, devC);
//kernel_global <<< blocks, threads >>> ( devA, devB, N, devC );
cudaMemcpy(c, devC, numBytes, cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&timerValueGPU, start, stop);
printf("\n GPU calculation time %f msec\n", timerValueGPU);
//---------------------------------------------------------------
// HOST ---------------------------------------------------------
CPUstart = clock();
for (n = 0; n<N; n++)
{
for (m = 0; m<N; m++)
{
cc[m + n*N] = 0.f;
for (k = 0; k<N; k++) cc[m + n*N] += a[k + n*N] * bT[k + m*N]; // T
// for(k=0;k<N;k++) cc[m+n*N]+=a[k+n*N]*b[m+k*N]; //
}
}
CPUstop = clock();
timerValueCPU = 1000.*(CPUstop - CPUstart) / CLOCKS_PER_SEC;
printf("CPU time : %.3f ms\n", timerValueCPU);
printf("Rate : %.3f \n", timerValueCPU / timerValueGPU);
//---------------------------------------------------------------
cudaFree(devA);
cudaFree(devB);
cudaFree(devC);
free(a);
free(b);
free(bT);
free(aT);
free(c);
free(cc);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define BLOCK_SIZE 16
__global__ void kernel_shared(float * a, float * b, int n, float * c)
{
int bx = blockIdx.x, by = blockIdx.y;
int tx = threadIdx.x, ty = threadIdx.y;
int aBegin = n * BLOCK_SIZE * by;
int aEnd = aBegin + n - 1;
int bBegin = BLOCK_SIZE * bx;
int aStep = BLOCK_SIZE, bStep = BLOCK_SIZE * n;
float sum = 0.0f;
__shared__ float as[BLOCK_SIZE][BLOCK_SIZE + 1];
__shared__ float bs[BLOCK_SIZE][BLOCK_SIZE + 1];
for (int ia = aBegin, ib = bBegin; ia <= aEnd; ia += aStep, ib += bStep)
{
as[tx][ty] = a[ia + n * ty + tx];
bs[tx][ty] = b[ib + n * ty + tx];
__syncthreads(); // Synchronize to make sure the matrices are loaded
for (int k = 0; k < BLOCK_SIZE; k++) sum += as[k][ty] * bs[tx][k];
__syncthreads(); // Synchronize to make sure submatrices not needed
}
c[n * BLOCK_SIZE * by + BLOCK_SIZE * bx + n * ty + tx] = sum;
}
__global__ void kernel_shared_1(float * a, float * b, int n, float * c)
{
int bx = blockIdx.x, by = blockIdx.y;
int tx = threadIdx.x, ty = threadIdx.y;
int aBegin = n * BLOCK_SIZE * by;
int aEnd = aBegin + n - 1;
int bBegin = BLOCK_SIZE * bx;
int aStep = BLOCK_SIZE, bStep = BLOCK_SIZE * n;
float sum = 0.0f;
for (int ia = aBegin, ib = bBegin; ia <= aEnd; ia += aStep, ib += bStep)
{
__shared__ float as[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float bs[BLOCK_SIZE][BLOCK_SIZE];
as[ty][tx] = a[ia + n * ty + tx];
bs[ty][tx] = b[ib + n * ty + tx];
__syncthreads(); // Synchronize to make sure the matrices are loaded
for (int k = 0; k < BLOCK_SIZE; k++) sum += as[ty][k] * bs[k][tx];
__syncthreads(); // Synchronize to make sure submatrices not needed
}
c[n * BLOCK_SIZE * by + BLOCK_SIZE * bx + n * ty + tx] = sum;
}
__global__ void kernel_global(float * a, float * b, int n, float * c)
{
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
float sum = 0.0f;
int ia = n * BLOCK_SIZE * by + n * ty;
int ib = BLOCK_SIZE * bx + tx;
int ic = n * BLOCK_SIZE * by + BLOCK_SIZE * bx;
for (int k = 0; k < n; k++) sum += a[ia + k] * b[ib + k*n];
c[ic + n * ty + tx] = sum;
}
int main()
{
int N = 1024;
int m, n, k;
float CPUstart, CPUstop;
float timerValueGPU, timerValueCPU;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
int numBytes = N*N*sizeof(float);
float *devA, *devB, *devC, *a, *b, *c, *cc, *bT, *aT;
a = (float*)malloc(numBytes);
b = (float*)malloc(numBytes);
bT = (float*)malloc(numBytes);
aT = (float*)malloc(numBytes);
c = (float*)malloc(numBytes);
cc = (float*)malloc(numBytes);
for (n = 0; n<N; n++)
{
for (m = 0; m<N; m++)
{
a[m + n*N] = 2.0f*m + n;
b[m + n*N] = m - n;
aT[m + n*N] = m + n*2.0f;
bT[m + n*N] = n - m;
}
}
hipMalloc((void**)&devA, numBytes); // allocate DRAM
hipMalloc((void**)&devB, numBytes); // allocate DRAM
hipMalloc((void**)&devC, numBytes); // allocate DRAM
dim3 threads(BLOCK_SIZE, BLOCK_SIZE);
dim3 blocks(N / threads.x, N / threads.y);
// DEVICE ------------------------------------------------------
hipEventRecord(start, 0);
hipMemcpy(devA, a, numBytes, hipMemcpyHostToDevice);
hipMemcpy(devB, b, numBytes, hipMemcpyHostToDevice);
kernel_shared <<<blocks, threads >>> (devA, devB, N, devC);
//kernel_shared_1 << <blocks, threads >> > (devA, devB, N, devC);
//kernel_global <<< blocks, threads >>> ( devA, devB, N, devC );
hipMemcpy(c, devC, numBytes, hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&timerValueGPU, start, stop);
printf("\n GPU calculation time %f msec\n", timerValueGPU);
//---------------------------------------------------------------
// HOST ---------------------------------------------------------
CPUstart = clock();
for (n = 0; n<N; n++)
{
for (m = 0; m<N; m++)
{
cc[m + n*N] = 0.f;
for (k = 0; k<N; k++) cc[m + n*N] += a[k + n*N] * bT[k + m*N]; // T
// for(k=0;k<N;k++) cc[m+n*N]+=a[k+n*N]*b[m+k*N]; //
}
}
CPUstop = clock();
timerValueCPU = 1000.*(CPUstop - CPUstart) / CLOCKS_PER_SEC;
printf("CPU time : %.3f ms\n", timerValueCPU);
printf("Rate : %.3f \n", timerValueCPU / timerValueGPU);
//---------------------------------------------------------------
hipFree(devA);
hipFree(devB);
hipFree(devC);
free(a);
free(b);
free(bT);
free(aT);
free(c);
free(cc);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define BLOCK_SIZE 16
__global__ void kernel_shared(float * a, float * b, int n, float * c)
{
int bx = blockIdx.x, by = blockIdx.y;
int tx = threadIdx.x, ty = threadIdx.y;
int aBegin = n * BLOCK_SIZE * by;
int aEnd = aBegin + n - 1;
int bBegin = BLOCK_SIZE * bx;
int aStep = BLOCK_SIZE, bStep = BLOCK_SIZE * n;
float sum = 0.0f;
__shared__ float as[BLOCK_SIZE][BLOCK_SIZE + 1];
__shared__ float bs[BLOCK_SIZE][BLOCK_SIZE + 1];
for (int ia = aBegin, ib = bBegin; ia <= aEnd; ia += aStep, ib += bStep)
{
as[tx][ty] = a[ia + n * ty + tx];
bs[tx][ty] = b[ib + n * ty + tx];
__syncthreads(); // Synchronize to make sure the matrices are loaded
for (int k = 0; k < BLOCK_SIZE; k++) sum += as[k][ty] * bs[tx][k];
__syncthreads(); // Synchronize to make sure submatrices not needed
}
c[n * BLOCK_SIZE * by + BLOCK_SIZE * bx + n * ty + tx] = sum;
}
__global__ void kernel_shared_1(float * a, float * b, int n, float * c)
{
int bx = blockIdx.x, by = blockIdx.y;
int tx = threadIdx.x, ty = threadIdx.y;
int aBegin = n * BLOCK_SIZE * by;
int aEnd = aBegin + n - 1;
int bBegin = BLOCK_SIZE * bx;
int aStep = BLOCK_SIZE, bStep = BLOCK_SIZE * n;
float sum = 0.0f;
for (int ia = aBegin, ib = bBegin; ia <= aEnd; ia += aStep, ib += bStep)
{
__shared__ float as[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float bs[BLOCK_SIZE][BLOCK_SIZE];
as[ty][tx] = a[ia + n * ty + tx];
bs[ty][tx] = b[ib + n * ty + tx];
__syncthreads(); // Synchronize to make sure the matrices are loaded
for (int k = 0; k < BLOCK_SIZE; k++) sum += as[ty][k] * bs[k][tx];
__syncthreads(); // Synchronize to make sure submatrices not needed
}
c[n * BLOCK_SIZE * by + BLOCK_SIZE * bx + n * ty + tx] = sum;
}
__global__ void kernel_global(float * a, float * b, int n, float * c)
{
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
float sum = 0.0f;
int ia = n * BLOCK_SIZE * by + n * ty;
int ib = BLOCK_SIZE * bx + tx;
int ic = n * BLOCK_SIZE * by + BLOCK_SIZE * bx;
for (int k = 0; k < n; k++) sum += a[ia + k] * b[ib + k*n];
c[ic + n * ty + tx] = sum;
}
int main()
{
int N = 1024;
int m, n, k;
float CPUstart, CPUstop;
float timerValueGPU, timerValueCPU;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
int numBytes = N*N*sizeof(float);
float *devA, *devB, *devC, *a, *b, *c, *cc, *bT, *aT;
a = (float*)malloc(numBytes);
b = (float*)malloc(numBytes);
bT = (float*)malloc(numBytes);
aT = (float*)malloc(numBytes);
c = (float*)malloc(numBytes);
cc = (float*)malloc(numBytes);
for (n = 0; n<N; n++)
{
for (m = 0; m<N; m++)
{
a[m + n*N] = 2.0f*m + n;
b[m + n*N] = m - n;
aT[m + n*N] = m + n*2.0f;
bT[m + n*N] = n - m;
}
}
hipMalloc((void**)&devA, numBytes); // allocate DRAM
hipMalloc((void**)&devB, numBytes); // allocate DRAM
hipMalloc((void**)&devC, numBytes); // allocate DRAM
dim3 threads(BLOCK_SIZE, BLOCK_SIZE);
dim3 blocks(N / threads.x, N / threads.y);
// DEVICE ------------------------------------------------------
hipEventRecord(start, 0);
hipMemcpy(devA, a, numBytes, hipMemcpyHostToDevice);
hipMemcpy(devB, b, numBytes, hipMemcpyHostToDevice);
kernel_shared <<<blocks, threads >>> (devA, devB, N, devC);
//kernel_shared_1 << <blocks, threads >> > (devA, devB, N, devC);
//kernel_global <<< blocks, threads >>> ( devA, devB, N, devC );
hipMemcpy(c, devC, numBytes, hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&timerValueGPU, start, stop);
printf("\n GPU calculation time %f msec\n", timerValueGPU);
//---------------------------------------------------------------
// HOST ---------------------------------------------------------
CPUstart = clock();
for (n = 0; n<N; n++)
{
for (m = 0; m<N; m++)
{
cc[m + n*N] = 0.f;
for (k = 0; k<N; k++) cc[m + n*N] += a[k + n*N] * bT[k + m*N]; // T
// for(k=0;k<N;k++) cc[m+n*N]+=a[k+n*N]*b[m+k*N]; //
}
}
CPUstop = clock();
timerValueCPU = 1000.*(CPUstop - CPUstart) / CLOCKS_PER_SEC;
printf("CPU time : %.3f ms\n", timerValueCPU);
printf("Rate : %.3f \n", timerValueCPU / timerValueGPU);
//---------------------------------------------------------------
hipFree(devA);
hipFree(devB);
hipFree(devC);
free(a);
free(b);
free(bT);
free(aT);
free(c);
free(cc);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13kernel_sharedPfS_iS_
.globl _Z13kernel_sharedPfS_iS_
.p2align 8
.type _Z13kernel_sharedPfS_iS_,@function
_Z13kernel_sharedPfS_iS_:
s_load_b32 s2, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_lshl_b32 s8, s14, 4
s_waitcnt lgkmcnt(0)
s_lshl_b32 s9, s2, 4
s_cmp_lt_i32 s2, 1
s_mul_i32 s3, s9, s15
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v4, 2, v0
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_mov_b32_e32 v3, 0
s_movk_i32 s10, 0x440
s_delay_alu instid0(VALU_DEP_3)
v_mad_u32_u24 v5, v1, 0x44, v4
v_mad_u32_u24 v7, v1, 0x44, s10
s_add_i32 s10, s3, s2
s_mov_b32 s11, s8
s_mov_b32 s12, s3
v_add_nc_u32_e32 v6, 0x440, v5
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v8, s12, v2
v_add_nc_u32_e32 v10, s11, v2
s_mov_b32 s13, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v10, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
global_load_b32 v9, v[8:9], off
global_load_b32 v10, v[10:11], off
v_mov_b32_e32 v8, v4
s_waitcnt vmcnt(1)
ds_store_b32 v5, v9
s_waitcnt vmcnt(0)
ds_store_b32 v6, v10
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v9, s13, v7
s_add_i32 s13, s13, 4
ds_load_b32 v10, v8
ds_load_b32 v9, v9
v_add_nc_u32_e32 v8, 0x44, v8
s_cmp_eq_u32 s13, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v3, v10, v9
s_cbranch_scc0 .LBB0_3
s_add_i32 s12, s12, 16
s_add_i32 s11, s11, s9
s_cmp_ge_i32 s12, s10
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v3, 0
.LBB0_6:
s_set_inst_prefetch_distance 0x2
v_mul_lo_u32 v0, v0, s2
v_add_nc_u32_e32 v1, s8, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, v1, v0, s3
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13kernel_sharedPfS_iS_
.amdhsa_group_segment_fixed_size 2176
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13kernel_sharedPfS_iS_, .Lfunc_end0-_Z13kernel_sharedPfS_iS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15kernel_shared_1PfS_iS_
.globl _Z15kernel_shared_1PfS_iS_
.p2align 8
.type _Z15kernel_shared_1PfS_iS_,@function
_Z15kernel_shared_1PfS_iS_:
s_load_b32 s2, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_lshl_b32 s8, s14, 4
s_waitcnt lgkmcnt(0)
s_lshl_b32 s9, s2, 4
s_cmp_lt_i32 s2, 1
s_mul_i32 s3, s9, s15
s_cbranch_scc1 .LBB1_5
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v6, 2, v1
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v4, 6, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v5, 0x400, v6
s_add_i32 s10, s3, s2
s_mov_b32 s11, s8
s_mov_b32 s12, s3
v_add_nc_u32_e32 v6, v4, v6
v_add_nc_u32_e32 v7, v5, v4
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB1_2:
v_add_nc_u32_e32 v8, s12, v2
v_add_nc_u32_e32 v10, s11, v2
s_mov_b32 s13, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v10, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
global_load_b32 v9, v[8:9], off
global_load_b32 v10, v[10:11], off
v_mov_b32_e32 v8, v5
s_waitcnt vmcnt(1)
ds_store_b32 v6, v9
s_waitcnt vmcnt(0)
ds_store_b32 v7, v10
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB1_3:
v_add_nc_u32_e32 v9, s13, v4
s_add_i32 s13, s13, 4
ds_load_b32 v10, v8
ds_load_b32 v9, v9
v_add_nc_u32_e32 v8, 64, v8
s_cmp_eq_u32 s13, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v3, v9, v10
s_cbranch_scc0 .LBB1_3
s_add_i32 s12, s12, 16
s_add_i32 s11, s11, s9
s_cmp_ge_i32 s12, s10
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_2
s_branch .LBB1_6
.LBB1_5:
v_mov_b32_e32 v3, 0
.LBB1_6:
s_set_inst_prefetch_distance 0x2
v_mul_lo_u32 v0, v0, s2
v_add_nc_u32_e32 v1, s8, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, v1, v0, s3
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15kernel_shared_1PfS_iS_
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15kernel_shared_1PfS_iS_, .Lfunc_end1-_Z15kernel_shared_1PfS_iS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13kernel_globalPfS_iS_
.globl _Z13kernel_globalPfS_iS_
.p2align 8
.type _Z13kernel_globalPfS_iS_,@function
_Z13kernel_globalPfS_iS_:
s_load_b32 s3, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_lshl_b32 s2, s14, 4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v5, s2, v0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v4, v1, s3
s_mul_i32 s4, s3, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s2, s4, 4
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB2_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v0, s2, v4
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v2, v5
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_mov_b32 s4, s3
.p2align 6
.LBB2_2:
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s4, 0
v_lshlrev_b64 v[7:8], 2, v[2:3]
v_add_nc_u32_e32 v2, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v3, v[0:1], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v3, v7
s_cbranch_scc0 .LBB2_2
s_branch .LBB2_4
.LBB2_3:
v_mov_b32_e32 v6, 0
.LBB2_4:
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, v5, v4, s2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13kernel_globalPfS_iS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z13kernel_globalPfS_iS_, .Lfunc_end2-_Z13kernel_globalPfS_iS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 2176
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13kernel_sharedPfS_iS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13kernel_sharedPfS_iS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15kernel_shared_1PfS_iS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15kernel_shared_1PfS_iS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13kernel_globalPfS_iS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13kernel_globalPfS_iS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define BLOCK_SIZE 16
__global__ void kernel_shared(float * a, float * b, int n, float * c)
{
int bx = blockIdx.x, by = blockIdx.y;
int tx = threadIdx.x, ty = threadIdx.y;
int aBegin = n * BLOCK_SIZE * by;
int aEnd = aBegin + n - 1;
int bBegin = BLOCK_SIZE * bx;
int aStep = BLOCK_SIZE, bStep = BLOCK_SIZE * n;
float sum = 0.0f;
__shared__ float as[BLOCK_SIZE][BLOCK_SIZE + 1];
__shared__ float bs[BLOCK_SIZE][BLOCK_SIZE + 1];
for (int ia = aBegin, ib = bBegin; ia <= aEnd; ia += aStep, ib += bStep)
{
as[tx][ty] = a[ia + n * ty + tx];
bs[tx][ty] = b[ib + n * ty + tx];
__syncthreads(); // Synchronize to make sure the matrices are loaded
for (int k = 0; k < BLOCK_SIZE; k++) sum += as[k][ty] * bs[tx][k];
__syncthreads(); // Synchronize to make sure submatrices not needed
}
c[n * BLOCK_SIZE * by + BLOCK_SIZE * bx + n * ty + tx] = sum;
}
__global__ void kernel_shared_1(float * a, float * b, int n, float * c)
{
int bx = blockIdx.x, by = blockIdx.y;
int tx = threadIdx.x, ty = threadIdx.y;
int aBegin = n * BLOCK_SIZE * by;
int aEnd = aBegin + n - 1;
int bBegin = BLOCK_SIZE * bx;
int aStep = BLOCK_SIZE, bStep = BLOCK_SIZE * n;
float sum = 0.0f;
for (int ia = aBegin, ib = bBegin; ia <= aEnd; ia += aStep, ib += bStep)
{
__shared__ float as[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float bs[BLOCK_SIZE][BLOCK_SIZE];
as[ty][tx] = a[ia + n * ty + tx];
bs[ty][tx] = b[ib + n * ty + tx];
__syncthreads(); // Synchronize to make sure the matrices are loaded
for (int k = 0; k < BLOCK_SIZE; k++) sum += as[ty][k] * bs[k][tx];
__syncthreads(); // Synchronize to make sure submatrices not needed
}
c[n * BLOCK_SIZE * by + BLOCK_SIZE * bx + n * ty + tx] = sum;
}
__global__ void kernel_global(float * a, float * b, int n, float * c)
{
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
float sum = 0.0f;
int ia = n * BLOCK_SIZE * by + n * ty;
int ib = BLOCK_SIZE * bx + tx;
int ic = n * BLOCK_SIZE * by + BLOCK_SIZE * bx;
for (int k = 0; k < n; k++) sum += a[ia + k] * b[ib + k*n];
c[ic + n * ty + tx] = sum;
}
int main()
{
int N = 1024;
int m, n, k;
float CPUstart, CPUstop;
float timerValueGPU, timerValueCPU;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
int numBytes = N*N*sizeof(float);
float *devA, *devB, *devC, *a, *b, *c, *cc, *bT, *aT;
a = (float*)malloc(numBytes);
b = (float*)malloc(numBytes);
bT = (float*)malloc(numBytes);
aT = (float*)malloc(numBytes);
c = (float*)malloc(numBytes);
cc = (float*)malloc(numBytes);
for (n = 0; n<N; n++)
{
for (m = 0; m<N; m++)
{
a[m + n*N] = 2.0f*m + n;
b[m + n*N] = m - n;
aT[m + n*N] = m + n*2.0f;
bT[m + n*N] = n - m;
}
}
hipMalloc((void**)&devA, numBytes); // allocate DRAM
hipMalloc((void**)&devB, numBytes); // allocate DRAM
hipMalloc((void**)&devC, numBytes); // allocate DRAM
dim3 threads(BLOCK_SIZE, BLOCK_SIZE);
dim3 blocks(N / threads.x, N / threads.y);
// DEVICE ------------------------------------------------------
hipEventRecord(start, 0);
hipMemcpy(devA, a, numBytes, hipMemcpyHostToDevice);
hipMemcpy(devB, b, numBytes, hipMemcpyHostToDevice);
kernel_shared <<<blocks, threads >>> (devA, devB, N, devC);
//kernel_shared_1 << <blocks, threads >> > (devA, devB, N, devC);
//kernel_global <<< blocks, threads >>> ( devA, devB, N, devC );
hipMemcpy(c, devC, numBytes, hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&timerValueGPU, start, stop);
printf("\n GPU calculation time %f msec\n", timerValueGPU);
//---------------------------------------------------------------
// HOST ---------------------------------------------------------
CPUstart = clock();
for (n = 0; n<N; n++)
{
for (m = 0; m<N; m++)
{
cc[m + n*N] = 0.f;
for (k = 0; k<N; k++) cc[m + n*N] += a[k + n*N] * bT[k + m*N]; // T
// for(k=0;k<N;k++) cc[m+n*N]+=a[k+n*N]*b[m+k*N]; //
}
}
CPUstop = clock();
timerValueCPU = 1000.*(CPUstop - CPUstart) / CLOCKS_PER_SEC;
printf("CPU time : %.3f ms\n", timerValueCPU);
printf("Rate : %.3f \n", timerValueCPU / timerValueGPU);
//---------------------------------------------------------------
hipFree(devA);
hipFree(devB);
hipFree(devC);
free(a);
free(b);
free(bT);
free(aT);
free(c);
free(cc);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
} | .text
.file "Example5.hip"
.globl _Z28__device_stub__kernel_sharedPfS_iS_ # -- Begin function _Z28__device_stub__kernel_sharedPfS_iS_
.p2align 4, 0x90
.type _Z28__device_stub__kernel_sharedPfS_iS_,@function
_Z28__device_stub__kernel_sharedPfS_iS_: # @_Z28__device_stub__kernel_sharedPfS_iS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13kernel_sharedPfS_iS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__kernel_sharedPfS_iS_, .Lfunc_end0-_Z28__device_stub__kernel_sharedPfS_iS_
.cfi_endproc
# -- End function
.globl _Z30__device_stub__kernel_shared_1PfS_iS_ # -- Begin function _Z30__device_stub__kernel_shared_1PfS_iS_
.p2align 4, 0x90
.type _Z30__device_stub__kernel_shared_1PfS_iS_,@function
_Z30__device_stub__kernel_shared_1PfS_iS_: # @_Z30__device_stub__kernel_shared_1PfS_iS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15kernel_shared_1PfS_iS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z30__device_stub__kernel_shared_1PfS_iS_, .Lfunc_end1-_Z30__device_stub__kernel_shared_1PfS_iS_
.cfi_endproc
# -- End function
.globl _Z28__device_stub__kernel_globalPfS_iS_ # -- Begin function _Z28__device_stub__kernel_globalPfS_iS_
.p2align 4, 0x90
.type _Z28__device_stub__kernel_globalPfS_iS_,@function
_Z28__device_stub__kernel_globalPfS_iS_: # @_Z28__device_stub__kernel_globalPfS_iS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13kernel_globalPfS_iS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z28__device_stub__kernel_globalPfS_iS_, .Lfunc_end2-_Z28__device_stub__kernel_globalPfS_iS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x408f400000000000 # double 1000
.LCPI3_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $176, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
xorl %eax, %eax
movq %rbx, %rcx
movq %r14, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_1: # %.preheader95
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorps %xmm0, %xmm0
cvtsi2ss %esi, %xmm0
xorl %edi, %edi
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm1, %xmm1
cvtsi2ss %edi, %xmm1
addss %xmm1, %xmm1
addss %xmm0, %xmm1
leal (%rax,%rdi), %r8d
xorps %xmm2, %xmm2
cvtsi2ss %r8d, %xmm2
movss %xmm1, (%rcx,%rdi,4)
movss %xmm2, (%rdx,%rdi,4)
incq %rdi
cmpq $1024, %rdi # imm = 0x400
jne .LBB3_2
# %bb.3: # in Loop: Header=BB3_1 Depth=1
incq %rsi
decq %rax
addq $4096, %rdx # imm = 0x1000
addq $4096, %rcx # imm = 0x1000
cmpq $1024, %rsi # imm = 0x400
jne .LBB3_1
# %bb.4:
leaq 40(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $274877907008, %rdi # imm = 0x4000000040
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movl $1024, 60(%rsp) # imm = 0x400
movq %rdx, 152(%rsp)
leaq 168(%rsp), %rax
movq %rax, 64(%rsp)
leaq 160(%rsp), %rax
movq %rax, 72(%rsp)
leaq 60(%rsp), %rax
movq %rax, 80(%rsp)
leaq 152(%rsp), %rax
movq %rax, 88(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13kernel_sharedPfS_iS_, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
movq 24(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 48(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
callq clock
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
callq clock
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
subss 12(%rsp), %xmm0 # 4-byte Folded Reload
cvtss2sd %xmm0, %xmm0
mulsd .LCPI3_0(%rip), %xmm0
divsd .LCPI3_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
divss 64(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 48(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $176, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kernel_sharedPfS_iS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15kernel_shared_1PfS_iS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kernel_globalPfS_iS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13kernel_sharedPfS_iS_,@object # @_Z13kernel_sharedPfS_iS_
.section .rodata,"a",@progbits
.globl _Z13kernel_sharedPfS_iS_
.p2align 3, 0x0
_Z13kernel_sharedPfS_iS_:
.quad _Z28__device_stub__kernel_sharedPfS_iS_
.size _Z13kernel_sharedPfS_iS_, 8
.type _Z15kernel_shared_1PfS_iS_,@object # @_Z15kernel_shared_1PfS_iS_
.globl _Z15kernel_shared_1PfS_iS_
.p2align 3, 0x0
_Z15kernel_shared_1PfS_iS_:
.quad _Z30__device_stub__kernel_shared_1PfS_iS_
.size _Z15kernel_shared_1PfS_iS_, 8
.type _Z13kernel_globalPfS_iS_,@object # @_Z13kernel_globalPfS_iS_
.globl _Z13kernel_globalPfS_iS_
.p2align 3, 0x0
_Z13kernel_globalPfS_iS_:
.quad _Z28__device_stub__kernel_globalPfS_iS_
.size _Z13kernel_globalPfS_iS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n GPU calculation time %f msec\n"
.size .L.str, 32
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CPU time : %.3f ms\n"
.size .L.str.1, 20
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Rate : %.3f \n"
.size .L.str.2, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13kernel_sharedPfS_iS_"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15kernel_shared_1PfS_iS_"
.size .L__unnamed_2, 27
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13kernel_globalPfS_iS_"
.size .L__unnamed_3, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__kernel_sharedPfS_iS_
.addrsig_sym _Z30__device_stub__kernel_shared_1PfS_iS_
.addrsig_sym _Z28__device_stub__kernel_globalPfS_iS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13kernel_sharedPfS_iS_
.addrsig_sym _Z15kernel_shared_1PfS_iS_
.addrsig_sym _Z13kernel_globalPfS_iS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005c3db_00000000-6_Example5.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z13kernel_sharedPfS_iS_PfS_iS_
.type _Z38__device_stub__Z13kernel_sharedPfS_iS_PfS_iS_, @function
_Z38__device_stub__Z13kernel_sharedPfS_iS_PfS_iS_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13kernel_sharedPfS_iS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z38__device_stub__Z13kernel_sharedPfS_iS_PfS_iS_, .-_Z38__device_stub__Z13kernel_sharedPfS_iS_PfS_iS_
.globl _Z13kernel_sharedPfS_iS_
.type _Z13kernel_sharedPfS_iS_, @function
_Z13kernel_sharedPfS_iS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13kernel_sharedPfS_iS_PfS_iS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z13kernel_sharedPfS_iS_, .-_Z13kernel_sharedPfS_iS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "\n GPU calculation time %f msec\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "CPU time : %.3f ms\n"
.LC5:
.string "Rate : %.3f \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %r13
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movl $4194304, %edi
call malloc@PLT
movq %rax, (%rsp)
movl $4194304, %edi
call malloc@PLT
movq %rax, %r15
movl $4194304, %edi
call malloc@PLT
movq %rax, %r14
movq %rbp, %rbx
movq %r13, %r8
movq (%rsp), %rdi
movq %r12, %rsi
movq %rbp, %rcx
movl $0, %r9d
.L12:
pxor %xmm2, %xmm2
cvtsi2ssl %r9d, %xmm2
movl %r9d, %edx
movaps %xmm2, %xmm3
addss %xmm2, %xmm3
movl $0, %eax
.L13:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movaps %xmm0, %xmm1
addss %xmm0, %xmm1
addss %xmm2, %xmm1
movss %xmm1, (%rcx,%rax,4)
movl %edx, %r10d
negl %r10d
pxor %xmm1, %xmm1
cvtsi2ssl %r10d, %xmm1
movss %xmm1, (%r8,%rax,4)
addss %xmm3, %xmm0
movss %xmm0, (%rdi,%rax,4)
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%rsi,%rax,4)
addq $1, %rax
subl $1, %edx
cmpq $1024, %rax
jne .L13
addl $1, %r9d
addq $4096, %rcx
addq $4096, %r8
addq $4096, %rdi
addq $4096, %rsi
cmpl $1024, %r9d
jne .L12
leaq 40(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $1, 72(%rsp)
movl $64, 76(%rsp)
movl $64, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %r13, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 64(%rsp)
movl $16, 68(%rsp)
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L15:
movl $2, %ecx
movl $4194304, %edx
movq 56(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call clock@PLT
pxor %xmm5, %xmm5
cvtsi2ssq %rax, %xmm5
movss %xmm5, 12(%rsp)
movq %r14, %r8
leaq 4194304(%rbp), %r9
jmp .L16
.L25:
movq 56(%rsp), %rcx
movl $1024, %edx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z38__device_stub__Z13kernel_sharedPfS_iS_PfS_iS_
jmp .L15
.L27:
movss %xmm1, (%rdi)
addq $4, %rsi
addl $1024, %ecx
addq $4096, %rdx
cmpl $1048576, %ecx
je .L26
.L18:
movq %rsi, %rdi
movl $0, %eax
pxor %xmm1, %xmm1
.L17:
movss (%rbx,%rax), %xmm0
mulss (%rdx,%rax), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
cmpq $4096, %rax
jne .L17
jmp .L27
.L26:
addq $4096, %rbx
addq $4096, %r8
cmpq %r9, %rbx
je .L19
.L16:
movq %r12, %rdx
movq %r8, %rsi
movl $0, %ecx
jmp .L18
.L19:
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
subss 12(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LC2(%rip), %xmm0
divsd .LC3(%rip), %xmm0
pxor %xmm4, %xmm4
cvtsd2ss %xmm0, %xmm4
movss %xmm4, 12(%rsp)
pxor %xmm0, %xmm0
cvtss2sd %xmm4, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 12(%rsp), %xmm4
divss 20(%rsp), %xmm4
pxor %xmm0, %xmm0
cvtss2sd %xmm4, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z40__device_stub__Z15kernel_shared_1PfS_iS_PfS_iS_
.type _Z40__device_stub__Z15kernel_shared_1PfS_iS_PfS_iS_, @function
_Z40__device_stub__Z15kernel_shared_1PfS_iS_PfS_iS_:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15kernel_shared_1PfS_iS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z40__device_stub__Z15kernel_shared_1PfS_iS_PfS_iS_, .-_Z40__device_stub__Z15kernel_shared_1PfS_iS_PfS_iS_
.globl _Z15kernel_shared_1PfS_iS_
.type _Z15kernel_shared_1PfS_iS_, @function
_Z15kernel_shared_1PfS_iS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15kernel_shared_1PfS_iS_PfS_iS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z15kernel_shared_1PfS_iS_, .-_Z15kernel_shared_1PfS_iS_
.globl _Z38__device_stub__Z13kernel_globalPfS_iS_PfS_iS_
.type _Z38__device_stub__Z13kernel_globalPfS_iS_PfS_iS_, @function
_Z38__device_stub__Z13kernel_globalPfS_iS_PfS_iS_:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13kernel_globalPfS_iS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z38__device_stub__Z13kernel_globalPfS_iS_PfS_iS_, .-_Z38__device_stub__Z13kernel_globalPfS_iS_PfS_iS_
.globl _Z13kernel_globalPfS_iS_
.type _Z13kernel_globalPfS_iS_, @function
_Z13kernel_globalPfS_iS_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13kernel_globalPfS_iS_PfS_iS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z13kernel_globalPfS_iS_, .-_Z13kernel_globalPfS_iS_
.section .rodata.str1.1
.LC6:
.string "_Z13kernel_globalPfS_iS_"
.LC7:
.string "_Z15kernel_shared_1PfS_iS_"
.LC8:
.string "_Z13kernel_sharedPfS_iS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kernel_globalPfS_iS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z15kernel_shared_1PfS_iS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kernel_sharedPfS_iS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1083129856
.align 8
.LC3:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Example5.hip"
.globl _Z28__device_stub__kernel_sharedPfS_iS_ # -- Begin function _Z28__device_stub__kernel_sharedPfS_iS_
.p2align 4, 0x90
.type _Z28__device_stub__kernel_sharedPfS_iS_,@function
_Z28__device_stub__kernel_sharedPfS_iS_: # @_Z28__device_stub__kernel_sharedPfS_iS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13kernel_sharedPfS_iS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__kernel_sharedPfS_iS_, .Lfunc_end0-_Z28__device_stub__kernel_sharedPfS_iS_
.cfi_endproc
# -- End function
.globl _Z30__device_stub__kernel_shared_1PfS_iS_ # -- Begin function _Z30__device_stub__kernel_shared_1PfS_iS_
.p2align 4, 0x90
.type _Z30__device_stub__kernel_shared_1PfS_iS_,@function
_Z30__device_stub__kernel_shared_1PfS_iS_: # @_Z30__device_stub__kernel_shared_1PfS_iS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15kernel_shared_1PfS_iS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z30__device_stub__kernel_shared_1PfS_iS_, .Lfunc_end1-_Z30__device_stub__kernel_shared_1PfS_iS_
.cfi_endproc
# -- End function
.globl _Z28__device_stub__kernel_globalPfS_iS_ # -- Begin function _Z28__device_stub__kernel_globalPfS_iS_
.p2align 4, 0x90
.type _Z28__device_stub__kernel_globalPfS_iS_,@function
_Z28__device_stub__kernel_globalPfS_iS_: # @_Z28__device_stub__kernel_globalPfS_iS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13kernel_globalPfS_iS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z28__device_stub__kernel_globalPfS_iS_, .Lfunc_end2-_Z28__device_stub__kernel_globalPfS_iS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x408f400000000000 # double 1000
.LCPI3_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $176, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
xorl %eax, %eax
movq %rbx, %rcx
movq %r14, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_1: # %.preheader95
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorps %xmm0, %xmm0
cvtsi2ss %esi, %xmm0
xorl %edi, %edi
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm1, %xmm1
cvtsi2ss %edi, %xmm1
addss %xmm1, %xmm1
addss %xmm0, %xmm1
leal (%rax,%rdi), %r8d
xorps %xmm2, %xmm2
cvtsi2ss %r8d, %xmm2
movss %xmm1, (%rcx,%rdi,4)
movss %xmm2, (%rdx,%rdi,4)
incq %rdi
cmpq $1024, %rdi # imm = 0x400
jne .LBB3_2
# %bb.3: # in Loop: Header=BB3_1 Depth=1
incq %rsi
decq %rax
addq $4096, %rdx # imm = 0x1000
addq $4096, %rcx # imm = 0x1000
cmpq $1024, %rsi # imm = 0x400
jne .LBB3_1
# %bb.4:
leaq 40(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $274877907008, %rdi # imm = 0x4000000040
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movl $1024, 60(%rsp) # imm = 0x400
movq %rdx, 152(%rsp)
leaq 168(%rsp), %rax
movq %rax, 64(%rsp)
leaq 160(%rsp), %rax
movq %rax, 72(%rsp)
leaq 60(%rsp), %rax
movq %rax, 80(%rsp)
leaq 152(%rsp), %rax
movq %rax, 88(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13kernel_sharedPfS_iS_, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
movq 24(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 48(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
callq clock
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
callq clock
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
subss 12(%rsp), %xmm0 # 4-byte Folded Reload
cvtss2sd %xmm0, %xmm0
mulsd .LCPI3_0(%rip), %xmm0
divsd .LCPI3_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
divss 64(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 48(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $176, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kernel_sharedPfS_iS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15kernel_shared_1PfS_iS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kernel_globalPfS_iS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13kernel_sharedPfS_iS_,@object # @_Z13kernel_sharedPfS_iS_
.section .rodata,"a",@progbits
.globl _Z13kernel_sharedPfS_iS_
.p2align 3, 0x0
_Z13kernel_sharedPfS_iS_:
.quad _Z28__device_stub__kernel_sharedPfS_iS_
.size _Z13kernel_sharedPfS_iS_, 8
.type _Z15kernel_shared_1PfS_iS_,@object # @_Z15kernel_shared_1PfS_iS_
.globl _Z15kernel_shared_1PfS_iS_
.p2align 3, 0x0
_Z15kernel_shared_1PfS_iS_:
.quad _Z30__device_stub__kernel_shared_1PfS_iS_
.size _Z15kernel_shared_1PfS_iS_, 8
.type _Z13kernel_globalPfS_iS_,@object # @_Z13kernel_globalPfS_iS_
.globl _Z13kernel_globalPfS_iS_
.p2align 3, 0x0
_Z13kernel_globalPfS_iS_:
.quad _Z28__device_stub__kernel_globalPfS_iS_
.size _Z13kernel_globalPfS_iS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n GPU calculation time %f msec\n"
.size .L.str, 32
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CPU time : %.3f ms\n"
.size .L.str.1, 20
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Rate : %.3f \n"
.size .L.str.2, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13kernel_sharedPfS_iS_"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15kernel_shared_1PfS_iS_"
.size .L__unnamed_2, 27
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13kernel_globalPfS_iS_"
.size .L__unnamed_3, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__kernel_sharedPfS_iS_
.addrsig_sym _Z30__device_stub__kernel_shared_1PfS_iS_
.addrsig_sym _Z28__device_stub__kernel_globalPfS_iS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13kernel_sharedPfS_iS_
.addrsig_sym _Z15kernel_shared_1PfS_iS_
.addrsig_sym _Z13kernel_globalPfS_iS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* @file compare.cu
* @brief cuda arrayの比較の実装
* @author HIKARU KONDO
* @date 2021/08/31
*/
#include "array_scalar_add.cuh"
#define BLOCKDIM 256
template<typename T>
__global__ void arrayAddScalar(T *array, T *resArray, T scalar, int size) {
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx >= size) { return; }
resArray[idx] = array[idx] + scalar;
}
void floatArrayScalarAdd(float *array, float *resArray, float scalar, int size) {
dim3 blockDim(BLOCKDIM);
dim3 gridDim((size + blockDim.x - 1) / blockDim.x);
arrayAddScalar<<< gridDim, blockDim >>> (array, resArray, scalar, size);
}
void doubleArrayScalarAdd(double *array, double *resArray, double scalar, int size) {
dim3 blockDim(BLOCKDIM);
dim3 gridDim((size + blockDim.x - 1) / blockDim.x);
arrayAddScalar<<< gridDim, blockDim >>> (array, resArray, scalar, size);
} | code for sm_80
Function : _Z14arrayAddScalarIdEvPT_S1_S0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fcc00078e0007 */
/*0090*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe200078e0007 */
/*00b0*/ DADD R4, R2, c[0x0][0x170] ; /* 0x00005c0002047629 */
/* 0x004e0e0000000000 */
/*00c0*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x001fe2000c101b04 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z14arrayAddScalarIfEvPT_S1_S0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0005 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0005 */
/*00b0*/ FADD R7, R2, c[0x0][0x170] ; /* 0x00005c0002077621 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* @file compare.cu
* @brief cuda arrayの比較の実装
* @author HIKARU KONDO
* @date 2021/08/31
*/
#include "array_scalar_add.cuh"
#define BLOCKDIM 256
template<typename T>
__global__ void arrayAddScalar(T *array, T *resArray, T scalar, int size) {
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx >= size) { return; }
resArray[idx] = array[idx] + scalar;
}
void floatArrayScalarAdd(float *array, float *resArray, float scalar, int size) {
dim3 blockDim(BLOCKDIM);
dim3 gridDim((size + blockDim.x - 1) / blockDim.x);
arrayAddScalar<<< gridDim, blockDim >>> (array, resArray, scalar, size);
}
void doubleArrayScalarAdd(double *array, double *resArray, double scalar, int size) {
dim3 blockDim(BLOCKDIM);
dim3 gridDim((size + blockDim.x - 1) / blockDim.x);
arrayAddScalar<<< gridDim, blockDim >>> (array, resArray, scalar, size);
} | .file "tmpxft_0000a275_00000000-6_array_scalar_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL46__device_stub__Z14arrayAddScalarIfEvPT_S1_S0_iPfS_fi, @function
_ZL46__device_stub__Z14arrayAddScalarIfEvPT_S1_S0_iPfS_fi:
.LFB2055:
.cfi_startproc
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14arrayAddScalarIfEvPT_S1_S0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _ZL46__device_stub__Z14arrayAddScalarIfEvPT_S1_S0_iPfS_fi, .-_ZL46__device_stub__Z14arrayAddScalarIfEvPT_S1_S0_iPfS_fi
.section .text._Z14arrayAddScalarIfEvPT_S1_S0_i,"axG",@progbits,_Z14arrayAddScalarIfEvPT_S1_S0_i,comdat
.weak _Z14arrayAddScalarIfEvPT_S1_S0_i
.type _Z14arrayAddScalarIfEvPT_S1_S0_i, @function
_Z14arrayAddScalarIfEvPT_S1_S0_i:
.LFB2106:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL46__device_stub__Z14arrayAddScalarIfEvPT_S1_S0_iPfS_fi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2106:
.size _Z14arrayAddScalarIfEvPT_S1_S0_i, .-_Z14arrayAddScalarIfEvPT_S1_S0_i
.text
.type _ZL46__device_stub__Z14arrayAddScalarIdEvPT_S1_S0_iPdS_di, @function
_ZL46__device_stub__Z14arrayAddScalarIdEvPT_S1_S0_iPdS_di:
.LFB2057:
.cfi_startproc
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movsd %xmm0, 8(%rsp)
movl %edx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14arrayAddScalarIdEvPT_S1_S0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _ZL46__device_stub__Z14arrayAddScalarIdEvPT_S1_S0_iPdS_di, .-_ZL46__device_stub__Z14arrayAddScalarIdEvPT_S1_S0_iPdS_di
.section .text._Z14arrayAddScalarIdEvPT_S1_S0_i,"axG",@progbits,_Z14arrayAddScalarIdEvPT_S1_S0_i,comdat
.weak _Z14arrayAddScalarIdEvPT_S1_S0_i
.type _Z14arrayAddScalarIdEvPT_S1_S0_i, @function
_Z14arrayAddScalarIdEvPT_S1_S0_i:
.LFB2107:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL46__device_stub__Z14arrayAddScalarIdEvPT_S1_S0_iPdS_di
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2107:
.size _Z14arrayAddScalarIdEvPT_S1_S0_i, .-_Z14arrayAddScalarIdEvPT_S1_S0_i
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl floatArrayScalarAdd
.type floatArrayScalarAdd, @function
floatArrayScalarAdd:
.LFB2029:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %r12
movss %xmm0, 12(%rsp)
movl %edx, %ebx
movl $1, 28(%rsp)
leal 255(%rdx), %eax
shrl $8, %eax
movl %eax, 36(%rsp)
movl $1, 40(%rsp)
movl $256, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L19:
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movl %ebx, %edx
movss 12(%rsp), %xmm0
movq %r12, %rsi
movq %rbp, %rdi
call _ZL46__device_stub__Z14arrayAddScalarIfEvPT_S1_S0_iPfS_fi
jmp .L19
.cfi_endproc
.LFE2029:
.size floatArrayScalarAdd, .-floatArrayScalarAdd
.globl doubleArrayScalarAdd
.type doubleArrayScalarAdd, @function
doubleArrayScalarAdd:
.LFB2030:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %r12
movsd %xmm0, 8(%rsp)
movl %edx, %ebx
movl $1, 28(%rsp)
leal 255(%rdx), %eax
shrl $8, %eax
movl %eax, 36(%rsp)
movl $1, 40(%rsp)
movl $256, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl %ebx, %edx
movsd 8(%rsp), %xmm0
movq %r12, %rsi
movq %rbp, %rdi
call _ZL46__device_stub__Z14arrayAddScalarIdEvPT_S1_S0_iPdS_di
jmp .L23
.cfi_endproc
.LFE2030:
.size doubleArrayScalarAdd, .-doubleArrayScalarAdd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14arrayAddScalarIdEvPT_S1_S0_i"
.align 8
.LC1:
.string "_Z14arrayAddScalarIfEvPT_S1_S0_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14arrayAddScalarIdEvPT_S1_S0_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14arrayAddScalarIfEvPT_S1_S0_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* @file compare.cu
* @brief cuda arrayの比較の実装
* @author HIKARU KONDO
* @date 2021/08/31
*/
#include "array_scalar_add.cuh"
#define BLOCKDIM 256
template<typename T>
__global__ void arrayAddScalar(T *array, T *resArray, T scalar, int size) {
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx >= size) { return; }
resArray[idx] = array[idx] + scalar;
}
void floatArrayScalarAdd(float *array, float *resArray, float scalar, int size) {
dim3 blockDim(BLOCKDIM);
dim3 gridDim((size + blockDim.x - 1) / blockDim.x);
arrayAddScalar<<< gridDim, blockDim >>> (array, resArray, scalar, size);
}
void doubleArrayScalarAdd(double *array, double *resArray, double scalar, int size) {
dim3 blockDim(BLOCKDIM);
dim3 gridDim((size + blockDim.x - 1) / blockDim.x);
arrayAddScalar<<< gridDim, blockDim >>> (array, resArray, scalar, size);
} | #pragma once
#include <hip/hip_runtime.h>
#ifdef __cplusplus
extern "C" {
#endif
void floatArrayScalarAdd(float *array, float *resArray, float scalar, int size);
void doubleArrayScalarAdd(double *array, double *resArray, double scalar, int size);
#ifdef __cplusplus
}
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #pragma once
#include <hip/hip_runtime.h>
#ifdef __cplusplus
extern "C" {
#endif
void floatArrayScalarAdd(float *array, float *resArray, float scalar, int size);
void doubleArrayScalarAdd(double *array, double *resArray, double scalar, int size);
#ifdef __cplusplus
}
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #pragma once
#include <hip/hip_runtime.h>
#ifdef __cplusplus
extern "C" {
#endif
void floatArrayScalarAdd(float *array, float *resArray, float scalar, int size);
void doubleArrayScalarAdd(double *array, double *resArray, double scalar, int size);
#ifdef __cplusplus
}
#endif | .text
.file "array_scalar_add.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14arrayAddScalarIdEvPT_S1_S0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fcc00078e0007 */
/*0090*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe200078e0007 */
/*00b0*/ DADD R4, R2, c[0x0][0x170] ; /* 0x00005c0002047629 */
/* 0x004e0e0000000000 */
/*00c0*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x001fe2000c101b04 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z14arrayAddScalarIfEvPT_S1_S0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0005 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0005 */
/*00b0*/ FADD R7, R2, c[0x0][0x170] ; /* 0x00005c0002077621 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000a275_00000000-6_array_scalar_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL46__device_stub__Z14arrayAddScalarIfEvPT_S1_S0_iPfS_fi, @function
_ZL46__device_stub__Z14arrayAddScalarIfEvPT_S1_S0_iPfS_fi:
.LFB2055:
.cfi_startproc
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14arrayAddScalarIfEvPT_S1_S0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _ZL46__device_stub__Z14arrayAddScalarIfEvPT_S1_S0_iPfS_fi, .-_ZL46__device_stub__Z14arrayAddScalarIfEvPT_S1_S0_iPfS_fi
.section .text._Z14arrayAddScalarIfEvPT_S1_S0_i,"axG",@progbits,_Z14arrayAddScalarIfEvPT_S1_S0_i,comdat
.weak _Z14arrayAddScalarIfEvPT_S1_S0_i
.type _Z14arrayAddScalarIfEvPT_S1_S0_i, @function
_Z14arrayAddScalarIfEvPT_S1_S0_i:
.LFB2106:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL46__device_stub__Z14arrayAddScalarIfEvPT_S1_S0_iPfS_fi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2106:
.size _Z14arrayAddScalarIfEvPT_S1_S0_i, .-_Z14arrayAddScalarIfEvPT_S1_S0_i
.text
.type _ZL46__device_stub__Z14arrayAddScalarIdEvPT_S1_S0_iPdS_di, @function
_ZL46__device_stub__Z14arrayAddScalarIdEvPT_S1_S0_iPdS_di:
.LFB2057:
.cfi_startproc
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movsd %xmm0, 8(%rsp)
movl %edx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14arrayAddScalarIdEvPT_S1_S0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _ZL46__device_stub__Z14arrayAddScalarIdEvPT_S1_S0_iPdS_di, .-_ZL46__device_stub__Z14arrayAddScalarIdEvPT_S1_S0_iPdS_di
.section .text._Z14arrayAddScalarIdEvPT_S1_S0_i,"axG",@progbits,_Z14arrayAddScalarIdEvPT_S1_S0_i,comdat
.weak _Z14arrayAddScalarIdEvPT_S1_S0_i
.type _Z14arrayAddScalarIdEvPT_S1_S0_i, @function
_Z14arrayAddScalarIdEvPT_S1_S0_i:
.LFB2107:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL46__device_stub__Z14arrayAddScalarIdEvPT_S1_S0_iPdS_di
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2107:
.size _Z14arrayAddScalarIdEvPT_S1_S0_i, .-_Z14arrayAddScalarIdEvPT_S1_S0_i
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl floatArrayScalarAdd
.type floatArrayScalarAdd, @function
floatArrayScalarAdd:
.LFB2029:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %r12
movss %xmm0, 12(%rsp)
movl %edx, %ebx
movl $1, 28(%rsp)
leal 255(%rdx), %eax
shrl $8, %eax
movl %eax, 36(%rsp)
movl $1, 40(%rsp)
movl $256, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L19:
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movl %ebx, %edx
movss 12(%rsp), %xmm0
movq %r12, %rsi
movq %rbp, %rdi
call _ZL46__device_stub__Z14arrayAddScalarIfEvPT_S1_S0_iPfS_fi
jmp .L19
.cfi_endproc
.LFE2029:
.size floatArrayScalarAdd, .-floatArrayScalarAdd
.globl doubleArrayScalarAdd
.type doubleArrayScalarAdd, @function
doubleArrayScalarAdd:
.LFB2030:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %r12
movsd %xmm0, 8(%rsp)
movl %edx, %ebx
movl $1, 28(%rsp)
leal 255(%rdx), %eax
shrl $8, %eax
movl %eax, 36(%rsp)
movl $1, 40(%rsp)
movl $256, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl %ebx, %edx
movsd 8(%rsp), %xmm0
movq %r12, %rsi
movq %rbp, %rdi
call _ZL46__device_stub__Z14arrayAddScalarIdEvPT_S1_S0_iPdS_di
jmp .L23
.cfi_endproc
.LFE2030:
.size doubleArrayScalarAdd, .-doubleArrayScalarAdd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14arrayAddScalarIdEvPT_S1_S0_i"
.align 8
.LC1:
.string "_Z14arrayAddScalarIfEvPT_S1_S0_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14arrayAddScalarIdEvPT_S1_S0_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14arrayAddScalarIfEvPT_S1_S0_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "array_scalar_add.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime_api.h>
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#define TILE_WIDTH 16
__global__ void gpu_matrix_mult_one(int *a, int *b, int *c, int m, int n, int k)
{
int row = blockIdx.y * blockDim.y + threadIdx.y; // get the row
int col = blockIdx.x * blockDim.x + threadIdx.x; // get the column
int sum = 0; // initialize the sum
if( col < k && row < m) // check to make sure that the thread needs to compute
{
for(int i = 0; i < n; i++)
{
sum += a[row * n + i] * b[i * k + col];
}
c[row * k + col] = sum;
}
}
__global__ void gpu_matrix_mult_two(int *d_M, int *d_N, int *d_P, int m, int n, int k)
{
// shared memory for tiling
__shared__ int Mds [TILE_WIDTH][TILE_WIDTH];
__shared__ int Nds [TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// recall that TILE_WIDTH = blockDim
int row = by * TILE_WIDTH + ty;
int col = bx * TILE_WIDTH + tx;
int pval = 0;
// this loop is iterating through cols of M and rows of N
// recall that n is the shared inner dimension, that's why we're using it
// to define our loop size
for (int ph = 0; ph < n / TILE_WIDTH; ph++){
// boundary check for shared Mds
if (row < k && ph * TILE_WIDTH + tx < m){
// saving tile from M
/* indexing thought exercise:
* "row * k" gets us to our desired row in M
* adding "ph * TILE_WIDTH" moves our tile over to the desired tile location
* adding "tx" moves us to the desired location within the tile
* */
Mds[ty][tx] = d_M[row * k + ph * TILE_WIDTH + tx];
}
// boundary check
if (ph*TILE_WIDTH + ty < k && col < m){
// saving tile from N
/* indexing thought exercise:
* "ph * TILE_WIDTH" moves the tile "down" to the desired location
* adding "ty" gets us to the desired location within the tile
* multiplying by "k" does the magic (remember row major order)
* adding col moves the tile to the desired column*/
Nds[ty][tx] = d_N[(ph * TILE_WIDTH + ty) * k + col];
}
__syncthreads(); // execution barrier
for (int j = 0; j < TILE_WIDTH; j++){
// performing part of inner product
pval += Mds[ty][j] * Nds[j][tx];
}
__syncthreads();
}
if (row < k && col < m){
d_P[row * k + col] = pval;
}
}
int main(int argc, char const *argv[])
{
int m, n, k; // init matrix dimensions
printf("---------------------------------------------\n");
printf("We will be multiplying two matrices\n");
printf("The first will be of size m x n\n");
printf("The second will be of size n x k\n");
printf("I will have you choose these dimensions!\n");
printf("---------------------------------------------\n\n");
printf("Input m:\n");
scanf("%d", &m);
printf("\nInput n:\n");
scanf("%d", &n);
printf("\nInput k:\n");
scanf("%d", &k);
printf("\n");
// Initialize pointers
int *cpu_a, *cpu_b, *cpu_result, *cpu_c;
// Allocate memory to the pointers on the host
cudaMallocHost((void **) &cpu_a, sizeof(int)*m*n); // matrix a
cudaMallocHost((void **) &cpu_b, sizeof(int)*n*k); // matrix b
cudaMallocHost((void **) &cpu_c, sizeof(int)*m*k); // cpu memory for gpu result
cudaMallocHost((void **) &cpu_result, sizeof(int)*m*k); // cpu result
// Generate the matrices
// cpu_a
for (int i = 0; i < m; i++)
{
for (int j = 0; j < n; j++)
{
cpu_a[i * n + j] = rand () % 1024;
}
}
// cpu_b
for (int i = 0; i < n; i++)
{
for (int j = 0; j < k; j++)
{
cpu_b[n * k + j] = rand () % 1024;
}
}
// variable to keep track of time
float gpu_time;
// create start and stop events
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// ******************************************************************************
// ================================ GPU =========================================
// ******************************************************************************
// the final matrix will have size m x k
// we need to spawn enough threads to compute all of the entries
unsigned int grid_rows = (m + TILE_WIDTH - 1) / TILE_WIDTH;
unsigned int grid_cols = (k + TILE_WIDTH - 1) / TILE_WIDTH;
printf("---------------------------------------------\n");
printf("The resulting matrix will be of size %d x %d\n", m, k);
printf("\nI am launching a grid size of %d x %d blocks\n", grid_rows, grid_cols);
printf("Each block will be %d x %d threads\n",TILE_WIDTH,TILE_WIDTH);
printf("This will give you %d x %d available threads\n",grid_rows*TILE_WIDTH,grid_cols*TILE_WIDTH);
printf("---------------------------------------------\n\n");
printf("Press ENTER to begin computation on GPU (w/o tiling)...\n");
getchar();
getchar();
// start to count execution time of GPU version
cudaEventRecord(start, 0);
// Allocate memory space on the device
int *gpu_a, *gpu_b, *gpu_c;
cudaMalloc((void **) &gpu_a, sizeof(int)*m*n);
cudaMalloc((void **) &gpu_b, sizeof(int)*n*k);
cudaMalloc((void **) &gpu_c, sizeof(int)*m*k);
// copy matrix A and B from host to device memory
cudaMemcpy(gpu_a, gpu_a, sizeof(int)*m*n, cudaMemcpyHostToDevice);
cudaMemcpy(gpu_b, gpu_b, sizeof(int)*n*k, cudaMemcpyHostToDevice);
dim3 dimGrid(grid_cols, grid_rows);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
// Launch kernel
// Kernels will always be launched using triple brackets
// the first input in the triple brackets is the dimension of the grid
// the second is the dimension of the block
gpu_matrix_mult_one<<<dimGrid, dimBlock>>>(gpu_a, gpu_b, gpu_c, m, n, k);
// Transefer results from device to host
cudaMemcpy(cpu_c, gpu_c, sizeof(int)*m*k, cudaMemcpyDeviceToHost);
cudaThreadSynchronize();
// time counting terminate
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
// compute time elapse on GPU computing
cudaEventElapsedTime(&gpu_time, start, stop);
printf("Time elapsed on matrix multiplication of %dx%d * %dx%d on GPU WITHOUT tiling: %f ms.\n\n", m, n, n, k, gpu_time);
printf("Press ENTER to begin computation on GPU (w/tiling)...\n");
getchar();
// start to count execution time of GPU version
cudaEventRecord(start, 0);
// copy matrix A and B from host to device memory
cudaMemcpy(gpu_a, gpu_a, sizeof(int)*m*n, cudaMemcpyHostToDevice);
cudaMemcpy(gpu_b, gpu_b, sizeof(int)*n*k, cudaMemcpyHostToDevice);
// Launch kernel
// Kernels will always be launched using triple brackets
// the first input in the triple brackets is the dimension of the grid
// the second is the dimension of the block
gpu_matrix_mult_two<<<dimGrid, dimBlock>>>(gpu_a, gpu_b, gpu_c, m, n, k);
// Transefer results from device to host
cudaMemcpy(cpu_c, gpu_c, sizeof(int)*m*k, cudaMemcpyDeviceToHost);
cudaThreadSynchronize();
// time counting terminate
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
// compute time elapse on GPU computing
cudaEventElapsedTime(&gpu_time, start, stop);
printf("Time elapsed on matrix multiplication of %dx%d * %dx%d on GPU WITH tiling: %f ms.\n\n", m, n, n, k, gpu_time);
// fin
return 0;
} | .file "tmpxft_00187ba3_00000000-6_mat_mult_tile.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z19gpu_matrix_mult_onePiS_S_iiiPiS_S_iii
.type _Z46__device_stub__Z19gpu_matrix_mult_onePiS_S_iiiPiS_S_iii, @function
_Z46__device_stub__Z19gpu_matrix_mult_onePiS_S_iiiPiS_S_iii:
.LFB2082:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19gpu_matrix_mult_onePiS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z46__device_stub__Z19gpu_matrix_mult_onePiS_S_iiiPiS_S_iii, .-_Z46__device_stub__Z19gpu_matrix_mult_onePiS_S_iiiPiS_S_iii
.globl _Z19gpu_matrix_mult_onePiS_S_iii
.type _Z19gpu_matrix_mult_onePiS_S_iii, @function
_Z19gpu_matrix_mult_onePiS_S_iii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z19gpu_matrix_mult_onePiS_S_iiiPiS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z19gpu_matrix_mult_onePiS_S_iii, .-_Z19gpu_matrix_mult_onePiS_S_iii
.globl _Z46__device_stub__Z19gpu_matrix_mult_twoPiS_S_iiiPiS_S_iii
.type _Z46__device_stub__Z19gpu_matrix_mult_twoPiS_S_iiiPiS_S_iii, @function
_Z46__device_stub__Z19gpu_matrix_mult_twoPiS_S_iiiPiS_S_iii:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19gpu_matrix_mult_twoPiS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z46__device_stub__Z19gpu_matrix_mult_twoPiS_S_iiiPiS_S_iii, .-_Z46__device_stub__Z19gpu_matrix_mult_twoPiS_S_iiiPiS_S_iii
.globl _Z19gpu_matrix_mult_twoPiS_S_iii
.type _Z19gpu_matrix_mult_twoPiS_S_iii, @function
_Z19gpu_matrix_mult_twoPiS_S_iii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z19gpu_matrix_mult_twoPiS_S_iiiPiS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z19gpu_matrix_mult_twoPiS_S_iii, .-_Z19gpu_matrix_mult_twoPiS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "---------------------------------------------\n"
.align 8
.LC1:
.string "We will be multiplying two matrices\n"
.align 8
.LC2:
.string "The first will be of size m x n\n"
.align 8
.LC3:
.string "The second will be of size n x k\n"
.align 8
.LC4:
.string "I will have you choose these dimensions!\n"
.align 8
.LC5:
.string "---------------------------------------------\n\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "Input m:\n"
.LC7:
.string "%d"
.LC8:
.string "\nInput n:\n"
.LC9:
.string "\nInput k:\n"
.LC10:
.string "\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "The resulting matrix will be of size %d x %d\n"
.align 8
.LC12:
.string "\nI am launching a grid size of %d x %d blocks\n"
.align 8
.LC13:
.string "Each block will be %d x %d threads\n"
.align 8
.LC14:
.string "This will give you %d x %d available threads\n"
.align 8
.LC15:
.string "Press ENTER to begin computation on GPU (w/o tiling)...\n"
.align 8
.LC16:
.string "Time elapsed on matrix multiplication of %dx%d * %dx%d on GPU WITHOUT tiling: %f ms.\n\n"
.align 8
.LC17:
.string "Press ENTER to begin computation on GPU (w/tiling)...\n"
.align 8
.LC18:
.string "Time elapsed on matrix multiplication of %dx%d * %dx%d on GPU WITH tiling: %f ms.\n\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $136, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rsi
leaq .LC7(%rip), %rbx
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 12(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq 8(%rsp), %rsi
movslq 12(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMallocHost@PLT
movslq 12(%rsp), %rsi
movslq 16(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 32(%rsp), %rdi
call cudaMallocHost@PLT
movslq 8(%rsp), %rsi
movslq 16(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 48(%rsp), %rdi
call cudaMallocHost@PLT
movslq 8(%rsp), %rsi
movslq 16(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 40(%rsp), %rdi
call cudaMallocHost@PLT
movl $0, %ebp
cmpl $0, 8(%rsp)
jg .L20
.L21:
movl $0, %ebp
cmpl $0, 12(%rsp)
jg .L24
.L25:
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movl 8(%rsp), %eax
leal 30(%rax), %ebx
addl $15, %eax
cmovns %eax, %ebx
sarl $4, %ebx
movl 16(%rsp), %eax
leal 30(%rax), %ebp
addl $15, %eax
cmovns %eax, %ebp
sarl $4, %ebp
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 16(%rsp), %ecx
movl 8(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %ecx
movl %ebx, %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, %ecx
movl $16, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %ecx
sall $4, %ecx
movl %ebx, %edx
sall $4, %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
movq stdin(%rip), %rdi
call getc@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movslq 8(%rsp), %rsi
movslq 12(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 72(%rsp), %rdi
call cudaMalloc@PLT
movslq 12(%rsp), %rsi
movslq 16(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 80(%rsp), %rdi
call cudaMalloc@PLT
movslq 8(%rsp), %rsi
movslq 16(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 88(%rsp), %rdi
call cudaMalloc@PLT
movq 72(%rsp), %rdi
movslq 8(%rsp), %rdx
movslq 12(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rdi, %rsi
call cudaMemcpy@PLT
movq 80(%rsp), %rdi
movslq 12(%rsp), %rdx
movslq 16(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rdi, %rsi
call cudaMemcpy@PLT
movl %ebp, 96(%rsp)
movl %ebx, 100(%rsp)
movl $1, 104(%rsp)
movl $16, 108(%rsp)
movl $16, 112(%rsp)
movl $1, 116(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L28:
movslq 8(%rsp), %rdx
movslq 16(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 88(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
call cudaThreadSynchronize@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl 12(%rsp), %ecx
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
movl 16(%rsp), %r9d
movl %ecx, %r8d
movl 8(%rsp), %edx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 72(%rsp), %rdi
movslq 8(%rsp), %rdx
movslq 12(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rdi, %rsi
call cudaMemcpy@PLT
movq 80(%rsp), %rdi
movslq 12(%rsp), %rdx
movslq 16(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rdi, %rsi
call cudaMemcpy@PLT
movl 116(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movq 96(%rsp), %rdi
movl 104(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L29:
movslq 8(%rsp), %rdx
movslq 16(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 88(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
call cudaThreadSynchronize@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl 12(%rsp), %ecx
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
movl 16(%rsp), %r9d
movl %ecx, %r8d
movl 8(%rsp), %edx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L44
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call rand@PLT
movl %ebp, %edx
imull 12(%rsp), %edx
addl %ebx, %edx
movslq %edx, %rdx
movl %eax, %ecx
sarl $31, %ecx
shrl $22, %ecx
addl %ecx, %eax
andl $1023, %eax
subl %ecx, %eax
movq 24(%rsp), %rcx
movl %eax, (%rcx,%rdx,4)
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L22
.L23:
addl $1, %ebp
cmpl %ebp, 8(%rsp)
jle .L21
.L20:
movl $0, %ebx
cmpl $0, 12(%rsp)
jg .L22
jmp .L23
.L26:
call rand@PLT
movl 12(%rsp), %edx
imull 16(%rsp), %edx
addl %ebx, %edx
movslq %edx, %rdx
movl %eax, %ecx
sarl $31, %ecx
shrl $22, %ecx
addl %ecx, %eax
andl $1023, %eax
subl %ecx, %eax
movq 32(%rsp), %rcx
movl %eax, (%rcx,%rdx,4)
addl $1, %ebx
cmpl %ebx, 16(%rsp)
jg .L26
.L27:
addl $1, %ebp
cmpl %ebp, 12(%rsp)
jle .L25
.L24:
movl $0, %ebx
cmpl $0, 16(%rsp)
jg .L26
jmp .L27
.L42:
movl 16(%rsp), %r9d
movl 12(%rsp), %r8d
movl 8(%rsp), %ecx
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z46__device_stub__Z19gpu_matrix_mult_onePiS_S_iiiPiS_S_iii
jmp .L28
.L43:
movl 16(%rsp), %r9d
movl 12(%rsp), %r8d
movl 8(%rsp), %ecx
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z46__device_stub__Z19gpu_matrix_mult_twoPiS_S_iiiPiS_S_iii
jmp .L29
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC19:
.string "_Z19gpu_matrix_mult_twoPiS_S_iii"
.align 8
.LC20:
.string "_Z19gpu_matrix_mult_onePiS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z19gpu_matrix_mult_twoPiS_S_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z19gpu_matrix_mult_onePiS_S_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime_api.h>
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#define TILE_WIDTH 16
__global__ void gpu_matrix_mult_one(int *a, int *b, int *c, int m, int n, int k)
{
int row = blockIdx.y * blockDim.y + threadIdx.y; // get the row
int col = blockIdx.x * blockDim.x + threadIdx.x; // get the column
int sum = 0; // initialize the sum
if( col < k && row < m) // check to make sure that the thread needs to compute
{
for(int i = 0; i < n; i++)
{
sum += a[row * n + i] * b[i * k + col];
}
c[row * k + col] = sum;
}
}
__global__ void gpu_matrix_mult_two(int *d_M, int *d_N, int *d_P, int m, int n, int k)
{
// shared memory for tiling
__shared__ int Mds [TILE_WIDTH][TILE_WIDTH];
__shared__ int Nds [TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// recall that TILE_WIDTH = blockDim
int row = by * TILE_WIDTH + ty;
int col = bx * TILE_WIDTH + tx;
int pval = 0;
// this loop is iterating through cols of M and rows of N
// recall that n is the shared inner dimension, that's why we're using it
// to define our loop size
for (int ph = 0; ph < n / TILE_WIDTH; ph++){
// boundary check for shared Mds
if (row < k && ph * TILE_WIDTH + tx < m){
// saving tile from M
/* indexing thought exercise:
* "row * k" gets us to our desired row in M
* adding "ph * TILE_WIDTH" moves our tile over to the desired tile location
* adding "tx" moves us to the desired location within the tile
* */
Mds[ty][tx] = d_M[row * k + ph * TILE_WIDTH + tx];
}
// boundary check
if (ph*TILE_WIDTH + ty < k && col < m){
// saving tile from N
/* indexing thought exercise:
* "ph * TILE_WIDTH" moves the tile "down" to the desired location
* adding "ty" gets us to the desired location within the tile
* multiplying by "k" does the magic (remember row major order)
* adding col moves the tile to the desired column*/
Nds[ty][tx] = d_N[(ph * TILE_WIDTH + ty) * k + col];
}
__syncthreads(); // execution barrier
for (int j = 0; j < TILE_WIDTH; j++){
// performing part of inner product
pval += Mds[ty][j] * Nds[j][tx];
}
__syncthreads();
}
if (row < k && col < m){
d_P[row * k + col] = pval;
}
}
int main(int argc, char const *argv[])
{
int m, n, k; // init matrix dimensions
printf("---------------------------------------------\n");
printf("We will be multiplying two matrices\n");
printf("The first will be of size m x n\n");
printf("The second will be of size n x k\n");
printf("I will have you choose these dimensions!\n");
printf("---------------------------------------------\n\n");
printf("Input m:\n");
scanf("%d", &m);
printf("\nInput n:\n");
scanf("%d", &n);
printf("\nInput k:\n");
scanf("%d", &k);
printf("\n");
// Initialize pointers
int *cpu_a, *cpu_b, *cpu_result, *cpu_c;
// Allocate memory to the pointers on the host
cudaMallocHost((void **) &cpu_a, sizeof(int)*m*n); // matrix a
cudaMallocHost((void **) &cpu_b, sizeof(int)*n*k); // matrix b
cudaMallocHost((void **) &cpu_c, sizeof(int)*m*k); // cpu memory for gpu result
cudaMallocHost((void **) &cpu_result, sizeof(int)*m*k); // cpu result
// Generate the matrices
// cpu_a
for (int i = 0; i < m; i++)
{
for (int j = 0; j < n; j++)
{
cpu_a[i * n + j] = rand () % 1024;
}
}
// cpu_b
for (int i = 0; i < n; i++)
{
for (int j = 0; j < k; j++)
{
cpu_b[n * k + j] = rand () % 1024;
}
}
// variable to keep track of time
float gpu_time;
// create start and stop events
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// ******************************************************************************
// ================================ GPU =========================================
// ******************************************************************************
// the final matrix will have size m x k
// we need to spawn enough threads to compute all of the entries
unsigned int grid_rows = (m + TILE_WIDTH - 1) / TILE_WIDTH;
unsigned int grid_cols = (k + TILE_WIDTH - 1) / TILE_WIDTH;
printf("---------------------------------------------\n");
printf("The resulting matrix will be of size %d x %d\n", m, k);
printf("\nI am launching a grid size of %d x %d blocks\n", grid_rows, grid_cols);
printf("Each block will be %d x %d threads\n",TILE_WIDTH,TILE_WIDTH);
printf("This will give you %d x %d available threads\n",grid_rows*TILE_WIDTH,grid_cols*TILE_WIDTH);
printf("---------------------------------------------\n\n");
printf("Press ENTER to begin computation on GPU (w/o tiling)...\n");
getchar();
getchar();
// start to count execution time of GPU version
cudaEventRecord(start, 0);
// Allocate memory space on the device
int *gpu_a, *gpu_b, *gpu_c;
cudaMalloc((void **) &gpu_a, sizeof(int)*m*n);
cudaMalloc((void **) &gpu_b, sizeof(int)*n*k);
cudaMalloc((void **) &gpu_c, sizeof(int)*m*k);
// copy matrix A and B from host to device memory
cudaMemcpy(gpu_a, gpu_a, sizeof(int)*m*n, cudaMemcpyHostToDevice);
cudaMemcpy(gpu_b, gpu_b, sizeof(int)*n*k, cudaMemcpyHostToDevice);
dim3 dimGrid(grid_cols, grid_rows);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
// Launch kernel
// Kernels will always be launched using triple brackets
// the first input in the triple brackets is the dimension of the grid
// the second is the dimension of the block
gpu_matrix_mult_one<<<dimGrid, dimBlock>>>(gpu_a, gpu_b, gpu_c, m, n, k);
// Transefer results from device to host
cudaMemcpy(cpu_c, gpu_c, sizeof(int)*m*k, cudaMemcpyDeviceToHost);
cudaThreadSynchronize();
// time counting terminate
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
// compute time elapse on GPU computing
cudaEventElapsedTime(&gpu_time, start, stop);
printf("Time elapsed on matrix multiplication of %dx%d * %dx%d on GPU WITHOUT tiling: %f ms.\n\n", m, n, n, k, gpu_time);
printf("Press ENTER to begin computation on GPU (w/tiling)...\n");
getchar();
// start to count execution time of GPU version
cudaEventRecord(start, 0);
// copy matrix A and B from host to device memory
cudaMemcpy(gpu_a, gpu_a, sizeof(int)*m*n, cudaMemcpyHostToDevice);
cudaMemcpy(gpu_b, gpu_b, sizeof(int)*n*k, cudaMemcpyHostToDevice);
// Launch kernel
// Kernels will always be launched using triple brackets
// the first input in the triple brackets is the dimension of the grid
// the second is the dimension of the block
gpu_matrix_mult_two<<<dimGrid, dimBlock>>>(gpu_a, gpu_b, gpu_c, m, n, k);
// Transefer results from device to host
cudaMemcpy(cpu_c, gpu_c, sizeof(int)*m*k, cudaMemcpyDeviceToHost);
cudaThreadSynchronize();
// time counting terminate
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
// compute time elapse on GPU computing
cudaEventElapsedTime(&gpu_time, start, stop);
printf("Time elapsed on matrix multiplication of %dx%d * %dx%d on GPU WITH tiling: %f ms.\n\n", m, n, n, k, gpu_time);
// fin
return 0;
} | #include <hip/hip_runtime_api.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#define TILE_WIDTH 16
__global__ void gpu_matrix_mult_one(int *a, int *b, int *c, int m, int n, int k)
{
int row = blockIdx.y * blockDim.y + threadIdx.y; // get the row
int col = blockIdx.x * blockDim.x + threadIdx.x; // get the column
int sum = 0; // initialize the sum
if( col < k && row < m) // check to make sure that the thread needs to compute
{
for(int i = 0; i < n; i++)
{
sum += a[row * n + i] * b[i * k + col];
}
c[row * k + col] = sum;
}
}
__global__ void gpu_matrix_mult_two(int *d_M, int *d_N, int *d_P, int m, int n, int k)
{
// shared memory for tiling
__shared__ int Mds [TILE_WIDTH][TILE_WIDTH];
__shared__ int Nds [TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// recall that TILE_WIDTH = blockDim
int row = by * TILE_WIDTH + ty;
int col = bx * TILE_WIDTH + tx;
int pval = 0;
// this loop is iterating through cols of M and rows of N
// recall that n is the shared inner dimension, that's why we're using it
// to define our loop size
for (int ph = 0; ph < n / TILE_WIDTH; ph++){
// boundary check for shared Mds
if (row < k && ph * TILE_WIDTH + tx < m){
// saving tile from M
/* indexing thought exercise:
* "row * k" gets us to our desired row in M
* adding "ph * TILE_WIDTH" moves our tile over to the desired tile location
* adding "tx" moves us to the desired location within the tile
* */
Mds[ty][tx] = d_M[row * k + ph * TILE_WIDTH + tx];
}
// boundary check
if (ph*TILE_WIDTH + ty < k && col < m){
// saving tile from N
/* indexing thought exercise:
* "ph * TILE_WIDTH" moves the tile "down" to the desired location
* adding "ty" gets us to the desired location within the tile
* multiplying by "k" does the magic (remember row major order)
* adding col moves the tile to the desired column*/
Nds[ty][tx] = d_N[(ph * TILE_WIDTH + ty) * k + col];
}
__syncthreads(); // execution barrier
for (int j = 0; j < TILE_WIDTH; j++){
// performing part of inner product
pval += Mds[ty][j] * Nds[j][tx];
}
__syncthreads();
}
if (row < k && col < m){
d_P[row * k + col] = pval;
}
}
int main(int argc, char const *argv[])
{
int m, n, k; // init matrix dimensions
printf("---------------------------------------------\n");
printf("We will be multiplying two matrices\n");
printf("The first will be of size m x n\n");
printf("The second will be of size n x k\n");
printf("I will have you choose these dimensions!\n");
printf("---------------------------------------------\n\n");
printf("Input m:\n");
scanf("%d", &m);
printf("\nInput n:\n");
scanf("%d", &n);
printf("\nInput k:\n");
scanf("%d", &k);
printf("\n");
// Initialize pointers
int *cpu_a, *cpu_b, *cpu_result, *cpu_c;
// Allocate memory to the pointers on the host
hipHostMalloc((void **) &cpu_a, sizeof(int)*m*n, hipHostMallocDefault); // matrix a
hipHostMalloc((void **) &cpu_b, sizeof(int)*n*k, hipHostMallocDefault); // matrix b
hipHostMalloc((void **) &cpu_c, sizeof(int)*m*k, hipHostMallocDefault); // cpu memory for gpu result
hipHostMalloc((void **) &cpu_result, sizeof(int)*m*k, hipHostMallocDefault); // cpu result
// Generate the matrices
// cpu_a
for (int i = 0; i < m; i++)
{
for (int j = 0; j < n; j++)
{
cpu_a[i * n + j] = rand () % 1024;
}
}
// cpu_b
for (int i = 0; i < n; i++)
{
for (int j = 0; j < k; j++)
{
cpu_b[n * k + j] = rand () % 1024;
}
}
// variable to keep track of time
float gpu_time;
// create start and stop events
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// ******************************************************************************
// ================================ GPU =========================================
// ******************************************************************************
// the final matrix will have size m x k
// we need to spawn enough threads to compute all of the entries
unsigned int grid_rows = (m + TILE_WIDTH - 1) / TILE_WIDTH;
unsigned int grid_cols = (k + TILE_WIDTH - 1) / TILE_WIDTH;
printf("---------------------------------------------\n");
printf("The resulting matrix will be of size %d x %d\n", m, k);
printf("\nI am launching a grid size of %d x %d blocks\n", grid_rows, grid_cols);
printf("Each block will be %d x %d threads\n",TILE_WIDTH,TILE_WIDTH);
printf("This will give you %d x %d available threads\n",grid_rows*TILE_WIDTH,grid_cols*TILE_WIDTH);
printf("---------------------------------------------\n\n");
printf("Press ENTER to begin computation on GPU (w/o tiling)...\n");
getchar();
getchar();
// start to count execution time of GPU version
hipEventRecord(start, 0);
// Allocate memory space on the device
int *gpu_a, *gpu_b, *gpu_c;
hipMalloc((void **) &gpu_a, sizeof(int)*m*n);
hipMalloc((void **) &gpu_b, sizeof(int)*n*k);
hipMalloc((void **) &gpu_c, sizeof(int)*m*k);
// copy matrix A and B from host to device memory
hipMemcpy(gpu_a, gpu_a, sizeof(int)*m*n, hipMemcpyHostToDevice);
hipMemcpy(gpu_b, gpu_b, sizeof(int)*n*k, hipMemcpyHostToDevice);
dim3 dimGrid(grid_cols, grid_rows);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
// Launch kernel
// Kernels will always be launched using triple brackets
// the first input in the triple brackets is the dimension of the grid
// the second is the dimension of the block
gpu_matrix_mult_one<<<dimGrid, dimBlock>>>(gpu_a, gpu_b, gpu_c, m, n, k);
// Transefer results from device to host
hipMemcpy(cpu_c, gpu_c, sizeof(int)*m*k, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
// time counting terminate
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
// compute time elapse on GPU computing
hipEventElapsedTime(&gpu_time, start, stop);
printf("Time elapsed on matrix multiplication of %dx%d * %dx%d on GPU WITHOUT tiling: %f ms.\n\n", m, n, n, k, gpu_time);
printf("Press ENTER to begin computation on GPU (w/tiling)...\n");
getchar();
// start to count execution time of GPU version
hipEventRecord(start, 0);
// copy matrix A and B from host to device memory
hipMemcpy(gpu_a, gpu_a, sizeof(int)*m*n, hipMemcpyHostToDevice);
hipMemcpy(gpu_b, gpu_b, sizeof(int)*n*k, hipMemcpyHostToDevice);
// Launch kernel
// Kernels will always be launched using triple brackets
// the first input in the triple brackets is the dimension of the grid
// the second is the dimension of the block
gpu_matrix_mult_two<<<dimGrid, dimBlock>>>(gpu_a, gpu_b, gpu_c, m, n, k);
// Transefer results from device to host
hipMemcpy(cpu_c, gpu_c, sizeof(int)*m*k, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
// time counting terminate
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
// compute time elapse on GPU computing
hipEventElapsedTime(&gpu_time, start, stop);
printf("Time elapsed on matrix multiplication of %dx%d * %dx%d on GPU WITH tiling: %f ms.\n\n", m, n, n, k, gpu_time);
// fin
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime_api.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#define TILE_WIDTH 16
__global__ void gpu_matrix_mult_one(int *a, int *b, int *c, int m, int n, int k)
{
int row = blockIdx.y * blockDim.y + threadIdx.y; // get the row
int col = blockIdx.x * blockDim.x + threadIdx.x; // get the column
int sum = 0; // initialize the sum
if( col < k && row < m) // check to make sure that the thread needs to compute
{
for(int i = 0; i < n; i++)
{
sum += a[row * n + i] * b[i * k + col];
}
c[row * k + col] = sum;
}
}
__global__ void gpu_matrix_mult_two(int *d_M, int *d_N, int *d_P, int m, int n, int k)
{
// shared memory for tiling
__shared__ int Mds [TILE_WIDTH][TILE_WIDTH];
__shared__ int Nds [TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// recall that TILE_WIDTH = blockDim
int row = by * TILE_WIDTH + ty;
int col = bx * TILE_WIDTH + tx;
int pval = 0;
// this loop is iterating through cols of M and rows of N
// recall that n is the shared inner dimension, that's why we're using it
// to define our loop size
for (int ph = 0; ph < n / TILE_WIDTH; ph++){
// boundary check for shared Mds
if (row < k && ph * TILE_WIDTH + tx < m){
// saving tile from M
/* indexing thought exercise:
* "row * k" gets us to our desired row in M
* adding "ph * TILE_WIDTH" moves our tile over to the desired tile location
* adding "tx" moves us to the desired location within the tile
* */
Mds[ty][tx] = d_M[row * k + ph * TILE_WIDTH + tx];
}
// boundary check
if (ph*TILE_WIDTH + ty < k && col < m){
// saving tile from N
/* indexing thought exercise:
* "ph * TILE_WIDTH" moves the tile "down" to the desired location
* adding "ty" gets us to the desired location within the tile
* multiplying by "k" does the magic (remember row major order)
* adding col moves the tile to the desired column*/
Nds[ty][tx] = d_N[(ph * TILE_WIDTH + ty) * k + col];
}
__syncthreads(); // execution barrier
for (int j = 0; j < TILE_WIDTH; j++){
// performing part of inner product
pval += Mds[ty][j] * Nds[j][tx];
}
__syncthreads();
}
if (row < k && col < m){
d_P[row * k + col] = pval;
}
}
int main(int argc, char const *argv[])
{
int m, n, k; // init matrix dimensions
printf("---------------------------------------------\n");
printf("We will be multiplying two matrices\n");
printf("The first will be of size m x n\n");
printf("The second will be of size n x k\n");
printf("I will have you choose these dimensions!\n");
printf("---------------------------------------------\n\n");
printf("Input m:\n");
scanf("%d", &m);
printf("\nInput n:\n");
scanf("%d", &n);
printf("\nInput k:\n");
scanf("%d", &k);
printf("\n");
// Initialize pointers
int *cpu_a, *cpu_b, *cpu_result, *cpu_c;
// Allocate memory to the pointers on the host
hipHostMalloc((void **) &cpu_a, sizeof(int)*m*n, hipHostMallocDefault); // matrix a
hipHostMalloc((void **) &cpu_b, sizeof(int)*n*k, hipHostMallocDefault); // matrix b
hipHostMalloc((void **) &cpu_c, sizeof(int)*m*k, hipHostMallocDefault); // cpu memory for gpu result
hipHostMalloc((void **) &cpu_result, sizeof(int)*m*k, hipHostMallocDefault); // cpu result
// Generate the matrices
// cpu_a
for (int i = 0; i < m; i++)
{
for (int j = 0; j < n; j++)
{
cpu_a[i * n + j] = rand () % 1024;
}
}
// cpu_b
for (int i = 0; i < n; i++)
{
for (int j = 0; j < k; j++)
{
cpu_b[n * k + j] = rand () % 1024;
}
}
// variable to keep track of time
float gpu_time;
// create start and stop events
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// ******************************************************************************
// ================================ GPU =========================================
// ******************************************************************************
// the final matrix will have size m x k
// we need to spawn enough threads to compute all of the entries
unsigned int grid_rows = (m + TILE_WIDTH - 1) / TILE_WIDTH;
unsigned int grid_cols = (k + TILE_WIDTH - 1) / TILE_WIDTH;
printf("---------------------------------------------\n");
printf("The resulting matrix will be of size %d x %d\n", m, k);
printf("\nI am launching a grid size of %d x %d blocks\n", grid_rows, grid_cols);
printf("Each block will be %d x %d threads\n",TILE_WIDTH,TILE_WIDTH);
printf("This will give you %d x %d available threads\n",grid_rows*TILE_WIDTH,grid_cols*TILE_WIDTH);
printf("---------------------------------------------\n\n");
printf("Press ENTER to begin computation on GPU (w/o tiling)...\n");
getchar();
getchar();
// start to count execution time of GPU version
hipEventRecord(start, 0);
// Allocate memory space on the device
int *gpu_a, *gpu_b, *gpu_c;
hipMalloc((void **) &gpu_a, sizeof(int)*m*n);
hipMalloc((void **) &gpu_b, sizeof(int)*n*k);
hipMalloc((void **) &gpu_c, sizeof(int)*m*k);
// copy matrix A and B from host to device memory
hipMemcpy(gpu_a, gpu_a, sizeof(int)*m*n, hipMemcpyHostToDevice);
hipMemcpy(gpu_b, gpu_b, sizeof(int)*n*k, hipMemcpyHostToDevice);
dim3 dimGrid(grid_cols, grid_rows);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
// Launch kernel
// Kernels will always be launched using triple brackets
// the first input in the triple brackets is the dimension of the grid
// the second is the dimension of the block
gpu_matrix_mult_one<<<dimGrid, dimBlock>>>(gpu_a, gpu_b, gpu_c, m, n, k);
// Transefer results from device to host
hipMemcpy(cpu_c, gpu_c, sizeof(int)*m*k, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
// time counting terminate
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
// compute time elapse on GPU computing
hipEventElapsedTime(&gpu_time, start, stop);
printf("Time elapsed on matrix multiplication of %dx%d * %dx%d on GPU WITHOUT tiling: %f ms.\n\n", m, n, n, k, gpu_time);
printf("Press ENTER to begin computation on GPU (w/tiling)...\n");
getchar();
// start to count execution time of GPU version
hipEventRecord(start, 0);
// copy matrix A and B from host to device memory
hipMemcpy(gpu_a, gpu_a, sizeof(int)*m*n, hipMemcpyHostToDevice);
hipMemcpy(gpu_b, gpu_b, sizeof(int)*n*k, hipMemcpyHostToDevice);
// Launch kernel
// Kernels will always be launched using triple brackets
// the first input in the triple brackets is the dimension of the grid
// the second is the dimension of the block
gpu_matrix_mult_two<<<dimGrid, dimBlock>>>(gpu_a, gpu_b, gpu_c, m, n, k);
// Transefer results from device to host
hipMemcpy(cpu_c, gpu_c, sizeof(int)*m*k, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
// time counting terminate
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
// compute time elapse on GPU computing
hipEventElapsedTime(&gpu_time, start, stop);
printf("Time elapsed on matrix multiplication of %dx%d * %dx%d on GPU WITH tiling: %f ms.\n\n", m, n, n, k, gpu_time);
// fin
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19gpu_matrix_mult_onePiS_S_iii
.globl _Z19gpu_matrix_mult_onePiS_S_iii
.p2align 8
.type _Z19gpu_matrix_mult_onePiS_S_iii,@function
_Z19gpu_matrix_mult_onePiS_S_iii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_load_b32 s4, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s5, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s3, v0
v_cmp_gt_i32_e64 s2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s2, s2, -1
s_cmp_eq_u32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s3, v5
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v1, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19gpu_matrix_mult_onePiS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19gpu_matrix_mult_onePiS_S_iii, .Lfunc_end0-_Z19gpu_matrix_mult_onePiS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z19gpu_matrix_mult_twoPiS_S_iii
.globl _Z19gpu_matrix_mult_twoPiS_S_iii
.p2align 8
.type _Z19gpu_matrix_mult_twoPiS_S_iii,@function
_Z19gpu_matrix_mult_twoPiS_S_iii:
s_clause 0x1
s_load_b32 s10, s[0:1], 0x20
s_load_b64 s[8:9], s[0:1], 0x18
v_bfe_u32 v6, v0, 10, 10
v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v1, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v5, s15, 4, v6
v_lshl_add_u32 v0, s14, 4, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s10, v5
v_cmp_gt_i32_e64 s2, s8, v0
s_cmp_lt_i32 s9, 16
s_cbranch_scc1 .LBB1_9
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v1
v_lshlrev_b32_e32 v7, 6, v6
s_ashr_i32 s3, s9, 31
s_mov_b32 s11, 0
s_lshr_b32 s3, s3, 28
v_add_nc_u32_e32 v8, 0x400, v2
v_mad_u64_u32 v[3:4], null, v5, s10, v[1:2]
v_add_nc_u32_e32 v4, v7, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v9, v8, v7
s_add_i32 s3, s9, s3
s_ashr_i32 s9, s3, 4
.LBB1_2:
s_lshl_b32 s13, s11, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v10, s13, v1
v_cmp_gt_i32_e64 s3, s8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, vcc_lo, s3
s_and_saveexec_b32 s12, s3
s_cbranch_execz .LBB1_4
v_add_nc_u32_e32 v10, s13, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v10, s3, s4, v10
v_add_co_ci_u32_e64 v11, s3, s5, v11, s3
global_load_b32 v10, v[10:11], off
s_waitcnt vmcnt(0)
ds_store_b32 v4, v10
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s12
v_lshl_add_u32 v10, s11, 4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s3, s10, v10
s_and_b32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s12, s3
s_cbranch_execz .LBB1_6
v_mad_u64_u32 v[11:12], null, v10, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[10:11], 2, v[11:12]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v10, s3, s6, v10
v_add_co_ci_u32_e64 v11, s3, s7, v11, s3
global_load_b32 v10, v[10:11], off
s_waitcnt vmcnt(0)
ds_store_b32 v9, v10
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s12
v_mov_b32_e32 v10, v8
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB1_7:
v_add_nc_u32_e32 v11, s3, v7
s_add_i32 s3, s3, 4
ds_load_b32 v13, v10
ds_load_b32 v14, v11
v_add_nc_u32_e32 v10, 64, v10
s_cmp_eq_u32 s3, 64
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[11:12], null, v13, v14, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v11
s_cbranch_scc0 .LBB1_7
s_add_i32 s11, s11, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s11, s9
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_2
.LBB1_9:
v_cmp_gt_i32_e32 vcc_lo, s10, v5
v_cmp_gt_i32_e64 s2, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_11
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v5, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB1_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19gpu_matrix_mult_twoPiS_S_iii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z19gpu_matrix_mult_twoPiS_S_iii, .Lfunc_end1-_Z19gpu_matrix_mult_twoPiS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19gpu_matrix_mult_onePiS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19gpu_matrix_mult_onePiS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19gpu_matrix_mult_twoPiS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19gpu_matrix_mult_twoPiS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime_api.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#define TILE_WIDTH 16
__global__ void gpu_matrix_mult_one(int *a, int *b, int *c, int m, int n, int k)
{
int row = blockIdx.y * blockDim.y + threadIdx.y; // get the row
int col = blockIdx.x * blockDim.x + threadIdx.x; // get the column
int sum = 0; // initialize the sum
if( col < k && row < m) // check to make sure that the thread needs to compute
{
for(int i = 0; i < n; i++)
{
sum += a[row * n + i] * b[i * k + col];
}
c[row * k + col] = sum;
}
}
__global__ void gpu_matrix_mult_two(int *d_M, int *d_N, int *d_P, int m, int n, int k)
{
// shared memory for tiling
__shared__ int Mds [TILE_WIDTH][TILE_WIDTH];
__shared__ int Nds [TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// recall that TILE_WIDTH = blockDim
int row = by * TILE_WIDTH + ty;
int col = bx * TILE_WIDTH + tx;
int pval = 0;
// this loop is iterating through cols of M and rows of N
// recall that n is the shared inner dimension, that's why we're using it
// to define our loop size
for (int ph = 0; ph < n / TILE_WIDTH; ph++){
// boundary check for shared Mds
if (row < k && ph * TILE_WIDTH + tx < m){
// saving tile from M
/* indexing thought exercise:
* "row * k" gets us to our desired row in M
* adding "ph * TILE_WIDTH" moves our tile over to the desired tile location
* adding "tx" moves us to the desired location within the tile
* */
Mds[ty][tx] = d_M[row * k + ph * TILE_WIDTH + tx];
}
// boundary check
if (ph*TILE_WIDTH + ty < k && col < m){
// saving tile from N
/* indexing thought exercise:
* "ph * TILE_WIDTH" moves the tile "down" to the desired location
* adding "ty" gets us to the desired location within the tile
* multiplying by "k" does the magic (remember row major order)
* adding col moves the tile to the desired column*/
Nds[ty][tx] = d_N[(ph * TILE_WIDTH + ty) * k + col];
}
__syncthreads(); // execution barrier
for (int j = 0; j < TILE_WIDTH; j++){
// performing part of inner product
pval += Mds[ty][j] * Nds[j][tx];
}
__syncthreads();
}
if (row < k && col < m){
d_P[row * k + col] = pval;
}
}
int main(int argc, char const *argv[])
{
int m, n, k; // init matrix dimensions
printf("---------------------------------------------\n");
printf("We will be multiplying two matrices\n");
printf("The first will be of size m x n\n");
printf("The second will be of size n x k\n");
printf("I will have you choose these dimensions!\n");
printf("---------------------------------------------\n\n");
printf("Input m:\n");
scanf("%d", &m);
printf("\nInput n:\n");
scanf("%d", &n);
printf("\nInput k:\n");
scanf("%d", &k);
printf("\n");
// Initialize pointers
int *cpu_a, *cpu_b, *cpu_result, *cpu_c;
// Allocate memory to the pointers on the host
hipHostMalloc((void **) &cpu_a, sizeof(int)*m*n, hipHostMallocDefault); // matrix a
hipHostMalloc((void **) &cpu_b, sizeof(int)*n*k, hipHostMallocDefault); // matrix b
hipHostMalloc((void **) &cpu_c, sizeof(int)*m*k, hipHostMallocDefault); // cpu memory for gpu result
hipHostMalloc((void **) &cpu_result, sizeof(int)*m*k, hipHostMallocDefault); // cpu result
// Generate the matrices
// cpu_a
for (int i = 0; i < m; i++)
{
for (int j = 0; j < n; j++)
{
cpu_a[i * n + j] = rand () % 1024;
}
}
// cpu_b
for (int i = 0; i < n; i++)
{
for (int j = 0; j < k; j++)
{
cpu_b[n * k + j] = rand () % 1024;
}
}
// variable to keep track of time
float gpu_time;
// create start and stop events
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// ******************************************************************************
// ================================ GPU =========================================
// ******************************************************************************
// the final matrix will have size m x k
// we need to spawn enough threads to compute all of the entries
unsigned int grid_rows = (m + TILE_WIDTH - 1) / TILE_WIDTH;
unsigned int grid_cols = (k + TILE_WIDTH - 1) / TILE_WIDTH;
printf("---------------------------------------------\n");
printf("The resulting matrix will be of size %d x %d\n", m, k);
printf("\nI am launching a grid size of %d x %d blocks\n", grid_rows, grid_cols);
printf("Each block will be %d x %d threads\n",TILE_WIDTH,TILE_WIDTH);
printf("This will give you %d x %d available threads\n",grid_rows*TILE_WIDTH,grid_cols*TILE_WIDTH);
printf("---------------------------------------------\n\n");
printf("Press ENTER to begin computation on GPU (w/o tiling)...\n");
getchar();
getchar();
// start to count execution time of GPU version
hipEventRecord(start, 0);
// Allocate memory space on the device
int *gpu_a, *gpu_b, *gpu_c;
hipMalloc((void **) &gpu_a, sizeof(int)*m*n);
hipMalloc((void **) &gpu_b, sizeof(int)*n*k);
hipMalloc((void **) &gpu_c, sizeof(int)*m*k);
// copy matrix A and B from host to device memory
hipMemcpy(gpu_a, gpu_a, sizeof(int)*m*n, hipMemcpyHostToDevice);
hipMemcpy(gpu_b, gpu_b, sizeof(int)*n*k, hipMemcpyHostToDevice);
dim3 dimGrid(grid_cols, grid_rows);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
// Launch kernel
// Kernels will always be launched using triple brackets
// the first input in the triple brackets is the dimension of the grid
// the second is the dimension of the block
gpu_matrix_mult_one<<<dimGrid, dimBlock>>>(gpu_a, gpu_b, gpu_c, m, n, k);
// Transefer results from device to host
hipMemcpy(cpu_c, gpu_c, sizeof(int)*m*k, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
// time counting terminate
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
// compute time elapse on GPU computing
hipEventElapsedTime(&gpu_time, start, stop);
printf("Time elapsed on matrix multiplication of %dx%d * %dx%d on GPU WITHOUT tiling: %f ms.\n\n", m, n, n, k, gpu_time);
printf("Press ENTER to begin computation on GPU (w/tiling)...\n");
getchar();
// start to count execution time of GPU version
hipEventRecord(start, 0);
// copy matrix A and B from host to device memory
hipMemcpy(gpu_a, gpu_a, sizeof(int)*m*n, hipMemcpyHostToDevice);
hipMemcpy(gpu_b, gpu_b, sizeof(int)*n*k, hipMemcpyHostToDevice);
// Launch kernel
// Kernels will always be launched using triple brackets
// the first input in the triple brackets is the dimension of the grid
// the second is the dimension of the block
gpu_matrix_mult_two<<<dimGrid, dimBlock>>>(gpu_a, gpu_b, gpu_c, m, n, k);
// Transefer results from device to host
hipMemcpy(cpu_c, gpu_c, sizeof(int)*m*k, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
// time counting terminate
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
// compute time elapse on GPU computing
hipEventElapsedTime(&gpu_time, start, stop);
printf("Time elapsed on matrix multiplication of %dx%d * %dx%d on GPU WITH tiling: %f ms.\n\n", m, n, n, k, gpu_time);
// fin
return 0;
} | .text
.file "mat_mult_tile.hip"
.globl _Z34__device_stub__gpu_matrix_mult_onePiS_S_iii # -- Begin function _Z34__device_stub__gpu_matrix_mult_onePiS_S_iii
.p2align 4, 0x90
.type _Z34__device_stub__gpu_matrix_mult_onePiS_S_iii,@function
_Z34__device_stub__gpu_matrix_mult_onePiS_S_iii: # @_Z34__device_stub__gpu_matrix_mult_onePiS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19gpu_matrix_mult_onePiS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z34__device_stub__gpu_matrix_mult_onePiS_S_iii, .Lfunc_end0-_Z34__device_stub__gpu_matrix_mult_onePiS_S_iii
.cfi_endproc
# -- End function
.globl _Z34__device_stub__gpu_matrix_mult_twoPiS_S_iii # -- Begin function _Z34__device_stub__gpu_matrix_mult_twoPiS_S_iii
.p2align 4, 0x90
.type _Z34__device_stub__gpu_matrix_mult_twoPiS_S_iii,@function
_Z34__device_stub__gpu_matrix_mult_twoPiS_S_iii: # @_Z34__device_stub__gpu_matrix_mult_twoPiS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19gpu_matrix_mult_twoPiS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z34__device_stub__gpu_matrix_mult_twoPiS_S_iii, .Lfunc_end1-_Z34__device_stub__gpu_matrix_mult_twoPiS_S_iii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $240, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.Lstr.9, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
movl $.Lstr.4, %edi
callq puts@PLT
movl $.Lstr.10, %edi
callq puts@PLT
movl $.Lstr.6, %edi
callq puts@PLT
xorl %ebx, %ebx
leaq 20(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.Lstr.7, %edi
callq puts@PLT
leaq 16(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.Lstr.8, %edi
callq puts@PLT
leaq 12(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $10, %edi
callq putchar@PLT
movslq 20(%rsp), %rax
movslq 16(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 224(%rsp), %rdi
xorl %edx, %edx
callq hipHostMalloc
movslq 16(%rsp), %rax
movslq 12(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 216(%rsp), %rdi
xorl %edx, %edx
callq hipHostMalloc
movslq 20(%rsp), %rax
movslq 12(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 152(%rsp), %rdi
xorl %edx, %edx
callq hipHostMalloc
movslq 20(%rsp), %rax
movslq 12(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 232(%rsp), %rdi
xorl %edx, %edx
callq hipHostMalloc
cmpl $0, 20(%rsp)
jg .LBB2_1
.LBB2_5: # %.preheader60
cmpl $0, 16(%rsp)
jle .LBB2_11
# %bb.6: # %.preheader.preheader
xorl %ebx, %ebx
jmp .LBB2_7
.p2align 4, 0x90
.LBB2_4: # %._crit_edge
# in Loop: Header=BB2_1 Depth=1
incl %ebx
cmpl 20(%rsp), %ebx
jge .LBB2_5
.LBB2_1: # %.preheader61
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
cmpl $0, 16(%rsp)
jle .LBB2_4
# %bb.2: # %.lr.ph.preheader
# in Loop: Header=BB2_1 Depth=1
movslq %ebx, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph
# Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
# kill: def $eax killed $eax def $rax
leal 1023(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-1024, %ecx # imm = 0xFC00
subl %ecx, %eax
movq 224(%rsp), %rcx
movslq 16(%rsp), %rdx
imulq %r14, %rdx
addq %r15, %rdx
movl %eax, (%rcx,%rdx,4)
incq %r15
cmpl 16(%rsp), %r15d
jl .LBB2_3
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_10: # %._crit_edge66
# in Loop: Header=BB2_7 Depth=1
incl %ebx
cmpl 16(%rsp), %ebx
jge .LBB2_11
.LBB2_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_9 Depth 2
cmpl $0, 12(%rsp)
jle .LBB2_10
# %bb.8: # %.lr.ph65.preheader
# in Loop: Header=BB2_7 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_9: # %.lr.ph65
# Parent Loop BB2_7 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
# kill: def $eax killed $eax def $rax
leal 1023(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-1024, %ecx # imm = 0xFC00
subl %ecx, %eax
movq 216(%rsp), %rcx
movslq 16(%rsp), %rdx
movslq 12(%rsp), %rsi
imulq %rdx, %rsi
addq %r14, %rsi
movl %eax, (%rcx,%rsi,4)
incq %r14
cmpl 12(%rsp), %r14d
jl .LBB2_9
jmp .LBB2_10
.LBB2_11: # %._crit_edge68
movabsq $68719476752, %rbx # imm = 0x1000000010
leaq 72(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
callq hipEventCreate
movl 20(%rsp), %r12d
leal 15(%r12), %eax
addl $30, %r12d
testl %eax, %eax
cmovnsl %eax, %r12d
movl %r12d, %r14d
sarl $4, %r14d
movl 12(%rsp), %r13d
leal 15(%r13), %eax
addl $30, %r13d
testl %eax, %eax
cmovnsl %eax, %r13d
movl %r13d, %r15d
sarl $4, %r15d
movl $.Lstr.9, %edi
callq puts@PLT
movl 20(%rsp), %esi
movl 12(%rsp), %edx
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl $.L.str.12, %edi
movl %r14d, %esi
movl %r15d, %edx
xorl %eax, %eax
callq printf
movl $.L.str.13, %edi
movl $16, %esi
movl $16, %edx
xorl %eax, %eax
callq printf
andl $-16, %r12d
andl $-16, %r13d
movl $.L.str.14, %edi
movl %r12d, %esi
movl %r13d, %edx
xorl %eax, %eax
callq printf
movl $.Lstr.10, %edi
callq puts@PLT
movl $.Lstr.11, %edi
callq puts@PLT
movq stdin(%rip), %rdi
callq getc
movq stdin(%rip), %rdi
callq getc
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movslq 20(%rsp), %rax
movslq 16(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 64(%rsp), %rdi
callq hipMalloc
movslq 16(%rsp), %rax
movslq 12(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 56(%rsp), %rdi
callq hipMalloc
movslq 20(%rsp), %rax
movslq 12(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 48(%rsp), %rdi
callq hipMalloc
movq 64(%rsp), %rdi
movslq 20(%rsp), %rax
movslq 16(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %rdi, %rsi
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movslq 16(%rsp), %rax
movslq 12(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %rdi, %rsi
movl $1, %ecx
callq hipMemcpy
shlq $32, %r14
orq %r15, %r14
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_13
# %bb.12:
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movl 20(%rsp), %esi
movl 16(%rsp), %edi
movl 12(%rsp), %r8d
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movl %esi, 36(%rsp)
movl %edi, 32(%rsp)
movl %r8d, 28(%rsp)
leaq 144(%rsp), %rax
movq %rax, 160(%rsp)
leaq 136(%rsp), %rax
movq %rax, 168(%rsp)
leaq 128(%rsp), %rax
movq %rax, 176(%rsp)
leaq 36(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 28(%rsp), %rax
movq %rax, 200(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z19gpu_matrix_mult_onePiS_S_iii, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_13:
movq 152(%rsp), %rdi
movq 48(%rsp), %rsi
movslq 20(%rsp), %rax
movslq 12(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
callq hipEventSynchronize
movq 72(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 24(%rsp), %rdi
callq hipEventElapsedTime
movl 20(%rsp), %esi
movl 16(%rsp), %ecx
movl 12(%rsp), %r8d
movss 24(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.16, %edi
movl %ecx, %edx
movb $1, %al
callq printf
movl $.Lstr.12, %edi
callq puts@PLT
movq stdin(%rip), %rdi
callq getc
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 64(%rsp), %rdi
movslq 20(%rsp), %rax
movslq 16(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %rdi, %rsi
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movslq 16(%rsp), %rax
movslq 12(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %rdi, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_15
# %bb.14:
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movl 20(%rsp), %esi
movl 16(%rsp), %edi
movl 12(%rsp), %r8d
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movl %esi, 36(%rsp)
movl %edi, 32(%rsp)
movl %r8d, 28(%rsp)
leaq 144(%rsp), %rax
movq %rax, 160(%rsp)
leaq 136(%rsp), %rax
movq %rax, 168(%rsp)
leaq 128(%rsp), %rax
movq %rax, 176(%rsp)
leaq 36(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 28(%rsp), %rax
movq %rax, 200(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z19gpu_matrix_mult_twoPiS_S_iii, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_15:
movq 152(%rsp), %rdi
movq 48(%rsp), %rsi
movslq 20(%rsp), %rax
movslq 12(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
callq hipEventSynchronize
movq 72(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 24(%rsp), %rdi
callq hipEventElapsedTime
movl 20(%rsp), %esi
movl 16(%rsp), %ecx
movl 12(%rsp), %r8d
movss 24(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.18, %edi
movl %ecx, %edx
movb $1, %al
callq printf
xorl %eax, %eax
addq $240, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19gpu_matrix_mult_onePiS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19gpu_matrix_mult_twoPiS_S_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19gpu_matrix_mult_onePiS_S_iii,@object # @_Z19gpu_matrix_mult_onePiS_S_iii
.section .rodata,"a",@progbits
.globl _Z19gpu_matrix_mult_onePiS_S_iii
.p2align 3, 0x0
_Z19gpu_matrix_mult_onePiS_S_iii:
.quad _Z34__device_stub__gpu_matrix_mult_onePiS_S_iii
.size _Z19gpu_matrix_mult_onePiS_S_iii, 8
.type _Z19gpu_matrix_mult_twoPiS_S_iii,@object # @_Z19gpu_matrix_mult_twoPiS_S_iii
.globl _Z19gpu_matrix_mult_twoPiS_S_iii
.p2align 3, 0x0
_Z19gpu_matrix_mult_twoPiS_S_iii:
.quad _Z34__device_stub__gpu_matrix_mult_twoPiS_S_iii
.size _Z19gpu_matrix_mult_twoPiS_S_iii, 8
.type .L.str.7,@object # @.str.7
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.7:
.asciz "%d"
.size .L.str.7, 3
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "The resulting matrix will be of size %d x %d\n"
.size .L.str.11, 46
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "\nI am launching a grid size of %d x %d blocks\n"
.size .L.str.12, 47
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Each block will be %d x %d threads\n"
.size .L.str.13, 36
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "This will give you %d x %d available threads\n"
.size .L.str.14, 46
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Time elapsed on matrix multiplication of %dx%d * %dx%d on GPU WITHOUT tiling: %f ms.\n\n"
.size .L.str.16, 87
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "Time elapsed on matrix multiplication of %dx%d * %dx%d on GPU WITH tiling: %f ms.\n\n"
.size .L.str.18, 84
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19gpu_matrix_mult_onePiS_S_iii"
.size .L__unnamed_1, 33
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z19gpu_matrix_mult_twoPiS_S_iii"
.size .L__unnamed_2, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "We will be multiplying two matrices"
.size .Lstr.1, 36
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "The first will be of size m x n"
.size .Lstr.2, 32
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "The second will be of size n x k"
.size .Lstr.3, 33
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "I will have you choose these dimensions!"
.size .Lstr.4, 41
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "Input m:"
.size .Lstr.6, 9
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "\nInput n:"
.size .Lstr.7, 10
.type .Lstr.8,@object # @str.8
.Lstr.8:
.asciz "\nInput k:"
.size .Lstr.8, 10
.type .Lstr.9,@object # @str.9
.Lstr.9:
.asciz "---------------------------------------------"
.size .Lstr.9, 46
.type .Lstr.10,@object # @str.10
.Lstr.10:
.asciz "---------------------------------------------\n"
.size .Lstr.10, 47
.type .Lstr.11,@object # @str.11
.Lstr.11:
.asciz "Press ENTER to begin computation on GPU (w/o tiling)..."
.size .Lstr.11, 56
.type .Lstr.12,@object # @str.12
.Lstr.12:
.asciz "Press ENTER to begin computation on GPU (w/tiling)..."
.size .Lstr.12, 54
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__gpu_matrix_mult_onePiS_S_iii
.addrsig_sym _Z34__device_stub__gpu_matrix_mult_twoPiS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19gpu_matrix_mult_onePiS_S_iii
.addrsig_sym _Z19gpu_matrix_mult_twoPiS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00187ba3_00000000-6_mat_mult_tile.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z19gpu_matrix_mult_onePiS_S_iiiPiS_S_iii
.type _Z46__device_stub__Z19gpu_matrix_mult_onePiS_S_iiiPiS_S_iii, @function
_Z46__device_stub__Z19gpu_matrix_mult_onePiS_S_iiiPiS_S_iii:
.LFB2082:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19gpu_matrix_mult_onePiS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z46__device_stub__Z19gpu_matrix_mult_onePiS_S_iiiPiS_S_iii, .-_Z46__device_stub__Z19gpu_matrix_mult_onePiS_S_iiiPiS_S_iii
.globl _Z19gpu_matrix_mult_onePiS_S_iii
.type _Z19gpu_matrix_mult_onePiS_S_iii, @function
_Z19gpu_matrix_mult_onePiS_S_iii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z19gpu_matrix_mult_onePiS_S_iiiPiS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z19gpu_matrix_mult_onePiS_S_iii, .-_Z19gpu_matrix_mult_onePiS_S_iii
.globl _Z46__device_stub__Z19gpu_matrix_mult_twoPiS_S_iiiPiS_S_iii
.type _Z46__device_stub__Z19gpu_matrix_mult_twoPiS_S_iiiPiS_S_iii, @function
_Z46__device_stub__Z19gpu_matrix_mult_twoPiS_S_iiiPiS_S_iii:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19gpu_matrix_mult_twoPiS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z46__device_stub__Z19gpu_matrix_mult_twoPiS_S_iiiPiS_S_iii, .-_Z46__device_stub__Z19gpu_matrix_mult_twoPiS_S_iiiPiS_S_iii
.globl _Z19gpu_matrix_mult_twoPiS_S_iii
.type _Z19gpu_matrix_mult_twoPiS_S_iii, @function
_Z19gpu_matrix_mult_twoPiS_S_iii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z19gpu_matrix_mult_twoPiS_S_iiiPiS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z19gpu_matrix_mult_twoPiS_S_iii, .-_Z19gpu_matrix_mult_twoPiS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "---------------------------------------------\n"
.align 8
.LC1:
.string "We will be multiplying two matrices\n"
.align 8
.LC2:
.string "The first will be of size m x n\n"
.align 8
.LC3:
.string "The second will be of size n x k\n"
.align 8
.LC4:
.string "I will have you choose these dimensions!\n"
.align 8
.LC5:
.string "---------------------------------------------\n\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "Input m:\n"
.LC7:
.string "%d"
.LC8:
.string "\nInput n:\n"
.LC9:
.string "\nInput k:\n"
.LC10:
.string "\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "The resulting matrix will be of size %d x %d\n"
.align 8
.LC12:
.string "\nI am launching a grid size of %d x %d blocks\n"
.align 8
.LC13:
.string "Each block will be %d x %d threads\n"
.align 8
.LC14:
.string "This will give you %d x %d available threads\n"
.align 8
.LC15:
.string "Press ENTER to begin computation on GPU (w/o tiling)...\n"
.align 8
.LC16:
.string "Time elapsed on matrix multiplication of %dx%d * %dx%d on GPU WITHOUT tiling: %f ms.\n\n"
.align 8
.LC17:
.string "Press ENTER to begin computation on GPU (w/tiling)...\n"
.align 8
.LC18:
.string "Time elapsed on matrix multiplication of %dx%d * %dx%d on GPU WITH tiling: %f ms.\n\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $136, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rsi
leaq .LC7(%rip), %rbx
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 12(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq 8(%rsp), %rsi
movslq 12(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMallocHost@PLT
movslq 12(%rsp), %rsi
movslq 16(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 32(%rsp), %rdi
call cudaMallocHost@PLT
movslq 8(%rsp), %rsi
movslq 16(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 48(%rsp), %rdi
call cudaMallocHost@PLT
movslq 8(%rsp), %rsi
movslq 16(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 40(%rsp), %rdi
call cudaMallocHost@PLT
movl $0, %ebp
cmpl $0, 8(%rsp)
jg .L20
.L21:
movl $0, %ebp
cmpl $0, 12(%rsp)
jg .L24
.L25:
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movl 8(%rsp), %eax
leal 30(%rax), %ebx
addl $15, %eax
cmovns %eax, %ebx
sarl $4, %ebx
movl 16(%rsp), %eax
leal 30(%rax), %ebp
addl $15, %eax
cmovns %eax, %ebp
sarl $4, %ebp
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 16(%rsp), %ecx
movl 8(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %ecx
movl %ebx, %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, %ecx
movl $16, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %ecx
sall $4, %ecx
movl %ebx, %edx
sall $4, %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
movq stdin(%rip), %rdi
call getc@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movslq 8(%rsp), %rsi
movslq 12(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 72(%rsp), %rdi
call cudaMalloc@PLT
movslq 12(%rsp), %rsi
movslq 16(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 80(%rsp), %rdi
call cudaMalloc@PLT
movslq 8(%rsp), %rsi
movslq 16(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 88(%rsp), %rdi
call cudaMalloc@PLT
movq 72(%rsp), %rdi
movslq 8(%rsp), %rdx
movslq 12(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rdi, %rsi
call cudaMemcpy@PLT
movq 80(%rsp), %rdi
movslq 12(%rsp), %rdx
movslq 16(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rdi, %rsi
call cudaMemcpy@PLT
movl %ebp, 96(%rsp)
movl %ebx, 100(%rsp)
movl $1, 104(%rsp)
movl $16, 108(%rsp)
movl $16, 112(%rsp)
movl $1, 116(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L28:
movslq 8(%rsp), %rdx
movslq 16(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 88(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
call cudaThreadSynchronize@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl 12(%rsp), %ecx
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
movl 16(%rsp), %r9d
movl %ecx, %r8d
movl 8(%rsp), %edx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 72(%rsp), %rdi
movslq 8(%rsp), %rdx
movslq 12(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rdi, %rsi
call cudaMemcpy@PLT
movq 80(%rsp), %rdi
movslq 12(%rsp), %rdx
movslq 16(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rdi, %rsi
call cudaMemcpy@PLT
movl 116(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movq 96(%rsp), %rdi
movl 104(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L29:
movslq 8(%rsp), %rdx
movslq 16(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 88(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
call cudaThreadSynchronize@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl 12(%rsp), %ecx
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
movl 16(%rsp), %r9d
movl %ecx, %r8d
movl 8(%rsp), %edx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L44
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call rand@PLT
movl %ebp, %edx
imull 12(%rsp), %edx
addl %ebx, %edx
movslq %edx, %rdx
movl %eax, %ecx
sarl $31, %ecx
shrl $22, %ecx
addl %ecx, %eax
andl $1023, %eax
subl %ecx, %eax
movq 24(%rsp), %rcx
movl %eax, (%rcx,%rdx,4)
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L22
.L23:
addl $1, %ebp
cmpl %ebp, 8(%rsp)
jle .L21
.L20:
movl $0, %ebx
cmpl $0, 12(%rsp)
jg .L22
jmp .L23
.L26:
call rand@PLT
movl 12(%rsp), %edx
imull 16(%rsp), %edx
addl %ebx, %edx
movslq %edx, %rdx
movl %eax, %ecx
sarl $31, %ecx
shrl $22, %ecx
addl %ecx, %eax
andl $1023, %eax
subl %ecx, %eax
movq 32(%rsp), %rcx
movl %eax, (%rcx,%rdx,4)
addl $1, %ebx
cmpl %ebx, 16(%rsp)
jg .L26
.L27:
addl $1, %ebp
cmpl %ebp, 12(%rsp)
jle .L25
.L24:
movl $0, %ebx
cmpl $0, 16(%rsp)
jg .L26
jmp .L27
.L42:
movl 16(%rsp), %r9d
movl 12(%rsp), %r8d
movl 8(%rsp), %ecx
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z46__device_stub__Z19gpu_matrix_mult_onePiS_S_iiiPiS_S_iii
jmp .L28
.L43:
movl 16(%rsp), %r9d
movl 12(%rsp), %r8d
movl 8(%rsp), %ecx
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z46__device_stub__Z19gpu_matrix_mult_twoPiS_S_iiiPiS_S_iii
jmp .L29
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC19:
.string "_Z19gpu_matrix_mult_twoPiS_S_iii"
.align 8
.LC20:
.string "_Z19gpu_matrix_mult_onePiS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z19gpu_matrix_mult_twoPiS_S_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z19gpu_matrix_mult_onePiS_S_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mat_mult_tile.hip"
.globl _Z34__device_stub__gpu_matrix_mult_onePiS_S_iii # -- Begin function _Z34__device_stub__gpu_matrix_mult_onePiS_S_iii
.p2align 4, 0x90
.type _Z34__device_stub__gpu_matrix_mult_onePiS_S_iii,@function
_Z34__device_stub__gpu_matrix_mult_onePiS_S_iii: # @_Z34__device_stub__gpu_matrix_mult_onePiS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19gpu_matrix_mult_onePiS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z34__device_stub__gpu_matrix_mult_onePiS_S_iii, .Lfunc_end0-_Z34__device_stub__gpu_matrix_mult_onePiS_S_iii
.cfi_endproc
# -- End function
.globl _Z34__device_stub__gpu_matrix_mult_twoPiS_S_iii # -- Begin function _Z34__device_stub__gpu_matrix_mult_twoPiS_S_iii
.p2align 4, 0x90
.type _Z34__device_stub__gpu_matrix_mult_twoPiS_S_iii,@function
_Z34__device_stub__gpu_matrix_mult_twoPiS_S_iii: # @_Z34__device_stub__gpu_matrix_mult_twoPiS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19gpu_matrix_mult_twoPiS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z34__device_stub__gpu_matrix_mult_twoPiS_S_iii, .Lfunc_end1-_Z34__device_stub__gpu_matrix_mult_twoPiS_S_iii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $240, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.Lstr.9, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
movl $.Lstr.4, %edi
callq puts@PLT
movl $.Lstr.10, %edi
callq puts@PLT
movl $.Lstr.6, %edi
callq puts@PLT
xorl %ebx, %ebx
leaq 20(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.Lstr.7, %edi
callq puts@PLT
leaq 16(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.Lstr.8, %edi
callq puts@PLT
leaq 12(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $10, %edi
callq putchar@PLT
movslq 20(%rsp), %rax
movslq 16(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 224(%rsp), %rdi
xorl %edx, %edx
callq hipHostMalloc
movslq 16(%rsp), %rax
movslq 12(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 216(%rsp), %rdi
xorl %edx, %edx
callq hipHostMalloc
movslq 20(%rsp), %rax
movslq 12(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 152(%rsp), %rdi
xorl %edx, %edx
callq hipHostMalloc
movslq 20(%rsp), %rax
movslq 12(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 232(%rsp), %rdi
xorl %edx, %edx
callq hipHostMalloc
cmpl $0, 20(%rsp)
jg .LBB2_1
.LBB2_5: # %.preheader60
cmpl $0, 16(%rsp)
jle .LBB2_11
# %bb.6: # %.preheader.preheader
xorl %ebx, %ebx
jmp .LBB2_7
.p2align 4, 0x90
.LBB2_4: # %._crit_edge
# in Loop: Header=BB2_1 Depth=1
incl %ebx
cmpl 20(%rsp), %ebx
jge .LBB2_5
.LBB2_1: # %.preheader61
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
cmpl $0, 16(%rsp)
jle .LBB2_4
# %bb.2: # %.lr.ph.preheader
# in Loop: Header=BB2_1 Depth=1
movslq %ebx, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph
# Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
# kill: def $eax killed $eax def $rax
leal 1023(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-1024, %ecx # imm = 0xFC00
subl %ecx, %eax
movq 224(%rsp), %rcx
movslq 16(%rsp), %rdx
imulq %r14, %rdx
addq %r15, %rdx
movl %eax, (%rcx,%rdx,4)
incq %r15
cmpl 16(%rsp), %r15d
jl .LBB2_3
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_10: # %._crit_edge66
# in Loop: Header=BB2_7 Depth=1
incl %ebx
cmpl 16(%rsp), %ebx
jge .LBB2_11
.LBB2_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_9 Depth 2
cmpl $0, 12(%rsp)
jle .LBB2_10
# %bb.8: # %.lr.ph65.preheader
# in Loop: Header=BB2_7 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_9: # %.lr.ph65
# Parent Loop BB2_7 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
# kill: def $eax killed $eax def $rax
leal 1023(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-1024, %ecx # imm = 0xFC00
subl %ecx, %eax
movq 216(%rsp), %rcx
movslq 16(%rsp), %rdx
movslq 12(%rsp), %rsi
imulq %rdx, %rsi
addq %r14, %rsi
movl %eax, (%rcx,%rsi,4)
incq %r14
cmpl 12(%rsp), %r14d
jl .LBB2_9
jmp .LBB2_10
.LBB2_11: # %._crit_edge68
movabsq $68719476752, %rbx # imm = 0x1000000010
leaq 72(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
callq hipEventCreate
movl 20(%rsp), %r12d
leal 15(%r12), %eax
addl $30, %r12d
testl %eax, %eax
cmovnsl %eax, %r12d
movl %r12d, %r14d
sarl $4, %r14d
movl 12(%rsp), %r13d
leal 15(%r13), %eax
addl $30, %r13d
testl %eax, %eax
cmovnsl %eax, %r13d
movl %r13d, %r15d
sarl $4, %r15d
movl $.Lstr.9, %edi
callq puts@PLT
movl 20(%rsp), %esi
movl 12(%rsp), %edx
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl $.L.str.12, %edi
movl %r14d, %esi
movl %r15d, %edx
xorl %eax, %eax
callq printf
movl $.L.str.13, %edi
movl $16, %esi
movl $16, %edx
xorl %eax, %eax
callq printf
andl $-16, %r12d
andl $-16, %r13d
movl $.L.str.14, %edi
movl %r12d, %esi
movl %r13d, %edx
xorl %eax, %eax
callq printf
movl $.Lstr.10, %edi
callq puts@PLT
movl $.Lstr.11, %edi
callq puts@PLT
movq stdin(%rip), %rdi
callq getc
movq stdin(%rip), %rdi
callq getc
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movslq 20(%rsp), %rax
movslq 16(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 64(%rsp), %rdi
callq hipMalloc
movslq 16(%rsp), %rax
movslq 12(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 56(%rsp), %rdi
callq hipMalloc
movslq 20(%rsp), %rax
movslq 12(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 48(%rsp), %rdi
callq hipMalloc
movq 64(%rsp), %rdi
movslq 20(%rsp), %rax
movslq 16(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %rdi, %rsi
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movslq 16(%rsp), %rax
movslq 12(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %rdi, %rsi
movl $1, %ecx
callq hipMemcpy
shlq $32, %r14
orq %r15, %r14
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_13
# %bb.12:
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movl 20(%rsp), %esi
movl 16(%rsp), %edi
movl 12(%rsp), %r8d
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movl %esi, 36(%rsp)
movl %edi, 32(%rsp)
movl %r8d, 28(%rsp)
leaq 144(%rsp), %rax
movq %rax, 160(%rsp)
leaq 136(%rsp), %rax
movq %rax, 168(%rsp)
leaq 128(%rsp), %rax
movq %rax, 176(%rsp)
leaq 36(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 28(%rsp), %rax
movq %rax, 200(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z19gpu_matrix_mult_onePiS_S_iii, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_13:
movq 152(%rsp), %rdi
movq 48(%rsp), %rsi
movslq 20(%rsp), %rax
movslq 12(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
callq hipEventSynchronize
movq 72(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 24(%rsp), %rdi
callq hipEventElapsedTime
movl 20(%rsp), %esi
movl 16(%rsp), %ecx
movl 12(%rsp), %r8d
movss 24(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.16, %edi
movl %ecx, %edx
movb $1, %al
callq printf
movl $.Lstr.12, %edi
callq puts@PLT
movq stdin(%rip), %rdi
callq getc
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 64(%rsp), %rdi
movslq 20(%rsp), %rax
movslq 16(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %rdi, %rsi
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movslq 16(%rsp), %rax
movslq 12(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %rdi, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_15
# %bb.14:
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movl 20(%rsp), %esi
movl 16(%rsp), %edi
movl 12(%rsp), %r8d
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movl %esi, 36(%rsp)
movl %edi, 32(%rsp)
movl %r8d, 28(%rsp)
leaq 144(%rsp), %rax
movq %rax, 160(%rsp)
leaq 136(%rsp), %rax
movq %rax, 168(%rsp)
leaq 128(%rsp), %rax
movq %rax, 176(%rsp)
leaq 36(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 28(%rsp), %rax
movq %rax, 200(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z19gpu_matrix_mult_twoPiS_S_iii, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_15:
movq 152(%rsp), %rdi
movq 48(%rsp), %rsi
movslq 20(%rsp), %rax
movslq 12(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
callq hipEventSynchronize
movq 72(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 24(%rsp), %rdi
callq hipEventElapsedTime
movl 20(%rsp), %esi
movl 16(%rsp), %ecx
movl 12(%rsp), %r8d
movss 24(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.18, %edi
movl %ecx, %edx
movb $1, %al
callq printf
xorl %eax, %eax
addq $240, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19gpu_matrix_mult_onePiS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19gpu_matrix_mult_twoPiS_S_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19gpu_matrix_mult_onePiS_S_iii,@object # @_Z19gpu_matrix_mult_onePiS_S_iii
.section .rodata,"a",@progbits
.globl _Z19gpu_matrix_mult_onePiS_S_iii
.p2align 3, 0x0
_Z19gpu_matrix_mult_onePiS_S_iii:
.quad _Z34__device_stub__gpu_matrix_mult_onePiS_S_iii
.size _Z19gpu_matrix_mult_onePiS_S_iii, 8
.type _Z19gpu_matrix_mult_twoPiS_S_iii,@object # @_Z19gpu_matrix_mult_twoPiS_S_iii
.globl _Z19gpu_matrix_mult_twoPiS_S_iii
.p2align 3, 0x0
_Z19gpu_matrix_mult_twoPiS_S_iii:
.quad _Z34__device_stub__gpu_matrix_mult_twoPiS_S_iii
.size _Z19gpu_matrix_mult_twoPiS_S_iii, 8
.type .L.str.7,@object # @.str.7
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.7:
.asciz "%d"
.size .L.str.7, 3
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "The resulting matrix will be of size %d x %d\n"
.size .L.str.11, 46
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "\nI am launching a grid size of %d x %d blocks\n"
.size .L.str.12, 47
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Each block will be %d x %d threads\n"
.size .L.str.13, 36
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "This will give you %d x %d available threads\n"
.size .L.str.14, 46
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Time elapsed on matrix multiplication of %dx%d * %dx%d on GPU WITHOUT tiling: %f ms.\n\n"
.size .L.str.16, 87
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "Time elapsed on matrix multiplication of %dx%d * %dx%d on GPU WITH tiling: %f ms.\n\n"
.size .L.str.18, 84
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19gpu_matrix_mult_onePiS_S_iii"
.size .L__unnamed_1, 33
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z19gpu_matrix_mult_twoPiS_S_iii"
.size .L__unnamed_2, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "We will be multiplying two matrices"
.size .Lstr.1, 36
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "The first will be of size m x n"
.size .Lstr.2, 32
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "The second will be of size n x k"
.size .Lstr.3, 33
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "I will have you choose these dimensions!"
.size .Lstr.4, 41
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "Input m:"
.size .Lstr.6, 9
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "\nInput n:"
.size .Lstr.7, 10
.type .Lstr.8,@object # @str.8
.Lstr.8:
.asciz "\nInput k:"
.size .Lstr.8, 10
.type .Lstr.9,@object # @str.9
.Lstr.9:
.asciz "---------------------------------------------"
.size .Lstr.9, 46
.type .Lstr.10,@object # @str.10
.Lstr.10:
.asciz "---------------------------------------------\n"
.size .Lstr.10, 47
.type .Lstr.11,@object # @str.11
.Lstr.11:
.asciz "Press ENTER to begin computation on GPU (w/o tiling)..."
.size .Lstr.11, 56
.type .Lstr.12,@object # @str.12
.Lstr.12:
.asciz "Press ENTER to begin computation on GPU (w/tiling)..."
.size .Lstr.12, 54
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__gpu_matrix_mult_onePiS_S_iii
.addrsig_sym _Z34__device_stub__gpu_matrix_mult_twoPiS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19gpu_matrix_mult_onePiS_S_iii
.addrsig_sym _Z19gpu_matrix_mult_twoPiS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <cuda.h>
#include <time.h>
/*
* Monte Carlo Pi Estimation Algorithm in CUDA
*
* This Project uses Cuda and thread
* topology to estimate Pi.
*
* Author: Clayton Glenn
*/
#define MAX_THREAD 16
#define MIN_THREAD 8
#define MAX_N 20
#define MIN_N 8
#define BLOCK_SIZE 256
#define DEBUG 0
/** Kernel Function
* First finds the Thread ID within the block of GPU Threads
* and if the Thread is Correct, it Encrypts the corresponding
* Character in the String.
**/
__global__
void monte(int *flags, float *x_vals, float *y_vals, int t, int n) {
//Get Thread id
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// Loop N/Threads times plus one
for(int i = 0; i < (n/t + 1); i++){
// If looped id count is less than n, grab rand x
// and y and check within unit. Increment if so
if((i*t+tid) < n){
if((pow(x_vals[(i*t+tid)], 2) + pow(y_vals[(i*t+tid)],2)) <= 1) flags[(tid)]++;
}
}
}
/**
* Helper Function
* Prints an string to standard error showing help
* for valid arguments in the executable
**/
void printerror(){
fprintf(stderr, "Invalid Arguments\n");
fprintf(stderr, "Correct Form: ./monte [# threads] [# points]\n");
exit(0);
}
/**
* Main Program
* This Program is for Homework 6 to encrypt some text or show
* the encryption method of text that is 2 to the power of N
* characters long all initialized to zero.
**/
int main(int argc, char **argv) {
// Declare a buffer of max size to start
int N = MIN_THREAD;
int THREADS = MIN_THREAD;
int BLOCKS = 256;
// Check for immediate errors in args
if (argc < 3 || argc > 3) printerror();
// Get Thread Count Per Block
THREADS = strtol(argv[1], NULL, 10);
THREADS = ((int)pow(2, THREADS));
if(THREADS < BLOCKS) BLOCKS = 1;
else THREADS = THREADS / BLOCKS;
// Get N Coordinates
N = strtol(argv[2], NULL, 10);
N = (int)pow(2, N);
// Print N and Threads for distinguish
printf("(Threads: %d) (N: %d)\n", THREADS * BLOCKS, N);
//Set Array of Size Thread
int flags[BLOCKS*THREADS];
float randx[N];
float randy[N];
srand( time( NULL ) );
for(int i = 0; i < N; i++){
if(i < BLOCKS*THREADS)flags[i] = 0;
randx[i] = ( float )rand()/RAND_MAX;
randy[i] = ( float )rand()/RAND_MAX;
}
// Init all other variables
int *dev_flags;
float *dev_randx;
float *dev_randy;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float final_time = 0.0;
// Allocate memory in the GPU for the int array
cudaMalloc(&dev_randx, N*sizeof(float));
cudaMalloc(&dev_randy, N*sizeof(float));
cudaMalloc(&dev_flags, BLOCKS*THREADS*sizeof(int));
// Copy the Memory from the array to the array pointers
cudaMemcpy(dev_flags, flags, BLOCKS*THREADS*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_randx, randx, N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dev_randy, randy, N*sizeof(float), cudaMemcpyHostToDevice);
// Total Time Record
cudaEventRecord(start);
monte<<<BLOCKS, THREADS>>>(dev_flags, dev_randx, dev_randy, BLOCKS*THREADS, N);
cudaEventRecord(stop);
// Copy the results from GPU to the CPU
cudaMemcpy(flags, dev_flags, BLOCKS*THREADS*sizeof(int), cudaMemcpyDeviceToHost);
// Count total successes for each thread
int success = 0;
for(int i = 0; i < BLOCKS*THREADS; i++){
if(flags[i] > 0) success += flags[i];
}
// Print Successes, failures, and estimation
//printf("Success: %d\n", success);
//printf("Failure: %d\n", (N - success));
printf("Estimation of Pi: %1.6f\n", ((float)success/N)*4);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&final_time, start, stop);
printf("Time in Kernel: %1.10f\n\n", final_time/1000);
cudaFree(dev_flags);
cudaFree(dev_randx);
cudaFree(dev_randy);
} | code for sm_80
Function : _Z5montePiPfS0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R5, c[0x0][0x178] ; /* 0x00005e0000057a13 */
/* 0x000fe20000000000 */
/*0020*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ ULOP3.LUT UR4, UR5, UR4, URZ, 0x3c, !UPT ; /* 0x0000000405047292 */
/* 0x000fe2000f8e3c3f */
/*0040*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e2a0000209400 */
/*0050*/ ISETP.LE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fc6000bf23270 */
/*0060*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0070*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0080*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0090*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00a0*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x002fc800078e0a03 */
/*00b0*/ IMAD R7, R4, R5, RZ ; /* 0x0000000504077224 */
/* 0x000fe200078e02ff */
/*00c0*/ IABS R4, c[0x0][0x17c] ; /* 0x00005f0000047a13 */
/* 0x000fc60000000000 */
/*00d0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*00e0*/ IMAD.HI.U32 R2, R3, R4, RZ ; /* 0x0000000403027227 */
/* 0x000fe400078e00ff */
/*00f0*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0100*/ IMAD.MOV R0, RZ, RZ, -R2 ; /* 0x000000ffff007224 */
/* 0x000fc800078e0a02 */
/*0110*/ IMAD R0, R5, R0, R4 ; /* 0x0000000005007224 */
/* 0x000fca00078e0204 */
/*0120*/ ISETP.GT.U32.AND P2, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f44070 */
/*0130*/ @!P2 IMAD.IADD R0, R0, 0x1, -R5 ; /* 0x000000010000a824 */
/* 0x000fe200078e0a05 */
/*0140*/ @!P2 IADD3 R2, R2, 0x1, RZ ; /* 0x000000010202a810 */
/* 0x000fe40007ffe0ff */
/*0150*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f45270 */
/*0160*/ ISETP.GE.U32.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe40003f06070 */
/*0170*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e360000002500 */
/*0180*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fca0007ffe0ff */
/*0190*/ @!P1 IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff029224 */
/* 0x000fe200078e0a02 */
/*01a0*/ @!P2 LOP3.LUT R2, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff02aa12 */
/* 0x000fc800078e33ff */
/*01b0*/ ISETP.GE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f06270 */
/*01c0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fd800078e0203 */
/*01d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*01f0*/ UMOV UR4, 0xffffffff ; /* 0xffffffff00047882 */
/* 0x000fe40000000000 */
/*0200*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0210*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e0207 */
/*0220*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f06270 */
/*0230*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0240*/ BSSY B0, 0x720 ; /* 0x000004d000007945 */
/* 0x000fea0003800000 */
/*0250*/ ISETP.LE.AND P1, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fcc000bf23270 */
/*0260*/ @P0 BRA 0x710 ; /* 0x000004a000000947 */
/* 0x00ffea0003800000 */
/*0270*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fc800078e00ff */
/*0280*/ IMAD.WIDE R10, R0, R11, c[0x0][0x168] ; /* 0x00005a00000a7625 */
/* 0x000fcc00078e020b */
/*0290*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000ea2000c1e1900 */
/*02a0*/ BSSY B1, 0x330 ; /* 0x0000008000017945 */
/* 0x000fe20003800000 */
/*02b0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe20000011400 */
/*02c0*/ F2F.F64.F32 R8, R10 ; /* 0x0000000a00087310 */
/* 0x004e240000201800 */
/*02d0*/ DADD R4, -RZ, |R8| ; /* 0x00000000ff047229 */
/* 0x001e140000000508 */
/*02e0*/ IMAD.MOV.U32 R18, RZ, RZ, R4 ; /* 0x000000ffff127224 */
/* 0x001fe200078e0004 */
/*02f0*/ MOV R4, 0x320 ; /* 0x0000032000047802 */
/* 0x000fe20000000f00 */
/*0300*/ IMAD.MOV.U32 R15, RZ, RZ, R5 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0005 */
/*0310*/ CALL.REL.NOINC 0x750 ; /* 0x0000043000007944 */
/* 0x000fea0003c00000 */
/*0320*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0330*/ DADD R4, R8, 2 ; /* 0x4000000008047429 */
/* 0x000ee20000000000 */
/*0340*/ FSETP.NEU.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720b */
/* 0x000fe20003f0d000 */
/*0350*/ BSSY B1, 0x470 ; /* 0x0000011000017945 */
/* 0x000ff00003800000 */
/*0360*/ LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005047812 */
/* 0x008fe200078ec0ff */
/*0370*/ IMAD.MOV.U32 R5, RZ, RZ, R17 ; /* 0x000000ffff057224 */
/* 0x004fc600078e0011 */
/*0380*/ ISETP.NE.AND P2, PT, R4, 0x7ff00000, PT ; /* 0x7ff000000400780c */
/* 0x000fe20003f45270 */
/*0390*/ IMAD.MOV.U32 R4, RZ, RZ, R16 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0010 */
/*03a0*/ @!P0 CS2R R4, SRZ ; /* 0x0000000000048805 */
/* 0x000fd6000001ff00 */
/*03b0*/ @P2 BRA 0x460 ; /* 0x000000a000002947 */
/* 0x000fea0003800000 */
/*03c0*/ DSETP.GTU.AND P0, PT, |R8|, +INF , PT ; /* 0x7ff000000800742a */
/* 0x000e9c0003f0c200 */
/*03d0*/ @P0 BRA 0x450 ; /* 0x0000007000000947 */
/* 0x004fea0003800000 */
/*03e0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*03f0*/ LOP3.LUT R8, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09087812 */
/* 0x000fc800078ec0ff */
/*0400*/ ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; /* 0x7ff000000800780c */
/* 0x000fda0000705670 */
/*0410*/ @P0 BRA 0x460 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0420*/ IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff047424 */
/* 0x000fe400078e00ff */
/*0430*/ IMAD.MOV.U32 R5, RZ, RZ, 0x7ff00000 ; /* 0x7ff00000ff057424 */
/* 0x000fe200078e00ff */
/*0440*/ BRA 0x460 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0450*/ DADD R4, R8, 2 ; /* 0x4000000008047429 */
/* 0x0004cc0000000000 */
/*0460*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0470*/ LEA R12, P0, R0, c[0x0][0x170], 0x2 ; /* 0x00005c00000c7a11 */
/* 0x002fc800078010ff */
/*0480*/ LEA.HI.X R13, R0, c[0x0][0x174], R3, 0x2, P0 ; /* 0x00005d00000d7a11 */
/* 0x000fca00000f1403 */
/*0490*/ LDG.E R3, [R12.64] ; /* 0x000000060c037981 */
/* 0x000f22000c1e1900 */
/*04a0*/ FSETP.NEU.AND P0, PT, R10, 1, PT ; /* 0x3f8000000a00780b */
/* 0x000fe20003f0d000 */
/*04b0*/ BSSY B1, 0x540 ; /* 0x0000008000017945 */
/* 0x000fe60003800000 */
/*04c0*/ FSEL R10, R4, RZ, P0 ; /* 0x000000ff040a7208 */
/* 0x008fe40000000000 */
/*04d0*/ FSEL R11, R5, 1.875, P0 ; /* 0x3ff00000050b7808 */
/* 0x000fe40000000000 */
/*04e0*/ MOV R4, 0x530 ; /* 0x0000053000047802 */
/* 0x000fe20000000f00 */
/*04f0*/ F2F.F64.F32 R8, R3 ; /* 0x0000000300087310 */
/* 0x014e640000201800 */
/*0500*/ DADD R14, -RZ, |R8| ; /* 0x00000000ff0e7229 */
/* 0x003e140000000508 */
/*0510*/ IMAD.MOV.U32 R18, RZ, RZ, R14 ; /* 0x000000ffff127224 */
/* 0x001fe400078e000e */
/*0520*/ CALL.REL.NOINC 0x750 ; /* 0x0000022000007944 */
/* 0x000fea0003c00000 */
/*0530*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0540*/ DADD R4, R8, 2 ; /* 0x4000000008047429 */
/* 0x000ee20000000000 */
/*0550*/ FSETP.NEU.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720b */
/* 0x000fe20003f0d000 */
/*0560*/ BSSY B1, 0x680 ; /* 0x0000011000017945 */
/* 0x000ff00003800000 */
/*0570*/ LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005047812 */
/* 0x008fe200078ec0ff */
/*0580*/ IMAD.MOV.U32 R5, RZ, RZ, R17 ; /* 0x000000ffff057224 */
/* 0x004fc600078e0011 */
/*0590*/ ISETP.NE.AND P2, PT, R4, 0x7ff00000, PT ; /* 0x7ff000000400780c */
/* 0x000fe20003f45270 */
/*05a0*/ IMAD.MOV.U32 R4, RZ, RZ, R16 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0010 */
/*05b0*/ @!P0 CS2R R4, SRZ ; /* 0x0000000000048805 */
/* 0x000fd6000001ff00 */
/*05c0*/ @P2 BRA 0x670 ; /* 0x000000a000002947 */
/* 0x000fea0003800000 */
/*05d0*/ DSETP.GTU.AND P0, PT, |R8|, +INF , PT ; /* 0x7ff000000800742a */
/* 0x000e9c0003f0c200 */
/*05e0*/ @P0 BRA 0x660 ; /* 0x0000007000000947 */
/* 0x004fea0003800000 */
/*05f0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*0600*/ LOP3.LUT R8, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09087812 */
/* 0x000fc800078ec0ff */
/*0610*/ ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; /* 0x7ff000000800780c */
/* 0x000fda0000705670 */
/*0620*/ @P0 BRA 0x670 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0630*/ IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff047424 */
/* 0x000fe400078e00ff */
/*0640*/ IMAD.MOV.U32 R5, RZ, RZ, 0x7ff00000 ; /* 0x7ff00000ff057424 */
/* 0x000fe200078e00ff */
/*0650*/ BRA 0x670 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0660*/ DADD R4, R8, 2 ; /* 0x4000000008047429 */
/* 0x0004cc0000000000 */
/*0670*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0680*/ FSETP.NEU.AND P0, PT, R3, 1, PT ; /* 0x3f8000000300780b */
/* 0x000fc80003f0d000 */
/*0690*/ FSEL R4, R4, RZ, P0 ; /* 0x000000ff04047208 */
/* 0x008fe40000000000 */
/*06a0*/ FSEL R5, R5, 1.875, P0 ; /* 0x3ff0000005057808 */
/* 0x000fcc0000000000 */
/*06b0*/ DADD R10, R10, R4 ; /* 0x000000000a0a7229 */
/* 0x000ecc0000000004 */
/*06c0*/ DSETP.GTU.AND P0, PT, R10, 1, PT ; /* 0x3ff000000a00742a */
/* 0x008edc0003f0c000 */
/*06d0*/ @P0 BRA 0x710 ; /* 0x0000003000000947 */
/* 0x008fea0003800000 */
/*06e0*/ LDG.E R3, [R6.64] ; /* 0x0000000606037981 */
/* 0x000ee4000c1e1900 */
/*06f0*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x008fca0007ffe0ff */
/*0700*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x0007e4000c101906 */
/*0710*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0720*/ IADD3 R0, R0, c[0x0][0x178], RZ ; /* 0x00005e0000007a10 */
/* 0x000fe20007ffe0ff */
/*0730*/ @!P1 BRA 0x220 ; /* 0xfffffae000009947 */
/* 0x000fea000383ffff */
/*0740*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0750*/ SHF.R.U32.HI R5, RZ, 0x14, R15.reuse ; /* 0x00000014ff057819 */
/* 0x100fe2000001160f */
/*0760*/ IMAD.MOV.U32 R12, RZ, RZ, R18 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0012 */
/*0770*/ IMAD.MOV.U32 R13, RZ, RZ, R15 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e000f */
/*0780*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0790*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd800078e00ff */
/*07a0*/ @!P0 DMUL R26, R12, 1.80143985094819840000e+16 ; /* 0x435000000c1a8828 */
/* 0x0000640000000000 */
/*07b0*/ IMAD.MOV.U32 R12, RZ, RZ, R15 ; /* 0x000000ffff0c7224 */
/* 0x001fd000078e000f */
/*07c0*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, R27 ; /* 0x000000ffff0c8224 */
/* 0x002fe200078e001b */
/*07d0*/ @!P0 LEA.HI R5, R27, 0xffffffca, RZ, 0xc ; /* 0xffffffca1b058811 */
/* 0x000fe200078f60ff */
/*07e0*/ @!P0 IMAD.MOV.U32 R18, RZ, RZ, R26 ; /* 0x000000ffff128224 */
/* 0x000fc600078e001a */
/*07f0*/ LOP3.LUT R12, R12, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff0c0c7812 */
/* 0x000fc800078ec0ff */
/*0800*/ LOP3.LUT R19, R12, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff000000c137812 */
/* 0x000fc800078efcff */
/*0810*/ ISETP.GE.U32.AND P2, PT, R19, 0x3ff6a09f, PT ; /* 0x3ff6a09f1300780c */
/* 0x000fda0003f46070 */
/*0820*/ @P2 IADD3 R13, R19, -0x100000, RZ ; /* 0xfff00000130d2810 */
/* 0x000fca0007ffe0ff */
/*0830*/ @P2 IMAD.MOV.U32 R19, RZ, RZ, R13 ; /* 0x000000ffff132224 */
/* 0x000fcc00078e000d */
/*0840*/ DADD R20, R18, 1 ; /* 0x3ff0000012147429 */
/* 0x000e080000000000 */
/*0850*/ DADD R18, R18, -1 ; /* 0xbff0000012127429 */
/* 0x000fe40000000000 */
/*0860*/ MUFU.RCP64H R15, R21 ; /* 0x00000015000f7308 */
/* 0x001e240000001800 */
/*0870*/ DFMA R12, -R20, R14, 1 ; /* 0x3ff00000140c742b */
/* 0x001e0c000000010e */
/*0880*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*0890*/ DFMA R12, R14, R12, R14 ; /* 0x0000000c0e0c722b */
/* 0x001064000000000e */
/*08a0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x7d2cafe2 ; /* 0x7d2cafe2ff0e7424 */
/* 0x001fe400078e00ff */
/*08b0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3eb0f5ff ; /* 0x3eb0f5ffff0f7424 */
/* 0x000fe400078e00ff */
/*08c0*/ DMUL R16, R12, R18 ; /* 0x000000120c107228 */
/* 0x002e0c0000000000 */
/*08d0*/ DFMA R16, R12, R18, R16 ; /* 0x000000120c10722b */
/* 0x001e0c0000000010 */
/*08e0*/ DMUL R22, R16, R16 ; /* 0x0000001010167228 */
/* 0x001e080000000000 */
/*08f0*/ DMUL R24, R16, R16 ; /* 0x0000001010187228 */
/* 0x000fc80000000000 */
/*0900*/ DFMA R14, R22, R14, c[0x2][0x0] ; /* 0x00800000160e762b */
/* 0x001e0c000000000e */
/*0910*/ DFMA R20, R22, R14, c[0x2][0x8] ; /* 0x008002001614762b */
/* 0x001e08000000000e */
/*0920*/ DADD R14, R18, -R16 ; /* 0x00000000120e7229 */
/* 0x000e480000000810 */
/*0930*/ DFMA R20, R22, R20, c[0x2][0x10] ; /* 0x008004001614762b */
/* 0x001e080000000014 */
/*0940*/ DADD R14, R14, R14 ; /* 0x000000000e0e7229 */
/* 0x002e48000000000e */
/*0950*/ DFMA R20, R22, R20, c[0x2][0x18] ; /* 0x008006001614762b */
/* 0x001e080000000014 */
/*0960*/ DFMA R14, R18, -R16, R14 ; /* 0x80000010120e722b */
/* 0x002e48000000000e */
/*0970*/ DFMA R20, R22, R20, c[0x2][0x20] ; /* 0x008008001614762b */
/* 0x001e080000000014 */
/*0980*/ DMUL R14, R12, R14 ; /* 0x0000000e0c0e7228 */
/* 0x002fc80000000000 */
/*0990*/ DFMA R20, R22, R20, c[0x2][0x28] ; /* 0x00800a001614762b */
/* 0x001e0c0000000014 */
/*09a0*/ DFMA R18, R22, R20, c[0x2][0x30] ; /* 0x00800c001612762b */
/* 0x001e0c0000000014 */
/*09b0*/ DADD R12, -R18, c[0x2][0x30] ; /* 0x00800c00120c7629 */
/* 0x001e0c0000000100 */
/*09c0*/ DFMA R12, R22, R20, R12 ; /* 0x00000014160c722b */
/* 0x001064000000000c */
/*09d0*/ IADD3 R23, R15, 0x100000, RZ ; /* 0x001000000f177810 */
/* 0x001fe20007ffe0ff */
/*09e0*/ IMAD.MOV.U32 R22, RZ, RZ, R14 ; /* 0x000000ffff167224 */
/* 0x000fe200078e000e */
/*09f0*/ DFMA R20, R16, R16, -R24 ; /* 0x000000101014722b */
/* 0x000e080000000818 */
/*0a00*/ DADD R12, RZ, R12 ; /* 0x00000000ff0c7229 */
/* 0x002e48000000000c */
/*0a10*/ DFMA R22, R16, R22, R20 ; /* 0x000000161016722b */
/* 0x001fc80000000014 */
/*0a20*/ DMUL R20, R16, R24 ; /* 0x0000001810147228 */
/* 0x000e080000000000 */
/*0a30*/ DADD R12, R12, c[0x2][0x38] ; /* 0x00800e000c0c7629 */
/* 0x002fc80000000000 */
/*0a40*/ DFMA R26, R16, R24, -R20 ; /* 0x00000018101a722b */
/* 0x001e0c0000000814 */
/*0a50*/ DFMA R26, R14, R24, R26 ; /* 0x000000180e1a722b */
/* 0x001e08000000001a */
/*0a60*/ DADD R24, R18, R12 ; /* 0x0000000012187229 */
/* 0x000e48000000000c */
/*0a70*/ DFMA R22, R16, R22, R26 ; /* 0x000000161016722b */
/* 0x001fc8000000001a */
/*0a80*/ DADD R26, R18, -R24 ; /* 0x00000000121a7229 */
/* 0x002e080000000818 */
/*0a90*/ DMUL R18, R24, R20 ; /* 0x0000001418127228 */
/* 0x000e480000000000 */
/*0aa0*/ DADD R26, R12, R26 ; /* 0x000000000c1a7229 */
/* 0x001fc8000000001a */
/*0ab0*/ DFMA R12, R24, R20, -R18 ; /* 0x00000014180c722b */
/* 0x002e0c0000000812 */
/*0ac0*/ DFMA R12, R24, R22, R12 ; /* 0x00000016180c722b */
/* 0x001e0c000000000c */
/*0ad0*/ DFMA R26, R26, R20, R12 ; /* 0x000000141a1a722b */
/* 0x001e0c000000000c */
/*0ae0*/ DADD R20, R18, R26 ; /* 0x0000000012147229 */
/* 0x001e0c000000001a */
/*0af0*/ DADD R12, R16, R20 ; /* 0x00000000100c7229 */
/* 0x001e080000000014 */
/*0b00*/ DADD R18, R18, -R20 ; /* 0x0000000012127229 */
/* 0x000e480000000814 */
/*0b10*/ DADD R16, R16, -R12 ; /* 0x0000000010107229 */
/* 0x001e08000000080c */
/*0b20*/ DADD R18, R26, R18 ; /* 0x000000001a127229 */
/* 0x002fc80000000012 */
/*0b30*/ DADD R16, R20, R16 ; /* 0x0000000014107229 */
/* 0x0010640000000010 */
/*0b40*/ IADD3 R20, R5.reuse, -0x3ff, RZ ; /* 0xfffffc0105147810 */
/* 0x041fe40007ffe0ff */
/*0b50*/ @P2 IADD3 R20, R5, -0x3fe, RZ ; /* 0xfffffc0205142810 */
/* 0x000fe40007ffe0ff */
/*0b60*/ DADD R18, R18, R16 ; /* 0x0000000012127229 */
/* 0x0020640000000010 */
/*0b70*/ LOP3.LUT R16, R20, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000014107812 */
/* 0x001fe200078e3cff */
/*0b80*/ IMAD.MOV.U32 R17, RZ, RZ, 0x43300000 ; /* 0x43300000ff117424 */
/* 0x000fc600078e00ff */
/*0b90*/ DADD R20, R14, R18 ; /* 0x000000000e147229 */
/* 0x002e080000000012 */
/*0ba0*/ DADD R14, R16, c[0x2][0x40] ; /* 0x00801000100e7629 */
/* 0x000fc80000000000 */
/*0bb0*/ DADD R16, R12, R20 ; /* 0x000000000c107229 */
/* 0x001e0c0000000014 */
/*0bc0*/ DFMA R18, R14, c[0x2][0x48], R16 ; /* 0x008012000e127a2b */
/* 0x001e080000000010 */
/*0bd0*/ DADD R22, R12, -R16 ; /* 0x000000000c167229 */
/* 0x000e480000000810 */
/*0be0*/ DFMA R12, -R14, c[0x2][0x48], R18 ; /* 0x008012000e0c7a2b */
/* 0x001e080000000112 */
/*0bf0*/ DADD R22, R20, R22 ; /* 0x0000000014167229 */
/* 0x0023e40000000016 */
/*0c00*/ IMAD.MOV.U32 R20, RZ, RZ, 0x652b82fe ; /* 0x652b82feff147424 */
/* 0x002fe400078e00ff */
/*0c10*/ DADD R12, -R16, R12 ; /* 0x00000000100c7229 */
/* 0x001e22000000010c */
/*0c20*/ IMAD.MOV.U32 R21, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff157424 */
/* 0x000fca00078e00ff */
/*0c30*/ DADD R12, R22, -R12 ; /* 0x00000000160c7229 */
/* 0x001e0c000000080c */
/*0c40*/ DFMA R14, R14, c[0x2][0x50], R12 ; /* 0x008014000e0e7a2b */
/* 0x001e0c000000000c */
/*0c50*/ DADD R12, R18, R14 ; /* 0x00000000120c7229 */
/* 0x001e0c000000000e */
/*0c60*/ DADD R18, R18, -R12 ; /* 0x0000000012127229 */
/* 0x001e08000000080c */
/*0c70*/ DMUL R24, R12, 2 ; /* 0x400000000c187828 */
/* 0x000e480000000000 */
/*0c80*/ DADD R18, R14, R18 ; /* 0x000000000e127229 */
/* 0x001fc80000000012 */
/*0c90*/ DFMA R22, R12, 2, -R24 ; /* 0x400000000c16782b */
/* 0x002e0c0000000818 */
/*0ca0*/ DFMA R22, R18, 2, R22 ; /* 0x400000001216782b */
/* 0x0010640000000016 */
/*0cb0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff127424 */
/* 0x001fe400078e00ff */
/*0cc0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff137424 */
/* 0x000fe400078e00ff */
/*0cd0*/ DADD R12, R24, R22 ; /* 0x00000000180c7229 */
/* 0x002e0c0000000016 */
/*0ce0*/ DFMA R20, R12, R20, 6.75539944105574400000e+15 ; /* 0x433800000c14742b */
/* 0x001e080000000014 */
/*0cf0*/ FSETP.GEU.AND P0, PT, |R13|, 4.1917929649353027344, PT ; /* 0x4086232b0d00780b */
/* 0x000fe40003f0e200 */
/*0d00*/ DADD R14, R20, -6.75539944105574400000e+15 ; /* 0xc3380000140e7429 */
/* 0x001e0c0000000000 */
/*0d10*/ DFMA R16, R14, c[0x2][0x58], R12 ; /* 0x008016000e107a2b */
/* 0x001e0c000000000c */
/*0d20*/ DFMA R14, R14, c[0x2][0x60], R16 ; /* 0x008018000e0e7a2b */
/* 0x001e0c0000000010 */
/*0d30*/ DFMA R16, R14, R18, c[0x2][0x68] ; /* 0x00801a000e10762b */
/* 0x001e0c0000000012 */
/*0d40*/ DFMA R16, R14, R16, c[0x2][0x70] ; /* 0x00801c000e10762b */
/* 0x001e0c0000000010 */
/*0d50*/ DFMA R16, R14, R16, c[0x2][0x78] ; /* 0x00801e000e10762b */
/* 0x001e0c0000000010 */
/*0d60*/ DFMA R16, R14, R16, c[0x2][0x80] ; /* 0x008020000e10762b */
/* 0x001e0c0000000010 */
/*0d70*/ DFMA R16, R14, R16, c[0x2][0x88] ; /* 0x008022000e10762b */
/* 0x001e0c0000000010 */
/*0d80*/ DFMA R16, R14, R16, c[0x2][0x90] ; /* 0x008024000e10762b */
/* 0x001e0c0000000010 */
/*0d90*/ DFMA R16, R14, R16, c[0x2][0x98] ; /* 0x008026000e10762b */
/* 0x001e0c0000000010 */
/*0da0*/ DFMA R16, R14, R16, c[0x2][0xa0] ; /* 0x008028000e10762b */
/* 0x001e0c0000000010 */
/*0db0*/ DFMA R16, R14, R16, c[0x2][0xa8] ; /* 0x00802a000e10762b */
/* 0x001e0c0000000010 */
/*0dc0*/ DFMA R16, R14, R16, 1 ; /* 0x3ff000000e10742b */
/* 0x001e0c0000000010 */
/*0dd0*/ DFMA R14, R14, R16, 1 ; /* 0x3ff000000e0e742b */
/* 0x001e140000000010 */
/*0de0*/ IMAD R17, R20, 0x100000, R15 ; /* 0x0010000014117824 */
/* 0x001fe400078e020f */
/*0df0*/ IMAD.MOV.U32 R16, RZ, RZ, R14 ; /* 0x000000ffff107224 */
/* 0x000fe200078e000e */
/*0e00*/ @!P0 BRA 0xed0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0e10*/ FSETP.GEU.AND P2, PT, |R13|, 4.2275390625, PT ; /* 0x408748000d00780b */
/* 0x000fe20003f4e200 */
/*0e20*/ DADD R16, R12, +INF ; /* 0x7ff000000c107429 */
/* 0x000fc80000000000 */
/*0e30*/ DSETP.GEU.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00722a */
/* 0x000e0c0003f0e000 */
/*0e40*/ FSEL R16, R16, RZ, P0 ; /* 0x000000ff10107208 */
/* 0x001fe40000000000 */
/*0e50*/ @!P2 LEA.HI R5, R20, R20, RZ, 0x1 ; /* 0x000000141405a211 */
/* 0x000fe400078f08ff */
/*0e60*/ FSEL R17, R17, RZ, P0 ; /* 0x000000ff11117208 */
/* 0x000fe40000000000 */
/*0e70*/ @!P2 SHF.R.S32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff05a819 */
/* 0x000fca0000011405 */
/*0e80*/ @!P2 IMAD.IADD R20, R20, 0x1, -R5 ; /* 0x000000011414a824 */
/* 0x000fe400078e0a05 */
/*0e90*/ @!P2 IMAD R15, R5, 0x100000, R15 ; /* 0x00100000050fa824 */
/* 0x000fc600078e020f */
/*0ea0*/ @!P2 LEA R21, R20, 0x3ff00000, 0x14 ; /* 0x3ff000001415a811 */
/* 0x000fe200078ea0ff */
/*0eb0*/ @!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff14a224 */
/* 0x000fcc00078e00ff */
/*0ec0*/ @!P2 DMUL R16, R14, R20 ; /* 0x000000140e10a228 */
/* 0x0000540000000000 */
/*0ed0*/ LOP3.LUT R5, R17, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff11057812 */
/* 0x002fe200078ec0ff */
/*0ee0*/ DADD R12, R24, -R12 ; /* 0x00000000180c7229 */
/* 0x000e46000000080c */
/*0ef0*/ ISETP.NE.AND P0, PT, R5, 0x7ff00000, PT ; /* 0x7ff000000500780c */
/* 0x000fe20003f05270 */
/*0f00*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fe400078e00ff */
/*0f10*/ DADD R12, R22, R12 ; /* 0x00000000160c7229 */
/* 0x002e62000000000c */
/*0f20*/ ISETP.EQ.AND P0, PT, R16, RZ, !P0 ; /* 0x000000ff1000720c */
/* 0x000fda0004702270 */
/*0f30*/ @!P0 DFMA R16, R12, R16, R16 ; /* 0x000000100c10822b */
/* 0x0022a20000000010 */
/*0f40*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff0b004007950 */
/* 0x000ff40003c3ffff */
/*0f50*/ BRA 0xf50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <cuda.h>
#include <time.h>
/*
* Monte Carlo Pi Estimation Algorithm in CUDA
*
* This Project uses Cuda and thread
* topology to estimate Pi.
*
* Author: Clayton Glenn
*/
#define MAX_THREAD 16
#define MIN_THREAD 8
#define MAX_N 20
#define MIN_N 8
#define BLOCK_SIZE 256
#define DEBUG 0
/** Kernel Function
* First finds the Thread ID within the block of GPU Threads
* and if the Thread is Correct, it Encrypts the corresponding
* Character in the String.
**/
__global__
void monte(int *flags, float *x_vals, float *y_vals, int t, int n) {
//Get Thread id
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// Loop N/Threads times plus one
for(int i = 0; i < (n/t + 1); i++){
// If looped id count is less than n, grab rand x
// and y and check within unit. Increment if so
if((i*t+tid) < n){
if((pow(x_vals[(i*t+tid)], 2) + pow(y_vals[(i*t+tid)],2)) <= 1) flags[(tid)]++;
}
}
}
/**
* Helper Function
* Prints an string to standard error showing help
* for valid arguments in the executable
**/
void printerror(){
fprintf(stderr, "Invalid Arguments\n");
fprintf(stderr, "Correct Form: ./monte [# threads] [# points]\n");
exit(0);
}
/**
* Main Program
* This Program is for Homework 6 to encrypt some text or show
* the encryption method of text that is 2 to the power of N
* characters long all initialized to zero.
**/
int main(int argc, char **argv) {
// Declare a buffer of max size to start
int N = MIN_THREAD;
int THREADS = MIN_THREAD;
int BLOCKS = 256;
// Check for immediate errors in args
if (argc < 3 || argc > 3) printerror();
// Get Thread Count Per Block
THREADS = strtol(argv[1], NULL, 10);
THREADS = ((int)pow(2, THREADS));
if(THREADS < BLOCKS) BLOCKS = 1;
else THREADS = THREADS / BLOCKS;
// Get N Coordinates
N = strtol(argv[2], NULL, 10);
N = (int)pow(2, N);
// Print N and Threads for distinguish
printf("(Threads: %d) (N: %d)\n", THREADS * BLOCKS, N);
//Set Array of Size Thread
int flags[BLOCKS*THREADS];
float randx[N];
float randy[N];
srand( time( NULL ) );
for(int i = 0; i < N; i++){
if(i < BLOCKS*THREADS)flags[i] = 0;
randx[i] = ( float )rand()/RAND_MAX;
randy[i] = ( float )rand()/RAND_MAX;
}
// Init all other variables
int *dev_flags;
float *dev_randx;
float *dev_randy;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float final_time = 0.0;
// Allocate memory in the GPU for the int array
cudaMalloc(&dev_randx, N*sizeof(float));
cudaMalloc(&dev_randy, N*sizeof(float));
cudaMalloc(&dev_flags, BLOCKS*THREADS*sizeof(int));
// Copy the Memory from the array to the array pointers
cudaMemcpy(dev_flags, flags, BLOCKS*THREADS*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_randx, randx, N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dev_randy, randy, N*sizeof(float), cudaMemcpyHostToDevice);
// Total Time Record
cudaEventRecord(start);
monte<<<BLOCKS, THREADS>>>(dev_flags, dev_randx, dev_randy, BLOCKS*THREADS, N);
cudaEventRecord(stop);
// Copy the results from GPU to the CPU
cudaMemcpy(flags, dev_flags, BLOCKS*THREADS*sizeof(int), cudaMemcpyDeviceToHost);
// Count total successes for each thread
int success = 0;
for(int i = 0; i < BLOCKS*THREADS; i++){
if(flags[i] > 0) success += flags[i];
}
// Print Successes, failures, and estimation
//printf("Success: %d\n", success);
//printf("Failure: %d\n", (N - success));
printf("Estimation of Pi: %1.6f\n", ((float)success/N)*4);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&final_time, start, stop);
printf("Time in Kernel: %1.10f\n\n", final_time/1000);
cudaFree(dev_flags);
cudaFree(dev_randx);
cudaFree(dev_randy);
} | .file "tmpxft_00039477_00000000-6_Monte_CUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Invalid Arguments\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Correct Form: ./monte [# threads] [# points]\n"
.text
.globl _Z10printerrorv
.type _Z10printerrorv, @function
_Z10printerrorv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10printerrorv, .-_Z10printerrorv
.globl _Z31__device_stub__Z5montePiPfS0_iiPiPfS0_ii
.type _Z31__device_stub__Z5montePiPfS0_iiPiPfS0_ii, @function
_Z31__device_stub__Z5montePiPfS0_iiPiPfS0_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5montePiPfS0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z31__device_stub__Z5montePiPfS0_iiPiPfS0_ii, .-_Z31__device_stub__Z5montePiPfS0_iiPiPfS0_ii
.globl _Z5montePiPfS0_ii
.type _Z5montePiPfS0_ii, @function
_Z5montePiPfS0_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z5montePiPfS0_iiPiPfS0_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z5montePiPfS0_ii, .-_Z5montePiPfS0_ii
.section .rodata.str1.1
.LC3:
.string "(Threads: %d) (N: %d)\n"
.LC7:
.string "Estimation of Pi: %1.6f\n"
.LC9:
.string "Time in Kernel: %1.10f\n\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $136, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
cmpl $3, %edi
jne .L39
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
movsd .LC2(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %eax
movl %eax, -140(%rbp)
movl $1, -144(%rbp)
cmpl $255, %eax
jle .L16
movl $256, %ecx
cltd
idivl %ecx
movl %eax, -140(%rbp)
movl $256, -144(%rbp)
.L16:
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
movsd .LC2(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %ecx
movl %ecx, -156(%rbp)
movl -140(%rbp), %r12d
movl -144(%rbp), %eax
imull %eax, %r12d
movl %r12d, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %r12d, %rax
salq $2, %rax
movq %rax, -152(%rbp)
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L17:
cmpq %rdx, %rsp
je .L18
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L17
.L39:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L40
call _Z10printerrorv
.L40:
call __stack_chk_fail@PLT
.L18:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L19
orq $0, -8(%rsp,%rax)
.L19:
movq %rsp, -136(%rbp)
movslq -156(%rbp), %r15
leaq 0(,%r15,4), %rax
movq %rax, -168(%rbp)
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L20:
cmpq %rdx, %rsp
je .L21
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L20
.L21:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L22
orq $0, -8(%rsp,%rax)
.L22:
movq %rsp, %r13
movq -168(%rbp), %rax
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L23:
cmpq %rdx, %rsp
je .L24
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L23
.L24:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L25
orq $0, -8(%rsp,%rax)
.L25:
movq %rsp, %r14
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
cmpl $0, -156(%rbp)
jle .L26
movl $0, %ebx
jmp .L28
.L27:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC4(%rip), %xmm0
movss %xmm0, 0(%r13,%rbx,4)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC4(%rip), %xmm0
movss %xmm0, (%r14,%rbx,4)
addq $1, %rbx
cmpq %rbx, %r15
je .L26
.L28:
cmpl %ebx, %r12d
jle .L27
movq -136(%rbp), %rax
movl $0, (%rax,%rbx,4)
jmp .L27
.L26:
leaq -96(%rbp), %rdi
call cudaEventCreate@PLT
leaq -88(%rbp), %rdi
call cudaEventCreate@PLT
movl $0x00000000, -124(%rbp)
leaq -112(%rbp), %rdi
movq -168(%rbp), %rbx
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -104(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -120(%rbp), %rdi
movq -152(%rbp), %r15
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq -136(%rbp), %rsi
movq -120(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq -112(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq -104(%rbp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq -96(%rbp), %rdi
call cudaEventRecord@PLT
movl -140(%rbp), %eax
movl %eax, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl -144(%rbp), %eax
movl %eax, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L29:
movl $0, %esi
movq -88(%rbp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq -152(%rbp), %r14
movq %r14, %rdx
movq -120(%rbp), %rsi
movq -136(%rbp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
testl %r12d, %r12d
jle .L35
movq %rbx, %rax
movq %rbx, %rsi
addq %r14, %rsi
movl $0, %edx
.L32:
movl (%rax), %ecx
leal (%rdx,%rcx), %edi
testl %ecx, %ecx
cmovg %edi, %edx
addq $4, %rax
cmpq %rsi, %rax
jne .L32
.L30:
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl -156(%rbp), %xmm1
divss %xmm1, %xmm0
mulss .LC6(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq -88(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -124(%rbp), %rdi
movq -88(%rbp), %rdx
movq -96(%rbp), %rsi
call cudaEventElapsedTime@PLT
movss -124(%rbp), %xmm0
divss .LC8(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq -120(%rbp), %rdi
call cudaFree@PLT
movq -112(%rbp), %rdi
call cudaFree@PLT
movq -104(%rbp), %rdi
call cudaFree@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L41:
.cfi_restore_state
movl -156(%rbp), %r8d
movl %r12d, %ecx
movq -104(%rbp), %rdx
movq -112(%rbp), %rsi
movq -120(%rbp), %rdi
call _Z31__device_stub__Z5montePiPfS0_iiPiPfS0_ii
jmp .L29
.L35:
movl $0, %edx
jmp .L30
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z5montePiPfS0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z5montePiPfS0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1073741824
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 805306368
.align 4
.LC6:
.long 1082130432
.align 4
.LC8:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <cuda.h>
#include <time.h>
/*
* Monte Carlo Pi Estimation Algorithm in CUDA
*
* This Project uses Cuda and thread
* topology to estimate Pi.
*
* Author: Clayton Glenn
*/
#define MAX_THREAD 16
#define MIN_THREAD 8
#define MAX_N 20
#define MIN_N 8
#define BLOCK_SIZE 256
#define DEBUG 0
/** Kernel Function
* First finds the Thread ID within the block of GPU Threads
* and if the Thread is Correct, it Encrypts the corresponding
* Character in the String.
**/
__global__
void monte(int *flags, float *x_vals, float *y_vals, int t, int n) {
//Get Thread id
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// Loop N/Threads times plus one
for(int i = 0; i < (n/t + 1); i++){
// If looped id count is less than n, grab rand x
// and y and check within unit. Increment if so
if((i*t+tid) < n){
if((pow(x_vals[(i*t+tid)], 2) + pow(y_vals[(i*t+tid)],2)) <= 1) flags[(tid)]++;
}
}
}
/**
* Helper Function
* Prints an string to standard error showing help
* for valid arguments in the executable
**/
void printerror(){
fprintf(stderr, "Invalid Arguments\n");
fprintf(stderr, "Correct Form: ./monte [# threads] [# points]\n");
exit(0);
}
/**
* Main Program
* This Program is for Homework 6 to encrypt some text or show
* the encryption method of text that is 2 to the power of N
* characters long all initialized to zero.
**/
int main(int argc, char **argv) {
// Declare a buffer of max size to start
int N = MIN_THREAD;
int THREADS = MIN_THREAD;
int BLOCKS = 256;
// Check for immediate errors in args
if (argc < 3 || argc > 3) printerror();
// Get Thread Count Per Block
THREADS = strtol(argv[1], NULL, 10);
THREADS = ((int)pow(2, THREADS));
if(THREADS < BLOCKS) BLOCKS = 1;
else THREADS = THREADS / BLOCKS;
// Get N Coordinates
N = strtol(argv[2], NULL, 10);
N = (int)pow(2, N);
// Print N and Threads for distinguish
printf("(Threads: %d) (N: %d)\n", THREADS * BLOCKS, N);
//Set Array of Size Thread
int flags[BLOCKS*THREADS];
float randx[N];
float randy[N];
srand( time( NULL ) );
for(int i = 0; i < N; i++){
if(i < BLOCKS*THREADS)flags[i] = 0;
randx[i] = ( float )rand()/RAND_MAX;
randy[i] = ( float )rand()/RAND_MAX;
}
// Init all other variables
int *dev_flags;
float *dev_randx;
float *dev_randy;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float final_time = 0.0;
// Allocate memory in the GPU for the int array
cudaMalloc(&dev_randx, N*sizeof(float));
cudaMalloc(&dev_randy, N*sizeof(float));
cudaMalloc(&dev_flags, BLOCKS*THREADS*sizeof(int));
// Copy the Memory from the array to the array pointers
cudaMemcpy(dev_flags, flags, BLOCKS*THREADS*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_randx, randx, N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dev_randy, randy, N*sizeof(float), cudaMemcpyHostToDevice);
// Total Time Record
cudaEventRecord(start);
monte<<<BLOCKS, THREADS>>>(dev_flags, dev_randx, dev_randy, BLOCKS*THREADS, N);
cudaEventRecord(stop);
// Copy the results from GPU to the CPU
cudaMemcpy(flags, dev_flags, BLOCKS*THREADS*sizeof(int), cudaMemcpyDeviceToHost);
// Count total successes for each thread
int success = 0;
for(int i = 0; i < BLOCKS*THREADS; i++){
if(flags[i] > 0) success += flags[i];
}
// Print Successes, failures, and estimation
//printf("Success: %d\n", success);
//printf("Failure: %d\n", (N - success));
printf("Estimation of Pi: %1.6f\n", ((float)success/N)*4);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&final_time, start, stop);
printf("Time in Kernel: %1.10f\n\n", final_time/1000);
cudaFree(dev_flags);
cudaFree(dev_randx);
cudaFree(dev_randy);
} | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <time.h>
/*
* Monte Carlo Pi Estimation Algorithm in CUDA
*
* This Project uses Cuda and thread
* topology to estimate Pi.
*
* Author: Clayton Glenn
*/
#define MAX_THREAD 16
#define MIN_THREAD 8
#define MAX_N 20
#define MIN_N 8
#define BLOCK_SIZE 256
#define DEBUG 0
/** Kernel Function
* First finds the Thread ID within the block of GPU Threads
* and if the Thread is Correct, it Encrypts the corresponding
* Character in the String.
**/
__global__
void monte(int *flags, float *x_vals, float *y_vals, int t, int n) {
//Get Thread id
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// Loop N/Threads times plus one
for(int i = 0; i < (n/t + 1); i++){
// If looped id count is less than n, grab rand x
// and y and check within unit. Increment if so
if((i*t+tid) < n){
if((pow(x_vals[(i*t+tid)], 2) + pow(y_vals[(i*t+tid)],2)) <= 1) flags[(tid)]++;
}
}
}
/**
* Helper Function
* Prints an string to standard error showing help
* for valid arguments in the executable
**/
void printerror(){
fprintf(stderr, "Invalid Arguments\n");
fprintf(stderr, "Correct Form: ./monte [# threads] [# points]\n");
exit(0);
}
/**
* Main Program
* This Program is for Homework 6 to encrypt some text or show
* the encryption method of text that is 2 to the power of N
* characters long all initialized to zero.
**/
int main(int argc, char **argv) {
// Declare a buffer of max size to start
int N = MIN_THREAD;
int THREADS = MIN_THREAD;
int BLOCKS = 256;
// Check for immediate errors in args
if (argc < 3 || argc > 3) printerror();
// Get Thread Count Per Block
THREADS = strtol(argv[1], NULL, 10);
THREADS = ((int)pow(2, THREADS));
if(THREADS < BLOCKS) BLOCKS = 1;
else THREADS = THREADS / BLOCKS;
// Get N Coordinates
N = strtol(argv[2], NULL, 10);
N = (int)pow(2, N);
// Print N and Threads for distinguish
printf("(Threads: %d) (N: %d)\n", THREADS * BLOCKS, N);
//Set Array of Size Thread
int flags[BLOCKS*THREADS];
float randx[N];
float randy[N];
srand( time( NULL ) );
for(int i = 0; i < N; i++){
if(i < BLOCKS*THREADS)flags[i] = 0;
randx[i] = ( float )rand()/RAND_MAX;
randy[i] = ( float )rand()/RAND_MAX;
}
// Init all other variables
int *dev_flags;
float *dev_randx;
float *dev_randy;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float final_time = 0.0;
// Allocate memory in the GPU for the int array
hipMalloc(&dev_randx, N*sizeof(float));
hipMalloc(&dev_randy, N*sizeof(float));
hipMalloc(&dev_flags, BLOCKS*THREADS*sizeof(int));
// Copy the Memory from the array to the array pointers
hipMemcpy(dev_flags, flags, BLOCKS*THREADS*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_randx, randx, N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_randy, randy, N*sizeof(float), hipMemcpyHostToDevice);
// Total Time Record
hipEventRecord(start);
monte<<<BLOCKS, THREADS>>>(dev_flags, dev_randx, dev_randy, BLOCKS*THREADS, N);
hipEventRecord(stop);
// Copy the results from GPU to the CPU
hipMemcpy(flags, dev_flags, BLOCKS*THREADS*sizeof(int), hipMemcpyDeviceToHost);
// Count total successes for each thread
int success = 0;
for(int i = 0; i < BLOCKS*THREADS; i++){
if(flags[i] > 0) success += flags[i];
}
// Print Successes, failures, and estimation
//printf("Success: %d\n", success);
//printf("Failure: %d\n", (N - success));
printf("Estimation of Pi: %1.6f\n", ((float)success/N)*4);
hipEventSynchronize(stop);
hipEventElapsedTime(&final_time, start, stop);
printf("Time in Kernel: %1.10f\n\n", final_time/1000);
hipFree(dev_flags);
hipFree(dev_randx);
hipFree(dev_randy);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <time.h>
/*
* Monte Carlo Pi Estimation Algorithm in CUDA
*
* This Project uses Cuda and thread
* topology to estimate Pi.
*
* Author: Clayton Glenn
*/
#define MAX_THREAD 16
#define MIN_THREAD 8
#define MAX_N 20
#define MIN_N 8
#define BLOCK_SIZE 256
#define DEBUG 0
/** Kernel Function
* First finds the Thread ID within the block of GPU Threads
* and if the Thread is Correct, it Encrypts the corresponding
* Character in the String.
**/
__global__
void monte(int *flags, float *x_vals, float *y_vals, int t, int n) {
//Get Thread id
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// Loop N/Threads times plus one
for(int i = 0; i < (n/t + 1); i++){
// If looped id count is less than n, grab rand x
// and y and check within unit. Increment if so
if((i*t+tid) < n){
if((pow(x_vals[(i*t+tid)], 2) + pow(y_vals[(i*t+tid)],2)) <= 1) flags[(tid)]++;
}
}
}
/**
* Helper Function
* Prints an string to standard error showing help
* for valid arguments in the executable
**/
void printerror(){
fprintf(stderr, "Invalid Arguments\n");
fprintf(stderr, "Correct Form: ./monte [# threads] [# points]\n");
exit(0);
}
/**
* Main Program
* This Program is for Homework 6 to encrypt some text or show
* the encryption method of text that is 2 to the power of N
* characters long all initialized to zero.
**/
int main(int argc, char **argv) {
// Declare a buffer of max size to start
int N = MIN_THREAD;
int THREADS = MIN_THREAD;
int BLOCKS = 256;
// Check for immediate errors in args
if (argc < 3 || argc > 3) printerror();
// Get Thread Count Per Block
THREADS = strtol(argv[1], NULL, 10);
THREADS = ((int)pow(2, THREADS));
if(THREADS < BLOCKS) BLOCKS = 1;
else THREADS = THREADS / BLOCKS;
// Get N Coordinates
N = strtol(argv[2], NULL, 10);
N = (int)pow(2, N);
// Print N and Threads for distinguish
printf("(Threads: %d) (N: %d)\n", THREADS * BLOCKS, N);
//Set Array of Size Thread
int flags[BLOCKS*THREADS];
float randx[N];
float randy[N];
srand( time( NULL ) );
for(int i = 0; i < N; i++){
if(i < BLOCKS*THREADS)flags[i] = 0;
randx[i] = ( float )rand()/RAND_MAX;
randy[i] = ( float )rand()/RAND_MAX;
}
// Init all other variables
int *dev_flags;
float *dev_randx;
float *dev_randy;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float final_time = 0.0;
// Allocate memory in the GPU for the int array
hipMalloc(&dev_randx, N*sizeof(float));
hipMalloc(&dev_randy, N*sizeof(float));
hipMalloc(&dev_flags, BLOCKS*THREADS*sizeof(int));
// Copy the Memory from the array to the array pointers
hipMemcpy(dev_flags, flags, BLOCKS*THREADS*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_randx, randx, N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_randy, randy, N*sizeof(float), hipMemcpyHostToDevice);
// Total Time Record
hipEventRecord(start);
monte<<<BLOCKS, THREADS>>>(dev_flags, dev_randx, dev_randy, BLOCKS*THREADS, N);
hipEventRecord(stop);
// Copy the results from GPU to the CPU
hipMemcpy(flags, dev_flags, BLOCKS*THREADS*sizeof(int), hipMemcpyDeviceToHost);
// Count total successes for each thread
int success = 0;
for(int i = 0; i < BLOCKS*THREADS; i++){
if(flags[i] > 0) success += flags[i];
}
// Print Successes, failures, and estimation
//printf("Success: %d\n", success);
//printf("Failure: %d\n", (N - success));
printf("Estimation of Pi: %1.6f\n", ((float)success/N)*4);
hipEventSynchronize(stop);
hipEventElapsedTime(&final_time, start, stop);
printf("Time in Kernel: %1.10f\n\n", final_time/1000);
hipFree(dev_flags);
hipFree(dev_randx);
hipFree(dev_randy);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5montePiPfS0_ii
.globl _Z5montePiPfS0_ii
.p2align 8
.type _Z5montePiPfS0_ii,@function
_Z5montePiPfS0_ii:
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s2, 31
s_ashr_i32 s8, s3, 31
s_add_i32 s5, s2, s4
s_add_i32 s9, s3, s8
s_xor_b32 s5, s5, s4
s_xor_b32 s9, s9, s8
v_cvt_f32_u32_e32 v1, s5
s_sub_i32 s7, 0, s5
s_xor_b32 s4, s8, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s6, v1
s_mul_i32 s7, s7, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s7, s6, s7
s_add_i32 s6, s6, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s6, s9, s6
s_mul_i32 s7, s6, s5
s_add_i32 s8, s6, 1
s_sub_i32 s7, s9, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s9, s7, s5
s_cmp_ge_u32 s7, s5
s_cselect_b32 s6, s8, s6
s_cselect_b32 s7, s9, s7
s_add_i32 s8, s6, 1
s_cmp_ge_u32 s7, s5
s_cselect_b32 s5, s8, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s5, s5, s4
s_sub_i32 s10, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s10, 0
s_cbranch_scc1 .LBB0_6
s_load_b32 s4, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_load_b64 s[8:9], s[0:1], 0x10
s_add_i32 s1, s10, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_mov_b32 s4, 0x3e76c4e1
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
v_add_nc_u32_e32 v1, s2, v1
s_add_i32 s1, s1, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_6
.LBB0_3:
s_mov_b32 s5, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_co_u32 v7, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
global_load_b32 v0, v[7:8], off
global_load_b32 v2, v[5:6], off
s_waitcnt vmcnt(1)
v_frexp_mant_f32_e64 v5, |v0|
s_waitcnt vmcnt(0)
v_frexp_mant_f32_e64 v6, |v2|
v_frexp_exp_i32_f32_e32 v20, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v5
v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v6
v_cndmask_b32_e64 v7, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v8, 0, 1, s0
v_ldexp_f32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f32 v6, v6, v8
v_dual_add_f32 v7, 1.0, v5 :: v_dual_add_f32 v8, 1.0, v6
v_dual_add_f32 v11, -1.0, v5 :: v_dual_add_f32 v12, -1.0, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v9, v7
v_rcp_f32_e32 v10, v8
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v13, v11, v9 :: v_dual_mul_f32 v14, v12, v10
v_add_f32_e32 v15, -1.0, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_add_f32 v17, -1.0, v8 :: v_dual_mul_f32 v16, v7, v13
v_dual_mul_f32 v18, v8, v14 :: v_dual_sub_f32 v5, v5, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v6, v6, v17
v_fma_f32 v7, v13, v7, -v16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, v14, v8, -v18
v_dual_fmac_f32 v7, v13, v5 :: v_dual_fmac_f32 v8, v14, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v5, v16, v7 :: v_dual_add_f32 v6, v18, v8
v_dual_sub_f32 v15, v11, v5 :: v_dual_sub_f32 v16, v5, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v18, v6, v18
v_sub_f32_e32 v17, v12, v6
v_dual_sub_f32 v11, v11, v15 :: v_dual_sub_f32 v8, v18, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v7, v16, v7
v_sub_f32_e32 v5, v11, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v7, v5
v_add_f32_e32 v5, v15, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v9, v5
v_add_f32_e32 v7, v13, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v12, v12, v17 :: v_dual_mul_f32 v11, v7, v7
v_sub_f32_e32 v6, v12, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v8, v6
v_add_f32_e32 v6, v17, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v10, v6
v_add_f32_e32 v8, v14, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v10, v8, v14 :: v_dual_sub_f32 v9, v7, v13
v_dual_sub_f32 v6, v6, v10 :: v_dual_sub_f32 v5, v5, v9
v_fma_f32 v10, v7, v7, -v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_add_f32 v14, v6, v6 :: v_dual_mul_f32 v9, v8, v8
v_add_f32_e32 v12, v5, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v13, v8, v8, -v9
v_dual_fmac_f32 v10, v7, v12 :: v_dual_fmac_f32 v13, v8, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v14, v9, v13
v_dual_add_f32 v12, v11, v10 :: v_dual_sub_f32 v9, v14, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_fmaak_f32 v15, s4, v12, 0x3e91f4c4 :: v_dual_fmaak_f32 v16, s4, v14, 0x3e91f4c4
v_sub_f32_e32 v11, v12, v11
v_sub_f32_e32 v9, v13, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_fmaak_f32 v15, v12, v15, 0x3ecccdef :: v_dual_fmaak_f32 v16, v14, v16, 0x3ecccdef
v_sub_f32_e32 v10, v10, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v17, v12, v15 :: v_dual_mul_f32 v18, v14, v16
v_fma_f32 v11, v12, v15, -v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v13, v14, v16, -v18
v_fmac_f32_e32 v11, v10, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v13, v9, v16
v_mul_f32_e32 v16, v7, v12
v_frexp_exp_i32_f32_e32 v15, v0
v_add_f32_e32 v19, v17, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v23, v12, v7, -v16
v_add_f32_e32 v24, 0x3f2aaaaa, v19
v_add_f32_e32 v22, v18, v13
v_sub_f32_e32 v17, v19, v17
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v23, v12, v5
v_ldexp_f32 v5, v5, 1
v_sub_f32_e32 v18, v22, v18
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_add_f32 v26, 0x3f2aaaaa, v22 :: v_dual_sub_f32 v11, v11, v17
v_add_f32_e32 v17, 0xbf2aaaaa, v24
v_dual_fmac_f32 v23, v10, v7 :: v_dual_sub_f32 v12, v13, v18
v_mul_f32_e32 v21, v8, v14
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f32_e32 v13, 0xbf2aaaaa, v26
v_add_f32_e32 v11, 0x31739010, v11
v_dual_sub_f32 v17, v19, v17 :: v_dual_add_f32 v10, 0x31739010, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v25, v14, v8, -v21
v_sub_f32_e32 v12, v22, v13
v_subrev_co_ci_u32_e32 v13, vcc_lo, 0, v15, vcc_lo
v_ldexp_f32 v7, v7, 1
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v25, v14, v6
v_subrev_co_ci_u32_e64 v14, vcc_lo, 0, v20, s0
v_ldexp_f32 v6, v6, 1
v_cmp_neq_f32_e64 s0, 0x7f800000, |v0|
v_fmac_f32_e32 v25, v9, v8
v_add_f32_e32 v9, v10, v12
v_ldexp_f32 v8, v8, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v15, v26, v9
v_dual_add_f32 v11, v11, v17 :: v_dual_sub_f32 v20, v26, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v12, v24, v11 :: v_dual_add_f32 v17, v21, v25
v_sub_f32_e32 v18, v24, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f32_e32 v22, v17, v15
v_add_f32_e32 v9, v9, v20
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v11, v11, v18
v_fma_f32 v20, v17, v15, -v22
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v20, v17, v9
v_add_f32_e32 v10, v16, v23
v_cvt_f32_i32_e32 v9, v14
v_mul_f32_e32 v19, v10, v12
v_sub_f32_e32 v16, v10, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v18, v10, v12, -v19
v_sub_f32_e32 v16, v23, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v18, v10, v11
v_cvt_f32_i32_e32 v10, v13
v_fmac_f32_e32 v18, v16, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v12, 0x3f317218, v10 :: v_dual_sub_f32 v21, v17, v21
v_sub_f32_e32 v11, v25, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v20, v11, v15
v_fma_f32 v15, v10, 0x3f317218, -v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v14, v22, v20 :: v_dual_fmac_f32 v15, 0xb102e308, v10
v_sub_f32_e32 v21, v14, v22
v_add_f32_e32 v11, v19, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v17, v11, v19
v_sub_f32_e32 v17, v18, v17
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v18, v20, v21
v_dual_add_f32 v16, v7, v11 :: v_dual_add_f32 v5, v5, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v6, v18
v_add_f32_e32 v19, v8, v14
v_dual_sub_f32 v8, v19, v8 :: v_dual_mul_f32 v13, 0x3f317218, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v8, v14, v8
v_dual_add_f32 v6, v6, v8 :: v_dual_sub_f32 v7, v16, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v10, v19, v6
v_sub_f32_e32 v7, v11, v7
v_fma_f32 v11, v9, 0x3f317218, -v13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v5, v5, v7
v_add_f32_e32 v7, v12, v15
v_add_f32_e32 v8, v16, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v12, v7, v12
v_add_f32_e32 v14, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_sub_f32 v18, v14, v7 :: v_dual_fmac_f32 v11, 0xb102e308, v9
v_dual_sub_f32 v12, v15, v12 :: v_dual_sub_f32 v19, v10, v19
v_sub_f32_e32 v15, v8, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v8, v8, v18
v_sub_f32_e32 v6, v6, v19
v_add_f32_e32 v9, v13, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v17, v9, v10
v_sub_f32_e32 v13, v9, v13
v_sub_f32_e32 v16, v17, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_sub_f32_e32 v11, v11, v13
v_sub_f32_e32 v13, v14, v18
v_sub_f32_e32 v5, v5, v15
v_sub_f32_e32 v15, v17, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v10, v10, v16 :: v_dual_sub_f32 v7, v7, v13
v_dual_add_f32 v7, v8, v7 :: v_dual_add_f32 v8, v11, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v9, v9, v15
v_add_f32_e32 v9, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v8, v9
v_add_f32_e32 v13, v12, v5
v_dual_sub_f32 v10, v13, v12 :: v_dual_sub_f32 v15, v8, v11
v_add_f32_e32 v7, v13, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v13, v13, v10 :: v_dual_sub_f32 v8, v8, v15
v_add_f32_e32 v16, v14, v7
v_sub_f32_e32 v6, v6, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_f32_e32 v12, v12, v13
v_dual_sub_f32 v8, v11, v8 :: v_dual_sub_f32 v5, v5, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_add_f32 v10, v17, v9 :: v_dual_sub_f32 v13, v16, v14
v_add_f32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v5, v5, v12
v_sub_f32_e32 v11, v10, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v8, v9, v11
v_add_f32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v10, v6
v_sub_f32_e32 v10, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_sub_f32 v6, v6, v10 :: v_dual_sub_f32 v7, v7, v13
v_mul_f32_e32 v13, 0, v8
v_add_f32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v13, 2.0, v6
v_add_f32_e32 v7, v16, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v9, v7, v16 :: v_dual_mul_f32 v12, 0, v7
v_sub_f32_e32 v5, v5, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v9, v8, v8 :: v_dual_fmac_f32 v12, 2.0, v5
v_fma_f32 v5, v8, 2.0, -v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v5, v13
v_dual_add_f32 v8, v9, v5 :: v_dual_add_f32 v11, v7, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v7, v7, 2.0, -v11
v_cmp_class_f32_e64 vcc_lo, v11, 0x204
v_add_f32_e32 v6, v7, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v11, v6
v_cndmask_b32_e32 v10, v7, v11, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v9, 0x204
v_cndmask_b32_e32 v12, v8, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v10
v_dual_sub_f32 v8, v8, v9 :: v_dual_sub_f32 v7, v7, v11
v_cndmask_b32_e64 v13, 0, 0x37000000, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v12
v_dual_sub_f32 v6, v6, v7 :: v_dual_sub_f32 v5, v5, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_sub_f32_e32 v15, v10, v13
v_cndmask_b32_e64 v14, 0, 0x37000000, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v10|
v_dual_mul_f32 v17, 0x3fb8aa3b, v15 :: v_dual_sub_f32 v16, v12, v14
v_cndmask_b32_e32 v6, 0, v6, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v12|
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v19, v15, 0x3fb8aa3b, -v17
v_mul_f32_e32 v18, 0x3fb8aa3b, v16
v_rndne_f32_e32 v20, v17
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v15
v_fmac_f32_e32 v19, 0x32a5705f, v15
v_fma_f32 v21, v16, 0x3fb8aa3b, -v18
v_rndne_f32_e32 v22, v18
v_sub_f32_e32 v17, v17, v20
v_cvt_i32_f32_e32 v7, v20
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_add_f32 v6, v13, v6 :: v_dual_fmac_f32 v21, 0x32a5705f, v16
v_dual_sub_f32 v18, v18, v22 :: v_dual_add_f32 v17, v17, v19
v_cvt_i32_f32_e32 v8, v22
v_add_f32_e32 v5, v14, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f32_e32 v18, v18, v21
v_exp_f32_e32 v11, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_exp_f32_e32 v9, v18
s_waitcnt_depctr 0xfff
v_ldexp_f32 v7, v11, v7
v_ldexp_f32 v8, v9, v8
v_cndmask_b32_e32 v7, 0, v7, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v8, 0, v8, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v15
v_cndmask_b32_e32 v7, 0x7f800000, v7, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f32 v6, v7, v6, v7
v_cndmask_b32_e32 v8, 0x7f800000, v8, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v7
v_fma_f32 v5, v8, v5, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v6, v6, v7, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v8
v_cndmask_b32_e64 v6, 0x7f800000, |v6|, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, v5, v8, vcc_lo
v_cmp_neq_f32_e64 s0, 0x7f800000, |v2|
v_cmp_neq_f32_e32 vcc_lo, 0, v0
v_cndmask_b32_e64 v5, 0x7f800000, |v5|, s0
v_cndmask_b32_e32 v0, 0, v6, vcc_lo
v_cmp_neq_f32_e32 vcc_lo, 0, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, 0, v5, vcc_lo
v_add_f32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ge_f32_e32 vcc_lo, 1.0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, 1, v0
global_store_b32 v[3:4], v0, off
s_branch .LBB0_2
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5montePiPfS0_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 27
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5montePiPfS0_ii, .Lfunc_end0-_Z5montePiPfS0_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5montePiPfS0_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5montePiPfS0_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 27
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <time.h>
/*
* Monte Carlo Pi Estimation Algorithm in CUDA
*
* This Project uses Cuda and thread
* topology to estimate Pi.
*
* Author: Clayton Glenn
*/
#define MAX_THREAD 16
#define MIN_THREAD 8
#define MAX_N 20
#define MIN_N 8
#define BLOCK_SIZE 256
#define DEBUG 0
/** Kernel Function
* First finds the Thread ID within the block of GPU Threads
* and if the Thread is Correct, it Encrypts the corresponding
* Character in the String.
**/
__global__
void monte(int *flags, float *x_vals, float *y_vals, int t, int n) {
//Get Thread id
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// Loop N/Threads times plus one
for(int i = 0; i < (n/t + 1); i++){
// If looped id count is less than n, grab rand x
// and y and check within unit. Increment if so
if((i*t+tid) < n){
if((pow(x_vals[(i*t+tid)], 2) + pow(y_vals[(i*t+tid)],2)) <= 1) flags[(tid)]++;
}
}
}
/**
* Helper Function
* Prints an string to standard error showing help
* for valid arguments in the executable
**/
void printerror(){
fprintf(stderr, "Invalid Arguments\n");
fprintf(stderr, "Correct Form: ./monte [# threads] [# points]\n");
exit(0);
}
/**
* Main Program
* This Program is for Homework 6 to encrypt some text or show
* the encryption method of text that is 2 to the power of N
* characters long all initialized to zero.
**/
int main(int argc, char **argv) {
// Declare a buffer of max size to start
int N = MIN_THREAD;
int THREADS = MIN_THREAD;
int BLOCKS = 256;
// Check for immediate errors in args
if (argc < 3 || argc > 3) printerror();
// Get Thread Count Per Block
THREADS = strtol(argv[1], NULL, 10);
THREADS = ((int)pow(2, THREADS));
if(THREADS < BLOCKS) BLOCKS = 1;
else THREADS = THREADS / BLOCKS;
// Get N Coordinates
N = strtol(argv[2], NULL, 10);
N = (int)pow(2, N);
// Print N and Threads for distinguish
printf("(Threads: %d) (N: %d)\n", THREADS * BLOCKS, N);
//Set Array of Size Thread
int flags[BLOCKS*THREADS];
float randx[N];
float randy[N];
srand( time( NULL ) );
for(int i = 0; i < N; i++){
if(i < BLOCKS*THREADS)flags[i] = 0;
randx[i] = ( float )rand()/RAND_MAX;
randy[i] = ( float )rand()/RAND_MAX;
}
// Init all other variables
int *dev_flags;
float *dev_randx;
float *dev_randy;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float final_time = 0.0;
// Allocate memory in the GPU for the int array
hipMalloc(&dev_randx, N*sizeof(float));
hipMalloc(&dev_randy, N*sizeof(float));
hipMalloc(&dev_flags, BLOCKS*THREADS*sizeof(int));
// Copy the Memory from the array to the array pointers
hipMemcpy(dev_flags, flags, BLOCKS*THREADS*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_randx, randx, N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_randy, randy, N*sizeof(float), hipMemcpyHostToDevice);
// Total Time Record
hipEventRecord(start);
monte<<<BLOCKS, THREADS>>>(dev_flags, dev_randx, dev_randy, BLOCKS*THREADS, N);
hipEventRecord(stop);
// Copy the results from GPU to the CPU
hipMemcpy(flags, dev_flags, BLOCKS*THREADS*sizeof(int), hipMemcpyDeviceToHost);
// Count total successes for each thread
int success = 0;
for(int i = 0; i < BLOCKS*THREADS; i++){
if(flags[i] > 0) success += flags[i];
}
// Print Successes, failures, and estimation
//printf("Success: %d\n", success);
//printf("Failure: %d\n", (N - success));
printf("Estimation of Pi: %1.6f\n", ((float)success/N)*4);
hipEventSynchronize(stop);
hipEventElapsedTime(&final_time, start, stop);
printf("Time in Kernel: %1.10f\n\n", final_time/1000);
hipFree(dev_flags);
hipFree(dev_randx);
hipFree(dev_randy);
} | .text
.file "Monte_CUDA.hip"
.globl _Z20__device_stub__montePiPfS0_ii # -- Begin function _Z20__device_stub__montePiPfS0_ii
.p2align 4, 0x90
.type _Z20__device_stub__montePiPfS0_ii,@function
_Z20__device_stub__montePiPfS0_ii: # @_Z20__device_stub__montePiPfS0_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5montePiPfS0_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__montePiPfS0_ii, .Lfunc_end0-_Z20__device_stub__montePiPfS0_ii
.cfi_endproc
# -- End function
.globl _Z10printerrorv # -- Begin function _Z10printerrorv
.p2align 4, 0x90
.type _Z10printerrorv,@function
_Z10printerrorv: # @_Z10printerrorv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $18, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $45, %esi
movl $1, %edx
callq fwrite@PLT
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size _Z10printerrorv, .Lfunc_end1-_Z10printerrorv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x3ff0000000000000 # double 1
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_1:
.long 0x30000000 # float 4.65661287E-10
.LCPI2_2:
.long 0x40800000 # float 4
.LCPI2_3:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $216, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
cmpl $3, %edi
jne .LBB2_14
# %bb.1:
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movsd .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl %eax, %edi
callq ldexp@PLT
cvttsd2si %xmm0, %eax
movl %eax, %r12d
shrl $8, %r12d
cmpl $256, %eax # imm = 0x100
setge %r14b
movl %eax, -92(%rbp) # 4-byte Spill
cmovll %eax, %r12d
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movsd .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl %eax, %edi
callq ldexp@PLT
cvttsd2si %xmm0, %r15d
shlb $3, %r14b
movl %r12d, -96(%rbp) # 4-byte Spill
# kill: def $r12d killed $r12d def $r12
movl %r14d, %ecx
shll %cl, %r12d
movl $.L.str.2, %edi
movl %r12d, %esi
movl %r15d, %edx
xorl %eax, %eax
callq printf
leaq 15(,%r12,4), %rax
andq $-16, %rax
movq %rsp, %rcx
subq %rax, %rcx
movq %rcx, -112(%rbp) # 8-byte Spill
movq %rcx, %rsp
leaq 15(,%r15,4), %rax
andq $-16, %rax
movq %rsp, %rbx
subq %rax, %rbx
movq %rbx, %rsp
movq %rsp, %r13
subq %rax, %r13
movq %r13, %rsp
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movq %r12, -136(%rbp) # 8-byte Spill
movslq %r12d, %r14
movq %r15, -64(%rbp) # 8-byte Spill
testl %r15d, %r15d
jle .LBB2_6
# %bb.2: # %.lr.ph.preheader
movl -64(%rbp), %r15d # 4-byte Reload
xorl %r12d, %r12d
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_3 Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%r12,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_1(%rip), %xmm0
movss %xmm0, (%r13,%r12,4)
incq %r12
cmpq %r12, %r15
je .LBB2_6
.LBB2_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpq %r14, %r12
jge .LBB2_5
# %bb.4: # in Loop: Header=BB2_3 Depth=1
movq -112(%rbp), %rax # 8-byte Reload
movl $0, (%rax,%r12,4)
jmp .LBB2_5
.LBB2_6: # %._crit_edge
leaq -120(%rbp), %rdi
callq hipEventCreate
leaq -72(%rbp), %rdi
callq hipEventCreate
movl $0, -44(%rbp)
movslq -64(%rbp), %r15 # 4-byte Folded Reload
shlq $2, %r15
leaq -88(%rbp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq -80(%rbp), %rdi
movq %r15, %rsi
callq hipMalloc
shlq $2, %r14
leaq -56(%rbp), %rdi
movq %r14, %rsi
callq hipMalloc
movq -56(%rbp), %rdi
movq -112(%rbp), %r12 # 8-byte Reload
movq %r12, %rsi
movq %r14, -128(%rbp) # 8-byte Spill
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq -88(%rbp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq -80(%rbp), %rdi
movq %r13, %rsi
movq -64(%rbp), %r13 # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq -120(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
cmpl $256, -92(%rbp) # 4-byte Folded Reload
# imm = 0x100
movl $1, %eax
movl $256, %edi # imm = 0x100
cmovlq %rax, %rdi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl -96(%rbp), %edx # 4-byte Reload
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq -136(%rbp), %r15 # 8-byte Reload
jne .LBB2_8
# %bb.7:
movq -56(%rbp), %rax
movq -88(%rbp), %rcx
movq -80(%rbp), %rdx
movq %rax, -208(%rbp)
movq %rcx, -200(%rbp)
movq %rdx, -192(%rbp)
movl %r15d, -104(%rbp)
movl %r13d, -100(%rbp)
leaq -208(%rbp), %rax
movq %rax, -256(%rbp)
leaq -200(%rbp), %rax
movq %rax, -248(%rbp)
leaq -192(%rbp), %rax
movq %rax, -240(%rbp)
leaq -104(%rbp), %rax
movq %rax, -232(%rbp)
leaq -100(%rbp), %rax
movq %rax, -224(%rbp)
leaq -184(%rbp), %rdi
leaq -168(%rbp), %rsi
leaq -152(%rbp), %rdx
leaq -144(%rbp), %rcx
callq __hipPopCallConfiguration
movq -184(%rbp), %rsi
movl -176(%rbp), %edx
movq -168(%rbp), %rcx
movl -160(%rbp), %r8d
leaq -256(%rbp), %r9
movl $_Z5montePiPfS0_ii, %edi
pushq -144(%rbp)
pushq -152(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB2_8:
movq -72(%rbp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
movq -56(%rbp), %rsi
movq %r12, %rdi
movq -128(%rbp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %r15d, %r15d
jle .LBB2_9
# %bb.12: # %.lr.ph70.preheader
movl %r15d, %eax
xorl %edx, %edx
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_13: # %.lr.ph70
# =>This Inner Loop Header: Depth=1
movl (%r12,%rdx,4), %esi
testl %esi, %esi
cmovlel %ebx, %esi
addl %esi, %ecx
incq %rdx
cmpq %rdx, %rax
jne .LBB2_13
# %bb.10: # %._crit_edge71.loopexit
cvtsi2ss %ecx, %xmm0
jmp .LBB2_11
.LBB2_9:
xorpd %xmm0, %xmm0
.LBB2_11: # %._crit_edge71
cvtsi2ss %r13d, %xmm1
divss %xmm1, %xmm0
mulss .LCPI2_2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq -72(%rbp), %rdi
callq hipEventSynchronize
movq -120(%rbp), %rsi
movq -72(%rbp), %rdx
leaq -44(%rbp), %rdi
callq hipEventElapsedTime
movss -44(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI2_3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movq -56(%rbp), %rdi
callq hipFree
movq -88(%rbp), %rdi
callq hipFree
movq -80(%rbp), %rdi
callq hipFree
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB2_14:
.cfi_def_cfa %rbp, 16
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $18, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $45, %esi
movl $1, %edx
callq fwrite@PLT
xorl %edi, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5montePiPfS0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5montePiPfS0_ii,@object # @_Z5montePiPfS0_ii
.section .rodata,"a",@progbits
.globl _Z5montePiPfS0_ii
.p2align 3, 0x0
_Z5montePiPfS0_ii:
.quad _Z20__device_stub__montePiPfS0_ii
.size _Z5montePiPfS0_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Invalid Arguments\n"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Correct Form: ./monte [# threads] [# points]\n"
.size .L.str.1, 46
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "(Threads: %d) (N: %d)\n"
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Estimation of Pi: %1.6f\n"
.size .L.str.3, 25
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Time in Kernel: %1.10f\n\n"
.size .L.str.4, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5montePiPfS0_ii"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__montePiPfS0_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5montePiPfS0_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00039477_00000000-6_Monte_CUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Invalid Arguments\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Correct Form: ./monte [# threads] [# points]\n"
.text
.globl _Z10printerrorv
.type _Z10printerrorv, @function
_Z10printerrorv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10printerrorv, .-_Z10printerrorv
.globl _Z31__device_stub__Z5montePiPfS0_iiPiPfS0_ii
.type _Z31__device_stub__Z5montePiPfS0_iiPiPfS0_ii, @function
_Z31__device_stub__Z5montePiPfS0_iiPiPfS0_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5montePiPfS0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z31__device_stub__Z5montePiPfS0_iiPiPfS0_ii, .-_Z31__device_stub__Z5montePiPfS0_iiPiPfS0_ii
.globl _Z5montePiPfS0_ii
.type _Z5montePiPfS0_ii, @function
_Z5montePiPfS0_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z5montePiPfS0_iiPiPfS0_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z5montePiPfS0_ii, .-_Z5montePiPfS0_ii
.section .rodata.str1.1
.LC3:
.string "(Threads: %d) (N: %d)\n"
.LC7:
.string "Estimation of Pi: %1.6f\n"
.LC9:
.string "Time in Kernel: %1.10f\n\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $136, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
cmpl $3, %edi
jne .L39
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
movsd .LC2(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %eax
movl %eax, -140(%rbp)
movl $1, -144(%rbp)
cmpl $255, %eax
jle .L16
movl $256, %ecx
cltd
idivl %ecx
movl %eax, -140(%rbp)
movl $256, -144(%rbp)
.L16:
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
movsd .LC2(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %ecx
movl %ecx, -156(%rbp)
movl -140(%rbp), %r12d
movl -144(%rbp), %eax
imull %eax, %r12d
movl %r12d, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %r12d, %rax
salq $2, %rax
movq %rax, -152(%rbp)
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L17:
cmpq %rdx, %rsp
je .L18
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L17
.L39:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L40
call _Z10printerrorv
.L40:
call __stack_chk_fail@PLT
.L18:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L19
orq $0, -8(%rsp,%rax)
.L19:
movq %rsp, -136(%rbp)
movslq -156(%rbp), %r15
leaq 0(,%r15,4), %rax
movq %rax, -168(%rbp)
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L20:
cmpq %rdx, %rsp
je .L21
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L20
.L21:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L22
orq $0, -8(%rsp,%rax)
.L22:
movq %rsp, %r13
movq -168(%rbp), %rax
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L23:
cmpq %rdx, %rsp
je .L24
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L23
.L24:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L25
orq $0, -8(%rsp,%rax)
.L25:
movq %rsp, %r14
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
cmpl $0, -156(%rbp)
jle .L26
movl $0, %ebx
jmp .L28
.L27:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC4(%rip), %xmm0
movss %xmm0, 0(%r13,%rbx,4)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC4(%rip), %xmm0
movss %xmm0, (%r14,%rbx,4)
addq $1, %rbx
cmpq %rbx, %r15
je .L26
.L28:
cmpl %ebx, %r12d
jle .L27
movq -136(%rbp), %rax
movl $0, (%rax,%rbx,4)
jmp .L27
.L26:
leaq -96(%rbp), %rdi
call cudaEventCreate@PLT
leaq -88(%rbp), %rdi
call cudaEventCreate@PLT
movl $0x00000000, -124(%rbp)
leaq -112(%rbp), %rdi
movq -168(%rbp), %rbx
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -104(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -120(%rbp), %rdi
movq -152(%rbp), %r15
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq -136(%rbp), %rsi
movq -120(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq -112(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq -104(%rbp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq -96(%rbp), %rdi
call cudaEventRecord@PLT
movl -140(%rbp), %eax
movl %eax, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl -144(%rbp), %eax
movl %eax, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L29:
movl $0, %esi
movq -88(%rbp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq -152(%rbp), %r14
movq %r14, %rdx
movq -120(%rbp), %rsi
movq -136(%rbp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
testl %r12d, %r12d
jle .L35
movq %rbx, %rax
movq %rbx, %rsi
addq %r14, %rsi
movl $0, %edx
.L32:
movl (%rax), %ecx
leal (%rdx,%rcx), %edi
testl %ecx, %ecx
cmovg %edi, %edx
addq $4, %rax
cmpq %rsi, %rax
jne .L32
.L30:
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl -156(%rbp), %xmm1
divss %xmm1, %xmm0
mulss .LC6(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq -88(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -124(%rbp), %rdi
movq -88(%rbp), %rdx
movq -96(%rbp), %rsi
call cudaEventElapsedTime@PLT
movss -124(%rbp), %xmm0
divss .LC8(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq -120(%rbp), %rdi
call cudaFree@PLT
movq -112(%rbp), %rdi
call cudaFree@PLT
movq -104(%rbp), %rdi
call cudaFree@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L41:
.cfi_restore_state
movl -156(%rbp), %r8d
movl %r12d, %ecx
movq -104(%rbp), %rdx
movq -112(%rbp), %rsi
movq -120(%rbp), %rdi
call _Z31__device_stub__Z5montePiPfS0_iiPiPfS0_ii
jmp .L29
.L35:
movl $0, %edx
jmp .L30
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z5montePiPfS0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z5montePiPfS0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1073741824
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 805306368
.align 4
.LC6:
.long 1082130432
.align 4
.LC8:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Monte_CUDA.hip"
.globl _Z20__device_stub__montePiPfS0_ii # -- Begin function _Z20__device_stub__montePiPfS0_ii
.p2align 4, 0x90
.type _Z20__device_stub__montePiPfS0_ii,@function
_Z20__device_stub__montePiPfS0_ii: # @_Z20__device_stub__montePiPfS0_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5montePiPfS0_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__montePiPfS0_ii, .Lfunc_end0-_Z20__device_stub__montePiPfS0_ii
.cfi_endproc
# -- End function
.globl _Z10printerrorv # -- Begin function _Z10printerrorv
.p2align 4, 0x90
.type _Z10printerrorv,@function
_Z10printerrorv: # @_Z10printerrorv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $18, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $45, %esi
movl $1, %edx
callq fwrite@PLT
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size _Z10printerrorv, .Lfunc_end1-_Z10printerrorv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x3ff0000000000000 # double 1
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_1:
.long 0x30000000 # float 4.65661287E-10
.LCPI2_2:
.long 0x40800000 # float 4
.LCPI2_3:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $216, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
cmpl $3, %edi
jne .LBB2_14
# %bb.1:
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movsd .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl %eax, %edi
callq ldexp@PLT
cvttsd2si %xmm0, %eax
movl %eax, %r12d
shrl $8, %r12d
cmpl $256, %eax # imm = 0x100
setge %r14b
movl %eax, -92(%rbp) # 4-byte Spill
cmovll %eax, %r12d
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movsd .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl %eax, %edi
callq ldexp@PLT
cvttsd2si %xmm0, %r15d
shlb $3, %r14b
movl %r12d, -96(%rbp) # 4-byte Spill
# kill: def $r12d killed $r12d def $r12
movl %r14d, %ecx
shll %cl, %r12d
movl $.L.str.2, %edi
movl %r12d, %esi
movl %r15d, %edx
xorl %eax, %eax
callq printf
leaq 15(,%r12,4), %rax
andq $-16, %rax
movq %rsp, %rcx
subq %rax, %rcx
movq %rcx, -112(%rbp) # 8-byte Spill
movq %rcx, %rsp
leaq 15(,%r15,4), %rax
andq $-16, %rax
movq %rsp, %rbx
subq %rax, %rbx
movq %rbx, %rsp
movq %rsp, %r13
subq %rax, %r13
movq %r13, %rsp
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movq %r12, -136(%rbp) # 8-byte Spill
movslq %r12d, %r14
movq %r15, -64(%rbp) # 8-byte Spill
testl %r15d, %r15d
jle .LBB2_6
# %bb.2: # %.lr.ph.preheader
movl -64(%rbp), %r15d # 4-byte Reload
xorl %r12d, %r12d
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_3 Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%r12,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_1(%rip), %xmm0
movss %xmm0, (%r13,%r12,4)
incq %r12
cmpq %r12, %r15
je .LBB2_6
.LBB2_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpq %r14, %r12
jge .LBB2_5
# %bb.4: # in Loop: Header=BB2_3 Depth=1
movq -112(%rbp), %rax # 8-byte Reload
movl $0, (%rax,%r12,4)
jmp .LBB2_5
.LBB2_6: # %._crit_edge
leaq -120(%rbp), %rdi
callq hipEventCreate
leaq -72(%rbp), %rdi
callq hipEventCreate
movl $0, -44(%rbp)
movslq -64(%rbp), %r15 # 4-byte Folded Reload
shlq $2, %r15
leaq -88(%rbp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq -80(%rbp), %rdi
movq %r15, %rsi
callq hipMalloc
shlq $2, %r14
leaq -56(%rbp), %rdi
movq %r14, %rsi
callq hipMalloc
movq -56(%rbp), %rdi
movq -112(%rbp), %r12 # 8-byte Reload
movq %r12, %rsi
movq %r14, -128(%rbp) # 8-byte Spill
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq -88(%rbp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq -80(%rbp), %rdi
movq %r13, %rsi
movq -64(%rbp), %r13 # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq -120(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
cmpl $256, -92(%rbp) # 4-byte Folded Reload
# imm = 0x100
movl $1, %eax
movl $256, %edi # imm = 0x100
cmovlq %rax, %rdi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl -96(%rbp), %edx # 4-byte Reload
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq -136(%rbp), %r15 # 8-byte Reload
jne .LBB2_8
# %bb.7:
movq -56(%rbp), %rax
movq -88(%rbp), %rcx
movq -80(%rbp), %rdx
movq %rax, -208(%rbp)
movq %rcx, -200(%rbp)
movq %rdx, -192(%rbp)
movl %r15d, -104(%rbp)
movl %r13d, -100(%rbp)
leaq -208(%rbp), %rax
movq %rax, -256(%rbp)
leaq -200(%rbp), %rax
movq %rax, -248(%rbp)
leaq -192(%rbp), %rax
movq %rax, -240(%rbp)
leaq -104(%rbp), %rax
movq %rax, -232(%rbp)
leaq -100(%rbp), %rax
movq %rax, -224(%rbp)
leaq -184(%rbp), %rdi
leaq -168(%rbp), %rsi
leaq -152(%rbp), %rdx
leaq -144(%rbp), %rcx
callq __hipPopCallConfiguration
movq -184(%rbp), %rsi
movl -176(%rbp), %edx
movq -168(%rbp), %rcx
movl -160(%rbp), %r8d
leaq -256(%rbp), %r9
movl $_Z5montePiPfS0_ii, %edi
pushq -144(%rbp)
pushq -152(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB2_8:
movq -72(%rbp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
movq -56(%rbp), %rsi
movq %r12, %rdi
movq -128(%rbp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %r15d, %r15d
jle .LBB2_9
# %bb.12: # %.lr.ph70.preheader
movl %r15d, %eax
xorl %edx, %edx
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_13: # %.lr.ph70
# =>This Inner Loop Header: Depth=1
movl (%r12,%rdx,4), %esi
testl %esi, %esi
cmovlel %ebx, %esi
addl %esi, %ecx
incq %rdx
cmpq %rdx, %rax
jne .LBB2_13
# %bb.10: # %._crit_edge71.loopexit
cvtsi2ss %ecx, %xmm0
jmp .LBB2_11
.LBB2_9:
xorpd %xmm0, %xmm0
.LBB2_11: # %._crit_edge71
cvtsi2ss %r13d, %xmm1
divss %xmm1, %xmm0
mulss .LCPI2_2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq -72(%rbp), %rdi
callq hipEventSynchronize
movq -120(%rbp), %rsi
movq -72(%rbp), %rdx
leaq -44(%rbp), %rdi
callq hipEventElapsedTime
movss -44(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI2_3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movq -56(%rbp), %rdi
callq hipFree
movq -88(%rbp), %rdi
callq hipFree
movq -80(%rbp), %rdi
callq hipFree
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB2_14:
.cfi_def_cfa %rbp, 16
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $18, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $45, %esi
movl $1, %edx
callq fwrite@PLT
xorl %edi, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5montePiPfS0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5montePiPfS0_ii,@object # @_Z5montePiPfS0_ii
.section .rodata,"a",@progbits
.globl _Z5montePiPfS0_ii
.p2align 3, 0x0
_Z5montePiPfS0_ii:
.quad _Z20__device_stub__montePiPfS0_ii
.size _Z5montePiPfS0_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Invalid Arguments\n"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Correct Form: ./monte [# threads] [# points]\n"
.size .L.str.1, 46
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "(Threads: %d) (N: %d)\n"
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Estimation of Pi: %1.6f\n"
.size .L.str.3, 25
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Time in Kernel: %1.10f\n\n"
.size .L.str.4, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5montePiPfS0_ii"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__montePiPfS0_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5montePiPfS0_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define N 578 // size of vectors
#define T 275 //number of threads per block
//Need to show array of a and b
__global__ void vecAdd(int *A ,int *B,int *C){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
}
int main(int argc, char *argv[]){
int blocks = (N + T - 1) / T;
srand(1234);
int i;
int size = N * sizeof ( int);
int a[N], b[N], c[N], *devA, *devB, *devC;
for (i = 0;i < N; i++){
a[i] = rand() % 100;
b[i] = rand() % 100;
}
cudaMalloc( (void**)&devA, size);
cudaMalloc( (void**)&devB, size);
cudaMalloc( (void**)&devC, size);
cudaMemcpy( devA, a, size, cudaMemcpyHostToDevice);
cudaMemcpy( devB, b, size, cudaMemcpyHostToDevice);
vecAdd<<<blocks,T>>>(devA,devB,devC);
cudaMemcpy( c, devC, size, cudaMemcpyDeviceToHost);
cudaFree( devA);
cudaFree( devB);
cudaFree( devC);
for (i = 0; i < N; i++){
printf("%d ",c[i]);
}
printf("\n");
} | code for sm_80
Function : _Z6vecAddPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0x241, PT ; /* 0x000002410600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define N 578 // size of vectors
#define T 275 //number of threads per block
//Need to show array of a and b
__global__ void vecAdd(int *A ,int *B,int *C){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
}
int main(int argc, char *argv[]){
int blocks = (N + T - 1) / T;
srand(1234);
int i;
int size = N * sizeof ( int);
int a[N], b[N], c[N], *devA, *devB, *devC;
for (i = 0;i < N; i++){
a[i] = rand() % 100;
b[i] = rand() % 100;
}
cudaMalloc( (void**)&devA, size);
cudaMalloc( (void**)&devB, size);
cudaMalloc( (void**)&devC, size);
cudaMemcpy( devA, a, size, cudaMemcpyHostToDevice);
cudaMemcpy( devB, b, size, cudaMemcpyHostToDevice);
vecAdd<<<blocks,T>>>(devA,devB,devC);
cudaMemcpy( c, devC, size, cudaMemcpyDeviceToHost);
cudaFree( devA);
cudaFree( devB);
cudaFree( devC);
for (i = 0; i < N; i++){
printf("%d ",c[i]);
}
printf("\n");
} | .file "tmpxft_000992a7_00000000-6_vecAdd4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6vecAddPiS_S_PiS_S_
.type _Z29__device_stub__Z6vecAddPiS_S_PiS_S_, @function
_Z29__device_stub__Z6vecAddPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z6vecAddPiS_S_PiS_S_, .-_Z29__device_stub__Z6vecAddPiS_S_PiS_S_
.globl _Z6vecAddPiS_S_
.type _Z6vecAddPiS_S_, @function
_Z6vecAddPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6vecAddPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6vecAddPiS_S_, .-_Z6vecAddPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $4096, %rsp
.cfi_def_cfa_offset 4128
orq $0, (%rsp)
subq $2912, %rsp
.cfi_def_cfa_offset 7040
movq %fs:40, %rax
movq %rax, 7000(%rsp)
xorl %eax, %eax
movl $1234, %edi
call srand@PLT
movl $0, %ebx
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, 48(%rsp,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, 2368(%rsp,%rbx)
addq $4, %rbx
cmpq $2312, %rbx
jne .L12
movq %rsp, %rdi
movl $2312, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $2312, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $2312, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $2312, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 2368(%rsp), %rsi
movl $1, %ecx
movl $2312, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $275, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $3, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 4688(%rsp), %rbx
movl $2, %ecx
movl $2312, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq 7000(%rsp), %r12
leaq .LC0(%rip), %rbp
.L14:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 7000(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $7008, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z29__device_stub__Z6vecAddPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6vecAddPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define N 578 // size of vectors
#define T 275 //number of threads per block
//Need to show array of a and b
__global__ void vecAdd(int *A ,int *B,int *C){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
}
int main(int argc, char *argv[]){
int blocks = (N + T - 1) / T;
srand(1234);
int i;
int size = N * sizeof ( int);
int a[N], b[N], c[N], *devA, *devB, *devC;
for (i = 0;i < N; i++){
a[i] = rand() % 100;
b[i] = rand() % 100;
}
cudaMalloc( (void**)&devA, size);
cudaMalloc( (void**)&devB, size);
cudaMalloc( (void**)&devC, size);
cudaMemcpy( devA, a, size, cudaMemcpyHostToDevice);
cudaMemcpy( devB, b, size, cudaMemcpyHostToDevice);
vecAdd<<<blocks,T>>>(devA,devB,devC);
cudaMemcpy( c, devC, size, cudaMemcpyDeviceToHost);
cudaFree( devA);
cudaFree( devB);
cudaFree( devC);
for (i = 0; i < N; i++){
printf("%d ",c[i]);
}
printf("\n");
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 578 // size of vectors
#define T 275 //number of threads per block
//Need to show array of a and b
__global__ void vecAdd(int *A ,int *B,int *C){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
}
int main(int argc, char *argv[]){
int blocks = (N + T - 1) / T;
srand(1234);
int i;
int size = N * sizeof ( int);
int a[N], b[N], c[N], *devA, *devB, *devC;
for (i = 0;i < N; i++){
a[i] = rand() % 100;
b[i] = rand() % 100;
}
hipMalloc( (void**)&devA, size);
hipMalloc( (void**)&devB, size);
hipMalloc( (void**)&devC, size);
hipMemcpy( devA, a, size, hipMemcpyHostToDevice);
hipMemcpy( devB, b, size, hipMemcpyHostToDevice);
vecAdd<<<blocks,T>>>(devA,devB,devC);
hipMemcpy( c, devC, size, hipMemcpyDeviceToHost);
hipFree( devA);
hipFree( devB);
hipFree( devC);
for (i = 0; i < N; i++){
printf("%d ",c[i]);
}
printf("\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 578 // size of vectors
#define T 275 //number of threads per block
//Need to show array of a and b
__global__ void vecAdd(int *A ,int *B,int *C){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
}
int main(int argc, char *argv[]){
int blocks = (N + T - 1) / T;
srand(1234);
int i;
int size = N * sizeof ( int);
int a[N], b[N], c[N], *devA, *devB, *devC;
for (i = 0;i < N; i++){
a[i] = rand() % 100;
b[i] = rand() % 100;
}
hipMalloc( (void**)&devA, size);
hipMalloc( (void**)&devB, size);
hipMalloc( (void**)&devC, size);
hipMemcpy( devA, a, size, hipMemcpyHostToDevice);
hipMemcpy( devB, b, size, hipMemcpyHostToDevice);
vecAdd<<<blocks,T>>>(devA,devB,devC);
hipMemcpy( c, devC, size, hipMemcpyDeviceToHost);
hipFree( devA);
hipFree( devB);
hipFree( devC);
for (i = 0; i < N; i++){
printf("%d ",c[i]);
}
printf("\n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPiS_S_
.globl _Z6vecAddPiS_S_
.p2align 8
.type _Z6vecAddPiS_S_,@function
_Z6vecAddPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x242, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPiS_S_, .Lfunc_end0-_Z6vecAddPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecAddPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 578 // size of vectors
#define T 275 //number of threads per block
//Need to show array of a and b
__global__ void vecAdd(int *A ,int *B,int *C){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
}
int main(int argc, char *argv[]){
int blocks = (N + T - 1) / T;
srand(1234);
int i;
int size = N * sizeof ( int);
int a[N], b[N], c[N], *devA, *devB, *devC;
for (i = 0;i < N; i++){
a[i] = rand() % 100;
b[i] = rand() % 100;
}
hipMalloc( (void**)&devA, size);
hipMalloc( (void**)&devB, size);
hipMalloc( (void**)&devC, size);
hipMemcpy( devA, a, size, hipMemcpyHostToDevice);
hipMemcpy( devB, b, size, hipMemcpyHostToDevice);
vecAdd<<<blocks,T>>>(devA,devB,devC);
hipMemcpy( c, devC, size, hipMemcpyDeviceToHost);
hipFree( devA);
hipFree( devB);
hipFree( devC);
for (i = 0; i < N; i++){
printf("%d ",c[i]);
}
printf("\n");
} | .text
.file "vecAdd4.hip"
.globl _Z21__device_stub__vecAddPiS_S_ # -- Begin function _Z21__device_stub__vecAddPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPiS_S_,@function
_Z21__device_stub__vecAddPiS_S_: # @_Z21__device_stub__vecAddPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__vecAddPiS_S_, .Lfunc_end0-_Z21__device_stub__vecAddPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $7056, %rsp # imm = 0x1B90
.cfi_def_cfa_offset 7072
.cfi_offset %rbx, -16
movl $1234, %edi # imm = 0x4D2
callq srand
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, 4736(%rsp,%rbx,4)
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, 2416(%rsp,%rbx,4)
incq %rbx
cmpq $578, %rbx # imm = 0x242
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $2312, %esi # imm = 0x908
callq hipMalloc
leaq 8(%rsp), %rdi
movl $2312, %esi # imm = 0x908
callq hipMalloc
movq %rsp, %rdi
movl $2312, %esi # imm = 0x908
callq hipMalloc
movq 16(%rsp), %rdi
leaq 4736(%rsp), %rsi
movl $2312, %edx # imm = 0x908
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 2416(%rsp), %rsi
movl $2312, %edx # imm = 0x908
movl $1, %ecx
callq hipMemcpy
movabsq $4294967299, %rdi # imm = 0x100000003
leaq 272(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6vecAddPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $2312, %edx # imm = 0x908
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 96(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $578, %rbx # imm = 0x242
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $7056, %rsp # imm = 0x1B90
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecAddPiS_S_,@object # @_Z6vecAddPiS_S_
.section .rodata,"a",@progbits
.globl _Z6vecAddPiS_S_
.p2align 3, 0x0
_Z6vecAddPiS_S_:
.quad _Z21__device_stub__vecAddPiS_S_
.size _Z6vecAddPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecAddPiS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6vecAddPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0x241, PT ; /* 0x000002410600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPiS_S_
.globl _Z6vecAddPiS_S_
.p2align 8
.type _Z6vecAddPiS_S_,@function
_Z6vecAddPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x242, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPiS_S_, .Lfunc_end0-_Z6vecAddPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecAddPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000992a7_00000000-6_vecAdd4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6vecAddPiS_S_PiS_S_
.type _Z29__device_stub__Z6vecAddPiS_S_PiS_S_, @function
_Z29__device_stub__Z6vecAddPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z6vecAddPiS_S_PiS_S_, .-_Z29__device_stub__Z6vecAddPiS_S_PiS_S_
.globl _Z6vecAddPiS_S_
.type _Z6vecAddPiS_S_, @function
_Z6vecAddPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6vecAddPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6vecAddPiS_S_, .-_Z6vecAddPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $4096, %rsp
.cfi_def_cfa_offset 4128
orq $0, (%rsp)
subq $2912, %rsp
.cfi_def_cfa_offset 7040
movq %fs:40, %rax
movq %rax, 7000(%rsp)
xorl %eax, %eax
movl $1234, %edi
call srand@PLT
movl $0, %ebx
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, 48(%rsp,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, 2368(%rsp,%rbx)
addq $4, %rbx
cmpq $2312, %rbx
jne .L12
movq %rsp, %rdi
movl $2312, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $2312, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $2312, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $2312, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 2368(%rsp), %rsi
movl $1, %ecx
movl $2312, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $275, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $3, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 4688(%rsp), %rbx
movl $2, %ecx
movl $2312, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq 7000(%rsp), %r12
leaq .LC0(%rip), %rbp
.L14:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 7000(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $7008, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z29__device_stub__Z6vecAddPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6vecAddPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vecAdd4.hip"
.globl _Z21__device_stub__vecAddPiS_S_ # -- Begin function _Z21__device_stub__vecAddPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPiS_S_,@function
_Z21__device_stub__vecAddPiS_S_: # @_Z21__device_stub__vecAddPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__vecAddPiS_S_, .Lfunc_end0-_Z21__device_stub__vecAddPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $7056, %rsp # imm = 0x1B90
.cfi_def_cfa_offset 7072
.cfi_offset %rbx, -16
movl $1234, %edi # imm = 0x4D2
callq srand
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, 4736(%rsp,%rbx,4)
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, 2416(%rsp,%rbx,4)
incq %rbx
cmpq $578, %rbx # imm = 0x242
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $2312, %esi # imm = 0x908
callq hipMalloc
leaq 8(%rsp), %rdi
movl $2312, %esi # imm = 0x908
callq hipMalloc
movq %rsp, %rdi
movl $2312, %esi # imm = 0x908
callq hipMalloc
movq 16(%rsp), %rdi
leaq 4736(%rsp), %rsi
movl $2312, %edx # imm = 0x908
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 2416(%rsp), %rsi
movl $2312, %edx # imm = 0x908
movl $1, %ecx
callq hipMemcpy
movabsq $4294967299, %rdi # imm = 0x100000003
leaq 272(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6vecAddPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $2312, %edx # imm = 0x908
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 96(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $578, %rbx # imm = 0x242
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $7056, %rsp # imm = 0x1B90
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecAddPiS_S_,@object # @_Z6vecAddPiS_S_
.section .rodata,"a",@progbits
.globl _Z6vecAddPiS_S_
.p2align 3, 0x0
_Z6vecAddPiS_S_:
.quad _Z21__device_stub__vecAddPiS_S_
.size _Z6vecAddPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecAddPiS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
__constant__ unsigned long long fatorial[20] = {1, 1, 2, 6, 24, 120, 720, 5040, 40320, 362880, 3628800, 39916800, 479001600, 6227020800, 87178291200, 1307674368000, 20922789888000, 355687428096000, 6402373705728000, 121645100408832000};
/*
__device__
unsigned long long fatorial(int n){
unsigned long long result = 1;
int i;
for(i = n; i > 1; i--){
result *= i;
}
return result;
}*/
//Coloca o elemento da variável pos na primeira posição, e da um shift para a direia nos outros
__device__
void shiftElement(char* dest, int pos){
char temp = dest[pos];
int i;
for(i = 0; i < pos; i++){
dest[pos-i] = dest[pos-i-1];
}
dest[0] = temp;
}
__device__
void getSequenceLexicographically(char* dest, int n, unsigned long long index){
//Cria o vetor primário de tamanho N
int i;
for(i = 0; i < n; i++)
dest[i] = i+4; //Começar do numero 4
//Percorre o vetor
for(i = 0; i < n-1; i++){
//Calcula quantas alterações são possiveis sem alterar o primeiro elemento atual
unsigned long long fat = fatorial[n-i-1];
//Calcula quantas vezes foi possível trocar essa posição
int num_movimentos = index/fat;
if(num_movimentos > 0){
shiftElement(dest, num_movimentos);
//Diminui a quantidade ja calcula do indice
index -= num_movimentos*fat;
}
dest++;
}
}
__device__
void getSequence(char* dest, int n, unsigned long long index){
unsigned int numDeslocamentos2e3 = index/fatorial[n-3];
unsigned int indexResto = index%fatorial[n-3];
unsigned int pos_num2 = 1;
unsigned int pos_num3;
int i;
for(i = 0; numDeslocamentos2e3; i++){
if(numDeslocamentos2e3 >= (n-2-i)){
pos_num2++;
numDeslocamentos2e3 -= (n-2-i);
}
else{
pos_num3 = pos_num2 + 1 + numDeslocamentos2e3;
break;
}
}
if(numDeslocamentos2e3 == 0){
pos_num3 = pos_num2+1;
}
getSequenceLexicographically(dest+3, n-3, indexResto);
dest[0] = (char) 1;
for(i = 1; i < pos_num2; i++){
dest[i] = dest[i+2];
}
dest[pos_num2] = (char) 2;
for(i = pos_num2+1; i < pos_num3; i++){
dest[i] = dest[i+1];
}
dest[pos_num3] = (char) 3;
}
//Pega a quantidade de valores menores que num na variável vet.
__device__
int qtdMenores(char* vet, int num, int n){
int qtd = 0;
int i;
for(i = 0; i < n; i++){
if(vet[i] < num)
qtd++;
}
return qtd;
}
__device__
unsigned long long getIndexLexicographically(char* vet, int n){
unsigned long long index = 0;
int i;
for(i = 0; i < n-1; i++){
index += qtdMenores(vet+i+1, vet[i], n-i-1)*fatorial[n-i-1];
}
return index;
}
__device__
unsigned long long getIndex(char* vet, int n){
unsigned long long index = 0;
int i;
int pos_num2 = -1, pos_num3 = -1;
//calcula os valores dos index considerando somente o 2 e 3
for(i = 1; i < n; i++){
if(pos_num2 == -1){
if(vet[i] == 2){
pos_num2 = i;
}
else{
index += (n-i-1)*fatorial[n-3];
}
}
else{
if(vet[i] == 3){
pos_num3 = i;
break;
}
else{
index += fatorial[n-3];
}
}
}
//calcula o valor dos index considerando os outros valores de N
int pos = 0;
for(i = 1; i < n; i++){
if(i != pos_num2 && i != pos_num3){
vet[pos] = vet[i];
pos++;
}
}
index += getIndexLexicographically(vet, n-3);
return index;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
__constant__ unsigned long long fatorial[20] = {1, 1, 2, 6, 24, 120, 720, 5040, 40320, 362880, 3628800, 39916800, 479001600, 6227020800, 87178291200, 1307674368000, 20922789888000, 355687428096000, 6402373705728000, 121645100408832000};
/*
__device__
unsigned long long fatorial(int n){
unsigned long long result = 1;
int i;
for(i = n; i > 1; i--){
result *= i;
}
return result;
}*/
//Coloca o elemento da variável pos na primeira posição, e da um shift para a direia nos outros
__device__
void shiftElement(char* dest, int pos){
char temp = dest[pos];
int i;
for(i = 0; i < pos; i++){
dest[pos-i] = dest[pos-i-1];
}
dest[0] = temp;
}
__device__
void getSequenceLexicographically(char* dest, int n, unsigned long long index){
//Cria o vetor primário de tamanho N
int i;
for(i = 0; i < n; i++)
dest[i] = i+4; //Começar do numero 4
//Percorre o vetor
for(i = 0; i < n-1; i++){
//Calcula quantas alterações são possiveis sem alterar o primeiro elemento atual
unsigned long long fat = fatorial[n-i-1];
//Calcula quantas vezes foi possível trocar essa posição
int num_movimentos = index/fat;
if(num_movimentos > 0){
shiftElement(dest, num_movimentos);
//Diminui a quantidade ja calcula do indice
index -= num_movimentos*fat;
}
dest++;
}
}
__device__
void getSequence(char* dest, int n, unsigned long long index){
unsigned int numDeslocamentos2e3 = index/fatorial[n-3];
unsigned int indexResto = index%fatorial[n-3];
unsigned int pos_num2 = 1;
unsigned int pos_num3;
int i;
for(i = 0; numDeslocamentos2e3; i++){
if(numDeslocamentos2e3 >= (n-2-i)){
pos_num2++;
numDeslocamentos2e3 -= (n-2-i);
}
else{
pos_num3 = pos_num2 + 1 + numDeslocamentos2e3;
break;
}
}
if(numDeslocamentos2e3 == 0){
pos_num3 = pos_num2+1;
}
getSequenceLexicographically(dest+3, n-3, indexResto);
dest[0] = (char) 1;
for(i = 1; i < pos_num2; i++){
dest[i] = dest[i+2];
}
dest[pos_num2] = (char) 2;
for(i = pos_num2+1; i < pos_num3; i++){
dest[i] = dest[i+1];
}
dest[pos_num3] = (char) 3;
}
//Pega a quantidade de valores menores que num na variável vet.
__device__
int qtdMenores(char* vet, int num, int n){
int qtd = 0;
int i;
for(i = 0; i < n; i++){
if(vet[i] < num)
qtd++;
}
return qtd;
}
__device__
unsigned long long getIndexLexicographically(char* vet, int n){
unsigned long long index = 0;
int i;
for(i = 0; i < n-1; i++){
index += qtdMenores(vet+i+1, vet[i], n-i-1)*fatorial[n-i-1];
}
return index;
}
__device__
unsigned long long getIndex(char* vet, int n){
unsigned long long index = 0;
int i;
int pos_num2 = -1, pos_num3 = -1;
//calcula os valores dos index considerando somente o 2 e 3
for(i = 1; i < n; i++){
if(pos_num2 == -1){
if(vet[i] == 2){
pos_num2 = i;
}
else{
index += (n-i-1)*fatorial[n-3];
}
}
else{
if(vet[i] == 3){
pos_num3 = i;
break;
}
else{
index += fatorial[n-3];
}
}
}
//calcula o valor dos index considerando os outros valores de N
int pos = 0;
for(i = 1; i < n; i++){
if(i != pos_num2 && i != pos_num3){
vet[pos] = vet[i];
pos++;
}
}
index += getIndexLexicographically(vet, n-3);
return index;
} | .file "tmpxft_000285a1_00000000-6_EnumaratorSequence.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12shiftElementPci
.type _Z12shiftElementPci, @function
_Z12shiftElementPci:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z12shiftElementPci, .-_Z12shiftElementPci
.globl _Z28getSequenceLexicographicallyPciy
.type _Z28getSequenceLexicographicallyPciy, @function
_Z28getSequenceLexicographicallyPciy:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z28getSequenceLexicographicallyPciy, .-_Z28getSequenceLexicographicallyPciy
.globl _Z11getSequencePciy
.type _Z11getSequencePciy, @function
_Z11getSequencePciy:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z11getSequencePciy, .-_Z11getSequencePciy
.globl _Z10qtdMenoresPcii
.type _Z10qtdMenoresPcii, @function
_Z10qtdMenoresPcii:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z10qtdMenoresPcii, .-_Z10qtdMenoresPcii
.globl _Z25getIndexLexicographicallyPci
.type _Z25getIndexLexicographicallyPci, @function
_Z25getIndexLexicographicallyPci:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z25getIndexLexicographicallyPci, .-_Z25getIndexLexicographicallyPci
.globl _Z8getIndexPci
.type _Z8getIndexPci, @function
_Z8getIndexPci:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z8getIndexPci, .-_Z8getIndexPci
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "fatorial"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $160, %r9d
movl $0, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8fatorial(%rip), %rsi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL8fatorial
.comm _ZL8fatorial,160,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
__constant__ unsigned long long fatorial[20] = {1, 1, 2, 6, 24, 120, 720, 5040, 40320, 362880, 3628800, 39916800, 479001600, 6227020800, 87178291200, 1307674368000, 20922789888000, 355687428096000, 6402373705728000, 121645100408832000};
/*
__device__
unsigned long long fatorial(int n){
unsigned long long result = 1;
int i;
for(i = n; i > 1; i--){
result *= i;
}
return result;
}*/
//Coloca o elemento da variável pos na primeira posição, e da um shift para a direia nos outros
__device__
void shiftElement(char* dest, int pos){
char temp = dest[pos];
int i;
for(i = 0; i < pos; i++){
dest[pos-i] = dest[pos-i-1];
}
dest[0] = temp;
}
__device__
void getSequenceLexicographically(char* dest, int n, unsigned long long index){
//Cria o vetor primário de tamanho N
int i;
for(i = 0; i < n; i++)
dest[i] = i+4; //Começar do numero 4
//Percorre o vetor
for(i = 0; i < n-1; i++){
//Calcula quantas alterações são possiveis sem alterar o primeiro elemento atual
unsigned long long fat = fatorial[n-i-1];
//Calcula quantas vezes foi possível trocar essa posição
int num_movimentos = index/fat;
if(num_movimentos > 0){
shiftElement(dest, num_movimentos);
//Diminui a quantidade ja calcula do indice
index -= num_movimentos*fat;
}
dest++;
}
}
__device__
void getSequence(char* dest, int n, unsigned long long index){
unsigned int numDeslocamentos2e3 = index/fatorial[n-3];
unsigned int indexResto = index%fatorial[n-3];
unsigned int pos_num2 = 1;
unsigned int pos_num3;
int i;
for(i = 0; numDeslocamentos2e3; i++){
if(numDeslocamentos2e3 >= (n-2-i)){
pos_num2++;
numDeslocamentos2e3 -= (n-2-i);
}
else{
pos_num3 = pos_num2 + 1 + numDeslocamentos2e3;
break;
}
}
if(numDeslocamentos2e3 == 0){
pos_num3 = pos_num2+1;
}
getSequenceLexicographically(dest+3, n-3, indexResto);
dest[0] = (char) 1;
for(i = 1; i < pos_num2; i++){
dest[i] = dest[i+2];
}
dest[pos_num2] = (char) 2;
for(i = pos_num2+1; i < pos_num3; i++){
dest[i] = dest[i+1];
}
dest[pos_num3] = (char) 3;
}
//Pega a quantidade de valores menores que num na variável vet.
__device__
int qtdMenores(char* vet, int num, int n){
int qtd = 0;
int i;
for(i = 0; i < n; i++){
if(vet[i] < num)
qtd++;
}
return qtd;
}
__device__
unsigned long long getIndexLexicographically(char* vet, int n){
unsigned long long index = 0;
int i;
for(i = 0; i < n-1; i++){
index += qtdMenores(vet+i+1, vet[i], n-i-1)*fatorial[n-i-1];
}
return index;
}
__device__
unsigned long long getIndex(char* vet, int n){
unsigned long long index = 0;
int i;
int pos_num2 = -1, pos_num3 = -1;
//calcula os valores dos index considerando somente o 2 e 3
for(i = 1; i < n; i++){
if(pos_num2 == -1){
if(vet[i] == 2){
pos_num2 = i;
}
else{
index += (n-i-1)*fatorial[n-3];
}
}
else{
if(vet[i] == 3){
pos_num3 = i;
break;
}
else{
index += fatorial[n-3];
}
}
}
//calcula o valor dos index considerando os outros valores de N
int pos = 0;
for(i = 1; i < n; i++){
if(i != pos_num2 && i != pos_num3){
vet[pos] = vet[i];
pos++;
}
}
index += getIndexLexicographically(vet, n-3);
return index;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__constant__ unsigned long long fatorial[20] = {1, 1, 2, 6, 24, 120, 720, 5040, 40320, 362880, 3628800, 39916800, 479001600, 6227020800, 87178291200, 1307674368000, 20922789888000, 355687428096000, 6402373705728000, 121645100408832000};
/*
__device__
unsigned long long fatorial(int n){
unsigned long long result = 1;
int i;
for(i = n; i > 1; i--){
result *= i;
}
return result;
}*/
//Coloca o elemento da variável pos na primeira posição, e da um shift para a direia nos outros
__device__
void shiftElement(char* dest, int pos){
char temp = dest[pos];
int i;
for(i = 0; i < pos; i++){
dest[pos-i] = dest[pos-i-1];
}
dest[0] = temp;
}
__device__
void getSequenceLexicographically(char* dest, int n, unsigned long long index){
//Cria o vetor primário de tamanho N
int i;
for(i = 0; i < n; i++)
dest[i] = i+4; //Começar do numero 4
//Percorre o vetor
for(i = 0; i < n-1; i++){
//Calcula quantas alterações são possiveis sem alterar o primeiro elemento atual
unsigned long long fat = fatorial[n-i-1];
//Calcula quantas vezes foi possível trocar essa posição
int num_movimentos = index/fat;
if(num_movimentos > 0){
shiftElement(dest, num_movimentos);
//Diminui a quantidade ja calcula do indice
index -= num_movimentos*fat;
}
dest++;
}
}
__device__
void getSequence(char* dest, int n, unsigned long long index){
unsigned int numDeslocamentos2e3 = index/fatorial[n-3];
unsigned int indexResto = index%fatorial[n-3];
unsigned int pos_num2 = 1;
unsigned int pos_num3;
int i;
for(i = 0; numDeslocamentos2e3; i++){
if(numDeslocamentos2e3 >= (n-2-i)){
pos_num2++;
numDeslocamentos2e3 -= (n-2-i);
}
else{
pos_num3 = pos_num2 + 1 + numDeslocamentos2e3;
break;
}
}
if(numDeslocamentos2e3 == 0){
pos_num3 = pos_num2+1;
}
getSequenceLexicographically(dest+3, n-3, indexResto);
dest[0] = (char) 1;
for(i = 1; i < pos_num2; i++){
dest[i] = dest[i+2];
}
dest[pos_num2] = (char) 2;
for(i = pos_num2+1; i < pos_num3; i++){
dest[i] = dest[i+1];
}
dest[pos_num3] = (char) 3;
}
//Pega a quantidade de valores menores que num na variável vet.
__device__
int qtdMenores(char* vet, int num, int n){
int qtd = 0;
int i;
for(i = 0; i < n; i++){
if(vet[i] < num)
qtd++;
}
return qtd;
}
__device__
unsigned long long getIndexLexicographically(char* vet, int n){
unsigned long long index = 0;
int i;
for(i = 0; i < n-1; i++){
index += qtdMenores(vet+i+1, vet[i], n-i-1)*fatorial[n-i-1];
}
return index;
}
__device__
unsigned long long getIndex(char* vet, int n){
unsigned long long index = 0;
int i;
int pos_num2 = -1, pos_num3 = -1;
//calcula os valores dos index considerando somente o 2 e 3
for(i = 1; i < n; i++){
if(pos_num2 == -1){
if(vet[i] == 2){
pos_num2 = i;
}
else{
index += (n-i-1)*fatorial[n-3];
}
}
else{
if(vet[i] == 3){
pos_num3 = i;
break;
}
else{
index += fatorial[n-3];
}
}
}
//calcula o valor dos index considerando os outros valores de N
int pos = 0;
for(i = 1; i < n; i++){
if(i != pos_num2 && i != pos_num3){
vet[pos] = vet[i];
pos++;
}
}
index += getIndexLexicographically(vet, n-3);
return index;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__constant__ unsigned long long fatorial[20] = {1, 1, 2, 6, 24, 120, 720, 5040, 40320, 362880, 3628800, 39916800, 479001600, 6227020800, 87178291200, 1307674368000, 20922789888000, 355687428096000, 6402373705728000, 121645100408832000};
/*
__device__
unsigned long long fatorial(int n){
unsigned long long result = 1;
int i;
for(i = n; i > 1; i--){
result *= i;
}
return result;
}*/
//Coloca o elemento da variável pos na primeira posição, e da um shift para a direia nos outros
__device__
void shiftElement(char* dest, int pos){
char temp = dest[pos];
int i;
for(i = 0; i < pos; i++){
dest[pos-i] = dest[pos-i-1];
}
dest[0] = temp;
}
__device__
void getSequenceLexicographically(char* dest, int n, unsigned long long index){
//Cria o vetor primário de tamanho N
int i;
for(i = 0; i < n; i++)
dest[i] = i+4; //Começar do numero 4
//Percorre o vetor
for(i = 0; i < n-1; i++){
//Calcula quantas alterações são possiveis sem alterar o primeiro elemento atual
unsigned long long fat = fatorial[n-i-1];
//Calcula quantas vezes foi possível trocar essa posição
int num_movimentos = index/fat;
if(num_movimentos > 0){
shiftElement(dest, num_movimentos);
//Diminui a quantidade ja calcula do indice
index -= num_movimentos*fat;
}
dest++;
}
}
__device__
void getSequence(char* dest, int n, unsigned long long index){
unsigned int numDeslocamentos2e3 = index/fatorial[n-3];
unsigned int indexResto = index%fatorial[n-3];
unsigned int pos_num2 = 1;
unsigned int pos_num3;
int i;
for(i = 0; numDeslocamentos2e3; i++){
if(numDeslocamentos2e3 >= (n-2-i)){
pos_num2++;
numDeslocamentos2e3 -= (n-2-i);
}
else{
pos_num3 = pos_num2 + 1 + numDeslocamentos2e3;
break;
}
}
if(numDeslocamentos2e3 == 0){
pos_num3 = pos_num2+1;
}
getSequenceLexicographically(dest+3, n-3, indexResto);
dest[0] = (char) 1;
for(i = 1; i < pos_num2; i++){
dest[i] = dest[i+2];
}
dest[pos_num2] = (char) 2;
for(i = pos_num2+1; i < pos_num3; i++){
dest[i] = dest[i+1];
}
dest[pos_num3] = (char) 3;
}
//Pega a quantidade de valores menores que num na variável vet.
__device__
int qtdMenores(char* vet, int num, int n){
int qtd = 0;
int i;
for(i = 0; i < n; i++){
if(vet[i] < num)
qtd++;
}
return qtd;
}
__device__
unsigned long long getIndexLexicographically(char* vet, int n){
unsigned long long index = 0;
int i;
for(i = 0; i < n-1; i++){
index += qtdMenores(vet+i+1, vet[i], n-i-1)*fatorial[n-i-1];
}
return index;
}
__device__
unsigned long long getIndex(char* vet, int n){
unsigned long long index = 0;
int i;
int pos_num2 = -1, pos_num3 = -1;
//calcula os valores dos index considerando somente o 2 e 3
for(i = 1; i < n; i++){
if(pos_num2 == -1){
if(vet[i] == 2){
pos_num2 = i;
}
else{
index += (n-i-1)*fatorial[n-3];
}
}
else{
if(vet[i] == 3){
pos_num3 = i;
break;
}
else{
index += fatorial[n-3];
}
}
}
//calcula o valor dos index considerando os outros valores de N
int pos = 0;
for(i = 1; i < n; i++){
if(i != pos_num2 && i != pos_num3){
vet[pos] = vet[i];
pos++;
}
}
index += getIndexLexicographically(vet, n-3);
return index;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected fatorial
.type fatorial,@object
.data
.globl fatorial
.p2align 4, 0x0
fatorial:
.quad 1
.quad 1
.quad 2
.quad 6
.quad 24
.quad 120
.quad 720
.quad 5040
.quad 40320
.quad 362880
.quad 3628800
.quad 39916800
.quad 479001600
.quad 6227020800
.quad 87178291200
.quad 1307674368000
.quad 20922789888000
.quad 355687428096000
.quad 6402373705728000
.quad 121645100408832000
.size fatorial, 160
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym fatorial
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__constant__ unsigned long long fatorial[20] = {1, 1, 2, 6, 24, 120, 720, 5040, 40320, 362880, 3628800, 39916800, 479001600, 6227020800, 87178291200, 1307674368000, 20922789888000, 355687428096000, 6402373705728000, 121645100408832000};
/*
__device__
unsigned long long fatorial(int n){
unsigned long long result = 1;
int i;
for(i = n; i > 1; i--){
result *= i;
}
return result;
}*/
//Coloca o elemento da variável pos na primeira posição, e da um shift para a direia nos outros
__device__
void shiftElement(char* dest, int pos){
char temp = dest[pos];
int i;
for(i = 0; i < pos; i++){
dest[pos-i] = dest[pos-i-1];
}
dest[0] = temp;
}
__device__
void getSequenceLexicographically(char* dest, int n, unsigned long long index){
//Cria o vetor primário de tamanho N
int i;
for(i = 0; i < n; i++)
dest[i] = i+4; //Começar do numero 4
//Percorre o vetor
for(i = 0; i < n-1; i++){
//Calcula quantas alterações são possiveis sem alterar o primeiro elemento atual
unsigned long long fat = fatorial[n-i-1];
//Calcula quantas vezes foi possível trocar essa posição
int num_movimentos = index/fat;
if(num_movimentos > 0){
shiftElement(dest, num_movimentos);
//Diminui a quantidade ja calcula do indice
index -= num_movimentos*fat;
}
dest++;
}
}
__device__
void getSequence(char* dest, int n, unsigned long long index){
unsigned int numDeslocamentos2e3 = index/fatorial[n-3];
unsigned int indexResto = index%fatorial[n-3];
unsigned int pos_num2 = 1;
unsigned int pos_num3;
int i;
for(i = 0; numDeslocamentos2e3; i++){
if(numDeslocamentos2e3 >= (n-2-i)){
pos_num2++;
numDeslocamentos2e3 -= (n-2-i);
}
else{
pos_num3 = pos_num2 + 1 + numDeslocamentos2e3;
break;
}
}
if(numDeslocamentos2e3 == 0){
pos_num3 = pos_num2+1;
}
getSequenceLexicographically(dest+3, n-3, indexResto);
dest[0] = (char) 1;
for(i = 1; i < pos_num2; i++){
dest[i] = dest[i+2];
}
dest[pos_num2] = (char) 2;
for(i = pos_num2+1; i < pos_num3; i++){
dest[i] = dest[i+1];
}
dest[pos_num3] = (char) 3;
}
//Pega a quantidade de valores menores que num na variável vet.
__device__
int qtdMenores(char* vet, int num, int n){
int qtd = 0;
int i;
for(i = 0; i < n; i++){
if(vet[i] < num)
qtd++;
}
return qtd;
}
__device__
unsigned long long getIndexLexicographically(char* vet, int n){
unsigned long long index = 0;
int i;
for(i = 0; i < n-1; i++){
index += qtdMenores(vet+i+1, vet[i], n-i-1)*fatorial[n-i-1];
}
return index;
}
__device__
unsigned long long getIndex(char* vet, int n){
unsigned long long index = 0;
int i;
int pos_num2 = -1, pos_num3 = -1;
//calcula os valores dos index considerando somente o 2 e 3
for(i = 1; i < n; i++){
if(pos_num2 == -1){
if(vet[i] == 2){
pos_num2 = i;
}
else{
index += (n-i-1)*fatorial[n-3];
}
}
else{
if(vet[i] == 3){
pos_num3 = i;
break;
}
else{
index += fatorial[n-3];
}
}
}
//calcula o valor dos index considerando os outros valores de N
int pos = 0;
for(i = 1; i < n; i++){
if(i != pos_num2 && i != pos_num3){
vet[pos] = vet[i];
pos++;
}
}
index += getIndexLexicographically(vet, n-3);
return index;
} | .text
.file "EnumaratorSequence.hip"
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB0_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB0_2:
movq __hip_gpubin_handle(%rip), %rdi
movl $fatorial, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $160, %r9d
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end0:
.size __hip_module_ctor, .Lfunc_end0-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB1_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB1_2:
retq
.Lfunc_end1:
.size __hip_module_dtor, .Lfunc_end1-__hip_module_dtor
.cfi_endproc
# -- End function
.type fatorial,@object # @fatorial
.local fatorial
.comm fatorial,160,16
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "fatorial"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym fatorial
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected fatorial
.type fatorial,@object
.data
.globl fatorial
.p2align 4, 0x0
fatorial:
.quad 1
.quad 1
.quad 2
.quad 6
.quad 24
.quad 120
.quad 720
.quad 5040
.quad 40320
.quad 362880
.quad 3628800
.quad 39916800
.quad 479001600
.quad 6227020800
.quad 87178291200
.quad 1307674368000
.quad 20922789888000
.quad 355687428096000
.quad 6402373705728000
.quad 121645100408832000
.size fatorial, 160
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym fatorial
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000285a1_00000000-6_EnumaratorSequence.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12shiftElementPci
.type _Z12shiftElementPci, @function
_Z12shiftElementPci:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z12shiftElementPci, .-_Z12shiftElementPci
.globl _Z28getSequenceLexicographicallyPciy
.type _Z28getSequenceLexicographicallyPciy, @function
_Z28getSequenceLexicographicallyPciy:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z28getSequenceLexicographicallyPciy, .-_Z28getSequenceLexicographicallyPciy
.globl _Z11getSequencePciy
.type _Z11getSequencePciy, @function
_Z11getSequencePciy:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z11getSequencePciy, .-_Z11getSequencePciy
.globl _Z10qtdMenoresPcii
.type _Z10qtdMenoresPcii, @function
_Z10qtdMenoresPcii:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z10qtdMenoresPcii, .-_Z10qtdMenoresPcii
.globl _Z25getIndexLexicographicallyPci
.type _Z25getIndexLexicographicallyPci, @function
_Z25getIndexLexicographicallyPci:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z25getIndexLexicographicallyPci, .-_Z25getIndexLexicographicallyPci
.globl _Z8getIndexPci
.type _Z8getIndexPci, @function
_Z8getIndexPci:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z8getIndexPci, .-_Z8getIndexPci
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "fatorial"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $160, %r9d
movl $0, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8fatorial(%rip), %rsi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL8fatorial
.comm _ZL8fatorial,160,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "EnumaratorSequence.hip"
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB0_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB0_2:
movq __hip_gpubin_handle(%rip), %rdi
movl $fatorial, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $160, %r9d
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end0:
.size __hip_module_ctor, .Lfunc_end0-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB1_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB1_2:
retq
.Lfunc_end1:
.size __hip_module_dtor, .Lfunc_end1-__hip_module_dtor
.cfi_endproc
# -- End function
.type fatorial,@object # @fatorial
.local fatorial
.comm fatorial,160,16
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "fatorial"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym fatorial
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ float mulWithKernel(int x, int y, int kx, int ky, float* input, int width, int height)
{
int px = min(max(x, 0), width - 1);
int py = min(max(y, 0), height - 1);
return D_KERNEL[3 * (ky + 1) + kx + 1] * input[py * width + px];
/* CROP
if (x >= 0 && y >= 0 && x < width && y < height)
{
return D_KERNEL[3 * (ky + 1) + kx + 1] * input[y * width + x];
}
else
{
return 0;
}
*/
}
__global__ void Convolution3x3Single(float* input, float* output, int width, int height)
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
int size = width * height;
if(threadId < size)
{
float result = 0;
int x = threadId % width;
int y = threadId / width;
result += mulWithKernel(x - 1, y - 1, -1, -1, input, width, height);
result += mulWithKernel(x - 1, y , -1, 0, input, width, height);
result += mulWithKernel(x - 1, y + 1, -1, 1, input, width, height);
result += mulWithKernel(x, y - 1, 0, -1, input, width, height);
result += mulWithKernel(x, y , 0, 0, input, width, height);
result += mulWithKernel(x, y + 1, 0, 1, input, width, height);
result += mulWithKernel(x + 1, y - 1, 1, -1, input, width, height);
result += mulWithKernel(x + 1, y , 1, 0, input, width, height);
result += mulWithKernel(x + 1, y + 1, 1, 1, input, width, height);
output[y * width + x] = result;
}
} | code for sm_80
Function : _Z20Convolution3x3SinglePfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0070*/ IMAD R4, R0, c[0x0][0x0], R5 ; /* 0x0000000000047a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fda000bf06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IABS R6, c[0x0][0x170] ; /* 0x00005c0000067a13 */
/* 0x000fe20000000000 */
/*00b0*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*00c0*/ IABS R7, R4 ; /* 0x0000000400077213 */
/* 0x000fe20000000000 */
/*00d0*/ ULDC UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000800 */
/*00e0*/ I2F.RP R0, R6 ; /* 0x0000000600007306 */
/* 0x000e220000209400 */
/*00f0*/ UIADD3 UR4, -UR4, UR6, URZ ; /* 0x0000000604047290 */
/* 0x000fe4000fffe13f */
/*0100*/ UIADD3 UR7, UR5, -0x1, URZ ; /* 0xffffffff05077890 */
/* 0x000fca000fffe03f */
/*0110*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0120*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0130*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0140*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0150*/ IADD3 R5, RZ, -R3, RZ ; /* 0x80000003ff057210 */
/* 0x002fca0007ffe0ff */
/*0160*/ IMAD R5, R5, R6, RZ ; /* 0x0000000605057224 */
/* 0x000fc800078e02ff */
/*0170*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fe200078e0002 */
/*0180*/ MOV R5, R7 ; /* 0x0000000700057202 */
/* 0x000fe40000000f00 */
/*0190*/ LOP3.LUT R2, R4, c[0x0][0x170], RZ, 0x3c, !PT ; /* 0x00005c0004027a12 */
/* 0x000fc600078e3cff */
/*01a0*/ IMAD.HI.U32 R0, R3, R5, RZ ; /* 0x0000000503007227 */
/* 0x000fe200078e00ff */
/*01b0*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc80003f26270 */
/*01c0*/ IADD3 R3, -R0, RZ, RZ ; /* 0x000000ff00037210 */
/* 0x000fca0007ffe1ff */
/*01d0*/ IMAD R3, R6, R3, R5 ; /* 0x0000000306037224 */
/* 0x000fca00078e0205 */
/*01e0*/ ISETP.GT.U32.AND P2, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f44070 */
/*01f0*/ @!P2 IADD3 R3, R3, -R6.reuse, RZ ; /* 0x800000060303a210 */
/* 0x080fe40007ffe0ff */
/*0200*/ @!P2 IADD3 R0, R0, 0x1, RZ ; /* 0x000000010000a810 */
/* 0x000fe40007ffe0ff */
/*0210*/ ISETP.GE.U32.AND P0, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x000fe40003f06070 */
/*0220*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fd60003f45270 */
/*0230*/ @P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100000810 */
/* 0x000fc80007ffe0ff */
/*0240*/ @!P1 IADD3 R0, -R0, RZ, RZ ; /* 0x000000ff00009210 */
/* 0x000fe40007ffe1ff */
/*0250*/ @!P2 LOP3.LUT R0, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff00aa12 */
/* 0x000fc800078e33ff */
/*0260*/ IADD3 R3, -R0.reuse, RZ, RZ ; /* 0x000000ff00037210 */
/* 0x040fe40007ffe1ff */
/*0270*/ IMNMX R5, RZ, R0, !PT ; /* 0x00000000ff057217 */
/* 0x000fe40007800200 */
/*0280*/ IADD3 R8, R0.reuse, 0x1, RZ ; /* 0x0000000100087810 */
/* 0x040fe20007ffe0ff */
/*0290*/ IMAD R3, R3, c[0x0][0x170], R4 ; /* 0x00005c0003037a24 */
/* 0x000fe200078e0204 */
/*02a0*/ IADD3 R4, R0, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ IMNMX R5, R5, UR7, PT ; /* 0x0000000705057c17 */
/* 0x000fe4000b800200 */
/*02c0*/ IADD3 R2, R3, -0x1, RZ ; /* 0xffffffff03027810 */
/* 0x000fc40007ffe0ff */
/*02d0*/ IMNMX R4, RZ, R4, !PT ; /* 0x00000004ff047217 */
/* 0x000fe40007800200 */
/*02e0*/ IMNMX R2, RZ, R2, !PT ; /* 0x00000002ff027217 */
/* 0x000fe40007800200 */
/*02f0*/ IMNMX R6, R4, UR7, PT ; /* 0x0000000704067c17 */
/* 0x000fe4000b800200 */
/*0300*/ IMNMX R7, R2, UR4, PT ; /* 0x0000000402077c17 */
/* 0x000fe2000b800200 */
/*0310*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0320*/ IMNMX R4, RZ, R8, !PT ; /* 0x00000008ff047217 */
/* 0x000fe40007800200 */
/*0330*/ IMNMX R8, RZ, R3, !PT ; /* 0x00000003ff087217 */
/* 0x000fe20007800200 */
/*0340*/ IMAD R15, R6, c[0x0][0x170], R7.reuse ; /* 0x00005c00060f7a24 */
/* 0x100fe200078e0207 */
/*0350*/ IMNMX R4, R4, UR7, PT ; /* 0x0000000704047c17 */
/* 0x000fe2000b800200 */
/*0360*/ IMAD R11, R5, c[0x0][0x170], R7 ; /* 0x00005c00050b7a24 */
/* 0x000fe200078e0207 */
/*0370*/ IMNMX R17, R8, UR4, PT ; /* 0x0000000408117c17 */
/* 0x000fe2000b800200 */
/*0380*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc40000000a00 */
/*0390*/ IMAD.WIDE R14, R15, R2, c[0x0][0x160] ; /* 0x000058000f0e7625 */
/* 0x000fe200078e0202 */
/*03a0*/ IADD3 R8, R3, 0x1, RZ ; /* 0x0000000103087810 */
/* 0x000fc60007ffe0ff */
/*03b0*/ IMAD R13, R4, c[0x0][0x170], R7 ; /* 0x00005c00040d7a24 */
/* 0x000fe400078e0207 */
/*03c0*/ IMAD.WIDE R10, R11, R2.reuse, c[0x0][0x160] ; /* 0x000058000b0a7625 */
/* 0x080fe200078e0202 */
/*03d0*/ LDG.E R7, [R14.64] ; /* 0x000000060e077981 */
/* 0x0000a6000c1e1900 */
/*03e0*/ IMAD R9, R6, c[0x0][0x170], R17 ; /* 0x00005c0006097a24 */
/* 0x000fe400078e0211 */
/*03f0*/ IMAD.WIDE R12, R13, R2, c[0x0][0x160] ; /* 0x000058000d0c7625 */
/* 0x000fe200078e0202 */
/*0400*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000ee2000c1e1900 */
/*0410*/ IMNMX R16, RZ, R8, !PT ; /* 0x00000008ff107217 */
/* 0x000fc40007800200 */
/*0420*/ IMAD R19, R5, c[0x0][0x170], R17.reuse ; /* 0x00005c0005137a24 */
/* 0x100fe400078e0211 */
/*0430*/ IMAD.WIDE R8, R9, R2.reuse, c[0x0][0x160] ; /* 0x0000580009087625 */
/* 0x080fe200078e0202 */
/*0440*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000f22000c1e1900 */
/*0450*/ IMNMX R21, R16, UR4, PT ; /* 0x0000000410157c17 */
/* 0x000fe4000b800200 */
/*0460*/ IMAD R17, R4, c[0x0][0x170], R17 ; /* 0x00005c0004117a24 */
/* 0x000fe400078e0211 */
/*0470*/ IMAD.WIDE R14, R19, R2, c[0x0][0x160] ; /* 0x00005800130e7625 */
/* 0x001fe200078e0202 */
/*0480*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000f66000c1e1900 */
/*0490*/ IMAD R19, R6, c[0x0][0x170], R21 ; /* 0x00005c0006137a24 */
/* 0x000fc400078e0215 */
/*04a0*/ IMAD.WIDE R16, R17, R2.reuse, c[0x0][0x160] ; /* 0x0000580011107625 */
/* 0x080fe200078e0202 */
/*04b0*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000f66000c1e1900 */
/*04c0*/ IMAD R5, R5, c[0x0][0x170], R21.reuse ; /* 0x00005c0005057a24 */
/* 0x100fe400078e0215 */
/*04d0*/ IMAD.WIDE R18, R19, R2, c[0x0][0x160] ; /* 0x0000580013127625 */
/* 0x000fe200078e0202 */
/*04e0*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000f66000c1e1900 */
/*04f0*/ IMAD R21, R4, c[0x0][0x170], R21 ; /* 0x00005c0004157a24 */
/* 0x000fc400078e0215 */
/*0500*/ IMAD.WIDE R4, R5, R2.reuse, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x080fe200078e0202 */
/*0510*/ LDG.E R18, [R18.64] ; /* 0x0000000612127981 */
/* 0x000f66000c1e1900 */
/*0520*/ IMAD.WIDE R20, R21, R2, c[0x0][0x160] ; /* 0x0000580015147625 */
/* 0x000fe400078e0202 */
/*0530*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000f68000c1e1900 */
/*0540*/ LDG.E R20, [R20.64] ; /* 0x0000000614147981 */
/* 0x000f62000c1e1900 */
/*0550*/ IMAD R3, R0, c[0x0][0x170], R3 ; /* 0x00005c0000037a24 */
/* 0x000fc800078e0203 */
/*0560*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fc800078e0202 */
/*0570*/ FFMA R7, R7, c[0x3][0x0], RZ ; /* 0x00c0000007077a23 */
/* 0x004fc800000000ff */
/*0580*/ FFMA R7, R10, c[0x3][0xc], R7 ; /* 0x00c003000a077a23 */
/* 0x008fc80000000007 */
/*0590*/ FFMA R7, R12, c[0x3][0x18], R7 ; /* 0x00c006000c077a23 */
/* 0x010fc80000000007 */
/*05a0*/ FFMA R7, R8, c[0x3][0x4], R7 ; /* 0x00c0010008077a23 */
/* 0x020fc80000000007 */
/*05b0*/ FFMA R7, R14, c[0x3][0x10], R7 ; /* 0x00c004000e077a23 */
/* 0x000fc80000000007 */
/*05c0*/ FFMA R7, R16, c[0x3][0x1c], R7 ; /* 0x00c0070010077a23 */
/* 0x000fc80000000007 */
/*05d0*/ FFMA R7, R18, c[0x3][0x8], R7 ; /* 0x00c0020012077a23 */
/* 0x000fc80000000007 */
/*05e0*/ FFMA R7, R4, c[0x3][0x14], R7 ; /* 0x00c0050004077a23 */
/* 0x000fc80000000007 */
/*05f0*/ FFMA R7, R20, c[0x3][0x20], R7 ; /* 0x00c0080014077a23 */
/* 0x000fca0000000007 */
/*0600*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*0610*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0620*/ BRA 0x620; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ float mulWithKernel(int x, int y, int kx, int ky, float* input, int width, int height)
{
int px = min(max(x, 0), width - 1);
int py = min(max(y, 0), height - 1);
return D_KERNEL[3 * (ky + 1) + kx + 1] * input[py * width + px];
/* CROP
if (x >= 0 && y >= 0 && x < width && y < height)
{
return D_KERNEL[3 * (ky + 1) + kx + 1] * input[y * width + x];
}
else
{
return 0;
}
*/
}
__global__ void Convolution3x3Single(float* input, float* output, int width, int height)
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
int size = width * height;
if(threadId < size)
{
float result = 0;
int x = threadId % width;
int y = threadId / width;
result += mulWithKernel(x - 1, y - 1, -1, -1, input, width, height);
result += mulWithKernel(x - 1, y , -1, 0, input, width, height);
result += mulWithKernel(x - 1, y + 1, -1, 1, input, width, height);
result += mulWithKernel(x, y - 1, 0, -1, input, width, height);
result += mulWithKernel(x, y , 0, 0, input, width, height);
result += mulWithKernel(x, y + 1, 0, 1, input, width, height);
result += mulWithKernel(x + 1, y - 1, 1, -1, input, width, height);
result += mulWithKernel(x + 1, y , 1, 0, input, width, height);
result += mulWithKernel(x + 1, y + 1, 1, 1, input, width, height);
output[y * width + x] = result;
}
} | .file "tmpxft_00124abd_00000000-6_Convolution3x3Single.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13mulWithKerneliiiiPfii
.type _Z13mulWithKerneliiiiPfii, @function
_Z13mulWithKerneliiiiPfii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z13mulWithKerneliiiiPfii, .-_Z13mulWithKerneliiiiPfii
.globl _Z44__device_stub__Z20Convolution3x3SinglePfS_iiPfS_ii
.type _Z44__device_stub__Z20Convolution3x3SinglePfS_iiPfS_ii, @function
_Z44__device_stub__Z20Convolution3x3SinglePfS_iiPfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20Convolution3x3SinglePfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z44__device_stub__Z20Convolution3x3SinglePfS_iiPfS_ii, .-_Z44__device_stub__Z20Convolution3x3SinglePfS_iiPfS_ii
.globl _Z20Convolution3x3SinglePfS_ii
.type _Z20Convolution3x3SinglePfS_ii, @function
_Z20Convolution3x3SinglePfS_ii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z20Convolution3x3SinglePfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z20Convolution3x3SinglePfS_ii, .-_Z20Convolution3x3SinglePfS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20Convolution3x3SinglePfS_ii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "D_KERNEL"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20Convolution3x3SinglePfS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $36, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8D_KERNEL(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL8D_KERNEL
.comm _ZL8D_KERNEL,36,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ float mulWithKernel(int x, int y, int kx, int ky, float* input, int width, int height)
{
int px = min(max(x, 0), width - 1);
int py = min(max(y, 0), height - 1);
return D_KERNEL[3 * (ky + 1) + kx + 1] * input[py * width + px];
/* CROP
if (x >= 0 && y >= 0 && x < width && y < height)
{
return D_KERNEL[3 * (ky + 1) + kx + 1] * input[y * width + x];
}
else
{
return 0;
}
*/
}
__global__ void Convolution3x3Single(float* input, float* output, int width, int height)
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
int size = width * height;
if(threadId < size)
{
float result = 0;
int x = threadId % width;
int y = threadId / width;
result += mulWithKernel(x - 1, y - 1, -1, -1, input, width, height);
result += mulWithKernel(x - 1, y , -1, 0, input, width, height);
result += mulWithKernel(x - 1, y + 1, -1, 1, input, width, height);
result += mulWithKernel(x, y - 1, 0, -1, input, width, height);
result += mulWithKernel(x, y , 0, 0, input, width, height);
result += mulWithKernel(x, y + 1, 0, 1, input, width, height);
result += mulWithKernel(x + 1, y - 1, 1, -1, input, width, height);
result += mulWithKernel(x + 1, y , 1, 0, input, width, height);
result += mulWithKernel(x + 1, y + 1, 1, 1, input, width, height);
output[y * width + x] = result;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ float mulWithKernel(int x, int y, int kx, int ky, float* input, int width, int height)
{
int px = min(max(x, 0), width - 1);
int py = min(max(y, 0), height - 1);
return D_KERNEL[3 * (ky + 1) + kx + 1] * input[py * width + px];
/* CROP
if (x >= 0 && y >= 0 && x < width && y < height)
{
return D_KERNEL[3 * (ky + 1) + kx + 1] * input[y * width + x];
}
else
{
return 0;
}
*/
}
__global__ void Convolution3x3Single(float* input, float* output, int width, int height)
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
int size = width * height;
if(threadId < size)
{
float result = 0;
int x = threadId % width;
int y = threadId / width;
result += mulWithKernel(x - 1, y - 1, -1, -1, input, width, height);
result += mulWithKernel(x - 1, y , -1, 0, input, width, height);
result += mulWithKernel(x - 1, y + 1, -1, 1, input, width, height);
result += mulWithKernel(x, y - 1, 0, -1, input, width, height);
result += mulWithKernel(x, y , 0, 0, input, width, height);
result += mulWithKernel(x, y + 1, 0, 1, input, width, height);
result += mulWithKernel(x + 1, y - 1, 1, -1, input, width, height);
result += mulWithKernel(x + 1, y , 1, 0, input, width, height);
result += mulWithKernel(x + 1, y + 1, 1, 1, input, width, height);
output[y * width + x] = result;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ float mulWithKernel(int x, int y, int kx, int ky, float* input, int width, int height)
{
int px = min(max(x, 0), width - 1);
int py = min(max(y, 0), height - 1);
return D_KERNEL[3 * (ky + 1) + kx + 1] * input[py * width + px];
/* CROP
if (x >= 0 && y >= 0 && x < width && y < height)
{
return D_KERNEL[3 * (ky + 1) + kx + 1] * input[y * width + x];
}
else
{
return 0;
}
*/
}
__global__ void Convolution3x3Single(float* input, float* output, int width, int height)
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
int size = width * height;
if(threadId < size)
{
float result = 0;
int x = threadId % width;
int y = threadId / width;
result += mulWithKernel(x - 1, y - 1, -1, -1, input, width, height);
result += mulWithKernel(x - 1, y , -1, 0, input, width, height);
result += mulWithKernel(x - 1, y + 1, -1, 1, input, width, height);
result += mulWithKernel(x, y - 1, 0, -1, input, width, height);
result += mulWithKernel(x, y , 0, 0, input, width, height);
result += mulWithKernel(x, y + 1, 0, 1, input, width, height);
result += mulWithKernel(x + 1, y - 1, 1, -1, input, width, height);
result += mulWithKernel(x + 1, y , 1, 0, input, width, height);
result += mulWithKernel(x + 1, y + 1, 1, 1, input, width, height);
output[y * width + x] = result;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20Convolution3x3SinglePfS_ii
.globl _Z20Convolution3x3SinglePfS_ii
.p2align 8
.type _Z20Convolution3x3SinglePfS_ii,@function
_Z20Convolution3x3SinglePfS_ii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s5, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s15
s_and_b32 s5, s5, 0xffff
s_add_i32 s4, s4, s14
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_mul_i32 s4, s3, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
s_ashr_i32 s4, s2, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s5, s2, s4
s_add_i32 s3, s3, -1
s_xor_b32 s5, s5, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s5
s_sub_i32 s6, 0, s5
v_xor_b32_e32 v4, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v3, s4, v3
s_add_i32 s4, s2, -1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s6, v0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v0, s5
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v5, s5, v2
v_cmp_le_u32_e32 vcc_lo, s5, v2
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s5, v2
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v3
v_sub_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_mul_lo_u32 v2, v0, s2
v_max_i32_e32 v3, 1, v0
v_max_i32_e32 v4, -1, v0
v_maxmin_i32 v0, v0, 0, s3
v_add_nc_u32_e32 v3, -1, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v4, 1, v4
v_sub_nc_u32_e32 v2, v1, v2
v_mul_lo_u32 v0, v0, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_min_i32_e32 v3, s3, v3
v_min_i32_e32 v4, s3, v4
s_delay_alu instid0(VALU_DEP_4)
v_max_i32_e32 v5, 1, v2
v_max_i32_e32 v7, -1, v2
v_maxmin_i32 v6, v2, 0, s4
v_mul_lo_u32 v9, v3, s2
v_mul_lo_u32 v11, v4, s2
v_add_nc_u32_e32 v3, -1, v5
v_add_nc_u32_e32 v5, 1, v7
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v2, v0, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_min_i32_e32 v7, s4, v3
v_min_i32_e32 v13, s4, v5
v_add_nc_u32_e32 v4, v9, v6
v_add_nc_u32_e32 v6, v11, v6
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v8, v9, v7
v_add_nc_u32_e32 v10, v0, v7
v_add_nc_u32_e32 v14, v9, v13
v_add_nc_u32_e32 v12, v11, v7
v_add_nc_u32_e32 v18, v11, v13
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v11, 31, v10
v_add_nc_u32_e32 v16, v0, v13
v_ashrrev_i32_e32 v13, 31, v12
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_lshlrev_b64 v[10:11], 2, v[10:11]
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v9, vcc_lo
v_add_co_u32 v10, vcc_lo, s0, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s1, v11, vcc_lo
global_load_b32 v0, v[8:9], off
v_add_co_u32 v8, vcc_lo, s0, v12
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v13, vcc_lo
global_load_b32 v12, v[10:11], off
v_add_co_u32 v4, vcc_lo, s0, v4
global_load_b32 v13, v[8:9], off
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_ashrrev_i32_e32 v15, 31, v14
v_add_co_u32 v2, vcc_lo, s0, v2
global_load_b32 v20, v[4:5], off
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v6
v_ashrrev_i32_e32 v17, 31, v16
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v7, vcc_lo
v_lshlrev_b64 v[6:7], 2, v[14:15]
v_ashrrev_i32_e32 v19, 31, v18
s_delay_alu instid0(VALU_DEP_4)
v_lshlrev_b64 v[8:9], 2, v[16:17]
s_clause 0x1
global_load_b32 v14, v[2:3], off
global_load_b32 v15, v[4:5], off
v_add_co_u32 v2, vcc_lo, s0, v6
v_lshlrev_b64 v[10:11], 2, v[18:19]
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v7, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v9, vcc_lo
global_load_b32 v6, v[2:3], off
v_add_co_u32 v2, vcc_lo, s0, v10
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v11, vcc_lo
s_clause 0x1
global_load_b32 v4, v[4:5], off
global_load_b32 v3, v[2:3], off
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, D_KERNEL@rel32@lo+4
s_addc_u32 s1, s1, D_KERNEL@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, D_KERNEL@rel32@lo+16
s_addc_u32 s5, s5, D_KERNEL@rel32@hi+24
s_clause 0x1
s_load_b32 s6, s[0:1], 0x0
s_load_b32 s7, s[4:5], 0x0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, D_KERNEL@rel32@lo+28
s_addc_u32 s1, s1, D_KERNEL@rel32@hi+36
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, D_KERNEL@rel32@lo+8
s_addc_u32 s5, s5, D_KERNEL@rel32@hi+16
s_clause 0x1
s_load_b32 s8, s[0:1], 0x0
s_load_b32 s9, s[4:5], 0x0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, D_KERNEL@rel32@lo+20
s_addc_u32 s1, s1, D_KERNEL@rel32@hi+28
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, D_KERNEL@rel32@lo+32
s_addc_u32 s5, s5, D_KERNEL@rel32@hi+40
s_load_b32 s10, s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt vmcnt(8) lgkmcnt(0)
v_fma_f32 v5, s6, v0, 0
s_load_b32 s6, s[4:5], 0x0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, D_KERNEL@rel32@lo+12
s_addc_u32 s1, s1, D_KERNEL@rel32@hi+20
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, D_KERNEL@rel32@lo+24
s_addc_u32 s5, s5, D_KERNEL@rel32@hi+32
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt vmcnt(7)
v_fmac_f32_e32 v5, s7, v12
s_clause 0x1
s_load_b32 s7, s[0:1], 0x0
s_load_b32 s4, s[4:5], 0x0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, D_KERNEL@rel32@lo+36
s_addc_u32 s1, s1, D_KERNEL@rel32@hi+44
s_waitcnt vmcnt(6)
v_fmac_f32_e32 v5, s8, v13
s_load_b32 s0, s[0:1], 0x0
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(5)
v_fmac_f32_e32 v5, s9, v20
s_waitcnt vmcnt(4)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, s10, v14
s_waitcnt vmcnt(3) lgkmcnt(0)
v_fmac_f32_e32 v5, s6, v15
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, s7, v6
s_waitcnt vmcnt(1)
v_fmac_f32_e32 v5, s4, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v5, s0, v3
global_store_b32 v[0:1], v5, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20Convolution3x3SinglePfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20Convolution3x3SinglePfS_ii, .Lfunc_end0-_Z20Convolution3x3SinglePfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected D_KERNEL
.type D_KERNEL,@object
.section .bss,"aw",@nobits
.globl D_KERNEL
.p2align 4, 0x0
D_KERNEL:
.zero 36
.size D_KERNEL, 36
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym D_KERNEL
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20Convolution3x3SinglePfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20Convolution3x3SinglePfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ float mulWithKernel(int x, int y, int kx, int ky, float* input, int width, int height)
{
int px = min(max(x, 0), width - 1);
int py = min(max(y, 0), height - 1);
return D_KERNEL[3 * (ky + 1) + kx + 1] * input[py * width + px];
/* CROP
if (x >= 0 && y >= 0 && x < width && y < height)
{
return D_KERNEL[3 * (ky + 1) + kx + 1] * input[y * width + x];
}
else
{
return 0;
}
*/
}
__global__ void Convolution3x3Single(float* input, float* output, int width, int height)
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
int size = width * height;
if(threadId < size)
{
float result = 0;
int x = threadId % width;
int y = threadId / width;
result += mulWithKernel(x - 1, y - 1, -1, -1, input, width, height);
result += mulWithKernel(x - 1, y , -1, 0, input, width, height);
result += mulWithKernel(x - 1, y + 1, -1, 1, input, width, height);
result += mulWithKernel(x, y - 1, 0, -1, input, width, height);
result += mulWithKernel(x, y , 0, 0, input, width, height);
result += mulWithKernel(x, y + 1, 0, 1, input, width, height);
result += mulWithKernel(x + 1, y - 1, 1, -1, input, width, height);
result += mulWithKernel(x + 1, y , 1, 0, input, width, height);
result += mulWithKernel(x + 1, y + 1, 1, 1, input, width, height);
output[y * width + x] = result;
}
} | .text
.file "Convolution3x3Single.hip"
.globl _Z35__device_stub__Convolution3x3SinglePfS_ii # -- Begin function _Z35__device_stub__Convolution3x3SinglePfS_ii
.p2align 4, 0x90
.type _Z35__device_stub__Convolution3x3SinglePfS_ii,@function
_Z35__device_stub__Convolution3x3SinglePfS_ii: # @_Z35__device_stub__Convolution3x3SinglePfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20Convolution3x3SinglePfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z35__device_stub__Convolution3x3SinglePfS_ii, .Lfunc_end0-_Z35__device_stub__Convolution3x3SinglePfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20Convolution3x3SinglePfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $D_KERNEL, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $36, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type D_KERNEL,@object # @D_KERNEL
.local D_KERNEL
.comm D_KERNEL,36,16
.type _Z20Convolution3x3SinglePfS_ii,@object # @_Z20Convolution3x3SinglePfS_ii
.section .rodata,"a",@progbits
.globl _Z20Convolution3x3SinglePfS_ii
.p2align 3, 0x0
_Z20Convolution3x3SinglePfS_ii:
.quad _Z35__device_stub__Convolution3x3SinglePfS_ii
.size _Z20Convolution3x3SinglePfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20Convolution3x3SinglePfS_ii"
.size .L__unnamed_1, 31
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "D_KERNEL"
.size .L__unnamed_2, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__Convolution3x3SinglePfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym D_KERNEL
.addrsig_sym _Z20Convolution3x3SinglePfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20Convolution3x3SinglePfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0070*/ IMAD R4, R0, c[0x0][0x0], R5 ; /* 0x0000000000047a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fda000bf06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IABS R6, c[0x0][0x170] ; /* 0x00005c0000067a13 */
/* 0x000fe20000000000 */
/*00b0*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*00c0*/ IABS R7, R4 ; /* 0x0000000400077213 */
/* 0x000fe20000000000 */
/*00d0*/ ULDC UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000800 */
/*00e0*/ I2F.RP R0, R6 ; /* 0x0000000600007306 */
/* 0x000e220000209400 */
/*00f0*/ UIADD3 UR4, -UR4, UR6, URZ ; /* 0x0000000604047290 */
/* 0x000fe4000fffe13f */
/*0100*/ UIADD3 UR7, UR5, -0x1, URZ ; /* 0xffffffff05077890 */
/* 0x000fca000fffe03f */
/*0110*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0120*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0130*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0140*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0150*/ IADD3 R5, RZ, -R3, RZ ; /* 0x80000003ff057210 */
/* 0x002fca0007ffe0ff */
/*0160*/ IMAD R5, R5, R6, RZ ; /* 0x0000000605057224 */
/* 0x000fc800078e02ff */
/*0170*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fe200078e0002 */
/*0180*/ MOV R5, R7 ; /* 0x0000000700057202 */
/* 0x000fe40000000f00 */
/*0190*/ LOP3.LUT R2, R4, c[0x0][0x170], RZ, 0x3c, !PT ; /* 0x00005c0004027a12 */
/* 0x000fc600078e3cff */
/*01a0*/ IMAD.HI.U32 R0, R3, R5, RZ ; /* 0x0000000503007227 */
/* 0x000fe200078e00ff */
/*01b0*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc80003f26270 */
/*01c0*/ IADD3 R3, -R0, RZ, RZ ; /* 0x000000ff00037210 */
/* 0x000fca0007ffe1ff */
/*01d0*/ IMAD R3, R6, R3, R5 ; /* 0x0000000306037224 */
/* 0x000fca00078e0205 */
/*01e0*/ ISETP.GT.U32.AND P2, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f44070 */
/*01f0*/ @!P2 IADD3 R3, R3, -R6.reuse, RZ ; /* 0x800000060303a210 */
/* 0x080fe40007ffe0ff */
/*0200*/ @!P2 IADD3 R0, R0, 0x1, RZ ; /* 0x000000010000a810 */
/* 0x000fe40007ffe0ff */
/*0210*/ ISETP.GE.U32.AND P0, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x000fe40003f06070 */
/*0220*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fd60003f45270 */
/*0230*/ @P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100000810 */
/* 0x000fc80007ffe0ff */
/*0240*/ @!P1 IADD3 R0, -R0, RZ, RZ ; /* 0x000000ff00009210 */
/* 0x000fe40007ffe1ff */
/*0250*/ @!P2 LOP3.LUT R0, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff00aa12 */
/* 0x000fc800078e33ff */
/*0260*/ IADD3 R3, -R0.reuse, RZ, RZ ; /* 0x000000ff00037210 */
/* 0x040fe40007ffe1ff */
/*0270*/ IMNMX R5, RZ, R0, !PT ; /* 0x00000000ff057217 */
/* 0x000fe40007800200 */
/*0280*/ IADD3 R8, R0.reuse, 0x1, RZ ; /* 0x0000000100087810 */
/* 0x040fe20007ffe0ff */
/*0290*/ IMAD R3, R3, c[0x0][0x170], R4 ; /* 0x00005c0003037a24 */
/* 0x000fe200078e0204 */
/*02a0*/ IADD3 R4, R0, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ IMNMX R5, R5, UR7, PT ; /* 0x0000000705057c17 */
/* 0x000fe4000b800200 */
/*02c0*/ IADD3 R2, R3, -0x1, RZ ; /* 0xffffffff03027810 */
/* 0x000fc40007ffe0ff */
/*02d0*/ IMNMX R4, RZ, R4, !PT ; /* 0x00000004ff047217 */
/* 0x000fe40007800200 */
/*02e0*/ IMNMX R2, RZ, R2, !PT ; /* 0x00000002ff027217 */
/* 0x000fe40007800200 */
/*02f0*/ IMNMX R6, R4, UR7, PT ; /* 0x0000000704067c17 */
/* 0x000fe4000b800200 */
/*0300*/ IMNMX R7, R2, UR4, PT ; /* 0x0000000402077c17 */
/* 0x000fe2000b800200 */
/*0310*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0320*/ IMNMX R4, RZ, R8, !PT ; /* 0x00000008ff047217 */
/* 0x000fe40007800200 */
/*0330*/ IMNMX R8, RZ, R3, !PT ; /* 0x00000003ff087217 */
/* 0x000fe20007800200 */
/*0340*/ IMAD R15, R6, c[0x0][0x170], R7.reuse ; /* 0x00005c00060f7a24 */
/* 0x100fe200078e0207 */
/*0350*/ IMNMX R4, R4, UR7, PT ; /* 0x0000000704047c17 */
/* 0x000fe2000b800200 */
/*0360*/ IMAD R11, R5, c[0x0][0x170], R7 ; /* 0x00005c00050b7a24 */
/* 0x000fe200078e0207 */
/*0370*/ IMNMX R17, R8, UR4, PT ; /* 0x0000000408117c17 */
/* 0x000fe2000b800200 */
/*0380*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc40000000a00 */
/*0390*/ IMAD.WIDE R14, R15, R2, c[0x0][0x160] ; /* 0x000058000f0e7625 */
/* 0x000fe200078e0202 */
/*03a0*/ IADD3 R8, R3, 0x1, RZ ; /* 0x0000000103087810 */
/* 0x000fc60007ffe0ff */
/*03b0*/ IMAD R13, R4, c[0x0][0x170], R7 ; /* 0x00005c00040d7a24 */
/* 0x000fe400078e0207 */
/*03c0*/ IMAD.WIDE R10, R11, R2.reuse, c[0x0][0x160] ; /* 0x000058000b0a7625 */
/* 0x080fe200078e0202 */
/*03d0*/ LDG.E R7, [R14.64] ; /* 0x000000060e077981 */
/* 0x0000a6000c1e1900 */
/*03e0*/ IMAD R9, R6, c[0x0][0x170], R17 ; /* 0x00005c0006097a24 */
/* 0x000fe400078e0211 */
/*03f0*/ IMAD.WIDE R12, R13, R2, c[0x0][0x160] ; /* 0x000058000d0c7625 */
/* 0x000fe200078e0202 */
/*0400*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000ee2000c1e1900 */
/*0410*/ IMNMX R16, RZ, R8, !PT ; /* 0x00000008ff107217 */
/* 0x000fc40007800200 */
/*0420*/ IMAD R19, R5, c[0x0][0x170], R17.reuse ; /* 0x00005c0005137a24 */
/* 0x100fe400078e0211 */
/*0430*/ IMAD.WIDE R8, R9, R2.reuse, c[0x0][0x160] ; /* 0x0000580009087625 */
/* 0x080fe200078e0202 */
/*0440*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000f22000c1e1900 */
/*0450*/ IMNMX R21, R16, UR4, PT ; /* 0x0000000410157c17 */
/* 0x000fe4000b800200 */
/*0460*/ IMAD R17, R4, c[0x0][0x170], R17 ; /* 0x00005c0004117a24 */
/* 0x000fe400078e0211 */
/*0470*/ IMAD.WIDE R14, R19, R2, c[0x0][0x160] ; /* 0x00005800130e7625 */
/* 0x001fe200078e0202 */
/*0480*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000f66000c1e1900 */
/*0490*/ IMAD R19, R6, c[0x0][0x170], R21 ; /* 0x00005c0006137a24 */
/* 0x000fc400078e0215 */
/*04a0*/ IMAD.WIDE R16, R17, R2.reuse, c[0x0][0x160] ; /* 0x0000580011107625 */
/* 0x080fe200078e0202 */
/*04b0*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000f66000c1e1900 */
/*04c0*/ IMAD R5, R5, c[0x0][0x170], R21.reuse ; /* 0x00005c0005057a24 */
/* 0x100fe400078e0215 */
/*04d0*/ IMAD.WIDE R18, R19, R2, c[0x0][0x160] ; /* 0x0000580013127625 */
/* 0x000fe200078e0202 */
/*04e0*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000f66000c1e1900 */
/*04f0*/ IMAD R21, R4, c[0x0][0x170], R21 ; /* 0x00005c0004157a24 */
/* 0x000fc400078e0215 */
/*0500*/ IMAD.WIDE R4, R5, R2.reuse, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x080fe200078e0202 */
/*0510*/ LDG.E R18, [R18.64] ; /* 0x0000000612127981 */
/* 0x000f66000c1e1900 */
/*0520*/ IMAD.WIDE R20, R21, R2, c[0x0][0x160] ; /* 0x0000580015147625 */
/* 0x000fe400078e0202 */
/*0530*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000f68000c1e1900 */
/*0540*/ LDG.E R20, [R20.64] ; /* 0x0000000614147981 */
/* 0x000f62000c1e1900 */
/*0550*/ IMAD R3, R0, c[0x0][0x170], R3 ; /* 0x00005c0000037a24 */
/* 0x000fc800078e0203 */
/*0560*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fc800078e0202 */
/*0570*/ FFMA R7, R7, c[0x3][0x0], RZ ; /* 0x00c0000007077a23 */
/* 0x004fc800000000ff */
/*0580*/ FFMA R7, R10, c[0x3][0xc], R7 ; /* 0x00c003000a077a23 */
/* 0x008fc80000000007 */
/*0590*/ FFMA R7, R12, c[0x3][0x18], R7 ; /* 0x00c006000c077a23 */
/* 0x010fc80000000007 */
/*05a0*/ FFMA R7, R8, c[0x3][0x4], R7 ; /* 0x00c0010008077a23 */
/* 0x020fc80000000007 */
/*05b0*/ FFMA R7, R14, c[0x3][0x10], R7 ; /* 0x00c004000e077a23 */
/* 0x000fc80000000007 */
/*05c0*/ FFMA R7, R16, c[0x3][0x1c], R7 ; /* 0x00c0070010077a23 */
/* 0x000fc80000000007 */
/*05d0*/ FFMA R7, R18, c[0x3][0x8], R7 ; /* 0x00c0020012077a23 */
/* 0x000fc80000000007 */
/*05e0*/ FFMA R7, R4, c[0x3][0x14], R7 ; /* 0x00c0050004077a23 */
/* 0x000fc80000000007 */
/*05f0*/ FFMA R7, R20, c[0x3][0x20], R7 ; /* 0x00c0080014077a23 */
/* 0x000fca0000000007 */
/*0600*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*0610*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0620*/ BRA 0x620; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20Convolution3x3SinglePfS_ii
.globl _Z20Convolution3x3SinglePfS_ii
.p2align 8
.type _Z20Convolution3x3SinglePfS_ii,@function
_Z20Convolution3x3SinglePfS_ii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s5, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s15
s_and_b32 s5, s5, 0xffff
s_add_i32 s4, s4, s14
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_mul_i32 s4, s3, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
s_ashr_i32 s4, s2, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s5, s2, s4
s_add_i32 s3, s3, -1
s_xor_b32 s5, s5, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s5
s_sub_i32 s6, 0, s5
v_xor_b32_e32 v4, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v3, s4, v3
s_add_i32 s4, s2, -1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s6, v0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v0, s5
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v5, s5, v2
v_cmp_le_u32_e32 vcc_lo, s5, v2
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s5, v2
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v3
v_sub_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_mul_lo_u32 v2, v0, s2
v_max_i32_e32 v3, 1, v0
v_max_i32_e32 v4, -1, v0
v_maxmin_i32 v0, v0, 0, s3
v_add_nc_u32_e32 v3, -1, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v4, 1, v4
v_sub_nc_u32_e32 v2, v1, v2
v_mul_lo_u32 v0, v0, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_min_i32_e32 v3, s3, v3
v_min_i32_e32 v4, s3, v4
s_delay_alu instid0(VALU_DEP_4)
v_max_i32_e32 v5, 1, v2
v_max_i32_e32 v7, -1, v2
v_maxmin_i32 v6, v2, 0, s4
v_mul_lo_u32 v9, v3, s2
v_mul_lo_u32 v11, v4, s2
v_add_nc_u32_e32 v3, -1, v5
v_add_nc_u32_e32 v5, 1, v7
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v2, v0, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_min_i32_e32 v7, s4, v3
v_min_i32_e32 v13, s4, v5
v_add_nc_u32_e32 v4, v9, v6
v_add_nc_u32_e32 v6, v11, v6
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v8, v9, v7
v_add_nc_u32_e32 v10, v0, v7
v_add_nc_u32_e32 v14, v9, v13
v_add_nc_u32_e32 v12, v11, v7
v_add_nc_u32_e32 v18, v11, v13
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v11, 31, v10
v_add_nc_u32_e32 v16, v0, v13
v_ashrrev_i32_e32 v13, 31, v12
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_lshlrev_b64 v[10:11], 2, v[10:11]
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v9, vcc_lo
v_add_co_u32 v10, vcc_lo, s0, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s1, v11, vcc_lo
global_load_b32 v0, v[8:9], off
v_add_co_u32 v8, vcc_lo, s0, v12
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v13, vcc_lo
global_load_b32 v12, v[10:11], off
v_add_co_u32 v4, vcc_lo, s0, v4
global_load_b32 v13, v[8:9], off
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_ashrrev_i32_e32 v15, 31, v14
v_add_co_u32 v2, vcc_lo, s0, v2
global_load_b32 v20, v[4:5], off
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v6
v_ashrrev_i32_e32 v17, 31, v16
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v7, vcc_lo
v_lshlrev_b64 v[6:7], 2, v[14:15]
v_ashrrev_i32_e32 v19, 31, v18
s_delay_alu instid0(VALU_DEP_4)
v_lshlrev_b64 v[8:9], 2, v[16:17]
s_clause 0x1
global_load_b32 v14, v[2:3], off
global_load_b32 v15, v[4:5], off
v_add_co_u32 v2, vcc_lo, s0, v6
v_lshlrev_b64 v[10:11], 2, v[18:19]
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v7, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v9, vcc_lo
global_load_b32 v6, v[2:3], off
v_add_co_u32 v2, vcc_lo, s0, v10
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v11, vcc_lo
s_clause 0x1
global_load_b32 v4, v[4:5], off
global_load_b32 v3, v[2:3], off
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, D_KERNEL@rel32@lo+4
s_addc_u32 s1, s1, D_KERNEL@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, D_KERNEL@rel32@lo+16
s_addc_u32 s5, s5, D_KERNEL@rel32@hi+24
s_clause 0x1
s_load_b32 s6, s[0:1], 0x0
s_load_b32 s7, s[4:5], 0x0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, D_KERNEL@rel32@lo+28
s_addc_u32 s1, s1, D_KERNEL@rel32@hi+36
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, D_KERNEL@rel32@lo+8
s_addc_u32 s5, s5, D_KERNEL@rel32@hi+16
s_clause 0x1
s_load_b32 s8, s[0:1], 0x0
s_load_b32 s9, s[4:5], 0x0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, D_KERNEL@rel32@lo+20
s_addc_u32 s1, s1, D_KERNEL@rel32@hi+28
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, D_KERNEL@rel32@lo+32
s_addc_u32 s5, s5, D_KERNEL@rel32@hi+40
s_load_b32 s10, s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt vmcnt(8) lgkmcnt(0)
v_fma_f32 v5, s6, v0, 0
s_load_b32 s6, s[4:5], 0x0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, D_KERNEL@rel32@lo+12
s_addc_u32 s1, s1, D_KERNEL@rel32@hi+20
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, D_KERNEL@rel32@lo+24
s_addc_u32 s5, s5, D_KERNEL@rel32@hi+32
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt vmcnt(7)
v_fmac_f32_e32 v5, s7, v12
s_clause 0x1
s_load_b32 s7, s[0:1], 0x0
s_load_b32 s4, s[4:5], 0x0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, D_KERNEL@rel32@lo+36
s_addc_u32 s1, s1, D_KERNEL@rel32@hi+44
s_waitcnt vmcnt(6)
v_fmac_f32_e32 v5, s8, v13
s_load_b32 s0, s[0:1], 0x0
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(5)
v_fmac_f32_e32 v5, s9, v20
s_waitcnt vmcnt(4)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, s10, v14
s_waitcnt vmcnt(3) lgkmcnt(0)
v_fmac_f32_e32 v5, s6, v15
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, s7, v6
s_waitcnt vmcnt(1)
v_fmac_f32_e32 v5, s4, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v5, s0, v3
global_store_b32 v[0:1], v5, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20Convolution3x3SinglePfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20Convolution3x3SinglePfS_ii, .Lfunc_end0-_Z20Convolution3x3SinglePfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected D_KERNEL
.type D_KERNEL,@object
.section .bss,"aw",@nobits
.globl D_KERNEL
.p2align 4, 0x0
D_KERNEL:
.zero 36
.size D_KERNEL, 36
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym D_KERNEL
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20Convolution3x3SinglePfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20Convolution3x3SinglePfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00124abd_00000000-6_Convolution3x3Single.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13mulWithKerneliiiiPfii
.type _Z13mulWithKerneliiiiPfii, @function
_Z13mulWithKerneliiiiPfii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z13mulWithKerneliiiiPfii, .-_Z13mulWithKerneliiiiPfii
.globl _Z44__device_stub__Z20Convolution3x3SinglePfS_iiPfS_ii
.type _Z44__device_stub__Z20Convolution3x3SinglePfS_iiPfS_ii, @function
_Z44__device_stub__Z20Convolution3x3SinglePfS_iiPfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20Convolution3x3SinglePfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z44__device_stub__Z20Convolution3x3SinglePfS_iiPfS_ii, .-_Z44__device_stub__Z20Convolution3x3SinglePfS_iiPfS_ii
.globl _Z20Convolution3x3SinglePfS_ii
.type _Z20Convolution3x3SinglePfS_ii, @function
_Z20Convolution3x3SinglePfS_ii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z20Convolution3x3SinglePfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z20Convolution3x3SinglePfS_ii, .-_Z20Convolution3x3SinglePfS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20Convolution3x3SinglePfS_ii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "D_KERNEL"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20Convolution3x3SinglePfS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $36, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8D_KERNEL(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL8D_KERNEL
.comm _ZL8D_KERNEL,36,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Convolution3x3Single.hip"
.globl _Z35__device_stub__Convolution3x3SinglePfS_ii # -- Begin function _Z35__device_stub__Convolution3x3SinglePfS_ii
.p2align 4, 0x90
.type _Z35__device_stub__Convolution3x3SinglePfS_ii,@function
_Z35__device_stub__Convolution3x3SinglePfS_ii: # @_Z35__device_stub__Convolution3x3SinglePfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20Convolution3x3SinglePfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z35__device_stub__Convolution3x3SinglePfS_ii, .Lfunc_end0-_Z35__device_stub__Convolution3x3SinglePfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20Convolution3x3SinglePfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $D_KERNEL, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $36, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type D_KERNEL,@object # @D_KERNEL
.local D_KERNEL
.comm D_KERNEL,36,16
.type _Z20Convolution3x3SinglePfS_ii,@object # @_Z20Convolution3x3SinglePfS_ii
.section .rodata,"a",@progbits
.globl _Z20Convolution3x3SinglePfS_ii
.p2align 3, 0x0
_Z20Convolution3x3SinglePfS_ii:
.quad _Z35__device_stub__Convolution3x3SinglePfS_ii
.size _Z20Convolution3x3SinglePfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20Convolution3x3SinglePfS_ii"
.size .L__unnamed_1, 31
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "D_KERNEL"
.size .L__unnamed_2, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__Convolution3x3SinglePfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym D_KERNEL
.addrsig_sym _Z20Convolution3x3SinglePfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
// Lets you use the Cuda FFT library
cudaError_t mathWithCuda(float *output, float *input1, float *input2, unsigned int size, int oper);
// Using __global__ to declare function as device code (GPU)
// Do the math inside here:
// Helper function for using CUDA to add vectors in parallel.
__global__ void mathKernel(float *output, float *input1, float *input2, int n, int oper)
{
// Allocate elements to threads
int i = threadIdx.x + blockIdx.x * blockDim.x;
// Avoid access beyond the end of the array
if (i < n)
{
// No for-loop needed, CUDA runtime will thread this
switch (oper)
{
case 1: // Addition
output[i] = input1[i] + input2[i];
break;
case 2: // Subtraction
output[i] = input1[i] - input2[i];
break;
case 3: // Multiplication
output[i] = input1[i] * input2[i];
break;
case 4: // Division
output[i] = input1[i] / input2[i];
break;
// Add more operations here:
case 5:
break;
case 6:
break;
case 7:
break;
default:
return;
}
// Ensure all the data is available
__syncthreads(); // Gives a syntax "error" but this doesn't give build errors
}
} | code for sm_80
Function : _Z10mathKernelPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff007624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0090*/ ISETP.GT.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f04270 */
/*00a0*/ IMAD.WIDE R4, R2, R3, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x000fc800078e0203 */
/*00b0*/ IMAD.WIDE R6, R2, R3, c[0x0][0x170] ; /* 0x00005c0002067625 */
/* 0x000fc800078e0203 */
/*00c0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0203 */
/*00d0*/ @P0 BRA 0x230 ; /* 0x0000015000000947 */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*00f0*/ IMNMX.U32 R0, R0, 0x3, PT ; /* 0x0000000300007817 */
/* 0x000fca0003800000 */
/*0100*/ IMAD.SHL.U32 R0, R0, 0x4, RZ ; /* 0x0000000400007824 */
/* 0x000fc800078e00ff */
/*0110*/ LDC R8, c[0x2][R0] ; /* 0x0080000000087b82 */
/* 0x000e240000000800 */
/*0120*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x001fc80000011408 */
/*0130*/ BRX R8 -0x140 ; /* 0xfffffec008007949 */
/* 0x000fea000383ffff */
/*0140*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea4000c1e1900 */
/*0160*/ FMUL R9, R4, R7 ; /* 0x0000000704097220 */
/* 0x004fca0000400000 */
/*0170*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e2000c101904 */
/*0180*/ BRA 0x370 ; /* 0x000001e000007947 */
/* 0x000fea0003800000 */
/*0190*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea4000c1e1900 */
/*01b0*/ FADD R9, R4, R7 ; /* 0x0000000704097221 */
/* 0x004fca0000000000 */
/*01c0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e2000c101904 */
/*01d0*/ BRA 0x370 ; /* 0x0000019000007947 */
/* 0x000fea0003800000 */
/*01e0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea4000c1e1900 */
/*0200*/ FADD R9, R4, -R7 ; /* 0x8000000704097221 */
/* 0x004fca0000000000 */
/*0210*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e2000c101904 */
/*0220*/ BRA 0x370 ; /* 0x0000014000007947 */
/* 0x000fea0003800000 */
/*0230*/ IADD3 R8, R0, -0x5, RZ ; /* 0xfffffffb00087810 */
/* 0x000fc80007ffe0ff */
/*0240*/ ISETP.GE.U32.AND P0, PT, R8, 0x3, PT ; /* 0x000000030800780c */
/* 0x000fda0003f06070 */
/*0250*/ @!P0 BRA 0x370 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0260*/ ISETP.NE.AND P0, PT, R0, 0x4, PT ; /* 0x000000040000780c */
/* 0x000fda0003f05270 */
/*0270*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0280*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea8000c1e1900 */
/*0290*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1900 */
/*02a0*/ BSSY B0, 0x360 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*02b0*/ MUFU.RCP R0, R7 ; /* 0x0000000700007308 */
/* 0x004e300000001000 */
/*02c0*/ FCHK P0, R4, R7 ; /* 0x0000000704007302 */
/* 0x008e620000000000 */
/*02d0*/ FFMA R9, -R7, R0, 1 ; /* 0x3f80000007097423 */
/* 0x001fc80000000100 */
/*02e0*/ FFMA R9, R0, R9, R0 ; /* 0x0000000900097223 */
/* 0x000fc80000000000 */
/*02f0*/ FFMA R0, R4, R9, RZ ; /* 0x0000000904007223 */
/* 0x000fc800000000ff */
/*0300*/ FFMA R8, -R7, R0, R4 ; /* 0x0000000007087223 */
/* 0x000fc80000000104 */
/*0310*/ FFMA R9, R9, R8, R0 ; /* 0x0000000809097223 */
/* 0x000fe20000000000 */
/*0320*/ @!P0 BRA 0x350 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*0330*/ MOV R0, 0x350 ; /* 0x0000035000007802 */
/* 0x000fe40000000f00 */
/*0340*/ CALL.REL.NOINC 0x390 ; /* 0x0000004000007944 */
/* 0x000fea0003c00000 */
/*0350*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0360*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e4000c101904 */
/*0370*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0380*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0390*/ SHF.R.U32.HI R6, RZ, 0x17, R7.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011607 */
/*03a0*/ BSSY B1, 0x9f0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*03b0*/ SHF.R.U32.HI R5, RZ, 0x17, R4.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011604 */
/*03c0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*03d0*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe200078ec0ff */
/*03e0*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0007 */
/*03f0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*0400*/ IADD3 R12, R6, -0x1, RZ ; /* 0xffffffff060c7810 */
/* 0x000fe40007ffe0ff */
/*0410*/ IADD3 R11, R5, -0x1, RZ ; /* 0xffffffff050b7810 */
/* 0x000fc40007ffe0ff */
/*0420*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*0430*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*0440*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*0450*/ @!P0 BRA 0x5d0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0460*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f1c200 */
/*0470*/ FSETP.GTU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fc80003f3c200 */
/*0480*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0490*/ @P0 BRA 0x9d0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*04a0*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, R8, 0xc8, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c808 */
/*04b0*/ @!P0 BRA 0x9b0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*04c0*/ FSETP.NEU.FTZ.AND P2, PT, |R4|.reuse, +INF , PT ; /* 0x7f8000000400780b */
/* 0x040fe40003f5d200 */
/*04d0*/ FSETP.NEU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe40003f3d200 */
/*04e0*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fd60003f1d200 */
/*04f0*/ @!P1 BRA !P2, 0x9b0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0500*/ LOP3.LUT P2, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000784c0ff */
/*0510*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0520*/ @P1 BRA 0x990 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0530*/ LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000782c0ff */
/*0540*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0550*/ @P0 BRA 0x960 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0560*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*0570*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0580*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*0590*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*05a0*/ @!P0 FFMA R8, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004088823 */
/* 0x000fe400000000ff */
/*05b0*/ @!P1 FFMA R9, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007099823 */
/* 0x000fe200000000ff */
/*05c0*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*05d0*/ LEA R4, R6, 0xc0800000, 0x17 ; /* 0xc080000006047811 */
/* 0x000fe200078eb8ff */
/*05e0*/ BSSY B2, 0x950 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*05f0*/ IADD3 R5, R5, -0x7f, RZ ; /* 0xffffff8105057810 */
/* 0x000fc60007ffe0ff */
/*0600*/ IMAD.IADD R9, R9, 0x1, -R4 ; /* 0x0000000109097824 */
/* 0x000fe400078e0a04 */
/*0610*/ IMAD R8, R5, -0x800000, R8 ; /* 0xff80000005087824 */
/* 0x000fe400078e0208 */
/*0620*/ MUFU.RCP R4, R9 ; /* 0x0000000900047308 */
/* 0x000e220000001000 */
/*0630*/ FADD.FTZ R7, -R9, -RZ ; /* 0x800000ff09077221 */
/* 0x000fc80000010100 */
/*0640*/ FFMA R11, R4, R7, 1 ; /* 0x3f800000040b7423 */
/* 0x001fc80000000007 */
/*0650*/ FFMA R13, R4, R11, R4 ; /* 0x0000000b040d7223 */
/* 0x000fc80000000004 */
/*0660*/ FFMA R4, R8, R13, RZ ; /* 0x0000000d08047223 */
/* 0x000fc800000000ff */
/*0670*/ FFMA R11, R7, R4, R8 ; /* 0x00000004070b7223 */
/* 0x000fc80000000008 */
/*0680*/ FFMA R12, R13, R11, R4 ; /* 0x0000000b0d0c7223 */
/* 0x000fc80000000004 */
/*0690*/ FFMA R8, R7, R12, R8 ; /* 0x0000000c07087223 */
/* 0x000fe20000000008 */
/*06a0*/ IADD3 R7, R5, 0x7f, -R6 ; /* 0x0000007f05077810 */
/* 0x000fc60007ffe806 */
/*06b0*/ FFMA R4, R13, R8, R12 ; /* 0x000000080d047223 */
/* 0x000fe4000000000c */
/*06c0*/ IMAD.IADD R7, R7, 0x1, R10 ; /* 0x0000000107077824 */
/* 0x000fc600078e020a */
/*06d0*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fc80000011604 */
/*06e0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*06f0*/ IMAD.IADD R9, R5, 0x1, R7 ; /* 0x0000000105097824 */
/* 0x000fca00078e0207 */
/*0700*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*0710*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0720*/ @!P0 BRA 0x930 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0730*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*0740*/ @P0 BRA 0x900 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0750*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*0760*/ @P0 BRA 0x940 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0770*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*0780*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*0790*/ @!P0 BRA 0x940 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*07a0*/ FFMA.RZ R5, R13, R8.reuse, R12.reuse ; /* 0x000000080d057223 */
/* 0x180fe2000000c00c */
/*07b0*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f45270 */
/*07c0*/ FFMA.RM R6, R13, R8.reuse, R12.reuse ; /* 0x000000080d067223 */
/* 0x180fe2000000400c */
/*07d0*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*07e0*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*07f0*/ FFMA.RP R5, R13, R8, R12 ; /* 0x000000080d057223 */
/* 0x000fe2000000800c */
/*0800*/ IADD3 R8, R9, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x000fe20007ffe0ff */
/*0810*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*0820*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*0830*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*0840*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*0850*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*0860*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0870*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*0880*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0890*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*08a0*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*08b0*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*08c0*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*08d0*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fca00078e0205 */
/*08e0*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*08f0*/ BRA 0x940 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0900*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*0910*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0920*/ BRA 0x940 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0930*/ IMAD R4, R7, 0x800000, R4 ; /* 0x0080000007047824 */
/* 0x000fe400078e0204 */
/*0940*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0950*/ BRA 0x9e0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0960*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fc800078e4808 */
/*0970*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0980*/ BRA 0x9e0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0990*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fe200078e4808 */
/*09a0*/ BRA 0x9e0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*09b0*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*09c0*/ BRA 0x9e0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*09d0*/ FADD.FTZ R4, R4, R7 ; /* 0x0000000704047221 */
/* 0x000fe40000010000 */
/*09e0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*09f0*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x001fe400078e0004 */
/*0a00*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0a10*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0a20*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff5d004007950 */
/* 0x000fea0003c3ffff */
/*0a30*/ BRA 0xa30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
// Lets you use the Cuda FFT library
cudaError_t mathWithCuda(float *output, float *input1, float *input2, unsigned int size, int oper);
// Using __global__ to declare function as device code (GPU)
// Do the math inside here:
// Helper function for using CUDA to add vectors in parallel.
__global__ void mathKernel(float *output, float *input1, float *input2, int n, int oper)
{
// Allocate elements to threads
int i = threadIdx.x + blockIdx.x * blockDim.x;
// Avoid access beyond the end of the array
if (i < n)
{
// No for-loop needed, CUDA runtime will thread this
switch (oper)
{
case 1: // Addition
output[i] = input1[i] + input2[i];
break;
case 2: // Subtraction
output[i] = input1[i] - input2[i];
break;
case 3: // Multiplication
output[i] = input1[i] * input2[i];
break;
case 4: // Division
output[i] = input1[i] / input2[i];
break;
// Add more operations here:
case 5:
break;
case 6:
break;
case 7:
break;
default:
return;
}
// Ensure all the data is available
__syncthreads(); // Gives a syntax "error" but this doesn't give build errors
}
} | .file "tmpxft_000b258e_00000000-6_mathKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z10mathKernelPfS_S_iiPfS_S_ii
.type _Z36__device_stub__Z10mathKernelPfS_S_iiPfS_S_ii, @function
_Z36__device_stub__Z10mathKernelPfS_S_iiPfS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10mathKernelPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z10mathKernelPfS_S_iiPfS_S_ii, .-_Z36__device_stub__Z10mathKernelPfS_S_iiPfS_S_ii
.globl _Z10mathKernelPfS_S_ii
.type _Z10mathKernelPfS_S_ii, @function
_Z10mathKernelPfS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10mathKernelPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10mathKernelPfS_S_ii, .-_Z10mathKernelPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10mathKernelPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10mathKernelPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
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