system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void __findBoundaries(long long *keys, int *jc, int n, int njc, int shift) {
__shared__ int dbuff[1024];
int i, j, iv, lasti;
int imin = ((int)(32 * ((((long long)n) * blockIdx.x) / (gridDim.x * 32))));
int imax = min(n, ((int)(32 * ((((long long)n) * (blockIdx.x + 1)) / (gridDim.x * 32) + 1))));
int tid = threadIdx.x + blockDim.x * threadIdx.y;
if (tid == 0 && blockIdx.x == 0) {
jc[0] = 0;
}
__syncthreads();
lasti = 0x7fffffff;
for (i = imin; i <= imax; i += blockDim.x * blockDim.y) {
iv = njc;
if (i + tid < imax) {
iv = (int)(keys[i + tid] >> shift);
dbuff[tid] = iv;
}
__syncthreads();
if (i + tid < imax || i + tid == n) {
if (tid > 0) lasti = dbuff[tid - 1];
if (iv > lasti) {
for (j = lasti+1; j <= iv; j++) {
jc[j] = i + tid;
}
}
if (tid == 0) {
lasti = dbuff[blockDim.x * blockDim.y - 1];
}
}
__syncthreads();
}
} | code for sm_80
Function : _Z16__findBoundariesPxPiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR9, SR_CTAID.X ; /* 0x00000000000979c3 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ USHF.R.S32.HI UR7, URZ, 0x1f, UR4 ; /* 0x0000001f3f077899 */
/* 0x000fc60008011404 */
/*0050*/ IMAD.SHL.U32 R4, R4, 0x20, RZ ; /* 0x0000002004047824 */
/* 0x000fe200078e00ff */
/*0060*/ UIMAD.WIDE.U32 UR4, UR9, UR4, URZ ; /* 0x00000004090472a5 */
/* 0x001fe4000f8e003f */
/*0070*/ UIMAD UR8, UR7, UR9, URZ ; /* 0x00000009070872a4 */
/* 0x000fc8000f8e023f */
/*0080*/ UIADD3 UR8, UR5, UR8, URZ ; /* 0x0000000805087290 */
/* 0x000fcc000fffe03f */
/*0090*/ ISETP.NE.U32.AND P0, PT, RZ, UR8, PT ; /* 0x00000008ff007c0c */
/* 0x000fda000bf05070 */
/*00a0*/ @!P0 BRA 0x120 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*00b0*/ MOV R6, 0x100 ; /* 0x0000010000067802 */
/* 0x000fe20000000f00 */
/*00c0*/ UMOV UR6, UR4 ; /* 0x0000000400067c82 */
/* 0x000fe40008000000 */
/*00d0*/ UMOV UR5, UR8 ; /* 0x0000000800057c82 */
/* 0x000fe40008000000 */
/*00e0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*00f0*/ CALL.REL.NOINC 0xbf0 ; /* 0x00000af000007944 */
/* 0x000fea0003c00000 */
/*0100*/ IMAD.MOV.U32 R0, RZ, RZ, R2 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0002 */
/*0110*/ BRA 0x240 ; /* 0x0000012000007947 */
/* 0x000fea0003800000 */
/*0120*/ I2F.U32.RP R0, R4 ; /* 0x0000000400007306 */
/* 0x000e220000209000 */
/*0130*/ IMAD.MOV R5, RZ, RZ, -R4 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a04 */
/*0140*/ ISETP.NE.U32.AND P2, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fcc0003f45070 */
/*0150*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0160*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0170*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0180*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0190*/ IMAD R5, R5, R3, RZ ; /* 0x0000000305057224 */
/* 0x002fc800078e02ff */
/*01a0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*01b0*/ IMAD.HI.U32 R0, R3, UR4, RZ ; /* 0x0000000403007c27 */
/* 0x000fc8000f8e00ff */
/*01c0*/ IMAD.MOV R3, RZ, RZ, -R0 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a00 */
/*01d0*/ IMAD R3, R4, R3, UR4 ; /* 0x0000000404037e24 */
/* 0x000fca000f8e0203 */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x000fda0003f06070 */
/*01f0*/ @P0 IMAD.IADD R3, R3, 0x1, -R4 ; /* 0x0000000103030824 */
/* 0x000fe200078e0a04 */
/*0200*/ @P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100000810 */
/* 0x000fc80007ffe0ff */
/*0210*/ ISETP.GE.U32.AND P1, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x000fda0003f26070 */
/*0220*/ @P1 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100001810 */
/* 0x000fe40007ffe0ff */
/*0230*/ @!P2 LOP3.LUT R0, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff00a212 */
/* 0x000fc800078e33ff */
/*0240*/ UIADD3 UR6, UR9, 0x1, URZ ; /* 0x0000000109067890 */
/* 0x000fe2000fffe03f */
/*0250*/ IMAD.SHL.U32 R0, R0, 0x20, RZ ; /* 0x0000002000007824 */
/* 0x000fe200078e00ff */
/*0260*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000800 */
/*0270*/ UIMAD.WIDE.U32 UR4, UR6, UR4, URZ ; /* 0x00000004060472a5 */
/* 0x000fe4000f8e003f */
/*0280*/ UIMAD UR7, UR7, UR6, URZ ; /* 0x00000006070772a4 */
/* 0x000fc8000f8e023f */
/*0290*/ UIADD3 UR7, UR5, UR7, URZ ; /* 0x0000000705077290 */
/* 0x000fcc000fffe03f */
/*02a0*/ ISETP.NE.U32.AND P0, PT, RZ, UR7, PT ; /* 0x00000007ff007c0c */
/* 0x000fda000bf05070 */
/*02b0*/ @!P0 BRA 0x320 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*02c0*/ MOV R6, 0x310 ; /* 0x0000031000067802 */
/* 0x000fe20000000f00 */
/*02d0*/ UMOV UR6, UR4 ; /* 0x0000000400067c82 */
/* 0x000fe40008000000 */
/*02e0*/ UMOV UR5, UR7 ; /* 0x0000000700057c82 */
/* 0x000fe40008000000 */
/*02f0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0300*/ CALL.REL.NOINC 0xbf0 ; /* 0x000008e000007944 */
/* 0x000fea0003c00000 */
/*0310*/ BRA 0x440 ; /* 0x0000012000007947 */
/* 0x000fea0003800000 */
/*0320*/ I2F.U32.RP R5, R4 ; /* 0x0000000400057306 */
/* 0x000e220000209000 */
/*0330*/ IMAD.MOV R7, RZ, RZ, -R4 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a04 */
/*0340*/ ISETP.NE.U32.AND P2, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f45070 */
/*0350*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fca00078e00ff */
/*0360*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*0370*/ IADD3 R6, R5, 0xffffffe, RZ ; /* 0x0ffffffe05067810 */
/* 0x001fcc0007ffe0ff */
/*0380*/ F2I.FTZ.U32.TRUNC.NTZ R3, R6 ; /* 0x0000000600037305 */
/* 0x000e24000021f000 */
/*0390*/ IMAD R7, R7, R3, RZ ; /* 0x0000000307077224 */
/* 0x001fc800078e02ff */
/*03a0*/ IMAD.HI.U32 R2, R3, R7, R2 ; /* 0x0000000703027227 */
/* 0x000fcc00078e0002 */
/*03b0*/ IMAD.HI.U32 R2, R2, UR4, RZ ; /* 0x0000000402027c27 */
/* 0x000fc8000f8e00ff */
/*03c0*/ IMAD.MOV R3, RZ, RZ, -R2 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a02 */
/*03d0*/ IMAD R3, R4, R3, UR4 ; /* 0x0000000404037e24 */
/* 0x000fca000f8e0203 */
/*03e0*/ ISETP.GE.U32.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x000fda0003f06070 */
/*03f0*/ @P0 IMAD.IADD R3, R3, 0x1, -R4 ; /* 0x0000000103030824 */
/* 0x000fe200078e0a04 */
/*0400*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*0410*/ ISETP.GE.U32.AND P1, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x000fda0003f26070 */
/*0420*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*0430*/ @!P2 LOP3.LUT R2, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff02a212 */
/* 0x000fe400078e33ff */
/*0440*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002200 */
/*0450*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0460*/ LEA R2, R2, 0x20, 0x5 ; /* 0x0000002002027811 */
/* 0x000fe400078e28ff */
/*0470*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e240000002100 */
/*0480*/ IMNMX R5, R2, c[0x0][0x170], PT ; /* 0x00005c0002057a17 */
/* 0x000fc80003800200 */
/*0490*/ ISETP.GT.AND P1, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe20003f24270 */
/*04a0*/ IMAD R3, R3, c[0x0][0x0], R4 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0204 */
/*04b0*/ LOP3.LUT P0, RZ, R3, UR9, RZ, 0xfc, !PT ; /* 0x0000000903ff7c12 */
/* 0x000fda000f80fcff */
/*04c0*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff068624 */
/* 0x000fe400078e00ff */
/*04d0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff078624 */
/* 0x000fca00078e00ff */
/*04e0*/ @!P0 STG.E [R6.64], RZ ; /* 0x000000ff06008986 */
/* 0x0001e8000c101904 */
/*04f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0500*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0510*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x001fe400078e00ff */
/*0520*/ IMAD.MOV.U32 R2, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff027424 */
/* 0x000fc400078e00ff */
/*0530*/ IMAD R7, R7, c[0x0][0x4], RZ ; /* 0x0000010007077a24 */
/* 0x000fe400078e02ff */
/*0540*/ IMAD.IADD R4, R3, 0x1, R0 ; /* 0x0000000103047824 */
/* 0x000fca00078e0200 */
/*0550*/ ISETP.GE.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fda0003f06270 */
/*0560*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff098424 */
/* 0x000fc800078e00ff */
/*0570*/ @!P0 IMAD.WIDE R8, R4, R9, c[0x0][0x160] ; /* 0x0000580004088625 */
/* 0x000fcc00078e0209 */
/*0580*/ @!P0 LDG.E.64 R8, [R8.64] ; /* 0x0000000408088981 */
/* 0x000ea2000c1e1b00 */
/*0590*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0b7624 */
/* 0x000fe200078e00ff */
/*05a0*/ ISETP.GE.AND P2, PT, R4, R5.reuse, PT ; /* 0x000000050400720c */
/* 0x080fe20003f46270 */
/*05b0*/ IMAD.IADD R0, R7, 0x1, R0 ; /* 0x0000000107007824 */
/* 0x000fe200078e0200 */
/*05c0*/ BSSY B1, 0xbc0 ; /* 0x000005f000017945 */
/* 0x000fe80003800000 */
/*05d0*/ ISETP.GT.AND P1, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe40003f24270 */
/*05e0*/ @!P0 SHF.R.S64 R11, R8, c[0x0][0x178], R9 ; /* 0x00005e00080b8a19 */
/* 0x004fca0000001009 */
/*05f0*/ @!P0 STS [R3.X4], R11 ; /* 0x0000000b03008388 */
/* 0x0001e80000004800 */
/*0600*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0610*/ ISETP.NE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f05270 */
/*0620*/ @P0 BRA P2, 0xbb0 ; /* 0x0000058000000947 */
/* 0x002fea0001000000 */
/*0630*/ ISETP.GE.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x001fe20003f06270 */
/*0640*/ BSSY B0, 0xb80 ; /* 0x0000053000007945 */
/* 0x000fd80003800000 */
/*0650*/ @P0 LDS R2, [R3.X4+-0x4] ; /* 0xfffffc0003020984 */
/* 0x000e240000004800 */
/*0660*/ ISETP.GT.AND P0, PT, R11, R2, PT ; /* 0x000000020b00720c */
/* 0x001fda0003f04270 */
/*0670*/ @!P0 BRA 0xb70 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0680*/ IMAD.IADD R6, R11, 0x1, -R2.reuse ; /* 0x000000010b067824 */
/* 0x100fe200078e0a02 */
/*0690*/ LOP3.LUT R8, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff087212 */
/* 0x000fe200078e33ff */
/*06a0*/ BSSY B2, 0x7c0 ; /* 0x0000011000027945 */
/* 0x000fe60003800000 */
/*06b0*/ LOP3.LUT P0, R10, R6, 0x3, RZ, 0xc0, !PT ; /* 0x00000003060a7812 */
/* 0x000fe2000780c0ff */
/*06c0*/ IMAD.IADD R8, R8, 0x1, R11 ; /* 0x0000000108087824 */
/* 0x000fe400078e020b */
/*06d0*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fc600078e0002 */
/*06e0*/ ISETP.GE.U32.AND P2, PT, R8, 0x3, PT ; /* 0x000000030800780c */
/* 0x000fce0003f46070 */
/*06f0*/ @!P0 BRA 0x7b0 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0700*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0710*/ IADD3 R6, R2, 0x1, RZ ; /* 0x0000000102067810 */
/* 0x000fe40007ffe0ff */
/*0720*/ ISETP.NE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fce0003f05270 */
/*0730*/ IMAD.WIDE R8, R6, R9, c[0x0][0x168] ; /* 0x00005a0006087625 */
/* 0x000fca00078e0209 */
/*0740*/ STG.E [R8.64], R4 ; /* 0x0000000408007986 */
/* 0x0001e2000c101904 */
/*0750*/ @!P0 BRA 0x7b0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0760*/ ISETP.NE.AND P0, PT, R10, 0x2, PT ; /* 0x000000020a00780c */
/* 0x000fe20003f05270 */
/*0770*/ STG.E [R8.64+0x4], R4 ; /* 0x0000040408007986 */
/* 0x0003e2000c101904 */
/*0780*/ IADD3 R6, R2, 0x2, RZ ; /* 0x0000000202067810 */
/* 0x000fd60007ffe0ff */
/*0790*/ @P0 STG.E [R8.64+0x8], R4 ; /* 0x0000080408000986 */
/* 0x0003e2000c101904 */
/*07a0*/ @P0 IADD3 R6, R2, 0x3, RZ ; /* 0x0000000302060810 */
/* 0x000fc60007ffe0ff */
/*07b0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*07c0*/ @!P2 BRA 0xb70 ; /* 0x000003a00000a947 */
/* 0x000fea0003800000 */
/*07d0*/ IMAD.IADD R8, R11, 0x1, -R6 ; /* 0x000000010b087824 */
/* 0x003fe200078e0a06 */
/*07e0*/ BSSY B2, 0x9f0 ; /* 0x0000020000027945 */
/* 0x000fe20003800000 */
/*07f0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0800*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0810*/ ISETP.GT.AND P2, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f44270 */
/*0820*/ IADD3 R8, R6, 0x1, RZ ; /* 0x0000000106087810 */
/* 0x000fca0007ffe0ff */
/*0830*/ IMAD.WIDE R8, R8, R9, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fcc00078e0209 */
/*0840*/ @!P2 BRA 0x9e0 ; /* 0x000001900000a947 */
/* 0x000fea0003800000 */
/*0850*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0860*/ IADD3 R15, R11, -0xc, RZ ; /* 0xfffffff40b0f7810 */
/* 0x000fe40007ffe0ff */
/*0870*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe20007ffe0ff */
/*0880*/ STG.E [R8.64], R4 ; /* 0x0000000408007986 */
/* 0x000fe2000c101904 */
/*0890*/ IADD3 R10, P3, R8, 0x40, RZ ; /* 0x00000040080a7810 */
/* 0x000fe40007f7e0ff */
/*08a0*/ ISETP.GE.AND P2, PT, R6, R15, PT ; /* 0x0000000f0600720c */
/* 0x000fe20003f46270 */
/*08b0*/ STG.E [R8.64+0x4], R4 ; /* 0x0000040408007986 */
/* 0x000fe4000c101904 */
/*08c0*/ IMAD.X R13, RZ, RZ, R9, P3 ; /* 0x000000ffff0d7224 */
/* 0x000fe400018e0609 */
/*08d0*/ STG.E [R8.64+0x8], R4 ; /* 0x0000080408007986 */
/* 0x000fe8000c101904 */
/*08e0*/ STG.E [R8.64+0xc], R4 ; /* 0x00000c0408007986 */
/* 0x000fe8000c101904 */
/*08f0*/ STG.E [R8.64+0x10], R4 ; /* 0x0000100408007986 */
/* 0x000fe8000c101904 */
/*0900*/ STG.E [R8.64+0x14], R4 ; /* 0x0000140408007986 */
/* 0x000fe8000c101904 */
/*0910*/ STG.E [R8.64+0x18], R4 ; /* 0x0000180408007986 */
/* 0x000fe8000c101904 */
/*0920*/ STG.E [R8.64+0x1c], R4 ; /* 0x00001c0408007986 */
/* 0x000fe8000c101904 */
/*0930*/ STG.E [R8.64+0x20], R4 ; /* 0x0000200408007986 */
/* 0x000fe8000c101904 */
/*0940*/ STG.E [R8.64+0x24], R4 ; /* 0x0000240408007986 */
/* 0x000fe8000c101904 */
/*0950*/ STG.E [R8.64+0x28], R4 ; /* 0x0000280408007986 */
/* 0x000fe8000c101904 */
/*0960*/ STG.E [R8.64+0x2c], R4 ; /* 0x00002c0408007986 */
/* 0x000fe8000c101904 */
/*0970*/ STG.E [R8.64+0x30], R4 ; /* 0x0000300408007986 */
/* 0x000fe8000c101904 */
/*0980*/ STG.E [R8.64+0x34], R4 ; /* 0x0000340408007986 */
/* 0x000fe8000c101904 */
/*0990*/ STG.E [R8.64+0x38], R4 ; /* 0x0000380408007986 */
/* 0x000fe8000c101904 */
/*09a0*/ STG.E [R8.64+0x3c], R4 ; /* 0x00003c0408007986 */
/* 0x0001e4000c101904 */
/*09b0*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */
/* 0x001fc400078e000a */
/*09c0*/ IMAD.MOV.U32 R9, RZ, RZ, R13 ; /* 0x000000ffff097224 */
/* 0x000fe200078e000d */
/*09d0*/ @!P2 BRA 0x870 ; /* 0xfffffe900000a947 */
/* 0x000fea000383ffff */
/*09e0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*09f0*/ IMAD.IADD R10, R11, 0x1, -R6 ; /* 0x000000010b0a7824 */
/* 0x000fe200078e0a06 */
/*0a00*/ BSSY B2, 0xb20 ; /* 0x0000011000027945 */
/* 0x000fe80003800000 */
/*0a10*/ ISETP.GT.AND P2, PT, R10, 0x4, PT ; /* 0x000000040a00780c */
/* 0x000fda0003f44270 */
/*0a20*/ @!P2 BRA 0xb10 ; /* 0x000000e00000a947 */
/* 0x000fea0003800000 */
/*0a30*/ IADD3 R10, P2, R8, 0x20, RZ ; /* 0x00000020080a7810 */
/* 0x000fe20007f5e0ff */
/*0a40*/ STG.E [R8.64], R4 ; /* 0x0000000408007986 */
/* 0x000fe2000c101904 */
/*0a50*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0a60*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe20007ffe0ff */
/*0a70*/ IMAD.X R13, RZ, RZ, R9, P2 ; /* 0x000000ffff0d7224 */
/* 0x000fe200010e0609 */
/*0a80*/ STG.E [R8.64+0x4], R4 ; /* 0x0000040408007986 */
/* 0x000fe8000c101904 */
/*0a90*/ STG.E [R8.64+0x8], R4 ; /* 0x0000080408007986 */
/* 0x000fe8000c101904 */
/*0aa0*/ STG.E [R8.64+0xc], R4 ; /* 0x00000c0408007986 */
/* 0x000fe8000c101904 */
/*0ab0*/ STG.E [R8.64+0x10], R4 ; /* 0x0000100408007986 */
/* 0x000fe8000c101904 */
/*0ac0*/ STG.E [R8.64+0x14], R4 ; /* 0x0000140408007986 */
/* 0x000fe8000c101904 */
/*0ad0*/ STG.E [R8.64+0x18], R4 ; /* 0x0000180408007986 */
/* 0x000fe8000c101904 */
/*0ae0*/ STG.E [R8.64+0x1c], R4 ; /* 0x00001c0408007986 */
/* 0x0001e4000c101904 */
/*0af0*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */
/* 0x001fc400078e000a */
/*0b00*/ IMAD.MOV.U32 R9, RZ, RZ, R13 ; /* 0x000000ffff097224 */
/* 0x000fe400078e000d */
/*0b10*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0b20*/ ISETP.LT.OR P0, PT, R6, R11, P0 ; /* 0x0000000b0600720c */
/* 0x000fda0000701670 */
/*0b30*/ @P0 STG.E [R8.64], R4 ; /* 0x0000000408000986 */
/* 0x0001e8000c101904 */
/*0b40*/ @P0 STG.E [R8.64+0x4], R4 ; /* 0x0000040408000986 */
/* 0x0001e8000c101904 */
/*0b50*/ @P0 STG.E [R8.64+0x8], R4 ; /* 0x0000080408000986 */
/* 0x0001e8000c101904 */
/*0b60*/ @P0 STG.E [R8.64+0xc], R4 ; /* 0x00000c0408000986 */
/* 0x0001e4000c101904 */
/*0b70*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b80*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0b90*/ @!P0 IMAD.SHL.U32 R4, R7, 0x4, RZ ; /* 0x0000000407048824 */
/* 0x003fca00078e00ff */
/*0ba0*/ @!P0 LDS R2, [R4+-0x4] ; /* 0xfffffc0004028984 */
/* 0x0000640000000800 */
/*0bb0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x001fea0003800000 */
/*0bc0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0bd0*/ @!P1 BRA 0x540 ; /* 0xfffff96000009947 */
/* 0x000fea000383ffff */
/*0be0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bf0*/ IADD3 R3, P1, RZ, -R4.reuse, RZ ; /* 0x80000004ff037210 */
/* 0x080fe40007f3e0ff */
/*0c00*/ ISETP.LE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe4000bf03270 */
/*0c10*/ ISETP.LE.AND P3, PT, RZ, UR5, PT ; /* 0x00000005ff007c0c */
/* 0x000fe2000bf63270 */
/*0c20*/ IMAD.X R5, RZ, RZ, ~UR4, P1 ; /* 0x80000004ff057e24 */
/* 0x000fe200088e06ff */
/*0c30*/ SEL R2, R3, R4, !P0 ; /* 0x0000000403027207 */
/* 0x000fc80004000000 */
/*0c40*/ SEL R3, R5, UR4, !P0 ; /* 0x0000000405037c07 */
/* 0x000fc8000c000000 */
/*0c50*/ I2F.U64.RP R5, R2 ; /* 0x0000000200057312 */
/* 0x000e300000309000 */
/*0c60*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*0c70*/ IADD3 R8, R5, 0x1ffffffe, RZ ; /* 0x1ffffffe05087810 */
/* 0x001fcc0007ffe0ff */
/*0c80*/ F2I.U64.TRUNC R8, R8 ; /* 0x0000000800087311 */
/* 0x000e24000020d800 */
/*0c90*/ IMAD.WIDE.U32 R10, R8, R2, RZ ; /* 0x00000002080a7225 */
/* 0x001fc800078e00ff */
/*0ca0*/ IMAD R7, R8.reuse, R3, R11 ; /* 0x0000000308077224 */
/* 0x040fe200078e020b */
/*0cb0*/ IADD3 R13, P0, RZ, -R10, RZ ; /* 0x8000000aff0d7210 */
/* 0x000fe40007f1e0ff */
/*0cc0*/ MOV R11, R8 ; /* 0x00000008000b7202 */
/* 0x000fe20000000f00 */
/*0cd0*/ IMAD R7, R9, R2, R7 ; /* 0x0000000209077224 */
/* 0x000fe400078e0207 */
/*0ce0*/ IMAD.HI.U32 R10, R8, R13, RZ ; /* 0x0000000d080a7227 */
/* 0x000fc800078e00ff */
/*0cf0*/ IMAD.X R7, RZ, RZ, ~R7, P0 ; /* 0x000000ffff077224 */
/* 0x000fc800000e0e07 */
/*0d00*/ IMAD.WIDE.U32 R10, P0, R8, R7, R10 ; /* 0x00000007080a7225 */
/* 0x000fc8000780000a */
/*0d10*/ IMAD R15, R9.reuse, R7, RZ ; /* 0x00000007090f7224 */
/* 0x040fe400078e02ff */
/*0d20*/ IMAD.HI.U32 R10, P1, R9, R13, R10 ; /* 0x0000000d090a7227 */
/* 0x000fc8000782000a */
/*0d30*/ IMAD.HI.U32 R5, R9, R7, RZ ; /* 0x0000000709057227 */
/* 0x000fe200078e00ff */
/*0d40*/ IADD3 R11, P2, R15, R10, RZ ; /* 0x0000000a0f0b7210 */
/* 0x000fc60007f5e0ff */
/*0d50*/ IMAD.X R5, R5, 0x1, R9, P0 ; /* 0x0000000105057824 */
/* 0x000fe400000e0609 */
/*0d60*/ IMAD.WIDE.U32 R8, R11, R2, RZ ; /* 0x000000020b087225 */
/* 0x000fc600078e00ff */
/*0d70*/ IADD3.X R7, RZ, RZ, R5, P2, P1 ; /* 0x000000ffff077210 */
/* 0x000fe200017e2405 */
/*0d80*/ IMAD R5, R11, R3, R9 ; /* 0x000000030b057224 */
/* 0x000fe200078e0209 */
/*0d90*/ IADD3 R9, P0, RZ, -R8, RZ ; /* 0x80000008ff097210 */
/* 0x000fc60007f1e0ff */
/*0da0*/ IMAD R5, R7, R2, R5 ; /* 0x0000000207057224 */
/* 0x000fe400078e0205 */
/*0db0*/ IMAD.HI.U32 R10, R11, R9, RZ ; /* 0x000000090b0a7227 */
/* 0x000fc800078e00ff */
/*0dc0*/ IMAD.X R8, RZ, RZ, ~R5, P0 ; /* 0x000000ffff087224 */
/* 0x000fe200000e0e05 */
/*0dd0*/ IADD3 R5, P4, RZ, -UR6, RZ ; /* 0x80000006ff057c10 */
/* 0x000fc6000ff9e0ff */
/*0de0*/ IMAD.WIDE.U32 R10, P0, R11, R8, R10 ; /* 0x000000080b0a7225 */
/* 0x000fe2000780000a */
/*0df0*/ SEL R5, R5, UR6, !P3 ; /* 0x0000000605057c07 */
/* 0x000fc6000d800000 */
/*0e00*/ IMAD.X R12, RZ, RZ, ~UR5, P4 ; /* 0x80000005ff0c7e24 */
/* 0x000fe4000a0e06ff */
/*0e10*/ IMAD.HI.U32 R10, P1, R7, R9, R10 ; /* 0x00000009070a7227 */
/* 0x000fc6000782000a */
/*0e20*/ SEL R12, R12, UR5, !P3 ; /* 0x000000050c0c7c07 */
/* 0x000fe2000d800000 */
/*0e30*/ IMAD R9, R7.reuse, R8.reuse, RZ ; /* 0x0000000807097224 */
/* 0x0c0fe200078e02ff */
/*0e40*/ ULOP3.LUT UR5, UR4, UR5, URZ, 0x3c, !UPT ; /* 0x0000000504057292 */
/* 0x000fe2000f8e3c3f */
/*0e50*/ IMAD.HI.U32 R8, R7, R8, RZ ; /* 0x0000000807087227 */
/* 0x000fc600078e00ff */
/*0e60*/ IADD3 R10, P2, R9, R10, RZ ; /* 0x0000000a090a7210 */
/* 0x000fe20007f5e0ff */
/*0e70*/ IMAD.X R7, R8, 0x1, R7, P0 ; /* 0x0000000108077824 */
/* 0x000fe400000e0607 */
/*0e80*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*0e90*/ IMAD.HI.U32 R8, R10, R5, RZ ; /* 0x000000050a087227 */
/* 0x000fe200078e00ff */
/*0ea0*/ IADD3.X R7, RZ, RZ, R7, P2, P1 ; /* 0x000000ffff077210 */
/* 0x000fca00017e2407 */
/*0eb0*/ IMAD.WIDE.U32 R8, R10, R12, R8 ; /* 0x0000000c0a087225 */
/* 0x000fc800078e0008 */
/*0ec0*/ IMAD R11, R7.reuse, R12, RZ ; /* 0x0000000c070b7224 */
/* 0x040fe400078e02ff */
/*0ed0*/ IMAD.HI.U32 R8, P0, R7, R5, R8 ; /* 0x0000000507087227 */
/* 0x000fc80007800008 */
/*0ee0*/ IMAD.HI.U32 R7, R7, R12, RZ ; /* 0x0000000c07077227 */
/* 0x000fe200078e00ff */
/*0ef0*/ IADD3 R11, P1, R11, R8, RZ ; /* 0x000000080b0b7210 */
/* 0x000fc60007f3e0ff */
/*0f00*/ IMAD.X R7, RZ, RZ, R7, P0 ; /* 0x000000ffff077224 */
/* 0x000fe400000e0607 */
/*0f10*/ IMAD.WIDE.U32 R8, R11, R2, RZ ; /* 0x000000020b087225 */
/* 0x000fc800078e00ff */
/*0f20*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fe200008e0607 */
/*0f30*/ IADD3 R13, P1, -R8, R5, RZ ; /* 0x00000005080d7210 */
/* 0x000fe20007f3e1ff */
/*0f40*/ IMAD R9, R11.reuse, R3, R9 ; /* 0x000000030b097224 */
/* 0x040fe200078e0209 */
/*0f50*/ IADD3 R8, R11, 0x1, RZ ; /* 0x000000010b087810 */
/* 0x000fe40007ffe0ff */
/*0f60*/ ISETP.GE.U32.AND P0, PT, R13, R2.reuse, PT ; /* 0x000000020d00720c */
/* 0x080fe20003f06070 */
/*0f70*/ IMAD R7, R7, R2, R9 ; /* 0x0000000207077224 */
/* 0x000fc800078e0209 */
/*0f80*/ IMAD.X R9, R12, 0x1, ~R7, P1 ; /* 0x000000010c097824 */
/* 0x000fe200008e0e07 */
/*0f90*/ IADD3 R5, P1, R13, -R2, RZ ; /* 0x800000020d057210 */
/* 0x000fc80007f3e0ff */
/*0fa0*/ ISETP.GE.U32.AND.EX P0, PT, R9.reuse, R3, PT, P0 ; /* 0x000000030900720c */
/* 0x040fe20003f06100 */
/*0fb0*/ IMAD.X R7, R9, 0x1, ~R3, P1 ; /* 0x0000000109077824 */
/* 0x000fe200008e0e03 */
/*0fc0*/ ISETP.LE.AND P1, PT, RZ, UR5, PT ; /* 0x00000005ff007c0c */
/* 0x000fe4000bf23270 */
/*0fd0*/ SEL R5, R5, R13, P0 ; /* 0x0000000d05057207 */
/* 0x000fe40000000000 */
/*0fe0*/ SEL R7, R7, R9, P0 ; /* 0x0000000907077207 */
/* 0x000fe40000000000 */
/*0ff0*/ SEL R11, R8, R11, P0 ; /* 0x0000000b080b7207 */
/* 0x000fe40000000000 */
/*1000*/ ISETP.GE.U32.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fc40003f06070 */
/*1010*/ IADD3 R2, R11, 0x1, RZ ; /* 0x000000010b027810 */
/* 0x000fe40007ffe0ff */
/*1020*/ ISETP.GE.U32.AND.EX P0, PT, R7, R3, PT, P0 ; /* 0x000000030700720c */
/* 0x000fe20003f06100 */
/*1030*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc600078e00ff */
/*1040*/ SEL R2, R2, R11, P0 ; /* 0x0000000b02027207 */
/* 0x000fe40000000000 */
/*1050*/ ISETP.NE.U32.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05070 */
/*1060*/ IMAD.MOV R3, RZ, RZ, -R2 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a02 */
/*1070*/ ISETP.NE.AND.EX P0, PT, RZ, UR4, PT, P0 ; /* 0x00000004ff007c0c */
/* 0x000fc8000bf05300 */
/*1080*/ SEL R2, R3, R2, !P1 ; /* 0x0000000203027207 */
/* 0x000fc80004800000 */
/*1090*/ SEL R2, R2, 0xffffffff, P0 ; /* 0xffffffff02027807 */
/* 0x000fe20000000000 */
/*10a0*/ RET.REL.NODEC R6 0x0 ; /* 0xffffef5006007950 */
/* 0x000fec0003c3ffff */
/*10b0*/ BRA 0x10b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void __findBoundaries(long long *keys, int *jc, int n, int njc, int shift) {
__shared__ int dbuff[1024];
int i, j, iv, lasti;
int imin = ((int)(32 * ((((long long)n) * blockIdx.x) / (gridDim.x * 32))));
int imax = min(n, ((int)(32 * ((((long long)n) * (blockIdx.x + 1)) / (gridDim.x * 32) + 1))));
int tid = threadIdx.x + blockDim.x * threadIdx.y;
if (tid == 0 && blockIdx.x == 0) {
jc[0] = 0;
}
__syncthreads();
lasti = 0x7fffffff;
for (i = imin; i <= imax; i += blockDim.x * blockDim.y) {
iv = njc;
if (i + tid < imax) {
iv = (int)(keys[i + tid] >> shift);
dbuff[tid] = iv;
}
__syncthreads();
if (i + tid < imax || i + tid == n) {
if (tid > 0) lasti = dbuff[tid - 1];
if (iv > lasti) {
for (j = lasti+1; j <= iv; j++) {
jc[j] = i + tid;
}
}
if (tid == 0) {
lasti = dbuff[blockDim.x * blockDim.y - 1];
}
}
__syncthreads();
}
} | .file "tmpxft_0016a066_00000000-6___findBoundaries.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z16__findBoundariesPxPiiiiPxPiiii
.type _Z41__device_stub__Z16__findBoundariesPxPiiiiPxPiiii, @function
_Z41__device_stub__Z16__findBoundariesPxPiiiiPxPiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16__findBoundariesPxPiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z16__findBoundariesPxPiiiiPxPiiii, .-_Z41__device_stub__Z16__findBoundariesPxPiiiiPxPiiii
.globl _Z16__findBoundariesPxPiiii
.type _Z16__findBoundariesPxPiiii, @function
_Z16__findBoundariesPxPiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16__findBoundariesPxPiiiiPxPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16__findBoundariesPxPiiii, .-_Z16__findBoundariesPxPiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16__findBoundariesPxPiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16__findBoundariesPxPiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void __findBoundaries(long long *keys, int *jc, int n, int njc, int shift) {
__shared__ int dbuff[1024];
int i, j, iv, lasti;
int imin = ((int)(32 * ((((long long)n) * blockIdx.x) / (gridDim.x * 32))));
int imax = min(n, ((int)(32 * ((((long long)n) * (blockIdx.x + 1)) / (gridDim.x * 32) + 1))));
int tid = threadIdx.x + blockDim.x * threadIdx.y;
if (tid == 0 && blockIdx.x == 0) {
jc[0] = 0;
}
__syncthreads();
lasti = 0x7fffffff;
for (i = imin; i <= imax; i += blockDim.x * blockDim.y) {
iv = njc;
if (i + tid < imax) {
iv = (int)(keys[i + tid] >> shift);
dbuff[tid] = iv;
}
__syncthreads();
if (i + tid < imax || i + tid == n) {
if (tid > 0) lasti = dbuff[tid - 1];
if (iv > lasti) {
for (j = lasti+1; j <= iv; j++) {
jc[j] = i + tid;
}
}
if (tid == 0) {
lasti = dbuff[blockDim.x * blockDim.y - 1];
}
}
__syncthreads();
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void __findBoundaries(long long *keys, int *jc, int n, int njc, int shift) {
__shared__ int dbuff[1024];
int i, j, iv, lasti;
int imin = ((int)(32 * ((((long long)n) * blockIdx.x) / (gridDim.x * 32))));
int imax = min(n, ((int)(32 * ((((long long)n) * (blockIdx.x + 1)) / (gridDim.x * 32) + 1))));
int tid = threadIdx.x + blockDim.x * threadIdx.y;
if (tid == 0 && blockIdx.x == 0) {
jc[0] = 0;
}
__syncthreads();
lasti = 0x7fffffff;
for (i = imin; i <= imax; i += blockDim.x * blockDim.y) {
iv = njc;
if (i + tid < imax) {
iv = (int)(keys[i + tid] >> shift);
dbuff[tid] = iv;
}
__syncthreads();
if (i + tid < imax || i + tid == n) {
if (tid > 0) lasti = dbuff[tid - 1];
if (iv > lasti) {
for (j = lasti+1; j <= iv; j++) {
jc[j] = i + tid;
}
}
if (tid == 0) {
lasti = dbuff[blockDim.x * blockDim.y - 1];
}
}
__syncthreads();
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void __findBoundaries(long long *keys, int *jc, int n, int njc, int shift) {
__shared__ int dbuff[1024];
int i, j, iv, lasti;
int imin = ((int)(32 * ((((long long)n) * blockIdx.x) / (gridDim.x * 32))));
int imax = min(n, ((int)(32 * ((((long long)n) * (blockIdx.x + 1)) / (gridDim.x * 32) + 1))));
int tid = threadIdx.x + blockDim.x * threadIdx.y;
if (tid == 0 && blockIdx.x == 0) {
jc[0] = 0;
}
__syncthreads();
lasti = 0x7fffffff;
for (i = imin; i <= imax; i += blockDim.x * blockDim.y) {
iv = njc;
if (i + tid < imax) {
iv = (int)(keys[i + tid] >> shift);
dbuff[tid] = iv;
}
__syncthreads();
if (i + tid < imax || i + tid == n) {
if (tid > 0) lasti = dbuff[tid - 1];
if (iv > lasti) {
for (j = lasti+1; j <= iv; j++) {
jc[j] = i + tid;
}
}
if (tid == 0) {
lasti = dbuff[blockDim.x * blockDim.y - 1];
}
}
__syncthreads();
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16__findBoundariesPxPiiii
.globl _Z16__findBoundariesPxPiiii
.p2align 8
.type _Z16__findBoundariesPxPiiii,@function
_Z16__findBoundariesPxPiiii:
s_clause 0x1
s_load_b32 s10, s[0:1], 0x10
s_load_b32 s6, s[0:1], 0x20
s_mov_b32 s2, 0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s7, s10, 31
s_mul_hi_u32 s3, s10, s15
s_mul_i32 s4, s7, s15
s_mul_i32 s8, s10, s15
s_add_i32 s3, s3, s4
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_lshl_b32 s6, s6, 5
s_cmp_lg_u64 s[2:3], 0
s_cbranch_scc0 .LBB0_23
v_cvt_f32_ubyte0_e32 v1, 0
v_cvt_f32_u32_e32 v2, s6
s_sub_u32 s12, 0, s6
s_subb_u32 s13, 0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v1, v1, 0x4f800000, v2
v_rcp_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x5f7ffffc, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, 0x2f800000, v1
v_trunc_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v1, v2, 0xcf800000, v1
v_cvt_u32_f32_e32 v2, v2
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s9, v2
v_readfirstlane_b32 s11, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s14, s12, s9
s_mul_hi_u32 s17, s12, s11
s_mul_i32 s16, s13, s11
s_add_i32 s14, s17, s14
s_mul_i32 s18, s12, s11
s_add_i32 s14, s14, s16
s_mul_hi_u32 s17, s11, s18
s_mul_hi_u32 s19, s9, s18
s_mul_i32 s16, s9, s18
s_mul_hi_u32 s18, s11, s14
s_mul_i32 s11, s11, s14
s_mul_hi_u32 s20, s9, s14
s_add_u32 s11, s17, s11
s_addc_u32 s17, 0, s18
s_add_u32 s11, s11, s16
s_mul_i32 s14, s9, s14
s_addc_u32 s11, s17, s19
s_addc_u32 s16, s20, 0
s_add_u32 s11, s11, s14
s_addc_u32 s14, 0, s16
v_add_co_u32 v1, s11, v1, s11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s11, 0
s_addc_u32 s9, s9, s14
v_readfirstlane_b32 s11, v1
s_mul_i32 s14, s12, s9
s_delay_alu instid0(VALU_DEP_1)
s_mul_hi_u32 s16, s12, s11
s_mul_i32 s13, s13, s11
s_add_i32 s14, s16, s14
s_mul_i32 s12, s12, s11
s_add_i32 s14, s14, s13
s_mul_hi_u32 s16, s9, s12
s_mul_i32 s17, s9, s12
s_mul_hi_u32 s12, s11, s12
s_mul_hi_u32 s18, s11, s14
s_mul_i32 s11, s11, s14
s_mul_hi_u32 s13, s9, s14
s_add_u32 s11, s12, s11
s_addc_u32 s12, 0, s18
s_add_u32 s11, s11, s17
s_mul_i32 s14, s9, s14
s_addc_u32 s11, s12, s16
s_addc_u32 s12, s13, 0
s_add_u32 s11, s11, s14
s_addc_u32 s12, 0, s12
v_add_co_u32 v1, s11, v1, s11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s11, 0
s_addc_u32 s9, s9, s12
s_ashr_i32 s12, s3, 31
s_add_u32 s16, s8, s12
s_addc_u32 s17, s3, s12
v_readfirstlane_b32 s3, v1
s_mov_b32 s13, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b64 s[16:17], s[16:17], s[12:13]
s_mul_i32 s13, s16, s9
s_delay_alu instid0(VALU_DEP_1)
s_mul_hi_u32 s14, s16, s3
s_mul_hi_u32 s11, s16, s9
s_mul_hi_u32 s19, s17, s3
s_mul_i32 s3, s17, s3
s_add_u32 s13, s14, s13
s_addc_u32 s11, 0, s11
s_mul_hi_u32 s18, s17, s9
s_add_u32 s3, s13, s3
s_mul_i32 s9, s17, s9
s_addc_u32 s3, s11, s19
s_addc_u32 s11, s18, 0
s_add_u32 s3, s3, s9
s_addc_u32 s9, 0, s11
s_mul_i32 s14, s6, s3
s_mul_hi_u32 s13, s6, s3
v_sub_co_u32 v1, s14, s16, s14
s_mul_i32 s9, s6, s9
s_add_u32 s11, s3, 1
s_add_i32 s13, s13, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sub_co_u32 v2, s9, v1, s6
s_add_u32 s16, s3, 2
s_cmp_lg_u32 s14, 0
v_mov_b32_e32 v3, s16
v_cmp_le_u32_e32 vcc_lo, s6, v2
s_subb_u32 s13, s17, s13
s_cmp_lg_u32 s9, 0
s_subb_u32 s9, s13, 0
v_cndmask_b32_e64 v2, 0, -1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s6, v1
s_cmp_eq_u32 s9, 0
v_cndmask_b32_e64 v1, 0, -1, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s13, 0
v_cndmask_b32_e32 v2, -1, v2, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
v_cndmask_b32_e32 v1, -1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_cndmask_b32_e32 v2, s11, v3, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, s3, v2, vcc_lo
v_xor_b32_e32 v1, s12, v1
s_delay_alu instid0(VALU_DEP_1)
v_sub_co_u32 v1, vcc_lo, v1, s12
s_and_not1_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_3
.LBB0_2:
v_cvt_f32_u32_e32 v1, s6
s_sub_i32 s3, 0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s2, v1
s_mul_i32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s3, s2, s3
s_add_i32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s2, s8, s2
s_mul_i32 s3, s2, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s3, s8, s3
s_add_i32 s8, s2, 1
s_sub_i32 s9, s3, s6
s_cmp_ge_u32 s3, s6
s_cselect_b32 s2, s8, s2
s_cselect_b32 s3, s9, s3
s_add_i32 s8, s2, 1
s_cmp_ge_u32 s3, s6
s_mov_b32 s3, 0
s_cselect_b32 s2, s8, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s3
.LBB0_3:
s_add_i32 s8, s15, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_mul_i32 s2, s7, s8
s_mul_hi_u32 s3, s10, s8
s_mul_i32 s7, s10, s8
s_add_i32 s3, s3, s2
s_mov_b32 s2, 0
s_cmp_lg_u64 s[2:3], 0
s_cbranch_scc0 .LBB0_24
v_cvt_f32_ubyte0_e32 v2, 0
v_cvt_f32_u32_e32 v3, s6
s_sub_u32 s11, 0, s6
s_subb_u32 s12, 0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v2, v2, 0x4f800000, v3
v_rcp_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x5f7ffffc, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, 0x2f800000, v2
v_trunc_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v2, v3, 0xcf800000, v2
v_cvt_u32_f32_e32 v3, v3
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s8, v3
v_readfirstlane_b32 s9, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s13, s11, s8
s_mul_hi_u32 s16, s11, s9
s_mul_i32 s14, s12, s9
s_add_i32 s13, s16, s13
s_mul_i32 s17, s11, s9
s_add_i32 s13, s13, s14
s_mul_hi_u32 s16, s9, s17
s_mul_hi_u32 s18, s8, s17
s_mul_i32 s14, s8, s17
s_mul_hi_u32 s17, s9, s13
s_mul_i32 s9, s9, s13
s_mul_hi_u32 s19, s8, s13
s_add_u32 s9, s16, s9
s_addc_u32 s16, 0, s17
s_add_u32 s9, s9, s14
s_mul_i32 s13, s8, s13
s_addc_u32 s9, s16, s18
s_addc_u32 s14, s19, 0
s_add_u32 s9, s9, s13
s_addc_u32 s13, 0, s14
v_add_co_u32 v2, s9, v2, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s9, 0
s_addc_u32 s8, s8, s13
v_readfirstlane_b32 s9, v2
s_mul_i32 s13, s11, s8
s_delay_alu instid0(VALU_DEP_1)
s_mul_hi_u32 s14, s11, s9
s_mul_i32 s12, s12, s9
s_add_i32 s13, s14, s13
s_mul_i32 s11, s11, s9
s_add_i32 s13, s13, s12
s_mul_hi_u32 s14, s8, s11
s_mul_i32 s16, s8, s11
s_mul_hi_u32 s11, s9, s11
s_mul_hi_u32 s17, s9, s13
s_mul_i32 s9, s9, s13
s_mul_hi_u32 s12, s8, s13
s_add_u32 s9, s11, s9
s_addc_u32 s11, 0, s17
s_add_u32 s9, s9, s16
s_mul_i32 s13, s8, s13
s_addc_u32 s9, s11, s14
s_addc_u32 s11, s12, 0
s_add_u32 s9, s9, s13
s_addc_u32 s11, 0, s11
v_add_co_u32 v2, s9, v2, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s9, 0
s_addc_u32 s11, s8, s11
s_ashr_i32 s8, s3, 31
s_add_u32 s12, s7, s8
s_addc_u32 s13, s3, s8
v_readfirstlane_b32 s3, v2
s_mov_b32 s9, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b64 s[12:13], s[12:13], s[8:9]
s_mul_i32 s14, s12, s11
s_delay_alu instid0(VALU_DEP_1)
s_mul_hi_u32 s16, s12, s3
s_mul_hi_u32 s9, s12, s11
s_mul_hi_u32 s18, s13, s3
s_mul_i32 s3, s13, s3
s_add_u32 s14, s16, s14
s_addc_u32 s9, 0, s9
s_mul_hi_u32 s17, s13, s11
s_add_u32 s3, s14, s3
s_mul_i32 s11, s13, s11
s_addc_u32 s3, s9, s18
s_addc_u32 s9, s17, 0
s_add_u32 s3, s3, s11
s_addc_u32 s9, 0, s9
s_mul_i32 s16, s6, s3
s_mul_hi_u32 s14, s6, s3
v_sub_co_u32 v2, s12, s12, s16
s_mul_i32 s9, s6, s9
s_add_u32 s11, s3, 1
s_add_i32 s14, s14, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sub_co_u32 v3, s9, v2, s6
s_add_u32 s16, s3, 2
s_cmp_lg_u32 s12, 0
v_mov_b32_e32 v4, s16
v_cmp_le_u32_e32 vcc_lo, s6, v3
s_subb_u32 s12, s13, s14
s_cmp_lg_u32 s9, 0
s_subb_u32 s9, s12, 0
v_cndmask_b32_e64 v3, 0, -1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s6, v2
s_cmp_eq_u32 s9, 0
v_cndmask_b32_e64 v2, 0, -1, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s12, 0
v_cndmask_b32_e32 v3, -1, v3, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
v_cndmask_b32_e32 v2, -1, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e32 vcc_lo, 0, v3
v_cndmask_b32_e32 v3, s11, v4, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, s3, v3, vcc_lo
v_xor_b32_e32 v2, s8, v2
s_delay_alu instid0(VALU_DEP_1)
v_sub_co_u32 v2, vcc_lo, v2, s8
s_and_not1_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_6
.LBB0_5:
v_cvt_f32_u32_e32 v2, s6
s_sub_i32 s3, 0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s2, v2
s_mul_i32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s3, s2, s3
s_add_i32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s2, s7, s2
s_mul_i32 s3, s2, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s3, s7, s3
s_add_i32 s7, s2, 1
s_sub_i32 s8, s3, s6
s_cmp_ge_u32 s3, s6
s_cselect_b32 s2, s7, s2
s_cselect_b32 s3, s8, s3
s_add_i32 s7, s2, 1
s_cmp_ge_u32 s3, s6
s_mov_b32 s3, 0
s_cselect_b32 s2, s7, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
.LBB0_6:
s_load_b32 s6, s[4:5], 0xc
s_load_b64 s[2:3], s[0:1], 0x8
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s11, s6, 0xffff
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u32_u24 v6, v0, s11, v3
v_or_b32_e32 v0, s15, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_8
v_mov_b32_e32 v0, 0
global_store_b32 v0, v0, s[2:3]
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s6
v_lshlrev_b32_e32 v0, 5, v2
v_lshlrev_b32_e32 v8, 5, v1
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_add_nc_u32_e32 v0, 32, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_i32_e32 v7, s10, v0
v_cmp_gt_i32_e32 vcc_lo, v8, v7
s_cbranch_vccnz .LBB0_22
s_load_b64 s[6:7], s[0:1], 0x14
s_load_b32 s12, s[4:5], 0xc
s_load_b64 s[8:9], s[0:1], 0x0
v_lshlrev_b32_e32 v9, 2, v6
v_cmp_eq_u32_e64 s0, 0, v6
v_cmp_ne_u32_e64 s1, 0, v6
v_bfrev_b32_e32 v0, -2
s_delay_alu instid0(VALU_DEP_4)
v_add_nc_u32_e32 v10, -4, v9
s_waitcnt lgkmcnt(0)
s_lshr_b32 s13, s12, 16
s_add_u32 s12, s2, 4
s_mul_i32 s13, s13, s11
s_addc_u32 s3, s3, 0
s_branch .LBB0_12
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_11:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s14
v_add_nc_u32_e32 v8, s13, v8
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmp_le_i32_e32 vcc_lo, v8, v7
s_cbranch_vccz .LBB0_22
.LBB0_12:
v_dual_mov_b32 v3, s6 :: v_dual_add_nc_u32 v2, v8, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, v2, v7
s_and_saveexec_b32 s14, vcc_lo
s_cbranch_execz .LBB0_14
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[2:3]
v_add_co_u32 v3, s2, s8, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s2, s9, v4, s2
global_load_b64 v[3:4], v[3:4], off
s_waitcnt vmcnt(0)
v_ashrrev_i64 v[3:4], s7, v[3:4]
ds_store_b32 v9, v3
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s14
v_cmp_eq_u32_e64 s2, s10, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s14, s2
s_cbranch_execz .LBB0_11
s_and_saveexec_b32 s2, s1
s_cbranch_execz .LBB0_17
ds_load_b32 v0, v10
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s15, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 v3, v0
s_cbranch_execz .LBB0_20
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s16, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_mov_b32_e32 v1, v0
v_add_co_u32 v4, vcc_lo, s12, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
.LBB0_19:
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, 1, v1
global_store_b32 v[4:5], v2, off
v_add_co_u32 v4, s2, v4, 4
v_add_co_ci_u32_e64 v5, s2, 0, v5, s2
v_cmp_ge_i32_e32 vcc_lo, v1, v3
s_or_b32 s16, vcc_lo, s16
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execnz .LBB0_19
.LBB0_20:
s_or_b32 exec_lo, exec_lo, s15
s_and_saveexec_b32 s2, s0
s_cbranch_execz .LBB0_10
s_load_b32 s15, s[4:5], 0xc
s_waitcnt lgkmcnt(0)
s_lshr_b32 s15, s15, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s11
s_lshl_b32 s15, s15, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s15, s15, -4
v_mov_b32_e32 v0, s15
ds_load_b32 v0, v0
s_branch .LBB0_10
.LBB0_22:
s_endpgm
.LBB0_23:
s_branch .LBB0_2
.LBB0_24:
s_branch .LBB0_5
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16__findBoundariesPxPiiii
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 21
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16__findBoundariesPxPiiii, .Lfunc_end0-_Z16__findBoundariesPxPiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16__findBoundariesPxPiiii
.private_segment_fixed_size: 0
.sgpr_count: 23
.sgpr_spill_count: 0
.symbol: _Z16__findBoundariesPxPiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void __findBoundaries(long long *keys, int *jc, int n, int njc, int shift) {
__shared__ int dbuff[1024];
int i, j, iv, lasti;
int imin = ((int)(32 * ((((long long)n) * blockIdx.x) / (gridDim.x * 32))));
int imax = min(n, ((int)(32 * ((((long long)n) * (blockIdx.x + 1)) / (gridDim.x * 32) + 1))));
int tid = threadIdx.x + blockDim.x * threadIdx.y;
if (tid == 0 && blockIdx.x == 0) {
jc[0] = 0;
}
__syncthreads();
lasti = 0x7fffffff;
for (i = imin; i <= imax; i += blockDim.x * blockDim.y) {
iv = njc;
if (i + tid < imax) {
iv = (int)(keys[i + tid] >> shift);
dbuff[tid] = iv;
}
__syncthreads();
if (i + tid < imax || i + tid == n) {
if (tid > 0) lasti = dbuff[tid - 1];
if (iv > lasti) {
for (j = lasti+1; j <= iv; j++) {
jc[j] = i + tid;
}
}
if (tid == 0) {
lasti = dbuff[blockDim.x * blockDim.y - 1];
}
}
__syncthreads();
}
} | .text
.file "__findBoundaries.hip"
.globl _Z31__device_stub____findBoundariesPxPiiii # -- Begin function _Z31__device_stub____findBoundariesPxPiiii
.p2align 4, 0x90
.type _Z31__device_stub____findBoundariesPxPiiii,@function
_Z31__device_stub____findBoundariesPxPiiii: # @_Z31__device_stub____findBoundariesPxPiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16__findBoundariesPxPiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub____findBoundariesPxPiiii, .Lfunc_end0-_Z31__device_stub____findBoundariesPxPiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16__findBoundariesPxPiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16__findBoundariesPxPiiii,@object # @_Z16__findBoundariesPxPiiii
.section .rodata,"a",@progbits
.globl _Z16__findBoundariesPxPiiii
.p2align 3, 0x0
_Z16__findBoundariesPxPiiii:
.quad _Z31__device_stub____findBoundariesPxPiiii
.size _Z16__findBoundariesPxPiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16__findBoundariesPxPiiii"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub____findBoundariesPxPiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16__findBoundariesPxPiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016a066_00000000-6___findBoundaries.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z16__findBoundariesPxPiiiiPxPiiii
.type _Z41__device_stub__Z16__findBoundariesPxPiiiiPxPiiii, @function
_Z41__device_stub__Z16__findBoundariesPxPiiiiPxPiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16__findBoundariesPxPiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z16__findBoundariesPxPiiiiPxPiiii, .-_Z41__device_stub__Z16__findBoundariesPxPiiiiPxPiiii
.globl _Z16__findBoundariesPxPiiii
.type _Z16__findBoundariesPxPiiii, @function
_Z16__findBoundariesPxPiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16__findBoundariesPxPiiiiPxPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16__findBoundariesPxPiiii, .-_Z16__findBoundariesPxPiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16__findBoundariesPxPiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16__findBoundariesPxPiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "__findBoundaries.hip"
.globl _Z31__device_stub____findBoundariesPxPiiii # -- Begin function _Z31__device_stub____findBoundariesPxPiiii
.p2align 4, 0x90
.type _Z31__device_stub____findBoundariesPxPiiii,@function
_Z31__device_stub____findBoundariesPxPiiii: # @_Z31__device_stub____findBoundariesPxPiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16__findBoundariesPxPiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub____findBoundariesPxPiiii, .Lfunc_end0-_Z31__device_stub____findBoundariesPxPiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16__findBoundariesPxPiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16__findBoundariesPxPiiii,@object # @_Z16__findBoundariesPxPiiii
.section .rodata,"a",@progbits
.globl _Z16__findBoundariesPxPiiii
.p2align 3, 0x0
_Z16__findBoundariesPxPiiii:
.quad _Z31__device_stub____findBoundariesPxPiiii
.size _Z16__findBoundariesPxPiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16__findBoundariesPxPiiii"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub____findBoundariesPxPiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16__findBoundariesPxPiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __device__ volatile int uc = 1;
__device__ volatile unsigned int counter = 0;
__device__ volatile unsigned int cnt = 1;
__global__ void histogram(int *d_input, int* d_bin, int M, int N, int BIN_COUNT)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id < M*N) {
int bid = d_input[id] % BIN_COUNT;
atomicAdd(&(d_bin[bid]), 1);
}
}
__global__ void updateBC(int* d_input, int M, int N)
{
int old = atomicAdd((int *)(&uc), 1);
if (N==1 || M==1) {
int mx = (N < M)? M:N;
if (old <= mx) {
d_input[old] = 1;
}
} else if (old <= 2*(N+M) - 4) {
int id;
if (old <= N) {
id = old;
} else if (old <= N+M-2) {
id = 1+N*(old-N);
} else if (old <= N+2*(M-2)) {
id = N+(old-(N+M-2))*N;
} else {
id = N*(M-1) + old-(N+2*(M-2));
}
d_input[id-1] = 1;
}
if (old == blockDim.x*gridDim.x*blockDim.y*gridDim.y) {
uc = 1;
}
}
__global__ void stencil(int* d_input, const int M, const int N)
{
int old = atomicInc((unsigned int*)(&counter), 1<<30);
const int max = (N-2)*(M-2);
if (old < max) {
int i = old % (N-2);
int j = old / (N-2);
int id = N*(j+1)+i+1;
int sum = 0.2 * (d_input[id]+d_input[id+1]+d_input[id-1]+d_input[id+N]+d_input[id-N]);
atomicInc((unsigned int*)(&cnt), 1<<30);
while (cnt < max);
d_input[id] = sum;
if (old+1 == max) {
cnt = 1;
}
}
if (old+1 == blockDim.x*gridDim.x*blockDim.y*gridDim.y) {
counter = 0;
}
} | code for sm_80
Function : _Z7stencilPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; /* 0x40000000ff077424 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff027624 */
/* 0x000fe400078e00ff */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff037624 */
/* 0x000fca00078e00ff */
/*0050*/ ATOMG.E.INC.STRONG.GPU PT, R0, [R2.64], R7 ; /* 0x00000007020079a8 */
/* 0x000ea200099ee1c8 */
/*0060*/ IMAD.MOV.U32 R11, RZ, RZ, 0x2 ; /* 0x00000002ff0b7424 */
/* 0x000fe200078e00ff */
/*0070*/ BSSY B0, 0x480 ; /* 0x0000040000007945 */
/* 0x000fe80003800000 */
/*0080*/ IADD3 R5, -R11.reuse, c[0x0][0x168], RZ ; /* 0x00005a000b057a10 */
/* 0x040fe40007ffe1ff */
/*0090*/ IADD3 R11, -R11, c[0x0][0x16c], RZ ; /* 0x00005b000b0b7a10 */
/* 0x000fca0007ffe1ff */
/*00a0*/ IMAD R5, R5, R11, RZ ; /* 0x0000000b05057224 */
/* 0x000fca00078e02ff */
/*00b0*/ ISETP.GE.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x004fda0003f06270 */
/*00c0*/ @P0 BRA 0x470 ; /* 0x000003a000000947 */
/* 0x000fea0003800000 */
/*00d0*/ IABS R13, R11.reuse ; /* 0x0000000b000d7213 */
/* 0x080fe40000000000 */
/*00e0*/ IABS R10, R0 ; /* 0x00000000000a7213 */
/* 0x000fe40000000000 */
/*00f0*/ I2F.RP R4, R13 ; /* 0x0000000d00047306 */
/* 0x000e220000209400 */
/*0100*/ IABS R12, R11 ; /* 0x0000000b000c7213 */
/* 0x000fce0000000000 */
/*0110*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0120*/ IADD3 R8, R4, 0xffffffe, RZ ; /* 0x0ffffffe04087810 */
/* 0x001fe40007ffe0ff */
/*0130*/ IADD3 R4, RZ, -R12, RZ ; /* 0x8000000cff047210 */
/* 0x000fc80007ffe0ff */
/*0140*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000064000021f000 */
/*0150*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fe400078e00ff */
/*0160*/ IMAD.MOV R6, RZ, RZ, -R9 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a09 */
/*0170*/ IMAD R15, R6, R13, RZ ; /* 0x0000000d060f7224 */
/* 0x000fe400078e02ff */
/*0180*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000a */
/*0190*/ IMAD.HI.U32 R9, R9, R15, R8 ; /* 0x0000000f09097227 */
/* 0x000fc800078e0008 */
/*01a0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe400078e00ff */
/*01b0*/ IMAD.HI.U32 R9, R9, R6, RZ ; /* 0x0000000609097227 */
/* 0x000fc800078e00ff */
/*01c0*/ IMAD R4, R9, R4, R6 ; /* 0x0000000409047224 */
/* 0x000fca00078e0206 */
/*01d0*/ ISETP.GT.U32.AND P2, PT, R13, R4, PT ; /* 0x000000040d00720c */
/* 0x000fda0003f44070 */
/*01e0*/ @!P2 IMAD.IADD R4, R4, 0x1, -R13 ; /* 0x000000010404a824 */
/* 0x000fe200078e0a0d */
/*01f0*/ @!P2 IADD3 R9, R9, 0x1, RZ ; /* 0x000000010909a810 */
/* 0x000fe40007ffe0ff */
/*0200*/ ISETP.NE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f45270 */
/*0210*/ ISETP.GE.U32.AND P0, PT, R4, R13, PT ; /* 0x0000000d0400720c */
/* 0x000fe40003f06070 */
/*0220*/ LOP3.LUT R4, R0, R11, RZ, 0x3c, !PT ; /* 0x0000000b00047212 */
/* 0x000fc800078e3cff */
/*0230*/ ISETP.GE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fce0003f26270 */
/*0240*/ @P0 IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109090810 */
/* 0x000fcc0007ffe0ff */
/*0250*/ @!P1 IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff099224 */
/* 0x000fe200078e0a09 */
/*0260*/ @!P2 LOP3.LUT R9, RZ, R11, RZ, 0x33, !PT ; /* 0x0000000bff09a212 */
/* 0x000fc800078e33ff */
/*0270*/ IADD3 R4, R9, 0x1, RZ ; /* 0x0000000109047810 */
/* 0x000fe20007ffe0ff */
/*0280*/ IMAD.MOV R6, RZ, RZ, -R9 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a09 */
/*0290*/ IMAD R11, R11, R6, R0 ; /* 0x000000060b0b7224 */
/* 0x000fc800078e0200 */
/*02a0*/ IMAD R4, R4, c[0x0][0x16c], R11 ; /* 0x00005b0004047a24 */
/* 0x000fc800078e020b */
/*02b0*/ IMAD.WIDE R8, R4.reuse, R15, c[0x0][0x160] ; /* 0x0000580004087625 */
/* 0x040fe200078e020f */
/*02c0*/ IADD3 R6, R4, 0x1, RZ ; /* 0x0000000104067810 */
/* 0x000fc80007ffe0ff */
/*02d0*/ IADD3 R14, R6.reuse, -c[0x0][0x16c], RZ ; /* 0x80005b00060e7a10 */
/* 0x040fe20007ffe0ff */
/*02e0*/ IMAD.WIDE R10, R6, R15, c[0x0][0x160] ; /* 0x00005800060a7625 */
/* 0x000fe200078e020f */
/*02f0*/ LDG.E R4, [R8.64+0x8] ; /* 0x0000080808047981 */
/* 0x000ea8000c1e1900 */
/*0300*/ LDG.E R17, [R8.64+0x4] ; /* 0x0000040808117981 */
/* 0x000ea2000c1e1900 */
/*0310*/ IMAD.WIDE R12, R15, c[0x0][0x16c], R10 ; /* 0x00005b000f0c7a25 */
/* 0x000fc600078e020a */
/*0320*/ LDG.E R6, [R8.64] ; /* 0x0000000808067981 */
/* 0x000ea2000c1e1900 */
/*0330*/ IMAD.WIDE R14, R14, R15, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fc600078e020f */
/*0340*/ LDG.E R13, [R12.64] ; /* 0x000000080c0d7981 */
/* 0x000ee8000c1e1900 */
/*0350*/ LDG.E R14, [R14.64] ; /* 0x000000080e0e7981 */
/* 0x000ee2000c1e1900 */
/*0360*/ MOV R10, c[0x4][0x10] ; /* 0x01000400000a7a02 */
/* 0x000fe20000000f00 */
/*0370*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff0b7624 */
/* 0x000fca00078e00ff */
/*0380*/ RED.E.INC.STRONG.GPU [R10.64], R7 ; /* 0x000000070a00798e */
/* 0x0001e2000d90e188 */
/*0390*/ IADD3 R4, R6, R4, R17 ; /* 0x0000000406047210 */
/* 0x004fc80007ffe011 */
/*03a0*/ IADD3 R4, R14, R4, R13 ; /* 0x000000040e047210 */
/* 0x008fc80007ffe00d */
/*03b0*/ I2F.F64 R16, R4 ; /* 0x0000000400107312 */
/* 0x000e640000201c00 */
/*03c0*/ DMUL R16, R16, c[0x2][0x0] ; /* 0x0080000010107a28 */
/* 0x002e540000000000 */
/*03d0*/ F2I.F64.TRUNC R17, R16 ; /* 0x0000001000117311 */
/* 0x002064000030d100 */
/*03e0*/ LDG.E.STRONG.SYS R4, [R10.64] ; /* 0x000000080a047981 */
/* 0x000ea2000c1f5900 */
/*03f0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0400*/ ISETP.GE.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x004fda0003f06070 */
/*0410*/ @!P0 BRA 0x3e0 ; /* 0xffffffc000008947 */
/* 0x000fea000383ffff */
/*0420*/ IADD3 R4, R0, 0x1, RZ ; /* 0x0000000100047810 */
/* 0x000fe20007ffe0ff */
/*0430*/ STG.E [R8.64+0x4], R17 ; /* 0x0000041108007986 */
/* 0x0023e6000c101908 */
/*0440*/ ISETP.NE.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fda0003f05270 */
/*0450*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff058424 */
/* 0x000fca00078e00ff */
/*0460*/ @!P0 STG.E.STRONG.SYS [R10.64], R5 ; /* 0x000000050a008986 */
/* 0x0003e4000c115908 */
/*0470*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0480*/ ULDC UR6, c[0x0][0xc] ; /* 0x0000030000067ab9 */
/* 0x000fe20000000800 */
/*0490*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*04a0*/ ULDC.64 UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000a00 */
/*04b0*/ UIMAD UR4, UR4, UR6, URZ ; /* 0x00000006040472a4 */
/* 0x000fc8000f8e023f */
/*04c0*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fc6000f8e023f */
/*04d0*/ ULDC UR5, c[0x0][0x10] ; /* 0x0000040000057ab9 */
/* 0x000fe40000000800 */
/*04e0*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fcc000f8e023f */
/*04f0*/ ISETP.NE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf05270 */
/*0500*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0510*/ STG.E.STRONG.SYS [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c115908 */
/*0520*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0530*/ BRA 0x530; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8updateBCPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_LANEID ; /* 0x0000000000037919 */
/* 0x000e220000000000 */
/*0020*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*0030*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x4][0x0] ; /* 0x01000000ff027624 */
/* 0x000fe200078e00ff */
/*0040*/ FLO.U32 R4, UR4 ; /* 0x0000000400047d00 */
/* 0x000e2200080e0000 */
/*0050*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fce0000000a00 */
/*0060*/ POPC R5, UR4 ; /* 0x0000000400057d09 */
/* 0x000e620008000000 */
/*0070*/ ISETP.EQ.U32.AND P0, PT, R4, R3, PT ; /* 0x000000030400720c */
/* 0x001fe20003f02070 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x4][0x4] ; /* 0x01000100ff037624 */
/* 0x000fd800078e00ff */
/*0090*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R5, [R2.64], R5 ; /* 0x00000005020509a8 */
/* 0x002ea200081ee1c8 */
/*00a0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fe200078e00ff */
/*00b0*/ BSSY B0, 0x390 ; /* 0x000002d000007945 */
/* 0x000fe40003800000 */
/*00c0*/ S2R R6, SR_LTMASK ; /* 0x0000000000067919 */
/* 0x000e240000003900 */
/*00d0*/ ISETP.NE.AND P0, PT, R11, c[0x0][0x16c], PT ; /* 0x00005b000b007a0c */
/* 0x000fc80003f05270 */
/*00e0*/ ISETP.EQ.OR P0, PT, R11, c[0x0][0x168], !P0 ; /* 0x00005a000b007a0c */
/* 0x000fe40004702670 */
/*00f0*/ LOP3.LUT R6, R6, UR4, RZ, 0xc0, !PT ; /* 0x0000000406067c12 */
/* 0x001fc8000f8ec0ff */
/*0100*/ POPC R7, R6 ; /* 0x0000000600077309 */
/* 0x000e220000000000 */
/*0110*/ SHFL.IDX PT, R0, R5, R4, 0x1f ; /* 0x00001f0405007589 */
/* 0x004e2400000e0000 */
/*0120*/ IMAD.IADD R0, R0, 0x1, R7 ; /* 0x0000000100007824 */
/* 0x001fc800078e0207 */
/*0130*/ @P0 BRA 0x310 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0140*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff067624 */
/* 0x000fca00078e00ff */
/*0150*/ IADD3 R4, R6, c[0x0][0x168], RZ ; /* 0x00005a0006047a10 */
/* 0x000fc80007ffe0ff */
/*0160*/ LEA R5, R4, 0xfffffffc, 0x1 ; /* 0xfffffffc04057811 */
/* 0x000fc800078e08ff */
/*0170*/ ISETP.GT.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fda0003f04270 */
/*0180*/ @P0 BRA 0x380 ; /* 0x000001f000000947 */
/* 0x000fea0003800000 */
/*0190*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fe20003f04270 */
/*01a0*/ BSSY B1, 0x2d0 ; /* 0x0000012000017945 */
/* 0x000fe20003800000 */
/*01b0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.MOV.U32 R5, RZ, RZ, R0 ; /* 0x000000ffff057224 */
/* 0x000fd200078e0000 */
/*01d0*/ @!P0 BRA 0x2c0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*01e0*/ IADD3 R7, R4, -0x2, RZ ; /* 0xfffffffe04077810 */
/* 0x000fc80007ffe0ff */
/*01f0*/ ISETP.GT.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fda0003f04270 */
/*0200*/ @!P0 IADD3 R5, R0, -c[0x0][0x16c], RZ ; /* 0x80005b0000058a10 */
/* 0x000fca0007ffe0ff */
/*0210*/ @!P0 IMAD R5, R5, R6, 0x1 ; /* 0x0000000105058424 */
/* 0x000fe200078e0206 */
/*0220*/ @!P0 BRA 0x2c0 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*0230*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff087624 */
/* 0x000fca00078e00ff */
/*0240*/ LEA R4, R8, c[0x0][0x16c], 0x1 ; /* 0x00005b0008047a11 */
/* 0x000fc800078e08ff */
/*0250*/ IADD3 R9, R4, -0x4, RZ ; /* 0xfffffffc04097810 */
/* 0x000fc80007ffe0ff */
/*0260*/ ISETP.GT.AND P0, PT, R0, R9, PT ; /* 0x000000090000720c */
/* 0x000fda0003f04270 */
/*0270*/ @P0 IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08040810 */
/* 0x000fe20007ffe0ff */
/*0280*/ @!P0 IMAD.IADD R5, R0, 0x1, -R7 ; /* 0x0000000100058824 */
/* 0x000fc800078e0a07 */
/*0290*/ @P0 IMAD R9, R4, c[0x0][0x16c], -R9 ; /* 0x00005b0004090a24 */
/* 0x000fe400078e0a09 */
/*02a0*/ @!P0 IMAD R5, R5, R6, c[0x0][0x16c] ; /* 0x00005b0005058624 */
/* 0x000fe400078e0206 */
/*02b0*/ @P0 IMAD.IADD R5, R0, 0x1, R9 ; /* 0x0000000100050824 */
/* 0x000fe400078e0209 */
/*02c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02d0*/ IADD3 R4, R5, -0x1, RZ ; /* 0xffffffff05047810 */
/* 0x000fca0007ffe0ff */
/*02e0*/ IMAD.WIDE R4, R4, R13, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e020d */
/*02f0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e2000c101908 */
/*0300*/ BRA 0x380 ; /* 0x0000007000007947 */
/* 0x000fea0003800000 */
/*0310*/ ULDC.64 UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000a00 */
/*0320*/ UISETP.LT.AND UP0, UPT, UR5, UR4, UPT ; /* 0x000000040500728c */
/* 0x000fc8000bf01270 */
/*0330*/ USEL UR4, UR5, UR4, !UP0 ; /* 0x0000000405047287 */
/* 0x000fcc000c000000 */
/*0340*/ ISETP.GT.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf04270 */
/*0350*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff058424 */
/* 0x000fc800078e00ff */
/*0360*/ @!P0 IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000048625 */
/* 0x000fca00078e0205 */
/*0370*/ @!P0 STG.E [R4.64], R11 ; /* 0x0000000b04008986 */
/* 0x0001e4000c101908 */
/*0380*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0390*/ ULDC UR6, c[0x0][0xc] ; /* 0x0000030000067ab9 */
/* 0x000fe40000000800 */
/*03a0*/ ULDC.64 UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000a00 */
/*03b0*/ UIMAD UR4, UR4, UR6, URZ ; /* 0x00000006040472a4 */
/* 0x000fc8000f8e023f */
/*03c0*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fc6000f8e023f */
/*03d0*/ ULDC UR5, c[0x0][0x10] ; /* 0x0000040000057ab9 */
/* 0x000fe40000000800 */
/*03e0*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fcc000f8e023f */
/*03f0*/ ISETP.NE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf05270 */
/*0400*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0410*/ STG.E.STRONG.SYS [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c115908 */
/*0420*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0430*/ BRA 0x430; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9histogramPiS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0207 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IABS R9, c[0x0][0x178] ; /* 0x00005e0000097a13 */
/* 0x000fc80000000000 */
/*00d0*/ I2F.RP R0, R9 ; /* 0x0000000900007306 */
/* 0x000e300000209400 */
/*00e0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R4, R0, 0xffffffe, RZ ; /* 0x0ffffffe00047810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0110*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0120*/ IMAD.MOV R6, RZ, RZ, -R5 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a05 */
/*0130*/ IMAD R11, R6, R9, RZ ; /* 0x00000009060b7224 */
/* 0x000fca00078e02ff */
/*0140*/ IMAD.HI.U32 R5, R5, R11, R4 ; /* 0x0000000b05057227 */
/* 0x000fe200078e0004 */
/*0150*/ IABS R6, R2 ; /* 0x0000000200067213 */
/* 0x004fe40000000000 */
/*0160*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc60003f46270 */
/*0170*/ IMAD.HI.U32 R5, R5, R6, RZ ; /* 0x0000000605057227 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a05 */
/*0190*/ IMAD R0, R9, R5, R6 ; /* 0x0000000509007224 */
/* 0x000fe400078e0206 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fc600078e00ff */
/*01b0*/ ISETP.GT.U32.AND P0, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fda0003f04070 */
/*01c0*/ @!P0 IADD3 R0, R0, -R9, RZ ; /* 0x8000000900008210 */
/* 0x000fe40007ffe0ff */
/*01d0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f05270 */
/*01e0*/ ISETP.GT.U32.AND P1, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fda0003f24070 */
/*01f0*/ @!P1 IMAD.IADD R0, R0, 0x1, -R9 ; /* 0x0000000100009824 */
/* 0x000fca00078e0a09 */
/*0200*/ @!P2 IADD3 R0, -R0, RZ, RZ ; /* 0x000000ff0000a210 */
/* 0x000fe40007ffe1ff */
/*0210*/ @!P0 LOP3.LUT R0, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff008a12 */
/* 0x000fca00078e33ff */
/*0220*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0207 */
/*0230*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x000fe2000c10e184 */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __device__ volatile int uc = 1;
__device__ volatile unsigned int counter = 0;
__device__ volatile unsigned int cnt = 1;
__global__ void histogram(int *d_input, int* d_bin, int M, int N, int BIN_COUNT)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id < M*N) {
int bid = d_input[id] % BIN_COUNT;
atomicAdd(&(d_bin[bid]), 1);
}
}
__global__ void updateBC(int* d_input, int M, int N)
{
int old = atomicAdd((int *)(&uc), 1);
if (N==1 || M==1) {
int mx = (N < M)? M:N;
if (old <= mx) {
d_input[old] = 1;
}
} else if (old <= 2*(N+M) - 4) {
int id;
if (old <= N) {
id = old;
} else if (old <= N+M-2) {
id = 1+N*(old-N);
} else if (old <= N+2*(M-2)) {
id = N+(old-(N+M-2))*N;
} else {
id = N*(M-1) + old-(N+2*(M-2));
}
d_input[id-1] = 1;
}
if (old == blockDim.x*gridDim.x*blockDim.y*gridDim.y) {
uc = 1;
}
}
__global__ void stencil(int* d_input, const int M, const int N)
{
int old = atomicInc((unsigned int*)(&counter), 1<<30);
const int max = (N-2)*(M-2);
if (old < max) {
int i = old % (N-2);
int j = old / (N-2);
int id = N*(j+1)+i+1;
int sum = 0.2 * (d_input[id]+d_input[id+1]+d_input[id-1]+d_input[id+N]+d_input[id-N]);
atomicInc((unsigned int*)(&cnt), 1<<30);
while (cnt < max);
d_input[id] = sum;
if (old+1 == max) {
cnt = 1;
}
}
if (old+1 == blockDim.x*gridDim.x*blockDim.y*gridDim.y) {
counter = 0;
}
} | .file "tmpxft_0007a65a_00000000-6_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9histogramPiS_iiiPiS_iii
.type _Z33__device_stub__Z9histogramPiS_iiiPiS_iii, @function
_Z33__device_stub__Z9histogramPiS_iiiPiS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9histogramPiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9histogramPiS_iiiPiS_iii, .-_Z33__device_stub__Z9histogramPiS_iiiPiS_iii
.globl _Z9histogramPiS_iii
.type _Z9histogramPiS_iii, @function
_Z9histogramPiS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9histogramPiS_iiiPiS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9histogramPiS_iii, .-_Z9histogramPiS_iii
.globl _Z29__device_stub__Z8updateBCPiiiPiii
.type _Z29__device_stub__Z8updateBCPiiiPiii, @function
_Z29__device_stub__Z8updateBCPiiiPiii:
.LFB2053:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8updateBCPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z29__device_stub__Z8updateBCPiiiPiii, .-_Z29__device_stub__Z8updateBCPiiiPiii
.globl _Z8updateBCPiii
.type _Z8updateBCPiii, @function
_Z8updateBCPiii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8updateBCPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z8updateBCPiii, .-_Z8updateBCPiii
.globl _Z28__device_stub__Z7stencilPiiiPiii
.type _Z28__device_stub__Z7stencilPiiiPiii, @function
_Z28__device_stub__Z7stencilPiiiPiii:
.LFB2055:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7stencilPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z28__device_stub__Z7stencilPiiiPiii, .-_Z28__device_stub__Z7stencilPiiiPiii
.globl _Z7stencilPiii
.type _Z7stencilPiii, @function
_Z7stencilPiii:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7stencilPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z7stencilPiii, .-_Z7stencilPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7stencilPiii"
.LC1:
.string "_Z8updateBCPiii"
.LC2:
.string "_Z9histogramPiS_iii"
.LC3:
.string "uc"
.LC4:
.string "counter"
.LC5:
.string "cnt"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7stencilPiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8updateBCPiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9histogramPiS_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2uc(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7counter(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3cnt(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL3cnt
.comm _ZL3cnt,4,4
.local _ZL7counter
.comm _ZL7counter,4,4
.local _ZL2uc
.comm _ZL2uc,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __device__ volatile int uc = 1;
__device__ volatile unsigned int counter = 0;
__device__ volatile unsigned int cnt = 1;
__global__ void histogram(int *d_input, int* d_bin, int M, int N, int BIN_COUNT)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id < M*N) {
int bid = d_input[id] % BIN_COUNT;
atomicAdd(&(d_bin[bid]), 1);
}
}
__global__ void updateBC(int* d_input, int M, int N)
{
int old = atomicAdd((int *)(&uc), 1);
if (N==1 || M==1) {
int mx = (N < M)? M:N;
if (old <= mx) {
d_input[old] = 1;
}
} else if (old <= 2*(N+M) - 4) {
int id;
if (old <= N) {
id = old;
} else if (old <= N+M-2) {
id = 1+N*(old-N);
} else if (old <= N+2*(M-2)) {
id = N+(old-(N+M-2))*N;
} else {
id = N*(M-1) + old-(N+2*(M-2));
}
d_input[id-1] = 1;
}
if (old == blockDim.x*gridDim.x*blockDim.y*gridDim.y) {
uc = 1;
}
}
__global__ void stencil(int* d_input, const int M, const int N)
{
int old = atomicInc((unsigned int*)(&counter), 1<<30);
const int max = (N-2)*(M-2);
if (old < max) {
int i = old % (N-2);
int j = old / (N-2);
int id = N*(j+1)+i+1;
int sum = 0.2 * (d_input[id]+d_input[id+1]+d_input[id-1]+d_input[id+N]+d_input[id-N]);
atomicInc((unsigned int*)(&cnt), 1<<30);
while (cnt < max);
d_input[id] = sum;
if (old+1 == max) {
cnt = 1;
}
}
if (old+1 == blockDim.x*gridDim.x*blockDim.y*gridDim.y) {
counter = 0;
}
} | #include <hip/hip_runtime.h>
__device__ volatile int uc = 1;
__device__ volatile unsigned int counter = 0;
__device__ volatile unsigned int cnt = 1;
__global__ void histogram(int *d_input, int* d_bin, int M, int N, int BIN_COUNT)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id < M*N) {
int bid = d_input[id] % BIN_COUNT;
atomicAdd(&(d_bin[bid]), 1);
}
}
__global__ void updateBC(int* d_input, int M, int N)
{
int old = atomicAdd((int *)(&uc), 1);
if (N==1 || M==1) {
int mx = (N < M)? M:N;
if (old <= mx) {
d_input[old] = 1;
}
} else if (old <= 2*(N+M) - 4) {
int id;
if (old <= N) {
id = old;
} else if (old <= N+M-2) {
id = 1+N*(old-N);
} else if (old <= N+2*(M-2)) {
id = N+(old-(N+M-2))*N;
} else {
id = N*(M-1) + old-(N+2*(M-2));
}
d_input[id-1] = 1;
}
if (old == blockDim.x*gridDim.x*blockDim.y*gridDim.y) {
uc = 1;
}
}
__global__ void stencil(int* d_input, const int M, const int N)
{
int old = atomicInc((unsigned int*)(&counter), 1<<30);
const int max = (N-2)*(M-2);
if (old < max) {
int i = old % (N-2);
int j = old / (N-2);
int id = N*(j+1)+i+1;
int sum = 0.2 * (d_input[id]+d_input[id+1]+d_input[id-1]+d_input[id+N]+d_input[id-N]);
atomicInc((unsigned int*)(&cnt), 1<<30);
while (cnt < max);
d_input[id] = sum;
if (old+1 == max) {
cnt = 1;
}
}
if (old+1 == blockDim.x*gridDim.x*blockDim.y*gridDim.y) {
counter = 0;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__device__ volatile int uc = 1;
__device__ volatile unsigned int counter = 0;
__device__ volatile unsigned int cnt = 1;
__global__ void histogram(int *d_input, int* d_bin, int M, int N, int BIN_COUNT)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id < M*N) {
int bid = d_input[id] % BIN_COUNT;
atomicAdd(&(d_bin[bid]), 1);
}
}
__global__ void updateBC(int* d_input, int M, int N)
{
int old = atomicAdd((int *)(&uc), 1);
if (N==1 || M==1) {
int mx = (N < M)? M:N;
if (old <= mx) {
d_input[old] = 1;
}
} else if (old <= 2*(N+M) - 4) {
int id;
if (old <= N) {
id = old;
} else if (old <= N+M-2) {
id = 1+N*(old-N);
} else if (old <= N+2*(M-2)) {
id = N+(old-(N+M-2))*N;
} else {
id = N*(M-1) + old-(N+2*(M-2));
}
d_input[id-1] = 1;
}
if (old == blockDim.x*gridDim.x*blockDim.y*gridDim.y) {
uc = 1;
}
}
__global__ void stencil(int* d_input, const int M, const int N)
{
int old = atomicInc((unsigned int*)(&counter), 1<<30);
const int max = (N-2)*(M-2);
if (old < max) {
int i = old % (N-2);
int j = old / (N-2);
int id = N*(j+1)+i+1;
int sum = 0.2 * (d_input[id]+d_input[id+1]+d_input[id-1]+d_input[id+N]+d_input[id-N]);
atomicInc((unsigned int*)(&cnt), 1<<30);
while (cnt < max);
d_input[id] = sum;
if (old+1 == max) {
cnt = 1;
}
}
if (old+1 == blockDim.x*gridDim.x*blockDim.y*gridDim.y) {
counter = 0;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9histogramPiS_iii
.globl _Z9histogramPiS_iii
.p2align 8
.type _Z9histogramPiS_iii,@function
_Z9histogramPiS_iii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s2, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_ashr_i32 s1, s0, 31
s_add_i32 s0, s0, s1
global_load_b32 v0, v[0:1], off
s_xor_b32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s0
s_sub_i32 s1, 0, s0
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v0
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v1, 0x4f7ffffe, v1 :: v_dual_add_nc_u32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v1, v1
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s1, v1
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v2, 1 :: v_dual_add_nc_u32 v1, v1, v2
v_mul_hi_u32 v1, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v1, s0
v_sub_nc_u32_e32 v0, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v1, s0, v0
v_cmp_le_u32_e32 vcc_lo, s0, v0
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v1, s0, v0
v_cmp_le_u32_e32 vcc_lo, s0, v0
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v3
v_sub_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9histogramPiS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9histogramPiS_iii, .Lfunc_end0-_Z9histogramPiS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8updateBCPiii
.globl _Z8updateBCPiii
.p2align 8
.type _Z8updateBCPiii,@function
_Z8updateBCPiii:
s_mov_b32 s4, exec_lo
s_mov_b32 s2, 0
v_mbcnt_lo_u32_b32 v0, s4, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_2
s_bcnt1_i32_b32 s6, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s6
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, uc@rel32@lo+4
s_addc_u32 s5, s5, uc@rel32@hi+12
global_atomic_add_u32 v1, v1, v2, s[4:5] glc
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s3
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s3, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v0, s3, v0
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s7, 1
s_cselect_b32 s8, -1, 0
s_cmp_lg_u32 s6, 1
s_cselect_b32 s9, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s8, s9, s8
s_and_b32 vcc_lo, exec_lo, s8
s_cbranch_vccz .LBB1_16
s_add_i32 s9, s7, s6
s_mov_b32 s3, 0
s_lshl_b32 s2, s9, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, -4
v_cmp_ge_i32_e32 vcc_lo, s2, v0
s_mov_b32 s2, 0
s_and_saveexec_b32 s8, vcc_lo
s_cbranch_execz .LBB1_15
v_mov_b32_e32 v1, v0
s_mov_b32 s2, exec_lo
v_cmpx_lt_i32_e64 s7, v0
s_cbranch_execz .LBB1_14
s_add_i32 s10, s9, -2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, s10, v0
s_and_saveexec_b32 s10, vcc_lo
s_xor_b32 s10, exec_lo, s10
v_subrev_nc_u32_e32 v3, s7, v0
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v3, s7, 1
s_and_not1_saveexec_b32 s10, s10
s_cbranch_execz .LBB1_13
s_lshl_b32 s11, s6, 1
s_mov_b32 s12, exec_lo
s_add_i32 s11, s11, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s11, s11, -4
v_cmpx_ge_i32_e64 s11, v0
s_xor_b32 s12, exec_lo, s12
v_subrev_nc_u32_e32 v1, s9, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, 3, v1
v_mul_lo_u32 v1, v1, s7
s_and_not1_saveexec_b32 s9, s12
s_add_i32 s12, s6, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s12, s12, s7
s_sub_i32 s11, s12, s11
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v1, s11, v0
s_or_b32 exec_lo, exec_lo, s9
.LBB1_13:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB1_14:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s2
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, -4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, -1, v2, vcc_lo
.LBB1_15:
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccz .LBB1_20
s_branch .LBB1_17
.LBB1_16:
s_cbranch_execz .LBB1_20
.LBB1_17:
s_max_i32 s3, s7, s6
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, s3, v0
s_and_saveexec_b32 s3, vcc_lo
v_ashrrev_i32_e32 v1, 31, v0
s_or_b32 s2, s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_or_b32 exec_lo, exec_lo, s3
.LBB1_20:
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_22
v_mov_b32_e32 v3, 1
global_store_b32 v[1:2], v3, off
.LBB1_22:
s_or_b32 exec_lo, exec_lo, s3
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s0, s0, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s0, s0, s1
s_mul_i32 s0, s0, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s0, v0
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB1_24
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, uc@rel32@lo+4
s_addc_u32 s1, s1, uc@rel32@hi+12
v_mov_b32_e32 v2, 1
v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
flat_store_b32 v[0:1], v2 dlc
s_waitcnt_vscnt null, 0x0
.LBB1_24:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8updateBCPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 13
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8updateBCPiii, .Lfunc_end1-_Z8updateBCPiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7stencilPiii
.globl _Z7stencilPiii
.p2align 8
.type _Z7stencilPiii,@function
_Z7stencilPiii:
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 2.0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, counter@rel32@lo+4
s_addc_u32 s3, s3, counter@rel32@hi+12
global_atomic_inc_u32 v2, v3, v4, s[2:3] glc
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_add_i32 s5, s3, -2
s_add_i32 s2, s2, -2
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s4, s5, s2
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 s4, v2
s_cbranch_execz .LBB2_5
s_ashr_i32 s6, s5, 31
v_ashrrev_i32_e32 v5, 31, v2
s_add_i32 s7, s5, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s7, s7, s6
v_add_nc_u32_e32 v6, v2, v5
v_cvt_f32_u32_e32 v0, s7
s_sub_i32 s8, 0, s7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v6, v6, v5
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v5, s6, v5
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v1, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v0, v1
v_add_nc_u32_e32 v0, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v6, v0
v_mul_lo_u32 v1, v0, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v1, v6, v1
v_add_nc_u32_e32 v6, 1, v0
v_subrev_nc_u32_e32 v7, s7, v1
v_cmp_le_u32_e32 vcc_lo, s7, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v1, v1, v7 :: v_dual_cndmask_b32 v0, v0, v6
v_cmp_le_u32_e32 vcc_lo, s7, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, 1, v0
s_load_b64 s[6:7], s[0:1], 0x0
v_cndmask_b32_e32 v0, v0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v5
v_sub_nc_u32_e32 v0, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v1, v0, s5
v_mul_lo_u32 v0, s3, v0
v_sub_nc_u32_e32 v1, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, v0, s3, v1
v_add_nc_u32_e32 v5, 1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v7, s3, v5
v_ashrrev_i32_e32 v6, 31, v5
v_subrev_nc_u32_e32 v9, s3, v5
v_lshlrev_b64 v[11:12], 2, v[0:1]
s_mov_b32 s3, 0
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v8, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v10, vcc_lo
v_add_co_u32 v10, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v12, vcc_lo
s_clause 0x4
global_load_b32 v5, v[0:1], off
global_load_b32 v6, v[6:7], off
global_load_b32 v7, v[8:9], off
global_load_b32 v8, v[10:11], off offset:8
global_load_b32 v9, v[10:11], off
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, cnt@rel32@lo+4
s_addc_u32 s7, s7, cnt@rel32@hi+12
global_atomic_inc_u32 v3, v4, s[6:7]
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, cnt@rel32@lo+4
s_addc_u32 s7, s7, cnt@rel32@hi+12
.LBB2_2:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v3, s6 :: v_dual_mov_b32 v4, s7
flat_load_b32 v3, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_le_u32_e32 vcc_lo, s4, v3
s_or_b32 s3, vcc_lo, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB2_2
s_or_b32 exec_lo, exec_lo, s3
v_add3_u32 v3, v8, v5, v9
s_mov_b32 s7, 0x3fc99999
s_mov_b32 s6, 0x9999999a
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v3, v3, v6, v7
v_cvt_f64_i32_e32 v[3:4], v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[3:4], v[3:4], s[6:7]
v_cvt_i32_f64_e32 v3, v[3:4]
v_add_nc_u32_e32 v4, 1, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, s4, v4
global_store_b32 v[0:1], v3, off
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_5
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, cnt@rel32@lo+4
s_addc_u32 s5, s5, cnt@rel32@hi+12
v_dual_mov_b32 v3, 1 :: v_dual_mov_b32 v0, s4
v_mov_b32_e32 v1, s5
flat_store_b32 v[0:1], v3 dlc
s_waitcnt_vscnt null, 0x0
.LBB2_5:
s_or_b32 exec_lo, exec_lo, s2
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x10
v_add_nc_u32_e32 v0, 1, v2
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s0, s0, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s0, s0, s1
s_mul_i32 s0, s0, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s0, v0
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB2_7
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, counter@rel32@lo+4
s_addc_u32 s1, s1, counter@rel32@hi+12
v_mov_b32_e32 v2, 0
v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
flat_store_b32 v[0:1], v2 dlc
s_waitcnt_vscnt null, 0x0
.LBB2_7:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7stencilPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 9
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z7stencilPiii, .Lfunc_end2-_Z7stencilPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected uc
.type uc,@object
.data
.globl uc
.p2align 2, 0x0
uc:
.long 1
.size uc, 4
.protected counter
.type counter,@object
.section .bss,"aw",@nobits
.globl counter
.p2align 2, 0x0
counter:
.long 0
.size counter, 4
.protected cnt
.type cnt,@object
.data
.globl cnt
.p2align 2, 0x0
cnt:
.long 1
.size cnt, 4
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym uc
.addrsig_sym counter
.addrsig_sym cnt
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9histogramPiS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9histogramPiS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8updateBCPiii
.private_segment_fixed_size: 0
.sgpr_count: 15
.sgpr_spill_count: 0
.symbol: _Z8updateBCPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7stencilPiii
.private_segment_fixed_size: 0
.sgpr_count: 11
.sgpr_spill_count: 0
.symbol: _Z7stencilPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__device__ volatile int uc = 1;
__device__ volatile unsigned int counter = 0;
__device__ volatile unsigned int cnt = 1;
__global__ void histogram(int *d_input, int* d_bin, int M, int N, int BIN_COUNT)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id < M*N) {
int bid = d_input[id] % BIN_COUNT;
atomicAdd(&(d_bin[bid]), 1);
}
}
__global__ void updateBC(int* d_input, int M, int N)
{
int old = atomicAdd((int *)(&uc), 1);
if (N==1 || M==1) {
int mx = (N < M)? M:N;
if (old <= mx) {
d_input[old] = 1;
}
} else if (old <= 2*(N+M) - 4) {
int id;
if (old <= N) {
id = old;
} else if (old <= N+M-2) {
id = 1+N*(old-N);
} else if (old <= N+2*(M-2)) {
id = N+(old-(N+M-2))*N;
} else {
id = N*(M-1) + old-(N+2*(M-2));
}
d_input[id-1] = 1;
}
if (old == blockDim.x*gridDim.x*blockDim.y*gridDim.y) {
uc = 1;
}
}
__global__ void stencil(int* d_input, const int M, const int N)
{
int old = atomicInc((unsigned int*)(&counter), 1<<30);
const int max = (N-2)*(M-2);
if (old < max) {
int i = old % (N-2);
int j = old / (N-2);
int id = N*(j+1)+i+1;
int sum = 0.2 * (d_input[id]+d_input[id+1]+d_input[id-1]+d_input[id+N]+d_input[id-N]);
atomicInc((unsigned int*)(&cnt), 1<<30);
while (cnt < max);
d_input[id] = sum;
if (old+1 == max) {
cnt = 1;
}
}
if (old+1 == blockDim.x*gridDim.x*blockDim.y*gridDim.y) {
counter = 0;
}
} | .text
.file "kernels.hip"
.globl _Z24__device_stub__histogramPiS_iii # -- Begin function _Z24__device_stub__histogramPiS_iii
.p2align 4, 0x90
.type _Z24__device_stub__histogramPiS_iii,@function
_Z24__device_stub__histogramPiS_iii: # @_Z24__device_stub__histogramPiS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9histogramPiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__histogramPiS_iii, .Lfunc_end0-_Z24__device_stub__histogramPiS_iii
.cfi_endproc
# -- End function
.globl _Z23__device_stub__updateBCPiii # -- Begin function _Z23__device_stub__updateBCPiii
.p2align 4, 0x90
.type _Z23__device_stub__updateBCPiii,@function
_Z23__device_stub__updateBCPiii: # @_Z23__device_stub__updateBCPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8updateBCPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z23__device_stub__updateBCPiii, .Lfunc_end1-_Z23__device_stub__updateBCPiii
.cfi_endproc
# -- End function
.globl _Z22__device_stub__stencilPiii # -- Begin function _Z22__device_stub__stencilPiii
.p2align 4, 0x90
.type _Z22__device_stub__stencilPiii,@function
_Z22__device_stub__stencilPiii: # @_Z22__device_stub__stencilPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7stencilPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z22__device_stub__stencilPiii, .Lfunc_end2-_Z22__device_stub__stencilPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9histogramPiS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8updateBCPiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7stencilPiii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $uc, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $counter, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $cnt, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type uc,@object # @uc
.local uc
.comm uc,4,4
.type counter,@object # @counter
.local counter
.comm counter,4,4
.type cnt,@object # @cnt
.local cnt
.comm cnt,4,4
.type _Z9histogramPiS_iii,@object # @_Z9histogramPiS_iii
.section .rodata,"a",@progbits
.globl _Z9histogramPiS_iii
.p2align 3, 0x0
_Z9histogramPiS_iii:
.quad _Z24__device_stub__histogramPiS_iii
.size _Z9histogramPiS_iii, 8
.type _Z8updateBCPiii,@object # @_Z8updateBCPiii
.globl _Z8updateBCPiii
.p2align 3, 0x0
_Z8updateBCPiii:
.quad _Z23__device_stub__updateBCPiii
.size _Z8updateBCPiii, 8
.type _Z7stencilPiii,@object # @_Z7stencilPiii
.globl _Z7stencilPiii
.p2align 3, 0x0
_Z7stencilPiii:
.quad _Z22__device_stub__stencilPiii
.size _Z7stencilPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9histogramPiS_iii"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8updateBCPiii"
.size .L__unnamed_2, 16
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z7stencilPiii"
.size .L__unnamed_3, 15
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "uc"
.size .L__unnamed_4, 3
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "counter"
.size .L__unnamed_5, 8
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "cnt"
.size .L__unnamed_6, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__histogramPiS_iii
.addrsig_sym _Z23__device_stub__updateBCPiii
.addrsig_sym _Z22__device_stub__stencilPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym uc
.addrsig_sym counter
.addrsig_sym cnt
.addrsig_sym _Z9histogramPiS_iii
.addrsig_sym _Z8updateBCPiii
.addrsig_sym _Z7stencilPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007a65a_00000000-6_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9histogramPiS_iiiPiS_iii
.type _Z33__device_stub__Z9histogramPiS_iiiPiS_iii, @function
_Z33__device_stub__Z9histogramPiS_iiiPiS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9histogramPiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9histogramPiS_iiiPiS_iii, .-_Z33__device_stub__Z9histogramPiS_iiiPiS_iii
.globl _Z9histogramPiS_iii
.type _Z9histogramPiS_iii, @function
_Z9histogramPiS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9histogramPiS_iiiPiS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9histogramPiS_iii, .-_Z9histogramPiS_iii
.globl _Z29__device_stub__Z8updateBCPiiiPiii
.type _Z29__device_stub__Z8updateBCPiiiPiii, @function
_Z29__device_stub__Z8updateBCPiiiPiii:
.LFB2053:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8updateBCPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z29__device_stub__Z8updateBCPiiiPiii, .-_Z29__device_stub__Z8updateBCPiiiPiii
.globl _Z8updateBCPiii
.type _Z8updateBCPiii, @function
_Z8updateBCPiii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8updateBCPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z8updateBCPiii, .-_Z8updateBCPiii
.globl _Z28__device_stub__Z7stencilPiiiPiii
.type _Z28__device_stub__Z7stencilPiiiPiii, @function
_Z28__device_stub__Z7stencilPiiiPiii:
.LFB2055:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7stencilPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z28__device_stub__Z7stencilPiiiPiii, .-_Z28__device_stub__Z7stencilPiiiPiii
.globl _Z7stencilPiii
.type _Z7stencilPiii, @function
_Z7stencilPiii:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7stencilPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z7stencilPiii, .-_Z7stencilPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7stencilPiii"
.LC1:
.string "_Z8updateBCPiii"
.LC2:
.string "_Z9histogramPiS_iii"
.LC3:
.string "uc"
.LC4:
.string "counter"
.LC5:
.string "cnt"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7stencilPiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8updateBCPiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9histogramPiS_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2uc(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7counter(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3cnt(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL3cnt
.comm _ZL3cnt,4,4
.local _ZL7counter
.comm _ZL7counter,4,4
.local _ZL2uc
.comm _ZL2uc,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernels.hip"
.globl _Z24__device_stub__histogramPiS_iii # -- Begin function _Z24__device_stub__histogramPiS_iii
.p2align 4, 0x90
.type _Z24__device_stub__histogramPiS_iii,@function
_Z24__device_stub__histogramPiS_iii: # @_Z24__device_stub__histogramPiS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9histogramPiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__histogramPiS_iii, .Lfunc_end0-_Z24__device_stub__histogramPiS_iii
.cfi_endproc
# -- End function
.globl _Z23__device_stub__updateBCPiii # -- Begin function _Z23__device_stub__updateBCPiii
.p2align 4, 0x90
.type _Z23__device_stub__updateBCPiii,@function
_Z23__device_stub__updateBCPiii: # @_Z23__device_stub__updateBCPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8updateBCPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z23__device_stub__updateBCPiii, .Lfunc_end1-_Z23__device_stub__updateBCPiii
.cfi_endproc
# -- End function
.globl _Z22__device_stub__stencilPiii # -- Begin function _Z22__device_stub__stencilPiii
.p2align 4, 0x90
.type _Z22__device_stub__stencilPiii,@function
_Z22__device_stub__stencilPiii: # @_Z22__device_stub__stencilPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7stencilPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z22__device_stub__stencilPiii, .Lfunc_end2-_Z22__device_stub__stencilPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9histogramPiS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8updateBCPiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7stencilPiii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $uc, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $counter, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $cnt, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type uc,@object # @uc
.local uc
.comm uc,4,4
.type counter,@object # @counter
.local counter
.comm counter,4,4
.type cnt,@object # @cnt
.local cnt
.comm cnt,4,4
.type _Z9histogramPiS_iii,@object # @_Z9histogramPiS_iii
.section .rodata,"a",@progbits
.globl _Z9histogramPiS_iii
.p2align 3, 0x0
_Z9histogramPiS_iii:
.quad _Z24__device_stub__histogramPiS_iii
.size _Z9histogramPiS_iii, 8
.type _Z8updateBCPiii,@object # @_Z8updateBCPiii
.globl _Z8updateBCPiii
.p2align 3, 0x0
_Z8updateBCPiii:
.quad _Z23__device_stub__updateBCPiii
.size _Z8updateBCPiii, 8
.type _Z7stencilPiii,@object # @_Z7stencilPiii
.globl _Z7stencilPiii
.p2align 3, 0x0
_Z7stencilPiii:
.quad _Z22__device_stub__stencilPiii
.size _Z7stencilPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9histogramPiS_iii"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8updateBCPiii"
.size .L__unnamed_2, 16
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z7stencilPiii"
.size .L__unnamed_3, 15
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "uc"
.size .L__unnamed_4, 3
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "counter"
.size .L__unnamed_5, 8
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "cnt"
.size .L__unnamed_6, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__histogramPiS_iii
.addrsig_sym _Z23__device_stub__updateBCPiii
.addrsig_sym _Z22__device_stub__stencilPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym uc
.addrsig_sym counter
.addrsig_sym cnt
.addrsig_sym _Z9histogramPiS_iii
.addrsig_sym _Z8updateBCPiii
.addrsig_sym _Z7stencilPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdint.h>
#define CHECK(call)\
{\
const cudaError_t error = call;\
if (error != cudaSuccess)\
{\
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__);\
fprintf(stderr, "code: %d, reason: %s\n", error,\
cudaGetErrorString(error));\
exit(EXIT_FAILURE);\
}\
}
struct GpuTimer
{
cudaEvent_t start;
cudaEvent_t stop;
GpuTimer()
{
cudaEventCreate(&start);
cudaEventCreate(&stop);
}
~GpuTimer()
{
cudaEventDestroy(start);
cudaEventDestroy(stop);
}
void Start()
{
cudaEventRecord(start, 0);
cudaEventSynchronize(start);
}
void Stop()
{
cudaEventRecord(stop, 0);
}
float Elapsed()
{
float elapsed;
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
void readPnm(char * fileName,
int &numChannels, int &width, int &height, uint8_t * &pixels)
{
FILE * f = fopen(fileName, "r");
if (f == NULL)
{
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
char type[3];
fscanf(f, "%s", type);
if (strcmp(type, "P2") == 0)
numChannels = 1;
else if (strcmp(type, "P3") == 0)
numChannels = 3;
else // In this exercise, we don't touch other types
{
fclose(f);
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
fscanf(f, "%i", &width);
fscanf(f, "%i", &height);
int max_val;
fscanf(f, "%i", &max_val);
if (max_val > 255) // In this exercise, we assume 1 byte per value
{
fclose(f);
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
pixels = (uint8_t *)malloc(width * height * numChannels);
for (int i = 0; i < width * height * numChannels; i++)
fscanf(f, "%hhu", &pixels[i]);
fclose(f);
}
void writePnm(uint8_t * pixels, int numChannels, int width, int height,
char * fileName)
{
FILE * f = fopen(fileName, "w");
if (f == NULL)
{
printf("Cannot write %s\n", fileName);
exit(EXIT_FAILURE);
}
if (numChannels == 1)
fprintf(f, "P2\n");
else if (numChannels == 3)
fprintf(f, "P3\n");
else
{
fclose(f);
printf("Cannot write %s\n", fileName);
exit(EXIT_FAILURE);
}
fprintf(f, "%i\n%i\n255\n", width, height);
for (int i = 0; i < width * height * numChannels; i++)
fprintf(f, "%hhu\n", pixels[i]);
fclose(f);
}
__global__ void convertRgb2GrayKernel(uint8_t * inPixels, int width, int height,
uint8_t * outPixels)
{
// TODO
int ix = blockIdx.x * blockDim.x + threadIdx.x;
int iy = blockIdx.y * blockDim.y + threadIdx.y;
if (ix < width && iy < height)
{
int i = iy * width + ix;
uint8_t r = inPixels[i * 3];
uint8_t g = inPixels[i * 3 + 1];
uint8_t b = inPixels[i * 3 + 2];
outPixels[i] = 0.299f * r + 0.587f * g + 0.114f * b;
}
}
void convertRgb2Gray(uint8_t * inPixels, int width, int height,
uint8_t * outPixels,
bool useDevice=false, dim3 blockSize=dim3(1))
{
GpuTimer timer;
timer.Start();
if (useDevice == false)
{
for (int r = 0; r < height; r++)
{
for (int c = 0; c < width; c++)
{
int i = r * width + c;
uint8_t r = inPixels[i * 3];
uint8_t g = inPixels[i * 3 + 1];
uint8_t b = inPixels[i * 3 + 2];
outPixels[i] = 0.299f * r + 0.587f * g + 0.114f * b;
}
}
}
else // use device
{
int numChannels = 3;
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, 0);
printf("GPU name: %s\n", devProp.name);
printf("GPU compute capability: %d.%d\n", devProp.major, devProp.minor);
// TODO: Allocate device memories
uint8_t *d_inPixels, * d_outPixels;
CHECK(cudaMalloc(&d_inPixels, height * width * numChannels * sizeof(uint8_t)));
CHECK(cudaMalloc(&d_outPixels, height * width * sizeof(uint8_t)));
// TODO: Copy data to device memories
CHECK(cudaMemcpy(d_inPixels, inPixels, height * width * numChannels * sizeof(uint8_t), cudaMemcpyHostToDevice));
// TODO: Set grid size and call kernel (remember to check kernel error)
dim3 gridSize((width - 1)/blockSize.x + 1, (height - 1)/blockSize.y + 1);
convertRgb2GrayKernel<<<gridSize, blockSize>>>(d_inPixels, width, height, d_outPixels);
cudaError_t errSync = cudaGetLastError();
cudaError_t errAsync = cudaDeviceSynchronize();
if (errSync != cudaSuccess)
printf("Sync kernel error: %s\n", cudaGetErrorString(errSync));
if (errAsync != cudaSuccess)
printf("Async kernel error: %s\n", cudaGetErrorString(errAsync));
// TODO: Copy result from device memories
CHECK(cudaMemcpy(outPixels, d_outPixels, height * width * sizeof(uint8_t), cudaMemcpyDeviceToHost));
// TODO: Free device memories
CHECK(cudaFree(d_inPixels));
CHECK(cudaFree(d_outPixels));
}
timer.Stop();
float time = timer.Elapsed();
printf("Processing time (%s): %f ms\n\n",
useDevice == true? "use device" : "use host", time);
}
float computeError(uint8_t * a1, uint8_t * a2, int n)
{
float err = 0;
for (int i = 0; i < n; i++)
err += abs((int)a1[i] - (int)a2[i]);
err /= n;
return err;
}
char * concatStr(const char * s1, const char * s2)
{
char * result = (char *)malloc(strlen(s1) + strlen(s2) + 1);
strcpy(result, s1);
strcat(result, s2);
return result;
}
int main(int argc, char ** argv)
{
if (argc != 3 && argc != 5)
{
printf("The number of arguments is invalid\n");
return EXIT_FAILURE;
}
// Read input RGB image file
int numChannels, width, height;
uint8_t * inPixels;
readPnm(argv[1], numChannels, width, height, inPixels);
if (numChannels != 3)
return EXIT_FAILURE; // Input image must be RGB
printf("Image size (width x height): %i x %i\n\n", width, height);
// Convert RGB to grayscale not using device
uint8_t * correctOutPixels= (uint8_t *)malloc(width * height);
convertRgb2Gray(inPixels, width, height, correctOutPixels);
// Convert RGB to grayscale using device
uint8_t * outPixels= (uint8_t *)malloc(width * height);
dim3 blockSize(32, 32); // Default
if (argc == 5)
{
blockSize.x = atoi(argv[3]);
blockSize.y = atoi(argv[4]);
}
convertRgb2Gray(inPixels, width, height, outPixels, true, blockSize);
// Compute mean absolute error between host result and device result
float err = computeError(outPixels, correctOutPixels, width * height);
printf("Error between device result and host result: %f\n", err);
// Write results to files
char * outFileNameBase = strtok(argv[2], "."); // Get rid of extension
writePnm(correctOutPixels, 1, width, height, concatStr(outFileNameBase, "_host.pnm"));
writePnm(outPixels, 1, width, height, concatStr(outFileNameBase, "_device.pnm"));
// Free memories
free(inPixels);
free(outPixels);
} | code for sm_80
Function : _Z21convertRgb2GrayKernelPhiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R0, R3, c[0x0][0x168], R0 ; /* 0x00005a0003007a24 */
/* 0x000fe200078e0200 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00c0*/ IMAD R3, R0, 0x3, RZ ; /* 0x0000000300037824 */
/* 0x000fca00078e02ff */
/*00d0*/ IADD3 R2, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003027a10 */
/* 0x000fc80007f1e0ff */
/*00e0*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P0 ; /* 0x0000590003037a11 */
/* 0x000fca00000f0eff */
/*00f0*/ LDG.E.U8 R7, [R2.64+0x1] ; /* 0x0000010402077981 */
/* 0x000ea8000c1e1100 */
/*0100*/ LDG.E.U8 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ee8000c1e1100 */
/*0110*/ LDG.E.U8 R8, [R2.64+0x2] ; /* 0x0000020402087981 */
/* 0x000f22000c1e1100 */
/*0120*/ IADD3 R4, P0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000047a10 */
/* 0x000fe20007f1e0ff */
/*0130*/ I2F.U16 R7, R7 ; /* 0x0000000700077306 */
/* 0x004e300000101000 */
/*0140*/ I2F.U16 R6, R6 ; /* 0x0000000600067306 */
/* 0x008e700000101000 */
/*0150*/ I2F.U16 R8, R8 ; /* 0x0000000800087306 */
/* 0x010ea20000101000 */
/*0160*/ FMUL R5, R7, 0.58700001239776611328 ; /* 0x3f1645a207057820 */
/* 0x001fc80000400000 */
/*0170*/ FFMA R5, R6, 0.29899999499320983887, R5 ; /* 0x3e99168706057823 */
/* 0x002fc80000000005 */
/*0180*/ FFMA R9, R8, 0.11400000005960464478, R5 ; /* 0x3de978d508097823 */
/* 0x004fe20000000005 */
/*0190*/ LEA.HI.X.SX32 R5, R0, c[0x0][0x174], 0x1, P0 ; /* 0x00005d0000057a11 */
/* 0x000fca00000f0eff */
/*01a0*/ F2I.U32.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e24000020f000 */
/*01b0*/ STG.E.U8 [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x001fe2000c101104 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdint.h>
#define CHECK(call)\
{\
const cudaError_t error = call;\
if (error != cudaSuccess)\
{\
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__);\
fprintf(stderr, "code: %d, reason: %s\n", error,\
cudaGetErrorString(error));\
exit(EXIT_FAILURE);\
}\
}
struct GpuTimer
{
cudaEvent_t start;
cudaEvent_t stop;
GpuTimer()
{
cudaEventCreate(&start);
cudaEventCreate(&stop);
}
~GpuTimer()
{
cudaEventDestroy(start);
cudaEventDestroy(stop);
}
void Start()
{
cudaEventRecord(start, 0);
cudaEventSynchronize(start);
}
void Stop()
{
cudaEventRecord(stop, 0);
}
float Elapsed()
{
float elapsed;
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
void readPnm(char * fileName,
int &numChannels, int &width, int &height, uint8_t * &pixels)
{
FILE * f = fopen(fileName, "r");
if (f == NULL)
{
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
char type[3];
fscanf(f, "%s", type);
if (strcmp(type, "P2") == 0)
numChannels = 1;
else if (strcmp(type, "P3") == 0)
numChannels = 3;
else // In this exercise, we don't touch other types
{
fclose(f);
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
fscanf(f, "%i", &width);
fscanf(f, "%i", &height);
int max_val;
fscanf(f, "%i", &max_val);
if (max_val > 255) // In this exercise, we assume 1 byte per value
{
fclose(f);
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
pixels = (uint8_t *)malloc(width * height * numChannels);
for (int i = 0; i < width * height * numChannels; i++)
fscanf(f, "%hhu", &pixels[i]);
fclose(f);
}
void writePnm(uint8_t * pixels, int numChannels, int width, int height,
char * fileName)
{
FILE * f = fopen(fileName, "w");
if (f == NULL)
{
printf("Cannot write %s\n", fileName);
exit(EXIT_FAILURE);
}
if (numChannels == 1)
fprintf(f, "P2\n");
else if (numChannels == 3)
fprintf(f, "P3\n");
else
{
fclose(f);
printf("Cannot write %s\n", fileName);
exit(EXIT_FAILURE);
}
fprintf(f, "%i\n%i\n255\n", width, height);
for (int i = 0; i < width * height * numChannels; i++)
fprintf(f, "%hhu\n", pixels[i]);
fclose(f);
}
__global__ void convertRgb2GrayKernel(uint8_t * inPixels, int width, int height,
uint8_t * outPixels)
{
// TODO
int ix = blockIdx.x * blockDim.x + threadIdx.x;
int iy = blockIdx.y * blockDim.y + threadIdx.y;
if (ix < width && iy < height)
{
int i = iy * width + ix;
uint8_t r = inPixels[i * 3];
uint8_t g = inPixels[i * 3 + 1];
uint8_t b = inPixels[i * 3 + 2];
outPixels[i] = 0.299f * r + 0.587f * g + 0.114f * b;
}
}
void convertRgb2Gray(uint8_t * inPixels, int width, int height,
uint8_t * outPixels,
bool useDevice=false, dim3 blockSize=dim3(1))
{
GpuTimer timer;
timer.Start();
if (useDevice == false)
{
for (int r = 0; r < height; r++)
{
for (int c = 0; c < width; c++)
{
int i = r * width + c;
uint8_t r = inPixels[i * 3];
uint8_t g = inPixels[i * 3 + 1];
uint8_t b = inPixels[i * 3 + 2];
outPixels[i] = 0.299f * r + 0.587f * g + 0.114f * b;
}
}
}
else // use device
{
int numChannels = 3;
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, 0);
printf("GPU name: %s\n", devProp.name);
printf("GPU compute capability: %d.%d\n", devProp.major, devProp.minor);
// TODO: Allocate device memories
uint8_t *d_inPixels, * d_outPixels;
CHECK(cudaMalloc(&d_inPixels, height * width * numChannels * sizeof(uint8_t)));
CHECK(cudaMalloc(&d_outPixels, height * width * sizeof(uint8_t)));
// TODO: Copy data to device memories
CHECK(cudaMemcpy(d_inPixels, inPixels, height * width * numChannels * sizeof(uint8_t), cudaMemcpyHostToDevice));
// TODO: Set grid size and call kernel (remember to check kernel error)
dim3 gridSize((width - 1)/blockSize.x + 1, (height - 1)/blockSize.y + 1);
convertRgb2GrayKernel<<<gridSize, blockSize>>>(d_inPixels, width, height, d_outPixels);
cudaError_t errSync = cudaGetLastError();
cudaError_t errAsync = cudaDeviceSynchronize();
if (errSync != cudaSuccess)
printf("Sync kernel error: %s\n", cudaGetErrorString(errSync));
if (errAsync != cudaSuccess)
printf("Async kernel error: %s\n", cudaGetErrorString(errAsync));
// TODO: Copy result from device memories
CHECK(cudaMemcpy(outPixels, d_outPixels, height * width * sizeof(uint8_t), cudaMemcpyDeviceToHost));
// TODO: Free device memories
CHECK(cudaFree(d_inPixels));
CHECK(cudaFree(d_outPixels));
}
timer.Stop();
float time = timer.Elapsed();
printf("Processing time (%s): %f ms\n\n",
useDevice == true? "use device" : "use host", time);
}
float computeError(uint8_t * a1, uint8_t * a2, int n)
{
float err = 0;
for (int i = 0; i < n; i++)
err += abs((int)a1[i] - (int)a2[i]);
err /= n;
return err;
}
char * concatStr(const char * s1, const char * s2)
{
char * result = (char *)malloc(strlen(s1) + strlen(s2) + 1);
strcpy(result, s1);
strcat(result, s2);
return result;
}
int main(int argc, char ** argv)
{
if (argc != 3 && argc != 5)
{
printf("The number of arguments is invalid\n");
return EXIT_FAILURE;
}
// Read input RGB image file
int numChannels, width, height;
uint8_t * inPixels;
readPnm(argv[1], numChannels, width, height, inPixels);
if (numChannels != 3)
return EXIT_FAILURE; // Input image must be RGB
printf("Image size (width x height): %i x %i\n\n", width, height);
// Convert RGB to grayscale not using device
uint8_t * correctOutPixels= (uint8_t *)malloc(width * height);
convertRgb2Gray(inPixels, width, height, correctOutPixels);
// Convert RGB to grayscale using device
uint8_t * outPixels= (uint8_t *)malloc(width * height);
dim3 blockSize(32, 32); // Default
if (argc == 5)
{
blockSize.x = atoi(argv[3]);
blockSize.y = atoi(argv[4]);
}
convertRgb2Gray(inPixels, width, height, outPixels, true, blockSize);
// Compute mean absolute error between host result and device result
float err = computeError(outPixels, correctOutPixels, width * height);
printf("Error between device result and host result: %f\n", err);
// Write results to files
char * outFileNameBase = strtok(argv[2], "."); // Get rid of extension
writePnm(correctOutPixels, 1, width, height, concatStr(outFileNameBase, "_host.pnm"));
writePnm(outPixels, 1, width, height, concatStr(outFileNameBase, "_device.pnm"));
// Free memories
free(inPixels);
free(outPixels);
} | .file "tmpxft_00057e8d_00000000-6_bt01_p1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "Cannot read %s\n"
.LC2:
.string "%s"
.LC3:
.string "P2"
.LC4:
.string "P3"
.LC5:
.string "%i"
.LC6:
.string "%hhu"
.text
.globl _Z7readPnmPcRiS0_S0_RPh
.type _Z7readPnmPcRiS0_S0_RPh, @function
_Z7readPnmPcRiS0_S0_RPh:
.LFB2066:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 8(%rsp)
movq %rsi, %r12
movq %rdx, %r13
movq %rcx, %r14
movq %r8, %r15
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L14
movq %rax, %rbp
leaq 21(%rsp), %rbx
movq %rbx, %rdx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call strcmp@PLT
testl %eax, %eax
je .L10
movq %rbx, %rdi
leaq .LC4(%rip), %rsi
call strcmp@PLT
testl %eax, %eax
jne .L15
movl $3, %eax
jmp .L5
.L14:
movq 8(%rsp), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L15:
movq %rbp, %rdi
call fclose@PLT
movq 8(%rsp), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L10:
movl $1, %eax
.L5:
movl %eax, (%r12)
movq %r13, %rdx
leaq .LC5(%rip), %rbx
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq %r14, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq 16(%rsp), %rdx
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $255, 16(%rsp)
jg .L16
movl 0(%r13), %edi
imull (%r14), %edi
imull (%r12), %edi
movslq %edi, %rdi
call malloc@PLT
movq %rax, (%r15)
movl 0(%r13), %eax
imull (%r14), %eax
imull (%r12), %eax
testl %eax, %eax
jle .L7
movl $0, %ebx
.L8:
movq %rbx, %rdx
addq (%r15), %rdx
leaq .LC6(%rip), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $1, %rbx
movl 0(%r13), %eax
imull (%r14), %eax
imull (%r12), %eax
cmpl %ebx, %eax
jg .L8
.L7:
movq %rbp, %rdi
call fclose@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movq %rbp, %rdi
call fclose@PLT
movq 8(%rsp), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2066:
.size _Z7readPnmPcRiS0_S0_RPh, .-_Z7readPnmPcRiS0_S0_RPh
.section .rodata.str1.1
.LC7:
.string "w"
.LC8:
.string "Cannot write %s\n"
.LC9:
.string "P2\n"
.LC10:
.string "P3\n"
.LC11:
.string "%i\n%i\n255\n"
.LC12:
.string "%hhu\n"
.text
.globl _Z8writePnmPhiiiPc
.type _Z8writePnmPhiiiPc, @function
_Z8writePnmPhiiiPc:
.LFB2067:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r12
movl %esi, %r13d
movl %edx, %ebx
movl %ecx, %r14d
movq %r8, %r15
leaq .LC7(%rip), %rsi
movq %r8, %rdi
call fopen@PLT
testq %rax, %rax
je .L27
movq %rax, %rbp
cmpl $1, %r13d
je .L28
cmpl $3, %r13d
jne .L22
leaq .LC10(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L21:
movl %r14d, %r8d
movl %ebx, %ecx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
imull %r14d, %ebx
imull %r13d, %ebx
movl %ebx, %r8d
testl %ebx, %ebx
jle .L23
movq %r12, %rbx
movslq %r8d, %r8
addq %r8, %r12
leaq .LC12(%rip), %r13
.L24:
movzbl (%rbx), %ecx
movq %r13, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpq %r12, %rbx
jne .L24
.L23:
movq %rbp, %rdi
call fclose@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq %r15, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L28:
leaq .LC9(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L21
.L22:
movq %rax, %rdi
call fclose@PLT
movq %r15, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2067:
.size _Z8writePnmPhiiiPc, .-_Z8writePnmPhiiiPc
.globl _Z12computeErrorPhS_i
.type _Z12computeErrorPhS_i, @function
_Z12computeErrorPhS_i:
.LFB2069:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L32
movslq %edx, %r9
movl $0, %ecx
pxor %xmm0, %xmm0
.L31:
movzbl (%rdi,%rcx), %eax
movzbl (%rsi,%rcx), %r8d
subl %r8d, %eax
movl %eax, %r8d
negl %r8d
cmovns %r8d, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
addss %xmm1, %xmm0
addq $1, %rcx
cmpq %r9, %rcx
jne .L31
.L30:
pxor %xmm1, %xmm1
cvtsi2ssl %edx, %xmm1
divss %xmm1, %xmm0
ret
.L32:
pxor %xmm0, %xmm0
jmp .L30
.cfi_endproc
.LFE2069:
.size _Z12computeErrorPhS_i, .-_Z12computeErrorPhS_i
.globl _Z9concatStrPKcS0_
.type _Z9concatStrPKcS0_, @function
_Z9concatStrPKcS0_:
.LFB2070:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movq %rsi, %rbp
call strlen@PLT
movq %rax, %rbx
movq %rbp, %rdi
call strlen@PLT
leaq 1(%rbx,%rax), %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r13, %rdx
movq %r12, %rsi
movq %rax, %rdi
call __strcpy_chk@PLT
movq %r13, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call __strcat_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2070:
.size _Z9concatStrPKcS0_, .-_Z9concatStrPKcS0_
.globl _Z45__device_stub__Z21convertRgb2GrayKernelPhiiS_PhiiS_
.type _Z45__device_stub__Z21convertRgb2GrayKernelPhiiS_PhiiS_, @function
_Z45__device_stub__Z21convertRgb2GrayKernelPhiiS_PhiiS_:
.LFB2096:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L41
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21convertRgb2GrayKernelPhiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z45__device_stub__Z21convertRgb2GrayKernelPhiiS_PhiiS_, .-_Z45__device_stub__Z21convertRgb2GrayKernelPhiiS_PhiiS_
.globl _Z21convertRgb2GrayKernelPhiiS_
.type _Z21convertRgb2GrayKernelPhiiS_, @function
_Z21convertRgb2GrayKernelPhiiS_:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z21convertRgb2GrayKernelPhiiS_PhiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z21convertRgb2GrayKernelPhiiS_, .-_Z21convertRgb2GrayKernelPhiiS_
.section .rodata.str1.1
.LC14:
.string "use device"
.LC15:
.string "use host"
.LC19:
.string "GPU name: %s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC20:
.string "GPU compute capability: %d.%d\n"
.align 8
.LC21:
.string "/home/ubuntu/Datasets/stackv2/train-structured/hmhuan/PG_GPU/master/assignment/BT01/1612858/bt01_p1.cu"
.section .rodata.str1.1
.LC22:
.string "Error: %s:%d, "
.LC23:
.string "code: %d, reason: %s\n"
.LC24:
.string "Sync kernel error: %s\n"
.LC25:
.string "Async kernel error: %s\n"
.LC26:
.string "Processing time (%s): %f ms\n\n"
.text
.globl _Z15convertRgb2GrayPhiiS_b4dim3
.type _Z15convertRgb2GrayPhiiS_b4dim3, @function
_Z15convertRgb2GrayPhiiS_b4dim3:
.LFB2068:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA2068
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1112, %rsp
.cfi_def_cfa_offset 1168
movq %rdi, %rbp
movl %esi, %ebx
movl %edx, %r12d
movq %rcx, %r13
movl %r8d, %r14d
movq %fs:40, %rax
movq %rax, 1096(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rdi
.LEHB0:
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
.LEHE0:
movl $0, %esi
movq 48(%rsp), %rdi
.LEHB1:
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
testb %r14b, %r14b
jne .L45
testl %r12d, %r12d
jle .L46
movl $0, %edi
movl $0, %r8d
movslq %ebx, %r9
movss .LC16(%rip), %xmm4
movss .LC17(%rip), %xmm3
movss .LC18(%rip), %xmm2
jmp .L47
.L49:
leal (%rdi,%rdi,2), %eax
cltq
addq %rbp, %rax
movslq %edi, %rcx
leaq 0(%r13,%rcx), %rdx
addq %r9, %rcx
leaq (%rcx,%rcx,2), %rsi
addq %rbp, %rsi
.L48:
movzbl (%rax), %ecx
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
mulss %xmm4, %xmm0
movzbl 1(%rax), %ecx
pxor %xmm1, %xmm1
cvtsi2ssl %ecx, %xmm1
mulss %xmm3, %xmm1
addss %xmm1, %xmm0
movzbl 2(%rax), %ecx
pxor %xmm1, %xmm1
cvtsi2ssl %ecx, %xmm1
mulss %xmm2, %xmm1
addss %xmm1, %xmm0
cvttss2sil %xmm0, %ecx
movb %cl, (%rdx)
addq $3, %rax
addq $1, %rdx
cmpq %rsi, %rax
jne .L48
.L50:
addl $1, %r8d
addl %ebx, %edi
cmpl %r8d, %r12d
je .L46
.L47:
testl %ebx, %ebx
jg .L49
jmp .L50
.L45:
leaq 64(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
leaq 64(%rsp), %rdx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 428(%rsp), %ecx
movl 424(%rsp), %edx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %r15d
imull %ebx, %r15d
leal (%r15,%r15,2), %eax
cltq
movq %rax, (%rsp)
leaq 16(%rsp), %rdi
movq %rax, %rsi
call cudaMalloc@PLT
movl %eax, 12(%rsp)
testl %eax, %eax
jne .L69
movslq %r15d, %r15
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
jmp .L70
.L69:
movl $170, %r8d
leaq .LC21(%rip), %rcx
leaq .LC22(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 12(%rsp), %ebx
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC23(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L70:
movl %eax, 12(%rsp)
testl %eax, %eax
jne .L71
movl $1, %ecx
movq (%rsp), %rdx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
jmp .L72
.L71:
movl $171, %r8d
leaq .LC21(%rip), %rcx
leaq .LC22(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 12(%rsp), %ebx
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC23(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L72:
movl %eax, %ebp
testl %eax, %eax
jne .L73
leal -1(%r12), %eax
movl $0, %edx
divl 1172(%rsp)
leal 1(%rax), %ecx
leal -1(%rbx), %eax
movl $0, %edx
divl 1168(%rsp)
addl $1, %eax
movl %eax, 36(%rsp)
movl %ecx, 40(%rsp)
movl $1, 44(%rsp)
movl 1176(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 1168(%rsp), %rdx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
jmp .L74
.L73:
movl $174, %r8d
leaq .LC21(%rip), %rcx
leaq .LC22(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebp, %ecx
leaq .LC23(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L74:
testl %eax, %eax
jne .L54
movq 24(%rsp), %rcx
movl %r12d, %edx
movl %ebx, %esi
movq 16(%rsp), %rdi
call _Z45__device_stub__Z21convertRgb2GrayKernelPhiiS_PhiiS_
.L54:
call cudaGetLastError@PLT
movl %eax, %ebp
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %ebp, %ebp
jne .L75
.L55:
testl %ebx, %ebx
je .L56
movl %ebx, %edi
call cudaGetErrorString@PLT
jmp .L76
.L75:
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L55
.L76:
movq %rax, %rdx
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L56:
movl $2, %ecx
movq %r15, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L77
movq 16(%rsp), %rdi
call cudaFree@PLT
jmp .L78
.L77:
movl $186, %r8d
leaq .LC21(%rip), %rcx
leaq .LC22(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC23(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L78:
movl %eax, %ebx
testl %eax, %eax
jne .L79
movq 24(%rsp), %rdi
call cudaFree@PLT
jmp .L80
.L79:
movl $189, %r8d
leaq .LC21(%rip), %rcx
leaq .LC22(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC23(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L80:
movl %eax, %ebx
testl %eax, %eax
jne .L81
.L46:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
jmp .L82
.L81:
movl $190, %r8d
leaq .LC21(%rip), %rcx
leaq .LC22(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC23(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L82:
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 36(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
testb %r14b, %r14b
leaq .LC15(%rip), %rdx
leaq .LC14(%rip), %rax
cmovne %rax, %rdx
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.LEHE1:
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq 1096(%rsp), %rax
subq %fs:40, %rax
jne .L83
addq $1112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
endbr64
movq %rax, %rbx
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq 1096(%rsp), %rax
subq %fs:40, %rax
je .L62
call __stack_chk_fail@PLT
.L62:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L83:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2068:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA2068:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE2068-.LLSDACSB2068
.LLSDACSB2068:
.uleb128 .LEHB0-.LFB2068
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB2068
.uleb128 .LEHE1-.LEHB1
.uleb128 .L65-.LFB2068
.uleb128 0
.uleb128 .LEHB2-.LFB2068
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE2068:
.text
.size _Z15convertRgb2GrayPhiiS_b4dim3, .-_Z15convertRgb2GrayPhiiS_b4dim3
.section .rodata.str1.8
.align 8
.LC27:
.string "The number of arguments is invalid\n"
.align 8
.LC28:
.string "Image size (width x height): %i x %i\n\n"
.align 8
.LC29:
.string "Error between device result and host result: %f\n"
.section .rodata.str1.1
.LC30:
.string "."
.LC31:
.string "_host.pnm"
.LC32:
.string "_device.pnm"
.text
.globl main
.type main, @function
main:
.LFB2071:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leal -3(%rdi), %eax
testl $-3, %eax
jne .L91
movl %edi, %ebx
movq %rsi, %rbp
leaq 12(%rsp), %rcx
leaq 8(%rsp), %rdx
leaq 4(%rsp), %rsi
movq 8(%rbp), %rdi
leaq 16(%rsp), %r8
call _Z7readPnmPcRiS0_S0_RPh
movl $1, %eax
cmpl $3, 4(%rsp)
je .L92
.L84:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L93
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L91:
.cfi_restore_state
leaq .LC27(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L84
.L92:
movl 12(%rsp), %ecx
movl 8(%rsp), %edx
leaq .LC28(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 8(%rsp), %r12d
movl 12(%rsp), %r15d
movl %r12d, %edi
imull %r15d, %edi
movslq %edi, %rdi
call malloc@PLT
movq %rax, %r13
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movq 16(%rsp), %r14
subq $16, %rsp
.cfi_def_cfa_offset 128
movq 44(%rsp), %rax
movq %rax, (%rsp)
movl $1, 8(%rsp)
movl $0, %r8d
movq %r13, %rcx
movl %r15d, %edx
movl %r12d, %esi
movq %r14, %rdi
call _Z15convertRgb2GrayPhiiS_b4dim3
movl 24(%rsp), %edi
imull 28(%rsp), %edi
movslq %edi, %rdi
call malloc@PLT
movq %rax, %r12
movl $32, 44(%rsp)
movl $32, 48(%rsp)
movl $1, 52(%rsp)
addq $16, %rsp
.cfi_def_cfa_offset 112
cmpl $5, %ebx
je .L94
.L87:
subq $16, %rsp
.cfi_def_cfa_offset 128
movq 44(%rsp), %rax
movq %rax, (%rsp)
movl 52(%rsp), %eax
movl %eax, 8(%rsp)
movl $1, %r8d
movq %r12, %rcx
movl 28(%rsp), %edx
movl 24(%rsp), %esi
movq %r14, %rdi
call _Z15convertRgb2GrayPhiiS_b4dim3
movl 24(%rsp), %edx
imull 28(%rsp), %edx
movq %r13, %rsi
movq %r12, %rdi
call _Z12computeErrorPhS_i
addq $16, %rsp
.cfi_def_cfa_offset 112
cvtss2sd %xmm0, %xmm0
leaq .LC29(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rbp), %rdi
leaq .LC30(%rip), %rsi
call strtok@PLT
movq %rax, %rbx
leaq .LC31(%rip), %rsi
movq %rax, %rdi
call _Z9concatStrPKcS0_
movq %rax, %r8
movl 12(%rsp), %ecx
movl 8(%rsp), %edx
movl $1, %esi
movq %r13, %rdi
call _Z8writePnmPhiiiPc
leaq .LC32(%rip), %rsi
movq %rbx, %rdi
call _Z9concatStrPKcS0_
movq %rax, %r8
movl 12(%rsp), %ecx
movl 8(%rsp), %edx
movl $1, %esi
movq %r12, %rdi
call _Z8writePnmPhiiiPc
movq %r14, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movl $0, %eax
jmp .L84
.L94:
movq 24(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 28(%rsp)
movq 32(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 32(%rsp)
jmp .L87
.L93:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC33:
.string "_Z21convertRgb2GrayKernelPhiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC33(%rip), %rdx
movq %rdx, %rcx
leaq _Z21convertRgb2GrayKernelPhiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC16:
.long 1050220167
.align 4
.LC17:
.long 1058424226
.align 4
.LC18:
.long 1038710997
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdint.h>
#define CHECK(call)\
{\
const cudaError_t error = call;\
if (error != cudaSuccess)\
{\
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__);\
fprintf(stderr, "code: %d, reason: %s\n", error,\
cudaGetErrorString(error));\
exit(EXIT_FAILURE);\
}\
}
struct GpuTimer
{
cudaEvent_t start;
cudaEvent_t stop;
GpuTimer()
{
cudaEventCreate(&start);
cudaEventCreate(&stop);
}
~GpuTimer()
{
cudaEventDestroy(start);
cudaEventDestroy(stop);
}
void Start()
{
cudaEventRecord(start, 0);
cudaEventSynchronize(start);
}
void Stop()
{
cudaEventRecord(stop, 0);
}
float Elapsed()
{
float elapsed;
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
void readPnm(char * fileName,
int &numChannels, int &width, int &height, uint8_t * &pixels)
{
FILE * f = fopen(fileName, "r");
if (f == NULL)
{
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
char type[3];
fscanf(f, "%s", type);
if (strcmp(type, "P2") == 0)
numChannels = 1;
else if (strcmp(type, "P3") == 0)
numChannels = 3;
else // In this exercise, we don't touch other types
{
fclose(f);
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
fscanf(f, "%i", &width);
fscanf(f, "%i", &height);
int max_val;
fscanf(f, "%i", &max_val);
if (max_val > 255) // In this exercise, we assume 1 byte per value
{
fclose(f);
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
pixels = (uint8_t *)malloc(width * height * numChannels);
for (int i = 0; i < width * height * numChannels; i++)
fscanf(f, "%hhu", &pixels[i]);
fclose(f);
}
void writePnm(uint8_t * pixels, int numChannels, int width, int height,
char * fileName)
{
FILE * f = fopen(fileName, "w");
if (f == NULL)
{
printf("Cannot write %s\n", fileName);
exit(EXIT_FAILURE);
}
if (numChannels == 1)
fprintf(f, "P2\n");
else if (numChannels == 3)
fprintf(f, "P3\n");
else
{
fclose(f);
printf("Cannot write %s\n", fileName);
exit(EXIT_FAILURE);
}
fprintf(f, "%i\n%i\n255\n", width, height);
for (int i = 0; i < width * height * numChannels; i++)
fprintf(f, "%hhu\n", pixels[i]);
fclose(f);
}
__global__ void convertRgb2GrayKernel(uint8_t * inPixels, int width, int height,
uint8_t * outPixels)
{
// TODO
int ix = blockIdx.x * blockDim.x + threadIdx.x;
int iy = blockIdx.y * blockDim.y + threadIdx.y;
if (ix < width && iy < height)
{
int i = iy * width + ix;
uint8_t r = inPixels[i * 3];
uint8_t g = inPixels[i * 3 + 1];
uint8_t b = inPixels[i * 3 + 2];
outPixels[i] = 0.299f * r + 0.587f * g + 0.114f * b;
}
}
void convertRgb2Gray(uint8_t * inPixels, int width, int height,
uint8_t * outPixels,
bool useDevice=false, dim3 blockSize=dim3(1))
{
GpuTimer timer;
timer.Start();
if (useDevice == false)
{
for (int r = 0; r < height; r++)
{
for (int c = 0; c < width; c++)
{
int i = r * width + c;
uint8_t r = inPixels[i * 3];
uint8_t g = inPixels[i * 3 + 1];
uint8_t b = inPixels[i * 3 + 2];
outPixels[i] = 0.299f * r + 0.587f * g + 0.114f * b;
}
}
}
else // use device
{
int numChannels = 3;
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, 0);
printf("GPU name: %s\n", devProp.name);
printf("GPU compute capability: %d.%d\n", devProp.major, devProp.minor);
// TODO: Allocate device memories
uint8_t *d_inPixels, * d_outPixels;
CHECK(cudaMalloc(&d_inPixels, height * width * numChannels * sizeof(uint8_t)));
CHECK(cudaMalloc(&d_outPixels, height * width * sizeof(uint8_t)));
// TODO: Copy data to device memories
CHECK(cudaMemcpy(d_inPixels, inPixels, height * width * numChannels * sizeof(uint8_t), cudaMemcpyHostToDevice));
// TODO: Set grid size and call kernel (remember to check kernel error)
dim3 gridSize((width - 1)/blockSize.x + 1, (height - 1)/blockSize.y + 1);
convertRgb2GrayKernel<<<gridSize, blockSize>>>(d_inPixels, width, height, d_outPixels);
cudaError_t errSync = cudaGetLastError();
cudaError_t errAsync = cudaDeviceSynchronize();
if (errSync != cudaSuccess)
printf("Sync kernel error: %s\n", cudaGetErrorString(errSync));
if (errAsync != cudaSuccess)
printf("Async kernel error: %s\n", cudaGetErrorString(errAsync));
// TODO: Copy result from device memories
CHECK(cudaMemcpy(outPixels, d_outPixels, height * width * sizeof(uint8_t), cudaMemcpyDeviceToHost));
// TODO: Free device memories
CHECK(cudaFree(d_inPixels));
CHECK(cudaFree(d_outPixels));
}
timer.Stop();
float time = timer.Elapsed();
printf("Processing time (%s): %f ms\n\n",
useDevice == true? "use device" : "use host", time);
}
float computeError(uint8_t * a1, uint8_t * a2, int n)
{
float err = 0;
for (int i = 0; i < n; i++)
err += abs((int)a1[i] - (int)a2[i]);
err /= n;
return err;
}
char * concatStr(const char * s1, const char * s2)
{
char * result = (char *)malloc(strlen(s1) + strlen(s2) + 1);
strcpy(result, s1);
strcat(result, s2);
return result;
}
int main(int argc, char ** argv)
{
if (argc != 3 && argc != 5)
{
printf("The number of arguments is invalid\n");
return EXIT_FAILURE;
}
// Read input RGB image file
int numChannels, width, height;
uint8_t * inPixels;
readPnm(argv[1], numChannels, width, height, inPixels);
if (numChannels != 3)
return EXIT_FAILURE; // Input image must be RGB
printf("Image size (width x height): %i x %i\n\n", width, height);
// Convert RGB to grayscale not using device
uint8_t * correctOutPixels= (uint8_t *)malloc(width * height);
convertRgb2Gray(inPixels, width, height, correctOutPixels);
// Convert RGB to grayscale using device
uint8_t * outPixels= (uint8_t *)malloc(width * height);
dim3 blockSize(32, 32); // Default
if (argc == 5)
{
blockSize.x = atoi(argv[3]);
blockSize.y = atoi(argv[4]);
}
convertRgb2Gray(inPixels, width, height, outPixels, true, blockSize);
// Compute mean absolute error between host result and device result
float err = computeError(outPixels, correctOutPixels, width * height);
printf("Error between device result and host result: %f\n", err);
// Write results to files
char * outFileNameBase = strtok(argv[2], "."); // Get rid of extension
writePnm(correctOutPixels, 1, width, height, concatStr(outFileNameBase, "_host.pnm"));
writePnm(outPixels, 1, width, height, concatStr(outFileNameBase, "_device.pnm"));
// Free memories
free(inPixels);
free(outPixels);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdint.h>
#define CHECK(call)\
{\
const hipError_t error = call;\
if (error != hipSuccess)\
{\
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__);\
fprintf(stderr, "code: %d, reason: %s\n", error,\
hipGetErrorString(error));\
exit(EXIT_FAILURE);\
}\
}
struct GpuTimer
{
hipEvent_t start;
hipEvent_t stop;
GpuTimer()
{
hipEventCreate(&start);
hipEventCreate(&stop);
}
~GpuTimer()
{
hipEventDestroy(start);
hipEventDestroy(stop);
}
void Start()
{
hipEventRecord(start, 0);
hipEventSynchronize(start);
}
void Stop()
{
hipEventRecord(stop, 0);
}
float Elapsed()
{
float elapsed;
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
void readPnm(char * fileName,
int &numChannels, int &width, int &height, uint8_t * &pixels)
{
FILE * f = fopen(fileName, "r");
if (f == NULL)
{
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
char type[3];
fscanf(f, "%s", type);
if (strcmp(type, "P2") == 0)
numChannels = 1;
else if (strcmp(type, "P3") == 0)
numChannels = 3;
else // In this exercise, we don't touch other types
{
fclose(f);
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
fscanf(f, "%i", &width);
fscanf(f, "%i", &height);
int max_val;
fscanf(f, "%i", &max_val);
if (max_val > 255) // In this exercise, we assume 1 byte per value
{
fclose(f);
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
pixels = (uint8_t *)malloc(width * height * numChannels);
for (int i = 0; i < width * height * numChannels; i++)
fscanf(f, "%hhu", &pixels[i]);
fclose(f);
}
void writePnm(uint8_t * pixels, int numChannels, int width, int height,
char * fileName)
{
FILE * f = fopen(fileName, "w");
if (f == NULL)
{
printf("Cannot write %s\n", fileName);
exit(EXIT_FAILURE);
}
if (numChannels == 1)
fprintf(f, "P2\n");
else if (numChannels == 3)
fprintf(f, "P3\n");
else
{
fclose(f);
printf("Cannot write %s\n", fileName);
exit(EXIT_FAILURE);
}
fprintf(f, "%i\n%i\n255\n", width, height);
for (int i = 0; i < width * height * numChannels; i++)
fprintf(f, "%hhu\n", pixels[i]);
fclose(f);
}
__global__ void convertRgb2GrayKernel(uint8_t * inPixels, int width, int height,
uint8_t * outPixels)
{
// TODO
int ix = blockIdx.x * blockDim.x + threadIdx.x;
int iy = blockIdx.y * blockDim.y + threadIdx.y;
if (ix < width && iy < height)
{
int i = iy * width + ix;
uint8_t r = inPixels[i * 3];
uint8_t g = inPixels[i * 3 + 1];
uint8_t b = inPixels[i * 3 + 2];
outPixels[i] = 0.299f * r + 0.587f * g + 0.114f * b;
}
}
void convertRgb2Gray(uint8_t * inPixels, int width, int height,
uint8_t * outPixels,
bool useDevice=false, dim3 blockSize=dim3(1))
{
GpuTimer timer;
timer.Start();
if (useDevice == false)
{
for (int r = 0; r < height; r++)
{
for (int c = 0; c < width; c++)
{
int i = r * width + c;
uint8_t r = inPixels[i * 3];
uint8_t g = inPixels[i * 3 + 1];
uint8_t b = inPixels[i * 3 + 2];
outPixels[i] = 0.299f * r + 0.587f * g + 0.114f * b;
}
}
}
else // use device
{
int numChannels = 3;
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, 0);
printf("GPU name: %s\n", devProp.name);
printf("GPU compute capability: %d.%d\n", devProp.major, devProp.minor);
// TODO: Allocate device memories
uint8_t *d_inPixels, * d_outPixels;
CHECK(hipMalloc(&d_inPixels, height * width * numChannels * sizeof(uint8_t)));
CHECK(hipMalloc(&d_outPixels, height * width * sizeof(uint8_t)));
// TODO: Copy data to device memories
CHECK(hipMemcpy(d_inPixels, inPixels, height * width * numChannels * sizeof(uint8_t), hipMemcpyHostToDevice));
// TODO: Set grid size and call kernel (remember to check kernel error)
dim3 gridSize((width - 1)/blockSize.x + 1, (height - 1)/blockSize.y + 1);
convertRgb2GrayKernel<<<gridSize, blockSize>>>(d_inPixels, width, height, d_outPixels);
hipError_t errSync = hipGetLastError();
hipError_t errAsync = hipDeviceSynchronize();
if (errSync != hipSuccess)
printf("Sync kernel error: %s\n", hipGetErrorString(errSync));
if (errAsync != hipSuccess)
printf("Async kernel error: %s\n", hipGetErrorString(errAsync));
// TODO: Copy result from device memories
CHECK(hipMemcpy(outPixels, d_outPixels, height * width * sizeof(uint8_t), hipMemcpyDeviceToHost));
// TODO: Free device memories
CHECK(hipFree(d_inPixels));
CHECK(hipFree(d_outPixels));
}
timer.Stop();
float time = timer.Elapsed();
printf("Processing time (%s): %f ms\n\n",
useDevice == true? "use device" : "use host", time);
}
float computeError(uint8_t * a1, uint8_t * a2, int n)
{
float err = 0;
for (int i = 0; i < n; i++)
err += abs((int)a1[i] - (int)a2[i]);
err /= n;
return err;
}
char * concatStr(const char * s1, const char * s2)
{
char * result = (char *)malloc(strlen(s1) + strlen(s2) + 1);
strcpy(result, s1);
strcat(result, s2);
return result;
}
int main(int argc, char ** argv)
{
if (argc != 3 && argc != 5)
{
printf("The number of arguments is invalid\n");
return EXIT_FAILURE;
}
// Read input RGB image file
int numChannels, width, height;
uint8_t * inPixels;
readPnm(argv[1], numChannels, width, height, inPixels);
if (numChannels != 3)
return EXIT_FAILURE; // Input image must be RGB
printf("Image size (width x height): %i x %i\n\n", width, height);
// Convert RGB to grayscale not using device
uint8_t * correctOutPixels= (uint8_t *)malloc(width * height);
convertRgb2Gray(inPixels, width, height, correctOutPixels);
// Convert RGB to grayscale using device
uint8_t * outPixels= (uint8_t *)malloc(width * height);
dim3 blockSize(32, 32); // Default
if (argc == 5)
{
blockSize.x = atoi(argv[3]);
blockSize.y = atoi(argv[4]);
}
convertRgb2Gray(inPixels, width, height, outPixels, true, blockSize);
// Compute mean absolute error between host result and device result
float err = computeError(outPixels, correctOutPixels, width * height);
printf("Error between device result and host result: %f\n", err);
// Write results to files
char * outFileNameBase = strtok(argv[2], "."); // Get rid of extension
writePnm(correctOutPixels, 1, width, height, concatStr(outFileNameBase, "_host.pnm"));
writePnm(outPixels, 1, width, height, concatStr(outFileNameBase, "_device.pnm"));
// Free memories
free(inPixels);
free(outPixels);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdint.h>
#define CHECK(call)\
{\
const hipError_t error = call;\
if (error != hipSuccess)\
{\
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__);\
fprintf(stderr, "code: %d, reason: %s\n", error,\
hipGetErrorString(error));\
exit(EXIT_FAILURE);\
}\
}
struct GpuTimer
{
hipEvent_t start;
hipEvent_t stop;
GpuTimer()
{
hipEventCreate(&start);
hipEventCreate(&stop);
}
~GpuTimer()
{
hipEventDestroy(start);
hipEventDestroy(stop);
}
void Start()
{
hipEventRecord(start, 0);
hipEventSynchronize(start);
}
void Stop()
{
hipEventRecord(stop, 0);
}
float Elapsed()
{
float elapsed;
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
void readPnm(char * fileName,
int &numChannels, int &width, int &height, uint8_t * &pixels)
{
FILE * f = fopen(fileName, "r");
if (f == NULL)
{
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
char type[3];
fscanf(f, "%s", type);
if (strcmp(type, "P2") == 0)
numChannels = 1;
else if (strcmp(type, "P3") == 0)
numChannels = 3;
else // In this exercise, we don't touch other types
{
fclose(f);
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
fscanf(f, "%i", &width);
fscanf(f, "%i", &height);
int max_val;
fscanf(f, "%i", &max_val);
if (max_val > 255) // In this exercise, we assume 1 byte per value
{
fclose(f);
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
pixels = (uint8_t *)malloc(width * height * numChannels);
for (int i = 0; i < width * height * numChannels; i++)
fscanf(f, "%hhu", &pixels[i]);
fclose(f);
}
void writePnm(uint8_t * pixels, int numChannels, int width, int height,
char * fileName)
{
FILE * f = fopen(fileName, "w");
if (f == NULL)
{
printf("Cannot write %s\n", fileName);
exit(EXIT_FAILURE);
}
if (numChannels == 1)
fprintf(f, "P2\n");
else if (numChannels == 3)
fprintf(f, "P3\n");
else
{
fclose(f);
printf("Cannot write %s\n", fileName);
exit(EXIT_FAILURE);
}
fprintf(f, "%i\n%i\n255\n", width, height);
for (int i = 0; i < width * height * numChannels; i++)
fprintf(f, "%hhu\n", pixels[i]);
fclose(f);
}
__global__ void convertRgb2GrayKernel(uint8_t * inPixels, int width, int height,
uint8_t * outPixels)
{
// TODO
int ix = blockIdx.x * blockDim.x + threadIdx.x;
int iy = blockIdx.y * blockDim.y + threadIdx.y;
if (ix < width && iy < height)
{
int i = iy * width + ix;
uint8_t r = inPixels[i * 3];
uint8_t g = inPixels[i * 3 + 1];
uint8_t b = inPixels[i * 3 + 2];
outPixels[i] = 0.299f * r + 0.587f * g + 0.114f * b;
}
}
void convertRgb2Gray(uint8_t * inPixels, int width, int height,
uint8_t * outPixels,
bool useDevice=false, dim3 blockSize=dim3(1))
{
GpuTimer timer;
timer.Start();
if (useDevice == false)
{
for (int r = 0; r < height; r++)
{
for (int c = 0; c < width; c++)
{
int i = r * width + c;
uint8_t r = inPixels[i * 3];
uint8_t g = inPixels[i * 3 + 1];
uint8_t b = inPixels[i * 3 + 2];
outPixels[i] = 0.299f * r + 0.587f * g + 0.114f * b;
}
}
}
else // use device
{
int numChannels = 3;
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, 0);
printf("GPU name: %s\n", devProp.name);
printf("GPU compute capability: %d.%d\n", devProp.major, devProp.minor);
// TODO: Allocate device memories
uint8_t *d_inPixels, * d_outPixels;
CHECK(hipMalloc(&d_inPixels, height * width * numChannels * sizeof(uint8_t)));
CHECK(hipMalloc(&d_outPixels, height * width * sizeof(uint8_t)));
// TODO: Copy data to device memories
CHECK(hipMemcpy(d_inPixels, inPixels, height * width * numChannels * sizeof(uint8_t), hipMemcpyHostToDevice));
// TODO: Set grid size and call kernel (remember to check kernel error)
dim3 gridSize((width - 1)/blockSize.x + 1, (height - 1)/blockSize.y + 1);
convertRgb2GrayKernel<<<gridSize, blockSize>>>(d_inPixels, width, height, d_outPixels);
hipError_t errSync = hipGetLastError();
hipError_t errAsync = hipDeviceSynchronize();
if (errSync != hipSuccess)
printf("Sync kernel error: %s\n", hipGetErrorString(errSync));
if (errAsync != hipSuccess)
printf("Async kernel error: %s\n", hipGetErrorString(errAsync));
// TODO: Copy result from device memories
CHECK(hipMemcpy(outPixels, d_outPixels, height * width * sizeof(uint8_t), hipMemcpyDeviceToHost));
// TODO: Free device memories
CHECK(hipFree(d_inPixels));
CHECK(hipFree(d_outPixels));
}
timer.Stop();
float time = timer.Elapsed();
printf("Processing time (%s): %f ms\n\n",
useDevice == true? "use device" : "use host", time);
}
float computeError(uint8_t * a1, uint8_t * a2, int n)
{
float err = 0;
for (int i = 0; i < n; i++)
err += abs((int)a1[i] - (int)a2[i]);
err /= n;
return err;
}
char * concatStr(const char * s1, const char * s2)
{
char * result = (char *)malloc(strlen(s1) + strlen(s2) + 1);
strcpy(result, s1);
strcat(result, s2);
return result;
}
int main(int argc, char ** argv)
{
if (argc != 3 && argc != 5)
{
printf("The number of arguments is invalid\n");
return EXIT_FAILURE;
}
// Read input RGB image file
int numChannels, width, height;
uint8_t * inPixels;
readPnm(argv[1], numChannels, width, height, inPixels);
if (numChannels != 3)
return EXIT_FAILURE; // Input image must be RGB
printf("Image size (width x height): %i x %i\n\n", width, height);
// Convert RGB to grayscale not using device
uint8_t * correctOutPixels= (uint8_t *)malloc(width * height);
convertRgb2Gray(inPixels, width, height, correctOutPixels);
// Convert RGB to grayscale using device
uint8_t * outPixels= (uint8_t *)malloc(width * height);
dim3 blockSize(32, 32); // Default
if (argc == 5)
{
blockSize.x = atoi(argv[3]);
blockSize.y = atoi(argv[4]);
}
convertRgb2Gray(inPixels, width, height, outPixels, true, blockSize);
// Compute mean absolute error between host result and device result
float err = computeError(outPixels, correctOutPixels, width * height);
printf("Error between device result and host result: %f\n", err);
// Write results to files
char * outFileNameBase = strtok(argv[2], "."); // Get rid of extension
writePnm(correctOutPixels, 1, width, height, concatStr(outFileNameBase, "_host.pnm"));
writePnm(outPixels, 1, width, height, concatStr(outFileNameBase, "_device.pnm"));
// Free memories
free(inPixels);
free(outPixels);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21convertRgb2GrayKernelPhiiS_
.globl _Z21convertRgb2GrayKernelPhiiS_
.p2align 8
.type _Z21convertRgb2GrayKernelPhiiS_,@function
_Z21convertRgb2GrayKernelPhiiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v0, v2, 1, v2
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_clause 0x2
global_load_u8 v3, v[0:1], off offset:1
global_load_u8 v4, v[0:1], off
global_load_u8 v0, v[0:1], off offset:2
s_waitcnt vmcnt(2)
v_cvt_f32_ubyte0_e32 v1, v3
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v3, v4
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v0, v0
v_mul_f32_e32 v1, 0x3f1645a2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v1, v3, 0x3e991687, v1
v_fmamk_f32 v0, v0, 0x3de978d5, v1
v_ashrrev_i32_e32 v1, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cvt_i32_f32_e32 v3, v0
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b8 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21convertRgb2GrayKernelPhiiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21convertRgb2GrayKernelPhiiS_, .Lfunc_end0-_Z21convertRgb2GrayKernelPhiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21convertRgb2GrayKernelPhiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21convertRgb2GrayKernelPhiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdint.h>
#define CHECK(call)\
{\
const hipError_t error = call;\
if (error != hipSuccess)\
{\
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__);\
fprintf(stderr, "code: %d, reason: %s\n", error,\
hipGetErrorString(error));\
exit(EXIT_FAILURE);\
}\
}
struct GpuTimer
{
hipEvent_t start;
hipEvent_t stop;
GpuTimer()
{
hipEventCreate(&start);
hipEventCreate(&stop);
}
~GpuTimer()
{
hipEventDestroy(start);
hipEventDestroy(stop);
}
void Start()
{
hipEventRecord(start, 0);
hipEventSynchronize(start);
}
void Stop()
{
hipEventRecord(stop, 0);
}
float Elapsed()
{
float elapsed;
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
void readPnm(char * fileName,
int &numChannels, int &width, int &height, uint8_t * &pixels)
{
FILE * f = fopen(fileName, "r");
if (f == NULL)
{
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
char type[3];
fscanf(f, "%s", type);
if (strcmp(type, "P2") == 0)
numChannels = 1;
else if (strcmp(type, "P3") == 0)
numChannels = 3;
else // In this exercise, we don't touch other types
{
fclose(f);
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
fscanf(f, "%i", &width);
fscanf(f, "%i", &height);
int max_val;
fscanf(f, "%i", &max_val);
if (max_val > 255) // In this exercise, we assume 1 byte per value
{
fclose(f);
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
pixels = (uint8_t *)malloc(width * height * numChannels);
for (int i = 0; i < width * height * numChannels; i++)
fscanf(f, "%hhu", &pixels[i]);
fclose(f);
}
void writePnm(uint8_t * pixels, int numChannels, int width, int height,
char * fileName)
{
FILE * f = fopen(fileName, "w");
if (f == NULL)
{
printf("Cannot write %s\n", fileName);
exit(EXIT_FAILURE);
}
if (numChannels == 1)
fprintf(f, "P2\n");
else if (numChannels == 3)
fprintf(f, "P3\n");
else
{
fclose(f);
printf("Cannot write %s\n", fileName);
exit(EXIT_FAILURE);
}
fprintf(f, "%i\n%i\n255\n", width, height);
for (int i = 0; i < width * height * numChannels; i++)
fprintf(f, "%hhu\n", pixels[i]);
fclose(f);
}
__global__ void convertRgb2GrayKernel(uint8_t * inPixels, int width, int height,
uint8_t * outPixels)
{
// TODO
int ix = blockIdx.x * blockDim.x + threadIdx.x;
int iy = blockIdx.y * blockDim.y + threadIdx.y;
if (ix < width && iy < height)
{
int i = iy * width + ix;
uint8_t r = inPixels[i * 3];
uint8_t g = inPixels[i * 3 + 1];
uint8_t b = inPixels[i * 3 + 2];
outPixels[i] = 0.299f * r + 0.587f * g + 0.114f * b;
}
}
void convertRgb2Gray(uint8_t * inPixels, int width, int height,
uint8_t * outPixels,
bool useDevice=false, dim3 blockSize=dim3(1))
{
GpuTimer timer;
timer.Start();
if (useDevice == false)
{
for (int r = 0; r < height; r++)
{
for (int c = 0; c < width; c++)
{
int i = r * width + c;
uint8_t r = inPixels[i * 3];
uint8_t g = inPixels[i * 3 + 1];
uint8_t b = inPixels[i * 3 + 2];
outPixels[i] = 0.299f * r + 0.587f * g + 0.114f * b;
}
}
}
else // use device
{
int numChannels = 3;
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, 0);
printf("GPU name: %s\n", devProp.name);
printf("GPU compute capability: %d.%d\n", devProp.major, devProp.minor);
// TODO: Allocate device memories
uint8_t *d_inPixels, * d_outPixels;
CHECK(hipMalloc(&d_inPixels, height * width * numChannels * sizeof(uint8_t)));
CHECK(hipMalloc(&d_outPixels, height * width * sizeof(uint8_t)));
// TODO: Copy data to device memories
CHECK(hipMemcpy(d_inPixels, inPixels, height * width * numChannels * sizeof(uint8_t), hipMemcpyHostToDevice));
// TODO: Set grid size and call kernel (remember to check kernel error)
dim3 gridSize((width - 1)/blockSize.x + 1, (height - 1)/blockSize.y + 1);
convertRgb2GrayKernel<<<gridSize, blockSize>>>(d_inPixels, width, height, d_outPixels);
hipError_t errSync = hipGetLastError();
hipError_t errAsync = hipDeviceSynchronize();
if (errSync != hipSuccess)
printf("Sync kernel error: %s\n", hipGetErrorString(errSync));
if (errAsync != hipSuccess)
printf("Async kernel error: %s\n", hipGetErrorString(errAsync));
// TODO: Copy result from device memories
CHECK(hipMemcpy(outPixels, d_outPixels, height * width * sizeof(uint8_t), hipMemcpyDeviceToHost));
// TODO: Free device memories
CHECK(hipFree(d_inPixels));
CHECK(hipFree(d_outPixels));
}
timer.Stop();
float time = timer.Elapsed();
printf("Processing time (%s): %f ms\n\n",
useDevice == true? "use device" : "use host", time);
}
float computeError(uint8_t * a1, uint8_t * a2, int n)
{
float err = 0;
for (int i = 0; i < n; i++)
err += abs((int)a1[i] - (int)a2[i]);
err /= n;
return err;
}
char * concatStr(const char * s1, const char * s2)
{
char * result = (char *)malloc(strlen(s1) + strlen(s2) + 1);
strcpy(result, s1);
strcat(result, s2);
return result;
}
int main(int argc, char ** argv)
{
if (argc != 3 && argc != 5)
{
printf("The number of arguments is invalid\n");
return EXIT_FAILURE;
}
// Read input RGB image file
int numChannels, width, height;
uint8_t * inPixels;
readPnm(argv[1], numChannels, width, height, inPixels);
if (numChannels != 3)
return EXIT_FAILURE; // Input image must be RGB
printf("Image size (width x height): %i x %i\n\n", width, height);
// Convert RGB to grayscale not using device
uint8_t * correctOutPixels= (uint8_t *)malloc(width * height);
convertRgb2Gray(inPixels, width, height, correctOutPixels);
// Convert RGB to grayscale using device
uint8_t * outPixels= (uint8_t *)malloc(width * height);
dim3 blockSize(32, 32); // Default
if (argc == 5)
{
blockSize.x = atoi(argv[3]);
blockSize.y = atoi(argv[4]);
}
convertRgb2Gray(inPixels, width, height, outPixels, true, blockSize);
// Compute mean absolute error between host result and device result
float err = computeError(outPixels, correctOutPixels, width * height);
printf("Error between device result and host result: %f\n", err);
// Write results to files
char * outFileNameBase = strtok(argv[2], "."); // Get rid of extension
writePnm(correctOutPixels, 1, width, height, concatStr(outFileNameBase, "_host.pnm"));
writePnm(outPixels, 1, width, height, concatStr(outFileNameBase, "_device.pnm"));
// Free memories
free(inPixels);
free(outPixels);
} | .text
.file "bt01_p1.hip"
.globl _Z7readPnmPcRiS0_S0_RPh # -- Begin function _Z7readPnmPcRiS0_S0_RPh
.p2align 4, 0x90
.type _Z7readPnmPcRiS0_S0_RPh,@function
_Z7readPnmPcRiS0_S0_RPh: # @_Z7readPnmPcRiS0_S0_RPh
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %rbx
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %rbp
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB0_10
# %bb.1:
movq %rax, %r13
leaq 1(%rsp), %rdx
movl $.L.str.2, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movzwl 1(%rsp), %eax
xorl $12880, %eax # imm = 0x3250
movzbl 3(%rsp), %ecx
orw %ax, %cx
je .LBB0_2
# %bb.8:
movzwl 1(%rsp), %ecx
xorl $13136, %ecx # imm = 0x3350
movzbl 3(%rsp), %edx
movl $3, %eax
orw %cx, %dx
je .LBB0_3
jmp .LBB0_9
.LBB0_2:
movl $1, %eax
.LBB0_3:
movl %eax, (%r12)
movl $.L.str.5, %esi
movq %r13, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl $.L.str.5, %esi
movq %r13, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
leaq 4(%rsp), %rdx
movl $.L.str.5, %esi
movq %r13, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $256, 4(%rsp) # imm = 0x100
jge .LBB0_9
# %bb.4:
movslq (%r15), %rax
movslq (%r14), %rcx
imulq %rax, %rcx
movslq (%r12), %rdi
imulq %rcx, %rdi
callq malloc
movq %rax, (%rbx)
movl (%r14), %eax
imull (%r15), %eax
imull (%r12), %eax
testl %eax, %eax
jle .LBB0_7
# %bb.5: # %.lr.ph.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_6: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq (%rbx), %rdx
addq %rbp, %rdx
movl $.L.str.6, %esi
movq %r13, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
incq %rbp
movslq (%r15), %rax
movslq (%r14), %rcx
imulq %rax, %rcx
movslq (%r12), %rax
imulq %rcx, %rax
cmpq %rax, %rbp
jl .LBB0_6
.LBB0_7: # %._crit_edge
movq %r13, %rdi
callq fclose
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_9:
.cfi_def_cfa_offset 64
movq %r13, %rdi
callq fclose
.LBB0_10:
movl $.L.str.1, %edi
movq %rbp, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z7readPnmPcRiS0_S0_RPh, .Lfunc_end0-_Z7readPnmPcRiS0_S0_RPh
.cfi_endproc
# -- End function
.globl _Z8writePnmPhiiiPc # -- Begin function _Z8writePnmPhiiiPc
.p2align 4, 0x90
.type _Z8writePnmPhiiiPc,@function
_Z8writePnmPhiiiPc: # @_Z8writePnmPhiiiPc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %r13
movl %ecx, %r15d
movl %edx, %r12d
movl %esi, %ebp
movq %rdi, %rbx
movl $.L.str.7, %esi
movq %r8, %rdi
callq fopen
testq %rax, %rax
je .LBB1_9
# %bb.1:
movq %rax, %r14
movl $.L.str.9, %edi
cmpl $1, %ebp
je .LBB1_4
# %bb.2:
cmpl $3, %ebp
jne .LBB1_8
# %bb.3:
movl $.L.str.10, %edi
.LBB1_4:
movl $3, %esi
movl $1, %edx
movq %r14, %rcx
callq fwrite@PLT
movl $.L.str.11, %esi
movq %r14, %rdi
movl %r12d, %edx
movl %r15d, %ecx
xorl %eax, %eax
callq fprintf
imull %r12d, %ebp
imull %r15d, %ebp
testl %ebp, %ebp
jle .LBB1_7
# %bb.5: # %.lr.ph.preheader
movl %ebp, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movzbl (%rbx,%r12), %edx
movl $.L.str.12, %esi
movq %r14, %rdi
xorl %eax, %eax
callq fprintf
incq %r12
cmpq %r12, %r15
jne .LBB1_6
.LBB1_7: # %._crit_edge
movq %r14, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.LBB1_8:
.cfi_def_cfa_offset 64
movq %r14, %rdi
callq fclose
.LBB1_9:
movl $.L.str.8, %edi
movq %r13, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z8writePnmPhiiiPc, .Lfunc_end1-_Z8writePnmPhiiiPc
.cfi_endproc
# -- End function
.globl _Z36__device_stub__convertRgb2GrayKernelPhiiS_ # -- Begin function _Z36__device_stub__convertRgb2GrayKernelPhiiS_
.p2align 4, 0x90
.type _Z36__device_stub__convertRgb2GrayKernelPhiiS_,@function
_Z36__device_stub__convertRgb2GrayKernelPhiiS_: # @_Z36__device_stub__convertRgb2GrayKernelPhiiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21convertRgb2GrayKernelPhiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z36__device_stub__convertRgb2GrayKernelPhiiS_, .Lfunc_end2-_Z36__device_stub__convertRgb2GrayKernelPhiiS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z15convertRgb2GrayPhiiS_b4dim3
.LCPI3_0:
.long 0x3e991687 # float 0.298999995
.LCPI3_1:
.long 0x3f1645a2 # float 0.587000012
.LCPI3_2:
.long 0x3de978d5 # float 0.114
.text
.globl _Z15convertRgb2GrayPhiiS_b4dim3
.p2align 4, 0x90
.type _Z15convertRgb2GrayPhiiS_b4dim3,@function
_Z15convertRgb2GrayPhiiS_b4dim3: # @_Z15convertRgb2GrayPhiiS_b4dim3
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1640, %rsp # imm = 0x668
.cfi_def_cfa_offset 1696
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %r12d
movq %rcx, %r14
movl %edx, %ebp
movl %esi, %r15d
movq %rdi, %r13
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipEventCreate
movq 8(%rsp), %rdi
.Ltmp0:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp1:
# %bb.1: # %.noexc
movq 8(%rsp), %rdi
.Ltmp2:
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
.Ltmp3:
# %bb.2: # %_ZN8GpuTimer5StartEv.exit
testb %r12b, %r12b
je .LBB3_3
# %bb.16:
.Ltmp4:
movl %r12d, 44(%rsp) # 4-byte Spill
.cfi_escape 0x2e, 0x00
leaq 168(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
.Ltmp5:
# %bb.17:
.cfi_escape 0x2e, 0x00
leaq 168(%rsp), %rsi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movl 528(%rsp), %esi
movl 532(%rsp), %edx
.cfi_escape 0x2e, 0x00
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
movl %ebp, %r12d
imull %r15d, %r12d
leal (%r12,%r12,2), %eax
movslq %eax, %rbx
.Ltmp7:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
.Ltmp8:
# %bb.18: # %_ZL9hipMallocIhE10hipError_tPPT_m.exit
testl %eax, %eax
jne .LBB3_19
# %bb.25:
movslq %r12d, %rsi
.Ltmp12:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movq %rsi, 56(%rsp) # 8-byte Spill
callq hipMalloc
.Ltmp13:
# %bb.26: # %_ZL9hipMallocIhE10hipError_tPPT_m.exit104
movl %eax, %r12d
testl %eax, %eax
jne .LBB3_27
# %bb.30:
movq 32(%rsp), %rdi
.Ltmp17:
.cfi_escape 0x2e, 0x00
movq %r13, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
.Ltmp18:
# %bb.31:
testl %eax, %eax
movl 44(%rsp), %r12d # 4-byte Reload
jne .LBB3_32
# %bb.35:
leaq 1696(%rsp), %rcx
leal -1(%r15), %eax
xorl %edx, %edx
divl (%rcx)
# kill: def $eax killed $eax def $rax
leal 1(%rax), %edi
leal -1(%rbp), %eax
xorl %edx, %edx
divl 4(%rcx)
# kill: def $eax killed $eax def $rax
incl %eax
shlq $32, %rax
orq %rax, %rdi
movq (%rcx), %rdx
movl 8(%rcx), %ecx
.Ltmp22:
.cfi_escape 0x2e, 0x00
movl $1, %esi
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp23:
# %bb.36:
testl %eax, %eax
jne .LBB3_39
# %bb.37:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 120(%rsp)
movl %r15d, 52(%rsp)
movl %ebp, 48(%rsp)
movq %rcx, 112(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 52(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rax
movq %rax, 152(%rsp)
.Ltmp24:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp25:
# %bb.38: # %.noexc105
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
.Ltmp26:
.cfi_escape 0x2e, 0x10
leaq 128(%rsp), %r9
movl $_Z21convertRgb2GrayKernelPhiiS_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp27:
.LBB3_39:
.Ltmp29:
.cfi_escape 0x2e, 0x00
callq hipGetLastError
.Ltmp30:
# %bb.40:
.Ltmp32:
movl %eax, %ebp
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp33:
# %bb.41:
movl %eax, %ebx
testl %ebp, %ebp
je .LBB3_44
# %bb.42:
.Ltmp34:
.cfi_escape 0x2e, 0x00
movl %ebp, %edi
callq hipGetErrorString
.Ltmp35:
# %bb.43:
.cfi_escape 0x2e, 0x00
movl $.L.str.18, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB3_44:
testl %ebx, %ebx
je .LBB3_47
# %bb.45:
.Ltmp36:
.cfi_escape 0x2e, 0x00
movl %ebx, %edi
callq hipGetErrorString
.Ltmp37:
# %bb.46:
.cfi_escape 0x2e, 0x00
movl $.L.str.19, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB3_47:
movq 24(%rsp), %rsi
.Ltmp39:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movq 56(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
.Ltmp40:
# %bb.48:
testl %eax, %eax
jne .LBB3_49
# %bb.54:
movq 32(%rsp), %rdi
.Ltmp44:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp45:
# %bb.55:
testl %eax, %eax
jne .LBB3_56
# %bb.59:
movq 24(%rsp), %rdi
.Ltmp49:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp50:
# %bb.60:
testl %eax, %eax
je .LBB3_9
# %bb.61:
movq stderr(%rip), %rdi
.cfi_escape 0x2e, 0x00
movl $.L.str.15, %esi
movl $.L.str.16, %edx
movl $192, %ecx
movl %eax, %ebp
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rbx
.Ltmp51:
.cfi_escape 0x2e, 0x00
movl %ebp, %edi
callq hipGetErrorString
.Ltmp52:
# %bb.62:
.cfi_escape 0x2e, 0x00
jmp .LBB3_21
.LBB3_3: # %.preheader111
testl %ebp, %ebp
jle .LBB3_9
# %bb.4: # %.preheader.lr.ph
movl %ebp, %eax
movl %r15d, %ecx
xorl %edx, %edx
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss .LCPI3_2(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
xorl %esi, %esi
jmp .LBB3_5
.p2align 4, 0x90
.LBB3_8: # %._crit_edge
# in Loop: Header=BB3_5 Depth=1
incq %rsi
addl %r15d, %edx
cmpq %rax, %rsi
je .LBB3_9
.LBB3_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_7 Depth 2
testl %r15d, %r15d
jle .LBB3_8
# %bb.6: # %.lr.ph
# in Loop: Header=BB3_5 Depth=1
movl %edx, %r8d
leaq (%r14,%r8), %rdi
leaq (%r8,%r8,2), %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB3_7: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
movl %r8d, %r10d
movzbl (%r13,%r10), %r11d
movzbl 1(%r13,%r10), %ebx
movzbl 2(%r13,%r10), %r10d
xorps %xmm3, %xmm3
cvtsi2ss %r11d, %xmm3
mulss %xmm0, %xmm3
xorps %xmm4, %xmm4
cvtsi2ss %ebx, %xmm4
mulss %xmm1, %xmm4
addss %xmm3, %xmm4
xorps %xmm3, %xmm3
cvtsi2ss %r10d, %xmm3
mulss %xmm2, %xmm3
addss %xmm4, %xmm3
cvttss2si %xmm3, %r10d
movb %r10b, (%rdi,%r9)
incq %r9
addq $3, %r8
cmpq %r9, %rcx
jne .LBB3_7
jmp .LBB3_8
.LBB3_9: # %.loopexit
movq 16(%rsp), %rdi
.Ltmp54:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp55:
# %bb.10: # %_ZN8GpuTimer4StopEv.exit
movq 16(%rsp), %rdi
.Ltmp57:
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
.Ltmp58:
# %bb.11: # %.noexc108
movq 8(%rsp), %rsi
movq 16(%rsp), %rdx
.Ltmp59:
.cfi_escape 0x2e, 0x00
leaq 168(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp60:
# %bb.12: # %_ZN8GpuTimer7ElapsedEv.exit
movss 168(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl $.L.str.21, %eax
movl $.L.str.22, %esi
testb %r12b, %r12b
cmovneq %rax, %rsi
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $.L.str.20, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rdi
.Ltmp67:
.cfi_escape 0x2e, 0x00
callq hipEventDestroy
.Ltmp68:
# %bb.13:
movq 16(%rsp), %rdi
.Ltmp69:
.cfi_escape 0x2e, 0x00
callq hipEventDestroy
.Ltmp70:
# %bb.14: # %_ZN8GpuTimerD2Ev.exit
addq $1640, %rsp # imm = 0x668
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_19:
.cfi_def_cfa_offset 1696
movq stderr(%rip), %rdi
.cfi_escape 0x2e, 0x00
movl $.L.str.15, %esi
movl $.L.str.16, %edx
movl $172, %ecx
movl %eax, %ebp
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rbx
.Ltmp9:
.cfi_escape 0x2e, 0x00
movl %ebp, %edi
callq hipGetErrorString
.Ltmp10:
# %bb.20:
.cfi_escape 0x2e, 0x00
jmp .LBB3_21
.LBB3_27:
movq stderr(%rip), %rdi
.cfi_escape 0x2e, 0x00
movl $.L.str.15, %esi
movl $.L.str.16, %edx
movl $173, %ecx
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rbx
.Ltmp14:
.cfi_escape 0x2e, 0x00
movl %r12d, %edi
callq hipGetErrorString
.Ltmp15:
# %bb.28:
.cfi_escape 0x2e, 0x00
movl $.L.str.17, %esi
movq %rbx, %rdi
movl %r12d, %edx
jmp .LBB3_22
.LBB3_32:
movq stderr(%rip), %rdi
.cfi_escape 0x2e, 0x00
movl $.L.str.15, %esi
movl $.L.str.16, %edx
movl $176, %ecx
movl %eax, %ebp
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rbx
.Ltmp19:
.cfi_escape 0x2e, 0x00
movl %ebp, %edi
callq hipGetErrorString
.Ltmp20:
# %bb.33:
.cfi_escape 0x2e, 0x00
jmp .LBB3_21
.LBB3_49:
movq stderr(%rip), %rdi
.cfi_escape 0x2e, 0x00
movl $.L.str.15, %esi
movl $.L.str.16, %edx
movl $188, %ecx
movl %eax, %ebp
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rbx
.Ltmp41:
.cfi_escape 0x2e, 0x00
movl %ebp, %edi
callq hipGetErrorString
.Ltmp42:
# %bb.50:
.cfi_escape 0x2e, 0x00
jmp .LBB3_21
.LBB3_56:
movq stderr(%rip), %rdi
.cfi_escape 0x2e, 0x00
movl $.L.str.15, %esi
movl $.L.str.16, %edx
movl $191, %ecx
movl %eax, %ebp
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rbx
.Ltmp46:
.cfi_escape 0x2e, 0x00
movl %ebp, %edi
callq hipGetErrorString
.Ltmp47:
# %bb.57:
.cfi_escape 0x2e, 0x00
.LBB3_21:
movl $.L.str.17, %esi
movq %rbx, %rdi
movl %ebp, %edx
.LBB3_22:
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
.cfi_escape 0x2e, 0x00
movl $1, %edi
callq exit
.LBB3_51:
.Ltmp31:
jmp .LBB3_66
.LBB3_23:
.Ltmp6:
jmp .LBB3_66
.LBB3_69:
.Ltmp28:
jmp .LBB3_66
.LBB3_52:
.Ltmp38:
jmp .LBB3_66
.LBB3_64:
.Ltmp71:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __clang_call_terminate
.LBB3_65:
.Ltmp61:
jmp .LBB3_66
.LBB3_15:
.Ltmp56:
jmp .LBB3_66
.LBB3_63:
.Ltmp53:
jmp .LBB3_66
.LBB3_58:
.Ltmp48:
jmp .LBB3_66
.LBB3_53:
.Ltmp43:
jmp .LBB3_66
.LBB3_34:
.Ltmp21:
jmp .LBB3_66
.LBB3_29:
.Ltmp16:
jmp .LBB3_66
.LBB3_24:
.Ltmp11:
.LBB3_66:
movq %rax, %rbx
movq 8(%rsp), %rdi
.Ltmp62:
.cfi_escape 0x2e, 0x00
callq hipEventDestroy
.Ltmp63:
# %bb.67:
movq 16(%rsp), %rdi
.Ltmp64:
.cfi_escape 0x2e, 0x00
callq hipEventDestroy
.Ltmp65:
# %bb.68: # %_ZN8GpuTimerD2Ev.exit110
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.LBB3_70:
.Ltmp66:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __clang_call_terminate
.Lfunc_end3:
.size _Z15convertRgb2GrayPhiiS_b4dim3, .Lfunc_end3-_Z15convertRgb2GrayPhiiS_b4dim3
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table3:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp56-.Lfunc_begin0 # jumps to .Ltmp56
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp5-.Ltmp4 # Call between .Ltmp4 and .Ltmp5
.uleb128 .Ltmp6-.Lfunc_begin0 # jumps to .Ltmp6
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp8-.Ltmp7 # Call between .Ltmp7 and .Ltmp8
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp18-.Ltmp17 # Call between .Ltmp17 and .Ltmp18
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp27-.Ltmp22 # Call between .Ltmp22 and .Ltmp27
.uleb128 .Ltmp28-.Lfunc_begin0 # jumps to .Ltmp28
.byte 0 # On action: cleanup
.uleb128 .Ltmp29-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp30-.Ltmp29 # Call between .Ltmp29 and .Ltmp30
.uleb128 .Ltmp31-.Lfunc_begin0 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp32-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp37-.Ltmp32 # Call between .Ltmp32 and .Ltmp37
.uleb128 .Ltmp38-.Lfunc_begin0 # jumps to .Ltmp38
.byte 0 # On action: cleanup
.uleb128 .Ltmp39-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp40-.Ltmp39 # Call between .Ltmp39 and .Ltmp40
.uleb128 .Ltmp43-.Lfunc_begin0 # jumps to .Ltmp43
.byte 0 # On action: cleanup
.uleb128 .Ltmp44-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp45-.Ltmp44 # Call between .Ltmp44 and .Ltmp45
.uleb128 .Ltmp48-.Lfunc_begin0 # jumps to .Ltmp48
.byte 0 # On action: cleanup
.uleb128 .Ltmp49-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp52-.Ltmp49 # Call between .Ltmp49 and .Ltmp52
.uleb128 .Ltmp53-.Lfunc_begin0 # jumps to .Ltmp53
.byte 0 # On action: cleanup
.uleb128 .Ltmp54-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp55-.Ltmp54 # Call between .Ltmp54 and .Ltmp55
.uleb128 .Ltmp56-.Lfunc_begin0 # jumps to .Ltmp56
.byte 0 # On action: cleanup
.uleb128 .Ltmp57-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp60-.Ltmp57 # Call between .Ltmp57 and .Ltmp60
.uleb128 .Ltmp61-.Lfunc_begin0 # jumps to .Ltmp61
.byte 0 # On action: cleanup
.uleb128 .Ltmp67-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Ltmp70-.Ltmp67 # Call between .Ltmp67 and .Ltmp70
.uleb128 .Ltmp71-.Lfunc_begin0 # jumps to .Ltmp71
.byte 1 # On action: 1
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 16 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp14-.Lfunc_begin0 # >> Call Site 17 <<
.uleb128 .Ltmp15-.Ltmp14 # Call between .Ltmp14 and .Ltmp15
.uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp19-.Lfunc_begin0 # >> Call Site 18 <<
.uleb128 .Ltmp20-.Ltmp19 # Call between .Ltmp19 and .Ltmp20
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp41-.Lfunc_begin0 # >> Call Site 19 <<
.uleb128 .Ltmp42-.Ltmp41 # Call between .Ltmp41 and .Ltmp42
.uleb128 .Ltmp43-.Lfunc_begin0 # jumps to .Ltmp43
.byte 0 # On action: cleanup
.uleb128 .Ltmp46-.Lfunc_begin0 # >> Call Site 20 <<
.uleb128 .Ltmp47-.Ltmp46 # Call between .Ltmp46 and .Ltmp47
.uleb128 .Ltmp48-.Lfunc_begin0 # jumps to .Ltmp48
.byte 0 # On action: cleanup
.uleb128 .Ltmp62-.Lfunc_begin0 # >> Call Site 21 <<
.uleb128 .Ltmp65-.Ltmp62 # Call between .Ltmp62 and .Ltmp65
.uleb128 .Ltmp66-.Lfunc_begin0 # jumps to .Ltmp66
.byte 1 # On action: 1
.uleb128 .Ltmp65-.Lfunc_begin0 # >> Call Site 22 <<
.uleb128 .Lfunc_end3-.Ltmp65 # Call between .Ltmp65 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.text
.globl _Z12computeErrorPhS_i # -- Begin function _Z12computeErrorPhS_i
.p2align 4, 0x90
.type _Z12computeErrorPhS_i,@function
_Z12computeErrorPhS_i: # @_Z12computeErrorPhS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB4_1
# %bb.3: # %.lr.ph.preheader
movl %edx, %eax
xorps %xmm0, %xmm0
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movzbl (%rdi,%rcx), %r8d
movzbl (%rsi,%rcx), %r9d
subl %r9d, %r8d
movl %r8d, %r9d
negl %r9d
cmovsl %r8d, %r9d
movzbl %r9b, %r8d
xorps %xmm1, %xmm1
cvtsi2ss %r8d, %xmm1
addss %xmm1, %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB4_4
jmp .LBB4_2
.LBB4_1:
xorps %xmm0, %xmm0
.LBB4_2: # %._crit_edge
xorps %xmm1, %xmm1
cvtsi2ss %edx, %xmm1
divss %xmm1, %xmm0
retq
.Lfunc_end4:
.size _Z12computeErrorPhS_i, .Lfunc_end4-_Z12computeErrorPhS_i
.cfi_endproc
# -- End function
.globl _Z9concatStrPKcS0_ # -- Begin function _Z9concatStrPKcS0_
.p2align 4, 0x90
.type _Z9concatStrPKcS0_,@function
_Z9concatStrPKcS0_: # @_Z9concatStrPKcS0_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
callq strlen
movq %rax, %r15
movq %rbx, %rdi
callq strlen
leaq (%r15,%rax), %rdi
incq %rdi
callq malloc
movq %rax, %r15
movq %rax, %rdi
movq %r14, %rsi
callq strcpy
movq %r15, %rdi
movq %rbx, %rsi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp strcat # TAILCALL
.Lfunc_end5:
.size _Z9concatStrPKcS0_, .Lfunc_end5-_Z9concatStrPKcS0_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movl %edi, %ebp
cmpl $3, %edi
je .LBB6_3
# %bb.1:
cmpl $5, %ebp
jne .LBB6_2
.LBB6_3:
movq 8(%r15), %rdi
leaq 20(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 12(%rsp), %rcx
leaq 64(%rsp), %r8
callq _Z7readPnmPcRiS0_S0_RPh
movl $1, %eax
cmpl $3, 20(%rsp)
jne .LBB6_11
# %bb.4:
movl 16(%rsp), %esi
movl 12(%rsp), %edx
movl $.L.str.24, %edi
xorl %eax, %eax
callq printf
movl 16(%rsp), %r14d
movl 12(%rsp), %r13d
movl %r13d, %eax
imull %r14d, %eax
movslq %eax, %rdi
callq malloc
movq %rax, %r12
movq 64(%rsp), %rbx
movabsq $4294967297, %rax # imm = 0x100000001
movq %rax, 48(%rsp)
movl $1, 56(%rsp)
movq 48(%rsp), %rax
movq %rbx, %rdi
movl %r14d, %esi
movl %r13d, %edx
movq %r12, %rcx
xorl %r8d, %r8d
pushq $1
.cfi_adjust_cfa_offset 8
pushq %rax
.cfi_adjust_cfa_offset 8
callq _Z15convertRgb2GrayPhiiS_b4dim3
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movslq 16(%rsp), %rax
movslq 12(%rsp), %rdi
imulq %rax, %rdi
callq malloc
movq %rax, %r14
movl $32, %eax
movl $32, %r13d
cmpl $5, %ebp
jne .LBB6_6
# %bb.5:
movq 24(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movq 32(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
.LBB6_6:
movl 16(%rsp), %esi
movl 12(%rsp), %edx
movl %r13d, 24(%rsp)
movl %eax, 28(%rsp)
movl $1, 32(%rsp)
movq 24(%rsp), %rax
movq %rbx, %rdi
movq %r14, %rcx
movl $1, %r8d
pushq $1
.cfi_adjust_cfa_offset 8
pushq %rax
.cfi_adjust_cfa_offset 8
callq _Z15convertRgb2GrayPhiiS_b4dim3
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl 12(%rsp), %eax
imull 16(%rsp), %eax
testl %eax, %eax
movq %rbx, 40(%rsp) # 8-byte Spill
jle .LBB6_7
# %bb.8: # %.lr.ph.preheader.i
movl %eax, %ecx
xorps %xmm0, %xmm0
xorl %edx, %edx
.p2align 4, 0x90
.LBB6_9: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movzbl (%r14,%rdx), %esi
movzbl (%r12,%rdx), %edi
subl %edi, %esi
movl %esi, %edi
negl %edi
cmovsl %esi, %edi
movzbl %dil, %esi
xorps %xmm1, %xmm1
cvtsi2ss %esi, %xmm1
addss %xmm1, %xmm0
incq %rdx
cmpq %rdx, %rcx
jne .LBB6_9
jmp .LBB6_10
.LBB6_2:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %eax
jmp .LBB6_11
.LBB6_7:
xorps %xmm0, %xmm0
.LBB6_10: # %_Z12computeErrorPhS_i.exit
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.25, %edi
movb $1, %al
callq printf
movq 16(%r15), %rdi
movl $.L.str.26, %esi
callq strtok
movq %rax, %r15
movl 16(%rsp), %ebp
movl 12(%rsp), %r13d
movq %rax, %rdi
callq strlen
leaq 10(%rax), %rdi
callq malloc
movq %rax, %rbx
movq %rax, %rdi
movq %r15, %rsi
callq strcpy
movq %rbx, %rdi
callq strlen
movabsq $7957911619251431519, %rcx # imm = 0x6E702E74736F685F
movq %rcx, (%rbx,%rax)
movw $109, 8(%rbx,%rax)
movq %r12, %rdi
movl $1, %esi
movl %ebp, %edx
movl %r13d, %ecx
movq %rbx, %r8
callq _Z8writePnmPhiiiPc
movl 16(%rsp), %ebx
movl 12(%rsp), %ebp
movq %r15, %rdi
callq strlen
leaq 12(%rax), %rdi
callq malloc
movq %rax, %r12
movq %rax, %rdi
movq %r15, %rsi
callq strcpy
movq %r12, %rdi
callq strlen
movabsq $3343187603001533535, %rcx # imm = 0x2E6563697665645F
movq %rcx, (%r12,%rax)
movl $7171696, 8(%r12,%rax) # imm = 0x6D6E70
movq %r14, %rdi
movl $1, %esi
movl %ebx, %edx
movl %ebp, %ecx
movq %r12, %r8
callq _Z8writePnmPhiiiPc
movq 40(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
.LBB6_11:
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end7:
.size __clang_call_terminate, .Lfunc_end7-__clang_call_terminate
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21convertRgb2GrayKernelPhiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Cannot read %s\n"
.size .L.str.1, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "P2"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "P3"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%i"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%hhu"
.size .L.str.6, 5
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "w"
.size .L.str.7, 2
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Cannot write %s\n"
.size .L.str.8, 17
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "P2\n"
.size .L.str.9, 4
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "P3\n"
.size .L.str.10, 4
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "%i\n%i\n255\n"
.size .L.str.11, 11
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "%hhu\n"
.size .L.str.12, 6
.type _Z21convertRgb2GrayKernelPhiiS_,@object # @_Z21convertRgb2GrayKernelPhiiS_
.section .rodata,"a",@progbits
.globl _Z21convertRgb2GrayKernelPhiiS_
.p2align 3, 0x0
_Z21convertRgb2GrayKernelPhiiS_:
.quad _Z36__device_stub__convertRgb2GrayKernelPhiiS_
.size _Z21convertRgb2GrayKernelPhiiS_, 8
.type .L.str.13,@object # @.str.13
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.13:
.asciz "GPU name: %s\n"
.size .L.str.13, 14
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "GPU compute capability: %d.%d\n"
.size .L.str.14, 31
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Error: %s:%d, "
.size .L.str.15, 15
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/hmhuan/PG_GPU/master/assignment/BT01/1612858/bt01_p1.hip"
.size .L.str.16, 114
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "code: %d, reason: %s\n"
.size .L.str.17, 22
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "Sync kernel error: %s\n"
.size .L.str.18, 23
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "Async kernel error: %s\n"
.size .L.str.19, 24
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "Processing time (%s): %f ms\n\n"
.size .L.str.20, 30
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "use device"
.size .L.str.21, 11
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "use host"
.size .L.str.22, 9
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz "Image size (width x height): %i x %i\n\n"
.size .L.str.24, 39
.type .L.str.25,@object # @.str.25
.L.str.25:
.asciz "Error between device result and host result: %f\n"
.size .L.str.25, 49
.type .L.str.26,@object # @.str.26
.L.str.26:
.asciz "."
.size .L.str.26, 2
.type .L.str.27,@object # @.str.27
.L.str.27:
.asciz "_host.pnm"
.size .L.str.27, 10
.type .L.str.28,@object # @.str.28
.L.str.28:
.asciz "_device.pnm"
.size .L.str.28, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z21convertRgb2GrayKernelPhiiS_"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "The number of arguments is invalid"
.size .Lstr, 35
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__convertRgb2GrayKernelPhiiS_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z21convertRgb2GrayKernelPhiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z21convertRgb2GrayKernelPhiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R0, R3, c[0x0][0x168], R0 ; /* 0x00005a0003007a24 */
/* 0x000fe200078e0200 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00c0*/ IMAD R3, R0, 0x3, RZ ; /* 0x0000000300037824 */
/* 0x000fca00078e02ff */
/*00d0*/ IADD3 R2, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003027a10 */
/* 0x000fc80007f1e0ff */
/*00e0*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P0 ; /* 0x0000590003037a11 */
/* 0x000fca00000f0eff */
/*00f0*/ LDG.E.U8 R7, [R2.64+0x1] ; /* 0x0000010402077981 */
/* 0x000ea8000c1e1100 */
/*0100*/ LDG.E.U8 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ee8000c1e1100 */
/*0110*/ LDG.E.U8 R8, [R2.64+0x2] ; /* 0x0000020402087981 */
/* 0x000f22000c1e1100 */
/*0120*/ IADD3 R4, P0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000047a10 */
/* 0x000fe20007f1e0ff */
/*0130*/ I2F.U16 R7, R7 ; /* 0x0000000700077306 */
/* 0x004e300000101000 */
/*0140*/ I2F.U16 R6, R6 ; /* 0x0000000600067306 */
/* 0x008e700000101000 */
/*0150*/ I2F.U16 R8, R8 ; /* 0x0000000800087306 */
/* 0x010ea20000101000 */
/*0160*/ FMUL R5, R7, 0.58700001239776611328 ; /* 0x3f1645a207057820 */
/* 0x001fc80000400000 */
/*0170*/ FFMA R5, R6, 0.29899999499320983887, R5 ; /* 0x3e99168706057823 */
/* 0x002fc80000000005 */
/*0180*/ FFMA R9, R8, 0.11400000005960464478, R5 ; /* 0x3de978d508097823 */
/* 0x004fe20000000005 */
/*0190*/ LEA.HI.X.SX32 R5, R0, c[0x0][0x174], 0x1, P0 ; /* 0x00005d0000057a11 */
/* 0x000fca00000f0eff */
/*01a0*/ F2I.U32.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e24000020f000 */
/*01b0*/ STG.E.U8 [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x001fe2000c101104 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21convertRgb2GrayKernelPhiiS_
.globl _Z21convertRgb2GrayKernelPhiiS_
.p2align 8
.type _Z21convertRgb2GrayKernelPhiiS_,@function
_Z21convertRgb2GrayKernelPhiiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v0, v2, 1, v2
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_clause 0x2
global_load_u8 v3, v[0:1], off offset:1
global_load_u8 v4, v[0:1], off
global_load_u8 v0, v[0:1], off offset:2
s_waitcnt vmcnt(2)
v_cvt_f32_ubyte0_e32 v1, v3
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v3, v4
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v0, v0
v_mul_f32_e32 v1, 0x3f1645a2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v1, v3, 0x3e991687, v1
v_fmamk_f32 v0, v0, 0x3de978d5, v1
v_ashrrev_i32_e32 v1, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cvt_i32_f32_e32 v3, v0
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b8 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21convertRgb2GrayKernelPhiiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21convertRgb2GrayKernelPhiiS_, .Lfunc_end0-_Z21convertRgb2GrayKernelPhiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21convertRgb2GrayKernelPhiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21convertRgb2GrayKernelPhiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /******************************************************************
File : lcsExclusiveScanForInt.cu
Author : Mingcheng Chen
Last Update : January 29th, 2013
*******************************************************************/
#include <stdio.h>
#define BLOCK_SIZE 512
#define NUM_BANKS 32
#define LOG_NUM_BANKS 5
#define CONFLICT_FREE_OFFSET(n) ((n) >> (LOG_NUM_BANKS))
#define POSI(n) ((n) + CONFLICT_FREE_OFFSET(n))
__global__ void ScanKernel(int *globalArray, int length, int step) {
__shared__ int localArray[POSI(BLOCK_SIZE << 1) + 1];
int localID = threadIdx.x;
int groupID = blockIdx.x;
int groupSize = blockDim.x;
int startOffset = (groupSize << 1) * groupID * step;
int posi1 = startOffset + localID * step;
int posi2 = posi1 + groupSize * step;
localArray[POSI(localID)] = posi1 < length ? globalArray[posi1] : 0;
localArray[POSI(localID + groupSize)] = posi2 < length ? globalArray[posi2] : 0;
// Up-sweep
for (int stride = 1, d = groupSize; stride <= groupSize; stride <<= 1, d >>= 1) {
__syncthreads();
if (localID < d) {
posi1 = stride * ((localID << 1) + 1) - 1;
posi2 = posi1 + stride;
localArray[POSI(posi2)] += localArray[POSI(posi1)];
}
}
// Down-sweep
for (int stride = groupSize, d = 1; stride >= 1; stride >>= 1, d <<= 1) {
__syncthreads();
if (localID < d) {
posi1 = stride * ((localID << 1) + 1) - 1;
posi2 = POSI(posi1 + stride);
posi1 = POSI(posi1);
int t = localArray[posi1];
localArray[posi1] = localArray[posi2];
localArray[posi2] = localArray[posi2] * !!localID + t;
}
}
__syncthreads();
// Write to global memory
posi1 = startOffset + localID * step;
posi2 = posi1 + groupSize * step;
if (posi1 < length) globalArray[posi1] = localArray[POSI(localID)];
if (posi2 < length) globalArray[posi2] = localArray[POSI(localID + groupSize)];
}
__global__ void ReverseUpdateKernel(int *globalArray, int length, int step) {
int localID = threadIdx.x;
int groupID = blockIdx.x;
int groupSize = blockDim.x;
int startOffset = groupID * (groupSize << 1) * step;
if (groupID) {
int value = globalArray[startOffset];
int posi1 = startOffset + localID * step;
int posi2 = posi1 + groupSize * step;
if (posi1 < length && localID) globalArray[posi1] += value;
if (posi2 < length) globalArray[posi2] += value;
}
}
extern "C"
int ExclusiveScanForInt(int *d_arr, int length) {
cudaError_t err;
// Get the work group size
int localWorkSize = BLOCK_SIZE;
// Up-sweep and down-sweep
static int records[10];
int problemSize = length;
int numOfRecords = 0;
int d_step = 1;
/// DEBUG ///
//printf("length = %d\n", length);
dim3 dimBlock(BLOCK_SIZE, 1, 1);
dim3 dimGrid(1, 1, 1);
for (; problemSize > 1; problemSize = (problemSize - 1) / (localWorkSize * 2) + 1) {
if (numOfRecords) d_step *= localWorkSize * 2;
records[numOfRecords++] = problemSize;
dimGrid.x = (problemSize - 1) / (localWorkSize * 2) + 1;
ScanKernel<<<dimGrid, dimBlock>>>(d_arr, length, d_step);
err = cudaDeviceSynchronize();
if (err) {
printf("Fail to finish scan kernel");
cudaGetErrorString(err);
exit(0);
}
}
int sum;
err = cudaMemcpy(&sum, d_arr, sizeof(int), cudaMemcpyDeviceToHost);
if (err) {
cudaGetErrorString(err);
exit(0);
}
err = cudaMemset(d_arr, 0, sizeof(int));
if (err) {
cudaGetErrorString(err);
exit(0);
}
// Reverse updates
for (int i = numOfRecords - 1; i >= 0; i--, d_step /= localWorkSize * 2) {
dimGrid.x = (records[i] - 1) / (localWorkSize * 2) + 1;
ReverseUpdateKernel<<<dimGrid, dimBlock>>>(d_arr, length, d_step);
err = cudaDeviceSynchronize();
if (err) {
printf("Fail to finish reverse update kernel");
cudaGetErrorString(err);
exit(0);
}
}
return sum;
} | code for sm_80
Function : _Z19ReverseUpdateKernelPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a24 */
/* 0x000fe200078e02ff */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0080*/ IMAD R0, R0, c[0x0][0x16c], RZ ; /* 0x00005b0000007a24 */
/* 0x000fca00078e02ff */
/*0090*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fe200000006ff */
/*00a0*/ IMAD R5, R2, c[0x0][0x16c], RZ ; /* 0x00005b0002057a24 */
/* 0x001fc800078e02ff */
/*00b0*/ IMAD.IADD R6, R0, 0x1, R5 ; /* 0x0000000100067824 */
/* 0x000fca00078e0205 */
/*00c0*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fc80003f06270 */
/*00d0*/ ISETP.EQ.OR P0, PT, R2, RZ, P0 ; /* 0x000000ff0200720c */
/* 0x000fe20000702670 */
/*00e0*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0209 */
/*00f0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000eae000c1e1900 */
/*0100*/ @!P0 IMAD.WIDE R4, R5, 0x4, R2 ; /* 0x0000000405048825 */
/* 0x000fca00078e0202 */
/*0110*/ @!P0 LDG.E R7, [R4.64] ; /* 0x0000000404078981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0b7624 */
/* 0x000fc800078e00ff */
/*0130*/ IMAD R6, R11, c[0x0][0x16c], R6 ; /* 0x00005b000b067a24 */
/* 0x000fca00078e0206 */
/*0140*/ ISETP.GE.AND P1, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fe40003f26270 */
/*0150*/ @!P0 IADD3 R7, R0, R7, RZ ; /* 0x0000000700078210 */
/* 0x004fca0007ffe0ff */
/*0160*/ @!P0 STG.E [R4.64], R7 ; /* 0x0000000704008986 */
/* 0x0001ec000c101904 */
/*0170*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0180*/ IMAD.WIDE R2, R6, R9, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fca00078e0209 */
/*0190*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x001ea4000c1e1900 */
/*01a0*/ IADD3 R5, R0, R5, RZ ; /* 0x0000000500057210 */
/* 0x004fca0007ffe0ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10ScanKernelPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0030*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0a7624 */
/* 0x000fe200078e00ff */
/*0040*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0070*/ IMAD.SHL.U32 R3, R10, 0x2, RZ ; /* 0x000000020a037824 */
/* 0x000fc800078e00ff */
/*0080*/ IMAD R3, R3, UR4, R0 ; /* 0x0000000403037c24 */
/* 0x001fc8000f8e0200 */
/*0090*/ IMAD R3, R3, c[0x0][0x16c], RZ ; /* 0x00005b0003037a24 */
/* 0x000fc800078e02ff */
/*00a0*/ IMAD R4, R10, c[0x0][0x16c], R3 ; /* 0x00005b000a047a24 */
/* 0x000fe200078e0203 */
/*00b0*/ ISETP.GE.AND P0, PT, R3.reuse, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x040fe20003f06270 */
/*00c0*/ IMAD.WIDE R2, R3, R5, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc600078e0205 */
/*00d0*/ ISETP.GE.AND P1, PT, R4.reuse, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x040fe20003f26270 */
/*00e0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fd000078e0205 */
/*00f0*/ @!P0 LDG.E R9, [R2.64] ; /* 0x0000000602098981 */
/* 0x000ea8000c1e1900 */
/*0100*/ @!P1 LDG.E R8, [R4.64] ; /* 0x0000000604089981 */
/* 0x000ee2000c1e1900 */
/*0110*/ IADD3 R7, R0.reuse, c[0x0][0x0], RZ ; /* 0x0000000000077a10 */
/* 0x040fe40007ffe0ff */
/*0120*/ LEA.HI.SX32 R6, R0, R0, 0x1b ; /* 0x0000000000067211 */
/* 0x000fe400078fdaff */
/*0130*/ LEA.HI.SX32 R7, R7, R7, 0x1b ; /* 0x0000000707077211 */
/* 0x000fe400078fdaff */
/*0140*/ ISETP.GE.AND P2, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe20003f46270 */
/*0150*/ STS [R6.X4], R9 ; /* 0x0000000906007388 */
/* 0x0041e80000004800 */
/*0160*/ STS [R7.X4], R8 ; /* 0x0000000807007388 */
/* 0x0081f00000004800 */
/*0170*/ @!P2 BRA 0x480 ; /* 0x000003000000a947 */
/* 0x000fea0003800000 */
/*0180*/ LEA R8, R0, 0x1, 0x1 ; /* 0x0000000100087811 */
/* 0x001fe200078e08ff */
/*0190*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe200078e00ff */
/*01a0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fc40000000800 */
/*01b0*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe40000000800 */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01d0*/ ISETP.GE.AND P2, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x000fca000bf46270 */
/*01e0*/ BSSY B0, 0x2b0 ; /* 0x000000c000007945 */
/* 0x000ff00003800000 */
/*01f0*/ @P2 BRA 0x2a0 ; /* 0x000000a000002947 */
/* 0x001fea0003800000 */
/*0200*/ IMAD R10, R8, R9, RZ ; /* 0x00000009080a7224 */
/* 0x000fc800078e02ff */
/*0210*/ IMAD.IADD R13, R10.reuse, 0x1, R9 ; /* 0x000000010a0d7824 */
/* 0x040fe200078e0209 */
/*0220*/ IADD3 R11, R10, -0x1, RZ ; /* 0xffffffff0a0b7810 */
/* 0x000fc80007ffe0ff */
/*0230*/ LEA.HI.SX32 R10, R11.reuse, R10, 0x1b ; /* 0x0000000a0b0a7211 */
/* 0x040fe200078fdaff */
/*0240*/ IMAD.IADD R12, R11, 0x1, R9 ; /* 0x000000010b0c7824 */
/* 0x000fca00078e0209 */
/*0250*/ LEA.HI.SX32 R12, R12, R13, 0x1b ; /* 0x0000000d0c0c7211 */
/* 0x000fe200078fdaff */
/*0260*/ LDS R10, [R10.X4+-0x4] ; /* 0xfffffc000a0a7984 */
/* 0x000fe80000004800 */
/*0270*/ LDS R11, [R12.X4+-0x4] ; /* 0xfffffc000c0b7984 */
/* 0x000e240000004800 */
/*0280*/ IMAD.IADD R11, R11, 0x1, R10 ; /* 0x000000010b0b7824 */
/* 0x001fca00078e020a */
/*0290*/ STS [R12.X4+-0x4], R11 ; /* 0xfffffc0b0c007388 */
/* 0x0001e40000004800 */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02b0*/ IMAD.SHL.U32 R9, R9, 0x2, RZ ; /* 0x0000000209097824 */
/* 0x000fe200078e00ff */
/*02c0*/ USHF.R.S32.HI UR5, URZ, 0x1, UR5 ; /* 0x000000013f057899 */
/* 0x000fc80008011405 */
/*02d0*/ ISETP.GT.AND P2, PT, R9, c[0x0][0x0], PT ; /* 0x0000000009007a0c */
/* 0x000fda0003f44270 */
/*02e0*/ @!P2 BRA 0x1c0 ; /* 0xfffffed00000a947 */
/* 0x000fea000383ffff */
/*02f0*/ LEA R13, R0, 0x1, 0x1 ; /* 0x00000001000d7811 */
/* 0x000fe200078e08ff */
/*0300*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe40000000000 */
/*0310*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0320*/ ISETP.GE.AND P2, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x000fca000bf46270 */
/*0330*/ BSSY B0, 0x440 ; /* 0x0000010000007945 */
/* 0x000ff00003800000 */
/*0340*/ @P2 BRA 0x430 ; /* 0x000000e000002947 */
/* 0x001fea0003800000 */
/*0350*/ IMAD R8, R13, UR4, RZ ; /* 0x000000040d087c24 */
/* 0x000fe2000f8e02ff */
/*0360*/ ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc80003f45270 */
/*0370*/ IADD3 R9, R8.reuse, -0x1, RZ ; /* 0xffffffff08097810 */
/* 0x040fe40007ffe0ff */
/*0380*/ IADD3 R11, R8, UR4, RZ ; /* 0x00000004080b7c10 */
/* 0x001fe4000fffe0ff */
/*0390*/ IADD3 R10, R9.reuse, UR4, RZ ; /* 0x00000004090a7c10 */
/* 0x040fe4000fffe0ff */
/*03a0*/ LEA.HI.SX32 R8, R9, R8, 0x1b ; /* 0x0000000809087211 */
/* 0x000fe400078fdaff */
/*03b0*/ LEA.HI.SX32 R10, R10, R11, 0x1b ; /* 0x0000000b0a0a7211 */
/* 0x000fc600078fdaff */
/*03c0*/ LDS R9, [R8.X4+-0x4] ; /* 0xfffffc0008097984 */
/* 0x000fe80000004800 */
/*03d0*/ LDS R11, [R10.X4+-0x4] ; /* 0xfffffc000a0b7984 */
/* 0x000e280000004800 */
/*03e0*/ STS [R8.X4+-0x4], R11 ; /* 0xfffffc0b08007388 */
/* 0x001fe80000004800 */
/*03f0*/ LDS R12, [R10.X4+-0x4] ; /* 0xfffffc000a0c7984 */
/* 0x000e240000004800 */
/*0400*/ SEL R12, R12, RZ, P2 ; /* 0x000000ff0c0c7207 */
/* 0x001fca0001000000 */
/*0410*/ IMAD.IADD R9, R9, 0x1, R12 ; /* 0x0000000109097824 */
/* 0x000fca00078e020c */
/*0420*/ STS [R10.X4+-0x4], R9 ; /* 0xfffffc090a007388 */
/* 0x0001e40000004800 */
/*0430*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0440*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe40008011604 */
/*0450*/ USHF.L.U32 UR5, UR5, 0x1, URZ ; /* 0x0000000105057899 */
/* 0x000fc8000800063f */
/*0460*/ ISETP.NE.AND P2, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf45270 */
/*0470*/ @P2 BRA 0x310 ; /* 0xfffffe9000002947 */
/* 0x000fea000383ffff */
/*0480*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0490*/ @!P0 LDS R9, [R6.X4] ; /* 0x0000000006098984 */
/* 0x001e280000004800 */
/*04a0*/ @!P0 STG.E [R2.64], R9 ; /* 0x0000000902008986 */
/* 0x0011e2000c101906 */
/*04b0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*04c0*/ LDS R7, [R7.X4] ; /* 0x0000000007077984 */
/* 0x000e680000004800 */
/*04d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x002fe2000c101906 */
/*04e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04f0*/ BRA 0x4f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /******************************************************************
File : lcsExclusiveScanForInt.cu
Author : Mingcheng Chen
Last Update : January 29th, 2013
*******************************************************************/
#include <stdio.h>
#define BLOCK_SIZE 512
#define NUM_BANKS 32
#define LOG_NUM_BANKS 5
#define CONFLICT_FREE_OFFSET(n) ((n) >> (LOG_NUM_BANKS))
#define POSI(n) ((n) + CONFLICT_FREE_OFFSET(n))
__global__ void ScanKernel(int *globalArray, int length, int step) {
__shared__ int localArray[POSI(BLOCK_SIZE << 1) + 1];
int localID = threadIdx.x;
int groupID = blockIdx.x;
int groupSize = blockDim.x;
int startOffset = (groupSize << 1) * groupID * step;
int posi1 = startOffset + localID * step;
int posi2 = posi1 + groupSize * step;
localArray[POSI(localID)] = posi1 < length ? globalArray[posi1] : 0;
localArray[POSI(localID + groupSize)] = posi2 < length ? globalArray[posi2] : 0;
// Up-sweep
for (int stride = 1, d = groupSize; stride <= groupSize; stride <<= 1, d >>= 1) {
__syncthreads();
if (localID < d) {
posi1 = stride * ((localID << 1) + 1) - 1;
posi2 = posi1 + stride;
localArray[POSI(posi2)] += localArray[POSI(posi1)];
}
}
// Down-sweep
for (int stride = groupSize, d = 1; stride >= 1; stride >>= 1, d <<= 1) {
__syncthreads();
if (localID < d) {
posi1 = stride * ((localID << 1) + 1) - 1;
posi2 = POSI(posi1 + stride);
posi1 = POSI(posi1);
int t = localArray[posi1];
localArray[posi1] = localArray[posi2];
localArray[posi2] = localArray[posi2] * !!localID + t;
}
}
__syncthreads();
// Write to global memory
posi1 = startOffset + localID * step;
posi2 = posi1 + groupSize * step;
if (posi1 < length) globalArray[posi1] = localArray[POSI(localID)];
if (posi2 < length) globalArray[posi2] = localArray[POSI(localID + groupSize)];
}
__global__ void ReverseUpdateKernel(int *globalArray, int length, int step) {
int localID = threadIdx.x;
int groupID = blockIdx.x;
int groupSize = blockDim.x;
int startOffset = groupID * (groupSize << 1) * step;
if (groupID) {
int value = globalArray[startOffset];
int posi1 = startOffset + localID * step;
int posi2 = posi1 + groupSize * step;
if (posi1 < length && localID) globalArray[posi1] += value;
if (posi2 < length) globalArray[posi2] += value;
}
}
extern "C"
int ExclusiveScanForInt(int *d_arr, int length) {
cudaError_t err;
// Get the work group size
int localWorkSize = BLOCK_SIZE;
// Up-sweep and down-sweep
static int records[10];
int problemSize = length;
int numOfRecords = 0;
int d_step = 1;
/// DEBUG ///
//printf("length = %d\n", length);
dim3 dimBlock(BLOCK_SIZE, 1, 1);
dim3 dimGrid(1, 1, 1);
for (; problemSize > 1; problemSize = (problemSize - 1) / (localWorkSize * 2) + 1) {
if (numOfRecords) d_step *= localWorkSize * 2;
records[numOfRecords++] = problemSize;
dimGrid.x = (problemSize - 1) / (localWorkSize * 2) + 1;
ScanKernel<<<dimGrid, dimBlock>>>(d_arr, length, d_step);
err = cudaDeviceSynchronize();
if (err) {
printf("Fail to finish scan kernel");
cudaGetErrorString(err);
exit(0);
}
}
int sum;
err = cudaMemcpy(&sum, d_arr, sizeof(int), cudaMemcpyDeviceToHost);
if (err) {
cudaGetErrorString(err);
exit(0);
}
err = cudaMemset(d_arr, 0, sizeof(int));
if (err) {
cudaGetErrorString(err);
exit(0);
}
// Reverse updates
for (int i = numOfRecords - 1; i >= 0; i--, d_step /= localWorkSize * 2) {
dimGrid.x = (records[i] - 1) / (localWorkSize * 2) + 1;
ReverseUpdateKernel<<<dimGrid, dimBlock>>>(d_arr, length, d_step);
err = cudaDeviceSynchronize();
if (err) {
printf("Fail to finish reverse update kernel");
cudaGetErrorString(err);
exit(0);
}
}
return sum;
} | .file "tmpxft_00006154_00000000-6_lcsExclusiveScanForInt.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10ScanKernelPiiiPiii
.type _Z32__device_stub__Z10ScanKernelPiiiPiii, @function
_Z32__device_stub__Z10ScanKernelPiiiPiii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10ScanKernelPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z10ScanKernelPiiiPiii, .-_Z32__device_stub__Z10ScanKernelPiiiPiii
.globl _Z10ScanKernelPiii
.type _Z10ScanKernelPiii, @function
_Z10ScanKernelPiii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10ScanKernelPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10ScanKernelPiii, .-_Z10ScanKernelPiii
.globl _Z41__device_stub__Z19ReverseUpdateKernelPiiiPiii
.type _Z41__device_stub__Z19ReverseUpdateKernelPiiiPiii, @function
_Z41__device_stub__Z19ReverseUpdateKernelPiiiPiii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z19ReverseUpdateKernelPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z41__device_stub__Z19ReverseUpdateKernelPiiiPiii, .-_Z41__device_stub__Z19ReverseUpdateKernelPiiiPiii
.globl _Z19ReverseUpdateKernelPiii
.type _Z19ReverseUpdateKernelPiii, @function
_Z19ReverseUpdateKernelPiii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z19ReverseUpdateKernelPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z19ReverseUpdateKernelPiii, .-_Z19ReverseUpdateKernelPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Fail to finish scan kernel"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Fail to finish reverse update kernel"
.text
.globl ExclusiveScanForInt
.type ExclusiveScanForInt, @function
ExclusiveScanForInt:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r15
movl %esi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $512, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %esi, %ebx
movl $0, %ebp
movl $1, %r12d
leaq _ZZ19ExclusiveScanForIntE7records(%rip), %r14
jmp .L20
.L22:
call cudaDeviceSynchronize@PLT
movl %eax, %r13d
addq $1, %rbp
testl %eax, %eax
jne .L34
.L20:
cmpl $1, %ebx
jle .L35
movl %r12d, %eax
sall $10, %eax
testl %ebp, %ebp
cmovne %eax, %r12d
movl %ebx, (%r14,%rbp,4)
leal 1022(%rbx), %eax
subl $1, %ebx
cmovs %eax, %ebx
sarl $10, %ebx
addl $1, %ebx
movl %ebx, 44(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L22
movl %r12d, %edx
movl 12(%rsp), %esi
movq %r15, %rdi
call _Z32__device_stub__Z10ScanKernelPiiiPiii
jmp .L22
.L34:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movl $0, %edi
call exit@PLT
.L35:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq %r15, %rsi
call cudaMemcpy@PLT
testl %eax, %eax
je .L24
movl %eax, %edi
call cudaGetErrorString@PLT
movl $0, %edi
call exit@PLT
.L24:
movl $4, %edx
movl $0, %esi
movq %r15, %rdi
call cudaMemset@PLT
testl %eax, %eax
jne .L36
testl %ebp, %ebp
jle .L26
movslq %ebp, %rax
leaq _ZZ19ExclusiveScanForIntE7records(%rip), %rdx
leaq (%rdx,%rax,4), %rbx
leal -1(%rbp), %edx
subq %rdx, %rax
leaq -4+_ZZ19ExclusiveScanForIntE7records(%rip), %rdx
leaq (%rdx,%rax,4), %rbp
jmp .L29
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movl $0, %edi
call exit@PLT
.L27:
call cudaDeviceSynchronize@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L37
leal 1023(%r12), %eax
testl %r12d, %r12d
cmovns %r12d, %eax
sarl $10, %eax
movl %eax, %r12d
subq $4, %rbx
cmpq %rbp, %rbx
je .L26
.L29:
movl -4(%rbx), %edx
leal 1022(%rdx), %eax
subl $1, %edx
cmovns %edx, %eax
sarl $10, %eax
addl $1, %eax
movl %eax, 44(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L27
movl %r12d, %edx
movl 12(%rsp), %esi
movq %r15, %rdi
call _Z41__device_stub__Z19ReverseUpdateKernelPiiiPiii
jmp .L27
.L37:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movl $0, %edi
call exit@PLT
.L26:
movl 28(%rsp), %eax
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L38
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size ExclusiveScanForInt, .-ExclusiveScanForInt
.section .rodata.str1.1
.LC2:
.string "_Z19ReverseUpdateKernelPiii"
.LC3:
.string "_Z10ScanKernelPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z19ReverseUpdateKernelPiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10ScanKernelPiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZ19ExclusiveScanForIntE7records
.comm _ZZ19ExclusiveScanForIntE7records,40,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /******************************************************************
File : lcsExclusiveScanForInt.cu
Author : Mingcheng Chen
Last Update : January 29th, 2013
*******************************************************************/
#include <stdio.h>
#define BLOCK_SIZE 512
#define NUM_BANKS 32
#define LOG_NUM_BANKS 5
#define CONFLICT_FREE_OFFSET(n) ((n) >> (LOG_NUM_BANKS))
#define POSI(n) ((n) + CONFLICT_FREE_OFFSET(n))
__global__ void ScanKernel(int *globalArray, int length, int step) {
__shared__ int localArray[POSI(BLOCK_SIZE << 1) + 1];
int localID = threadIdx.x;
int groupID = blockIdx.x;
int groupSize = blockDim.x;
int startOffset = (groupSize << 1) * groupID * step;
int posi1 = startOffset + localID * step;
int posi2 = posi1 + groupSize * step;
localArray[POSI(localID)] = posi1 < length ? globalArray[posi1] : 0;
localArray[POSI(localID + groupSize)] = posi2 < length ? globalArray[posi2] : 0;
// Up-sweep
for (int stride = 1, d = groupSize; stride <= groupSize; stride <<= 1, d >>= 1) {
__syncthreads();
if (localID < d) {
posi1 = stride * ((localID << 1) + 1) - 1;
posi2 = posi1 + stride;
localArray[POSI(posi2)] += localArray[POSI(posi1)];
}
}
// Down-sweep
for (int stride = groupSize, d = 1; stride >= 1; stride >>= 1, d <<= 1) {
__syncthreads();
if (localID < d) {
posi1 = stride * ((localID << 1) + 1) - 1;
posi2 = POSI(posi1 + stride);
posi1 = POSI(posi1);
int t = localArray[posi1];
localArray[posi1] = localArray[posi2];
localArray[posi2] = localArray[posi2] * !!localID + t;
}
}
__syncthreads();
// Write to global memory
posi1 = startOffset + localID * step;
posi2 = posi1 + groupSize * step;
if (posi1 < length) globalArray[posi1] = localArray[POSI(localID)];
if (posi2 < length) globalArray[posi2] = localArray[POSI(localID + groupSize)];
}
__global__ void ReverseUpdateKernel(int *globalArray, int length, int step) {
int localID = threadIdx.x;
int groupID = blockIdx.x;
int groupSize = blockDim.x;
int startOffset = groupID * (groupSize << 1) * step;
if (groupID) {
int value = globalArray[startOffset];
int posi1 = startOffset + localID * step;
int posi2 = posi1 + groupSize * step;
if (posi1 < length && localID) globalArray[posi1] += value;
if (posi2 < length) globalArray[posi2] += value;
}
}
extern "C"
int ExclusiveScanForInt(int *d_arr, int length) {
cudaError_t err;
// Get the work group size
int localWorkSize = BLOCK_SIZE;
// Up-sweep and down-sweep
static int records[10];
int problemSize = length;
int numOfRecords = 0;
int d_step = 1;
/// DEBUG ///
//printf("length = %d\n", length);
dim3 dimBlock(BLOCK_SIZE, 1, 1);
dim3 dimGrid(1, 1, 1);
for (; problemSize > 1; problemSize = (problemSize - 1) / (localWorkSize * 2) + 1) {
if (numOfRecords) d_step *= localWorkSize * 2;
records[numOfRecords++] = problemSize;
dimGrid.x = (problemSize - 1) / (localWorkSize * 2) + 1;
ScanKernel<<<dimGrid, dimBlock>>>(d_arr, length, d_step);
err = cudaDeviceSynchronize();
if (err) {
printf("Fail to finish scan kernel");
cudaGetErrorString(err);
exit(0);
}
}
int sum;
err = cudaMemcpy(&sum, d_arr, sizeof(int), cudaMemcpyDeviceToHost);
if (err) {
cudaGetErrorString(err);
exit(0);
}
err = cudaMemset(d_arr, 0, sizeof(int));
if (err) {
cudaGetErrorString(err);
exit(0);
}
// Reverse updates
for (int i = numOfRecords - 1; i >= 0; i--, d_step /= localWorkSize * 2) {
dimGrid.x = (records[i] - 1) / (localWorkSize * 2) + 1;
ReverseUpdateKernel<<<dimGrid, dimBlock>>>(d_arr, length, d_step);
err = cudaDeviceSynchronize();
if (err) {
printf("Fail to finish reverse update kernel");
cudaGetErrorString(err);
exit(0);
}
}
return sum;
} | /******************************************************************
File : lcsExclusiveScanForInt.cu
Author : Mingcheng Chen
Last Update : January 29th, 2013
*******************************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCK_SIZE 512
#define NUM_BANKS 32
#define LOG_NUM_BANKS 5
#define CONFLICT_FREE_OFFSET(n) ((n) >> (LOG_NUM_BANKS))
#define POSI(n) ((n) + CONFLICT_FREE_OFFSET(n))
__global__ void ScanKernel(int *globalArray, int length, int step) {
__shared__ int localArray[POSI(BLOCK_SIZE << 1) + 1];
int localID = threadIdx.x;
int groupID = blockIdx.x;
int groupSize = blockDim.x;
int startOffset = (groupSize << 1) * groupID * step;
int posi1 = startOffset + localID * step;
int posi2 = posi1 + groupSize * step;
localArray[POSI(localID)] = posi1 < length ? globalArray[posi1] : 0;
localArray[POSI(localID + groupSize)] = posi2 < length ? globalArray[posi2] : 0;
// Up-sweep
for (int stride = 1, d = groupSize; stride <= groupSize; stride <<= 1, d >>= 1) {
__syncthreads();
if (localID < d) {
posi1 = stride * ((localID << 1) + 1) - 1;
posi2 = posi1 + stride;
localArray[POSI(posi2)] += localArray[POSI(posi1)];
}
}
// Down-sweep
for (int stride = groupSize, d = 1; stride >= 1; stride >>= 1, d <<= 1) {
__syncthreads();
if (localID < d) {
posi1 = stride * ((localID << 1) + 1) - 1;
posi2 = POSI(posi1 + stride);
posi1 = POSI(posi1);
int t = localArray[posi1];
localArray[posi1] = localArray[posi2];
localArray[posi2] = localArray[posi2] * !!localID + t;
}
}
__syncthreads();
// Write to global memory
posi1 = startOffset + localID * step;
posi2 = posi1 + groupSize * step;
if (posi1 < length) globalArray[posi1] = localArray[POSI(localID)];
if (posi2 < length) globalArray[posi2] = localArray[POSI(localID + groupSize)];
}
__global__ void ReverseUpdateKernel(int *globalArray, int length, int step) {
int localID = threadIdx.x;
int groupID = blockIdx.x;
int groupSize = blockDim.x;
int startOffset = groupID * (groupSize << 1) * step;
if (groupID) {
int value = globalArray[startOffset];
int posi1 = startOffset + localID * step;
int posi2 = posi1 + groupSize * step;
if (posi1 < length && localID) globalArray[posi1] += value;
if (posi2 < length) globalArray[posi2] += value;
}
}
extern "C"
int ExclusiveScanForInt(int *d_arr, int length) {
hipError_t err;
// Get the work group size
int localWorkSize = BLOCK_SIZE;
// Up-sweep and down-sweep
static int records[10];
int problemSize = length;
int numOfRecords = 0;
int d_step = 1;
/// DEBUG ///
//printf("length = %d\n", length);
dim3 dimBlock(BLOCK_SIZE, 1, 1);
dim3 dimGrid(1, 1, 1);
for (; problemSize > 1; problemSize = (problemSize - 1) / (localWorkSize * 2) + 1) {
if (numOfRecords) d_step *= localWorkSize * 2;
records[numOfRecords++] = problemSize;
dimGrid.x = (problemSize - 1) / (localWorkSize * 2) + 1;
ScanKernel<<<dimGrid, dimBlock>>>(d_arr, length, d_step);
err = hipDeviceSynchronize();
if (err) {
printf("Fail to finish scan kernel");
hipGetErrorString(err);
exit(0);
}
}
int sum;
err = hipMemcpy(&sum, d_arr, sizeof(int), hipMemcpyDeviceToHost);
if (err) {
hipGetErrorString(err);
exit(0);
}
err = hipMemset(d_arr, 0, sizeof(int));
if (err) {
hipGetErrorString(err);
exit(0);
}
// Reverse updates
for (int i = numOfRecords - 1; i >= 0; i--, d_step /= localWorkSize * 2) {
dimGrid.x = (records[i] - 1) / (localWorkSize * 2) + 1;
ReverseUpdateKernel<<<dimGrid, dimBlock>>>(d_arr, length, d_step);
err = hipDeviceSynchronize();
if (err) {
printf("Fail to finish reverse update kernel");
hipGetErrorString(err);
exit(0);
}
}
return sum;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /******************************************************************
File : lcsExclusiveScanForInt.cu
Author : Mingcheng Chen
Last Update : January 29th, 2013
*******************************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCK_SIZE 512
#define NUM_BANKS 32
#define LOG_NUM_BANKS 5
#define CONFLICT_FREE_OFFSET(n) ((n) >> (LOG_NUM_BANKS))
#define POSI(n) ((n) + CONFLICT_FREE_OFFSET(n))
__global__ void ScanKernel(int *globalArray, int length, int step) {
__shared__ int localArray[POSI(BLOCK_SIZE << 1) + 1];
int localID = threadIdx.x;
int groupID = blockIdx.x;
int groupSize = blockDim.x;
int startOffset = (groupSize << 1) * groupID * step;
int posi1 = startOffset + localID * step;
int posi2 = posi1 + groupSize * step;
localArray[POSI(localID)] = posi1 < length ? globalArray[posi1] : 0;
localArray[POSI(localID + groupSize)] = posi2 < length ? globalArray[posi2] : 0;
// Up-sweep
for (int stride = 1, d = groupSize; stride <= groupSize; stride <<= 1, d >>= 1) {
__syncthreads();
if (localID < d) {
posi1 = stride * ((localID << 1) + 1) - 1;
posi2 = posi1 + stride;
localArray[POSI(posi2)] += localArray[POSI(posi1)];
}
}
// Down-sweep
for (int stride = groupSize, d = 1; stride >= 1; stride >>= 1, d <<= 1) {
__syncthreads();
if (localID < d) {
posi1 = stride * ((localID << 1) + 1) - 1;
posi2 = POSI(posi1 + stride);
posi1 = POSI(posi1);
int t = localArray[posi1];
localArray[posi1] = localArray[posi2];
localArray[posi2] = localArray[posi2] * !!localID + t;
}
}
__syncthreads();
// Write to global memory
posi1 = startOffset + localID * step;
posi2 = posi1 + groupSize * step;
if (posi1 < length) globalArray[posi1] = localArray[POSI(localID)];
if (posi2 < length) globalArray[posi2] = localArray[POSI(localID + groupSize)];
}
__global__ void ReverseUpdateKernel(int *globalArray, int length, int step) {
int localID = threadIdx.x;
int groupID = blockIdx.x;
int groupSize = blockDim.x;
int startOffset = groupID * (groupSize << 1) * step;
if (groupID) {
int value = globalArray[startOffset];
int posi1 = startOffset + localID * step;
int posi2 = posi1 + groupSize * step;
if (posi1 < length && localID) globalArray[posi1] += value;
if (posi2 < length) globalArray[posi2] += value;
}
}
extern "C"
int ExclusiveScanForInt(int *d_arr, int length) {
hipError_t err;
// Get the work group size
int localWorkSize = BLOCK_SIZE;
// Up-sweep and down-sweep
static int records[10];
int problemSize = length;
int numOfRecords = 0;
int d_step = 1;
/// DEBUG ///
//printf("length = %d\n", length);
dim3 dimBlock(BLOCK_SIZE, 1, 1);
dim3 dimGrid(1, 1, 1);
for (; problemSize > 1; problemSize = (problemSize - 1) / (localWorkSize * 2) + 1) {
if (numOfRecords) d_step *= localWorkSize * 2;
records[numOfRecords++] = problemSize;
dimGrid.x = (problemSize - 1) / (localWorkSize * 2) + 1;
ScanKernel<<<dimGrid, dimBlock>>>(d_arr, length, d_step);
err = hipDeviceSynchronize();
if (err) {
printf("Fail to finish scan kernel");
hipGetErrorString(err);
exit(0);
}
}
int sum;
err = hipMemcpy(&sum, d_arr, sizeof(int), hipMemcpyDeviceToHost);
if (err) {
hipGetErrorString(err);
exit(0);
}
err = hipMemset(d_arr, 0, sizeof(int));
if (err) {
hipGetErrorString(err);
exit(0);
}
// Reverse updates
for (int i = numOfRecords - 1; i >= 0; i--, d_step /= localWorkSize * 2) {
dimGrid.x = (records[i] - 1) / (localWorkSize * 2) + 1;
ReverseUpdateKernel<<<dimGrid, dimBlock>>>(d_arr, length, d_step);
err = hipDeviceSynchronize();
if (err) {
printf("Fail to finish reverse update kernel");
hipGetErrorString(err);
exit(0);
}
}
return sum;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10ScanKernelPiii
.globl _Z10ScanKernelPiii
.p2align 8
.type _Z10ScanKernelPiii,@function
_Z10ScanKernelPiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s2
v_lshl_add_u32 v3, s15, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v3, s7
v_cmp_gt_i32_e32 vcc_lo, s6, v1
s_and_saveexec_b32 s1, vcc_lo
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_co_u32 v6, s0, s4, v6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
global_load_b32 v4, v[6:7], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v2, s2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v2, s7
v_lshrrev_b32_e32 v2, 5, v0
v_add_lshl_u32 v2, v2, v0, 2
s_delay_alu instid0(VALU_DEP_3)
v_cmp_gt_i32_e64 s0, s6, v3
s_waitcnt vmcnt(0)
ds_store_b32 v2, v4
s_and_saveexec_b32 s3, s0
s_cbranch_execz .LBB0_4
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[3:4]
v_add_co_u32 v4, s1, s4, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s1, s5, v5, s1
global_load_b32 v5, v[4:5], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s3
v_add_nc_u32_e32 v4, s2, v0
s_cmp_eq_u32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v6, 5, v4
v_add_lshl_u32 v4, v6, v4, 2
s_waitcnt vmcnt(0)
ds_store_b32 v4, v5
s_cbranch_scc1 .LBB0_13
v_lshl_or_b32 v5, v0, 1, 1
s_mov_b32 s3, 1
s_mov_b32 s6, s2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_7
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s7
s_lshl_b32 s3, s3, 1
s_lshr_b32 s6, s6, 1
s_cmp_gt_i32 s3, s2
s_cbranch_scc1 .LBB0_9
.LBB0_7:
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s6, v0
s_cbranch_execz .LBB0_6
v_mad_u64_u32 v[6:7], null, s3, v5, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, s3, v6
v_ashrrev_i32_e32 v8, 5, v6
v_ashrrev_i32_e32 v9, 5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_lshl_u32 v6, v8, v6, 2
v_add_lshl_u32 v7, v9, v7, 2
ds_load_b32 v6, v6
ds_load_b32 v8, v7
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v6, v8, v6
ds_store_b32 v7, v6
s_branch .LBB0_6
.LBB0_9:
s_set_inst_prefetch_distance 0x2
v_lshl_or_b32 v5, v0, 1, 1
v_cmp_eq_u32_e64 s3, 0, v0
s_mov_b32 s6, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_11
.p2align 6
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s7
s_lshr_b32 s1, s2, 1
s_lshl_b32 s6, s6, 1
s_cmp_lt_u32 s2, 2
s_mov_b32 s2, s1
s_cbranch_scc1 .LBB0_13
.LBB0_11:
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e64 s6, v0
s_cbranch_execz .LBB0_10
v_mad_u32_u24 v6, s2, v5, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, s2, v6
v_ashrrev_i32_e32 v9, 5, v6
v_ashrrev_i32_e32 v8, 5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_lshl_u32 v6, v9, v6, 2
v_add_lshl_u32 v7, v8, v7, 2
ds_load_b32 v9, v6
ds_load_b32 v8, v7
s_waitcnt lgkmcnt(0)
ds_store_b32 v6, v8
ds_load_b32 v6, v7
s_waitcnt lgkmcnt(0)
v_cndmask_b32_e64 v6, v6, 0, s3
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v6, v6, v9
ds_store_b32 v7, v6
s_branch .LBB0_10
.LBB0_13:
s_set_inst_prefetch_distance 0x2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s1, vcc_lo
s_cbranch_execz .LBB0_15
ds_load_b32 v5, v2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v5, off
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
ds_load_b32 v2, v4
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10ScanKernelPiii
.amdhsa_group_segment_fixed_size 4228
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10ScanKernelPiii, .Lfunc_end0-_Z10ScanKernelPiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z19ReverseUpdateKernelPiii
.globl _Z19ReverseUpdateKernelPiii
.p2align 8
.type _Z19ReverseUpdateKernelPiii,@function
_Z19ReverseUpdateKernelPiii:
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB1_5
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s0, s2, s15
s_lshl_b32 s3, s0, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s0, s3, s7
v_add_nc_u32_e32 v3, s3, v0
s_ashr_i32 s1, s0, 31
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_mul_lo_u32 v1, v3, s7
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
s_load_b32 s1, s[0:1], 0x0
v_cmp_ne_u32_e64 s0, 0, v0
v_cmp_gt_i32_e32 vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s0, vcc_lo
s_and_saveexec_b32 s0, s3
s_cbranch_execz .LBB1_3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v2, s1, v2
global_store_b32 v[0:1], v2, off
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v0, s2, v3
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s7
v_cmpx_gt_i32_e64 s6, v0
s_cbranch_execz .LBB1_5
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v2, s1, v2
global_store_b32 v[0:1], v2, off
.LBB1_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19ReverseUpdateKernelPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z19ReverseUpdateKernelPiii, .Lfunc_end1-_Z19ReverseUpdateKernelPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4228
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10ScanKernelPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10ScanKernelPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19ReverseUpdateKernelPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19ReverseUpdateKernelPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /******************************************************************
File : lcsExclusiveScanForInt.cu
Author : Mingcheng Chen
Last Update : January 29th, 2013
*******************************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCK_SIZE 512
#define NUM_BANKS 32
#define LOG_NUM_BANKS 5
#define CONFLICT_FREE_OFFSET(n) ((n) >> (LOG_NUM_BANKS))
#define POSI(n) ((n) + CONFLICT_FREE_OFFSET(n))
__global__ void ScanKernel(int *globalArray, int length, int step) {
__shared__ int localArray[POSI(BLOCK_SIZE << 1) + 1];
int localID = threadIdx.x;
int groupID = blockIdx.x;
int groupSize = blockDim.x;
int startOffset = (groupSize << 1) * groupID * step;
int posi1 = startOffset + localID * step;
int posi2 = posi1 + groupSize * step;
localArray[POSI(localID)] = posi1 < length ? globalArray[posi1] : 0;
localArray[POSI(localID + groupSize)] = posi2 < length ? globalArray[posi2] : 0;
// Up-sweep
for (int stride = 1, d = groupSize; stride <= groupSize; stride <<= 1, d >>= 1) {
__syncthreads();
if (localID < d) {
posi1 = stride * ((localID << 1) + 1) - 1;
posi2 = posi1 + stride;
localArray[POSI(posi2)] += localArray[POSI(posi1)];
}
}
// Down-sweep
for (int stride = groupSize, d = 1; stride >= 1; stride >>= 1, d <<= 1) {
__syncthreads();
if (localID < d) {
posi1 = stride * ((localID << 1) + 1) - 1;
posi2 = POSI(posi1 + stride);
posi1 = POSI(posi1);
int t = localArray[posi1];
localArray[posi1] = localArray[posi2];
localArray[posi2] = localArray[posi2] * !!localID + t;
}
}
__syncthreads();
// Write to global memory
posi1 = startOffset + localID * step;
posi2 = posi1 + groupSize * step;
if (posi1 < length) globalArray[posi1] = localArray[POSI(localID)];
if (posi2 < length) globalArray[posi2] = localArray[POSI(localID + groupSize)];
}
__global__ void ReverseUpdateKernel(int *globalArray, int length, int step) {
int localID = threadIdx.x;
int groupID = blockIdx.x;
int groupSize = blockDim.x;
int startOffset = groupID * (groupSize << 1) * step;
if (groupID) {
int value = globalArray[startOffset];
int posi1 = startOffset + localID * step;
int posi2 = posi1 + groupSize * step;
if (posi1 < length && localID) globalArray[posi1] += value;
if (posi2 < length) globalArray[posi2] += value;
}
}
extern "C"
int ExclusiveScanForInt(int *d_arr, int length) {
hipError_t err;
// Get the work group size
int localWorkSize = BLOCK_SIZE;
// Up-sweep and down-sweep
static int records[10];
int problemSize = length;
int numOfRecords = 0;
int d_step = 1;
/// DEBUG ///
//printf("length = %d\n", length);
dim3 dimBlock(BLOCK_SIZE, 1, 1);
dim3 dimGrid(1, 1, 1);
for (; problemSize > 1; problemSize = (problemSize - 1) / (localWorkSize * 2) + 1) {
if (numOfRecords) d_step *= localWorkSize * 2;
records[numOfRecords++] = problemSize;
dimGrid.x = (problemSize - 1) / (localWorkSize * 2) + 1;
ScanKernel<<<dimGrid, dimBlock>>>(d_arr, length, d_step);
err = hipDeviceSynchronize();
if (err) {
printf("Fail to finish scan kernel");
hipGetErrorString(err);
exit(0);
}
}
int sum;
err = hipMemcpy(&sum, d_arr, sizeof(int), hipMemcpyDeviceToHost);
if (err) {
hipGetErrorString(err);
exit(0);
}
err = hipMemset(d_arr, 0, sizeof(int));
if (err) {
hipGetErrorString(err);
exit(0);
}
// Reverse updates
for (int i = numOfRecords - 1; i >= 0; i--, d_step /= localWorkSize * 2) {
dimGrid.x = (records[i] - 1) / (localWorkSize * 2) + 1;
ReverseUpdateKernel<<<dimGrid, dimBlock>>>(d_arr, length, d_step);
err = hipDeviceSynchronize();
if (err) {
printf("Fail to finish reverse update kernel");
hipGetErrorString(err);
exit(0);
}
}
return sum;
} | .text
.file "lcsExclusiveScanForInt.hip"
.globl _Z25__device_stub__ScanKernelPiii # -- Begin function _Z25__device_stub__ScanKernelPiii
.p2align 4, 0x90
.type _Z25__device_stub__ScanKernelPiii,@function
_Z25__device_stub__ScanKernelPiii: # @_Z25__device_stub__ScanKernelPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10ScanKernelPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__ScanKernelPiii, .Lfunc_end0-_Z25__device_stub__ScanKernelPiii
.cfi_endproc
# -- End function
.globl _Z34__device_stub__ReverseUpdateKernelPiii # -- Begin function _Z34__device_stub__ReverseUpdateKernelPiii
.p2align 4, 0x90
.type _Z34__device_stub__ReverseUpdateKernelPiii,@function
_Z34__device_stub__ReverseUpdateKernelPiii: # @_Z34__device_stub__ReverseUpdateKernelPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z19ReverseUpdateKernelPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z34__device_stub__ReverseUpdateKernelPiii, .Lfunc_end1-_Z34__device_stub__ReverseUpdateKernelPiii
.cfi_endproc
# -- End function
.globl ExclusiveScanForInt # -- Begin function ExclusiveScanForInt
.p2align 4, 0x90
.type ExclusiveScanForInt,@function
ExclusiveScanForInt: # @ExclusiveScanForInt
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %r12
movabsq $4294967296, %rax # imm = 0x100000000
movl $1, %ebx
xorl %r13d, %r13d
leaq 512(%rax), %r15
movl %esi, 12(%rsp) # 4-byte Spill
movl %esi, %r14d
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_1 Depth=1
callq hipDeviceSynchronize
incq %r13
testl %eax, %eax
jne .LBB2_5
.LBB2_1: # =>This Inner Loop Header: Depth=1
cmpl $2, %r14d
jl .LBB2_7
# %bb.2: # in Loop: Header=BB2_1 Depth=1
movl %ebx, %eax
shll $10, %eax
testq %r13, %r13
cmovnel %eax, %ebx
movl %r14d, _ZZ19ExclusiveScanForIntE7records(,%r13,4)
decl %r14d
shrl $10, %r14d
incl %r14d
movq %r14, %rdi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3: # in Loop: Header=BB2_1 Depth=1
movq %r12, 64(%rsp)
movl 12(%rsp), %eax # 4-byte Reload
movl %eax, 8(%rsp)
movl %ebx, 4(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z10ScanKernelPiii, %edi
leaq 80(%rsp), %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_4
.LBB2_7:
leaq 76(%rsp), %rdi
movl $4, %edx
movq %r12, %r14
movq %r12, %rsi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_8
# %bb.10:
movl $4, %edx
movq %r14, %rdi
xorl %esi, %esi
callq hipMemset
testl %eax, %eax
jne .LBB2_8
# %bb.11: # %.preheader
testl %r13d, %r13d
je .LBB2_18
# %bb.12:
incq %r13
leaq 48(%rsp), %r12
.p2align 4, 0x90
.LBB2_13: # =>This Inner Loop Header: Depth=1
leal -2(%r13), %eax
movl _ZZ19ExclusiveScanForIntE7records(,%rax,4), %edi
leal -1(%rdi), %eax
addl $1022, %edi # imm = 0x3FE
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
incl %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_15
# %bb.14: # in Loop: Header=BB2_13 Depth=1
movq %r14, 64(%rsp)
movl 12(%rsp), %eax # 4-byte Reload
movl %eax, 8(%rsp)
movl %ebx, 4(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %r12, %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z19ReverseUpdateKernelPiii, %edi
leaq 80(%rsp), %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_15: # in Loop: Header=BB2_13 Depth=1
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_16
# %bb.17: # in Loop: Header=BB2_13 Depth=1
leal 1023(%rbx), %eax
testl %ebx, %ebx
cmovnsl %ebx, %eax
sarl $10, %eax
decq %r13
movl %eax, %ebx
cmpq $1, %r13
jg .LBB2_13
.LBB2_18: # %._crit_edge
movl 76(%rsp), %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_5:
.cfi_def_cfa_offset 160
movl %eax, %ebp
movl $.L.str, %edi
jmp .LBB2_6
.LBB2_16:
movl %eax, %ebp
movl $.L.str.1, %edi
.LBB2_6:
xorl %eax, %eax
callq printf
movl %ebp, %edi
.LBB2_9:
callq hipGetErrorString
xorl %edi, %edi
callq exit
.LBB2_8:
movl %eax, %edi
jmp .LBB2_9
.Lfunc_end2:
.size ExclusiveScanForInt, .Lfunc_end2-ExclusiveScanForInt
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10ScanKernelPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19ReverseUpdateKernelPiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10ScanKernelPiii,@object # @_Z10ScanKernelPiii
.section .rodata,"a",@progbits
.globl _Z10ScanKernelPiii
.p2align 3, 0x0
_Z10ScanKernelPiii:
.quad _Z25__device_stub__ScanKernelPiii
.size _Z10ScanKernelPiii, 8
.type _Z19ReverseUpdateKernelPiii,@object # @_Z19ReverseUpdateKernelPiii
.globl _Z19ReverseUpdateKernelPiii
.p2align 3, 0x0
_Z19ReverseUpdateKernelPiii:
.quad _Z34__device_stub__ReverseUpdateKernelPiii
.size _Z19ReverseUpdateKernelPiii, 8
.type _ZZ19ExclusiveScanForIntE7records,@object # @_ZZ19ExclusiveScanForIntE7records
.local _ZZ19ExclusiveScanForIntE7records
.comm _ZZ19ExclusiveScanForIntE7records,40,16
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Fail to finish scan kernel"
.size .L.str, 27
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Fail to finish reverse update kernel"
.size .L.str.1, 37
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10ScanKernelPiii"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z19ReverseUpdateKernelPiii"
.size .L__unnamed_2, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__ScanKernelPiii
.addrsig_sym _Z34__device_stub__ReverseUpdateKernelPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10ScanKernelPiii
.addrsig_sym _Z19ReverseUpdateKernelPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19ReverseUpdateKernelPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a24 */
/* 0x000fe200078e02ff */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0080*/ IMAD R0, R0, c[0x0][0x16c], RZ ; /* 0x00005b0000007a24 */
/* 0x000fca00078e02ff */
/*0090*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fe200000006ff */
/*00a0*/ IMAD R5, R2, c[0x0][0x16c], RZ ; /* 0x00005b0002057a24 */
/* 0x001fc800078e02ff */
/*00b0*/ IMAD.IADD R6, R0, 0x1, R5 ; /* 0x0000000100067824 */
/* 0x000fca00078e0205 */
/*00c0*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fc80003f06270 */
/*00d0*/ ISETP.EQ.OR P0, PT, R2, RZ, P0 ; /* 0x000000ff0200720c */
/* 0x000fe20000702670 */
/*00e0*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0209 */
/*00f0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000eae000c1e1900 */
/*0100*/ @!P0 IMAD.WIDE R4, R5, 0x4, R2 ; /* 0x0000000405048825 */
/* 0x000fca00078e0202 */
/*0110*/ @!P0 LDG.E R7, [R4.64] ; /* 0x0000000404078981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0b7624 */
/* 0x000fc800078e00ff */
/*0130*/ IMAD R6, R11, c[0x0][0x16c], R6 ; /* 0x00005b000b067a24 */
/* 0x000fca00078e0206 */
/*0140*/ ISETP.GE.AND P1, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fe40003f26270 */
/*0150*/ @!P0 IADD3 R7, R0, R7, RZ ; /* 0x0000000700078210 */
/* 0x004fca0007ffe0ff */
/*0160*/ @!P0 STG.E [R4.64], R7 ; /* 0x0000000704008986 */
/* 0x0001ec000c101904 */
/*0170*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0180*/ IMAD.WIDE R2, R6, R9, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fca00078e0209 */
/*0190*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x001ea4000c1e1900 */
/*01a0*/ IADD3 R5, R0, R5, RZ ; /* 0x0000000500057210 */
/* 0x004fca0007ffe0ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10ScanKernelPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0030*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0a7624 */
/* 0x000fe200078e00ff */
/*0040*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0070*/ IMAD.SHL.U32 R3, R10, 0x2, RZ ; /* 0x000000020a037824 */
/* 0x000fc800078e00ff */
/*0080*/ IMAD R3, R3, UR4, R0 ; /* 0x0000000403037c24 */
/* 0x001fc8000f8e0200 */
/*0090*/ IMAD R3, R3, c[0x0][0x16c], RZ ; /* 0x00005b0003037a24 */
/* 0x000fc800078e02ff */
/*00a0*/ IMAD R4, R10, c[0x0][0x16c], R3 ; /* 0x00005b000a047a24 */
/* 0x000fe200078e0203 */
/*00b0*/ ISETP.GE.AND P0, PT, R3.reuse, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x040fe20003f06270 */
/*00c0*/ IMAD.WIDE R2, R3, R5, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc600078e0205 */
/*00d0*/ ISETP.GE.AND P1, PT, R4.reuse, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x040fe20003f26270 */
/*00e0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fd000078e0205 */
/*00f0*/ @!P0 LDG.E R9, [R2.64] ; /* 0x0000000602098981 */
/* 0x000ea8000c1e1900 */
/*0100*/ @!P1 LDG.E R8, [R4.64] ; /* 0x0000000604089981 */
/* 0x000ee2000c1e1900 */
/*0110*/ IADD3 R7, R0.reuse, c[0x0][0x0], RZ ; /* 0x0000000000077a10 */
/* 0x040fe40007ffe0ff */
/*0120*/ LEA.HI.SX32 R6, R0, R0, 0x1b ; /* 0x0000000000067211 */
/* 0x000fe400078fdaff */
/*0130*/ LEA.HI.SX32 R7, R7, R7, 0x1b ; /* 0x0000000707077211 */
/* 0x000fe400078fdaff */
/*0140*/ ISETP.GE.AND P2, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe20003f46270 */
/*0150*/ STS [R6.X4], R9 ; /* 0x0000000906007388 */
/* 0x0041e80000004800 */
/*0160*/ STS [R7.X4], R8 ; /* 0x0000000807007388 */
/* 0x0081f00000004800 */
/*0170*/ @!P2 BRA 0x480 ; /* 0x000003000000a947 */
/* 0x000fea0003800000 */
/*0180*/ LEA R8, R0, 0x1, 0x1 ; /* 0x0000000100087811 */
/* 0x001fe200078e08ff */
/*0190*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe200078e00ff */
/*01a0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fc40000000800 */
/*01b0*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe40000000800 */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01d0*/ ISETP.GE.AND P2, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x000fca000bf46270 */
/*01e0*/ BSSY B0, 0x2b0 ; /* 0x000000c000007945 */
/* 0x000ff00003800000 */
/*01f0*/ @P2 BRA 0x2a0 ; /* 0x000000a000002947 */
/* 0x001fea0003800000 */
/*0200*/ IMAD R10, R8, R9, RZ ; /* 0x00000009080a7224 */
/* 0x000fc800078e02ff */
/*0210*/ IMAD.IADD R13, R10.reuse, 0x1, R9 ; /* 0x000000010a0d7824 */
/* 0x040fe200078e0209 */
/*0220*/ IADD3 R11, R10, -0x1, RZ ; /* 0xffffffff0a0b7810 */
/* 0x000fc80007ffe0ff */
/*0230*/ LEA.HI.SX32 R10, R11.reuse, R10, 0x1b ; /* 0x0000000a0b0a7211 */
/* 0x040fe200078fdaff */
/*0240*/ IMAD.IADD R12, R11, 0x1, R9 ; /* 0x000000010b0c7824 */
/* 0x000fca00078e0209 */
/*0250*/ LEA.HI.SX32 R12, R12, R13, 0x1b ; /* 0x0000000d0c0c7211 */
/* 0x000fe200078fdaff */
/*0260*/ LDS R10, [R10.X4+-0x4] ; /* 0xfffffc000a0a7984 */
/* 0x000fe80000004800 */
/*0270*/ LDS R11, [R12.X4+-0x4] ; /* 0xfffffc000c0b7984 */
/* 0x000e240000004800 */
/*0280*/ IMAD.IADD R11, R11, 0x1, R10 ; /* 0x000000010b0b7824 */
/* 0x001fca00078e020a */
/*0290*/ STS [R12.X4+-0x4], R11 ; /* 0xfffffc0b0c007388 */
/* 0x0001e40000004800 */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02b0*/ IMAD.SHL.U32 R9, R9, 0x2, RZ ; /* 0x0000000209097824 */
/* 0x000fe200078e00ff */
/*02c0*/ USHF.R.S32.HI UR5, URZ, 0x1, UR5 ; /* 0x000000013f057899 */
/* 0x000fc80008011405 */
/*02d0*/ ISETP.GT.AND P2, PT, R9, c[0x0][0x0], PT ; /* 0x0000000009007a0c */
/* 0x000fda0003f44270 */
/*02e0*/ @!P2 BRA 0x1c0 ; /* 0xfffffed00000a947 */
/* 0x000fea000383ffff */
/*02f0*/ LEA R13, R0, 0x1, 0x1 ; /* 0x00000001000d7811 */
/* 0x000fe200078e08ff */
/*0300*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe40000000000 */
/*0310*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0320*/ ISETP.GE.AND P2, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x000fca000bf46270 */
/*0330*/ BSSY B0, 0x440 ; /* 0x0000010000007945 */
/* 0x000ff00003800000 */
/*0340*/ @P2 BRA 0x430 ; /* 0x000000e000002947 */
/* 0x001fea0003800000 */
/*0350*/ IMAD R8, R13, UR4, RZ ; /* 0x000000040d087c24 */
/* 0x000fe2000f8e02ff */
/*0360*/ ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc80003f45270 */
/*0370*/ IADD3 R9, R8.reuse, -0x1, RZ ; /* 0xffffffff08097810 */
/* 0x040fe40007ffe0ff */
/*0380*/ IADD3 R11, R8, UR4, RZ ; /* 0x00000004080b7c10 */
/* 0x001fe4000fffe0ff */
/*0390*/ IADD3 R10, R9.reuse, UR4, RZ ; /* 0x00000004090a7c10 */
/* 0x040fe4000fffe0ff */
/*03a0*/ LEA.HI.SX32 R8, R9, R8, 0x1b ; /* 0x0000000809087211 */
/* 0x000fe400078fdaff */
/*03b0*/ LEA.HI.SX32 R10, R10, R11, 0x1b ; /* 0x0000000b0a0a7211 */
/* 0x000fc600078fdaff */
/*03c0*/ LDS R9, [R8.X4+-0x4] ; /* 0xfffffc0008097984 */
/* 0x000fe80000004800 */
/*03d0*/ LDS R11, [R10.X4+-0x4] ; /* 0xfffffc000a0b7984 */
/* 0x000e280000004800 */
/*03e0*/ STS [R8.X4+-0x4], R11 ; /* 0xfffffc0b08007388 */
/* 0x001fe80000004800 */
/*03f0*/ LDS R12, [R10.X4+-0x4] ; /* 0xfffffc000a0c7984 */
/* 0x000e240000004800 */
/*0400*/ SEL R12, R12, RZ, P2 ; /* 0x000000ff0c0c7207 */
/* 0x001fca0001000000 */
/*0410*/ IMAD.IADD R9, R9, 0x1, R12 ; /* 0x0000000109097824 */
/* 0x000fca00078e020c */
/*0420*/ STS [R10.X4+-0x4], R9 ; /* 0xfffffc090a007388 */
/* 0x0001e40000004800 */
/*0430*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0440*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe40008011604 */
/*0450*/ USHF.L.U32 UR5, UR5, 0x1, URZ ; /* 0x0000000105057899 */
/* 0x000fc8000800063f */
/*0460*/ ISETP.NE.AND P2, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf45270 */
/*0470*/ @P2 BRA 0x310 ; /* 0xfffffe9000002947 */
/* 0x000fea000383ffff */
/*0480*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0490*/ @!P0 LDS R9, [R6.X4] ; /* 0x0000000006098984 */
/* 0x001e280000004800 */
/*04a0*/ @!P0 STG.E [R2.64], R9 ; /* 0x0000000902008986 */
/* 0x0011e2000c101906 */
/*04b0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*04c0*/ LDS R7, [R7.X4] ; /* 0x0000000007077984 */
/* 0x000e680000004800 */
/*04d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x002fe2000c101906 */
/*04e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04f0*/ BRA 0x4f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10ScanKernelPiii
.globl _Z10ScanKernelPiii
.p2align 8
.type _Z10ScanKernelPiii,@function
_Z10ScanKernelPiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s2
v_lshl_add_u32 v3, s15, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v3, s7
v_cmp_gt_i32_e32 vcc_lo, s6, v1
s_and_saveexec_b32 s1, vcc_lo
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_co_u32 v6, s0, s4, v6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
global_load_b32 v4, v[6:7], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v2, s2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v2, s7
v_lshrrev_b32_e32 v2, 5, v0
v_add_lshl_u32 v2, v2, v0, 2
s_delay_alu instid0(VALU_DEP_3)
v_cmp_gt_i32_e64 s0, s6, v3
s_waitcnt vmcnt(0)
ds_store_b32 v2, v4
s_and_saveexec_b32 s3, s0
s_cbranch_execz .LBB0_4
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[3:4]
v_add_co_u32 v4, s1, s4, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s1, s5, v5, s1
global_load_b32 v5, v[4:5], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s3
v_add_nc_u32_e32 v4, s2, v0
s_cmp_eq_u32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v6, 5, v4
v_add_lshl_u32 v4, v6, v4, 2
s_waitcnt vmcnt(0)
ds_store_b32 v4, v5
s_cbranch_scc1 .LBB0_13
v_lshl_or_b32 v5, v0, 1, 1
s_mov_b32 s3, 1
s_mov_b32 s6, s2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_7
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s7
s_lshl_b32 s3, s3, 1
s_lshr_b32 s6, s6, 1
s_cmp_gt_i32 s3, s2
s_cbranch_scc1 .LBB0_9
.LBB0_7:
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s6, v0
s_cbranch_execz .LBB0_6
v_mad_u64_u32 v[6:7], null, s3, v5, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, s3, v6
v_ashrrev_i32_e32 v8, 5, v6
v_ashrrev_i32_e32 v9, 5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_lshl_u32 v6, v8, v6, 2
v_add_lshl_u32 v7, v9, v7, 2
ds_load_b32 v6, v6
ds_load_b32 v8, v7
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v6, v8, v6
ds_store_b32 v7, v6
s_branch .LBB0_6
.LBB0_9:
s_set_inst_prefetch_distance 0x2
v_lshl_or_b32 v5, v0, 1, 1
v_cmp_eq_u32_e64 s3, 0, v0
s_mov_b32 s6, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_11
.p2align 6
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s7
s_lshr_b32 s1, s2, 1
s_lshl_b32 s6, s6, 1
s_cmp_lt_u32 s2, 2
s_mov_b32 s2, s1
s_cbranch_scc1 .LBB0_13
.LBB0_11:
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e64 s6, v0
s_cbranch_execz .LBB0_10
v_mad_u32_u24 v6, s2, v5, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, s2, v6
v_ashrrev_i32_e32 v9, 5, v6
v_ashrrev_i32_e32 v8, 5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_lshl_u32 v6, v9, v6, 2
v_add_lshl_u32 v7, v8, v7, 2
ds_load_b32 v9, v6
ds_load_b32 v8, v7
s_waitcnt lgkmcnt(0)
ds_store_b32 v6, v8
ds_load_b32 v6, v7
s_waitcnt lgkmcnt(0)
v_cndmask_b32_e64 v6, v6, 0, s3
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v6, v6, v9
ds_store_b32 v7, v6
s_branch .LBB0_10
.LBB0_13:
s_set_inst_prefetch_distance 0x2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s1, vcc_lo
s_cbranch_execz .LBB0_15
ds_load_b32 v5, v2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v5, off
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
ds_load_b32 v2, v4
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10ScanKernelPiii
.amdhsa_group_segment_fixed_size 4228
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10ScanKernelPiii, .Lfunc_end0-_Z10ScanKernelPiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z19ReverseUpdateKernelPiii
.globl _Z19ReverseUpdateKernelPiii
.p2align 8
.type _Z19ReverseUpdateKernelPiii,@function
_Z19ReverseUpdateKernelPiii:
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB1_5
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s0, s2, s15
s_lshl_b32 s3, s0, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s0, s3, s7
v_add_nc_u32_e32 v3, s3, v0
s_ashr_i32 s1, s0, 31
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_mul_lo_u32 v1, v3, s7
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
s_load_b32 s1, s[0:1], 0x0
v_cmp_ne_u32_e64 s0, 0, v0
v_cmp_gt_i32_e32 vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s0, vcc_lo
s_and_saveexec_b32 s0, s3
s_cbranch_execz .LBB1_3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v2, s1, v2
global_store_b32 v[0:1], v2, off
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v0, s2, v3
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s7
v_cmpx_gt_i32_e64 s6, v0
s_cbranch_execz .LBB1_5
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v2, s1, v2
global_store_b32 v[0:1], v2, off
.LBB1_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19ReverseUpdateKernelPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z19ReverseUpdateKernelPiii, .Lfunc_end1-_Z19ReverseUpdateKernelPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4228
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10ScanKernelPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10ScanKernelPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19ReverseUpdateKernelPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19ReverseUpdateKernelPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00006154_00000000-6_lcsExclusiveScanForInt.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10ScanKernelPiiiPiii
.type _Z32__device_stub__Z10ScanKernelPiiiPiii, @function
_Z32__device_stub__Z10ScanKernelPiiiPiii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10ScanKernelPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z10ScanKernelPiiiPiii, .-_Z32__device_stub__Z10ScanKernelPiiiPiii
.globl _Z10ScanKernelPiii
.type _Z10ScanKernelPiii, @function
_Z10ScanKernelPiii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10ScanKernelPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10ScanKernelPiii, .-_Z10ScanKernelPiii
.globl _Z41__device_stub__Z19ReverseUpdateKernelPiiiPiii
.type _Z41__device_stub__Z19ReverseUpdateKernelPiiiPiii, @function
_Z41__device_stub__Z19ReverseUpdateKernelPiiiPiii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z19ReverseUpdateKernelPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z41__device_stub__Z19ReverseUpdateKernelPiiiPiii, .-_Z41__device_stub__Z19ReverseUpdateKernelPiiiPiii
.globl _Z19ReverseUpdateKernelPiii
.type _Z19ReverseUpdateKernelPiii, @function
_Z19ReverseUpdateKernelPiii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z19ReverseUpdateKernelPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z19ReverseUpdateKernelPiii, .-_Z19ReverseUpdateKernelPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Fail to finish scan kernel"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Fail to finish reverse update kernel"
.text
.globl ExclusiveScanForInt
.type ExclusiveScanForInt, @function
ExclusiveScanForInt:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r15
movl %esi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $512, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %esi, %ebx
movl $0, %ebp
movl $1, %r12d
leaq _ZZ19ExclusiveScanForIntE7records(%rip), %r14
jmp .L20
.L22:
call cudaDeviceSynchronize@PLT
movl %eax, %r13d
addq $1, %rbp
testl %eax, %eax
jne .L34
.L20:
cmpl $1, %ebx
jle .L35
movl %r12d, %eax
sall $10, %eax
testl %ebp, %ebp
cmovne %eax, %r12d
movl %ebx, (%r14,%rbp,4)
leal 1022(%rbx), %eax
subl $1, %ebx
cmovs %eax, %ebx
sarl $10, %ebx
addl $1, %ebx
movl %ebx, 44(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L22
movl %r12d, %edx
movl 12(%rsp), %esi
movq %r15, %rdi
call _Z32__device_stub__Z10ScanKernelPiiiPiii
jmp .L22
.L34:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movl $0, %edi
call exit@PLT
.L35:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq %r15, %rsi
call cudaMemcpy@PLT
testl %eax, %eax
je .L24
movl %eax, %edi
call cudaGetErrorString@PLT
movl $0, %edi
call exit@PLT
.L24:
movl $4, %edx
movl $0, %esi
movq %r15, %rdi
call cudaMemset@PLT
testl %eax, %eax
jne .L36
testl %ebp, %ebp
jle .L26
movslq %ebp, %rax
leaq _ZZ19ExclusiveScanForIntE7records(%rip), %rdx
leaq (%rdx,%rax,4), %rbx
leal -1(%rbp), %edx
subq %rdx, %rax
leaq -4+_ZZ19ExclusiveScanForIntE7records(%rip), %rdx
leaq (%rdx,%rax,4), %rbp
jmp .L29
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movl $0, %edi
call exit@PLT
.L27:
call cudaDeviceSynchronize@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L37
leal 1023(%r12), %eax
testl %r12d, %r12d
cmovns %r12d, %eax
sarl $10, %eax
movl %eax, %r12d
subq $4, %rbx
cmpq %rbp, %rbx
je .L26
.L29:
movl -4(%rbx), %edx
leal 1022(%rdx), %eax
subl $1, %edx
cmovns %edx, %eax
sarl $10, %eax
addl $1, %eax
movl %eax, 44(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L27
movl %r12d, %edx
movl 12(%rsp), %esi
movq %r15, %rdi
call _Z41__device_stub__Z19ReverseUpdateKernelPiiiPiii
jmp .L27
.L37:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movl $0, %edi
call exit@PLT
.L26:
movl 28(%rsp), %eax
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L38
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size ExclusiveScanForInt, .-ExclusiveScanForInt
.section .rodata.str1.1
.LC2:
.string "_Z19ReverseUpdateKernelPiii"
.LC3:
.string "_Z10ScanKernelPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z19ReverseUpdateKernelPiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10ScanKernelPiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZ19ExclusiveScanForIntE7records
.comm _ZZ19ExclusiveScanForIntE7records,40,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lcsExclusiveScanForInt.hip"
.globl _Z25__device_stub__ScanKernelPiii # -- Begin function _Z25__device_stub__ScanKernelPiii
.p2align 4, 0x90
.type _Z25__device_stub__ScanKernelPiii,@function
_Z25__device_stub__ScanKernelPiii: # @_Z25__device_stub__ScanKernelPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10ScanKernelPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__ScanKernelPiii, .Lfunc_end0-_Z25__device_stub__ScanKernelPiii
.cfi_endproc
# -- End function
.globl _Z34__device_stub__ReverseUpdateKernelPiii # -- Begin function _Z34__device_stub__ReverseUpdateKernelPiii
.p2align 4, 0x90
.type _Z34__device_stub__ReverseUpdateKernelPiii,@function
_Z34__device_stub__ReverseUpdateKernelPiii: # @_Z34__device_stub__ReverseUpdateKernelPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z19ReverseUpdateKernelPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z34__device_stub__ReverseUpdateKernelPiii, .Lfunc_end1-_Z34__device_stub__ReverseUpdateKernelPiii
.cfi_endproc
# -- End function
.globl ExclusiveScanForInt # -- Begin function ExclusiveScanForInt
.p2align 4, 0x90
.type ExclusiveScanForInt,@function
ExclusiveScanForInt: # @ExclusiveScanForInt
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %r12
movabsq $4294967296, %rax # imm = 0x100000000
movl $1, %ebx
xorl %r13d, %r13d
leaq 512(%rax), %r15
movl %esi, 12(%rsp) # 4-byte Spill
movl %esi, %r14d
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_1 Depth=1
callq hipDeviceSynchronize
incq %r13
testl %eax, %eax
jne .LBB2_5
.LBB2_1: # =>This Inner Loop Header: Depth=1
cmpl $2, %r14d
jl .LBB2_7
# %bb.2: # in Loop: Header=BB2_1 Depth=1
movl %ebx, %eax
shll $10, %eax
testq %r13, %r13
cmovnel %eax, %ebx
movl %r14d, _ZZ19ExclusiveScanForIntE7records(,%r13,4)
decl %r14d
shrl $10, %r14d
incl %r14d
movq %r14, %rdi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3: # in Loop: Header=BB2_1 Depth=1
movq %r12, 64(%rsp)
movl 12(%rsp), %eax # 4-byte Reload
movl %eax, 8(%rsp)
movl %ebx, 4(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z10ScanKernelPiii, %edi
leaq 80(%rsp), %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_4
.LBB2_7:
leaq 76(%rsp), %rdi
movl $4, %edx
movq %r12, %r14
movq %r12, %rsi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_8
# %bb.10:
movl $4, %edx
movq %r14, %rdi
xorl %esi, %esi
callq hipMemset
testl %eax, %eax
jne .LBB2_8
# %bb.11: # %.preheader
testl %r13d, %r13d
je .LBB2_18
# %bb.12:
incq %r13
leaq 48(%rsp), %r12
.p2align 4, 0x90
.LBB2_13: # =>This Inner Loop Header: Depth=1
leal -2(%r13), %eax
movl _ZZ19ExclusiveScanForIntE7records(,%rax,4), %edi
leal -1(%rdi), %eax
addl $1022, %edi # imm = 0x3FE
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
incl %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_15
# %bb.14: # in Loop: Header=BB2_13 Depth=1
movq %r14, 64(%rsp)
movl 12(%rsp), %eax # 4-byte Reload
movl %eax, 8(%rsp)
movl %ebx, 4(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %r12, %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z19ReverseUpdateKernelPiii, %edi
leaq 80(%rsp), %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_15: # in Loop: Header=BB2_13 Depth=1
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_16
# %bb.17: # in Loop: Header=BB2_13 Depth=1
leal 1023(%rbx), %eax
testl %ebx, %ebx
cmovnsl %ebx, %eax
sarl $10, %eax
decq %r13
movl %eax, %ebx
cmpq $1, %r13
jg .LBB2_13
.LBB2_18: # %._crit_edge
movl 76(%rsp), %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_5:
.cfi_def_cfa_offset 160
movl %eax, %ebp
movl $.L.str, %edi
jmp .LBB2_6
.LBB2_16:
movl %eax, %ebp
movl $.L.str.1, %edi
.LBB2_6:
xorl %eax, %eax
callq printf
movl %ebp, %edi
.LBB2_9:
callq hipGetErrorString
xorl %edi, %edi
callq exit
.LBB2_8:
movl %eax, %edi
jmp .LBB2_9
.Lfunc_end2:
.size ExclusiveScanForInt, .Lfunc_end2-ExclusiveScanForInt
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10ScanKernelPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19ReverseUpdateKernelPiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10ScanKernelPiii,@object # @_Z10ScanKernelPiii
.section .rodata,"a",@progbits
.globl _Z10ScanKernelPiii
.p2align 3, 0x0
_Z10ScanKernelPiii:
.quad _Z25__device_stub__ScanKernelPiii
.size _Z10ScanKernelPiii, 8
.type _Z19ReverseUpdateKernelPiii,@object # @_Z19ReverseUpdateKernelPiii
.globl _Z19ReverseUpdateKernelPiii
.p2align 3, 0x0
_Z19ReverseUpdateKernelPiii:
.quad _Z34__device_stub__ReverseUpdateKernelPiii
.size _Z19ReverseUpdateKernelPiii, 8
.type _ZZ19ExclusiveScanForIntE7records,@object # @_ZZ19ExclusiveScanForIntE7records
.local _ZZ19ExclusiveScanForIntE7records
.comm _ZZ19ExclusiveScanForIntE7records,40,16
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Fail to finish scan kernel"
.size .L.str, 27
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Fail to finish reverse update kernel"
.size .L.str.1, 37
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10ScanKernelPiii"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z19ReverseUpdateKernelPiii"
.size .L__unnamed_2, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__ScanKernelPiii
.addrsig_sym _Z34__device_stub__ReverseUpdateKernelPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10ScanKernelPiii
.addrsig_sym _Z19ReverseUpdateKernelPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <math.h>
#include <stdio.h>
#include <cuda_runtime.h>
#define WARP_SIZE 32
#define MAX_THREADS_X 1024
#define MAX_THREADS_Y 1024
#define MAX_THREADS_Z 64
#define MAX_BLOCKS_X 2147483647
#define MAX_BLOCKS_Y 65535
#define MAX_BLOCKS_Z 65535
#define THREADS_PER_BLOCK 128
//3.0, 16 blocks, 2048 threads
//MIN THREADS_PER_BLOCK = 128
#define SIZE 1024
static inline void _safe_cuda_call(cudaError err, const char* msg, const char* file_name, const int line_number)
{
if (err != cudaSuccess)
{
fprintf(stderr, "%s\n\nFile: %s\n\nLine Number: %d\n\nReason: %s\n", msg, file_name, line_number, cudaGetErrorString(err));
//cin.get();
exit(EXIT_FAILURE);
}
}
#define SAFE_CALL(call,msg) _safe_cuda_call((call),(msg),__FILE__,__LINE__)
__global__ void scan(int *input, int n, int d, int size)
{
int i = blockIdx.x *blockDim.x + threadIdx.x;
//printf("i: %d\n", i);
//if(n == 1)
// input[i + (int)pow(2.0, (double)(d+1)) - 1] = 0;
//else
//if (i < n )
{
i*=pow(2.0, (double)d+1);
if(i + (int)pow(2.0, (double)(d+1)) - 1 < size)
{
input[i + (int)pow(2.0, (double)(d+1)) - 1] = input[i + (int)pow(2.0,(double)d) - 1] + input[i + (int)pow(2.0,(double)(d + 1)) - 1];
//printf("[%d(%d+%d-1)] = [%d] + [%d], SIZE=%d\n", i + (int)pow(2.0, (double)(d+1)) - 1, i,(int)pow(2.0, (double)(d+1)), i + (int)pow(2.0,(double)d) - 1,i + (int)pow(2.0,(double)(d + 1)) - 1, size);
}
}
}
__global__ void down_sweep(int *input, int n, int d, int size)
{
int i = blockIdx.x *blockDim.x + threadIdx.x;
//if (i < n)
{
i*=pow(2.0, (double)d+1);
if(i + (int)pow(2.0, (double)(d+1)) - 1 < size)
{
int temp = input[i + (int)pow(2.0, (double)d) - 1];
input[i + (int)pow(2.0, (double)d) -1] = input[i + (int)pow(2.0, (double)(d+1)) - 1];
input[i + (int)pow(2.0, (double)(d+1)) - 1] = temp + input[i + (int)pow(2.0, (double)(d+1)) - 1];
}
}
}
__global__ void quickfix(int *input, int size)
{
input[size-1] = 0;
}
int main()
{
int * input = (int *)malloc(SIZE * sizeof(int));// = {1,2,3,4,5,6,7,8,9};
for (int i = 0; i < SIZE; i++)
input[i] = i;
int *d_input;
int d = ceil(log2((float)SIZE));
SAFE_CALL(cudaMalloc<int>(&d_input, SIZE*sizeof(int)), "CUDA Malloc Failed");
SAFE_CALL(cudaMemcpy(d_input, input, SIZE*sizeof(int), cudaMemcpyHostToDevice ), "CUDA Memcpy Host To Device Failed");
for (int i = 0; i < d; i++)
{
//int numop = ceil(SIZE/2)
int numop = ceil(SIZE/pow(2, i+1));
int bloques = ceil((float)numop/THREADS_PER_BLOCK);
printf("numop: %d", numop);
scan<<<bloques,THREADS_PER_BLOCK>>>(d_input, numop, i, SIZE);
}
quickfix<<<1,1>>>(d_input, SIZE);
int numop2 = 1;
for (int i = d - 1; i >= 0; i--)
{
int bloques = ceil((float)numop2/THREADS_PER_BLOCK);
down_sweep<<<bloques,THREADS_PER_BLOCK>>>(d_input, numop2, i, SIZE);
numop2*=2;
}
SAFE_CALL(cudaMemcpy(input, d_input, SIZE*sizeof(int), cudaMemcpyDeviceToHost), "CUDA Memcpy Device To Host Failed");
SAFE_CALL(cudaFree(d_input), "CUDA Free Failed");
for(int i = 0; i < SIZE; i++)
{
printf("%d\n", input[i]);
}
free(input);
} | .file "tmpxft_000eed48_00000000-6_prefix.cudafe1.cpp"
.text
#APP
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "%s\n\nFile: %s\n\nLine Number: %d\n\nReason: %s\n"
#NO_APP
.text
.type _ZL15_safe_cuda_call9cudaErrorPKcS1_i, @function
_ZL15_safe_cuda_call9cudaErrorPKcS1_i:
.LFB2057:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %r12
movq %rdx, %rbx
movl %ecx, %ebp
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
movl %ebp, %r9d
movq %rbx, %r8
movq %r12, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _ZL15_safe_cuda_call9cudaErrorPKcS1_i, .-_ZL15_safe_cuda_call9cudaErrorPKcS1_i
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z4scanPiiiiPiiii
.type _Z26__device_stub__Z4scanPiiiiPiiii, @function
_Z26__device_stub__Z4scanPiiiiPiiii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4scanPiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z26__device_stub__Z4scanPiiiiPiiii, .-_Z26__device_stub__Z4scanPiiiiPiiii
.globl _Z4scanPiiii
.type _Z4scanPiiii, @function
_Z4scanPiiii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4scanPiiiiPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z4scanPiiii, .-_Z4scanPiiii
.globl _Z33__device_stub__Z10down_sweepPiiiiPiiii
.type _Z33__device_stub__Z10down_sweepPiiiiPiiii, @function
_Z33__device_stub__Z10down_sweepPiiiiPiiii:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10down_sweepPiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z33__device_stub__Z10down_sweepPiiiiPiiii, .-_Z33__device_stub__Z10down_sweepPiiiiPiiii
.globl _Z10down_sweepPiiii
.type _Z10down_sweepPiiii, @function
_Z10down_sweepPiiii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10down_sweepPiiiiPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z10down_sweepPiiii, .-_Z10down_sweepPiiii
.globl _Z28__device_stub__Z8quickfixPiiPii
.type _Z28__device_stub__Z8quickfixPiiPii, @function
_Z28__device_stub__Z8quickfixPiiPii:
.LFB2087:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8quickfixPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z28__device_stub__Z8quickfixPiiPii, .-_Z28__device_stub__Z8quickfixPiiPii
.globl _Z8quickfixPii
.type _Z8quickfixPii, @function
_Z8quickfixPii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z8quickfixPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z8quickfixPii, .-_Z8quickfixPii
.section .rodata.str1.8
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/rafacorrea/multinucleos/master/proyecto/etc/prefix.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "CUDA Malloc Failed"
.section .rodata.str1.8
.align 8
.LC3:
.string "CUDA Memcpy Host To Device Failed"
.section .rodata.str1.1
.LC13:
.string "numop: %d"
.section .rodata.str1.8
.align 8
.LC14:
.string "CUDA Memcpy Device To Host Failed"
.section .rodata.str1.1
.LC15:
.string "CUDA Free Failed"
.LC16:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4096, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
.L34:
movl %eax, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $1024, %rax
jne .L34
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $80, %ecx
leaq .LC1(%rip), %rbx
movq %rbx, %rdx
leaq .LC2(%rip), %rsi
call _ZL15_safe_cuda_call9cudaErrorPKcS1_i
movl $1, %ecx
movl $4096, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $81, %ecx
movq %rbx, %rdx
leaq .LC3(%rip), %rsi
call _ZL15_safe_cuda_call9cudaErrorPKcS1_i
movl $0, %ebx
jmp .L38
.L36:
movl %r13d, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $128, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
cvttss2sil 12(%rsp), %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L37:
cmpl $10, %ebx
je .L51
.L38:
movl %ebx, %r12d
addl $1, %ebx
pxor %xmm1, %xmm1
cvtsi2sdl %ebx, %xmm1
movsd .LC4(%rip), %xmm0
call pow@PLT
movsd .LC5(%rip), %xmm1
divsd %xmm0, %xmm1
movapd %xmm1, %xmm2
movsd .LC18(%rip), %xmm0
andpd %xmm1, %xmm0
movsd .LC6(%rip), %xmm3
ucomisd %xmm0, %xmm3
jbe .L35
cvttsd2siq %xmm1, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
cmpnlesd %xmm0, %xmm2
movsd .LC8(%rip), %xmm3
andpd %xmm3, %xmm2
addsd %xmm2, %xmm0
movsd .LC18(%rip), %xmm2
andnpd %xmm1, %xmm2
orpd %xmm0, %xmm2
.L35:
cvttsd2sil %xmm2, %r13d
pxor %xmm0, %xmm0
cvtsi2ssl %r13d, %xmm0
mulss .LC9(%rip), %xmm0
movss %xmm0, 12(%rsp)
movss .LC17(%rip), %xmm1
andps %xmm0, %xmm1
movss .LC10(%rip), %xmm2
ucomiss %xmm1, %xmm2
jbe .L36
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
movaps %xmm0, %xmm2
cmpnless %xmm1, %xmm2
movss .LC12(%rip), %xmm3
andps %xmm3, %xmm2
addss %xmm2, %xmm1
movss .LC17(%rip), %xmm2
andnps %xmm0, %xmm2
orps %xmm2, %xmm1
movss %xmm1, 12(%rsp)
jmp .L36
.L50:
movl $1024, %ecx
movl %r12d, %edx
movl %r13d, %esi
movq 24(%rsp), %rdi
call _Z26__device_stub__Z4scanPiiiiPiiii
jmp .L37
.L51:
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L39:
movl $9, %r12d
movl $1, %ebx
jmp .L42
.L52:
movl $1024, %esi
movq 24(%rsp), %rdi
call _Z28__device_stub__Z8quickfixPiiPii
jmp .L39
.L40:
movl $128, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
cvttss2sil %xmm2, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L41:
addl %ebx, %ebx
subl $1, %r12d
cmpl $-1, %r12d
je .L54
.L42:
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
mulss .LC9(%rip), %xmm0
movaps %xmm0, %xmm2
movss .LC17(%rip), %xmm1
andps %xmm0, %xmm1
movss .LC10(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L40
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm2
movss .LC12(%rip), %xmm5
andps %xmm5, %xmm2
addss %xmm2, %xmm1
movss .LC17(%rip), %xmm2
andnps %xmm0, %xmm2
orps %xmm1, %xmm2
jmp .L40
.L53:
movl $1024, %ecx
movl %r12d, %edx
movl %ebx, %esi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z10down_sweepPiiiiPiiii
jmp .L41
.L54:
movl $2, %ecx
movl $4096, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $100, %ecx
leaq .LC1(%rip), %rbx
movq %rbx, %rdx
leaq .LC14(%rip), %rsi
call _ZL15_safe_cuda_call9cudaErrorPKcS1_i
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $101, %ecx
movq %rbx, %rdx
leaq .LC15(%rip), %rsi
call _ZL15_safe_cuda_call9cudaErrorPKcS1_i
movq %rbp, %rbx
leaq 4096(%rbp), %r13
leaq .LC16(%rip), %r12
.L43:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L43
movq %rbp, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L55
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC19:
.string "_Z8quickfixPii"
.LC20:
.string "_Z10down_sweepPiiii"
.LC21:
.string "_Z4scanPiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z8quickfixPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z10down_sweepPiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z4scanPiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1073741824
.align 8
.LC5:
.long 0
.long 1083179008
.align 8
.LC6:
.long 0
.long 1127219200
.align 8
.LC8:
.long 0
.long 1072693248
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC9:
.long 1006632960
.align 4
.LC10:
.long 1258291200
.align 4
.LC12:
.long 1065353216
.set .LC17,.LC18+4
.section .rodata.cst8
.align 8
.LC18:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <math.h>
#include <stdio.h>
#include <cuda_runtime.h>
#define WARP_SIZE 32
#define MAX_THREADS_X 1024
#define MAX_THREADS_Y 1024
#define MAX_THREADS_Z 64
#define MAX_BLOCKS_X 2147483647
#define MAX_BLOCKS_Y 65535
#define MAX_BLOCKS_Z 65535
#define THREADS_PER_BLOCK 128
//3.0, 16 blocks, 2048 threads
//MIN THREADS_PER_BLOCK = 128
#define SIZE 1024
static inline void _safe_cuda_call(cudaError err, const char* msg, const char* file_name, const int line_number)
{
if (err != cudaSuccess)
{
fprintf(stderr, "%s\n\nFile: %s\n\nLine Number: %d\n\nReason: %s\n", msg, file_name, line_number, cudaGetErrorString(err));
//cin.get();
exit(EXIT_FAILURE);
}
}
#define SAFE_CALL(call,msg) _safe_cuda_call((call),(msg),__FILE__,__LINE__)
__global__ void scan(int *input, int n, int d, int size)
{
int i = blockIdx.x *blockDim.x + threadIdx.x;
//printf("i: %d\n", i);
//if(n == 1)
// input[i + (int)pow(2.0, (double)(d+1)) - 1] = 0;
//else
//if (i < n )
{
i*=pow(2.0, (double)d+1);
if(i + (int)pow(2.0, (double)(d+1)) - 1 < size)
{
input[i + (int)pow(2.0, (double)(d+1)) - 1] = input[i + (int)pow(2.0,(double)d) - 1] + input[i + (int)pow(2.0,(double)(d + 1)) - 1];
//printf("[%d(%d+%d-1)] = [%d] + [%d], SIZE=%d\n", i + (int)pow(2.0, (double)(d+1)) - 1, i,(int)pow(2.0, (double)(d+1)), i + (int)pow(2.0,(double)d) - 1,i + (int)pow(2.0,(double)(d + 1)) - 1, size);
}
}
}
__global__ void down_sweep(int *input, int n, int d, int size)
{
int i = blockIdx.x *blockDim.x + threadIdx.x;
//if (i < n)
{
i*=pow(2.0, (double)d+1);
if(i + (int)pow(2.0, (double)(d+1)) - 1 < size)
{
int temp = input[i + (int)pow(2.0, (double)d) - 1];
input[i + (int)pow(2.0, (double)d) -1] = input[i + (int)pow(2.0, (double)(d+1)) - 1];
input[i + (int)pow(2.0, (double)(d+1)) - 1] = temp + input[i + (int)pow(2.0, (double)(d+1)) - 1];
}
}
}
__global__ void quickfix(int *input, int size)
{
input[size-1] = 0;
}
int main()
{
int * input = (int *)malloc(SIZE * sizeof(int));// = {1,2,3,4,5,6,7,8,9};
for (int i = 0; i < SIZE; i++)
input[i] = i;
int *d_input;
int d = ceil(log2((float)SIZE));
SAFE_CALL(cudaMalloc<int>(&d_input, SIZE*sizeof(int)), "CUDA Malloc Failed");
SAFE_CALL(cudaMemcpy(d_input, input, SIZE*sizeof(int), cudaMemcpyHostToDevice ), "CUDA Memcpy Host To Device Failed");
for (int i = 0; i < d; i++)
{
//int numop = ceil(SIZE/2)
int numop = ceil(SIZE/pow(2, i+1));
int bloques = ceil((float)numop/THREADS_PER_BLOCK);
printf("numop: %d", numop);
scan<<<bloques,THREADS_PER_BLOCK>>>(d_input, numop, i, SIZE);
}
quickfix<<<1,1>>>(d_input, SIZE);
int numop2 = 1;
for (int i = d - 1; i >= 0; i--)
{
int bloques = ceil((float)numop2/THREADS_PER_BLOCK);
down_sweep<<<bloques,THREADS_PER_BLOCK>>>(d_input, numop2, i, SIZE);
numop2*=2;
}
SAFE_CALL(cudaMemcpy(input, d_input, SIZE*sizeof(int), cudaMemcpyDeviceToHost), "CUDA Memcpy Device To Host Failed");
SAFE_CALL(cudaFree(d_input), "CUDA Free Failed");
for(int i = 0; i < SIZE; i++)
{
printf("%d\n", input[i]);
}
free(input);
} | #include <math.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#define WARP_SIZE 32
#define MAX_THREADS_X 1024
#define MAX_THREADS_Y 1024
#define MAX_THREADS_Z 64
#define MAX_BLOCKS_X 2147483647
#define MAX_BLOCKS_Y 65535
#define MAX_BLOCKS_Z 65535
#define THREADS_PER_BLOCK 128
//3.0, 16 blocks, 2048 threads
//MIN THREADS_PER_BLOCK = 128
#define SIZE 1024
static inline void _safe_cuda_call(hipError_t err, const char* msg, const char* file_name, const int line_number)
{
if (err != hipSuccess)
{
fprintf(stderr, "%s\n\nFile: %s\n\nLine Number: %d\n\nReason: %s\n", msg, file_name, line_number, hipGetErrorString(err));
//cin.get();
exit(EXIT_FAILURE);
}
}
#define SAFE_CALL(call,msg) _safe_cuda_call((call),(msg),__FILE__,__LINE__)
__global__ void scan(int *input, int n, int d, int size)
{
int i = blockIdx.x *blockDim.x + threadIdx.x;
//printf("i: %d\n", i);
//if(n == 1)
// input[i + (int)pow(2.0, (double)(d+1)) - 1] = 0;
//else
//if (i < n )
{
i*=pow(2.0, (double)d+1);
if(i + (int)pow(2.0, (double)(d+1)) - 1 < size)
{
input[i + (int)pow(2.0, (double)(d+1)) - 1] = input[i + (int)pow(2.0,(double)d) - 1] + input[i + (int)pow(2.0,(double)(d + 1)) - 1];
//printf("[%d(%d+%d-1)] = [%d] + [%d], SIZE=%d\n", i + (int)pow(2.0, (double)(d+1)) - 1, i,(int)pow(2.0, (double)(d+1)), i + (int)pow(2.0,(double)d) - 1,i + (int)pow(2.0,(double)(d + 1)) - 1, size);
}
}
}
__global__ void down_sweep(int *input, int n, int d, int size)
{
int i = blockIdx.x *blockDim.x + threadIdx.x;
//if (i < n)
{
i*=pow(2.0, (double)d+1);
if(i + (int)pow(2.0, (double)(d+1)) - 1 < size)
{
int temp = input[i + (int)pow(2.0, (double)d) - 1];
input[i + (int)pow(2.0, (double)d) -1] = input[i + (int)pow(2.0, (double)(d+1)) - 1];
input[i + (int)pow(2.0, (double)(d+1)) - 1] = temp + input[i + (int)pow(2.0, (double)(d+1)) - 1];
}
}
}
__global__ void quickfix(int *input, int size)
{
input[size-1] = 0;
}
int main()
{
int * input = (int *)malloc(SIZE * sizeof(int));// = {1,2,3,4,5,6,7,8,9};
for (int i = 0; i < SIZE; i++)
input[i] = i;
int *d_input;
int d = ceil(log2((float)SIZE));
SAFE_CALL(hipMalloc<int>(&d_input, SIZE*sizeof(int)), "CUDA Malloc Failed");
SAFE_CALL(hipMemcpy(d_input, input, SIZE*sizeof(int), hipMemcpyHostToDevice ), "CUDA Memcpy Host To Device Failed");
for (int i = 0; i < d; i++)
{
//int numop = ceil(SIZE/2)
int numop = ceil(SIZE/pow(2, i+1));
int bloques = ceil((float)numop/THREADS_PER_BLOCK);
printf("numop: %d", numop);
scan<<<bloques,THREADS_PER_BLOCK>>>(d_input, numop, i, SIZE);
}
quickfix<<<1,1>>>(d_input, SIZE);
int numop2 = 1;
for (int i = d - 1; i >= 0; i--)
{
int bloques = ceil((float)numop2/THREADS_PER_BLOCK);
down_sweep<<<bloques,THREADS_PER_BLOCK>>>(d_input, numop2, i, SIZE);
numop2*=2;
}
SAFE_CALL(hipMemcpy(input, d_input, SIZE*sizeof(int), hipMemcpyDeviceToHost), "CUDA Memcpy Device To Host Failed");
SAFE_CALL(hipFree(d_input), "CUDA Free Failed");
for(int i = 0; i < SIZE; i++)
{
printf("%d\n", input[i]);
}
free(input);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <math.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#define WARP_SIZE 32
#define MAX_THREADS_X 1024
#define MAX_THREADS_Y 1024
#define MAX_THREADS_Z 64
#define MAX_BLOCKS_X 2147483647
#define MAX_BLOCKS_Y 65535
#define MAX_BLOCKS_Z 65535
#define THREADS_PER_BLOCK 128
//3.0, 16 blocks, 2048 threads
//MIN THREADS_PER_BLOCK = 128
#define SIZE 1024
static inline void _safe_cuda_call(hipError_t err, const char* msg, const char* file_name, const int line_number)
{
if (err != hipSuccess)
{
fprintf(stderr, "%s\n\nFile: %s\n\nLine Number: %d\n\nReason: %s\n", msg, file_name, line_number, hipGetErrorString(err));
//cin.get();
exit(EXIT_FAILURE);
}
}
#define SAFE_CALL(call,msg) _safe_cuda_call((call),(msg),__FILE__,__LINE__)
__global__ void scan(int *input, int n, int d, int size)
{
int i = blockIdx.x *blockDim.x + threadIdx.x;
//printf("i: %d\n", i);
//if(n == 1)
// input[i + (int)pow(2.0, (double)(d+1)) - 1] = 0;
//else
//if (i < n )
{
i*=pow(2.0, (double)d+1);
if(i + (int)pow(2.0, (double)(d+1)) - 1 < size)
{
input[i + (int)pow(2.0, (double)(d+1)) - 1] = input[i + (int)pow(2.0,(double)d) - 1] + input[i + (int)pow(2.0,(double)(d + 1)) - 1];
//printf("[%d(%d+%d-1)] = [%d] + [%d], SIZE=%d\n", i + (int)pow(2.0, (double)(d+1)) - 1, i,(int)pow(2.0, (double)(d+1)), i + (int)pow(2.0,(double)d) - 1,i + (int)pow(2.0,(double)(d + 1)) - 1, size);
}
}
}
__global__ void down_sweep(int *input, int n, int d, int size)
{
int i = blockIdx.x *blockDim.x + threadIdx.x;
//if (i < n)
{
i*=pow(2.0, (double)d+1);
if(i + (int)pow(2.0, (double)(d+1)) - 1 < size)
{
int temp = input[i + (int)pow(2.0, (double)d) - 1];
input[i + (int)pow(2.0, (double)d) -1] = input[i + (int)pow(2.0, (double)(d+1)) - 1];
input[i + (int)pow(2.0, (double)(d+1)) - 1] = temp + input[i + (int)pow(2.0, (double)(d+1)) - 1];
}
}
}
__global__ void quickfix(int *input, int size)
{
input[size-1] = 0;
}
int main()
{
int * input = (int *)malloc(SIZE * sizeof(int));// = {1,2,3,4,5,6,7,8,9};
for (int i = 0; i < SIZE; i++)
input[i] = i;
int *d_input;
int d = ceil(log2((float)SIZE));
SAFE_CALL(hipMalloc<int>(&d_input, SIZE*sizeof(int)), "CUDA Malloc Failed");
SAFE_CALL(hipMemcpy(d_input, input, SIZE*sizeof(int), hipMemcpyHostToDevice ), "CUDA Memcpy Host To Device Failed");
for (int i = 0; i < d; i++)
{
//int numop = ceil(SIZE/2)
int numop = ceil(SIZE/pow(2, i+1));
int bloques = ceil((float)numop/THREADS_PER_BLOCK);
printf("numop: %d", numop);
scan<<<bloques,THREADS_PER_BLOCK>>>(d_input, numop, i, SIZE);
}
quickfix<<<1,1>>>(d_input, SIZE);
int numop2 = 1;
for (int i = d - 1; i >= 0; i--)
{
int bloques = ceil((float)numop2/THREADS_PER_BLOCK);
down_sweep<<<bloques,THREADS_PER_BLOCK>>>(d_input, numop2, i, SIZE);
numop2*=2;
}
SAFE_CALL(hipMemcpy(input, d_input, SIZE*sizeof(int), hipMemcpyDeviceToHost), "CUDA Memcpy Device To Host Failed");
SAFE_CALL(hipFree(d_input), "CUDA Free Failed");
for(int i = 0; i < SIZE; i++)
{
printf("%d\n", input[i]);
}
free(input);
} | .text
.file "prefix.hip"
.globl _Z19__device_stub__scanPiiii # -- Begin function _Z19__device_stub__scanPiiii
.p2align 4, 0x90
.type _Z19__device_stub__scanPiiii,@function
_Z19__device_stub__scanPiiii: # @_Z19__device_stub__scanPiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4scanPiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__scanPiiii, .Lfunc_end0-_Z19__device_stub__scanPiiii
.cfi_endproc
# -- End function
.globl _Z25__device_stub__down_sweepPiiii # -- Begin function _Z25__device_stub__down_sweepPiiii
.p2align 4, 0x90
.type _Z25__device_stub__down_sweepPiiii,@function
_Z25__device_stub__down_sweepPiiii: # @_Z25__device_stub__down_sweepPiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10down_sweepPiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z25__device_stub__down_sweepPiiii, .Lfunc_end1-_Z25__device_stub__down_sweepPiiii
.cfi_endproc
# -- End function
.globl _Z23__device_stub__quickfixPii # -- Begin function _Z23__device_stub__quickfixPii
.p2align 4, 0x90
.type _Z23__device_stub__quickfixPii,@function
_Z23__device_stub__quickfixPii: # @_Z23__device_stub__quickfixPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8quickfixPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z23__device_stub__quickfixPii, .Lfunc_end2-_Z23__device_stub__quickfixPii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3ff0000000000000 # double 1
.LCPI3_1:
.quad 0x4090000000000000 # double 1024
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI3_2:
.long 0x3c000000 # float 0.0078125
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB3_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
testl %eax, %eax
jne .LBB3_3
# %bb.5: # %_ZL15_safe_cuda_call10hipError_tPKcS1_i.exit
movq 16(%rsp), %rdi
movl $1, %r15d
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_23
# %bb.6: # %_ZL15_safe_cuda_call10hipError_tPKcS1_i.exit47.preheader
movabsq $4294967296, %r13 # imm = 0x100000000
leaq 128(%r13), %r14
jmp .LBB3_7
.p2align 4, 0x90
.LBB3_9: # %_ZL15_safe_cuda_call10hipError_tPKcS1_i.exit47
# in Loop: Header=BB3_7 Depth=1
incl %r15d
cmpl $11, %r15d
je .LBB3_10
.LBB3_7: # =>This Inner Loop Header: Depth=1
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl %r15d, %edi
callq ldexp@PLT
movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movapd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %ebp
cvttpd2dq %xmm0, %xmm0
cvtdq2ps %xmm0, %xmm0
mulss .LCPI3_2(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %r12d
movl $.L.str.3, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
orq %r13, %r12
movq %r12, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_9
# %bb.8: # in Loop: Header=BB3_7 Depth=1
leal -1(%r15), %eax
movq 16(%rsp), %rcx
movq %rcx, 72(%rsp)
movl %ebp, 4(%rsp)
movl %eax, 12(%rsp)
movl $1024, 8(%rsp) # imm = 0x400
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z4scanPiiii, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_9
.LBB3_10:
leaq 1(%r13), %rdi
movl $1, %r12d
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_12
# %bb.11:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $1024, 4(%rsp) # imm = 0x400
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8quickfixPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_12:
movl $9, %ebp
leaq 80(%rsp), %r15
jmp .LBB3_13
.p2align 4, 0x90
.LBB3_15: # in Loop: Header=BB3_13 Depth=1
addl %r12d, %r12d
addl $-1, %ebp
jae .LBB3_16
.LBB3_13: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r12d, %xmm0
mulss .LCPI3_2(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %edi
orq %r13, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_15
# %bb.14: # in Loop: Header=BB3_13 Depth=1
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl %r12d, 4(%rsp)
movl %ebp, 12(%rsp)
movl $1024, 8(%rsp) # imm = 0x400
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z10down_sweepPiiii, %edi
movq %r15, %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_15
.LBB3_16:
movq 16(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_17
# %bb.18: # %_ZL15_safe_cuda_call10hipError_tPKcS1_i.exit55
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_22
# %bb.19: # %_ZL15_safe_cuda_call10hipError_tPKcS1_i.exit57.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_20: # %_ZL15_safe_cuda_call10hipError_tPKcS1_i.exit57
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $1024, %r14 # imm = 0x400
jne .LBB3_20
# %bb.21:
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_3:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str, %edx
movl $.L.str.1, %ecx
movq %rbx, %rdi
movl $80, %r8d
jmp .LBB3_4
.LBB3_23:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movl $.L.str.1, %ecx
movq %rbx, %rdi
movl $81, %r8d
jmp .LBB3_4
.LBB3_17:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.4, %edx
movl $.L.str.1, %ecx
movq %rbx, %rdi
movl $100, %r8d
jmp .LBB3_4
.LBB3_22:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.5, %edx
movl $.L.str.1, %ecx
movq %rbx, %rdi
movl $101, %r8d
.LBB3_4:
movq %rax, %r9
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4scanPiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10down_sweepPiiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8quickfixPii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4scanPiiii,@object # @_Z4scanPiiii
.section .rodata,"a",@progbits
.globl _Z4scanPiiii
.p2align 3, 0x0
_Z4scanPiiii:
.quad _Z19__device_stub__scanPiiii
.size _Z4scanPiiii, 8
.type _Z10down_sweepPiiii,@object # @_Z10down_sweepPiiii
.globl _Z10down_sweepPiiii
.p2align 3, 0x0
_Z10down_sweepPiiii:
.quad _Z25__device_stub__down_sweepPiiii
.size _Z10down_sweepPiiii, 8
.type _Z8quickfixPii,@object # @_Z8quickfixPii
.globl _Z8quickfixPii
.p2align 3, 0x0
_Z8quickfixPii:
.quad _Z23__device_stub__quickfixPii
.size _Z8quickfixPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA Malloc Failed"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/rafacorrea/multinucleos/master/proyecto/etc/prefix.hip"
.size .L.str.1, 112
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CUDA Memcpy Host To Device Failed"
.size .L.str.2, 34
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "numop: %d"
.size .L.str.3, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CUDA Memcpy Device To Host Failed"
.size .L.str.4, 34
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "CUDA Free Failed"
.size .L.str.5, 17
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d\n"
.size .L.str.6, 4
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%s\n\nFile: %s\n\nLine Number: %d\n\nReason: %s\n"
.size .L.str.7, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4scanPiiii"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10down_sweepPiiii"
.size .L__unnamed_2, 20
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z8quickfixPii"
.size .L__unnamed_3, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__scanPiiii
.addrsig_sym _Z25__device_stub__down_sweepPiiii
.addrsig_sym _Z23__device_stub__quickfixPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4scanPiiii
.addrsig_sym _Z10down_sweepPiiii
.addrsig_sym _Z8quickfixPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000eed48_00000000-6_prefix.cudafe1.cpp"
.text
#APP
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "%s\n\nFile: %s\n\nLine Number: %d\n\nReason: %s\n"
#NO_APP
.text
.type _ZL15_safe_cuda_call9cudaErrorPKcS1_i, @function
_ZL15_safe_cuda_call9cudaErrorPKcS1_i:
.LFB2057:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %r12
movq %rdx, %rbx
movl %ecx, %ebp
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
movl %ebp, %r9d
movq %rbx, %r8
movq %r12, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _ZL15_safe_cuda_call9cudaErrorPKcS1_i, .-_ZL15_safe_cuda_call9cudaErrorPKcS1_i
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z4scanPiiiiPiiii
.type _Z26__device_stub__Z4scanPiiiiPiiii, @function
_Z26__device_stub__Z4scanPiiiiPiiii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4scanPiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z26__device_stub__Z4scanPiiiiPiiii, .-_Z26__device_stub__Z4scanPiiiiPiiii
.globl _Z4scanPiiii
.type _Z4scanPiiii, @function
_Z4scanPiiii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4scanPiiiiPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z4scanPiiii, .-_Z4scanPiiii
.globl _Z33__device_stub__Z10down_sweepPiiiiPiiii
.type _Z33__device_stub__Z10down_sweepPiiiiPiiii, @function
_Z33__device_stub__Z10down_sweepPiiiiPiiii:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10down_sweepPiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z33__device_stub__Z10down_sweepPiiiiPiiii, .-_Z33__device_stub__Z10down_sweepPiiiiPiiii
.globl _Z10down_sweepPiiii
.type _Z10down_sweepPiiii, @function
_Z10down_sweepPiiii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10down_sweepPiiiiPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z10down_sweepPiiii, .-_Z10down_sweepPiiii
.globl _Z28__device_stub__Z8quickfixPiiPii
.type _Z28__device_stub__Z8quickfixPiiPii, @function
_Z28__device_stub__Z8quickfixPiiPii:
.LFB2087:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8quickfixPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z28__device_stub__Z8quickfixPiiPii, .-_Z28__device_stub__Z8quickfixPiiPii
.globl _Z8quickfixPii
.type _Z8quickfixPii, @function
_Z8quickfixPii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z8quickfixPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z8quickfixPii, .-_Z8quickfixPii
.section .rodata.str1.8
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/rafacorrea/multinucleos/master/proyecto/etc/prefix.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "CUDA Malloc Failed"
.section .rodata.str1.8
.align 8
.LC3:
.string "CUDA Memcpy Host To Device Failed"
.section .rodata.str1.1
.LC13:
.string "numop: %d"
.section .rodata.str1.8
.align 8
.LC14:
.string "CUDA Memcpy Device To Host Failed"
.section .rodata.str1.1
.LC15:
.string "CUDA Free Failed"
.LC16:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4096, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
.L34:
movl %eax, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $1024, %rax
jne .L34
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $80, %ecx
leaq .LC1(%rip), %rbx
movq %rbx, %rdx
leaq .LC2(%rip), %rsi
call _ZL15_safe_cuda_call9cudaErrorPKcS1_i
movl $1, %ecx
movl $4096, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $81, %ecx
movq %rbx, %rdx
leaq .LC3(%rip), %rsi
call _ZL15_safe_cuda_call9cudaErrorPKcS1_i
movl $0, %ebx
jmp .L38
.L36:
movl %r13d, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $128, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
cvttss2sil 12(%rsp), %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L37:
cmpl $10, %ebx
je .L51
.L38:
movl %ebx, %r12d
addl $1, %ebx
pxor %xmm1, %xmm1
cvtsi2sdl %ebx, %xmm1
movsd .LC4(%rip), %xmm0
call pow@PLT
movsd .LC5(%rip), %xmm1
divsd %xmm0, %xmm1
movapd %xmm1, %xmm2
movsd .LC18(%rip), %xmm0
andpd %xmm1, %xmm0
movsd .LC6(%rip), %xmm3
ucomisd %xmm0, %xmm3
jbe .L35
cvttsd2siq %xmm1, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
cmpnlesd %xmm0, %xmm2
movsd .LC8(%rip), %xmm3
andpd %xmm3, %xmm2
addsd %xmm2, %xmm0
movsd .LC18(%rip), %xmm2
andnpd %xmm1, %xmm2
orpd %xmm0, %xmm2
.L35:
cvttsd2sil %xmm2, %r13d
pxor %xmm0, %xmm0
cvtsi2ssl %r13d, %xmm0
mulss .LC9(%rip), %xmm0
movss %xmm0, 12(%rsp)
movss .LC17(%rip), %xmm1
andps %xmm0, %xmm1
movss .LC10(%rip), %xmm2
ucomiss %xmm1, %xmm2
jbe .L36
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
movaps %xmm0, %xmm2
cmpnless %xmm1, %xmm2
movss .LC12(%rip), %xmm3
andps %xmm3, %xmm2
addss %xmm2, %xmm1
movss .LC17(%rip), %xmm2
andnps %xmm0, %xmm2
orps %xmm2, %xmm1
movss %xmm1, 12(%rsp)
jmp .L36
.L50:
movl $1024, %ecx
movl %r12d, %edx
movl %r13d, %esi
movq 24(%rsp), %rdi
call _Z26__device_stub__Z4scanPiiiiPiiii
jmp .L37
.L51:
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L39:
movl $9, %r12d
movl $1, %ebx
jmp .L42
.L52:
movl $1024, %esi
movq 24(%rsp), %rdi
call _Z28__device_stub__Z8quickfixPiiPii
jmp .L39
.L40:
movl $128, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
cvttss2sil %xmm2, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L41:
addl %ebx, %ebx
subl $1, %r12d
cmpl $-1, %r12d
je .L54
.L42:
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
mulss .LC9(%rip), %xmm0
movaps %xmm0, %xmm2
movss .LC17(%rip), %xmm1
andps %xmm0, %xmm1
movss .LC10(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L40
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm2
movss .LC12(%rip), %xmm5
andps %xmm5, %xmm2
addss %xmm2, %xmm1
movss .LC17(%rip), %xmm2
andnps %xmm0, %xmm2
orps %xmm1, %xmm2
jmp .L40
.L53:
movl $1024, %ecx
movl %r12d, %edx
movl %ebx, %esi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z10down_sweepPiiiiPiiii
jmp .L41
.L54:
movl $2, %ecx
movl $4096, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $100, %ecx
leaq .LC1(%rip), %rbx
movq %rbx, %rdx
leaq .LC14(%rip), %rsi
call _ZL15_safe_cuda_call9cudaErrorPKcS1_i
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $101, %ecx
movq %rbx, %rdx
leaq .LC15(%rip), %rsi
call _ZL15_safe_cuda_call9cudaErrorPKcS1_i
movq %rbp, %rbx
leaq 4096(%rbp), %r13
leaq .LC16(%rip), %r12
.L43:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L43
movq %rbp, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L55
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC19:
.string "_Z8quickfixPii"
.LC20:
.string "_Z10down_sweepPiiii"
.LC21:
.string "_Z4scanPiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z8quickfixPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z10down_sweepPiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z4scanPiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1073741824
.align 8
.LC5:
.long 0
.long 1083179008
.align 8
.LC6:
.long 0
.long 1127219200
.align 8
.LC8:
.long 0
.long 1072693248
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC9:
.long 1006632960
.align 4
.LC10:
.long 1258291200
.align 4
.LC12:
.long 1065353216
.set .LC17,.LC18+4
.section .rodata.cst8
.align 8
.LC18:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "prefix.hip"
.globl _Z19__device_stub__scanPiiii # -- Begin function _Z19__device_stub__scanPiiii
.p2align 4, 0x90
.type _Z19__device_stub__scanPiiii,@function
_Z19__device_stub__scanPiiii: # @_Z19__device_stub__scanPiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4scanPiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__scanPiiii, .Lfunc_end0-_Z19__device_stub__scanPiiii
.cfi_endproc
# -- End function
.globl _Z25__device_stub__down_sweepPiiii # -- Begin function _Z25__device_stub__down_sweepPiiii
.p2align 4, 0x90
.type _Z25__device_stub__down_sweepPiiii,@function
_Z25__device_stub__down_sweepPiiii: # @_Z25__device_stub__down_sweepPiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10down_sweepPiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z25__device_stub__down_sweepPiiii, .Lfunc_end1-_Z25__device_stub__down_sweepPiiii
.cfi_endproc
# -- End function
.globl _Z23__device_stub__quickfixPii # -- Begin function _Z23__device_stub__quickfixPii
.p2align 4, 0x90
.type _Z23__device_stub__quickfixPii,@function
_Z23__device_stub__quickfixPii: # @_Z23__device_stub__quickfixPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8quickfixPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z23__device_stub__quickfixPii, .Lfunc_end2-_Z23__device_stub__quickfixPii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3ff0000000000000 # double 1
.LCPI3_1:
.quad 0x4090000000000000 # double 1024
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI3_2:
.long 0x3c000000 # float 0.0078125
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB3_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
testl %eax, %eax
jne .LBB3_3
# %bb.5: # %_ZL15_safe_cuda_call10hipError_tPKcS1_i.exit
movq 16(%rsp), %rdi
movl $1, %r15d
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_23
# %bb.6: # %_ZL15_safe_cuda_call10hipError_tPKcS1_i.exit47.preheader
movabsq $4294967296, %r13 # imm = 0x100000000
leaq 128(%r13), %r14
jmp .LBB3_7
.p2align 4, 0x90
.LBB3_9: # %_ZL15_safe_cuda_call10hipError_tPKcS1_i.exit47
# in Loop: Header=BB3_7 Depth=1
incl %r15d
cmpl $11, %r15d
je .LBB3_10
.LBB3_7: # =>This Inner Loop Header: Depth=1
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl %r15d, %edi
callq ldexp@PLT
movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movapd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %ebp
cvttpd2dq %xmm0, %xmm0
cvtdq2ps %xmm0, %xmm0
mulss .LCPI3_2(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %r12d
movl $.L.str.3, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
orq %r13, %r12
movq %r12, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_9
# %bb.8: # in Loop: Header=BB3_7 Depth=1
leal -1(%r15), %eax
movq 16(%rsp), %rcx
movq %rcx, 72(%rsp)
movl %ebp, 4(%rsp)
movl %eax, 12(%rsp)
movl $1024, 8(%rsp) # imm = 0x400
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z4scanPiiii, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_9
.LBB3_10:
leaq 1(%r13), %rdi
movl $1, %r12d
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_12
# %bb.11:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $1024, 4(%rsp) # imm = 0x400
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8quickfixPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_12:
movl $9, %ebp
leaq 80(%rsp), %r15
jmp .LBB3_13
.p2align 4, 0x90
.LBB3_15: # in Loop: Header=BB3_13 Depth=1
addl %r12d, %r12d
addl $-1, %ebp
jae .LBB3_16
.LBB3_13: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r12d, %xmm0
mulss .LCPI3_2(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %edi
orq %r13, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_15
# %bb.14: # in Loop: Header=BB3_13 Depth=1
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl %r12d, 4(%rsp)
movl %ebp, 12(%rsp)
movl $1024, 8(%rsp) # imm = 0x400
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z10down_sweepPiiii, %edi
movq %r15, %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_15
.LBB3_16:
movq 16(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_17
# %bb.18: # %_ZL15_safe_cuda_call10hipError_tPKcS1_i.exit55
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_22
# %bb.19: # %_ZL15_safe_cuda_call10hipError_tPKcS1_i.exit57.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_20: # %_ZL15_safe_cuda_call10hipError_tPKcS1_i.exit57
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $1024, %r14 # imm = 0x400
jne .LBB3_20
# %bb.21:
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_3:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str, %edx
movl $.L.str.1, %ecx
movq %rbx, %rdi
movl $80, %r8d
jmp .LBB3_4
.LBB3_23:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movl $.L.str.1, %ecx
movq %rbx, %rdi
movl $81, %r8d
jmp .LBB3_4
.LBB3_17:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.4, %edx
movl $.L.str.1, %ecx
movq %rbx, %rdi
movl $100, %r8d
jmp .LBB3_4
.LBB3_22:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.5, %edx
movl $.L.str.1, %ecx
movq %rbx, %rdi
movl $101, %r8d
.LBB3_4:
movq %rax, %r9
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4scanPiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10down_sweepPiiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8quickfixPii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4scanPiiii,@object # @_Z4scanPiiii
.section .rodata,"a",@progbits
.globl _Z4scanPiiii
.p2align 3, 0x0
_Z4scanPiiii:
.quad _Z19__device_stub__scanPiiii
.size _Z4scanPiiii, 8
.type _Z10down_sweepPiiii,@object # @_Z10down_sweepPiiii
.globl _Z10down_sweepPiiii
.p2align 3, 0x0
_Z10down_sweepPiiii:
.quad _Z25__device_stub__down_sweepPiiii
.size _Z10down_sweepPiiii, 8
.type _Z8quickfixPii,@object # @_Z8quickfixPii
.globl _Z8quickfixPii
.p2align 3, 0x0
_Z8quickfixPii:
.quad _Z23__device_stub__quickfixPii
.size _Z8quickfixPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA Malloc Failed"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/rafacorrea/multinucleos/master/proyecto/etc/prefix.hip"
.size .L.str.1, 112
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CUDA Memcpy Host To Device Failed"
.size .L.str.2, 34
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "numop: %d"
.size .L.str.3, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CUDA Memcpy Device To Host Failed"
.size .L.str.4, 34
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "CUDA Free Failed"
.size .L.str.5, 17
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d\n"
.size .L.str.6, 4
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%s\n\nFile: %s\n\nLine Number: %d\n\nReason: %s\n"
.size .L.str.7, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4scanPiiii"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10down_sweepPiiii"
.size .L__unnamed_2, 20
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z8quickfixPii"
.size .L__unnamed_3, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__scanPiiii
.addrsig_sym _Z25__device_stub__down_sweepPiiii
.addrsig_sym _Z23__device_stub__quickfixPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4scanPiiii
.addrsig_sym _Z10down_sweepPiiii
.addrsig_sym _Z8quickfixPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <fstream>
#include <chrono>
__global__
void sumOne(int n,int *m,int *partialSum,int *sum){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
int threadSum =0;
for (int i = index; i < n; i += stride){
if(m[i]==1){
threadSum++;
}
}
// Block Sum
atomicAdd(&partialSum[blockIdx.x],threadSum);
__syncthreads();
if(threadIdx.x==0){
// Global Sum;
atomicAdd(&sum[0],partialSum[blockIdx.x]);
}
}
int main(int argc,char **argv){
//Read input matrix
std::ifstream infile;
infile.open(argv[1]);
if (!infile.is_open()){
std::cerr << "Couldn't read " << argv[1] << std::endl;
return 0;
}
int w,h;
infile >> w >> h;
int N = w*h;
int *m;
//Unified memory allocation
cudaMallocManaged(&m, N*sizeof(int));
for(int i=0;i<N;i++){
infile >> m[i];
}
infile.close();
auto start = std::chrono::system_clock::now();
//Block,Grid parameters
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
int *partialSum;
int *sum;
cudaMallocManaged(&partialSum,numBlocks*sizeof(int));
cudaMallocManaged(&sum, sizeof(int));
//prefetch input matrix
int device = -1;
cudaGetDevice(&device);
cudaMemPrefetchAsync(m, N*sizeof(int), device, NULL);
cudaMemPrefetchAsync(partialSum, numBlocks*sizeof(int), device, NULL);
cudaMemPrefetchAsync(sum, sizeof(int), device, NULL);
//Sum ones
sumOne<<<numBlocks, blockSize>>>(N, m, partialSum,sum);
cudaDeviceSynchronize();
std::cout << sum[0] << std::endl;
cudaFree(m);
cudaFree(partialSum);
cudaFree(sum);
return 0;
} | code for sm_80
Function : _Z6sumOneiPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B2, 0xed0 ; /* 0x00000e9000027945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R7, R0, c[0x0][0x0], R3 ; /* 0x0000000000077a24 */
/* 0x001fca00078e0203 */
/*0070*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x160], PT ; /* 0x0000580007007a0c */
/* 0x000fda0003f06270 */
/*0080*/ @P0 BRA 0xec0 ; /* 0x00000e3000000947 */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff047624 */
/* 0x000fe200078e00ff */
/*00a0*/ BSSY B1, 0xdf0 ; /* 0x00000d4000017945 */
/* 0x000fe60003800000 */
/*00b0*/ IMAD R4, R4, c[0x0][0xc], RZ ; /* 0x0000030004047a24 */
/* 0x000fc800078e02ff */
/*00c0*/ I2F.U32.RP R6, R4 ; /* 0x0000000400067306 */
/* 0x000e220000209000 */
/*00d0*/ IMAD.MOV R11, RZ, RZ, -R4 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a04 */
/*00e0*/ ISETP.NE.U32.AND P2, PT, R4.reuse, RZ, PT ; /* 0x000000ff0400720c */
/* 0x040fe20003f45070 */
/*00f0*/ IMAD.IADD R2, R4, 0x1, R7 ; /* 0x0000000104027824 */
/* 0x000fca00078e0207 */
/*0100*/ LOP3.LUT R5, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff057212 */
/* 0x000fc800078e33ff */
/*0110*/ IADD3 R5, R5, c[0x0][0x160], R4 ; /* 0x0000580005057a10 */
/* 0x000fe20007ffe004 */
/*0120*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0130*/ IADD3 R8, R6, 0xffffffe, RZ ; /* 0x0ffffffe06087810 */
/* 0x001fcc0007ffe0ff */
/*0140*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000064000021f000 */
/*0150*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fe400078e00ff */
/*0160*/ IMAD R11, R11, R9, RZ ; /* 0x000000090b0b7224 */
/* 0x002fc800078e02ff */
/*0170*/ IMAD.HI.U32 R2, R9, R11, R8 ; /* 0x0000000b09027227 */
/* 0x000fcc00078e0008 */
/*0180*/ IMAD.HI.U32 R2, R2, R5, RZ ; /* 0x0000000502027227 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.MOV R6, RZ, RZ, -R2 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a02 */
/*01a0*/ IMAD R5, R4, R6, R5 ; /* 0x0000000604057224 */
/* 0x000fca00078e0205 */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fda0003f06070 */
/*01c0*/ @P0 IMAD.IADD R5, R5, 0x1, -R4 ; /* 0x0000000105050824 */
/* 0x000fe200078e0a04 */
/*01d0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P1, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fda0003f26070 */
/*01f0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*0200*/ @!P2 LOP3.LUT R2, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff02a212 */
/* 0x000fc800078e33ff */
/*0210*/ ISETP.GE.U32.AND P0, PT, R2.reuse, 0x3, PT ; /* 0x000000030200780c */
/* 0x040fe40003f06070 */
/*0220*/ IADD3 R5, R2, 0x1, RZ ; /* 0x0000000102057810 */
/* 0x000fe20007ffe0ff */
/*0230*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fc600078e00ff */
/*0240*/ LOP3.LUT R6, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305067812 */
/* 0x000fce00078ec0ff */
/*0250*/ @!P0 BRA 0xde0 ; /* 0x00000b8000008947 */
/* 0x000fea0003800000 */
/*0260*/ IMAD.IADD R5, R5, 0x1, -R6 ; /* 0x0000000105057824 */
/* 0x000fe200078e0a06 */
/*0270*/ BSSY B0, 0xc40 ; /* 0x000009c000007945 */
/* 0x000fe20003800000 */
/*0280*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fc600078e00ff */
/*0290*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f04270 */
/*02a0*/ @!P0 BRA 0xc30 ; /* 0x0000098000008947 */
/* 0x000fea0003800000 */
/*02b0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe20003f24270 */
/*02c0*/ BSSY B3, 0x8d0 ; /* 0x0000060000037945 */
/* 0x000fe20003800000 */
/*02d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*02e0*/ @!P1 BRA 0x8c0 ; /* 0x000005d000009947 */
/* 0x000fea0003800000 */
/*02f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0300*/ IMAD.MOV.U32 R28, RZ, RZ, 0x4 ; /* 0x00000004ff1c7424 */
/* 0x000fc800078e00ff */
/*0310*/ IMAD.WIDE R12, R7, R28, c[0x0][0x168] ; /* 0x00005a00070c7625 */
/* 0x000fca00078e021c */
/*0320*/ LDG.E R8, [R12.64] ; /* 0x000000060c087981 */
/* 0x0000a2000c1e1900 */
/*0330*/ IMAD.WIDE R16, R4, 0x4, R12 ; /* 0x0000000404107825 */
/* 0x000fca00078e020c */
/*0340*/ LDG.E R9, [R16.64] ; /* 0x0000000610097981 */
/* 0x0002e2000c1e1900 */
/*0350*/ IMAD.WIDE R18, R4.reuse, 0x4, R16 ; /* 0x0000000404127825 */
/* 0x040fe200078e0210 */
/*0360*/ IADD3 R7, R4, R7, R4 ; /* 0x0000000704077210 */
/* 0x000fc80007ffe004 */
/*0370*/ LDG.E R10, [R18.64] ; /* 0x00000006120a7981 */
/* 0x000962000c1e1900 */
/*0380*/ IMAD.WIDE R20, R4.reuse, 0x4, R18 ; /* 0x0000000404147825 */
/* 0x040fe200078e0212 */
/*0390*/ IADD3 R27, R4, R7, R4 ; /* 0x00000007041b7210 */
/* 0x000fc80007ffe004 */
/*03a0*/ LDG.E R11, [R20.64] ; /* 0x00000006140b7981 */
/* 0x000162000c1e1900 */
/*03b0*/ IMAD.WIDE R22, R27, R28, c[0x0][0x168] ; /* 0x00005a001b167625 */
/* 0x000fca00078e021c */
/*03c0*/ LDG.E R7, [R22.64] ; /* 0x0000000616077981 */
/* 0x000162000c1e1900 */
/*03d0*/ IMAD.WIDE R14, R4, 0x4, R22 ; /* 0x00000004040e7825 */
/* 0x000fca00078e0216 */
/*03e0*/ LDG.E R25, [R14.64] ; /* 0x000000060e197981 */
/* 0x000162000c1e1900 */
/*03f0*/ IMAD.WIDE R16, R4.reuse, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x042fe200078e020e */
/*0400*/ IADD3 R27, R4, R27, R4 ; /* 0x0000001b041b7210 */
/* 0x000fc80007ffe004 */
/*0410*/ LDG.E R24, [R16.64] ; /* 0x0000000610187981 */
/* 0x000362000c1e1900 */
/*0420*/ IMAD.WIDE R18, R4.reuse, 0x4, R16 ; /* 0x0000000404127825 */
/* 0x050fe200078e0210 */
/*0430*/ IADD3 R29, R4, R27, R4 ; /* 0x0000001b041d7210 */
/* 0x000fc80007ffe004 */
/*0440*/ LDG.E R13, [R18.64] ; /* 0x00000006120d7981 */
/* 0x001122000c1e1900 */
/*0450*/ IMAD.WIDE R20, R29, R28, c[0x0][0x168] ; /* 0x00005a001d147625 */
/* 0x000fca00078e021c */
/*0460*/ LDG.E R12, [R20.64] ; /* 0x00000006140c7981 */
/* 0x000122000c1e1900 */
/*0470*/ IMAD.WIDE R22, R4, 0x4, R20 ; /* 0x0000000404167825 */
/* 0x000fca00078e0214 */
/*0480*/ LDG.E R26, [R22.64] ; /* 0x00000006161a7981 */
/* 0x000122000c1e1900 */
/*0490*/ IMAD.WIDE R14, R4.reuse, 0x4, R22 ; /* 0x00000004040e7825 */
/* 0x040fe200078e0216 */
/*04a0*/ IADD3 R29, R4, R29, R4 ; /* 0x0000001d041d7210 */
/* 0x000fc80007ffe004 */
/*04b0*/ LDG.E R27, [R14.64] ; /* 0x000000060e1b7981 */
/* 0x000122000c1e1900 */
/*04c0*/ IMAD.WIDE R16, R4.reuse, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x042fe200078e020e */
/*04d0*/ IADD3 R29, R4, R29, R4 ; /* 0x0000001d041d7210 */
/* 0x000fca0007ffe004 */
/*04e0*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000322000c1e1900 */
/*04f0*/ IMAD.WIDE R18, R29, R28, c[0x0][0x168] ; /* 0x00005a001d127625 */
/* 0x001fca00078e021c */
/*0500*/ LDG.E R28, [R18.64] ; /* 0x00000006121c7981 */
/* 0x000122000c1e1900 */
/*0510*/ IMAD.WIDE R20, R4, 0x4, R18 ; /* 0x0000000404147825 */
/* 0x000fca00078e0212 */
/*0520*/ LDG.E R17, [R20.64] ; /* 0x0000000614117981 */
/* 0x002f22000c1e1900 */
/*0530*/ IMAD.WIDE R22, R4, 0x4, R20 ; /* 0x0000000404167825 */
/* 0x000fca00078e0214 */
/*0540*/ LDG.E R18, [R22.64] ; /* 0x0000000616127981 */
/* 0x001f22000c1e1900 */
/*0550*/ IMAD.WIDE R14, R4, 0x4, R22 ; /* 0x00000004040e7825 */
/* 0x000fcc00078e0216 */
/*0560*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000f22000c1e1900 */
/*0570*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fe40007ffe0ff */
/*0580*/ ISETP.NE.AND P1, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x004fe40003f25270 */
/*0590*/ IADD3 R8, R2, 0x1, RZ ; /* 0x0000000102087810 */
/* 0x000fe40007ffe0ff */
/*05a0*/ ISETP.NE.AND P2, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x008fd20003f45270 */
/*05b0*/ @P1 IMAD.MOV R8, RZ, RZ, R2 ; /* 0x000000ffff081224 */
/* 0x000fe200078e0202 */
/*05c0*/ ISETP.NE.AND P1, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x020fc80003f25270 */
/*05d0*/ IADD3 R2, R8, 0x1, RZ ; /* 0x0000000108027810 */
/* 0x000fe20007ffe0ff */
/*05e0*/ @P2 IMAD.MOV R2, RZ, RZ, R8 ; /* 0x000000ffff022224 */
/* 0x000fe200078e0208 */
/*05f0*/ ISETP.NE.AND P2, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fc80003f45270 */
/*0600*/ IADD3 R8, R2, 0x1, RZ ; /* 0x0000000102087810 */
/* 0x000fc60007ffe0ff */
/*0610*/ @P1 IMAD.MOV R8, RZ, RZ, R2 ; /* 0x000000ffff081224 */
/* 0x000fe200078e0202 */
/*0620*/ ISETP.NE.AND P1, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fc80003f25270 */
/*0630*/ IADD3 R2, R8, 0x1, RZ ; /* 0x0000000108027810 */
/* 0x000fe20007ffe0ff */
/*0640*/ @P2 IMAD.MOV R2, RZ, RZ, R8 ; /* 0x000000ffff022224 */
/* 0x000fe200078e0208 */
/*0650*/ ISETP.NE.AND P2, PT, R25, 0x1, PT ; /* 0x000000011900780c */
/* 0x000fc80003f45270 */
/*0660*/ IADD3 R7, R2, 0x1, RZ ; /* 0x0000000102077810 */
/* 0x000fc60007ffe0ff */
/*0670*/ @P1 IMAD.MOV R7, RZ, RZ, R2 ; /* 0x000000ffff071224 */
/* 0x000fe200078e0202 */
/*0680*/ ISETP.NE.AND P1, PT, R24, 0x1, PT ; /* 0x000000011800780c */
/* 0x000fc80003f25270 */
/*0690*/ IADD3 R2, R7, 0x1, RZ ; /* 0x0000000107027810 */
/* 0x000fe20007ffe0ff */
/*06a0*/ @P2 IMAD.MOV R2, RZ, RZ, R7 ; /* 0x000000ffff022224 */
/* 0x000fe200078e0207 */
/*06b0*/ ISETP.NE.AND P2, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x010fc80003f45270 */
/*06c0*/ IADD3 R7, R2, 0x1, RZ ; /* 0x0000000102077810 */
/* 0x000fc60007ffe0ff */
/*06d0*/ @P1 IMAD.MOV R7, RZ, RZ, R2 ; /* 0x000000ffff071224 */
/* 0x000fe200078e0202 */
/*06e0*/ ISETP.NE.AND P1, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fc80003f25270 */
/*06f0*/ IADD3 R2, R7, 0x1, RZ ; /* 0x0000000107027810 */
/* 0x000fe20007ffe0ff */
/*0700*/ @P2 IMAD.MOV R2, RZ, RZ, R7 ; /* 0x000000ffff022224 */
/* 0x000fe200078e0207 */
/*0710*/ ISETP.NE.AND P2, PT, R26, 0x1, PT ; /* 0x000000011a00780c */
/* 0x000fc80003f45270 */
/*0720*/ IADD3 R7, R2, 0x1, RZ ; /* 0x0000000102077810 */
/* 0x000fc60007ffe0ff */
/*0730*/ @P1 IMAD.MOV R7, RZ, RZ, R2 ; /* 0x000000ffff071224 */
/* 0x000fe200078e0202 */
/*0740*/ ISETP.NE.AND P1, PT, R27, 0x1, PT ; /* 0x000000011b00780c */
/* 0x000fc80003f25270 */
/*0750*/ IADD3 R2, R7, 0x1, RZ ; /* 0x0000000107027810 */
/* 0x000fe20007ffe0ff */
/*0760*/ @P2 IMAD.MOV R2, RZ, RZ, R7 ; /* 0x000000ffff022224 */
/* 0x000fe200078e0207 */
/*0770*/ ISETP.NE.AND P2, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x000fc80003f45270 */
/*0780*/ IADD3 R7, R2, 0x1, RZ ; /* 0x0000000102077810 */
/* 0x000fc60007ffe0ff */
/*0790*/ @P1 IMAD.MOV R7, RZ, RZ, R2 ; /* 0x000000ffff071224 */
/* 0x000fe200078e0202 */
/*07a0*/ ISETP.NE.AND P1, PT, R28, 0x1, PT ; /* 0x000000011c00780c */
/* 0x000fc80003f25270 */
/*07b0*/ IADD3 R2, R7, 0x1, RZ ; /* 0x0000000107027810 */
/* 0x000fe20007ffe0ff */
/*07c0*/ @P2 IMAD.MOV R2, RZ, RZ, R7 ; /* 0x000000ffff022224 */
/* 0x000fe200078e0207 */
/*07d0*/ ISETP.NE.AND P2, PT, R17, 0x1, PT ; /* 0x000000011100780c */
/* 0x000fc80003f45270 */
/*07e0*/ IADD3 R7, R2, 0x1, RZ ; /* 0x0000000102077810 */
/* 0x000fc60007ffe0ff */
/*07f0*/ @P1 IMAD.MOV R7, RZ, RZ, R2 ; /* 0x000000ffff071224 */
/* 0x000fe200078e0202 */
/*0800*/ ISETP.NE.AND P1, PT, R18, 0x1, PT ; /* 0x000000011200780c */
/* 0x000fc80003f25270 */
/*0810*/ IADD3 R2, R7, 0x1, RZ ; /* 0x0000000107027810 */
/* 0x000fe20007ffe0ff */
/*0820*/ @P2 IMAD.MOV R2, RZ, RZ, R7 ; /* 0x000000ffff022224 */
/* 0x000fe200078e0207 */
/*0830*/ ISETP.NE.AND P2, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fe40003f45270 */
/*0840*/ IADD3 R7, R4, R29, R4.reuse ; /* 0x0000001d04077210 */
/* 0x100fe40007ffe004 */
/*0850*/ IADD3 R8, R2, 0x1, RZ ; /* 0x0000000102087810 */
/* 0x000fe40007ffe0ff */
/*0860*/ IADD3 R7, R4, R7, R4 ; /* 0x0000000704077210 */
/* 0x000fe20007ffe004 */
/*0870*/ @P1 IMAD.MOV R8, RZ, RZ, R2 ; /* 0x000000ffff081224 */
/* 0x000fe200078e0202 */
/*0880*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fc80003f24270 */
/*0890*/ IADD3 R2, R8, 0x1, RZ ; /* 0x0000000108027810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ @P2 IMAD.MOV R2, RZ, RZ, R8 ; /* 0x000000ffff022224 */
/* 0x000fd000078e0208 */
/*08b0*/ @P1 BRA 0x300 ; /* 0xfffffa4000001947 */
/* 0x000fea000383ffff */
/*08c0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*08d0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fe20003f24270 */
/*08e0*/ BSSY B3, 0xc00 ; /* 0x0000031000037945 */
/* 0x000fd80003800000 */
/*08f0*/ @!P1 BRA 0xbf0 ; /* 0x000002f000009947 */
/* 0x000fea0003800000 */
/*0900*/ IMAD.MOV.U32 R18, RZ, RZ, 0x4 ; /* 0x00000004ff127424 */
/* 0x000fc800078e00ff */
/*0910*/ IMAD.WIDE R10, R7, R18, c[0x0][0x168] ; /* 0x00005a00070a7625 */
/* 0x000fca00078e0212 */
/*0920*/ LDG.E R22, [R10.64] ; /* 0x000000060a167981 */
/* 0x0000a2000c1e1900 */
/*0930*/ IMAD.WIDE R12, R4, 0x4, R10 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020a */
/*0940*/ LDG.E R8, [R12.64] ; /* 0x000000060c087981 */
/* 0x0002e2000c1e1900 */
/*0950*/ IMAD.WIDE R14, R4.reuse, 0x4, R12 ; /* 0x00000004040e7825 */
/* 0x040fe200078e020c */
/*0960*/ IADD3 R7, R4, R7, R4 ; /* 0x0000000704077210 */
/* 0x000fc80007ffe004 */
/*0970*/ LDG.E R9, [R14.64] ; /* 0x000000060e097981 */
/* 0x000f22000c1e1900 */
/*0980*/ IMAD.WIDE R16, R4.reuse, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x040fe200078e020e */
/*0990*/ IADD3 R7, R4, R7, R4 ; /* 0x0000000704077210 */
/* 0x000fca0007ffe004 */
/*09a0*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000f62000c1e1900 */
/*09b0*/ IMAD.WIDE R18, R7, R18, c[0x0][0x168] ; /* 0x00005a0007127625 */
/* 0x000fca00078e0212 */
/*09c0*/ LDG.E R23, [R18.64] ; /* 0x0000000612177981 */
/* 0x000f62000c1e1900 */
/*09d0*/ IMAD.WIDE R20, R4, 0x4, R18 ; /* 0x0000000404147825 */
/* 0x000fca00078e0212 */
/*09e0*/ LDG.E R24, [R20.64] ; /* 0x0000000614187981 */
/* 0x000f62000c1e1900 */
/*09f0*/ IMAD.WIDE R10, R4, 0x4, R20 ; /* 0x00000004040a7825 */
/* 0x001fca00078e0214 */
/*0a00*/ LDG.E R25, [R10.64] ; /* 0x000000060a197981 */
/* 0x000f62000c1e1900 */
/*0a10*/ IMAD.WIDE R12, R4, 0x4, R10 ; /* 0x00000004040c7825 */
/* 0x002fcc00078e020a */
/*0a20*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000f62000c1e1900 */
/*0a30*/ IADD3 R7, R4.reuse, R7, R4.reuse ; /* 0x0000000704077210 */
/* 0x140fe40007ffe004 */
/*0a40*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe40007ffe0ff */
/*0a50*/ IADD3 R7, R4, R7, R4 ; /* 0x0000000704077210 */
/* 0x000fe40007ffe004 */
/*0a60*/ ISETP.NE.AND P0, PT, R22, 0x1, PT ; /* 0x000000011600780c */
/* 0x004fe40003f05270 */
/*0a70*/ ISETP.NE.AND P1, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x008fe40003f25270 */
/*0a80*/ IADD3 R8, R2, 0x1, RZ ; /* 0x0000000102087810 */
/* 0x000fd20007ffe0ff */
/*0a90*/ @P0 IMAD.MOV R8, RZ, RZ, R2 ; /* 0x000000ffff080224 */
/* 0x000fe200078e0202 */
/*0aa0*/ ISETP.NE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x010fc80003f05270 */
/*0ab0*/ IADD3 R2, R8, 0x1, RZ ; /* 0x0000000108027810 */
/* 0x000fe20007ffe0ff */
/*0ac0*/ @P1 IMAD.MOV R2, RZ, RZ, R8 ; /* 0x000000ffff021224 */
/* 0x000fe200078e0208 */
/*0ad0*/ ISETP.NE.AND P1, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x020fc80003f25270 */
/*0ae0*/ IADD3 R8, R2, 0x1, RZ ; /* 0x0000000102087810 */
/* 0x000fc60007ffe0ff */
/*0af0*/ @P0 IMAD.MOV R8, RZ, RZ, R2 ; /* 0x000000ffff080224 */
/* 0x000fe200078e0202 */
/*0b00*/ ISETP.NE.AND P0, PT, R23, 0x1, PT ; /* 0x000000011700780c */
/* 0x000fc80003f05270 */
/*0b10*/ IADD3 R2, R8, 0x1, RZ ; /* 0x0000000108027810 */
/* 0x000fe20007ffe0ff */
/*0b20*/ @P1 IMAD.MOV R2, RZ, RZ, R8 ; /* 0x000000ffff021224 */
/* 0x000fe200078e0208 */
/*0b30*/ ISETP.NE.AND P1, PT, R24, 0x1, PT ; /* 0x000000011800780c */
/* 0x000fc80003f25270 */
/*0b40*/ IADD3 R8, R2, 0x1, RZ ; /* 0x0000000102087810 */
/* 0x000fc60007ffe0ff */
/*0b50*/ @P0 IMAD.MOV R8, RZ, RZ, R2 ; /* 0x000000ffff080224 */
/* 0x000fe200078e0202 */
/*0b60*/ ISETP.NE.AND P0, PT, R25, 0x1, PT ; /* 0x000000011900780c */
/* 0x000fc80003f05270 */
/*0b70*/ IADD3 R2, R8, 0x1, RZ ; /* 0x0000000108027810 */
/* 0x000fe20007ffe0ff */
/*0b80*/ @P1 IMAD.MOV R2, RZ, RZ, R8 ; /* 0x000000ffff021224 */
/* 0x000fe200078e0208 */
/*0b90*/ ISETP.NE.AND P1, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fc80003f25270 */
/*0ba0*/ IADD3 R8, R2, 0x1, RZ ; /* 0x0000000102087810 */
/* 0x000fc60007ffe0ff */
/*0bb0*/ @P0 IMAD.MOV R8, RZ, RZ, R2 ; /* 0x000000ffff080224 */
/* 0x000fe200078e0202 */
/*0bc0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0e170 */
/*0bd0*/ IADD3 R2, R8, 0x1, RZ ; /* 0x0000000108027810 */
/* 0x000fe20007ffe0ff */
/*0be0*/ @P1 IMAD.MOV R2, RZ, RZ, R8 ; /* 0x000000ffff021224 */
/* 0x000fc600078e0208 */
/*0bf0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0c00*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0c10*/ @!P0 BREAK B0 ; /* 0x0000000000008942 */
/* 0x000fe20003800000 */
/*0c20*/ @!P0 BRA 0xde0 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0c30*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0c40*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fc800078e00ff */
/*0c50*/ IMAD.WIDE R8, R7, R8, c[0x0][0x168] ; /* 0x00005a0007087625 */
/* 0x000fca00078e0208 */
/*0c60*/ LDG.E R18, [R8.64] ; /* 0x0000000608127981 */
/* 0x000ea2000c1e1900 */
/*0c70*/ IMAD.WIDE R10, R4, 0x4, R8 ; /* 0x00000004040a7825 */
/* 0x000fca00078e0208 */
/*0c80*/ LDG.E R16, [R10.64] ; /* 0x000000060a107981 */
/* 0x000ee2000c1e1900 */
/*0c90*/ IMAD.WIDE R12, R4, 0x4, R10 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020a */
/*0ca0*/ LDG.E R17, [R12.64] ; /* 0x000000060c117981 */
/* 0x000f22000c1e1900 */
/*0cb0*/ IMAD.WIDE R14, R4, 0x4, R12 ; /* 0x00000004040e7825 */
/* 0x000fcc00078e020c */
/*0cc0*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000f62000c1e1900 */
/*0cd0*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fe40007ffe0ff */
/*0ce0*/ IADD3 R7, R4, R7, R4 ; /* 0x0000000704077210 */
/* 0x000fc80007ffe004 */
/*0cf0*/ IADD3 R7, R4, R7, R4 ; /* 0x0000000704077210 */
/* 0x000fe40007ffe004 */
/*0d00*/ ISETP.NE.AND P0, PT, R18, 0x1, PT ; /* 0x000000011200780c */
/* 0x004fe40003f05270 */
/*0d10*/ ISETP.NE.AND P1, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x008fe40003f25270 */
/*0d20*/ IADD3 R16, R2, 0x1, RZ ; /* 0x0000000102107810 */
/* 0x000fd20007ffe0ff */
/*0d30*/ @P0 IMAD.MOV R16, RZ, RZ, R2 ; /* 0x000000ffff100224 */
/* 0x000fe200078e0202 */
/*0d40*/ ISETP.NE.AND P0, PT, R17, 0x1, PT ; /* 0x000000011100780c */
/* 0x010fc80003f05270 */
/*0d50*/ IADD3 R2, R16, 0x1, RZ ; /* 0x0000000110027810 */
/* 0x000fe20007ffe0ff */
/*0d60*/ @P1 IMAD.MOV R2, RZ, RZ, R16 ; /* 0x000000ffff021224 */
/* 0x000fe200078e0210 */
/*0d70*/ ISETP.NE.AND P1, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x020fc80003f25270 */
/*0d80*/ IADD3 R8, R2, 0x1, RZ ; /* 0x0000000102087810 */
/* 0x000fc60007ffe0ff */
/*0d90*/ @P0 IMAD.MOV R8, RZ, RZ, R2 ; /* 0x000000ffff080224 */
/* 0x000fe200078e0202 */
/*0da0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc80003f05270 */
/*0db0*/ IADD3 R2, R8, 0x1, RZ ; /* 0x0000000108027810 */
/* 0x000fe20007ffe0ff */
/*0dc0*/ @P1 IMAD.MOV R2, RZ, RZ, R8 ; /* 0x000000ffff021224 */
/* 0x000fd000078e0208 */
/*0dd0*/ @P0 BRA 0xc40 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0de0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0df0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0e00*/ @!P0 BRA 0xec0 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0e10*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fc800078e00ff */
/*0e20*/ IMAD.WIDE R8, R7, R8, c[0x0][0x168] ; /* 0x00005a0007087625 */
/* 0x000fca00078e0208 */
/*0e30*/ LDG.E R5, [R8.64] ; /* 0x0000000608057981 */
/* 0x0000a2000c1e1900 */
/*0e40*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fc80007ffe0ff */
/*0e50*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f25270 */
/*0e60*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x001fe200078e0208 */
/*0e70*/ ISETP.NE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x004fe40003f05270 */
/*0e80*/ IADD3 R5, R2, 0x1, RZ ; /* 0x0000000102057810 */
/* 0x000fd60007ffe0ff */
/*0e90*/ @P0 IMAD.MOV R5, RZ, RZ, R2 ; /* 0x000000ffff050224 */
/* 0x000fc800078e0202 */
/*0ea0*/ IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0005 */
/*0eb0*/ @P1 BRA 0xe30 ; /* 0xffffff7000001947 */
/* 0x000fea000383ffff */
/*0ec0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0ed0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0ee0*/ S2R R4, SR_LANEID ; /* 0x0000000000047919 */
/* 0x000e220000000000 */
/*0ef0*/ REDUX.SUM UR5, R2 ; /* 0x00000000020573c4 */
/* 0x000e62000000c000 */
/*0f00*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*0f10*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0f20*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*0f30*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fca0003f05270 */
/*0f40*/ ISETP.EQ.U32.AND P1, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x001fe2000bf22070 */
/*0f50*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0005 */
/*0f60*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x002fd0000f8e00ff */
/*0f70*/ @P1 RED.E.ADD.STRONG.GPU [R4.64], R3 ; /* 0x000000030400198e */
/* 0x0001e8000c10e186 */
/*0f80*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0f90*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0fa0*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x001ea2000c1e1900 */
/*0fb0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fc400078e00ff */
/*0fc0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff037624 */
/* 0x000fca00078e00ff */
/*0fd0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x004fe2000c10e186 */
/*0fe0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ff0*/ BRA 0xff0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <fstream>
#include <chrono>
__global__
void sumOne(int n,int *m,int *partialSum,int *sum){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
int threadSum =0;
for (int i = index; i < n; i += stride){
if(m[i]==1){
threadSum++;
}
}
// Block Sum
atomicAdd(&partialSum[blockIdx.x],threadSum);
__syncthreads();
if(threadIdx.x==0){
// Global Sum;
atomicAdd(&sum[0],partialSum[blockIdx.x]);
}
}
int main(int argc,char **argv){
//Read input matrix
std::ifstream infile;
infile.open(argv[1]);
if (!infile.is_open()){
std::cerr << "Couldn't read " << argv[1] << std::endl;
return 0;
}
int w,h;
infile >> w >> h;
int N = w*h;
int *m;
//Unified memory allocation
cudaMallocManaged(&m, N*sizeof(int));
for(int i=0;i<N;i++){
infile >> m[i];
}
infile.close();
auto start = std::chrono::system_clock::now();
//Block,Grid parameters
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
int *partialSum;
int *sum;
cudaMallocManaged(&partialSum,numBlocks*sizeof(int));
cudaMallocManaged(&sum, sizeof(int));
//prefetch input matrix
int device = -1;
cudaGetDevice(&device);
cudaMemPrefetchAsync(m, N*sizeof(int), device, NULL);
cudaMemPrefetchAsync(partialSum, numBlocks*sizeof(int), device, NULL);
cudaMemPrefetchAsync(sum, sizeof(int), device, NULL);
//Sum ones
sumOne<<<numBlocks, blockSize>>>(N, m, partialSum,sum);
cudaDeviceSynchronize();
std::cout << sum[0] << std::endl;
cudaFree(m);
cudaFree(partialSum);
cudaFree(sum);
return 0;
} | .file "tmpxft_0013445c_00000000-6_Homework2_1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3902:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3902:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6sumOneiPiS_S_iPiS_S_
.type _Z30__device_stub__Z6sumOneiPiS_S_iPiS_S_, @function
_Z30__device_stub__Z6sumOneiPiS_S_iPiS_S_:
.LFB3924:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6sumOneiPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3924:
.size _Z30__device_stub__Z6sumOneiPiS_S_iPiS_S_, .-_Z30__device_stub__Z6sumOneiPiS_S_iPiS_S_
.globl _Z6sumOneiPiS_S_
.type _Z6sumOneiPiS_S_, @function
_Z6sumOneiPiS_S_:
.LFB3925:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6sumOneiPiS_S_iPiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3925:
.size _Z6sumOneiPiS_S_, .-_Z6sumOneiPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6sumOneiPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3927:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6sumOneiPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3927:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC1:
.string "Couldn't read "
.text
.globl main
.type main, @function
main:
.LFB3899:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3899
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $600, %rsp
.cfi_def_cfa_offset 640
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 584(%rsp)
xorl %eax, %eax
leaq 64(%rsp), %rbp
movq %rbp, %rdi
.LEHB0:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE0:
movq 8(%rbx), %rsi
movl $8, %edx
movq %rbp, %rdi
.LEHB1:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
leaq 184(%rsp), %rdi
call _ZNKSt12__basic_fileIcE7is_openEv@PLT
testb %al, %al
je .L26
leaq 4(%rsp), %rsi
leaq 64(%rsp), %rdi
call _ZNSirsERi@PLT
jmp .L27
.L26:
leaq .LC1(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 8(%rbx), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L15
.L27:
movq %rax, %rdi
leaq 8(%rsp), %rsi
call _ZNSirsERi@PLT
movl 4(%rsp), %r13d
imull 8(%rsp), %r13d
movslq %r13d, %rbp
salq $2, %rbp
leaq 16(%rsp), %rdi
movl $1, %edx
movq %rbp, %rsi
call cudaMallocManaged@PLT
testl %r13d, %r13d
jle .L16
movl $0, %ebx
leaq 64(%rsp), %r12
jmp .L17
.L28:
addq $4, %rbx
cmpq %rbx, %rbp
je .L16
.L17:
movq %rbx, %rsi
addq 16(%rsp), %rsi
movq %r12, %rdi
call _ZNSirsERi@PLT
jmp .L28
.L16:
leaq 64(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
leal 255(%r13), %eax
movl $256, %ecx
cltd
idivl %ecx
movl %eax, %ebx
movslq %eax, %r12
salq $2, %r12
leaq 24(%rsp), %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
leaq 32(%rsp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
movl $-1, 12(%rsp)
leaq 12(%rsp), %rdi
call cudaGetDevice@PLT
movl $0, %ecx
movl 12(%rsp), %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $0, %ecx
movl 12(%rsp), %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $0, %ecx
movl 12(%rsp), %edx
movl $4, %esi
movq 32(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $256, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %ebx, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L18
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movl %r13d, %edi
call _Z30__device_stub__Z6sumOneiPiS_S_iPiS_S_
.L18:
call cudaDeviceSynchronize@PLT
movq 32(%rsp), %rax
movl (%rax), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
.LEHE1:
.L15:
leaq 64(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 584(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $600, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 584(%rsp), %rax
subq %fs:40, %rax
je .L20
call __stack_chk_fail@PLT
.L20:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3899:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3899:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3899-.LLSDACSB3899
.LLSDACSB3899:
.uleb128 .LEHB0-.LFB3899
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3899
.uleb128 .LEHE1-.LEHB1
.uleb128 .L22-.LFB3899
.uleb128 0
.uleb128 .LEHB2-.LFB3899
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE3899:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <fstream>
#include <chrono>
__global__
void sumOne(int n,int *m,int *partialSum,int *sum){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
int threadSum =0;
for (int i = index; i < n; i += stride){
if(m[i]==1){
threadSum++;
}
}
// Block Sum
atomicAdd(&partialSum[blockIdx.x],threadSum);
__syncthreads();
if(threadIdx.x==0){
// Global Sum;
atomicAdd(&sum[0],partialSum[blockIdx.x]);
}
}
int main(int argc,char **argv){
//Read input matrix
std::ifstream infile;
infile.open(argv[1]);
if (!infile.is_open()){
std::cerr << "Couldn't read " << argv[1] << std::endl;
return 0;
}
int w,h;
infile >> w >> h;
int N = w*h;
int *m;
//Unified memory allocation
cudaMallocManaged(&m, N*sizeof(int));
for(int i=0;i<N;i++){
infile >> m[i];
}
infile.close();
auto start = std::chrono::system_clock::now();
//Block,Grid parameters
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
int *partialSum;
int *sum;
cudaMallocManaged(&partialSum,numBlocks*sizeof(int));
cudaMallocManaged(&sum, sizeof(int));
//prefetch input matrix
int device = -1;
cudaGetDevice(&device);
cudaMemPrefetchAsync(m, N*sizeof(int), device, NULL);
cudaMemPrefetchAsync(partialSum, numBlocks*sizeof(int), device, NULL);
cudaMemPrefetchAsync(sum, sizeof(int), device, NULL);
//Sum ones
sumOne<<<numBlocks, blockSize>>>(N, m, partialSum,sum);
cudaDeviceSynchronize();
std::cout << sum[0] << std::endl;
cudaFree(m);
cudaFree(partialSum);
cudaFree(sum);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <chrono>
__global__
void sumOne(int n,int *m,int *partialSum,int *sum){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
int threadSum =0;
for (int i = index; i < n; i += stride){
if(m[i]==1){
threadSum++;
}
}
// Block Sum
atomicAdd(&partialSum[blockIdx.x],threadSum);
__syncthreads();
if(threadIdx.x==0){
// Global Sum;
atomicAdd(&sum[0],partialSum[blockIdx.x]);
}
}
int main(int argc,char **argv){
//Read input matrix
std::ifstream infile;
infile.open(argv[1]);
if (!infile.is_open()){
std::cerr << "Couldn't read " << argv[1] << std::endl;
return 0;
}
int w,h;
infile >> w >> h;
int N = w*h;
int *m;
//Unified memory allocation
hipMallocManaged(&m, N*sizeof(int));
for(int i=0;i<N;i++){
infile >> m[i];
}
infile.close();
auto start = std::chrono::system_clock::now();
//Block,Grid parameters
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
int *partialSum;
int *sum;
hipMallocManaged(&partialSum,numBlocks*sizeof(int));
hipMallocManaged(&sum, sizeof(int));
//prefetch input matrix
int device = -1;
hipGetDevice(&device);
hipMemPrefetchAsync(m, N*sizeof(int), device, NULL);
hipMemPrefetchAsync(partialSum, numBlocks*sizeof(int), device, NULL);
hipMemPrefetchAsync(sum, sizeof(int), device, NULL);
//Sum ones
sumOne<<<numBlocks, blockSize>>>(N, m, partialSum,sum);
hipDeviceSynchronize();
std::cout << sum[0] << std::endl;
hipFree(m);
hipFree(partialSum);
hipFree(sum);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <chrono>
__global__
void sumOne(int n,int *m,int *partialSum,int *sum){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
int threadSum =0;
for (int i = index; i < n; i += stride){
if(m[i]==1){
threadSum++;
}
}
// Block Sum
atomicAdd(&partialSum[blockIdx.x],threadSum);
__syncthreads();
if(threadIdx.x==0){
// Global Sum;
atomicAdd(&sum[0],partialSum[blockIdx.x]);
}
}
int main(int argc,char **argv){
//Read input matrix
std::ifstream infile;
infile.open(argv[1]);
if (!infile.is_open()){
std::cerr << "Couldn't read " << argv[1] << std::endl;
return 0;
}
int w,h;
infile >> w >> h;
int N = w*h;
int *m;
//Unified memory allocation
hipMallocManaged(&m, N*sizeof(int));
for(int i=0;i<N;i++){
infile >> m[i];
}
infile.close();
auto start = std::chrono::system_clock::now();
//Block,Grid parameters
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
int *partialSum;
int *sum;
hipMallocManaged(&partialSum,numBlocks*sizeof(int));
hipMallocManaged(&sum, sizeof(int));
//prefetch input matrix
int device = -1;
hipGetDevice(&device);
hipMemPrefetchAsync(m, N*sizeof(int), device, NULL);
hipMemPrefetchAsync(partialSum, numBlocks*sizeof(int), device, NULL);
hipMemPrefetchAsync(sum, sizeof(int), device, NULL);
//Sum ones
sumOne<<<numBlocks, blockSize>>>(N, m, partialSum,sum);
hipDeviceSynchronize();
std::cout << sum[0] << std::endl;
hipFree(m);
hipFree(partialSum);
hipFree(sum);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6sumOneiPiS_S_
.globl _Z6sumOneiPiS_S_
.p2align 8
.type _Z6sumOneiPiS_S_,@function
_Z6sumOneiPiS_S_:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b32 s5, s[0:1], 0x0
s_add_u32 s2, s0, 32
s_mov_b32 s4, s15
s_addc_u32 s3, s1, 0
v_mov_b32_e32 v4, 0
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s4, s6, v[0:1]
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_4
s_load_b32 s7, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s6, s7, s6
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_ashr_i32 s7, s6, 31
s_mov_b32 s3, 0
s_lshl_b64 s[8:9], s[6:7], 2
.LBB0_2:
global_load_b32 v5, v[2:3], off
v_add_nc_u32_e32 v1, s6, v1
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, s5, v1
s_or_b32 s3, vcc_lo, s3
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s2, 1, v5
v_add_co_ci_u32_e64 v4, s2, 0, v4, s2
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s3
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
s_mov_b32 s2, exec_lo
s_mov_b32 s6, 0
.LBB0_5:
s_ctz_i32_b32 s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s5, v4, s3
s_lshl_b32 s3, 1, s3
s_and_not1_b32 s2, s2, s3
s_delay_alu instid0(VALU_DEP_1)
s_add_i32 s6, s6, s5
s_cmp_lg_u32 s2, 0
s_cbranch_scc1 .LBB0_5
s_load_b64 s[2:3], s[0:1], 0x10
s_mov_b32 s5, 0
v_mbcnt_lo_u32_b32 v1, exec_lo, 0
s_lshl_b64 s[4:5], s[4:5], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s4
s_addc_u32 s3, s3, s5
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v1
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s6
global_atomic_add_u32 v1, v2, s[2:3]
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_11
s_mov_b32 s4, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v0, s4, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 s5, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s5
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x18
global_load_b32 v1, v0, s[2:3]
s_bcnt1_i32_b32 s2, s4
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v1, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6sumOneiPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6sumOneiPiS_S_, .Lfunc_end0-_Z6sumOneiPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6sumOneiPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6sumOneiPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <chrono>
__global__
void sumOne(int n,int *m,int *partialSum,int *sum){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
int threadSum =0;
for (int i = index; i < n; i += stride){
if(m[i]==1){
threadSum++;
}
}
// Block Sum
atomicAdd(&partialSum[blockIdx.x],threadSum);
__syncthreads();
if(threadIdx.x==0){
// Global Sum;
atomicAdd(&sum[0],partialSum[blockIdx.x]);
}
}
int main(int argc,char **argv){
//Read input matrix
std::ifstream infile;
infile.open(argv[1]);
if (!infile.is_open()){
std::cerr << "Couldn't read " << argv[1] << std::endl;
return 0;
}
int w,h;
infile >> w >> h;
int N = w*h;
int *m;
//Unified memory allocation
hipMallocManaged(&m, N*sizeof(int));
for(int i=0;i<N;i++){
infile >> m[i];
}
infile.close();
auto start = std::chrono::system_clock::now();
//Block,Grid parameters
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
int *partialSum;
int *sum;
hipMallocManaged(&partialSum,numBlocks*sizeof(int));
hipMallocManaged(&sum, sizeof(int));
//prefetch input matrix
int device = -1;
hipGetDevice(&device);
hipMemPrefetchAsync(m, N*sizeof(int), device, NULL);
hipMemPrefetchAsync(partialSum, numBlocks*sizeof(int), device, NULL);
hipMemPrefetchAsync(sum, sizeof(int), device, NULL);
//Sum ones
sumOne<<<numBlocks, blockSize>>>(N, m, partialSum,sum);
hipDeviceSynchronize();
std::cout << sum[0] << std::endl;
hipFree(m);
hipFree(partialSum);
hipFree(sum);
return 0;
} | .text
.file "Homework2_1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__sumOneiPiS_S_ # -- Begin function _Z21__device_stub__sumOneiPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__sumOneiPiS_S_,@function
_Z21__device_stub__sumOneiPiS_S_: # @_Z21__device_stub__sumOneiPiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6sumOneiPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__sumOneiPiS_S_, .Lfunc_end0-_Z21__device_stub__sumOneiPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $680, %rsp # imm = 0x2A8
.cfi_def_cfa_offset 736
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
.cfi_escape 0x2e, 0x00
leaq 160(%rsp), %r15
movq %r15, %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev
movq 8(%rbx), %rsi
leaq 176(%rsp), %r14
.Ltmp0:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $8, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.1: # %.noexc
movq 160(%rsp), %rcx
addq -24(%rcx), %r15
xorl %esi, %esi
testq %rax, %rax
jne .LBB1_3
# %bb.2:
movl 32(%r15), %esi
orl $4, %esi
.LBB1_3: # %.invoke
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp3:
# %bb.4: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
leaq 280(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNKSt12__basic_fileIcE7is_openEv
testb %al, %al
je .LBB1_5
# %bb.18:
.Ltmp21:
.cfi_escape 0x2e, 0x00
leaq 160(%rsp), %rdi
leaq 48(%rsp), %rsi
callq _ZNSirsERi
.Ltmp22:
# %bb.19:
.Ltmp23:
.cfi_escape 0x2e, 0x00
leaq 44(%rsp), %rsi
movq %rax, %rdi
callq _ZNSirsERi
.Ltmp24:
# %bb.20:
movslq 48(%rsp), %rax
movslq 44(%rsp), %r12
imulq %rax, %r12
leaq (,%r12,4), %rbx
.Ltmp26:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movq %rbx, %rsi
movl $1, %edx
callq hipMallocManaged
.Ltmp27:
# %bb.21: # %_ZL16hipMallocManagedIiE10hipError_tPPT_mj.exit.preheader
testl %r12d, %r12d
jle .LBB1_25
# %bb.22: # %.lr.ph.preheader
movl %r12d, %r13d
shlq $2, %r13
xorl %ebp, %ebp
leaq 160(%rsp), %r15
.p2align 4, 0x90
.LBB1_23: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq 24(%rsp), %rsi
addq %rbp, %rsi
.Ltmp28:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNSirsERi
.Ltmp29:
# %bb.24: # %_ZL16hipMallocManagedIiE10hipError_tPPT_mj.exit
# in Loop: Header=BB1_23 Depth=1
addq $4, %rbp
cmpq %rbp, %r13
jne .LBB1_23
.LBB1_25: # %_ZL16hipMallocManagedIiE10hipError_tPPT_mj.exit._crit_edge
.Ltmp31:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp32:
# %bb.26: # %.noexc42
testq %rax, %rax
jne .LBB1_28
# %bb.27:
movq 160(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $160, %rdi
movl 192(%rsp,%rax), %esi
orl $4, %esi
.Ltmp33:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp34:
.LBB1_28: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv.exit
.cfi_escape 0x2e, 0x00
callq _ZNSt6chrono3_V212system_clock3nowEv
leal 255(%r12), %eax
leal 510(%r12), %ebp
testl %eax, %eax
cmovnsl %eax, %ebp
sarl $8, %ebp
movslq %ebp, %r14
shlq $2, %r14
.Ltmp36:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
movq %r14, %rsi
movl $1, %edx
callq hipMallocManaged
.Ltmp37:
# %bb.29: # %_ZL16hipMallocManagedIiE10hipError_tPPT_mj.exit45
.Ltmp38:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
.Ltmp39:
# %bb.30: # %_ZL16hipMallocManagedIiE10hipError_tPPT_mj.exit47
movl $-1, 12(%rsp)
.Ltmp41:
.cfi_escape 0x2e, 0x00
leaq 12(%rsp), %rdi
callq hipGetDevice
.Ltmp42:
# %bb.31:
movq 24(%rsp), %rdi
movl 12(%rsp), %edx
.Ltmp43:
.cfi_escape 0x2e, 0x00
movq %rbx, %rsi
xorl %ecx, %ecx
callq hipMemPrefetchAsync
.Ltmp44:
# %bb.32:
movq 32(%rsp), %rdi
movl 12(%rsp), %edx
.Ltmp45:
.cfi_escape 0x2e, 0x00
movq %r14, %rsi
xorl %ecx, %ecx
callq hipMemPrefetchAsync
.Ltmp46:
# %bb.33:
movq 16(%rsp), %rdi
movl 12(%rsp), %edx
.Ltmp47:
.cfi_escape 0x2e, 0x00
movl $4, %esi
xorl %ecx, %ecx
callq hipMemPrefetchAsync
.Ltmp48:
# %bb.34:
movl %ebp, %eax
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rax, %rdi
.Ltmp49:
.cfi_escape 0x2e, 0x00
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp50:
# %bb.35:
testl %eax, %eax
jne .LBB1_38
# %bb.36:
movq 24(%rsp), %rax
movq 32(%rsp), %rcx
movq 16(%rsp), %rdx
movl %r12d, 52(%rsp)
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 52(%rsp), %rax
movq %rax, 128(%rsp)
leaq 120(%rsp), %rax
movq %rax, 136(%rsp)
leaq 112(%rsp), %rax
movq %rax, 144(%rsp)
leaq 104(%rsp), %rax
movq %rax, 152(%rsp)
.Ltmp51:
.cfi_escape 0x2e, 0x00
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp52:
# %bb.37: # %.noexc48
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
.Ltmp53:
.cfi_escape 0x2e, 0x10
leaq 128(%rsp), %r9
movl $_Z6sumOneiPiS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp54:
.LBB1_38:
.Ltmp55:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp56:
# %bb.39:
movq 16(%rsp), %rax
movl (%rax), %esi
.Ltmp57:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSolsEi
.Ltmp58:
# %bb.40:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_41
# %bb.48: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i58
cmpb $0, 56(%r14)
je .LBB1_50
# %bb.49:
movzbl 67(%r14), %eax
jmp .LBB1_52
.LBB1_5:
.Ltmp4:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp5:
# %bb.6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq 8(%rbx), %rbx
testq %rbx, %rbx
je .LBB1_7
# %bb.8:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq strlen
.Ltmp6:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp7:
jmp .LBB1_9
.LBB1_7:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
.Ltmp8:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp9:
.LBB1_9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit38
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_10
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_14
# %bb.13:
movzbl 67(%rbx), %eax
jmp .LBB1_16
.LBB1_14:
.Ltmp10:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp11:
# %bb.15: # %.noexc53
movq (%rbx), %rax
.Ltmp12:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp13:
.LBB1_16: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp14:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
.Ltmp15:
# %bb.17: # %.noexc55
.Ltmp16:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp17:
jmp .LBB1_57
.LBB1_50:
.Ltmp59:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp60:
# %bb.51: # %.noexc63
movq (%r14), %rax
.Ltmp61:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp62:
.LBB1_52: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i60
.Ltmp63:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp64:
# %bb.53: # %.noexc65
.Ltmp65:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp66:
# %bb.54: # %_ZNSolsEPFRSoS_E.exit51
movq 24(%rsp), %rdi
.Ltmp67:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp68:
# %bb.55:
movq 32(%rsp), %rdi
.Ltmp69:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp70:
# %bb.56:
movq 16(%rsp), %rdi
.Ltmp71:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp72:
.LBB1_57: # %_ZNSolsEPFRSoS_E.exit
.cfi_escape 0x2e, 0x00
leaq 160(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 416(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
xorl %eax, %eax
addq $680, %rsp # imm = 0x2A8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_10:
.cfi_def_cfa_offset 736
.Ltmp18:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp19:
# %bb.11: # %.noexc52
.LBB1_41:
.Ltmp73:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp74:
# %bb.47: # %.noexc62
.LBB1_45:
.Ltmp40:
jmp .LBB1_59
.LBB1_42:
.Ltmp25:
jmp .LBB1_59
.LBB1_43:
.Ltmp35:
jmp .LBB1_59
.LBB1_58:
.Ltmp20:
jmp .LBB1_59
.LBB1_46:
.Ltmp75:
jmp .LBB1_59
.LBB1_44:
.Ltmp30:
.LBB1_59:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 160(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 416(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp20-.Lfunc_begin0 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp24-.Ltmp21 # Call between .Ltmp21 and .Ltmp24
.uleb128 .Ltmp25-.Lfunc_begin0 # jumps to .Ltmp25
.byte 0 # On action: cleanup
.uleb128 .Ltmp26-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp27-.Ltmp26 # Call between .Ltmp26 and .Ltmp27
.uleb128 .Ltmp35-.Lfunc_begin0 # jumps to .Ltmp35
.byte 0 # On action: cleanup
.uleb128 .Ltmp28-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp29-.Ltmp28 # Call between .Ltmp28 and .Ltmp29
.uleb128 .Ltmp30-.Lfunc_begin0 # jumps to .Ltmp30
.byte 0 # On action: cleanup
.uleb128 .Ltmp31-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp34-.Ltmp31 # Call between .Ltmp31 and .Ltmp34
.uleb128 .Ltmp35-.Lfunc_begin0 # jumps to .Ltmp35
.byte 0 # On action: cleanup
.uleb128 .Ltmp36-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp39-.Ltmp36 # Call between .Ltmp36 and .Ltmp39
.uleb128 .Ltmp40-.Lfunc_begin0 # jumps to .Ltmp40
.byte 0 # On action: cleanup
.uleb128 .Ltmp41-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp58-.Ltmp41 # Call between .Ltmp41 and .Ltmp58
.uleb128 .Ltmp75-.Lfunc_begin0 # jumps to .Ltmp75
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp17-.Ltmp4 # Call between .Ltmp4 and .Ltmp17
.uleb128 .Ltmp20-.Lfunc_begin0 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp59-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp72-.Ltmp59 # Call between .Ltmp59 and .Ltmp72
.uleb128 .Ltmp75-.Lfunc_begin0 # jumps to .Ltmp75
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp19-.Ltmp18 # Call between .Ltmp18 and .Ltmp19
.uleb128 .Ltmp20-.Lfunc_begin0 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp73-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp74-.Ltmp73 # Call between .Ltmp73 and .Ltmp74
.uleb128 .Ltmp75-.Lfunc_begin0 # jumps to .Ltmp75
.byte 0 # On action: cleanup
.uleb128 .Ltmp74-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Lfunc_end1-.Ltmp74 # Call between .Ltmp74 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6sumOneiPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6sumOneiPiS_S_,@object # @_Z6sumOneiPiS_S_
.section .rodata,"a",@progbits
.globl _Z6sumOneiPiS_S_
.p2align 3, 0x0
_Z6sumOneiPiS_S_:
.quad _Z21__device_stub__sumOneiPiS_S_
.size _Z6sumOneiPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Couldn't read "
.size .L.str, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6sumOneiPiS_S_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__sumOneiPiS_S_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z6sumOneiPiS_S_
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6sumOneiPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B2, 0xed0 ; /* 0x00000e9000027945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R7, R0, c[0x0][0x0], R3 ; /* 0x0000000000077a24 */
/* 0x001fca00078e0203 */
/*0070*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x160], PT ; /* 0x0000580007007a0c */
/* 0x000fda0003f06270 */
/*0080*/ @P0 BRA 0xec0 ; /* 0x00000e3000000947 */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff047624 */
/* 0x000fe200078e00ff */
/*00a0*/ BSSY B1, 0xdf0 ; /* 0x00000d4000017945 */
/* 0x000fe60003800000 */
/*00b0*/ IMAD R4, R4, c[0x0][0xc], RZ ; /* 0x0000030004047a24 */
/* 0x000fc800078e02ff */
/*00c0*/ I2F.U32.RP R6, R4 ; /* 0x0000000400067306 */
/* 0x000e220000209000 */
/*00d0*/ IMAD.MOV R11, RZ, RZ, -R4 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a04 */
/*00e0*/ ISETP.NE.U32.AND P2, PT, R4.reuse, RZ, PT ; /* 0x000000ff0400720c */
/* 0x040fe20003f45070 */
/*00f0*/ IMAD.IADD R2, R4, 0x1, R7 ; /* 0x0000000104027824 */
/* 0x000fca00078e0207 */
/*0100*/ LOP3.LUT R5, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff057212 */
/* 0x000fc800078e33ff */
/*0110*/ IADD3 R5, R5, c[0x0][0x160], R4 ; /* 0x0000580005057a10 */
/* 0x000fe20007ffe004 */
/*0120*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0130*/ IADD3 R8, R6, 0xffffffe, RZ ; /* 0x0ffffffe06087810 */
/* 0x001fcc0007ffe0ff */
/*0140*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000064000021f000 */
/*0150*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fe400078e00ff */
/*0160*/ IMAD R11, R11, R9, RZ ; /* 0x000000090b0b7224 */
/* 0x002fc800078e02ff */
/*0170*/ IMAD.HI.U32 R2, R9, R11, R8 ; /* 0x0000000b09027227 */
/* 0x000fcc00078e0008 */
/*0180*/ IMAD.HI.U32 R2, R2, R5, RZ ; /* 0x0000000502027227 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.MOV R6, RZ, RZ, -R2 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a02 */
/*01a0*/ IMAD R5, R4, R6, R5 ; /* 0x0000000604057224 */
/* 0x000fca00078e0205 */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fda0003f06070 */
/*01c0*/ @P0 IMAD.IADD R5, R5, 0x1, -R4 ; /* 0x0000000105050824 */
/* 0x000fe200078e0a04 */
/*01d0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P1, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fda0003f26070 */
/*01f0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*0200*/ @!P2 LOP3.LUT R2, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff02a212 */
/* 0x000fc800078e33ff */
/*0210*/ ISETP.GE.U32.AND P0, PT, R2.reuse, 0x3, PT ; /* 0x000000030200780c */
/* 0x040fe40003f06070 */
/*0220*/ IADD3 R5, R2, 0x1, RZ ; /* 0x0000000102057810 */
/* 0x000fe20007ffe0ff */
/*0230*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fc600078e00ff */
/*0240*/ LOP3.LUT R6, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305067812 */
/* 0x000fce00078ec0ff */
/*0250*/ @!P0 BRA 0xde0 ; /* 0x00000b8000008947 */
/* 0x000fea0003800000 */
/*0260*/ IMAD.IADD R5, R5, 0x1, -R6 ; /* 0x0000000105057824 */
/* 0x000fe200078e0a06 */
/*0270*/ BSSY B0, 0xc40 ; /* 0x000009c000007945 */
/* 0x000fe20003800000 */
/*0280*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fc600078e00ff */
/*0290*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f04270 */
/*02a0*/ @!P0 BRA 0xc30 ; /* 0x0000098000008947 */
/* 0x000fea0003800000 */
/*02b0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe20003f24270 */
/*02c0*/ BSSY B3, 0x8d0 ; /* 0x0000060000037945 */
/* 0x000fe20003800000 */
/*02d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*02e0*/ @!P1 BRA 0x8c0 ; /* 0x000005d000009947 */
/* 0x000fea0003800000 */
/*02f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0300*/ IMAD.MOV.U32 R28, RZ, RZ, 0x4 ; /* 0x00000004ff1c7424 */
/* 0x000fc800078e00ff */
/*0310*/ IMAD.WIDE R12, R7, R28, c[0x0][0x168] ; /* 0x00005a00070c7625 */
/* 0x000fca00078e021c */
/*0320*/ LDG.E R8, [R12.64] ; /* 0x000000060c087981 */
/* 0x0000a2000c1e1900 */
/*0330*/ IMAD.WIDE R16, R4, 0x4, R12 ; /* 0x0000000404107825 */
/* 0x000fca00078e020c */
/*0340*/ LDG.E R9, [R16.64] ; /* 0x0000000610097981 */
/* 0x0002e2000c1e1900 */
/*0350*/ IMAD.WIDE R18, R4.reuse, 0x4, R16 ; /* 0x0000000404127825 */
/* 0x040fe200078e0210 */
/*0360*/ IADD3 R7, R4, R7, R4 ; /* 0x0000000704077210 */
/* 0x000fc80007ffe004 */
/*0370*/ LDG.E R10, [R18.64] ; /* 0x00000006120a7981 */
/* 0x000962000c1e1900 */
/*0380*/ IMAD.WIDE R20, R4.reuse, 0x4, R18 ; /* 0x0000000404147825 */
/* 0x040fe200078e0212 */
/*0390*/ IADD3 R27, R4, R7, R4 ; /* 0x00000007041b7210 */
/* 0x000fc80007ffe004 */
/*03a0*/ LDG.E R11, [R20.64] ; /* 0x00000006140b7981 */
/* 0x000162000c1e1900 */
/*03b0*/ IMAD.WIDE R22, R27, R28, c[0x0][0x168] ; /* 0x00005a001b167625 */
/* 0x000fca00078e021c */
/*03c0*/ LDG.E R7, [R22.64] ; /* 0x0000000616077981 */
/* 0x000162000c1e1900 */
/*03d0*/ IMAD.WIDE R14, R4, 0x4, R22 ; /* 0x00000004040e7825 */
/* 0x000fca00078e0216 */
/*03e0*/ LDG.E R25, [R14.64] ; /* 0x000000060e197981 */
/* 0x000162000c1e1900 */
/*03f0*/ IMAD.WIDE R16, R4.reuse, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x042fe200078e020e */
/*0400*/ IADD3 R27, R4, R27, R4 ; /* 0x0000001b041b7210 */
/* 0x000fc80007ffe004 */
/*0410*/ LDG.E R24, [R16.64] ; /* 0x0000000610187981 */
/* 0x000362000c1e1900 */
/*0420*/ IMAD.WIDE R18, R4.reuse, 0x4, R16 ; /* 0x0000000404127825 */
/* 0x050fe200078e0210 */
/*0430*/ IADD3 R29, R4, R27, R4 ; /* 0x0000001b041d7210 */
/* 0x000fc80007ffe004 */
/*0440*/ LDG.E R13, [R18.64] ; /* 0x00000006120d7981 */
/* 0x001122000c1e1900 */
/*0450*/ IMAD.WIDE R20, R29, R28, c[0x0][0x168] ; /* 0x00005a001d147625 */
/* 0x000fca00078e021c */
/*0460*/ LDG.E R12, [R20.64] ; /* 0x00000006140c7981 */
/* 0x000122000c1e1900 */
/*0470*/ IMAD.WIDE R22, R4, 0x4, R20 ; /* 0x0000000404167825 */
/* 0x000fca00078e0214 */
/*0480*/ LDG.E R26, [R22.64] ; /* 0x00000006161a7981 */
/* 0x000122000c1e1900 */
/*0490*/ IMAD.WIDE R14, R4.reuse, 0x4, R22 ; /* 0x00000004040e7825 */
/* 0x040fe200078e0216 */
/*04a0*/ IADD3 R29, R4, R29, R4 ; /* 0x0000001d041d7210 */
/* 0x000fc80007ffe004 */
/*04b0*/ LDG.E R27, [R14.64] ; /* 0x000000060e1b7981 */
/* 0x000122000c1e1900 */
/*04c0*/ IMAD.WIDE R16, R4.reuse, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x042fe200078e020e */
/*04d0*/ IADD3 R29, R4, R29, R4 ; /* 0x0000001d041d7210 */
/* 0x000fca0007ffe004 */
/*04e0*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000322000c1e1900 */
/*04f0*/ IMAD.WIDE R18, R29, R28, c[0x0][0x168] ; /* 0x00005a001d127625 */
/* 0x001fca00078e021c */
/*0500*/ LDG.E R28, [R18.64] ; /* 0x00000006121c7981 */
/* 0x000122000c1e1900 */
/*0510*/ IMAD.WIDE R20, R4, 0x4, R18 ; /* 0x0000000404147825 */
/* 0x000fca00078e0212 */
/*0520*/ LDG.E R17, [R20.64] ; /* 0x0000000614117981 */
/* 0x002f22000c1e1900 */
/*0530*/ IMAD.WIDE R22, R4, 0x4, R20 ; /* 0x0000000404167825 */
/* 0x000fca00078e0214 */
/*0540*/ LDG.E R18, [R22.64] ; /* 0x0000000616127981 */
/* 0x001f22000c1e1900 */
/*0550*/ IMAD.WIDE R14, R4, 0x4, R22 ; /* 0x00000004040e7825 */
/* 0x000fcc00078e0216 */
/*0560*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000f22000c1e1900 */
/*0570*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fe40007ffe0ff */
/*0580*/ ISETP.NE.AND P1, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x004fe40003f25270 */
/*0590*/ IADD3 R8, R2, 0x1, RZ ; /* 0x0000000102087810 */
/* 0x000fe40007ffe0ff */
/*05a0*/ ISETP.NE.AND P2, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x008fd20003f45270 */
/*05b0*/ @P1 IMAD.MOV R8, RZ, RZ, R2 ; /* 0x000000ffff081224 */
/* 0x000fe200078e0202 */
/*05c0*/ ISETP.NE.AND P1, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x020fc80003f25270 */
/*05d0*/ IADD3 R2, R8, 0x1, RZ ; /* 0x0000000108027810 */
/* 0x000fe20007ffe0ff */
/*05e0*/ @P2 IMAD.MOV R2, RZ, RZ, R8 ; /* 0x000000ffff022224 */
/* 0x000fe200078e0208 */
/*05f0*/ ISETP.NE.AND P2, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fc80003f45270 */
/*0600*/ IADD3 R8, R2, 0x1, RZ ; /* 0x0000000102087810 */
/* 0x000fc60007ffe0ff */
/*0610*/ @P1 IMAD.MOV R8, RZ, RZ, R2 ; /* 0x000000ffff081224 */
/* 0x000fe200078e0202 */
/*0620*/ ISETP.NE.AND P1, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fc80003f25270 */
/*0630*/ IADD3 R2, R8, 0x1, RZ ; /* 0x0000000108027810 */
/* 0x000fe20007ffe0ff */
/*0640*/ @P2 IMAD.MOV R2, RZ, RZ, R8 ; /* 0x000000ffff022224 */
/* 0x000fe200078e0208 */
/*0650*/ ISETP.NE.AND P2, PT, R25, 0x1, PT ; /* 0x000000011900780c */
/* 0x000fc80003f45270 */
/*0660*/ IADD3 R7, R2, 0x1, RZ ; /* 0x0000000102077810 */
/* 0x000fc60007ffe0ff */
/*0670*/ @P1 IMAD.MOV R7, RZ, RZ, R2 ; /* 0x000000ffff071224 */
/* 0x000fe200078e0202 */
/*0680*/ ISETP.NE.AND P1, PT, R24, 0x1, PT ; /* 0x000000011800780c */
/* 0x000fc80003f25270 */
/*0690*/ IADD3 R2, R7, 0x1, RZ ; /* 0x0000000107027810 */
/* 0x000fe20007ffe0ff */
/*06a0*/ @P2 IMAD.MOV R2, RZ, RZ, R7 ; /* 0x000000ffff022224 */
/* 0x000fe200078e0207 */
/*06b0*/ ISETP.NE.AND P2, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x010fc80003f45270 */
/*06c0*/ IADD3 R7, R2, 0x1, RZ ; /* 0x0000000102077810 */
/* 0x000fc60007ffe0ff */
/*06d0*/ @P1 IMAD.MOV R7, RZ, RZ, R2 ; /* 0x000000ffff071224 */
/* 0x000fe200078e0202 */
/*06e0*/ ISETP.NE.AND P1, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fc80003f25270 */
/*06f0*/ IADD3 R2, R7, 0x1, RZ ; /* 0x0000000107027810 */
/* 0x000fe20007ffe0ff */
/*0700*/ @P2 IMAD.MOV R2, RZ, RZ, R7 ; /* 0x000000ffff022224 */
/* 0x000fe200078e0207 */
/*0710*/ ISETP.NE.AND P2, PT, R26, 0x1, PT ; /* 0x000000011a00780c */
/* 0x000fc80003f45270 */
/*0720*/ IADD3 R7, R2, 0x1, RZ ; /* 0x0000000102077810 */
/* 0x000fc60007ffe0ff */
/*0730*/ @P1 IMAD.MOV R7, RZ, RZ, R2 ; /* 0x000000ffff071224 */
/* 0x000fe200078e0202 */
/*0740*/ ISETP.NE.AND P1, PT, R27, 0x1, PT ; /* 0x000000011b00780c */
/* 0x000fc80003f25270 */
/*0750*/ IADD3 R2, R7, 0x1, RZ ; /* 0x0000000107027810 */
/* 0x000fe20007ffe0ff */
/*0760*/ @P2 IMAD.MOV R2, RZ, RZ, R7 ; /* 0x000000ffff022224 */
/* 0x000fe200078e0207 */
/*0770*/ ISETP.NE.AND P2, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x000fc80003f45270 */
/*0780*/ IADD3 R7, R2, 0x1, RZ ; /* 0x0000000102077810 */
/* 0x000fc60007ffe0ff */
/*0790*/ @P1 IMAD.MOV R7, RZ, RZ, R2 ; /* 0x000000ffff071224 */
/* 0x000fe200078e0202 */
/*07a0*/ ISETP.NE.AND P1, PT, R28, 0x1, PT ; /* 0x000000011c00780c */
/* 0x000fc80003f25270 */
/*07b0*/ IADD3 R2, R7, 0x1, RZ ; /* 0x0000000107027810 */
/* 0x000fe20007ffe0ff */
/*07c0*/ @P2 IMAD.MOV R2, RZ, RZ, R7 ; /* 0x000000ffff022224 */
/* 0x000fe200078e0207 */
/*07d0*/ ISETP.NE.AND P2, PT, R17, 0x1, PT ; /* 0x000000011100780c */
/* 0x000fc80003f45270 */
/*07e0*/ IADD3 R7, R2, 0x1, RZ ; /* 0x0000000102077810 */
/* 0x000fc60007ffe0ff */
/*07f0*/ @P1 IMAD.MOV R7, RZ, RZ, R2 ; /* 0x000000ffff071224 */
/* 0x000fe200078e0202 */
/*0800*/ ISETP.NE.AND P1, PT, R18, 0x1, PT ; /* 0x000000011200780c */
/* 0x000fc80003f25270 */
/*0810*/ IADD3 R2, R7, 0x1, RZ ; /* 0x0000000107027810 */
/* 0x000fe20007ffe0ff */
/*0820*/ @P2 IMAD.MOV R2, RZ, RZ, R7 ; /* 0x000000ffff022224 */
/* 0x000fe200078e0207 */
/*0830*/ ISETP.NE.AND P2, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fe40003f45270 */
/*0840*/ IADD3 R7, R4, R29, R4.reuse ; /* 0x0000001d04077210 */
/* 0x100fe40007ffe004 */
/*0850*/ IADD3 R8, R2, 0x1, RZ ; /* 0x0000000102087810 */
/* 0x000fe40007ffe0ff */
/*0860*/ IADD3 R7, R4, R7, R4 ; /* 0x0000000704077210 */
/* 0x000fe20007ffe004 */
/*0870*/ @P1 IMAD.MOV R8, RZ, RZ, R2 ; /* 0x000000ffff081224 */
/* 0x000fe200078e0202 */
/*0880*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fc80003f24270 */
/*0890*/ IADD3 R2, R8, 0x1, RZ ; /* 0x0000000108027810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ @P2 IMAD.MOV R2, RZ, RZ, R8 ; /* 0x000000ffff022224 */
/* 0x000fd000078e0208 */
/*08b0*/ @P1 BRA 0x300 ; /* 0xfffffa4000001947 */
/* 0x000fea000383ffff */
/*08c0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*08d0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fe20003f24270 */
/*08e0*/ BSSY B3, 0xc00 ; /* 0x0000031000037945 */
/* 0x000fd80003800000 */
/*08f0*/ @!P1 BRA 0xbf0 ; /* 0x000002f000009947 */
/* 0x000fea0003800000 */
/*0900*/ IMAD.MOV.U32 R18, RZ, RZ, 0x4 ; /* 0x00000004ff127424 */
/* 0x000fc800078e00ff */
/*0910*/ IMAD.WIDE R10, R7, R18, c[0x0][0x168] ; /* 0x00005a00070a7625 */
/* 0x000fca00078e0212 */
/*0920*/ LDG.E R22, [R10.64] ; /* 0x000000060a167981 */
/* 0x0000a2000c1e1900 */
/*0930*/ IMAD.WIDE R12, R4, 0x4, R10 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020a */
/*0940*/ LDG.E R8, [R12.64] ; /* 0x000000060c087981 */
/* 0x0002e2000c1e1900 */
/*0950*/ IMAD.WIDE R14, R4.reuse, 0x4, R12 ; /* 0x00000004040e7825 */
/* 0x040fe200078e020c */
/*0960*/ IADD3 R7, R4, R7, R4 ; /* 0x0000000704077210 */
/* 0x000fc80007ffe004 */
/*0970*/ LDG.E R9, [R14.64] ; /* 0x000000060e097981 */
/* 0x000f22000c1e1900 */
/*0980*/ IMAD.WIDE R16, R4.reuse, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x040fe200078e020e */
/*0990*/ IADD3 R7, R4, R7, R4 ; /* 0x0000000704077210 */
/* 0x000fca0007ffe004 */
/*09a0*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000f62000c1e1900 */
/*09b0*/ IMAD.WIDE R18, R7, R18, c[0x0][0x168] ; /* 0x00005a0007127625 */
/* 0x000fca00078e0212 */
/*09c0*/ LDG.E R23, [R18.64] ; /* 0x0000000612177981 */
/* 0x000f62000c1e1900 */
/*09d0*/ IMAD.WIDE R20, R4, 0x4, R18 ; /* 0x0000000404147825 */
/* 0x000fca00078e0212 */
/*09e0*/ LDG.E R24, [R20.64] ; /* 0x0000000614187981 */
/* 0x000f62000c1e1900 */
/*09f0*/ IMAD.WIDE R10, R4, 0x4, R20 ; /* 0x00000004040a7825 */
/* 0x001fca00078e0214 */
/*0a00*/ LDG.E R25, [R10.64] ; /* 0x000000060a197981 */
/* 0x000f62000c1e1900 */
/*0a10*/ IMAD.WIDE R12, R4, 0x4, R10 ; /* 0x00000004040c7825 */
/* 0x002fcc00078e020a */
/*0a20*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000f62000c1e1900 */
/*0a30*/ IADD3 R7, R4.reuse, R7, R4.reuse ; /* 0x0000000704077210 */
/* 0x140fe40007ffe004 */
/*0a40*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe40007ffe0ff */
/*0a50*/ IADD3 R7, R4, R7, R4 ; /* 0x0000000704077210 */
/* 0x000fe40007ffe004 */
/*0a60*/ ISETP.NE.AND P0, PT, R22, 0x1, PT ; /* 0x000000011600780c */
/* 0x004fe40003f05270 */
/*0a70*/ ISETP.NE.AND P1, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x008fe40003f25270 */
/*0a80*/ IADD3 R8, R2, 0x1, RZ ; /* 0x0000000102087810 */
/* 0x000fd20007ffe0ff */
/*0a90*/ @P0 IMAD.MOV R8, RZ, RZ, R2 ; /* 0x000000ffff080224 */
/* 0x000fe200078e0202 */
/*0aa0*/ ISETP.NE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x010fc80003f05270 */
/*0ab0*/ IADD3 R2, R8, 0x1, RZ ; /* 0x0000000108027810 */
/* 0x000fe20007ffe0ff */
/*0ac0*/ @P1 IMAD.MOV R2, RZ, RZ, R8 ; /* 0x000000ffff021224 */
/* 0x000fe200078e0208 */
/*0ad0*/ ISETP.NE.AND P1, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x020fc80003f25270 */
/*0ae0*/ IADD3 R8, R2, 0x1, RZ ; /* 0x0000000102087810 */
/* 0x000fc60007ffe0ff */
/*0af0*/ @P0 IMAD.MOV R8, RZ, RZ, R2 ; /* 0x000000ffff080224 */
/* 0x000fe200078e0202 */
/*0b00*/ ISETP.NE.AND P0, PT, R23, 0x1, PT ; /* 0x000000011700780c */
/* 0x000fc80003f05270 */
/*0b10*/ IADD3 R2, R8, 0x1, RZ ; /* 0x0000000108027810 */
/* 0x000fe20007ffe0ff */
/*0b20*/ @P1 IMAD.MOV R2, RZ, RZ, R8 ; /* 0x000000ffff021224 */
/* 0x000fe200078e0208 */
/*0b30*/ ISETP.NE.AND P1, PT, R24, 0x1, PT ; /* 0x000000011800780c */
/* 0x000fc80003f25270 */
/*0b40*/ IADD3 R8, R2, 0x1, RZ ; /* 0x0000000102087810 */
/* 0x000fc60007ffe0ff */
/*0b50*/ @P0 IMAD.MOV R8, RZ, RZ, R2 ; /* 0x000000ffff080224 */
/* 0x000fe200078e0202 */
/*0b60*/ ISETP.NE.AND P0, PT, R25, 0x1, PT ; /* 0x000000011900780c */
/* 0x000fc80003f05270 */
/*0b70*/ IADD3 R2, R8, 0x1, RZ ; /* 0x0000000108027810 */
/* 0x000fe20007ffe0ff */
/*0b80*/ @P1 IMAD.MOV R2, RZ, RZ, R8 ; /* 0x000000ffff021224 */
/* 0x000fe200078e0208 */
/*0b90*/ ISETP.NE.AND P1, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fc80003f25270 */
/*0ba0*/ IADD3 R8, R2, 0x1, RZ ; /* 0x0000000102087810 */
/* 0x000fc60007ffe0ff */
/*0bb0*/ @P0 IMAD.MOV R8, RZ, RZ, R2 ; /* 0x000000ffff080224 */
/* 0x000fe200078e0202 */
/*0bc0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0e170 */
/*0bd0*/ IADD3 R2, R8, 0x1, RZ ; /* 0x0000000108027810 */
/* 0x000fe20007ffe0ff */
/*0be0*/ @P1 IMAD.MOV R2, RZ, RZ, R8 ; /* 0x000000ffff021224 */
/* 0x000fc600078e0208 */
/*0bf0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0c00*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0c10*/ @!P0 BREAK B0 ; /* 0x0000000000008942 */
/* 0x000fe20003800000 */
/*0c20*/ @!P0 BRA 0xde0 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0c30*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0c40*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fc800078e00ff */
/*0c50*/ IMAD.WIDE R8, R7, R8, c[0x0][0x168] ; /* 0x00005a0007087625 */
/* 0x000fca00078e0208 */
/*0c60*/ LDG.E R18, [R8.64] ; /* 0x0000000608127981 */
/* 0x000ea2000c1e1900 */
/*0c70*/ IMAD.WIDE R10, R4, 0x4, R8 ; /* 0x00000004040a7825 */
/* 0x000fca00078e0208 */
/*0c80*/ LDG.E R16, [R10.64] ; /* 0x000000060a107981 */
/* 0x000ee2000c1e1900 */
/*0c90*/ IMAD.WIDE R12, R4, 0x4, R10 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020a */
/*0ca0*/ LDG.E R17, [R12.64] ; /* 0x000000060c117981 */
/* 0x000f22000c1e1900 */
/*0cb0*/ IMAD.WIDE R14, R4, 0x4, R12 ; /* 0x00000004040e7825 */
/* 0x000fcc00078e020c */
/*0cc0*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000f62000c1e1900 */
/*0cd0*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fe40007ffe0ff */
/*0ce0*/ IADD3 R7, R4, R7, R4 ; /* 0x0000000704077210 */
/* 0x000fc80007ffe004 */
/*0cf0*/ IADD3 R7, R4, R7, R4 ; /* 0x0000000704077210 */
/* 0x000fe40007ffe004 */
/*0d00*/ ISETP.NE.AND P0, PT, R18, 0x1, PT ; /* 0x000000011200780c */
/* 0x004fe40003f05270 */
/*0d10*/ ISETP.NE.AND P1, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x008fe40003f25270 */
/*0d20*/ IADD3 R16, R2, 0x1, RZ ; /* 0x0000000102107810 */
/* 0x000fd20007ffe0ff */
/*0d30*/ @P0 IMAD.MOV R16, RZ, RZ, R2 ; /* 0x000000ffff100224 */
/* 0x000fe200078e0202 */
/*0d40*/ ISETP.NE.AND P0, PT, R17, 0x1, PT ; /* 0x000000011100780c */
/* 0x010fc80003f05270 */
/*0d50*/ IADD3 R2, R16, 0x1, RZ ; /* 0x0000000110027810 */
/* 0x000fe20007ffe0ff */
/*0d60*/ @P1 IMAD.MOV R2, RZ, RZ, R16 ; /* 0x000000ffff021224 */
/* 0x000fe200078e0210 */
/*0d70*/ ISETP.NE.AND P1, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x020fc80003f25270 */
/*0d80*/ IADD3 R8, R2, 0x1, RZ ; /* 0x0000000102087810 */
/* 0x000fc60007ffe0ff */
/*0d90*/ @P0 IMAD.MOV R8, RZ, RZ, R2 ; /* 0x000000ffff080224 */
/* 0x000fe200078e0202 */
/*0da0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc80003f05270 */
/*0db0*/ IADD3 R2, R8, 0x1, RZ ; /* 0x0000000108027810 */
/* 0x000fe20007ffe0ff */
/*0dc0*/ @P1 IMAD.MOV R2, RZ, RZ, R8 ; /* 0x000000ffff021224 */
/* 0x000fd000078e0208 */
/*0dd0*/ @P0 BRA 0xc40 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0de0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0df0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0e00*/ @!P0 BRA 0xec0 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0e10*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fc800078e00ff */
/*0e20*/ IMAD.WIDE R8, R7, R8, c[0x0][0x168] ; /* 0x00005a0007087625 */
/* 0x000fca00078e0208 */
/*0e30*/ LDG.E R5, [R8.64] ; /* 0x0000000608057981 */
/* 0x0000a2000c1e1900 */
/*0e40*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fc80007ffe0ff */
/*0e50*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f25270 */
/*0e60*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x001fe200078e0208 */
/*0e70*/ ISETP.NE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x004fe40003f05270 */
/*0e80*/ IADD3 R5, R2, 0x1, RZ ; /* 0x0000000102057810 */
/* 0x000fd60007ffe0ff */
/*0e90*/ @P0 IMAD.MOV R5, RZ, RZ, R2 ; /* 0x000000ffff050224 */
/* 0x000fc800078e0202 */
/*0ea0*/ IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0005 */
/*0eb0*/ @P1 BRA 0xe30 ; /* 0xffffff7000001947 */
/* 0x000fea000383ffff */
/*0ec0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0ed0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0ee0*/ S2R R4, SR_LANEID ; /* 0x0000000000047919 */
/* 0x000e220000000000 */
/*0ef0*/ REDUX.SUM UR5, R2 ; /* 0x00000000020573c4 */
/* 0x000e62000000c000 */
/*0f00*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*0f10*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0f20*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*0f30*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fca0003f05270 */
/*0f40*/ ISETP.EQ.U32.AND P1, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x001fe2000bf22070 */
/*0f50*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0005 */
/*0f60*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x002fd0000f8e00ff */
/*0f70*/ @P1 RED.E.ADD.STRONG.GPU [R4.64], R3 ; /* 0x000000030400198e */
/* 0x0001e8000c10e186 */
/*0f80*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0f90*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0fa0*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x001ea2000c1e1900 */
/*0fb0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fc400078e00ff */
/*0fc0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff037624 */
/* 0x000fca00078e00ff */
/*0fd0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x004fe2000c10e186 */
/*0fe0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ff0*/ BRA 0xff0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6sumOneiPiS_S_
.globl _Z6sumOneiPiS_S_
.p2align 8
.type _Z6sumOneiPiS_S_,@function
_Z6sumOneiPiS_S_:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b32 s5, s[0:1], 0x0
s_add_u32 s2, s0, 32
s_mov_b32 s4, s15
s_addc_u32 s3, s1, 0
v_mov_b32_e32 v4, 0
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s4, s6, v[0:1]
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_4
s_load_b32 s7, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s6, s7, s6
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_ashr_i32 s7, s6, 31
s_mov_b32 s3, 0
s_lshl_b64 s[8:9], s[6:7], 2
.LBB0_2:
global_load_b32 v5, v[2:3], off
v_add_nc_u32_e32 v1, s6, v1
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, s5, v1
s_or_b32 s3, vcc_lo, s3
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s2, 1, v5
v_add_co_ci_u32_e64 v4, s2, 0, v4, s2
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s3
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
s_mov_b32 s2, exec_lo
s_mov_b32 s6, 0
.LBB0_5:
s_ctz_i32_b32 s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s5, v4, s3
s_lshl_b32 s3, 1, s3
s_and_not1_b32 s2, s2, s3
s_delay_alu instid0(VALU_DEP_1)
s_add_i32 s6, s6, s5
s_cmp_lg_u32 s2, 0
s_cbranch_scc1 .LBB0_5
s_load_b64 s[2:3], s[0:1], 0x10
s_mov_b32 s5, 0
v_mbcnt_lo_u32_b32 v1, exec_lo, 0
s_lshl_b64 s[4:5], s[4:5], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s4
s_addc_u32 s3, s3, s5
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v1
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s6
global_atomic_add_u32 v1, v2, s[2:3]
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_11
s_mov_b32 s4, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v0, s4, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 s5, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s5
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x18
global_load_b32 v1, v0, s[2:3]
s_bcnt1_i32_b32 s2, s4
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v1, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6sumOneiPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6sumOneiPiS_S_, .Lfunc_end0-_Z6sumOneiPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6sumOneiPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6sumOneiPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013445c_00000000-6_Homework2_1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3902:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3902:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6sumOneiPiS_S_iPiS_S_
.type _Z30__device_stub__Z6sumOneiPiS_S_iPiS_S_, @function
_Z30__device_stub__Z6sumOneiPiS_S_iPiS_S_:
.LFB3924:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6sumOneiPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3924:
.size _Z30__device_stub__Z6sumOneiPiS_S_iPiS_S_, .-_Z30__device_stub__Z6sumOneiPiS_S_iPiS_S_
.globl _Z6sumOneiPiS_S_
.type _Z6sumOneiPiS_S_, @function
_Z6sumOneiPiS_S_:
.LFB3925:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6sumOneiPiS_S_iPiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3925:
.size _Z6sumOneiPiS_S_, .-_Z6sumOneiPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6sumOneiPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3927:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6sumOneiPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3927:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC1:
.string "Couldn't read "
.text
.globl main
.type main, @function
main:
.LFB3899:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3899
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $600, %rsp
.cfi_def_cfa_offset 640
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 584(%rsp)
xorl %eax, %eax
leaq 64(%rsp), %rbp
movq %rbp, %rdi
.LEHB0:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE0:
movq 8(%rbx), %rsi
movl $8, %edx
movq %rbp, %rdi
.LEHB1:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
leaq 184(%rsp), %rdi
call _ZNKSt12__basic_fileIcE7is_openEv@PLT
testb %al, %al
je .L26
leaq 4(%rsp), %rsi
leaq 64(%rsp), %rdi
call _ZNSirsERi@PLT
jmp .L27
.L26:
leaq .LC1(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 8(%rbx), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L15
.L27:
movq %rax, %rdi
leaq 8(%rsp), %rsi
call _ZNSirsERi@PLT
movl 4(%rsp), %r13d
imull 8(%rsp), %r13d
movslq %r13d, %rbp
salq $2, %rbp
leaq 16(%rsp), %rdi
movl $1, %edx
movq %rbp, %rsi
call cudaMallocManaged@PLT
testl %r13d, %r13d
jle .L16
movl $0, %ebx
leaq 64(%rsp), %r12
jmp .L17
.L28:
addq $4, %rbx
cmpq %rbx, %rbp
je .L16
.L17:
movq %rbx, %rsi
addq 16(%rsp), %rsi
movq %r12, %rdi
call _ZNSirsERi@PLT
jmp .L28
.L16:
leaq 64(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
leal 255(%r13), %eax
movl $256, %ecx
cltd
idivl %ecx
movl %eax, %ebx
movslq %eax, %r12
salq $2, %r12
leaq 24(%rsp), %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
leaq 32(%rsp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
movl $-1, 12(%rsp)
leaq 12(%rsp), %rdi
call cudaGetDevice@PLT
movl $0, %ecx
movl 12(%rsp), %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $0, %ecx
movl 12(%rsp), %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $0, %ecx
movl 12(%rsp), %edx
movl $4, %esi
movq 32(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $256, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %ebx, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L18
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movl %r13d, %edi
call _Z30__device_stub__Z6sumOneiPiS_S_iPiS_S_
.L18:
call cudaDeviceSynchronize@PLT
movq 32(%rsp), %rax
movl (%rax), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
.LEHE1:
.L15:
leaq 64(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 584(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $600, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 584(%rsp), %rax
subq %fs:40, %rax
je .L20
call __stack_chk_fail@PLT
.L20:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3899:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3899:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3899-.LLSDACSB3899
.LLSDACSB3899:
.uleb128 .LEHB0-.LFB3899
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3899
.uleb128 .LEHE1-.LEHB1
.uleb128 .L22-.LFB3899
.uleb128 0
.uleb128 .LEHB2-.LFB3899
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE3899:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Homework2_1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__sumOneiPiS_S_ # -- Begin function _Z21__device_stub__sumOneiPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__sumOneiPiS_S_,@function
_Z21__device_stub__sumOneiPiS_S_: # @_Z21__device_stub__sumOneiPiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6sumOneiPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__sumOneiPiS_S_, .Lfunc_end0-_Z21__device_stub__sumOneiPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $680, %rsp # imm = 0x2A8
.cfi_def_cfa_offset 736
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
.cfi_escape 0x2e, 0x00
leaq 160(%rsp), %r15
movq %r15, %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev
movq 8(%rbx), %rsi
leaq 176(%rsp), %r14
.Ltmp0:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $8, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.1: # %.noexc
movq 160(%rsp), %rcx
addq -24(%rcx), %r15
xorl %esi, %esi
testq %rax, %rax
jne .LBB1_3
# %bb.2:
movl 32(%r15), %esi
orl $4, %esi
.LBB1_3: # %.invoke
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp3:
# %bb.4: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
leaq 280(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNKSt12__basic_fileIcE7is_openEv
testb %al, %al
je .LBB1_5
# %bb.18:
.Ltmp21:
.cfi_escape 0x2e, 0x00
leaq 160(%rsp), %rdi
leaq 48(%rsp), %rsi
callq _ZNSirsERi
.Ltmp22:
# %bb.19:
.Ltmp23:
.cfi_escape 0x2e, 0x00
leaq 44(%rsp), %rsi
movq %rax, %rdi
callq _ZNSirsERi
.Ltmp24:
# %bb.20:
movslq 48(%rsp), %rax
movslq 44(%rsp), %r12
imulq %rax, %r12
leaq (,%r12,4), %rbx
.Ltmp26:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movq %rbx, %rsi
movl $1, %edx
callq hipMallocManaged
.Ltmp27:
# %bb.21: # %_ZL16hipMallocManagedIiE10hipError_tPPT_mj.exit.preheader
testl %r12d, %r12d
jle .LBB1_25
# %bb.22: # %.lr.ph.preheader
movl %r12d, %r13d
shlq $2, %r13
xorl %ebp, %ebp
leaq 160(%rsp), %r15
.p2align 4, 0x90
.LBB1_23: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq 24(%rsp), %rsi
addq %rbp, %rsi
.Ltmp28:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNSirsERi
.Ltmp29:
# %bb.24: # %_ZL16hipMallocManagedIiE10hipError_tPPT_mj.exit
# in Loop: Header=BB1_23 Depth=1
addq $4, %rbp
cmpq %rbp, %r13
jne .LBB1_23
.LBB1_25: # %_ZL16hipMallocManagedIiE10hipError_tPPT_mj.exit._crit_edge
.Ltmp31:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp32:
# %bb.26: # %.noexc42
testq %rax, %rax
jne .LBB1_28
# %bb.27:
movq 160(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $160, %rdi
movl 192(%rsp,%rax), %esi
orl $4, %esi
.Ltmp33:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp34:
.LBB1_28: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv.exit
.cfi_escape 0x2e, 0x00
callq _ZNSt6chrono3_V212system_clock3nowEv
leal 255(%r12), %eax
leal 510(%r12), %ebp
testl %eax, %eax
cmovnsl %eax, %ebp
sarl $8, %ebp
movslq %ebp, %r14
shlq $2, %r14
.Ltmp36:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
movq %r14, %rsi
movl $1, %edx
callq hipMallocManaged
.Ltmp37:
# %bb.29: # %_ZL16hipMallocManagedIiE10hipError_tPPT_mj.exit45
.Ltmp38:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
.Ltmp39:
# %bb.30: # %_ZL16hipMallocManagedIiE10hipError_tPPT_mj.exit47
movl $-1, 12(%rsp)
.Ltmp41:
.cfi_escape 0x2e, 0x00
leaq 12(%rsp), %rdi
callq hipGetDevice
.Ltmp42:
# %bb.31:
movq 24(%rsp), %rdi
movl 12(%rsp), %edx
.Ltmp43:
.cfi_escape 0x2e, 0x00
movq %rbx, %rsi
xorl %ecx, %ecx
callq hipMemPrefetchAsync
.Ltmp44:
# %bb.32:
movq 32(%rsp), %rdi
movl 12(%rsp), %edx
.Ltmp45:
.cfi_escape 0x2e, 0x00
movq %r14, %rsi
xorl %ecx, %ecx
callq hipMemPrefetchAsync
.Ltmp46:
# %bb.33:
movq 16(%rsp), %rdi
movl 12(%rsp), %edx
.Ltmp47:
.cfi_escape 0x2e, 0x00
movl $4, %esi
xorl %ecx, %ecx
callq hipMemPrefetchAsync
.Ltmp48:
# %bb.34:
movl %ebp, %eax
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rax, %rdi
.Ltmp49:
.cfi_escape 0x2e, 0x00
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp50:
# %bb.35:
testl %eax, %eax
jne .LBB1_38
# %bb.36:
movq 24(%rsp), %rax
movq 32(%rsp), %rcx
movq 16(%rsp), %rdx
movl %r12d, 52(%rsp)
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 52(%rsp), %rax
movq %rax, 128(%rsp)
leaq 120(%rsp), %rax
movq %rax, 136(%rsp)
leaq 112(%rsp), %rax
movq %rax, 144(%rsp)
leaq 104(%rsp), %rax
movq %rax, 152(%rsp)
.Ltmp51:
.cfi_escape 0x2e, 0x00
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp52:
# %bb.37: # %.noexc48
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
.Ltmp53:
.cfi_escape 0x2e, 0x10
leaq 128(%rsp), %r9
movl $_Z6sumOneiPiS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp54:
.LBB1_38:
.Ltmp55:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp56:
# %bb.39:
movq 16(%rsp), %rax
movl (%rax), %esi
.Ltmp57:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSolsEi
.Ltmp58:
# %bb.40:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_41
# %bb.48: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i58
cmpb $0, 56(%r14)
je .LBB1_50
# %bb.49:
movzbl 67(%r14), %eax
jmp .LBB1_52
.LBB1_5:
.Ltmp4:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp5:
# %bb.6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq 8(%rbx), %rbx
testq %rbx, %rbx
je .LBB1_7
# %bb.8:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq strlen
.Ltmp6:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp7:
jmp .LBB1_9
.LBB1_7:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
.Ltmp8:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp9:
.LBB1_9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit38
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_10
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_14
# %bb.13:
movzbl 67(%rbx), %eax
jmp .LBB1_16
.LBB1_14:
.Ltmp10:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp11:
# %bb.15: # %.noexc53
movq (%rbx), %rax
.Ltmp12:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp13:
.LBB1_16: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp14:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
.Ltmp15:
# %bb.17: # %.noexc55
.Ltmp16:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp17:
jmp .LBB1_57
.LBB1_50:
.Ltmp59:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp60:
# %bb.51: # %.noexc63
movq (%r14), %rax
.Ltmp61:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp62:
.LBB1_52: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i60
.Ltmp63:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp64:
# %bb.53: # %.noexc65
.Ltmp65:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp66:
# %bb.54: # %_ZNSolsEPFRSoS_E.exit51
movq 24(%rsp), %rdi
.Ltmp67:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp68:
# %bb.55:
movq 32(%rsp), %rdi
.Ltmp69:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp70:
# %bb.56:
movq 16(%rsp), %rdi
.Ltmp71:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp72:
.LBB1_57: # %_ZNSolsEPFRSoS_E.exit
.cfi_escape 0x2e, 0x00
leaq 160(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 416(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
xorl %eax, %eax
addq $680, %rsp # imm = 0x2A8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_10:
.cfi_def_cfa_offset 736
.Ltmp18:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp19:
# %bb.11: # %.noexc52
.LBB1_41:
.Ltmp73:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp74:
# %bb.47: # %.noexc62
.LBB1_45:
.Ltmp40:
jmp .LBB1_59
.LBB1_42:
.Ltmp25:
jmp .LBB1_59
.LBB1_43:
.Ltmp35:
jmp .LBB1_59
.LBB1_58:
.Ltmp20:
jmp .LBB1_59
.LBB1_46:
.Ltmp75:
jmp .LBB1_59
.LBB1_44:
.Ltmp30:
.LBB1_59:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 160(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 416(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp20-.Lfunc_begin0 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp24-.Ltmp21 # Call between .Ltmp21 and .Ltmp24
.uleb128 .Ltmp25-.Lfunc_begin0 # jumps to .Ltmp25
.byte 0 # On action: cleanup
.uleb128 .Ltmp26-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp27-.Ltmp26 # Call between .Ltmp26 and .Ltmp27
.uleb128 .Ltmp35-.Lfunc_begin0 # jumps to .Ltmp35
.byte 0 # On action: cleanup
.uleb128 .Ltmp28-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp29-.Ltmp28 # Call between .Ltmp28 and .Ltmp29
.uleb128 .Ltmp30-.Lfunc_begin0 # jumps to .Ltmp30
.byte 0 # On action: cleanup
.uleb128 .Ltmp31-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp34-.Ltmp31 # Call between .Ltmp31 and .Ltmp34
.uleb128 .Ltmp35-.Lfunc_begin0 # jumps to .Ltmp35
.byte 0 # On action: cleanup
.uleb128 .Ltmp36-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp39-.Ltmp36 # Call between .Ltmp36 and .Ltmp39
.uleb128 .Ltmp40-.Lfunc_begin0 # jumps to .Ltmp40
.byte 0 # On action: cleanup
.uleb128 .Ltmp41-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp58-.Ltmp41 # Call between .Ltmp41 and .Ltmp58
.uleb128 .Ltmp75-.Lfunc_begin0 # jumps to .Ltmp75
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp17-.Ltmp4 # Call between .Ltmp4 and .Ltmp17
.uleb128 .Ltmp20-.Lfunc_begin0 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp59-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp72-.Ltmp59 # Call between .Ltmp59 and .Ltmp72
.uleb128 .Ltmp75-.Lfunc_begin0 # jumps to .Ltmp75
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp19-.Ltmp18 # Call between .Ltmp18 and .Ltmp19
.uleb128 .Ltmp20-.Lfunc_begin0 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp73-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp74-.Ltmp73 # Call between .Ltmp73 and .Ltmp74
.uleb128 .Ltmp75-.Lfunc_begin0 # jumps to .Ltmp75
.byte 0 # On action: cleanup
.uleb128 .Ltmp74-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Lfunc_end1-.Ltmp74 # Call between .Ltmp74 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6sumOneiPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6sumOneiPiS_S_,@object # @_Z6sumOneiPiS_S_
.section .rodata,"a",@progbits
.globl _Z6sumOneiPiS_S_
.p2align 3, 0x0
_Z6sumOneiPiS_S_:
.quad _Z21__device_stub__sumOneiPiS_S_
.size _Z6sumOneiPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Couldn't read "
.size .L.str, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6sumOneiPiS_S_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__sumOneiPiS_S_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z6sumOneiPiS_S_
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void kGauss( double * Y, const double * x, const double * w, const int K )
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
double y = Y[idx];
Y[idx]=0;
for(int i=0; i<K; ++i)
Y[idx] += w[i]*exp(-(y-x[i])*(y-x[i]));
} | code for sm_80
Function : _Z6kGaussPdPKdS1_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0030*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fc600078e00ff */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fc800078e0203 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*0090*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000168000c1e1b00 */
/*00a0*/ STG.E.64 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x0001e2000c101b04 */
/*00b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00c0*/ ISETP.NE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f05270 */
/*00d0*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fe2000001ff00 */
/*00e0*/ CS2R R22, SRZ ; /* 0x0000000000167805 */
/* 0x000fd6000001ff00 */
/*00f0*/ @!P0 BRA 0x710 ; /* 0x0000061000008947 */
/* 0x000fea0003800000 */
/*0100*/ LOP3.LUT R0, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100007812 */
/* 0x000fe200078ec0ff */
/*0110*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fe200078e00ff */
/*0120*/ CS2R R22, SRZ ; /* 0x0000000000167805 */
/* 0x000fe4000001ff00 */
/*0130*/ IADD3 R0, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000007a10 */
/* 0x000fe40007ffe1ff */
/*0140*/ IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b7424 */
/* 0x000fc800078e00ff */
/*0150*/ IMAD.WIDE R8, R20, R11, c[0x0][0x168] ; /* 0x00005a0014087625 */
/* 0x000fca00078e020b */
/*0160*/ LDG.E.64 R16, [R8.64] ; /* 0x0000000408107981 */
/* 0x000ea2000c1e1b00 */
/*0170*/ IMAD.WIDE R10, R20, R11, c[0x0][0x170] ; /* 0x00005c00140a7625 */
/* 0x000fca00078e020b */
/*0180*/ LDG.E.64 R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x022362000c1e1b00 */
/*0190*/ IMAD.MOV.U32 R12, RZ, RZ, 0x652b82fe ; /* 0x652b82feff0c7424 */
/* 0x000fe200078e00ff */
/*01a0*/ BSSY B0, 0x420 ; /* 0x0000027000007945 */
/* 0x000fe20003800000 */
/*01b0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff0d7424 */
/* 0x000fe200078e00ff */
/*01c0*/ DADD R16, R6, -R16 ; /* 0x0000000006107229 */
/* 0x004e8c0000000810 */
/*01d0*/ DMUL R16, R16, R16 ; /* 0x0000001010107228 */
/* 0x004e8c0000000000 */
/*01e0*/ DFMA R14, -R16, R12, 6.75539944105574400000e+15 ; /* 0x43380000100e742b */
/* 0x004e8c000000010c */
/*01f0*/ DADD R24, R14, -6.75539944105574400000e+15 ; /* 0xc33800000e187429 */
/* 0x004e8c0000000000 */
/*0200*/ DFMA R2, R24, c[0x2][0x0], -R16 ; /* 0x0080000018027a2b */
/* 0x004e8c0000000810 */
/*0210*/ DFMA R24, R24, c[0x2][0x8], R2 ; /* 0x0080020018187a2b */
/* 0x0044e40000000002 */
/*0220*/ IMAD.MOV.U32 R2, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff027424 */
/* 0x004fe400078e00ff */
/*0230*/ IMAD.MOV.U32 R3, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff037424 */
/* 0x000fcc00078e00ff */
/*0240*/ DFMA R26, R24, R2, c[0x2][0x10] ; /* 0x00800400181a762b */
/* 0x008e8c0000000002 */
/*0250*/ DFMA R26, R24, R26, c[0x2][0x18] ; /* 0x00800600181a762b */
/* 0x004e8c000000001a */
/*0260*/ DFMA R26, R24, R26, c[0x2][0x20] ; /* 0x00800800181a762b */
/* 0x004e8c000000001a */
/*0270*/ DFMA R26, R24, R26, c[0x2][0x28] ; /* 0x00800a00181a762b */
/* 0x004e8c000000001a */
/*0280*/ DFMA R26, R24, R26, c[0x2][0x30] ; /* 0x00800c00181a762b */
/* 0x004e8c000000001a */
/*0290*/ DFMA R26, R24, R26, c[0x2][0x38] ; /* 0x00800e00181a762b */
/* 0x004e8c000000001a */
/*02a0*/ DFMA R26, R24, R26, c[0x2][0x40] ; /* 0x00801000181a762b */
/* 0x004e8c000000001a */
/*02b0*/ DFMA R26, R24, R26, c[0x2][0x48] ; /* 0x00801200181a762b */
/* 0x004e8c000000001a */
/*02c0*/ DFMA R26, R24, R26, c[0x2][0x50] ; /* 0x00801400181a762b */
/* 0x004e8c000000001a */
/*02d0*/ DFMA R26, R24, R26, 1 ; /* 0x3ff00000181a742b */
/* 0x004e8c000000001a */
/*02e0*/ DFMA R24, R24, R26, 1 ; /* 0x3ff000001818742b */
/* 0x004fc8000000001a */
/*02f0*/ DADD R26, -RZ, -R16 ; /* 0x00000000ff1a7229 */
/* 0x000e8c0000000910 */
/*0300*/ IMAD.MOV.U32 R26, RZ, RZ, R24 ; /* 0x000000ffff1a7224 */
/* 0x004fc800078e0018 */
/*0310*/ IMAD.MOV.U32 R21, RZ, RZ, R27 ; /* 0x000000ffff157224 */
/* 0x000fe400078e001b */
/*0320*/ IMAD R27, R14, 0x100000, R25 ; /* 0x001000000e1b7824 */
/* 0x000fc600078e0219 */
/*0330*/ FSETP.GEU.AND P0, PT, |R21|, 4.1917929649353027344, PT ; /* 0x4086232b1500780b */
/* 0x000fda0003f0e200 */
/*0340*/ @!P0 BRA 0x410 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0350*/ FSETP.GEU.AND P1, PT, |R21|, 4.2275390625, PT ; /* 0x408748001500780b */
/* 0x002fe20003f2e200 */
/*0360*/ DSETP.GT.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000722a */
/* 0x000fc80003f04000 */
/*0370*/ DADD R16, -R16, +INF ; /* 0x7ff0000010107429 */
/* 0x000e500000000100 */
/*0380*/ @!P1 LEA.HI R15, R14, R14, RZ, 0x1 ; /* 0x0000000e0e0f9211 */
/* 0x000fe400078f08ff */
/*0390*/ FSEL R26, R16, RZ, !P0 ; /* 0x000000ff101a7208 */
/* 0x002fe40004000000 */
/*03a0*/ @!P1 SHF.R.S32.HI R15, RZ, 0x1, R15 ; /* 0x00000001ff0f9819 */
/* 0x000fe4000001140f */
/*03b0*/ FSEL R27, R17, RZ, !P0 ; /* 0x000000ff111b7208 */
/* 0x000fc60004000000 */
/*03c0*/ @!P1 IMAD.IADD R14, R14, 0x1, -R15 ; /* 0x000000010e0e9824 */
/* 0x000fe400078e0a0f */
/*03d0*/ @!P1 IMAD R25, R15, 0x100000, R25 ; /* 0x001000000f199824 */
/* 0x000fc600078e0219 */
/*03e0*/ @!P1 LEA R15, R14, 0x3ff00000, 0x14 ; /* 0x3ff000000e0f9811 */
/* 0x000fe200078ea0ff */
/*03f0*/ @!P1 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e9224 */
/* 0x000fcc00078e00ff */
/*0400*/ @!P1 DMUL R26, R24, R14 ; /* 0x0000000e181a9228 */
/* 0x00028c0000000000 */
/*0410*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0420*/ DFMA R18, R18, R26, R22 ; /* 0x0000001a1212722b */
/* 0x024e4e0000000016 */
/*0430*/ STG.E.64 [R4.64], R18 ; /* 0x0000001204007986 */
/* 0x0023e8000c101b04 */
/*0440*/ LDG.E.64 R8, [R8.64+0x8] ; /* 0x0000080408087981 */
/* 0x000ea8000c1e1b00 */
/*0450*/ LDG.E.64 R10, [R10.64+0x8] ; /* 0x000008040a0a7981 */
/* 0x000f62000c1e1b00 */
/*0460*/ IADD3 R0, R0, -0x2, RZ ; /* 0xfffffffe00007810 */
/* 0x000fe20007ffe0ff */
/*0470*/ BSSY B0, 0x6c0 ; /* 0x0000024000007945 */
/* 0x000fe60003800000 */
/*0480*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0490*/ DADD R14, R6, -R8 ; /* 0x00000000060e7229 */
/* 0x004e8c0000000808 */
/*04a0*/ DMUL R14, R14, R14 ; /* 0x0000000e0e0e7228 */
/* 0x004e8c0000000000 */
/*04b0*/ DFMA R12, -R14, R12, 6.75539944105574400000e+15 ; /* 0x433800000e0c742b */
/* 0x004e88000000010c */
/*04c0*/ DADD R8, -RZ, -R14 ; /* 0x00000000ff087229 */
/* 0x000fc8000000090e */
/*04d0*/ DADD R16, R12, -6.75539944105574400000e+15 ; /* 0xc33800000c107429 */
/* 0x004e8c0000000000 */
/*04e0*/ DFMA R22, R16, c[0x2][0x0], -R14 ; /* 0x0080000010167a2b */
/* 0x004ea2000000080e */
/*04f0*/ FSETP.GEU.AND P1, PT, |R9|, 4.1917929649353027344, PT ; /* 0x4086232b0900780b */
/* 0x000fca0003f2e200 */
/*0500*/ DFMA R16, R16, c[0x2][0x8], R22 ; /* 0x0080020010107a2b */
/* 0x004e8c0000000016 */
/*0510*/ DFMA R2, R16, R2, c[0x2][0x10] ; /* 0x008004001002762b */
/* 0x004e8c0000000002 */
/*0520*/ DFMA R2, R16, R2, c[0x2][0x18] ; /* 0x008006001002762b */
/* 0x004e8c0000000002 */
/*0530*/ DFMA R2, R16, R2, c[0x2][0x20] ; /* 0x008008001002762b */
/* 0x004e8c0000000002 */
/*0540*/ DFMA R2, R16, R2, c[0x2][0x28] ; /* 0x00800a001002762b */
/* 0x004e8c0000000002 */
/*0550*/ DFMA R2, R16, R2, c[0x2][0x30] ; /* 0x00800c001002762b */
/* 0x004e8c0000000002 */
/*0560*/ DFMA R2, R16, R2, c[0x2][0x38] ; /* 0x00800e001002762b */
/* 0x004e8c0000000002 */
/*0570*/ DFMA R2, R16, R2, c[0x2][0x40] ; /* 0x008010001002762b */
/* 0x004e8c0000000002 */
/*0580*/ DFMA R2, R16, R2, c[0x2][0x48] ; /* 0x008012001002762b */
/* 0x004e8c0000000002 */
/*0590*/ DFMA R2, R16, R2, c[0x2][0x50] ; /* 0x008014001002762b */
/* 0x004e8c0000000002 */
/*05a0*/ DFMA R2, R16, R2, 1 ; /* 0x3ff000001002742b */
/* 0x004e8c0000000002 */
/*05b0*/ DFMA R16, R16, R2, 1 ; /* 0x3ff000001010742b */
/* 0x004e940000000002 */
/*05c0*/ IMAD R23, R12, 0x100000, R17 ; /* 0x001000000c177824 */
/* 0x004fe200078e0211 */
/*05d0*/ MOV R22, R16 ; /* 0x0000001000167202 */
/* 0x000fe20000000f00 */
/*05e0*/ @!P1 BRA 0x6b0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*05f0*/ FSETP.GEU.AND P2, PT, |R9|, 4.2275390625, PT ; /* 0x408748000900780b */
/* 0x002fe20003f4e200 */
/*0600*/ DADD R8, -R14, +INF ; /* 0x7ff000000e087429 */
/* 0x000fc80000000100 */
/*0610*/ DSETP.GT.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00722a */
/* 0x000e4c0003f24000 */
/*0620*/ FSEL R22, R8, RZ, !P1 ; /* 0x000000ff08167208 */
/* 0x002fe40004800000 */
/*0630*/ @!P2 LEA.HI R2, R12, R12, RZ, 0x1 ; /* 0x0000000c0c02a211 */
/* 0x000fe400078f08ff */
/*0640*/ FSEL R23, R9, RZ, !P1 ; /* 0x000000ff09177208 */
/* 0x000fe40004800000 */
/*0650*/ @!P2 SHF.R.S32.HI R3, RZ, 0x1, R2 ; /* 0x00000001ff03a819 */
/* 0x000fca0000011402 */
/*0660*/ @!P2 IMAD.IADD R2, R12, 0x1, -R3 ; /* 0x000000010c02a824 */
/* 0x000fe400078e0a03 */
/*0670*/ @!P2 IMAD R17, R3, 0x100000, R17 ; /* 0x001000000311a824 */
/* 0x000fc600078e0211 */
/*0680*/ @!P2 LEA R3, R2, 0x3ff00000, 0x14 ; /* 0x3ff000000203a811 */
/* 0x000fe200078ea0ff */
/*0690*/ @!P2 IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff02a224 */
/* 0x000fcc00078e00ff */
/*06a0*/ @!P2 DMUL R22, R16, R2 ; /* 0x000000021016a228 */
/* 0x00028c0000000000 */
/*06b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*06c0*/ DFMA R22, R10, R22, R18 ; /* 0x000000160a16722b */
/* 0x024e620000000012 */
/*06d0*/ IADD3 R20, R20, 0x2, RZ ; /* 0x0000000214147810 */
/* 0x000fcc0007ffe0ff */
/*06e0*/ STG.E.64 [R4.64], R22 ; /* 0x0000001604007986 */
/* 0x0023e2000c101b04 */
/*06f0*/ @P0 BRA 0x140 ; /* 0xfffffa4000000947 */
/* 0x000fea000383ffff */
/*0700*/ SHF.R.S32.HI R21, RZ, 0x1f, R20 ; /* 0x0000001fff157819 */
/* 0x000fe40000011414 */
/*0710*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fca00078e00ff */
/*0720*/ LOP3.LUT P0, RZ, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100ff7812 */
/* 0x000fda000780c0ff */
/*0730*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0740*/ IMAD.SHL.U32 R2, R20.reuse, 0x8, RZ ; /* 0x0000000814027824 */
/* 0x040fe200078e00ff */
/*0750*/ SHF.L.U64.HI R20, R20, 0x3, R21 ; /* 0x0000000314147819 */
/* 0x000fc80000010215 */
/*0760*/ IADD3 R14, P0, R2, c[0x0][0x168], RZ ; /* 0x00005a00020e7a10 */
/* 0x000fc80007f1e0ff */
/*0770*/ IADD3.X R15, R20, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b00140f7a10 */
/* 0x000fca00007fe4ff */
/*0780*/ LDG.E.64 R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000ea2000c1e1b00 */
/*0790*/ IADD3 R2, P0, R2, c[0x0][0x170], RZ ; /* 0x00005c0002027a10 */
/* 0x000fc80007f1e0ff */
/*07a0*/ IADD3.X R3, R20, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0014037a10 */
/* 0x000fcc00007fe4ff */
/*07b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000f62000c1e1b00 */
/*07c0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff107424 */
/* 0x000fe200078e00ff */
/*07d0*/ MOV R17, 0x3e5ade15 ; /* 0x3e5ade1500117802 */
/* 0x000fe20000000f00 */
/*07e0*/ BSSY B0, 0xa50 ; /* 0x0000026000007945 */
/* 0x000fe20003800000 */
/*07f0*/ DADD R6, R6, -R8 ; /* 0x0000000006067229 */
/* 0x0244e40000000808 */
/*0800*/ IMAD.MOV.U32 R8, RZ, RZ, 0x652b82fe ; /* 0x652b82feff087424 */
/* 0x004fe400078e00ff */
/*0810*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff097424 */
/* 0x000fe400078e00ff */
/*0820*/ DMUL R6, R6, R6 ; /* 0x0000000606067228 */
/* 0x008e8c0000000000 */
/*0830*/ DFMA R8, -R6, R8, 6.75539944105574400000e+15 ; /* 0x433800000608742b */
/* 0x004e880000000108 */
/*0840*/ DADD R14, -RZ, -R6 ; /* 0x00000000ff0e7229 */
/* 0x000fc80000000906 */
/*0850*/ DADD R10, R8, -6.75539944105574400000e+15 ; /* 0xc3380000080a7429 */
/* 0x004e8c0000000000 */
/*0860*/ DFMA R12, R10, c[0x2][0x0], -R6 ; /* 0x008000000a0c7a2b */
/* 0x004ea20000000806 */
/*0870*/ FSETP.GEU.AND P0, PT, |R15|, 4.1917929649353027344, PT ; /* 0x4086232b0f00780b */
/* 0x000fca0003f0e200 */
/*0880*/ DFMA R10, R10, c[0x2][0x8], R12 ; /* 0x008002000a0a7a2b */
/* 0x004e8c000000000c */
/*0890*/ DFMA R12, R10, R16, c[0x2][0x10] ; /* 0x008004000a0c762b */
/* 0x004e8c0000000010 */
/*08a0*/ DFMA R12, R10, R12, c[0x2][0x18] ; /* 0x008006000a0c762b */
/* 0x004e8c000000000c */
/*08b0*/ DFMA R12, R10, R12, c[0x2][0x20] ; /* 0x008008000a0c762b */
/* 0x004e8c000000000c */
/*08c0*/ DFMA R12, R10, R12, c[0x2][0x28] ; /* 0x00800a000a0c762b */
/* 0x004e8c000000000c */
/*08d0*/ DFMA R12, R10, R12, c[0x2][0x30] ; /* 0x00800c000a0c762b */
/* 0x004e8c000000000c */
/*08e0*/ DFMA R12, R10, R12, c[0x2][0x38] ; /* 0x00800e000a0c762b */
/* 0x004e8c000000000c */
/*08f0*/ DFMA R12, R10, R12, c[0x2][0x40] ; /* 0x008010000a0c762b */
/* 0x004e8c000000000c */
/*0900*/ DFMA R12, R10, R12, c[0x2][0x48] ; /* 0x008012000a0c762b */
/* 0x004e8c000000000c */
/*0910*/ DFMA R12, R10, R12, c[0x2][0x50] ; /* 0x008014000a0c762b */
/* 0x004e8c000000000c */
/*0920*/ DFMA R12, R10, R12, 1 ; /* 0x3ff000000a0c742b */
/* 0x004e8c000000000c */
/*0930*/ DFMA R12, R10, R12, 1 ; /* 0x3ff000000a0c742b */
/* 0x004e94000000000c */
/*0940*/ IMAD R11, R8, 0x100000, R13 ; /* 0x00100000080b7824 */
/* 0x004fe400078e020d */
/*0950*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e000c */
/*0960*/ @!P0 BRA 0xa40 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0970*/ FSETP.GEU.AND P1, PT, |R15|, 4.2275390625, PT ; /* 0x408748000f00780b */
/* 0x000fe20003f2e200 */
/*0980*/ DADD R10, -R6, +INF ; /* 0x7ff00000060a7429 */
/* 0x000fc80000000100 */
/*0990*/ DSETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600722a */
/* 0x000e8c0003f04000 */
/*09a0*/ FSEL R10, R10, RZ, !P0 ; /* 0x000000ff0a0a7208 */
/* 0x004fe40004000000 */
/*09b0*/ @!P1 LEA.HI R0, R8, R8, RZ, 0x1 ; /* 0x0000000808009211 */
/* 0x000fe200078f08ff */
/*09c0*/ @!P1 IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff069224 */
/* 0x000fe200078e000c */
/*09d0*/ FSEL R11, R11, RZ, !P0 ; /* 0x000000ff0b0b7208 */
/* 0x000fe40004000000 */
/*09e0*/ @!P1 SHF.R.S32.HI R7, RZ, 0x1, R0 ; /* 0x00000001ff079819 */
/* 0x000fca0000011400 */
/*09f0*/ @!P1 IMAD.IADD R8, R8, 0x1, -R7 ; /* 0x0000000108089824 */
/* 0x000fe400078e0a07 */
/*0a00*/ @!P1 IMAD R7, R7, 0x100000, R13 ; /* 0x0010000007079824 */
/* 0x000fc600078e020d */
/*0a10*/ @!P1 LEA R9, R8, 0x3ff00000, 0x14 ; /* 0x3ff0000008099811 */
/* 0x000fe200078ea0ff */
/*0a20*/ @!P1 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff089224 */
/* 0x000fcc00078e00ff */
/*0a30*/ @!P1 DMUL R10, R6, R8 ; /* 0x00000008060a9228 */
/* 0x0004cc0000000000 */
/*0a40*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a50*/ DFMA R2, R2, R10, R22 ; /* 0x0000000a0202722b */
/* 0x008ece0000000016 */
/*0a60*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x008fe2000c101b04 */
/*0a70*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a80*/ BRA 0xa80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void kGauss( double * Y, const double * x, const double * w, const int K )
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
double y = Y[idx];
Y[idx]=0;
for(int i=0; i<K; ++i)
Y[idx] += w[i]*exp(-(y-x[i])*(y-x[i]));
} | .file "tmpxft_001a04c2_00000000-6_simpleEx.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z6kGaussPdPKdS1_iPdPKdS1_i
.type _Z32__device_stub__Z6kGaussPdPKdS1_iPdPKdS1_i, @function
_Z32__device_stub__Z6kGaussPdPKdS1_iPdPKdS1_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kGaussPdPKdS1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z6kGaussPdPKdS1_iPdPKdS1_i, .-_Z32__device_stub__Z6kGaussPdPKdS1_iPdPKdS1_i
.globl _Z6kGaussPdPKdS1_i
.type _Z6kGaussPdPKdS1_i, @function
_Z6kGaussPdPKdS1_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6kGaussPdPKdS1_iPdPKdS1_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6kGaussPdPKdS1_i, .-_Z6kGaussPdPKdS1_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kGaussPdPKdS1_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kGaussPdPKdS1_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void kGauss( double * Y, const double * x, const double * w, const int K )
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
double y = Y[idx];
Y[idx]=0;
for(int i=0; i<K; ++i)
Y[idx] += w[i]*exp(-(y-x[i])*(y-x[i]));
} | #include <hip/hip_runtime.h>
__global__ void kGauss( double * Y, const double * x, const double * w, const int K )
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
double y = Y[idx];
Y[idx]=0;
for(int i=0; i<K; ++i)
Y[idx] += w[i]*exp(-(y-x[i])*(y-x[i]));
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void kGauss( double * Y, const double * x, const double * w, const int K )
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
double y = Y[idx];
Y[idx]=0;
for(int i=0; i<K; ++i)
Y[idx] += w[i]*exp(-(y-x[i])*(y-x[i]));
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kGaussPdPKdS1_i
.globl _Z6kGaussPdPKdS1_i
.p2align 8
.type _Z6kGaussPdPKdS1_i,@function
_Z6kGaussPdPKdS1_i:
s_load_b32 s2, s[0:1], 0x2c
v_mov_b32_e32 v4, 0
s_load_b32 s33, s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v5, v4
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_cmp_lt_i32 s33, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[0:1], off
global_store_b64 v[0:1], v[4:5], off
s_cbranch_scc1 .LBB0_3
global_load_b64 v[4:5], v[0:1], off
s_load_b128 s[4:7], s[0:1], 0x8
v_mov_b32_e32 v6, 0
s_mov_b32 s3, 0x3ff71547
s_mov_b32 s2, 0x652b82fe
s_mov_b32 s9, 0xbfe62e42
s_mov_b32 s8, 0xfefa39ef
s_mov_b32 s11, 0xbc7abc9e
s_mov_b32 s10, 0x3b39803f
s_mov_b32 s13, 0x3e928af3
s_mov_b32 s12, 0xfca7ab0c
s_mov_b32 s15, 0x3e5ade15
s_mov_b32 s14, 0x6a5dcb37
s_mov_b32 s17, 0x3ec71dee
s_mov_b32 s16, 0x623fde64
s_mov_b32 s19, 0x3efa0199
s_mov_b32 s18, 0x7c89e6b0
s_mov_b32 s21, 0x3f2a01a0
s_mov_b32 s20, 0x14761f6e
s_mov_b32 s23, 0x3f56c16c
s_mov_b32 s22, 0x1852b7b0
s_mov_b32 s25, 0x3f811111
s_mov_b32 s24, 0x11122322
s_mov_b32 s27, 0x3fa55555
s_mov_b32 s26, 0x555502a1
s_mov_b32 s29, 0x3fc55555
s_mov_b32 s28, 0x55555511
s_mov_b32 s31, 0x3fe00000
s_mov_b32 s30, 11
.LBB0_2:
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[7:8], v6, s[4:5]
global_load_b64 v[9:10], v6, s[6:7]
s_add_i32 s33, s33, -1
s_waitcnt vmcnt(1)
v_add_f64 v[7:8], v[2:3], -v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[7:8], v[7:8], -v[7:8]
v_mul_f64 v[11:12], v[7:8], s[2:3]
v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[7:8]
v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[7:8]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[11:12], v[11:12]
v_fma_f64 v[13:14], v[11:12], s[8:9], v[7:8]
v_cvt_i32_f64_e32 v17, v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[11:12], s[10:11], v[13:14]
v_fma_f64 v[15:16], v[13:14], s[14:15], s[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[16:17]
v_fma_f64 v[15:16], v[13:14], v[15:16], s[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[20:21]
v_fma_f64 v[15:16], v[13:14], v[15:16], s[22:23]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[24:25]
v_fma_f64 v[15:16], v[13:14], v[15:16], s[26:27]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[28:29]
v_fma_f64 v[15:16], v[13:14], v[15:16], s[30:31]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], 1.0
v_fma_f64 v[11:12], v[13:14], v[15:16], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[11:12], v[11:12], v17
v_cndmask_b32_e32 v12, 0x7ff00000, v12, vcc_lo
s_and_b32 vcc_lo, s0, vcc_lo
s_add_u32 s6, s6, 8
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v7, 0, v11, vcc_lo
s_addc_u32 s7, s7, 0
v_cndmask_b32_e64 v8, 0, v12, s0
s_add_u32 s4, s4, 8
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s33, 0
s_waitcnt vmcnt(0)
v_fma_f64 v[4:5], v[9:10], v[7:8], v[4:5]
global_store_b64 v[0:1], v[4:5], off
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kGaussPdPKdS1_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 34
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kGaussPdPKdS1_i, .Lfunc_end0-_Z6kGaussPdPKdS1_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kGaussPdPKdS1_i
.private_segment_fixed_size: 0
.sgpr_count: 36
.sgpr_spill_count: 0
.symbol: _Z6kGaussPdPKdS1_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void kGauss( double * Y, const double * x, const double * w, const int K )
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
double y = Y[idx];
Y[idx]=0;
for(int i=0; i<K; ++i)
Y[idx] += w[i]*exp(-(y-x[i])*(y-x[i]));
} | .text
.file "simpleEx.hip"
.globl _Z21__device_stub__kGaussPdPKdS1_i # -- Begin function _Z21__device_stub__kGaussPdPKdS1_i
.p2align 4, 0x90
.type _Z21__device_stub__kGaussPdPKdS1_i,@function
_Z21__device_stub__kGaussPdPKdS1_i: # @_Z21__device_stub__kGaussPdPKdS1_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kGaussPdPKdS1_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__kGaussPdPKdS1_i, .Lfunc_end0-_Z21__device_stub__kGaussPdPKdS1_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kGaussPdPKdS1_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kGaussPdPKdS1_i,@object # @_Z6kGaussPdPKdS1_i
.section .rodata,"a",@progbits
.globl _Z6kGaussPdPKdS1_i
.p2align 3, 0x0
_Z6kGaussPdPKdS1_i:
.quad _Z21__device_stub__kGaussPdPKdS1_i
.size _Z6kGaussPdPKdS1_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kGaussPdPKdS1_i"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kGaussPdPKdS1_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kGaussPdPKdS1_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kGaussPdPKdS1_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0030*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fc600078e00ff */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fc800078e0203 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*0090*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000168000c1e1b00 */
/*00a0*/ STG.E.64 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x0001e2000c101b04 */
/*00b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00c0*/ ISETP.NE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f05270 */
/*00d0*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fe2000001ff00 */
/*00e0*/ CS2R R22, SRZ ; /* 0x0000000000167805 */
/* 0x000fd6000001ff00 */
/*00f0*/ @!P0 BRA 0x710 ; /* 0x0000061000008947 */
/* 0x000fea0003800000 */
/*0100*/ LOP3.LUT R0, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100007812 */
/* 0x000fe200078ec0ff */
/*0110*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fe200078e00ff */
/*0120*/ CS2R R22, SRZ ; /* 0x0000000000167805 */
/* 0x000fe4000001ff00 */
/*0130*/ IADD3 R0, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000007a10 */
/* 0x000fe40007ffe1ff */
/*0140*/ IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b7424 */
/* 0x000fc800078e00ff */
/*0150*/ IMAD.WIDE R8, R20, R11, c[0x0][0x168] ; /* 0x00005a0014087625 */
/* 0x000fca00078e020b */
/*0160*/ LDG.E.64 R16, [R8.64] ; /* 0x0000000408107981 */
/* 0x000ea2000c1e1b00 */
/*0170*/ IMAD.WIDE R10, R20, R11, c[0x0][0x170] ; /* 0x00005c00140a7625 */
/* 0x000fca00078e020b */
/*0180*/ LDG.E.64 R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x022362000c1e1b00 */
/*0190*/ IMAD.MOV.U32 R12, RZ, RZ, 0x652b82fe ; /* 0x652b82feff0c7424 */
/* 0x000fe200078e00ff */
/*01a0*/ BSSY B0, 0x420 ; /* 0x0000027000007945 */
/* 0x000fe20003800000 */
/*01b0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff0d7424 */
/* 0x000fe200078e00ff */
/*01c0*/ DADD R16, R6, -R16 ; /* 0x0000000006107229 */
/* 0x004e8c0000000810 */
/*01d0*/ DMUL R16, R16, R16 ; /* 0x0000001010107228 */
/* 0x004e8c0000000000 */
/*01e0*/ DFMA R14, -R16, R12, 6.75539944105574400000e+15 ; /* 0x43380000100e742b */
/* 0x004e8c000000010c */
/*01f0*/ DADD R24, R14, -6.75539944105574400000e+15 ; /* 0xc33800000e187429 */
/* 0x004e8c0000000000 */
/*0200*/ DFMA R2, R24, c[0x2][0x0], -R16 ; /* 0x0080000018027a2b */
/* 0x004e8c0000000810 */
/*0210*/ DFMA R24, R24, c[0x2][0x8], R2 ; /* 0x0080020018187a2b */
/* 0x0044e40000000002 */
/*0220*/ IMAD.MOV.U32 R2, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff027424 */
/* 0x004fe400078e00ff */
/*0230*/ IMAD.MOV.U32 R3, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff037424 */
/* 0x000fcc00078e00ff */
/*0240*/ DFMA R26, R24, R2, c[0x2][0x10] ; /* 0x00800400181a762b */
/* 0x008e8c0000000002 */
/*0250*/ DFMA R26, R24, R26, c[0x2][0x18] ; /* 0x00800600181a762b */
/* 0x004e8c000000001a */
/*0260*/ DFMA R26, R24, R26, c[0x2][0x20] ; /* 0x00800800181a762b */
/* 0x004e8c000000001a */
/*0270*/ DFMA R26, R24, R26, c[0x2][0x28] ; /* 0x00800a00181a762b */
/* 0x004e8c000000001a */
/*0280*/ DFMA R26, R24, R26, c[0x2][0x30] ; /* 0x00800c00181a762b */
/* 0x004e8c000000001a */
/*0290*/ DFMA R26, R24, R26, c[0x2][0x38] ; /* 0x00800e00181a762b */
/* 0x004e8c000000001a */
/*02a0*/ DFMA R26, R24, R26, c[0x2][0x40] ; /* 0x00801000181a762b */
/* 0x004e8c000000001a */
/*02b0*/ DFMA R26, R24, R26, c[0x2][0x48] ; /* 0x00801200181a762b */
/* 0x004e8c000000001a */
/*02c0*/ DFMA R26, R24, R26, c[0x2][0x50] ; /* 0x00801400181a762b */
/* 0x004e8c000000001a */
/*02d0*/ DFMA R26, R24, R26, 1 ; /* 0x3ff00000181a742b */
/* 0x004e8c000000001a */
/*02e0*/ DFMA R24, R24, R26, 1 ; /* 0x3ff000001818742b */
/* 0x004fc8000000001a */
/*02f0*/ DADD R26, -RZ, -R16 ; /* 0x00000000ff1a7229 */
/* 0x000e8c0000000910 */
/*0300*/ IMAD.MOV.U32 R26, RZ, RZ, R24 ; /* 0x000000ffff1a7224 */
/* 0x004fc800078e0018 */
/*0310*/ IMAD.MOV.U32 R21, RZ, RZ, R27 ; /* 0x000000ffff157224 */
/* 0x000fe400078e001b */
/*0320*/ IMAD R27, R14, 0x100000, R25 ; /* 0x001000000e1b7824 */
/* 0x000fc600078e0219 */
/*0330*/ FSETP.GEU.AND P0, PT, |R21|, 4.1917929649353027344, PT ; /* 0x4086232b1500780b */
/* 0x000fda0003f0e200 */
/*0340*/ @!P0 BRA 0x410 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0350*/ FSETP.GEU.AND P1, PT, |R21|, 4.2275390625, PT ; /* 0x408748001500780b */
/* 0x002fe20003f2e200 */
/*0360*/ DSETP.GT.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000722a */
/* 0x000fc80003f04000 */
/*0370*/ DADD R16, -R16, +INF ; /* 0x7ff0000010107429 */
/* 0x000e500000000100 */
/*0380*/ @!P1 LEA.HI R15, R14, R14, RZ, 0x1 ; /* 0x0000000e0e0f9211 */
/* 0x000fe400078f08ff */
/*0390*/ FSEL R26, R16, RZ, !P0 ; /* 0x000000ff101a7208 */
/* 0x002fe40004000000 */
/*03a0*/ @!P1 SHF.R.S32.HI R15, RZ, 0x1, R15 ; /* 0x00000001ff0f9819 */
/* 0x000fe4000001140f */
/*03b0*/ FSEL R27, R17, RZ, !P0 ; /* 0x000000ff111b7208 */
/* 0x000fc60004000000 */
/*03c0*/ @!P1 IMAD.IADD R14, R14, 0x1, -R15 ; /* 0x000000010e0e9824 */
/* 0x000fe400078e0a0f */
/*03d0*/ @!P1 IMAD R25, R15, 0x100000, R25 ; /* 0x001000000f199824 */
/* 0x000fc600078e0219 */
/*03e0*/ @!P1 LEA R15, R14, 0x3ff00000, 0x14 ; /* 0x3ff000000e0f9811 */
/* 0x000fe200078ea0ff */
/*03f0*/ @!P1 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e9224 */
/* 0x000fcc00078e00ff */
/*0400*/ @!P1 DMUL R26, R24, R14 ; /* 0x0000000e181a9228 */
/* 0x00028c0000000000 */
/*0410*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0420*/ DFMA R18, R18, R26, R22 ; /* 0x0000001a1212722b */
/* 0x024e4e0000000016 */
/*0430*/ STG.E.64 [R4.64], R18 ; /* 0x0000001204007986 */
/* 0x0023e8000c101b04 */
/*0440*/ LDG.E.64 R8, [R8.64+0x8] ; /* 0x0000080408087981 */
/* 0x000ea8000c1e1b00 */
/*0450*/ LDG.E.64 R10, [R10.64+0x8] ; /* 0x000008040a0a7981 */
/* 0x000f62000c1e1b00 */
/*0460*/ IADD3 R0, R0, -0x2, RZ ; /* 0xfffffffe00007810 */
/* 0x000fe20007ffe0ff */
/*0470*/ BSSY B0, 0x6c0 ; /* 0x0000024000007945 */
/* 0x000fe60003800000 */
/*0480*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0490*/ DADD R14, R6, -R8 ; /* 0x00000000060e7229 */
/* 0x004e8c0000000808 */
/*04a0*/ DMUL R14, R14, R14 ; /* 0x0000000e0e0e7228 */
/* 0x004e8c0000000000 */
/*04b0*/ DFMA R12, -R14, R12, 6.75539944105574400000e+15 ; /* 0x433800000e0c742b */
/* 0x004e88000000010c */
/*04c0*/ DADD R8, -RZ, -R14 ; /* 0x00000000ff087229 */
/* 0x000fc8000000090e */
/*04d0*/ DADD R16, R12, -6.75539944105574400000e+15 ; /* 0xc33800000c107429 */
/* 0x004e8c0000000000 */
/*04e0*/ DFMA R22, R16, c[0x2][0x0], -R14 ; /* 0x0080000010167a2b */
/* 0x004ea2000000080e */
/*04f0*/ FSETP.GEU.AND P1, PT, |R9|, 4.1917929649353027344, PT ; /* 0x4086232b0900780b */
/* 0x000fca0003f2e200 */
/*0500*/ DFMA R16, R16, c[0x2][0x8], R22 ; /* 0x0080020010107a2b */
/* 0x004e8c0000000016 */
/*0510*/ DFMA R2, R16, R2, c[0x2][0x10] ; /* 0x008004001002762b */
/* 0x004e8c0000000002 */
/*0520*/ DFMA R2, R16, R2, c[0x2][0x18] ; /* 0x008006001002762b */
/* 0x004e8c0000000002 */
/*0530*/ DFMA R2, R16, R2, c[0x2][0x20] ; /* 0x008008001002762b */
/* 0x004e8c0000000002 */
/*0540*/ DFMA R2, R16, R2, c[0x2][0x28] ; /* 0x00800a001002762b */
/* 0x004e8c0000000002 */
/*0550*/ DFMA R2, R16, R2, c[0x2][0x30] ; /* 0x00800c001002762b */
/* 0x004e8c0000000002 */
/*0560*/ DFMA R2, R16, R2, c[0x2][0x38] ; /* 0x00800e001002762b */
/* 0x004e8c0000000002 */
/*0570*/ DFMA R2, R16, R2, c[0x2][0x40] ; /* 0x008010001002762b */
/* 0x004e8c0000000002 */
/*0580*/ DFMA R2, R16, R2, c[0x2][0x48] ; /* 0x008012001002762b */
/* 0x004e8c0000000002 */
/*0590*/ DFMA R2, R16, R2, c[0x2][0x50] ; /* 0x008014001002762b */
/* 0x004e8c0000000002 */
/*05a0*/ DFMA R2, R16, R2, 1 ; /* 0x3ff000001002742b */
/* 0x004e8c0000000002 */
/*05b0*/ DFMA R16, R16, R2, 1 ; /* 0x3ff000001010742b */
/* 0x004e940000000002 */
/*05c0*/ IMAD R23, R12, 0x100000, R17 ; /* 0x001000000c177824 */
/* 0x004fe200078e0211 */
/*05d0*/ MOV R22, R16 ; /* 0x0000001000167202 */
/* 0x000fe20000000f00 */
/*05e0*/ @!P1 BRA 0x6b0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*05f0*/ FSETP.GEU.AND P2, PT, |R9|, 4.2275390625, PT ; /* 0x408748000900780b */
/* 0x002fe20003f4e200 */
/*0600*/ DADD R8, -R14, +INF ; /* 0x7ff000000e087429 */
/* 0x000fc80000000100 */
/*0610*/ DSETP.GT.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00722a */
/* 0x000e4c0003f24000 */
/*0620*/ FSEL R22, R8, RZ, !P1 ; /* 0x000000ff08167208 */
/* 0x002fe40004800000 */
/*0630*/ @!P2 LEA.HI R2, R12, R12, RZ, 0x1 ; /* 0x0000000c0c02a211 */
/* 0x000fe400078f08ff */
/*0640*/ FSEL R23, R9, RZ, !P1 ; /* 0x000000ff09177208 */
/* 0x000fe40004800000 */
/*0650*/ @!P2 SHF.R.S32.HI R3, RZ, 0x1, R2 ; /* 0x00000001ff03a819 */
/* 0x000fca0000011402 */
/*0660*/ @!P2 IMAD.IADD R2, R12, 0x1, -R3 ; /* 0x000000010c02a824 */
/* 0x000fe400078e0a03 */
/*0670*/ @!P2 IMAD R17, R3, 0x100000, R17 ; /* 0x001000000311a824 */
/* 0x000fc600078e0211 */
/*0680*/ @!P2 LEA R3, R2, 0x3ff00000, 0x14 ; /* 0x3ff000000203a811 */
/* 0x000fe200078ea0ff */
/*0690*/ @!P2 IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff02a224 */
/* 0x000fcc00078e00ff */
/*06a0*/ @!P2 DMUL R22, R16, R2 ; /* 0x000000021016a228 */
/* 0x00028c0000000000 */
/*06b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*06c0*/ DFMA R22, R10, R22, R18 ; /* 0x000000160a16722b */
/* 0x024e620000000012 */
/*06d0*/ IADD3 R20, R20, 0x2, RZ ; /* 0x0000000214147810 */
/* 0x000fcc0007ffe0ff */
/*06e0*/ STG.E.64 [R4.64], R22 ; /* 0x0000001604007986 */
/* 0x0023e2000c101b04 */
/*06f0*/ @P0 BRA 0x140 ; /* 0xfffffa4000000947 */
/* 0x000fea000383ffff */
/*0700*/ SHF.R.S32.HI R21, RZ, 0x1f, R20 ; /* 0x0000001fff157819 */
/* 0x000fe40000011414 */
/*0710*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fca00078e00ff */
/*0720*/ LOP3.LUT P0, RZ, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100ff7812 */
/* 0x000fda000780c0ff */
/*0730*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0740*/ IMAD.SHL.U32 R2, R20.reuse, 0x8, RZ ; /* 0x0000000814027824 */
/* 0x040fe200078e00ff */
/*0750*/ SHF.L.U64.HI R20, R20, 0x3, R21 ; /* 0x0000000314147819 */
/* 0x000fc80000010215 */
/*0760*/ IADD3 R14, P0, R2, c[0x0][0x168], RZ ; /* 0x00005a00020e7a10 */
/* 0x000fc80007f1e0ff */
/*0770*/ IADD3.X R15, R20, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b00140f7a10 */
/* 0x000fca00007fe4ff */
/*0780*/ LDG.E.64 R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000ea2000c1e1b00 */
/*0790*/ IADD3 R2, P0, R2, c[0x0][0x170], RZ ; /* 0x00005c0002027a10 */
/* 0x000fc80007f1e0ff */
/*07a0*/ IADD3.X R3, R20, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0014037a10 */
/* 0x000fcc00007fe4ff */
/*07b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000f62000c1e1b00 */
/*07c0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff107424 */
/* 0x000fe200078e00ff */
/*07d0*/ MOV R17, 0x3e5ade15 ; /* 0x3e5ade1500117802 */
/* 0x000fe20000000f00 */
/*07e0*/ BSSY B0, 0xa50 ; /* 0x0000026000007945 */
/* 0x000fe20003800000 */
/*07f0*/ DADD R6, R6, -R8 ; /* 0x0000000006067229 */
/* 0x0244e40000000808 */
/*0800*/ IMAD.MOV.U32 R8, RZ, RZ, 0x652b82fe ; /* 0x652b82feff087424 */
/* 0x004fe400078e00ff */
/*0810*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff097424 */
/* 0x000fe400078e00ff */
/*0820*/ DMUL R6, R6, R6 ; /* 0x0000000606067228 */
/* 0x008e8c0000000000 */
/*0830*/ DFMA R8, -R6, R8, 6.75539944105574400000e+15 ; /* 0x433800000608742b */
/* 0x004e880000000108 */
/*0840*/ DADD R14, -RZ, -R6 ; /* 0x00000000ff0e7229 */
/* 0x000fc80000000906 */
/*0850*/ DADD R10, R8, -6.75539944105574400000e+15 ; /* 0xc3380000080a7429 */
/* 0x004e8c0000000000 */
/*0860*/ DFMA R12, R10, c[0x2][0x0], -R6 ; /* 0x008000000a0c7a2b */
/* 0x004ea20000000806 */
/*0870*/ FSETP.GEU.AND P0, PT, |R15|, 4.1917929649353027344, PT ; /* 0x4086232b0f00780b */
/* 0x000fca0003f0e200 */
/*0880*/ DFMA R10, R10, c[0x2][0x8], R12 ; /* 0x008002000a0a7a2b */
/* 0x004e8c000000000c */
/*0890*/ DFMA R12, R10, R16, c[0x2][0x10] ; /* 0x008004000a0c762b */
/* 0x004e8c0000000010 */
/*08a0*/ DFMA R12, R10, R12, c[0x2][0x18] ; /* 0x008006000a0c762b */
/* 0x004e8c000000000c */
/*08b0*/ DFMA R12, R10, R12, c[0x2][0x20] ; /* 0x008008000a0c762b */
/* 0x004e8c000000000c */
/*08c0*/ DFMA R12, R10, R12, c[0x2][0x28] ; /* 0x00800a000a0c762b */
/* 0x004e8c000000000c */
/*08d0*/ DFMA R12, R10, R12, c[0x2][0x30] ; /* 0x00800c000a0c762b */
/* 0x004e8c000000000c */
/*08e0*/ DFMA R12, R10, R12, c[0x2][0x38] ; /* 0x00800e000a0c762b */
/* 0x004e8c000000000c */
/*08f0*/ DFMA R12, R10, R12, c[0x2][0x40] ; /* 0x008010000a0c762b */
/* 0x004e8c000000000c */
/*0900*/ DFMA R12, R10, R12, c[0x2][0x48] ; /* 0x008012000a0c762b */
/* 0x004e8c000000000c */
/*0910*/ DFMA R12, R10, R12, c[0x2][0x50] ; /* 0x008014000a0c762b */
/* 0x004e8c000000000c */
/*0920*/ DFMA R12, R10, R12, 1 ; /* 0x3ff000000a0c742b */
/* 0x004e8c000000000c */
/*0930*/ DFMA R12, R10, R12, 1 ; /* 0x3ff000000a0c742b */
/* 0x004e94000000000c */
/*0940*/ IMAD R11, R8, 0x100000, R13 ; /* 0x00100000080b7824 */
/* 0x004fe400078e020d */
/*0950*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e000c */
/*0960*/ @!P0 BRA 0xa40 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0970*/ FSETP.GEU.AND P1, PT, |R15|, 4.2275390625, PT ; /* 0x408748000f00780b */
/* 0x000fe20003f2e200 */
/*0980*/ DADD R10, -R6, +INF ; /* 0x7ff00000060a7429 */
/* 0x000fc80000000100 */
/*0990*/ DSETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600722a */
/* 0x000e8c0003f04000 */
/*09a0*/ FSEL R10, R10, RZ, !P0 ; /* 0x000000ff0a0a7208 */
/* 0x004fe40004000000 */
/*09b0*/ @!P1 LEA.HI R0, R8, R8, RZ, 0x1 ; /* 0x0000000808009211 */
/* 0x000fe200078f08ff */
/*09c0*/ @!P1 IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff069224 */
/* 0x000fe200078e000c */
/*09d0*/ FSEL R11, R11, RZ, !P0 ; /* 0x000000ff0b0b7208 */
/* 0x000fe40004000000 */
/*09e0*/ @!P1 SHF.R.S32.HI R7, RZ, 0x1, R0 ; /* 0x00000001ff079819 */
/* 0x000fca0000011400 */
/*09f0*/ @!P1 IMAD.IADD R8, R8, 0x1, -R7 ; /* 0x0000000108089824 */
/* 0x000fe400078e0a07 */
/*0a00*/ @!P1 IMAD R7, R7, 0x100000, R13 ; /* 0x0010000007079824 */
/* 0x000fc600078e020d */
/*0a10*/ @!P1 LEA R9, R8, 0x3ff00000, 0x14 ; /* 0x3ff0000008099811 */
/* 0x000fe200078ea0ff */
/*0a20*/ @!P1 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff089224 */
/* 0x000fcc00078e00ff */
/*0a30*/ @!P1 DMUL R10, R6, R8 ; /* 0x00000008060a9228 */
/* 0x0004cc0000000000 */
/*0a40*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a50*/ DFMA R2, R2, R10, R22 ; /* 0x0000000a0202722b */
/* 0x008ece0000000016 */
/*0a60*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x008fe2000c101b04 */
/*0a70*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a80*/ BRA 0xa80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kGaussPdPKdS1_i
.globl _Z6kGaussPdPKdS1_i
.p2align 8
.type _Z6kGaussPdPKdS1_i,@function
_Z6kGaussPdPKdS1_i:
s_load_b32 s2, s[0:1], 0x2c
v_mov_b32_e32 v4, 0
s_load_b32 s33, s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v5, v4
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_cmp_lt_i32 s33, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[0:1], off
global_store_b64 v[0:1], v[4:5], off
s_cbranch_scc1 .LBB0_3
global_load_b64 v[4:5], v[0:1], off
s_load_b128 s[4:7], s[0:1], 0x8
v_mov_b32_e32 v6, 0
s_mov_b32 s3, 0x3ff71547
s_mov_b32 s2, 0x652b82fe
s_mov_b32 s9, 0xbfe62e42
s_mov_b32 s8, 0xfefa39ef
s_mov_b32 s11, 0xbc7abc9e
s_mov_b32 s10, 0x3b39803f
s_mov_b32 s13, 0x3e928af3
s_mov_b32 s12, 0xfca7ab0c
s_mov_b32 s15, 0x3e5ade15
s_mov_b32 s14, 0x6a5dcb37
s_mov_b32 s17, 0x3ec71dee
s_mov_b32 s16, 0x623fde64
s_mov_b32 s19, 0x3efa0199
s_mov_b32 s18, 0x7c89e6b0
s_mov_b32 s21, 0x3f2a01a0
s_mov_b32 s20, 0x14761f6e
s_mov_b32 s23, 0x3f56c16c
s_mov_b32 s22, 0x1852b7b0
s_mov_b32 s25, 0x3f811111
s_mov_b32 s24, 0x11122322
s_mov_b32 s27, 0x3fa55555
s_mov_b32 s26, 0x555502a1
s_mov_b32 s29, 0x3fc55555
s_mov_b32 s28, 0x55555511
s_mov_b32 s31, 0x3fe00000
s_mov_b32 s30, 11
.LBB0_2:
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[7:8], v6, s[4:5]
global_load_b64 v[9:10], v6, s[6:7]
s_add_i32 s33, s33, -1
s_waitcnt vmcnt(1)
v_add_f64 v[7:8], v[2:3], -v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[7:8], v[7:8], -v[7:8]
v_mul_f64 v[11:12], v[7:8], s[2:3]
v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[7:8]
v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[7:8]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[11:12], v[11:12]
v_fma_f64 v[13:14], v[11:12], s[8:9], v[7:8]
v_cvt_i32_f64_e32 v17, v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[11:12], s[10:11], v[13:14]
v_fma_f64 v[15:16], v[13:14], s[14:15], s[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[16:17]
v_fma_f64 v[15:16], v[13:14], v[15:16], s[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[20:21]
v_fma_f64 v[15:16], v[13:14], v[15:16], s[22:23]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[24:25]
v_fma_f64 v[15:16], v[13:14], v[15:16], s[26:27]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[28:29]
v_fma_f64 v[15:16], v[13:14], v[15:16], s[30:31]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], 1.0
v_fma_f64 v[11:12], v[13:14], v[15:16], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[11:12], v[11:12], v17
v_cndmask_b32_e32 v12, 0x7ff00000, v12, vcc_lo
s_and_b32 vcc_lo, s0, vcc_lo
s_add_u32 s6, s6, 8
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v7, 0, v11, vcc_lo
s_addc_u32 s7, s7, 0
v_cndmask_b32_e64 v8, 0, v12, s0
s_add_u32 s4, s4, 8
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s33, 0
s_waitcnt vmcnt(0)
v_fma_f64 v[4:5], v[9:10], v[7:8], v[4:5]
global_store_b64 v[0:1], v[4:5], off
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kGaussPdPKdS1_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 34
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kGaussPdPKdS1_i, .Lfunc_end0-_Z6kGaussPdPKdS1_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kGaussPdPKdS1_i
.private_segment_fixed_size: 0
.sgpr_count: 36
.sgpr_spill_count: 0
.symbol: _Z6kGaussPdPKdS1_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a04c2_00000000-6_simpleEx.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z6kGaussPdPKdS1_iPdPKdS1_i
.type _Z32__device_stub__Z6kGaussPdPKdS1_iPdPKdS1_i, @function
_Z32__device_stub__Z6kGaussPdPKdS1_iPdPKdS1_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kGaussPdPKdS1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z6kGaussPdPKdS1_iPdPKdS1_i, .-_Z32__device_stub__Z6kGaussPdPKdS1_iPdPKdS1_i
.globl _Z6kGaussPdPKdS1_i
.type _Z6kGaussPdPKdS1_i, @function
_Z6kGaussPdPKdS1_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6kGaussPdPKdS1_iPdPKdS1_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6kGaussPdPKdS1_i, .-_Z6kGaussPdPKdS1_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kGaussPdPKdS1_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kGaussPdPKdS1_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "simpleEx.hip"
.globl _Z21__device_stub__kGaussPdPKdS1_i # -- Begin function _Z21__device_stub__kGaussPdPKdS1_i
.p2align 4, 0x90
.type _Z21__device_stub__kGaussPdPKdS1_i,@function
_Z21__device_stub__kGaussPdPKdS1_i: # @_Z21__device_stub__kGaussPdPKdS1_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kGaussPdPKdS1_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__kGaussPdPKdS1_i, .Lfunc_end0-_Z21__device_stub__kGaussPdPKdS1_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kGaussPdPKdS1_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kGaussPdPKdS1_i,@object # @_Z6kGaussPdPKdS1_i
.section .rodata,"a",@progbits
.globl _Z6kGaussPdPKdS1_i
.p2align 3, 0x0
_Z6kGaussPdPKdS1_i:
.quad _Z21__device_stub__kGaussPdPKdS1_i
.size _Z6kGaussPdPKdS1_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kGaussPdPKdS1_i"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kGaussPdPKdS1_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kGaussPdPKdS1_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<cuda_runtime.h>
#include "device_launch_parameters.h"
#include <ctime>
#include <iostream>
using namespace std;
#define BLOCK 16
#define WIDTH 1024
float* d_A, * d_B, * d_C;
__global__ void d_multiply0(float* A, float* B, float* C) {
unsigned int r = blockDim.y * blockIdx.y + threadIdx.y;
unsigned int c = blockDim.x * blockIdx.x + threadIdx.x;
unsigned int i;
float tmp;
tmp = 0.0f;
for (i = 0; i < WIDTH; i++) {
tmp += A[WIDTH * r + i] * B[WIDTH * i + c];
}
C[WIDTH * r + c] = tmp;
}
float ha_A[WIDTH * WIDTH];
float ha_B[WIDTH * WIDTH];
float ha_C[WIDTH * WIDTH];
void d_multiply() {
clock_t start = clock();
size_t size = sizeof(float) * WIDTH * WIDTH;
cudaMemcpy(d_A, ha_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, ha_B, size, cudaMemcpyHostToDevice);
dim3 grid(WIDTH / BLOCK, WIDTH / BLOCK);
dim3 block(BLOCK, BLOCK);
d_multiply0 << < grid, block >> > (d_A, d_B, d_C);
cudaMemcpy(ha_C, d_C, size, cudaMemcpyDeviceToHost);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
clock_t end = clock();
cout << "CUDA計算時間:" << (double)(end - start) << endl;
}
float* d_process() {
unsigned int i;
cudaMalloc((void**)&d_A, sizeof(float) * WIDTH * WIDTH);
cudaMalloc((void**)&d_B, sizeof(float) * WIDTH * WIDTH);
cudaMalloc((void**)&d_C, sizeof(float) * WIDTH * WIDTH);
for (i = 0; i < WIDTH * WIDTH; i++) {
ha_A[i] = (float)i;
ha_B[i] = (float)i;
}
d_multiply();
return &ha_C[0];
} | code for sm_80
Function : _Z11d_multiply0PfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ MOV R29, RZ ; /* 0x000000ff001d7202 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0050*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0060*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e620000002100 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R0 ; /* 0x0000010003037a24 */
/* 0x001fe200078e0200 */
/*0080*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fc800000001ff */
/*0090*/ SHF.L.U32 R3, R3, 0xa, RZ ; /* 0x0000000a03037819 */
/* 0x000fe200000006ff */
/*00a0*/ IMAD R2, R2, c[0x0][0x0], R7 ; /* 0x0000000002027a24 */
/* 0x002fca00078e0207 */
/*00b0*/ IMAD.WIDE.U32 R4, R3, R0, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fe200078e0000 */
/*00c0*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fc80000000f00 */
/*00d0*/ IADD3 R12, P0, R4, 0x20, RZ ; /* 0x00000020040c7810 */
/* 0x000fe20007f1e0ff */
/*00e0*/ HFMA2.MMA R4, -RZ, RZ, 0, 0.0078125 ; /* 0x00002000ff047435 */
/* 0x000fc600000001ff */
/*00f0*/ IADD3.X R13, RZ, R5, RZ, P0, !PT ; /* 0x00000005ff0d7210 */
/* 0x000fe400007fe4ff */
/*0100*/ IADD3 R5, R2, 0x3c00, RZ ; /* 0x00003c0002057810 */
/* 0x000fc80007ffe0ff */
/*0110*/ IADD3 R9, R5.reuse, -0x3c00, RZ ; /* 0xffffc40005097810 */
/* 0x040fe20007ffe0ff */
/*0120*/ LDG.E R28, [R12.64+-0x20] ; /* 0xffffe0040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0130*/ IADD3 R11, R5.reuse, -0x3800, RZ ; /* 0xffffc800050b7810 */
/* 0x040fe40007ffe0ff */
/*0140*/ IADD3 R19, R5, -0x3400, RZ ; /* 0xffffcc0005137810 */
/* 0x000fe20007ffe0ff */
/*0150*/ IMAD.WIDE.U32 R8, R9, R0.reuse, c[0x0][0x168] ; /* 0x00005a0009087625 */
/* 0x080fe200078e0000 */
/*0160*/ LDG.E R26, [R12.64+-0x1c] ; /* 0xffffe4040c1a7981 */
/* 0x000ee6000c1e1900 */
/*0170*/ IMAD.WIDE.U32 R10, R11, R0, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fe200078e0000 */
/*0180*/ LDG.E R27, [R8.64] ; /* 0x00000004081b7981 */
/* 0x0000a2000c1e1900 */
/*0190*/ IADD3 R21, R6, 0xc00, RZ ; /* 0x00000c0006157810 */
/* 0x000fc40007ffe0ff */
/*01a0*/ IMAD.WIDE.U32 R18, R19, R0.reuse, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x080fe200078e0000 */
/*01b0*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x0002e2000c1e1900 */
/*01c0*/ IADD3 R17, R6.reuse, 0x1000, RZ ; /* 0x0000100006117810 */
/* 0x040fe40007ffe0ff */
/*01d0*/ IMAD.WIDE.U32 R20, R21, R0.reuse, c[0x0][0x168] ; /* 0x00005a0015147625 */
/* 0x080fe200078e0000 */
/*01e0*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000968000c1e1900 */
/*01f0*/ LDG.E R15, [R12.64+-0x18] ; /* 0xffffe8040c0f7981 */
/* 0x000f62000c1e1900 */
/*0200*/ IADD3 R25, R6, 0x1400, RZ ; /* 0x0000140006197810 */
/* 0x000fe20007ffe0ff */
/*0210*/ IMAD.WIDE.U32 R16, R17, R0, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x000fc400078e0000 */
/*0220*/ LDG.E R7, [R20.64] ; /* 0x0000000414077981 */
/* 0x000368000c1e1900 */
/*0230*/ LDG.E R8, [R12.64+-0x14] ; /* 0xffffec040c087981 */
/* 0x001f62000c1e1900 */
/*0240*/ IMAD.WIDE.U32 R24, R25, R0, c[0x0][0x168] ; /* 0x00005a0019187625 */
/* 0x000fe200078e0000 */
/*0250*/ IADD3 R19, R6.reuse, 0x1800, RZ ; /* 0x0000180006137810 */
/* 0x050fe40007ffe0ff */
/*0260*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000128000c1e1900 */
/*0270*/ LDG.E R10, [R12.64+-0x10] ; /* 0xfffff0040c0a7981 */
/* 0x002f22000c1e1900 */
/*0280*/ IADD3 R21, R6, 0x1c00, RZ ; /* 0x00001c0006157810 */
/* 0x000fc60007ffe0ff */
/*0290*/ LDG.E R11, [R24.64] ; /* 0x00000004180b7981 */
/* 0x000322000c1e1900 */
/*02a0*/ IMAD.WIDE.U32 R16, R19, R0, c[0x0][0x168] ; /* 0x00005a0013107625 */
/* 0x001fc600078e0000 */
/*02b0*/ LDG.E R18, [R12.64+-0xc] ; /* 0xfffff4040c127981 */
/* 0x000f28000c1e1900 */
/*02c0*/ LDG.E R19, [R16.64] ; /* 0x0000000410137981 */
/* 0x000122000c1e1900 */
/*02d0*/ IMAD.WIDE.U32 R20, R21, R0, c[0x0][0x168] ; /* 0x00005a0015147625 */
/* 0x000fc600078e0000 */
/*02e0*/ LDG.E R22, [R12.64+-0x8] ; /* 0xfffff8040c167981 */
/* 0x000f28000c1e1900 */
/*02f0*/ LDG.E R21, [R20.64] ; /* 0x0000000414157981 */
/* 0x000128000c1e1900 */
/*0300*/ LDG.E R20, [R12.64+-0x4] ; /* 0xfffffc040c147981 */
/* 0x001f22000c1e1900 */
/*0310*/ IADD3 R25, R6, 0x2000, RZ ; /* 0x0000200006197810 */
/* 0x002fe20007ffe0ff */
/*0320*/ FFMA R27, R27, R28, R29 ; /* 0x0000001c1b1b7223 */
/* 0x004fc8000000001d */
/*0330*/ FFMA R23, R23, R26, R27 ; /* 0x0000001a17177223 */
/* 0x008fe2000000001b */
/*0340*/ IADD3 R27, R6, 0x2400, RZ ; /* 0x00002400061b7810 */
/* 0x000fc60007ffe0ff */
/*0350*/ FFMA R23, R14, R15, R23 ; /* 0x0000000f0e177223 */
/* 0x020fe40000000017 */
/*0360*/ IMAD.WIDE.U32 R14, R25, R0, c[0x0][0x168] ; /* 0x00005a00190e7625 */
/* 0x000fe200078e0000 */
/*0370*/ IADD3 R25, R6, 0x2800, RZ ; /* 0x0000280006197810 */
/* 0x000fc60007ffe0ff */
/*0380*/ IMAD.WIDE.U32 R16, R27, R0, c[0x0][0x168] ; /* 0x00005a001b107625 */
/* 0x000fe200078e0000 */
/*0390*/ IADD3 R27, R6, 0x2c00, RZ ; /* 0x00002c00061b7810 */
/* 0x000fe20007ffe0ff */
/*03a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000a4000c1e1900 */
/*03b0*/ FFMA R8, R7, R8, R23 ; /* 0x0000000807087223 */
/* 0x000fe40000000017 */
/*03c0*/ LDG.E R7, [R12.64] ; /* 0x000000040c077981 */
/* 0x0002a2000c1e1900 */
/*03d0*/ IMAD.WIDE.U32 R24, R25, R0, c[0x0][0x168] ; /* 0x00005a0019187625 */
/* 0x000fe200078e0000 */
/*03e0*/ IADD3 R29, R5, -0xc00, RZ ; /* 0xfffff400051d7810 */
/* 0x000fe40007ffe0ff */
/*03f0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000762000c1e1900 */
/*0400*/ FFMA R10, R9, R10, R8 ; /* 0x0000000a090a7223 */
/* 0x010fc60000000008 */
/*0410*/ LDG.E R23, [R12.64+0x4] ; /* 0x000004040c177981 */
/* 0x000362000c1e1900 */
/*0420*/ IMAD.WIDE.U32 R26, R27, R0, c[0x0][0x168] ; /* 0x00005a001b1a7625 */
/* 0x000fc600078e0000 */
/*0430*/ LDG.E R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000962000c1e1900 */
/*0440*/ FFMA R10, R11, R18, R10 ; /* 0x000000120b0a7223 */
/* 0x000fe2000000000a */
/*0450*/ IADD3 R11, R5, -0x800, RZ ; /* 0xfffff800050b7810 */
/* 0x000fe40007ffe0ff */
/*0460*/ LDG.E R15, [R12.64+0x8] ; /* 0x000008040c0f7981 */
/* 0x001362000c1e1900 */
/*0470*/ IMAD.WIDE.U32 R8, R29, R0, c[0x0][0x168] ; /* 0x00005a001d087625 */
/* 0x000fe200078e0000 */
/*0480*/ IADD3 R18, R5, -0x400, RZ ; /* 0xfffffc0005127810 */
/* 0x000fe40007ffe0ff */
/*0490*/ LDG.E R26, [R26.64] ; /* 0x000000041a1a7981 */
/* 0x000f62000c1e1900 */
/*04a0*/ FFMA R28, R19, R22, R10 ; /* 0x00000016131c7223 */
/* 0x000fc6000000000a */
/*04b0*/ LDG.E R29, [R12.64+0xc] ; /* 0x00000c040c1d7981 */
/* 0x000362000c1e1900 */
/*04c0*/ IMAD.WIDE.U32 R10, R11, R0, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fc600078e0000 */
/*04d0*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x0080e2000c1e1900 */
/*04e0*/ IMAD.WIDE.U32 R18, R18, R0, c[0x0][0x168] ; /* 0x00005a0012127625 */
/* 0x000fc600078e0000 */
/*04f0*/ LDG.E R22, [R12.64+0x10] ; /* 0x000010040c167981 */
/* 0x0002e8000c1e1900 */
/*0500*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee2000c1e1900 */
/*0510*/ FFMA R28, R21, R20, R28 ; /* 0x00000014151c7223 */
/* 0x000fc6000000001c */
/*0520*/ LDG.E R25, [R12.64+0x14] ; /* 0x000014040c197981 */
/* 0x010322000c1e1900 */
/*0530*/ IMAD.WIDE.U32 R8, R5, R0, c[0x0][0x168] ; /* 0x00005a0005087625 */
/* 0x001fc600078e0000 */
/*0540*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f28000c1e1900 */
/*0550*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x000328000c1e1900 */
/*0560*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000f28000c1e1900 */
/*0570*/ LDG.E R20, [R12.64+0x1c] ; /* 0x00001c040c147981 */
/* 0x000322000c1e1900 */
/*0580*/ IADD3 R4, R4, 0x4000, RZ ; /* 0x0000400004047810 */
/* 0x000fc80007ffe0ff */
/*0590*/ ISETP.NE.AND P0, PT, R4, 0x102000, PT ; /* 0x001020000400780c */
/* 0x000fe40003f05270 */
/*05a0*/ IADD3 R12, P1, R12, 0x40, RZ ; /* 0x000000400c0c7810 */
/* 0x002fe40007f3e0ff */
/*05b0*/ IADD3 R5, R5, 0x4000, RZ ; /* 0x0000400005057810 */
/* 0x000fe40007ffe0ff */
/*05c0*/ IADD3.X R13, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe40000ffe4ff */
/*05d0*/ IADD3 R6, R6, 0x4000, RZ ; /* 0x0000400006067810 */
/* 0x000fe20007ffe0ff */
/*05e0*/ FFMA R7, R14, R7, R28 ; /* 0x000000070e077223 */
/* 0x004fc8000000001c */
/*05f0*/ FFMA R7, R16, R23, R7 ; /* 0x0000001710077223 */
/* 0x020fc80000000007 */
/*0600*/ FFMA R7, R24, R15, R7 ; /* 0x0000000f18077223 */
/* 0x000fc80000000007 */
/*0610*/ FFMA R7, R26, R29, R7 ; /* 0x0000001d1a077223 */
/* 0x000fc80000000007 */
/*0620*/ FFMA R7, R17, R22, R7 ; /* 0x0000001611077223 */
/* 0x008fc80000000007 */
/*0630*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x010fc80000000007 */
/*0640*/ FFMA R7, R18, R21, R7 ; /* 0x0000001512077223 */
/* 0x000fc80000000007 */
/*0650*/ FFMA R29, R9, R20, R7 ; /* 0x00000014091d7223 */
/* 0x000fe20000000007 */
/*0660*/ @P0 BRA 0x110 ; /* 0xfffffaa000000947 */
/* 0x000fea000383ffff */
/*0670*/ IADD3 R3, R2, R3, RZ ; /* 0x0000000302037210 */
/* 0x000fca0007ffe0ff */
/*0680*/ IMAD.WIDE.U32 R2, R3, R0, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0000 */
/*0690*/ STG.E [R2.64], R29 ; /* 0x0000001d02007986 */
/* 0x000fe2000c101904 */
/*06a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06b0*/ BRA 0x6b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<cuda_runtime.h>
#include "device_launch_parameters.h"
#include <ctime>
#include <iostream>
using namespace std;
#define BLOCK 16
#define WIDTH 1024
float* d_A, * d_B, * d_C;
__global__ void d_multiply0(float* A, float* B, float* C) {
unsigned int r = blockDim.y * blockIdx.y + threadIdx.y;
unsigned int c = blockDim.x * blockIdx.x + threadIdx.x;
unsigned int i;
float tmp;
tmp = 0.0f;
for (i = 0; i < WIDTH; i++) {
tmp += A[WIDTH * r + i] * B[WIDTH * i + c];
}
C[WIDTH * r + c] = tmp;
}
float ha_A[WIDTH * WIDTH];
float ha_B[WIDTH * WIDTH];
float ha_C[WIDTH * WIDTH];
void d_multiply() {
clock_t start = clock();
size_t size = sizeof(float) * WIDTH * WIDTH;
cudaMemcpy(d_A, ha_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, ha_B, size, cudaMemcpyHostToDevice);
dim3 grid(WIDTH / BLOCK, WIDTH / BLOCK);
dim3 block(BLOCK, BLOCK);
d_multiply0 << < grid, block >> > (d_A, d_B, d_C);
cudaMemcpy(ha_C, d_C, size, cudaMemcpyDeviceToHost);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
clock_t end = clock();
cout << "CUDA計算時間:" << (double)(end - start) << endl;
}
float* d_process() {
unsigned int i;
cudaMalloc((void**)&d_A, sizeof(float) * WIDTH * WIDTH);
cudaMalloc((void**)&d_B, sizeof(float) * WIDTH * WIDTH);
cudaMalloc((void**)&d_C, sizeof(float) * WIDTH * WIDTH);
for (i = 0; i < WIDTH * WIDTH; i++) {
ha_A[i] = (float)i;
ha_B[i] = (float)i;
}
d_multiply();
return &ha_C[0];
} | .file "tmpxft_000699b9_00000000-6_cuda_multiply.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11d_multiply0PfS_S_PfS_S_
.type _Z35__device_stub__Z11d_multiply0PfS_S_PfS_S_, @function
_Z35__device_stub__Z11d_multiply0PfS_S_PfS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11d_multiply0PfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z35__device_stub__Z11d_multiply0PfS_S_PfS_S_, .-_Z35__device_stub__Z11d_multiply0PfS_S_PfS_S_
.globl _Z11d_multiply0PfS_S_
.type _Z11d_multiply0PfS_S_, @function
_Z11d_multiply0PfS_S_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11d_multiply0PfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z11d_multiply0PfS_S_, .-_Z11d_multiply0PfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA\350\250\210\347\256\227\346\231\202\351\226\223:"
.text
.globl _Z10d_multiplyv
.type _Z10d_multiplyv, @function
_Z10d_multiplyv:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
call clock@PLT
movq %rax, %rbp
movl $1, %ecx
movl $4194304, %edx
leaq ha_A(%rip), %rsi
movq d_A(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
leaq ha_B(%rip), %rsi
movq d_B(%rip), %rdi
call cudaMemcpy@PLT
movl $64, 8(%rsp)
movl $64, 12(%rsp)
movl $1, 16(%rsp)
movl $16, 20(%rsp)
movl $16, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
movl $2, %ecx
movl $4194304, %edx
movq d_C(%rip), %rsi
leaq ha_C(%rip), %rdi
call cudaMemcpy@PLT
movq d_A(%rip), %rdi
call cudaFree@PLT
movq d_B(%rip), %rdi
call cudaFree@PLT
movq d_C(%rip), %rdi
call cudaFree@PLT
call clock@PLT
movq %rax, %rbx
movl $17, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
subq %rbp, %rbx
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L18
cmpb $0, 56(%rbp)
je .L14
movzbl 67(%rbp), %esi
.L15:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq d_C(%rip), %rdx
movq d_B(%rip), %rsi
movq d_A(%rip), %rdi
call _Z35__device_stub__Z11d_multiply0PfS_S_PfS_S_
jmp .L12
.L18:
call _ZSt16__throw_bad_castv@PLT
.L14:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L15
.cfi_endproc
.LFE3669:
.size _Z10d_multiplyv, .-_Z10d_multiplyv
.globl _Z9d_processv
.type _Z9d_processv, @function
_Z9d_processv:
.LFB3670:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $4194304, %esi
leaq d_A(%rip), %rdi
call cudaMalloc@PLT
movl $4194304, %esi
leaq d_B(%rip), %rdi
call cudaMalloc@PLT
movl $4194304, %esi
leaq d_C(%rip), %rdi
call cudaMalloc@PLT
movl $0, %eax
leaq ha_A(%rip), %rsi
leaq ha_B(%rip), %rcx
.L22:
movl %eax, %edx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
movss %xmm0, (%rsi,%rax,4)
movss %xmm0, (%rcx,%rax,4)
addq $1, %rax
cmpq $1048576, %rax
jne .L22
call _Z10d_multiplyv
leaq ha_C(%rip), %rax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z9d_processv, .-_Z9d_processv
.section .rodata.str1.1
.LC1:
.string "_Z11d_multiply0PfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11d_multiply0PfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl ha_C
.bss
.align 32
.type ha_C, @object
.size ha_C, 4194304
ha_C:
.zero 4194304
.globl ha_B
.align 32
.type ha_B, @object
.size ha_B, 4194304
ha_B:
.zero 4194304
.globl ha_A
.align 32
.type ha_A, @object
.size ha_A, 4194304
ha_A:
.zero 4194304
.globl d_C
.align 8
.type d_C, @object
.size d_C, 8
d_C:
.zero 8
.globl d_B
.align 8
.type d_B, @object
.size d_B, 8
d_B:
.zero 8
.globl d_A
.align 8
.type d_A, @object
.size d_A, 8
d_A:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<cuda_runtime.h>
#include "device_launch_parameters.h"
#include <ctime>
#include <iostream>
using namespace std;
#define BLOCK 16
#define WIDTH 1024
float* d_A, * d_B, * d_C;
__global__ void d_multiply0(float* A, float* B, float* C) {
unsigned int r = blockDim.y * blockIdx.y + threadIdx.y;
unsigned int c = blockDim.x * blockIdx.x + threadIdx.x;
unsigned int i;
float tmp;
tmp = 0.0f;
for (i = 0; i < WIDTH; i++) {
tmp += A[WIDTH * r + i] * B[WIDTH * i + c];
}
C[WIDTH * r + c] = tmp;
}
float ha_A[WIDTH * WIDTH];
float ha_B[WIDTH * WIDTH];
float ha_C[WIDTH * WIDTH];
void d_multiply() {
clock_t start = clock();
size_t size = sizeof(float) * WIDTH * WIDTH;
cudaMemcpy(d_A, ha_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, ha_B, size, cudaMemcpyHostToDevice);
dim3 grid(WIDTH / BLOCK, WIDTH / BLOCK);
dim3 block(BLOCK, BLOCK);
d_multiply0 << < grid, block >> > (d_A, d_B, d_C);
cudaMemcpy(ha_C, d_C, size, cudaMemcpyDeviceToHost);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
clock_t end = clock();
cout << "CUDA計算時間:" << (double)(end - start) << endl;
}
float* d_process() {
unsigned int i;
cudaMalloc((void**)&d_A, sizeof(float) * WIDTH * WIDTH);
cudaMalloc((void**)&d_B, sizeof(float) * WIDTH * WIDTH);
cudaMalloc((void**)&d_C, sizeof(float) * WIDTH * WIDTH);
for (i = 0; i < WIDTH * WIDTH; i++) {
ha_A[i] = (float)i;
ha_B[i] = (float)i;
}
d_multiply();
return &ha_C[0];
} | #pragma once
#include <hip/hip_runtime.h>
float* d_process(); |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #pragma once
#include <hip/hip_runtime.h>
float* d_process(); | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #pragma once
#include <hip/hip_runtime.h>
float* d_process(); | .text
.file "cuda_multiply.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11d_multiply0PfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ MOV R29, RZ ; /* 0x000000ff001d7202 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0050*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0060*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e620000002100 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R0 ; /* 0x0000010003037a24 */
/* 0x001fe200078e0200 */
/*0080*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fc800000001ff */
/*0090*/ SHF.L.U32 R3, R3, 0xa, RZ ; /* 0x0000000a03037819 */
/* 0x000fe200000006ff */
/*00a0*/ IMAD R2, R2, c[0x0][0x0], R7 ; /* 0x0000000002027a24 */
/* 0x002fca00078e0207 */
/*00b0*/ IMAD.WIDE.U32 R4, R3, R0, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fe200078e0000 */
/*00c0*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fc80000000f00 */
/*00d0*/ IADD3 R12, P0, R4, 0x20, RZ ; /* 0x00000020040c7810 */
/* 0x000fe20007f1e0ff */
/*00e0*/ HFMA2.MMA R4, -RZ, RZ, 0, 0.0078125 ; /* 0x00002000ff047435 */
/* 0x000fc600000001ff */
/*00f0*/ IADD3.X R13, RZ, R5, RZ, P0, !PT ; /* 0x00000005ff0d7210 */
/* 0x000fe400007fe4ff */
/*0100*/ IADD3 R5, R2, 0x3c00, RZ ; /* 0x00003c0002057810 */
/* 0x000fc80007ffe0ff */
/*0110*/ IADD3 R9, R5.reuse, -0x3c00, RZ ; /* 0xffffc40005097810 */
/* 0x040fe20007ffe0ff */
/*0120*/ LDG.E R28, [R12.64+-0x20] ; /* 0xffffe0040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0130*/ IADD3 R11, R5.reuse, -0x3800, RZ ; /* 0xffffc800050b7810 */
/* 0x040fe40007ffe0ff */
/*0140*/ IADD3 R19, R5, -0x3400, RZ ; /* 0xffffcc0005137810 */
/* 0x000fe20007ffe0ff */
/*0150*/ IMAD.WIDE.U32 R8, R9, R0.reuse, c[0x0][0x168] ; /* 0x00005a0009087625 */
/* 0x080fe200078e0000 */
/*0160*/ LDG.E R26, [R12.64+-0x1c] ; /* 0xffffe4040c1a7981 */
/* 0x000ee6000c1e1900 */
/*0170*/ IMAD.WIDE.U32 R10, R11, R0, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fe200078e0000 */
/*0180*/ LDG.E R27, [R8.64] ; /* 0x00000004081b7981 */
/* 0x0000a2000c1e1900 */
/*0190*/ IADD3 R21, R6, 0xc00, RZ ; /* 0x00000c0006157810 */
/* 0x000fc40007ffe0ff */
/*01a0*/ IMAD.WIDE.U32 R18, R19, R0.reuse, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x080fe200078e0000 */
/*01b0*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x0002e2000c1e1900 */
/*01c0*/ IADD3 R17, R6.reuse, 0x1000, RZ ; /* 0x0000100006117810 */
/* 0x040fe40007ffe0ff */
/*01d0*/ IMAD.WIDE.U32 R20, R21, R0.reuse, c[0x0][0x168] ; /* 0x00005a0015147625 */
/* 0x080fe200078e0000 */
/*01e0*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000968000c1e1900 */
/*01f0*/ LDG.E R15, [R12.64+-0x18] ; /* 0xffffe8040c0f7981 */
/* 0x000f62000c1e1900 */
/*0200*/ IADD3 R25, R6, 0x1400, RZ ; /* 0x0000140006197810 */
/* 0x000fe20007ffe0ff */
/*0210*/ IMAD.WIDE.U32 R16, R17, R0, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x000fc400078e0000 */
/*0220*/ LDG.E R7, [R20.64] ; /* 0x0000000414077981 */
/* 0x000368000c1e1900 */
/*0230*/ LDG.E R8, [R12.64+-0x14] ; /* 0xffffec040c087981 */
/* 0x001f62000c1e1900 */
/*0240*/ IMAD.WIDE.U32 R24, R25, R0, c[0x0][0x168] ; /* 0x00005a0019187625 */
/* 0x000fe200078e0000 */
/*0250*/ IADD3 R19, R6.reuse, 0x1800, RZ ; /* 0x0000180006137810 */
/* 0x050fe40007ffe0ff */
/*0260*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000128000c1e1900 */
/*0270*/ LDG.E R10, [R12.64+-0x10] ; /* 0xfffff0040c0a7981 */
/* 0x002f22000c1e1900 */
/*0280*/ IADD3 R21, R6, 0x1c00, RZ ; /* 0x00001c0006157810 */
/* 0x000fc60007ffe0ff */
/*0290*/ LDG.E R11, [R24.64] ; /* 0x00000004180b7981 */
/* 0x000322000c1e1900 */
/*02a0*/ IMAD.WIDE.U32 R16, R19, R0, c[0x0][0x168] ; /* 0x00005a0013107625 */
/* 0x001fc600078e0000 */
/*02b0*/ LDG.E R18, [R12.64+-0xc] ; /* 0xfffff4040c127981 */
/* 0x000f28000c1e1900 */
/*02c0*/ LDG.E R19, [R16.64] ; /* 0x0000000410137981 */
/* 0x000122000c1e1900 */
/*02d0*/ IMAD.WIDE.U32 R20, R21, R0, c[0x0][0x168] ; /* 0x00005a0015147625 */
/* 0x000fc600078e0000 */
/*02e0*/ LDG.E R22, [R12.64+-0x8] ; /* 0xfffff8040c167981 */
/* 0x000f28000c1e1900 */
/*02f0*/ LDG.E R21, [R20.64] ; /* 0x0000000414157981 */
/* 0x000128000c1e1900 */
/*0300*/ LDG.E R20, [R12.64+-0x4] ; /* 0xfffffc040c147981 */
/* 0x001f22000c1e1900 */
/*0310*/ IADD3 R25, R6, 0x2000, RZ ; /* 0x0000200006197810 */
/* 0x002fe20007ffe0ff */
/*0320*/ FFMA R27, R27, R28, R29 ; /* 0x0000001c1b1b7223 */
/* 0x004fc8000000001d */
/*0330*/ FFMA R23, R23, R26, R27 ; /* 0x0000001a17177223 */
/* 0x008fe2000000001b */
/*0340*/ IADD3 R27, R6, 0x2400, RZ ; /* 0x00002400061b7810 */
/* 0x000fc60007ffe0ff */
/*0350*/ FFMA R23, R14, R15, R23 ; /* 0x0000000f0e177223 */
/* 0x020fe40000000017 */
/*0360*/ IMAD.WIDE.U32 R14, R25, R0, c[0x0][0x168] ; /* 0x00005a00190e7625 */
/* 0x000fe200078e0000 */
/*0370*/ IADD3 R25, R6, 0x2800, RZ ; /* 0x0000280006197810 */
/* 0x000fc60007ffe0ff */
/*0380*/ IMAD.WIDE.U32 R16, R27, R0, c[0x0][0x168] ; /* 0x00005a001b107625 */
/* 0x000fe200078e0000 */
/*0390*/ IADD3 R27, R6, 0x2c00, RZ ; /* 0x00002c00061b7810 */
/* 0x000fe20007ffe0ff */
/*03a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000a4000c1e1900 */
/*03b0*/ FFMA R8, R7, R8, R23 ; /* 0x0000000807087223 */
/* 0x000fe40000000017 */
/*03c0*/ LDG.E R7, [R12.64] ; /* 0x000000040c077981 */
/* 0x0002a2000c1e1900 */
/*03d0*/ IMAD.WIDE.U32 R24, R25, R0, c[0x0][0x168] ; /* 0x00005a0019187625 */
/* 0x000fe200078e0000 */
/*03e0*/ IADD3 R29, R5, -0xc00, RZ ; /* 0xfffff400051d7810 */
/* 0x000fe40007ffe0ff */
/*03f0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000762000c1e1900 */
/*0400*/ FFMA R10, R9, R10, R8 ; /* 0x0000000a090a7223 */
/* 0x010fc60000000008 */
/*0410*/ LDG.E R23, [R12.64+0x4] ; /* 0x000004040c177981 */
/* 0x000362000c1e1900 */
/*0420*/ IMAD.WIDE.U32 R26, R27, R0, c[0x0][0x168] ; /* 0x00005a001b1a7625 */
/* 0x000fc600078e0000 */
/*0430*/ LDG.E R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000962000c1e1900 */
/*0440*/ FFMA R10, R11, R18, R10 ; /* 0x000000120b0a7223 */
/* 0x000fe2000000000a */
/*0450*/ IADD3 R11, R5, -0x800, RZ ; /* 0xfffff800050b7810 */
/* 0x000fe40007ffe0ff */
/*0460*/ LDG.E R15, [R12.64+0x8] ; /* 0x000008040c0f7981 */
/* 0x001362000c1e1900 */
/*0470*/ IMAD.WIDE.U32 R8, R29, R0, c[0x0][0x168] ; /* 0x00005a001d087625 */
/* 0x000fe200078e0000 */
/*0480*/ IADD3 R18, R5, -0x400, RZ ; /* 0xfffffc0005127810 */
/* 0x000fe40007ffe0ff */
/*0490*/ LDG.E R26, [R26.64] ; /* 0x000000041a1a7981 */
/* 0x000f62000c1e1900 */
/*04a0*/ FFMA R28, R19, R22, R10 ; /* 0x00000016131c7223 */
/* 0x000fc6000000000a */
/*04b0*/ LDG.E R29, [R12.64+0xc] ; /* 0x00000c040c1d7981 */
/* 0x000362000c1e1900 */
/*04c0*/ IMAD.WIDE.U32 R10, R11, R0, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fc600078e0000 */
/*04d0*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x0080e2000c1e1900 */
/*04e0*/ IMAD.WIDE.U32 R18, R18, R0, c[0x0][0x168] ; /* 0x00005a0012127625 */
/* 0x000fc600078e0000 */
/*04f0*/ LDG.E R22, [R12.64+0x10] ; /* 0x000010040c167981 */
/* 0x0002e8000c1e1900 */
/*0500*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee2000c1e1900 */
/*0510*/ FFMA R28, R21, R20, R28 ; /* 0x00000014151c7223 */
/* 0x000fc6000000001c */
/*0520*/ LDG.E R25, [R12.64+0x14] ; /* 0x000014040c197981 */
/* 0x010322000c1e1900 */
/*0530*/ IMAD.WIDE.U32 R8, R5, R0, c[0x0][0x168] ; /* 0x00005a0005087625 */
/* 0x001fc600078e0000 */
/*0540*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f28000c1e1900 */
/*0550*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x000328000c1e1900 */
/*0560*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000f28000c1e1900 */
/*0570*/ LDG.E R20, [R12.64+0x1c] ; /* 0x00001c040c147981 */
/* 0x000322000c1e1900 */
/*0580*/ IADD3 R4, R4, 0x4000, RZ ; /* 0x0000400004047810 */
/* 0x000fc80007ffe0ff */
/*0590*/ ISETP.NE.AND P0, PT, R4, 0x102000, PT ; /* 0x001020000400780c */
/* 0x000fe40003f05270 */
/*05a0*/ IADD3 R12, P1, R12, 0x40, RZ ; /* 0x000000400c0c7810 */
/* 0x002fe40007f3e0ff */
/*05b0*/ IADD3 R5, R5, 0x4000, RZ ; /* 0x0000400005057810 */
/* 0x000fe40007ffe0ff */
/*05c0*/ IADD3.X R13, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe40000ffe4ff */
/*05d0*/ IADD3 R6, R6, 0x4000, RZ ; /* 0x0000400006067810 */
/* 0x000fe20007ffe0ff */
/*05e0*/ FFMA R7, R14, R7, R28 ; /* 0x000000070e077223 */
/* 0x004fc8000000001c */
/*05f0*/ FFMA R7, R16, R23, R7 ; /* 0x0000001710077223 */
/* 0x020fc80000000007 */
/*0600*/ FFMA R7, R24, R15, R7 ; /* 0x0000000f18077223 */
/* 0x000fc80000000007 */
/*0610*/ FFMA R7, R26, R29, R7 ; /* 0x0000001d1a077223 */
/* 0x000fc80000000007 */
/*0620*/ FFMA R7, R17, R22, R7 ; /* 0x0000001611077223 */
/* 0x008fc80000000007 */
/*0630*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x010fc80000000007 */
/*0640*/ FFMA R7, R18, R21, R7 ; /* 0x0000001512077223 */
/* 0x000fc80000000007 */
/*0650*/ FFMA R29, R9, R20, R7 ; /* 0x00000014091d7223 */
/* 0x000fe20000000007 */
/*0660*/ @P0 BRA 0x110 ; /* 0xfffffaa000000947 */
/* 0x000fea000383ffff */
/*0670*/ IADD3 R3, R2, R3, RZ ; /* 0x0000000302037210 */
/* 0x000fca0007ffe0ff */
/*0680*/ IMAD.WIDE.U32 R2, R3, R0, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0000 */
/*0690*/ STG.E [R2.64], R29 ; /* 0x0000001d02007986 */
/* 0x000fe2000c101904 */
/*06a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06b0*/ BRA 0x6b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000699b9_00000000-6_cuda_multiply.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11d_multiply0PfS_S_PfS_S_
.type _Z35__device_stub__Z11d_multiply0PfS_S_PfS_S_, @function
_Z35__device_stub__Z11d_multiply0PfS_S_PfS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11d_multiply0PfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z35__device_stub__Z11d_multiply0PfS_S_PfS_S_, .-_Z35__device_stub__Z11d_multiply0PfS_S_PfS_S_
.globl _Z11d_multiply0PfS_S_
.type _Z11d_multiply0PfS_S_, @function
_Z11d_multiply0PfS_S_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11d_multiply0PfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z11d_multiply0PfS_S_, .-_Z11d_multiply0PfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA\350\250\210\347\256\227\346\231\202\351\226\223:"
.text
.globl _Z10d_multiplyv
.type _Z10d_multiplyv, @function
_Z10d_multiplyv:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
call clock@PLT
movq %rax, %rbp
movl $1, %ecx
movl $4194304, %edx
leaq ha_A(%rip), %rsi
movq d_A(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
leaq ha_B(%rip), %rsi
movq d_B(%rip), %rdi
call cudaMemcpy@PLT
movl $64, 8(%rsp)
movl $64, 12(%rsp)
movl $1, 16(%rsp)
movl $16, 20(%rsp)
movl $16, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
movl $2, %ecx
movl $4194304, %edx
movq d_C(%rip), %rsi
leaq ha_C(%rip), %rdi
call cudaMemcpy@PLT
movq d_A(%rip), %rdi
call cudaFree@PLT
movq d_B(%rip), %rdi
call cudaFree@PLT
movq d_C(%rip), %rdi
call cudaFree@PLT
call clock@PLT
movq %rax, %rbx
movl $17, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
subq %rbp, %rbx
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L18
cmpb $0, 56(%rbp)
je .L14
movzbl 67(%rbp), %esi
.L15:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq d_C(%rip), %rdx
movq d_B(%rip), %rsi
movq d_A(%rip), %rdi
call _Z35__device_stub__Z11d_multiply0PfS_S_PfS_S_
jmp .L12
.L18:
call _ZSt16__throw_bad_castv@PLT
.L14:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L15
.cfi_endproc
.LFE3669:
.size _Z10d_multiplyv, .-_Z10d_multiplyv
.globl _Z9d_processv
.type _Z9d_processv, @function
_Z9d_processv:
.LFB3670:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $4194304, %esi
leaq d_A(%rip), %rdi
call cudaMalloc@PLT
movl $4194304, %esi
leaq d_B(%rip), %rdi
call cudaMalloc@PLT
movl $4194304, %esi
leaq d_C(%rip), %rdi
call cudaMalloc@PLT
movl $0, %eax
leaq ha_A(%rip), %rsi
leaq ha_B(%rip), %rcx
.L22:
movl %eax, %edx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
movss %xmm0, (%rsi,%rax,4)
movss %xmm0, (%rcx,%rax,4)
addq $1, %rax
cmpq $1048576, %rax
jne .L22
call _Z10d_multiplyv
leaq ha_C(%rip), %rax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z9d_processv, .-_Z9d_processv
.section .rodata.str1.1
.LC1:
.string "_Z11d_multiply0PfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11d_multiply0PfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl ha_C
.bss
.align 32
.type ha_C, @object
.size ha_C, 4194304
ha_C:
.zero 4194304
.globl ha_B
.align 32
.type ha_B, @object
.size ha_B, 4194304
ha_B:
.zero 4194304
.globl ha_A
.align 32
.type ha_A, @object
.size ha_A, 4194304
ha_A:
.zero 4194304
.globl d_C
.align 8
.type d_C, @object
.size d_C, 8
d_C:
.zero 8
.globl d_B
.align 8
.type d_B, @object
.size d_B, 8
d_B:
.zero 8
.globl d_A
.align 8
.type d_A, @object
.size d_A, 8
d_A:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_multiply.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuComplex.h>
#include <math_constants.h>
// Use symmetry
// Use max_half_support threads only
// Perhaps it's not very cache friendly, but it is
// very simple to perform work-distribution for this variant
#define __SET_MAP \
const int \
x = blockIdx.x * blockDim.x + threadIdx.x \
, y = blockIdx.y * blockDim.y + threadIdx.y \
, xl = max_half_support - x \
, xr = max_half_support + x \
, yl = max_half_support - y \
, yr = max_half_support + y \
;
template <int max_half_support>
__device__ __inline__
void ucs_common(
cuDoubleComplex mesh[max_half_support * 2 + 1][max_half_support * 2 + 1]
, double t2
){
__SET_MAP
double
t2_div_sc = t2 / double(max_half_support)
, xs = double(x) * t2_div_sc
, ys = double(y) * t2_div_sc
;
cuDoubleComplex r2 = make_cuDoubleComplex(xs * xs + ys * ys, 0.0);
mesh[xl][yl] = r2;
mesh[xl][yr] = r2;
mesh[xr][yl] = r2;
mesh[xr][yr] = r2;
}
extern "C" __global__ void r2(cuDoubleComplex mesh[257][257], double t2) {
ucs_common<128>(mesh, t2);
}
#if 0
template <int max_half_support>
__device__
void calc_inplace(
cuDoubleComplex mesh[max_half_support * 2 + 1][max_half_support * 2 + 1]
, double w
){
__SET_MAP
// mesh is symmetric, thus we need no recalc ph
double ph = w * (1.0 - sqrt(1.0 - mesh[xl][yl].x));
double s, c;
sincos(2.0 * CUDART_PI * ph, &s, &c);
cuDoubleComplex res = make_cuDoubleComplex(c, -s); // to get rid of conj later
mesh[xl][yl] = res;
mesh[xl][yr] = res;
mesh[xr][yl] = res;
mesh[xr][yr] = res;
}
// test instantiation
template __device__
void calc_inplace<128>(
cuDoubleComplex mesh[257][257]
, double w
);
#endif
template <int max_half_support>
__device__ __inline__
void calc(
cuDoubleComplex dst[max_half_support * 2 + 1][max_half_support * 2 + 1]
, const cuDoubleComplex src[max_half_support * 2 + 1][max_half_support * 2 + 1]
, double w
){
__SET_MAP
double ph = w * (1.0 - sqrt(1.0 - src[xl][yl].x));
double s, c;
sincos(2.0 * CUDART_PI * ph, &s, &c);
cuDoubleComplex res = make_cuDoubleComplex(c, -s); // to get rid of conj later
dst[xl][yl] = res;
dst[xl][yr] = res;
dst[xr][yl] = res;
dst[xr][yr] = res;
}
extern "C" __global__ void wkernff(
cuDoubleComplex dst[257][257]
, const cuDoubleComplex src[257][257]
, double w
){
calc<128>(dst, src, w);
}
template <
int max_half_support
, int oversample
>
__device__ __inline__
void copy_ucs_2_over(
cuDoubleComplex dst[(max_half_support * 2 + 1) * oversample][(max_half_support * 2 + 1) * oversample]
, const cuDoubleComplex src[max_half_support * 2 + 1][max_half_support * 2 + 1]
){
const int dst_center = (max_half_support * 2 + 1) * oversample / 2;
__SET_MAP
dst[dst_center - x][dst_center - y] = src[xl][yl];
dst[dst_center - x][dst_center + y] = src[xl][yr];
dst[dst_center + x][dst_center - y] = src[xr][yl];
dst[dst_center + x][dst_center + y] = src[xr][yr];
}
extern "C" __global__ void copy_2_over(
cuDoubleComplex dst[2056][2056]
, const cuDoubleComplex src[257][257]
){
copy_ucs_2_over<128,8>(dst, src);
}
#ifdef __SMALL_EXTRACT
template <
int max_half_support
, int oversample
>
__device__ __inline__
void extract_over(
int overx
, int overy
, cuDoubleComplex dst[max_half_support * 2 + 1][max_half_support * 2 + 1]
, const cuDoubleComplex src[(max_half_support * 2 + 1) * oversample][(max_half_support * 2 + 1) * oversample]
) {
__SET_MAP
const int
sxl = xl * oversample + overx
, sxr = xr * oversample + overx
, syl = yl * oversample + overy
, syr = yr * oversample + overy
;
dst[xl][yl] = src[sxl][syl];
dst[xl][yr] = src[sxl][syr];
dst[xr][yl] = src[sxr][syl];
dst[xr][yr] = src[sxr][syr];
}
extern "C" __global__ void wextract0(
int overx
, int overy
, cuDoubleComplex dst[257][257]
, const cuDoubleComplex src[2056][2056]
){
extract_over<128,8>(overx, overy, dst, src);
}
#else
// We use 3rd grid dimension to cover oversample range
template <
int max_half_support
, int oversample
>
__device__ __inline__
void transpose_over(
cuDoubleComplex dst[oversample][oversample][max_half_support * 2 + 1][max_half_support * 2 + 1]
, const cuDoubleComplex src[(max_half_support * 2 + 1) * oversample][(max_half_support * 2 + 1) * oversample]
) {
__SET_MAP
const int
overx = blockIdx.z / oversample
, overy = blockIdx.z % oversample
, sxl = xl * oversample + overx
, sxr = xr * oversample + overx
, syl = yl * oversample + overy
, syr = yr * oversample + overy
;
dst[overx][overy][xl][yl] = src[sxl][syl];
dst[overx][overy][xl][yr] = src[sxl][syr];
dst[overx][overy][xr][yl] = src[sxr][syl];
dst[overx][overy][xr][yr] = src[sxr][syr];
}
extern "C" __global__ void transpose_over0(
cuDoubleComplex dst[8][8][257][257]
, const cuDoubleComplex src[2056][2056]
){
transpose_over<128,8>(dst, src);
}
#endif
template <
int max_half_support
, int oversample
>
__device__ __inline__
void cut_out(
int half_supp
, cuDoubleComplex * dst
, const cuDoubleComplex src[max_half_support * 2 + 1][max_half_support * 2 + 1]
) {
__SET_MAP
const int supp = half_supp * 2 + 1;
if (x > half_supp || y > half_supp) return;
const int
dxl = (half_supp - x) * supp
, dxr = (half_supp + x) * supp
, dyl = half_supp - y
, dyr = half_supp + y
;
dst[dxl + dyl] = src[xl][yl];
dst[dxl + dyr] = src[xl][yr];
dst[dxr + dyl] = src[xr][yl];
dst[dxr + dyr] = src[xr][yr];
}
extern "C" __global__ void wextract1(
int half_supp
, cuDoubleComplex * dst
, const cuDoubleComplex src[257][257]
){
cut_out<128,8>(half_supp, dst, src);
} | .file "tmpxft_001b2090_00000000-6_GCF_odd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z2r2PA257_7double2dPA257_7double2d
.type _Z34__device_stub__Z2r2PA257_7double2dPA257_7double2d, @function
_Z34__device_stub__Z2r2PA257_7double2dPA257_7double2d:
.LFB2079:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movsd %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq r2(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2079:
.size _Z34__device_stub__Z2r2PA257_7double2dPA257_7double2d, .-_Z34__device_stub__Z2r2PA257_7double2dPA257_7double2d
.globl r2
.type r2, @function
r2:
.LFB2080:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z2r2PA257_7double2dPA257_7double2d
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2080:
.size r2, .-r2
.globl _Z48__device_stub__Z7wkernffPA257_7double2PA257_KS_dPA257_7double2PA257_KS_d
.type _Z48__device_stub__Z7wkernffPA257_7double2PA257_KS_dPA257_7double2PA257_KS_d, @function
_Z48__device_stub__Z7wkernffPA257_7double2PA257_KS_dPA257_7double2PA257_KS_d:
.LFB2081:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movsd %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq wkernff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z48__device_stub__Z7wkernffPA257_7double2PA257_KS_dPA257_7double2PA257_KS_d, .-_Z48__device_stub__Z7wkernffPA257_7double2PA257_KS_dPA257_7double2PA257_KS_d
.globl wkernff
.type wkernff, @function
wkernff:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z7wkernffPA257_7double2PA257_KS_dPA257_7double2PA257_KS_d
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size wkernff, .-wkernff
.globl _Z53__device_stub__Z11copy_2_overPA2056_7double2PA257_KS_PA2056_7double2PA257_KS_
.type _Z53__device_stub__Z11copy_2_overPA2056_7double2PA257_KS_PA2056_7double2PA257_KS_, @function
_Z53__device_stub__Z11copy_2_overPA2056_7double2PA257_KS_PA2056_7double2PA257_KS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq copy_2_over(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z53__device_stub__Z11copy_2_overPA2056_7double2PA257_KS_PA2056_7double2PA257_KS_, .-_Z53__device_stub__Z11copy_2_overPA2056_7double2PA257_KS_PA2056_7double2PA257_KS_
.globl copy_2_over
.type copy_2_over, @function
copy_2_over:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z11copy_2_overPA2056_7double2PA257_KS_PA2056_7double2PA257_KS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size copy_2_over, .-copy_2_over
.globl _Z65__device_stub__Z15transpose_over0PA8_A257_A257_7double2PA2056_KS_PA8_A257_A257_7double2PA2056_KS_
.type _Z65__device_stub__Z15transpose_over0PA8_A257_A257_7double2PA2056_KS_PA8_A257_A257_7double2PA2056_KS_, @function
_Z65__device_stub__Z15transpose_over0PA8_A257_A257_7double2PA2056_KS_PA8_A257_A257_7double2PA2056_KS_:
.LFB2085:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq transpose_over0(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z65__device_stub__Z15transpose_over0PA8_A257_A257_7double2PA2056_KS_PA8_A257_A257_7double2PA2056_KS_, .-_Z65__device_stub__Z15transpose_over0PA8_A257_A257_7double2PA2056_KS_PA8_A257_A257_7double2PA2056_KS_
.globl transpose_over0
.type transpose_over0, @function
transpose_over0:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z65__device_stub__Z15transpose_over0PA8_A257_A257_7double2PA2056_KS_PA8_A257_A257_7double2PA2056_KS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size transpose_over0, .-transpose_over0
.globl _Z45__device_stub__Z9wextract1iP7double2PA257_KS_iP7double2PA257_KS_
.type _Z45__device_stub__Z9wextract1iP7double2PA257_KS_iP7double2PA257_KS_, @function
_Z45__device_stub__Z9wextract1iP7double2PA257_KS_iP7double2PA257_KS_:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq wextract1(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z45__device_stub__Z9wextract1iP7double2PA257_KS_iP7double2PA257_KS_, .-_Z45__device_stub__Z9wextract1iP7double2PA257_KS_iP7double2PA257_KS_
.globl wextract1
.type wextract1, @function
wextract1:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z9wextract1iP7double2PA257_KS_iP7double2PA257_KS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size wextract1, .-wextract1
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "wextract1"
.LC1:
.string "transpose_over0"
.LC2:
.string "copy_2_over"
.LC3:
.string "wkernff"
.LC4:
.string "r2"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq wextract1(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq transpose_over0(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq copy_2_over(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq wkernff(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq r2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuComplex.h>
#include <math_constants.h>
// Use symmetry
// Use max_half_support threads only
// Perhaps it's not very cache friendly, but it is
// very simple to perform work-distribution for this variant
#define __SET_MAP \
const int \
x = blockIdx.x * blockDim.x + threadIdx.x \
, y = blockIdx.y * blockDim.y + threadIdx.y \
, xl = max_half_support - x \
, xr = max_half_support + x \
, yl = max_half_support - y \
, yr = max_half_support + y \
;
template <int max_half_support>
__device__ __inline__
void ucs_common(
cuDoubleComplex mesh[max_half_support * 2 + 1][max_half_support * 2 + 1]
, double t2
){
__SET_MAP
double
t2_div_sc = t2 / double(max_half_support)
, xs = double(x) * t2_div_sc
, ys = double(y) * t2_div_sc
;
cuDoubleComplex r2 = make_cuDoubleComplex(xs * xs + ys * ys, 0.0);
mesh[xl][yl] = r2;
mesh[xl][yr] = r2;
mesh[xr][yl] = r2;
mesh[xr][yr] = r2;
}
extern "C" __global__ void r2(cuDoubleComplex mesh[257][257], double t2) {
ucs_common<128>(mesh, t2);
}
#if 0
template <int max_half_support>
__device__
void calc_inplace(
cuDoubleComplex mesh[max_half_support * 2 + 1][max_half_support * 2 + 1]
, double w
){
__SET_MAP
// mesh is symmetric, thus we need no recalc ph
double ph = w * (1.0 - sqrt(1.0 - mesh[xl][yl].x));
double s, c;
sincos(2.0 * CUDART_PI * ph, &s, &c);
cuDoubleComplex res = make_cuDoubleComplex(c, -s); // to get rid of conj later
mesh[xl][yl] = res;
mesh[xl][yr] = res;
mesh[xr][yl] = res;
mesh[xr][yr] = res;
}
// test instantiation
template __device__
void calc_inplace<128>(
cuDoubleComplex mesh[257][257]
, double w
);
#endif
template <int max_half_support>
__device__ __inline__
void calc(
cuDoubleComplex dst[max_half_support * 2 + 1][max_half_support * 2 + 1]
, const cuDoubleComplex src[max_half_support * 2 + 1][max_half_support * 2 + 1]
, double w
){
__SET_MAP
double ph = w * (1.0 - sqrt(1.0 - src[xl][yl].x));
double s, c;
sincos(2.0 * CUDART_PI * ph, &s, &c);
cuDoubleComplex res = make_cuDoubleComplex(c, -s); // to get rid of conj later
dst[xl][yl] = res;
dst[xl][yr] = res;
dst[xr][yl] = res;
dst[xr][yr] = res;
}
extern "C" __global__ void wkernff(
cuDoubleComplex dst[257][257]
, const cuDoubleComplex src[257][257]
, double w
){
calc<128>(dst, src, w);
}
template <
int max_half_support
, int oversample
>
__device__ __inline__
void copy_ucs_2_over(
cuDoubleComplex dst[(max_half_support * 2 + 1) * oversample][(max_half_support * 2 + 1) * oversample]
, const cuDoubleComplex src[max_half_support * 2 + 1][max_half_support * 2 + 1]
){
const int dst_center = (max_half_support * 2 + 1) * oversample / 2;
__SET_MAP
dst[dst_center - x][dst_center - y] = src[xl][yl];
dst[dst_center - x][dst_center + y] = src[xl][yr];
dst[dst_center + x][dst_center - y] = src[xr][yl];
dst[dst_center + x][dst_center + y] = src[xr][yr];
}
extern "C" __global__ void copy_2_over(
cuDoubleComplex dst[2056][2056]
, const cuDoubleComplex src[257][257]
){
copy_ucs_2_over<128,8>(dst, src);
}
#ifdef __SMALL_EXTRACT
template <
int max_half_support
, int oversample
>
__device__ __inline__
void extract_over(
int overx
, int overy
, cuDoubleComplex dst[max_half_support * 2 + 1][max_half_support * 2 + 1]
, const cuDoubleComplex src[(max_half_support * 2 + 1) * oversample][(max_half_support * 2 + 1) * oversample]
) {
__SET_MAP
const int
sxl = xl * oversample + overx
, sxr = xr * oversample + overx
, syl = yl * oversample + overy
, syr = yr * oversample + overy
;
dst[xl][yl] = src[sxl][syl];
dst[xl][yr] = src[sxl][syr];
dst[xr][yl] = src[sxr][syl];
dst[xr][yr] = src[sxr][syr];
}
extern "C" __global__ void wextract0(
int overx
, int overy
, cuDoubleComplex dst[257][257]
, const cuDoubleComplex src[2056][2056]
){
extract_over<128,8>(overx, overy, dst, src);
}
#else
// We use 3rd grid dimension to cover oversample range
template <
int max_half_support
, int oversample
>
__device__ __inline__
void transpose_over(
cuDoubleComplex dst[oversample][oversample][max_half_support * 2 + 1][max_half_support * 2 + 1]
, const cuDoubleComplex src[(max_half_support * 2 + 1) * oversample][(max_half_support * 2 + 1) * oversample]
) {
__SET_MAP
const int
overx = blockIdx.z / oversample
, overy = blockIdx.z % oversample
, sxl = xl * oversample + overx
, sxr = xr * oversample + overx
, syl = yl * oversample + overy
, syr = yr * oversample + overy
;
dst[overx][overy][xl][yl] = src[sxl][syl];
dst[overx][overy][xl][yr] = src[sxl][syr];
dst[overx][overy][xr][yl] = src[sxr][syl];
dst[overx][overy][xr][yr] = src[sxr][syr];
}
extern "C" __global__ void transpose_over0(
cuDoubleComplex dst[8][8][257][257]
, const cuDoubleComplex src[2056][2056]
){
transpose_over<128,8>(dst, src);
}
#endif
template <
int max_half_support
, int oversample
>
__device__ __inline__
void cut_out(
int half_supp
, cuDoubleComplex * dst
, const cuDoubleComplex src[max_half_support * 2 + 1][max_half_support * 2 + 1]
) {
__SET_MAP
const int supp = half_supp * 2 + 1;
if (x > half_supp || y > half_supp) return;
const int
dxl = (half_supp - x) * supp
, dxr = (half_supp + x) * supp
, dyl = half_supp - y
, dyr = half_supp + y
;
dst[dxl + dyl] = src[xl][yl];
dst[dxl + dyr] = src[xl][yr];
dst[dxr + dyl] = src[xr][yl];
dst[dxr + dyr] = src[xr][yr];
}
extern "C" __global__ void wextract1(
int half_supp
, cuDoubleComplex * dst
, const cuDoubleComplex src[257][257]
){
cut_out<128,8>(half_supp, dst, src);
} | #include <hip/hip_runtime.h>
#include <hip/hip_complex.h>
#include <hip/hip_math_constants.h>
// Use symmetry
// Use max_half_support threads only
// Perhaps it's not very cache friendly, but it is
// very simple to perform work-distribution for this variant
#define __SET_MAP \
const int \
x = blockIdx.x * blockDim.x + threadIdx.x \
, y = blockIdx.y * blockDim.y + threadIdx.y \
, xl = max_half_support - x \
, xr = max_half_support + x \
, yl = max_half_support - y \
, yr = max_half_support + y \
;
template <int max_half_support>
__device__ __inline__
void ucs_common(
hipDoubleComplex mesh[max_half_support * 2 + 1][max_half_support * 2 + 1]
, double t2
){
__SET_MAP
double
t2_div_sc = t2 / double(max_half_support)
, xs = double(x) * t2_div_sc
, ys = double(y) * t2_div_sc
;
hipDoubleComplex r2 = make_hipDoubleComplex(xs * xs + ys * ys, 0.0);
mesh[xl][yl] = r2;
mesh[xl][yr] = r2;
mesh[xr][yl] = r2;
mesh[xr][yr] = r2;
}
extern "C" __global__ void r2(hipDoubleComplex mesh[257][257], double t2) {
ucs_common<128>(mesh, t2);
}
#if 0
template <int max_half_support>
__device__
void calc_inplace(
hipDoubleComplex mesh[max_half_support * 2 + 1][max_half_support * 2 + 1]
, double w
){
__SET_MAP
// mesh is symmetric, thus we need no recalc ph
double ph = w * (1.0 - sqrt(1.0 - mesh[xl][yl].x));
double s, c;
sincos(2.0 * HIP_PI * ph, &s, &c);
hipDoubleComplex res = make_hipDoubleComplex(c, -s); // to get rid of conj later
mesh[xl][yl] = res;
mesh[xl][yr] = res;
mesh[xr][yl] = res;
mesh[xr][yr] = res;
}
// test instantiation
template __device__
void calc_inplace<128>(
hipDoubleComplex mesh[257][257]
, double w
);
#endif
template <int max_half_support>
__device__ __inline__
void calc(
hipDoubleComplex dst[max_half_support * 2 + 1][max_half_support * 2 + 1]
, const hipDoubleComplex src[max_half_support * 2 + 1][max_half_support * 2 + 1]
, double w
){
__SET_MAP
double ph = w * (1.0 - sqrt(1.0 - src[xl][yl].x));
double s, c;
sincos(2.0 * HIP_PI * ph, &s, &c);
hipDoubleComplex res = make_hipDoubleComplex(c, -s); // to get rid of conj later
dst[xl][yl] = res;
dst[xl][yr] = res;
dst[xr][yl] = res;
dst[xr][yr] = res;
}
extern "C" __global__ void wkernff(
hipDoubleComplex dst[257][257]
, const hipDoubleComplex src[257][257]
, double w
){
calc<128>(dst, src, w);
}
template <
int max_half_support
, int oversample
>
__device__ __inline__
void copy_ucs_2_over(
hipDoubleComplex dst[(max_half_support * 2 + 1) * oversample][(max_half_support * 2 + 1) * oversample]
, const hipDoubleComplex src[max_half_support * 2 + 1][max_half_support * 2 + 1]
){
const int dst_center = (max_half_support * 2 + 1) * oversample / 2;
__SET_MAP
dst[dst_center - x][dst_center - y] = src[xl][yl];
dst[dst_center - x][dst_center + y] = src[xl][yr];
dst[dst_center + x][dst_center - y] = src[xr][yl];
dst[dst_center + x][dst_center + y] = src[xr][yr];
}
extern "C" __global__ void copy_2_over(
hipDoubleComplex dst[2056][2056]
, const hipDoubleComplex src[257][257]
){
copy_ucs_2_over<128,8>(dst, src);
}
#ifdef __SMALL_EXTRACT
template <
int max_half_support
, int oversample
>
__device__ __inline__
void extract_over(
int overx
, int overy
, hipDoubleComplex dst[max_half_support * 2 + 1][max_half_support * 2 + 1]
, const hipDoubleComplex src[(max_half_support * 2 + 1) * oversample][(max_half_support * 2 + 1) * oversample]
) {
__SET_MAP
const int
sxl = xl * oversample + overx
, sxr = xr * oversample + overx
, syl = yl * oversample + overy
, syr = yr * oversample + overy
;
dst[xl][yl] = src[sxl][syl];
dst[xl][yr] = src[sxl][syr];
dst[xr][yl] = src[sxr][syl];
dst[xr][yr] = src[sxr][syr];
}
extern "C" __global__ void wextract0(
int overx
, int overy
, hipDoubleComplex dst[257][257]
, const hipDoubleComplex src[2056][2056]
){
extract_over<128,8>(overx, overy, dst, src);
}
#else
// We use 3rd grid dimension to cover oversample range
template <
int max_half_support
, int oversample
>
__device__ __inline__
void transpose_over(
hipDoubleComplex dst[oversample][oversample][max_half_support * 2 + 1][max_half_support * 2 + 1]
, const hipDoubleComplex src[(max_half_support * 2 + 1) * oversample][(max_half_support * 2 + 1) * oversample]
) {
__SET_MAP
const int
overx = blockIdx.z / oversample
, overy = blockIdx.z % oversample
, sxl = xl * oversample + overx
, sxr = xr * oversample + overx
, syl = yl * oversample + overy
, syr = yr * oversample + overy
;
dst[overx][overy][xl][yl] = src[sxl][syl];
dst[overx][overy][xl][yr] = src[sxl][syr];
dst[overx][overy][xr][yl] = src[sxr][syl];
dst[overx][overy][xr][yr] = src[sxr][syr];
}
extern "C" __global__ void transpose_over0(
hipDoubleComplex dst[8][8][257][257]
, const hipDoubleComplex src[2056][2056]
){
transpose_over<128,8>(dst, src);
}
#endif
template <
int max_half_support
, int oversample
>
__device__ __inline__
void cut_out(
int half_supp
, hipDoubleComplex * dst
, const hipDoubleComplex src[max_half_support * 2 + 1][max_half_support * 2 + 1]
) {
__SET_MAP
const int supp = half_supp * 2 + 1;
if (x > half_supp || y > half_supp) return;
const int
dxl = (half_supp - x) * supp
, dxr = (half_supp + x) * supp
, dyl = half_supp - y
, dyr = half_supp + y
;
dst[dxl + dyl] = src[xl][yl];
dst[dxl + dyr] = src[xl][yr];
dst[dxr + dyl] = src[xr][yl];
dst[dxr + dyr] = src[xr][yr];
}
extern "C" __global__ void wextract1(
int half_supp
, hipDoubleComplex * dst
, const hipDoubleComplex src[257][257]
){
cut_out<128,8>(half_supp, dst, src);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_complex.h>
#include <hip/hip_math_constants.h>
// Use symmetry
// Use max_half_support threads only
// Perhaps it's not very cache friendly, but it is
// very simple to perform work-distribution for this variant
#define __SET_MAP \
const int \
x = blockIdx.x * blockDim.x + threadIdx.x \
, y = blockIdx.y * blockDim.y + threadIdx.y \
, xl = max_half_support - x \
, xr = max_half_support + x \
, yl = max_half_support - y \
, yr = max_half_support + y \
;
template <int max_half_support>
__device__ __inline__
void ucs_common(
hipDoubleComplex mesh[max_half_support * 2 + 1][max_half_support * 2 + 1]
, double t2
){
__SET_MAP
double
t2_div_sc = t2 / double(max_half_support)
, xs = double(x) * t2_div_sc
, ys = double(y) * t2_div_sc
;
hipDoubleComplex r2 = make_hipDoubleComplex(xs * xs + ys * ys, 0.0);
mesh[xl][yl] = r2;
mesh[xl][yr] = r2;
mesh[xr][yl] = r2;
mesh[xr][yr] = r2;
}
extern "C" __global__ void r2(hipDoubleComplex mesh[257][257], double t2) {
ucs_common<128>(mesh, t2);
}
#if 0
template <int max_half_support>
__device__
void calc_inplace(
hipDoubleComplex mesh[max_half_support * 2 + 1][max_half_support * 2 + 1]
, double w
){
__SET_MAP
// mesh is symmetric, thus we need no recalc ph
double ph = w * (1.0 - sqrt(1.0 - mesh[xl][yl].x));
double s, c;
sincos(2.0 * HIP_PI * ph, &s, &c);
hipDoubleComplex res = make_hipDoubleComplex(c, -s); // to get rid of conj later
mesh[xl][yl] = res;
mesh[xl][yr] = res;
mesh[xr][yl] = res;
mesh[xr][yr] = res;
}
// test instantiation
template __device__
void calc_inplace<128>(
hipDoubleComplex mesh[257][257]
, double w
);
#endif
template <int max_half_support>
__device__ __inline__
void calc(
hipDoubleComplex dst[max_half_support * 2 + 1][max_half_support * 2 + 1]
, const hipDoubleComplex src[max_half_support * 2 + 1][max_half_support * 2 + 1]
, double w
){
__SET_MAP
double ph = w * (1.0 - sqrt(1.0 - src[xl][yl].x));
double s, c;
sincos(2.0 * HIP_PI * ph, &s, &c);
hipDoubleComplex res = make_hipDoubleComplex(c, -s); // to get rid of conj later
dst[xl][yl] = res;
dst[xl][yr] = res;
dst[xr][yl] = res;
dst[xr][yr] = res;
}
extern "C" __global__ void wkernff(
hipDoubleComplex dst[257][257]
, const hipDoubleComplex src[257][257]
, double w
){
calc<128>(dst, src, w);
}
template <
int max_half_support
, int oversample
>
__device__ __inline__
void copy_ucs_2_over(
hipDoubleComplex dst[(max_half_support * 2 + 1) * oversample][(max_half_support * 2 + 1) * oversample]
, const hipDoubleComplex src[max_half_support * 2 + 1][max_half_support * 2 + 1]
){
const int dst_center = (max_half_support * 2 + 1) * oversample / 2;
__SET_MAP
dst[dst_center - x][dst_center - y] = src[xl][yl];
dst[dst_center - x][dst_center + y] = src[xl][yr];
dst[dst_center + x][dst_center - y] = src[xr][yl];
dst[dst_center + x][dst_center + y] = src[xr][yr];
}
extern "C" __global__ void copy_2_over(
hipDoubleComplex dst[2056][2056]
, const hipDoubleComplex src[257][257]
){
copy_ucs_2_over<128,8>(dst, src);
}
#ifdef __SMALL_EXTRACT
template <
int max_half_support
, int oversample
>
__device__ __inline__
void extract_over(
int overx
, int overy
, hipDoubleComplex dst[max_half_support * 2 + 1][max_half_support * 2 + 1]
, const hipDoubleComplex src[(max_half_support * 2 + 1) * oversample][(max_half_support * 2 + 1) * oversample]
) {
__SET_MAP
const int
sxl = xl * oversample + overx
, sxr = xr * oversample + overx
, syl = yl * oversample + overy
, syr = yr * oversample + overy
;
dst[xl][yl] = src[sxl][syl];
dst[xl][yr] = src[sxl][syr];
dst[xr][yl] = src[sxr][syl];
dst[xr][yr] = src[sxr][syr];
}
extern "C" __global__ void wextract0(
int overx
, int overy
, hipDoubleComplex dst[257][257]
, const hipDoubleComplex src[2056][2056]
){
extract_over<128,8>(overx, overy, dst, src);
}
#else
// We use 3rd grid dimension to cover oversample range
template <
int max_half_support
, int oversample
>
__device__ __inline__
void transpose_over(
hipDoubleComplex dst[oversample][oversample][max_half_support * 2 + 1][max_half_support * 2 + 1]
, const hipDoubleComplex src[(max_half_support * 2 + 1) * oversample][(max_half_support * 2 + 1) * oversample]
) {
__SET_MAP
const int
overx = blockIdx.z / oversample
, overy = blockIdx.z % oversample
, sxl = xl * oversample + overx
, sxr = xr * oversample + overx
, syl = yl * oversample + overy
, syr = yr * oversample + overy
;
dst[overx][overy][xl][yl] = src[sxl][syl];
dst[overx][overy][xl][yr] = src[sxl][syr];
dst[overx][overy][xr][yl] = src[sxr][syl];
dst[overx][overy][xr][yr] = src[sxr][syr];
}
extern "C" __global__ void transpose_over0(
hipDoubleComplex dst[8][8][257][257]
, const hipDoubleComplex src[2056][2056]
){
transpose_over<128,8>(dst, src);
}
#endif
template <
int max_half_support
, int oversample
>
__device__ __inline__
void cut_out(
int half_supp
, hipDoubleComplex * dst
, const hipDoubleComplex src[max_half_support * 2 + 1][max_half_support * 2 + 1]
) {
__SET_MAP
const int supp = half_supp * 2 + 1;
if (x > half_supp || y > half_supp) return;
const int
dxl = (half_supp - x) * supp
, dxr = (half_supp + x) * supp
, dyl = half_supp - y
, dyr = half_supp + y
;
dst[dxl + dyl] = src[xl][yl];
dst[dxl + dyr] = src[xl][yr];
dst[dxr + dyl] = src[xr][yl];
dst[dxr + dyr] = src[xr][yr];
}
extern "C" __global__ void wextract1(
int half_supp
, hipDoubleComplex * dst
, const hipDoubleComplex src[257][257]
){
cut_out<128,8>(half_supp, dst, src);
} | .text
.file "GCF_odd.hip"
.globl __device_stub__r2 # -- Begin function __device_stub__r2
.p2align 4, 0x90
.type __device_stub__r2,@function
__device_stub__r2: # @__device_stub__r2
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movsd %xmm0, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $r2, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size __device_stub__r2, .Lfunc_end0-__device_stub__r2
.cfi_endproc
# -- End function
.globl __device_stub__wkernff # -- Begin function __device_stub__wkernff
.p2align 4, 0x90
.type __device_stub__wkernff,@function
__device_stub__wkernff: # @__device_stub__wkernff
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movsd %xmm0, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $wkernff, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size __device_stub__wkernff, .Lfunc_end1-__device_stub__wkernff
.cfi_endproc
# -- End function
.globl __device_stub__copy_2_over # -- Begin function __device_stub__copy_2_over
.p2align 4, 0x90
.type __device_stub__copy_2_over,@function
__device_stub__copy_2_over: # @__device_stub__copy_2_over
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $copy_2_over, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size __device_stub__copy_2_over, .Lfunc_end2-__device_stub__copy_2_over
.cfi_endproc
# -- End function
.globl __device_stub__transpose_over0 # -- Begin function __device_stub__transpose_over0
.p2align 4, 0x90
.type __device_stub__transpose_over0,@function
__device_stub__transpose_over0: # @__device_stub__transpose_over0
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $transpose_over0, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size __device_stub__transpose_over0, .Lfunc_end3-__device_stub__transpose_over0
.cfi_endproc
# -- End function
.globl __device_stub__wextract1 # -- Begin function __device_stub__wextract1
.p2align 4, 0x90
.type __device_stub__wextract1,@function
__device_stub__wextract1: # @__device_stub__wextract1
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $wextract1, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size __device_stub__wextract1, .Lfunc_end4-__device_stub__wextract1
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $r2, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $wkernff, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $copy_2_over, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $transpose_over0, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $wextract1, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type r2,@object # @r2
.section .rodata,"a",@progbits
.globl r2
.p2align 3, 0x0
r2:
.quad __device_stub__r2
.size r2, 8
.type wkernff,@object # @wkernff
.globl wkernff
.p2align 3, 0x0
wkernff:
.quad __device_stub__wkernff
.size wkernff, 8
.type copy_2_over,@object # @copy_2_over
.globl copy_2_over
.p2align 3, 0x0
copy_2_over:
.quad __device_stub__copy_2_over
.size copy_2_over, 8
.type transpose_over0,@object # @transpose_over0
.globl transpose_over0
.p2align 3, 0x0
transpose_over0:
.quad __device_stub__transpose_over0
.size transpose_over0, 8
.type wextract1,@object # @wextract1
.globl wextract1
.p2align 3, 0x0
wextract1:
.quad __device_stub__wextract1
.size wextract1, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "r2"
.size .L__unnamed_1, 3
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "wkernff"
.size .L__unnamed_2, 8
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "copy_2_over"
.size .L__unnamed_3, 12
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "transpose_over0"
.size .L__unnamed_4, 16
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "wextract1"
.size .L__unnamed_5, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__r2
.addrsig_sym __device_stub__wkernff
.addrsig_sym __device_stub__copy_2_over
.addrsig_sym __device_stub__transpose_over0
.addrsig_sym __device_stub__wextract1
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym r2
.addrsig_sym wkernff
.addrsig_sym copy_2_over
.addrsig_sym transpose_over0
.addrsig_sym wextract1
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b2090_00000000-6_GCF_odd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z2r2PA257_7double2dPA257_7double2d
.type _Z34__device_stub__Z2r2PA257_7double2dPA257_7double2d, @function
_Z34__device_stub__Z2r2PA257_7double2dPA257_7double2d:
.LFB2079:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movsd %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq r2(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2079:
.size _Z34__device_stub__Z2r2PA257_7double2dPA257_7double2d, .-_Z34__device_stub__Z2r2PA257_7double2dPA257_7double2d
.globl r2
.type r2, @function
r2:
.LFB2080:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z2r2PA257_7double2dPA257_7double2d
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2080:
.size r2, .-r2
.globl _Z48__device_stub__Z7wkernffPA257_7double2PA257_KS_dPA257_7double2PA257_KS_d
.type _Z48__device_stub__Z7wkernffPA257_7double2PA257_KS_dPA257_7double2PA257_KS_d, @function
_Z48__device_stub__Z7wkernffPA257_7double2PA257_KS_dPA257_7double2PA257_KS_d:
.LFB2081:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movsd %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq wkernff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z48__device_stub__Z7wkernffPA257_7double2PA257_KS_dPA257_7double2PA257_KS_d, .-_Z48__device_stub__Z7wkernffPA257_7double2PA257_KS_dPA257_7double2PA257_KS_d
.globl wkernff
.type wkernff, @function
wkernff:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z7wkernffPA257_7double2PA257_KS_dPA257_7double2PA257_KS_d
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size wkernff, .-wkernff
.globl _Z53__device_stub__Z11copy_2_overPA2056_7double2PA257_KS_PA2056_7double2PA257_KS_
.type _Z53__device_stub__Z11copy_2_overPA2056_7double2PA257_KS_PA2056_7double2PA257_KS_, @function
_Z53__device_stub__Z11copy_2_overPA2056_7double2PA257_KS_PA2056_7double2PA257_KS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq copy_2_over(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z53__device_stub__Z11copy_2_overPA2056_7double2PA257_KS_PA2056_7double2PA257_KS_, .-_Z53__device_stub__Z11copy_2_overPA2056_7double2PA257_KS_PA2056_7double2PA257_KS_
.globl copy_2_over
.type copy_2_over, @function
copy_2_over:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z11copy_2_overPA2056_7double2PA257_KS_PA2056_7double2PA257_KS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size copy_2_over, .-copy_2_over
.globl _Z65__device_stub__Z15transpose_over0PA8_A257_A257_7double2PA2056_KS_PA8_A257_A257_7double2PA2056_KS_
.type _Z65__device_stub__Z15transpose_over0PA8_A257_A257_7double2PA2056_KS_PA8_A257_A257_7double2PA2056_KS_, @function
_Z65__device_stub__Z15transpose_over0PA8_A257_A257_7double2PA2056_KS_PA8_A257_A257_7double2PA2056_KS_:
.LFB2085:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq transpose_over0(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z65__device_stub__Z15transpose_over0PA8_A257_A257_7double2PA2056_KS_PA8_A257_A257_7double2PA2056_KS_, .-_Z65__device_stub__Z15transpose_over0PA8_A257_A257_7double2PA2056_KS_PA8_A257_A257_7double2PA2056_KS_
.globl transpose_over0
.type transpose_over0, @function
transpose_over0:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z65__device_stub__Z15transpose_over0PA8_A257_A257_7double2PA2056_KS_PA8_A257_A257_7double2PA2056_KS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size transpose_over0, .-transpose_over0
.globl _Z45__device_stub__Z9wextract1iP7double2PA257_KS_iP7double2PA257_KS_
.type _Z45__device_stub__Z9wextract1iP7double2PA257_KS_iP7double2PA257_KS_, @function
_Z45__device_stub__Z9wextract1iP7double2PA257_KS_iP7double2PA257_KS_:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq wextract1(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z45__device_stub__Z9wextract1iP7double2PA257_KS_iP7double2PA257_KS_, .-_Z45__device_stub__Z9wextract1iP7double2PA257_KS_iP7double2PA257_KS_
.globl wextract1
.type wextract1, @function
wextract1:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z9wextract1iP7double2PA257_KS_iP7double2PA257_KS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size wextract1, .-wextract1
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "wextract1"
.LC1:
.string "transpose_over0"
.LC2:
.string "copy_2_over"
.LC3:
.string "wkernff"
.LC4:
.string "r2"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq wextract1(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq transpose_over0(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq copy_2_over(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq wkernff(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq r2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "GCF_odd.hip"
.globl __device_stub__r2 # -- Begin function __device_stub__r2
.p2align 4, 0x90
.type __device_stub__r2,@function
__device_stub__r2: # @__device_stub__r2
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movsd %xmm0, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $r2, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size __device_stub__r2, .Lfunc_end0-__device_stub__r2
.cfi_endproc
# -- End function
.globl __device_stub__wkernff # -- Begin function __device_stub__wkernff
.p2align 4, 0x90
.type __device_stub__wkernff,@function
__device_stub__wkernff: # @__device_stub__wkernff
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movsd %xmm0, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $wkernff, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size __device_stub__wkernff, .Lfunc_end1-__device_stub__wkernff
.cfi_endproc
# -- End function
.globl __device_stub__copy_2_over # -- Begin function __device_stub__copy_2_over
.p2align 4, 0x90
.type __device_stub__copy_2_over,@function
__device_stub__copy_2_over: # @__device_stub__copy_2_over
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $copy_2_over, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size __device_stub__copy_2_over, .Lfunc_end2-__device_stub__copy_2_over
.cfi_endproc
# -- End function
.globl __device_stub__transpose_over0 # -- Begin function __device_stub__transpose_over0
.p2align 4, 0x90
.type __device_stub__transpose_over0,@function
__device_stub__transpose_over0: # @__device_stub__transpose_over0
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $transpose_over0, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size __device_stub__transpose_over0, .Lfunc_end3-__device_stub__transpose_over0
.cfi_endproc
# -- End function
.globl __device_stub__wextract1 # -- Begin function __device_stub__wextract1
.p2align 4, 0x90
.type __device_stub__wextract1,@function
__device_stub__wextract1: # @__device_stub__wextract1
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $wextract1, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size __device_stub__wextract1, .Lfunc_end4-__device_stub__wextract1
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $r2, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $wkernff, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $copy_2_over, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $transpose_over0, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $wextract1, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type r2,@object # @r2
.section .rodata,"a",@progbits
.globl r2
.p2align 3, 0x0
r2:
.quad __device_stub__r2
.size r2, 8
.type wkernff,@object # @wkernff
.globl wkernff
.p2align 3, 0x0
wkernff:
.quad __device_stub__wkernff
.size wkernff, 8
.type copy_2_over,@object # @copy_2_over
.globl copy_2_over
.p2align 3, 0x0
copy_2_over:
.quad __device_stub__copy_2_over
.size copy_2_over, 8
.type transpose_over0,@object # @transpose_over0
.globl transpose_over0
.p2align 3, 0x0
transpose_over0:
.quad __device_stub__transpose_over0
.size transpose_over0, 8
.type wextract1,@object # @wextract1
.globl wextract1
.p2align 3, 0x0
wextract1:
.quad __device_stub__wextract1
.size wextract1, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "r2"
.size .L__unnamed_1, 3
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "wkernff"
.size .L__unnamed_2, 8
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "copy_2_over"
.size .L__unnamed_3, 12
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "transpose_over0"
.size .L__unnamed_4, 16
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "wextract1"
.size .L__unnamed_5, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__r2
.addrsig_sym __device_stub__wkernff
.addrsig_sym __device_stub__copy_2_over
.addrsig_sym __device_stub__transpose_over0
.addrsig_sym __device_stub__wextract1
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym r2
.addrsig_sym wkernff
.addrsig_sym copy_2_over
.addrsig_sym transpose_over0
.addrsig_sym wextract1
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kSetSelectedRows(float* target, float* source, float* indices, int nRowIs, int nCols, int nTargetRows){
__shared__ int targetRowIndices[32];
const int startSourceRowI = blockIdx.x * 32;
const int tid = threadIdx.x;
const int localNRowIs = min(32, nRowIs-startSourceRowI);
// cooperatively load 32 row indices
if (tid < localNRowIs){
targetRowIndices[tid] = int(indices[startSourceRowI + tid]);
if (targetRowIndices[tid]<0)
targetRowIndices[tid] += nTargetRows;
if (targetRowIndices[tid]<0 || targetRowIndices[tid]>=nTargetRows)
targetRowIndices[tid] = -1;
}
__syncthreads();
// copy 32 rows
for (int i=0; i<localNRowIs; i++){
const int sourceRowI = startSourceRowI + i, targetRowI = targetRowIndices[i];
for (int colI=tid; colI<nCols; colI+=32)
target[targetRowI * nCols + colI] = targetRowI==-1 ? (1.0/0.0 -1.0/0.0) : source[sourceRowI * nCols + colI];
}
} | code for sm_80
Function : _Z16kSetSelectedRowsPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, -0x20 ; /* 0xffffffe0ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x170 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R2, R5, c[0x0][0x178] ; /* 0x00005e0002007624 */
/* 0x001fca00078e0205 */
/*0070*/ IMNMX R4, R0.reuse, 0x20, PT ; /* 0x0000002000047817 */
/* 0x040fe40003800200 */
/*0080*/ ISETP.GE.AND P1, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe40003f26270 */
/*0090*/ ISETP.GE.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x002fda0003f06270 */
/*00a0*/ @P0 BRA 0x160 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD R6, R2, 0x20, R3 ; /* 0x0000002002067824 */
/* 0x000fe400078e0203 */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*00d0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fcc00078e0207 */
/*00e0*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ F2I.TRUNC.NTZ R0, R6 ; /* 0x0000000600007305 */
/* 0x004e24000020f100 */
/*0100*/ ISETP.GE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f06270 */
/*0110*/ @!P0 IADD3 R0, R0, c[0x0][0x180], RZ ; /* 0x0000600000008a10 */
/* 0x000fc80007ffe0ff */
/*0120*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fc80003f06270 */
/*0130*/ ISETP.GT.AND P0, PT, R0, -0x1, !P0 ; /* 0xffffffff0000780c */
/* 0x000fc80004704270 */
/*0140*/ SEL R0, R0, 0xffffffff, P0 ; /* 0xffffffff00007807 */
/* 0x000fca0000000000 */
/*0150*/ STS [R3.X4], R0 ; /* 0x0000000003007388 */
/* 0x0001e80000004800 */
/*0160*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0170*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0180*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0190*/ LOP3.LUT R5, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff057212 */
/* 0x000fe200078e33ff */
/*01a0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*01b0*/ IADD3 R6, R3, 0x20, RZ ; /* 0x0000002003067810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ IADD3 R5, R5, c[0x0][0x17c], RZ ; /* 0x00005f0005057a10 */
/* 0x000fc40007ffe0ff */
/*01d0*/ IADD3 R7, R3, 0x40, RZ ; /* 0x0000004003077810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ LEA.HI R9, R5, 0x1, RZ, 0x1b ; /* 0x0000000105097811 */
/* 0x000fe400078fd8ff */
/*01f0*/ IADD3 R8, R3, 0x60, RZ ; /* 0x0000006003087810 */
/* 0x000fe40007ffe0ff */
/*0200*/ LOP3.LUT R9, R9, 0x3, RZ, 0xc0, !PT ; /* 0x0000000309097812 */
/* 0x000fe400078ec0ff */
/*0210*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fe20003f06270 */
/*0220*/ BSSY B0, 0x940 ; /* 0x0000071000007945 */
/* 0x000fd80003800000 */
/*0230*/ @P0 BRA 0x930 ; /* 0x000006f000000947 */
/* 0x003fea0003800000 */
/*0240*/ USHF.L.U32 UR5, UR4, 0x2, URZ ; /* 0x0000000204057899 */
/* 0x000fe2000800063f */
/*0250*/ IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; /* 0x00000004ff137424 */
/* 0x000fd000078e00ff */
/*0260*/ LDS R20, [UR5] ; /* 0x00000005ff147984 */
/* 0x000e640008000800 */
/*0270*/ ISETP.NE.AND P0, PT, R20.reuse, -0x1, PT ; /* 0xffffffff1400780c */
/* 0x042fe20003f05270 */
/*0280*/ IMAD R16, R20, c[0x0][0x17c], R3 ; /* 0x00005f0014107a24 */
/* 0x000fc800078e0203 */
/*0290*/ IMAD.WIDE R16, R16, R19, c[0x0][0x160] ; /* 0x0000580010107625 */
/* 0x000fd000078e0213 */
/*02a0*/ @!P0 BRA 0x600 ; /* 0x0000035000008947 */
/* 0x000fea0003800000 */
/*02b0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f05270 */
/*02c0*/ BSSY B1, 0x400 ; /* 0x0000013000017945 */
/* 0x000fe20003800000 */
/*02d0*/ LEA R0, R2, UR4, 0x5 ; /* 0x0000000402007c11 */
/* 0x001fe4000f8e28ff */
/*02e0*/ MOV R15, R3 ; /* 0x00000003000f7202 */
/* 0x000fd20000000f00 */
/*02f0*/ @!P0 BRA 0x3f0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0300*/ IMAD R10, R0, c[0x0][0x17c], R3 ; /* 0x00005f00000a7a24 */
/* 0x000fc800078e0203 */
/*0310*/ IMAD.WIDE R10, R10, R19, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x000fca00078e0213 */
/*0320*/ LDG.E R13, [R10.64] ; /* 0x000000060a0d7981 */
/* 0x000ea2000c1e1900 */
/*0330*/ ISETP.NE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe20003f05270 */
/*0340*/ IMAD.MOV.U32 R15, RZ, RZ, R6 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0006 */
/*0350*/ STG.E [R16.64], R13 ; /* 0x0000000d10007986 */
/* 0x0041f4000c101906 */
/*0360*/ @!P0 BRA 0x3f0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0370*/ LDG.E R13, [R10.64+0x80] ; /* 0x000080060a0d7981 */
/* 0x001ea2000c1e1900 */
/*0380*/ ISETP.NE.AND P0, PT, R9, 0x2, PT ; /* 0x000000020900780c */
/* 0x000fe20003f05270 */
/*0390*/ IMAD.MOV.U32 R15, RZ, RZ, R7 ; /* 0x000000ffff0f7224 */
/* 0x000fc400078e0007 */
/*03a0*/ STG.E [R16.64+0x80], R13 ; /* 0x0000800d10007986 */
/* 0x0041f4000c101906 */
/*03b0*/ @!P0 BRA 0x3f0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*03c0*/ LDG.E R11, [R10.64+0x100] ; /* 0x000100060a0b7981 */
/* 0x000ea2000c1e1900 */
/*03d0*/ IMAD.MOV.U32 R15, RZ, RZ, R8 ; /* 0x000000ffff0f7224 */
/* 0x000fc600078e0008 */
/*03e0*/ STG.E [R16.64+0x100], R11 ; /* 0x0001000b10007986 */
/* 0x0043e8000c101906 */
/*03f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0400*/ ISETP.GE.U32.AND P0, PT, R5, 0x60, PT ; /* 0x000000600500780c */
/* 0x000fe20003f06070 */
/*0410*/ BSSY B1, 0x5f0 ; /* 0x000001d000017945 */
/* 0x000fd80003800000 */
/*0420*/ @!P0 BRA 0x5e0 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0430*/ IMAD R10, R0, c[0x0][0x17c], R15.reuse ; /* 0x00005f00000a7a24 */
/* 0x100fe400078e020f */
/*0440*/ IMAD R27, R20, c[0x0][0x17c], R15 ; /* 0x00005f00141b7a24 */
/* 0x000fe400078e020f */
/*0450*/ IMAD.WIDE R10, R10, R19, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x002fc800078e0213 */
/*0460*/ IMAD.MOV.U32 R14, RZ, RZ, R10 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e000a */
/*0470*/ MOV R17, R11 ; /* 0x0000000b00117202 */
/* 0x001fe20000000f00 */
/*0480*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff007624 */
/* 0x000fe400078e00ff */
/*0490*/ IMAD.MOV.U32 R25, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff197624 */
/* 0x000fe400078e00ff */
/*04a0*/ IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e000e */
/*04b0*/ IMAD.MOV.U32 R11, RZ, RZ, R17 ; /* 0x000000ffff0b7224 */
/* 0x000fca00078e0011 */
/*04c0*/ LDG.E R17, [R10.64] ; /* 0x000000060a117981 */
/* 0x000ea2000c1e1900 */
/*04d0*/ MOV R12, R0 ; /* 0x00000000000c7202 */
/* 0x002fe20000000f00 */
/*04e0*/ IMAD.MOV.U32 R13, RZ, RZ, R25 ; /* 0x000000ffff0d7224 */
/* 0x000fc800078e0019 */
/*04f0*/ IMAD.WIDE R12, R27, 0x4, R12 ; /* 0x000000041b0c7825 */
/* 0x000fca00078e020c */
/*0500*/ STG.E [R12.64], R17 ; /* 0x000000110c007986 */
/* 0x0041e8000c101906 */
/*0510*/ LDG.E R19, [R10.64+0x80] ; /* 0x000080060a137981 */
/* 0x000ea8000c1e1900 */
/*0520*/ STG.E [R12.64+0x80], R19 ; /* 0x000080130c007986 */
/* 0x0043e8000c101906 */
/*0530*/ LDG.E R21, [R10.64+0x100] ; /* 0x000100060a157981 */
/* 0x000ea8000c1e1900 */
/*0540*/ STG.E [R12.64+0x100], R21 ; /* 0x000100150c007986 */
/* 0x0043e8000c101906 */
/*0550*/ LDG.E R23, [R10.64+0x180] ; /* 0x000180060a177981 */
/* 0x000ea2000c1e1900 */
/*0560*/ IADD3 R15, R15, 0x80, RZ ; /* 0x000000800f0f7810 */
/* 0x000fc40007ffe0ff */
/*0570*/ IADD3 R0, P1, R0, 0x200, RZ ; /* 0x0000020000007810 */
/* 0x000fe40007f3e0ff */
/*0580*/ ISETP.GE.AND P0, PT, R15, c[0x0][0x17c], PT ; /* 0x00005f000f007a0c */
/* 0x000fe40003f06270 */
/*0590*/ IADD3 R14, P2, R10, 0x200, RZ ; /* 0x000002000a0e7810 */
/* 0x000fe20007f5e0ff */
/*05a0*/ IMAD.X R25, RZ, RZ, R25, P1 ; /* 0x000000ffff197224 */
/* 0x000fc800008e0619 */
/*05b0*/ IMAD.X R17, RZ, RZ, R11, P2 ; /* 0x000000ffff117224 */
/* 0x001fe200010e060b */
/*05c0*/ STG.E [R12.64+0x180], R23 ; /* 0x000180170c007986 */
/* 0x0043ea000c101906 */
/*05d0*/ @!P0 BRA 0x4a0 ; /* 0xfffffec000008947 */
/* 0x000fea000383ffff */
/*05e0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*05f0*/ BRA 0x930 ; /* 0x0000033000007947 */
/* 0x000fea0003800000 */
/*0600*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f05270 */
/*0610*/ BSSY B1, 0x7f0 ; /* 0x000001d000017945 */
/* 0x000fe20003800000 */
/*0620*/ IMAD.MOV.U32 R21, RZ, RZ, R3 ; /* 0x000000ffff157224 */
/* 0x000fd600078e0003 */
/*0630*/ @!P0 BRA 0x7e0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0640*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe200000001ff */
/*0650*/ ISETP.NE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe20003f05270 */
/*0660*/ IMAD.MOV.U32 R19, RZ, RZ, -0x100000 ; /* 0xfff00000ff137424 */
/* 0x000fe200078e00ff */
/*0670*/ MOV R0, 0x690 ; /* 0x0000069000007802 */
/* 0x001fcc0000000f00 */
/*0680*/ CALL.REL.NOINC 0x980 ; /* 0x000002f000007944 */
/* 0x000fea0003c00000 */
/*0690*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x002fe400078e000c */
/*06a0*/ IMAD.MOV.U32 R11, RZ, RZ, R13 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e000d */
/*06b0*/ IMAD.MOV.U32 R21, RZ, RZ, R6 ; /* 0x000000ffff157224 */
/* 0x000fc800078e0006 */
/*06c0*/ DADD R10, R10, -R10 ; /* 0x000000000a0a7229 */
/* 0x000e14000000080a */
/*06d0*/ F2F.F32.F64 R11, R10 ; /* 0x0000000a000b7310 */
/* 0x001e240000301000 */
/*06e0*/ STG.E [R16.64], R11 ; /* 0x0000000b10007986 */
/* 0x0011e2000c101906 */
/*06f0*/ @!P0 BRA 0x7e0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0700*/ STG.E [R16.64+0x80], R11 ; /* 0x0000800b10007986 */
/* 0x0003e2000c101906 */
/*0710*/ ISETP.NE.AND P0, PT, R9, 0x2, PT ; /* 0x000000020900780c */
/* 0x000fe40003f05270 */
/*0720*/ MOV R21, R7 ; /* 0x0000000700157202 */
/* 0x000fd60000000f00 */
/*0730*/ @!P0 BRA 0x7e0 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*0740*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x002fe200078e00ff */
/*0750*/ MOV R0, 0x780 ; /* 0x0000078000007802 */
/* 0x000fe20000000f00 */
/*0760*/ IMAD.MOV.U32 R19, RZ, RZ, -0x100000 ; /* 0xfff00000ff137424 */
/* 0x000fe400078e00ff */
/*0770*/ CALL.REL.NOINC 0x980 ; /* 0x0000020000007944 */
/* 0x001fea0003c00000 */
/*0780*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x002fe200078e000c */
/*0790*/ MOV R21, R8 ; /* 0x0000000800157202 */
/* 0x000fe20000000f00 */
/*07a0*/ IMAD.MOV.U32 R11, RZ, RZ, R13 ; /* 0x000000ffff0b7224 */
/* 0x000fcc00078e000d */
/*07b0*/ DADD R10, R10, -R10 ; /* 0x000000000a0a7229 */
/* 0x000e14000000080a */
/*07c0*/ F2F.F32.F64 R11, R10 ; /* 0x0000000a000b7310 */
/* 0x001e240000301000 */
/*07d0*/ STG.E [R16.64+0x100], R11 ; /* 0x0001000b10007986 */
/* 0x0011e4000c101906 */
/*07e0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x002fea0003800000 */
/*07f0*/ ISETP.GE.U32.AND P0, PT, R5, 0x60, PT ; /* 0x000000600500780c */
/* 0x000fda0003f06070 */
/*0800*/ @!P0 BRA 0x930 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0810*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x001fe200078e00ff */
/*0820*/ MOV R0, 0x880 ; /* 0x0000088000007802 */
/* 0x000fe20000000f00 */
/*0830*/ IMAD R16, R20, c[0x0][0x17c], R21 ; /* 0x00005f0014107a24 */
/* 0x000fe400078e0215 */
/*0840*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e00ff */
/*0850*/ IMAD.MOV.U32 R19, RZ, RZ, -0x100000 ; /* 0xfff00000ff137424 */
/* 0x000fe400078e00ff */
/*0860*/ IMAD.WIDE R16, R16, R17, c[0x0][0x160] ; /* 0x0000580010107625 */
/* 0x000fc800078e0211 */
/*0870*/ CALL.REL.NOINC 0x980 ; /* 0x0000010000007944 */
/* 0x000fea0003c00000 */
/*0880*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x002fe200078e000c */
/*0890*/ MOV R11, R13 ; /* 0x0000000d000b7202 */
/* 0x000fe40000000f00 */
/*08a0*/ IADD3 R21, R21, 0x80, RZ ; /* 0x0000008015157810 */
/* 0x000fc80007ffe0ff */
/*08b0*/ DADD R10, R10, -R10 ; /* 0x000000000a0a7229 */
/* 0x000e22000000080a */
/*08c0*/ ISETP.GE.AND P0, PT, R21, c[0x0][0x17c], PT ; /* 0x00005f0015007a0c */
/* 0x000fd20003f06270 */
/*08d0*/ F2F.F32.F64 R11, R10 ; /* 0x0000000a000b7310 */
/* 0x001e240000301000 */
/*08e0*/ STG.E [R16.64], R11 ; /* 0x0000000b10007986 */
/* 0x0011e8000c101906 */
/*08f0*/ STG.E [R16.64+0x80], R11 ; /* 0x0000800b10007986 */
/* 0x0001e8000c101906 */
/*0900*/ STG.E [R16.64+0x100], R11 ; /* 0x0001000b10007986 */
/* 0x0001e8000c101906 */
/*0910*/ STG.E [R16.64+0x180], R11 ; /* 0x0001800b10007986 */
/* 0x0001e2000c101906 */
/*0920*/ @!P0 BRA 0x810 ; /* 0xfffffee000008947 */
/* 0x000fea000383ffff */
/*0930*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0940*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fcc000fffe03f */
/*0950*/ ISETP.LE.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fda000bf03270 */
/*0960*/ @!P0 BRA 0x210 ; /* 0xfffff8a000008947 */
/* 0x000fea000383ffff */
/*0970*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0980*/ IMAD.MOV.U32 R11, RZ, RZ, R10 ; /* 0x000000ffff0b7224 */
/* 0x000fcc00078e000a */
/*0990*/ DSETP.GTU.AND P1, PT, |R10|, +INF , PT ; /* 0x7ff000000a00742a */
/* 0x000e1c0003f2c200 */
/*09a0*/ @P1 BRA 0xbb0 ; /* 0x0000020000001947 */
/* 0x001fea0003800000 */
/*09b0*/ LOP3.LUT R14, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0a0e7812 */
/* 0x000fc800078ec0ff */
/*09c0*/ IADD3 R12, R14, -0x1, RZ ; /* 0xffffffff0e0c7810 */
/* 0x000fc80007ffe0ff */
/*09d0*/ ISETP.GE.U32.AND P1, PT, R12, 0x7fefffff, PT ; /* 0x7fefffff0c00780c */
/* 0x000fda0003f26070 */
/*09e0*/ @P1 LOP3.LUT R13, R11, 0x7ff00000, RZ, 0x3c, !PT ; /* 0x7ff000000b0d1812 */
/* 0x000fe200078e3cff */
/*09f0*/ @P1 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c1224 */
/* 0x000fe200078e00ff */
/*0a00*/ @P1 BRA 0xbd0 ; /* 0x000001c000001947 */
/* 0x000fea0003800000 */
/*0a10*/ ISETP.GE.U32.AND P1, PT, R14, 0x1000001, PT ; /* 0x010000010e00780c */
/* 0x000fda0003f26070 */
/*0a20*/ @!P1 BRA 0xb10 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*0a30*/ IADD3 R13, R11, -0x3fe00000, RZ ; /* 0xc02000000b0d7810 */
/* 0x000fe20007ffe0ff */
/*0a40*/ IMAD.MOV.U32 R12, RZ, RZ, R10 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e000a */
/*0a50*/ IMAD.MOV.U32 R14, RZ, RZ, R19 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0013 */
/*0a60*/ MUFU.RCP64H R15, R13 ; /* 0x0000000d000f7308 */
/* 0x000e2a0000001800 */
/*0a70*/ DFMA R18, -R12, R14, 1 ; /* 0x3ff000000c12742b */
/* 0x001e0c000000010e */
/*0a80*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*0a90*/ DFMA R18, R14, R18, R14 ; /* 0x000000120e12722b */
/* 0x001e0c000000000e */
/*0aa0*/ DFMA R14, -R12, R18, 1 ; /* 0x3ff000000c0e742b */
/* 0x001e0c0000000112 */
/*0ab0*/ DFMA R14, R18, R14, R18 ; /* 0x0000000e120e722b */
/* 0x001e0c0000000012 */
/*0ac0*/ DMUL R14, R14, 2.2250738585072013831e-308 ; /* 0x001000000e0e7828 */
/* 0x001e0c0000000000 */
/*0ad0*/ DFMA R10, -R10, R14, 1 ; /* 0x3ff000000a0a742b */
/* 0x001e0c000000010e */
/*0ae0*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0af0*/ DFMA R12, R14, R10, R14 ; /* 0x0000000a0e0c722b */
/* 0x001062000000000e */
/*0b00*/ BRA 0xbd0 ; /* 0x000000c000007947 */
/* 0x000fea0003800000 */
/*0b10*/ DMUL R14, R10, 8.11296384146066816958e+31 ; /* 0x469000000a0e7828 */
/* 0x0000640000000000 */
/*0b20*/ MOV R10, R19 ; /* 0x00000013000a7202 */
/* 0x001fc80000000f00 */
/*0b30*/ MUFU.RCP64H R11, R15 ; /* 0x0000000f000b7308 */
/* 0x002e240000001800 */
/*0b40*/ DFMA R12, -R14, R10, 1 ; /* 0x3ff000000e0c742b */
/* 0x001e0c000000010a */
/*0b50*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*0b60*/ DFMA R12, R10, R12, R10 ; /* 0x0000000c0a0c722b */
/* 0x001e0c000000000a */
/*0b70*/ DFMA R10, -R14, R12, 1 ; /* 0x3ff000000e0a742b */
/* 0x001e0c000000010c */
/*0b80*/ DFMA R10, R12, R10, R12 ; /* 0x0000000a0c0a722b */
/* 0x001e0c000000000c */
/*0b90*/ DMUL R12, R10, 8.11296384146066816958e+31 ; /* 0x469000000a0c7828 */
/* 0x0010620000000000 */
/*0ba0*/ BRA 0xbd0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0bb0*/ LOP3.LUT R13, R11, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000b0d7812 */
/* 0x000fe200078efcff */
/*0bc0*/ IMAD.MOV.U32 R12, RZ, RZ, R10 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e000a */
/*0bd0*/ IMAD.MOV.U32 R10, RZ, RZ, R0 ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e0000 */
/*0be0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; /* 0x00000000ff0b7424 */
/* 0x000fc800078e00ff */
/*0bf0*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff4000a007950 */
/* 0x000fea0003c3ffff */
/*0c00*/ BRA 0xc00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kSetSelectedRows(float* target, float* source, float* indices, int nRowIs, int nCols, int nTargetRows){
__shared__ int targetRowIndices[32];
const int startSourceRowI = blockIdx.x * 32;
const int tid = threadIdx.x;
const int localNRowIs = min(32, nRowIs-startSourceRowI);
// cooperatively load 32 row indices
if (tid < localNRowIs){
targetRowIndices[tid] = int(indices[startSourceRowI + tid]);
if (targetRowIndices[tid]<0)
targetRowIndices[tid] += nTargetRows;
if (targetRowIndices[tid]<0 || targetRowIndices[tid]>=nTargetRows)
targetRowIndices[tid] = -1;
}
__syncthreads();
// copy 32 rows
for (int i=0; i<localNRowIs; i++){
const int sourceRowI = startSourceRowI + i, targetRowI = targetRowIndices[i];
for (int colI=tid; colI<nCols; colI+=32)
target[targetRowI * nCols + colI] = targetRowI==-1 ? (1.0/0.0 -1.0/0.0) : source[sourceRowI * nCols + colI];
}
} | .file "tmpxft_00139fcb_00000000-6_kSetSelectedRows.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z16kSetSelectedRowsPfS_S_iiiPfS_S_iii
.type _Z43__device_stub__Z16kSetSelectedRowsPfS_S_iiiPfS_S_iii, @function
_Z43__device_stub__Z16kSetSelectedRowsPfS_S_iiiPfS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16kSetSelectedRowsPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z16kSetSelectedRowsPfS_S_iiiPfS_S_iii, .-_Z43__device_stub__Z16kSetSelectedRowsPfS_S_iiiPfS_S_iii
.globl _Z16kSetSelectedRowsPfS_S_iii
.type _Z16kSetSelectedRowsPfS_S_iii, @function
_Z16kSetSelectedRowsPfS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z16kSetSelectedRowsPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16kSetSelectedRowsPfS_S_iii, .-_Z16kSetSelectedRowsPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16kSetSelectedRowsPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16kSetSelectedRowsPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kSetSelectedRows(float* target, float* source, float* indices, int nRowIs, int nCols, int nTargetRows){
__shared__ int targetRowIndices[32];
const int startSourceRowI = blockIdx.x * 32;
const int tid = threadIdx.x;
const int localNRowIs = min(32, nRowIs-startSourceRowI);
// cooperatively load 32 row indices
if (tid < localNRowIs){
targetRowIndices[tid] = int(indices[startSourceRowI + tid]);
if (targetRowIndices[tid]<0)
targetRowIndices[tid] += nTargetRows;
if (targetRowIndices[tid]<0 || targetRowIndices[tid]>=nTargetRows)
targetRowIndices[tid] = -1;
}
__syncthreads();
// copy 32 rows
for (int i=0; i<localNRowIs; i++){
const int sourceRowI = startSourceRowI + i, targetRowI = targetRowIndices[i];
for (int colI=tid; colI<nCols; colI+=32)
target[targetRowI * nCols + colI] = targetRowI==-1 ? (1.0/0.0 -1.0/0.0) : source[sourceRowI * nCols + colI];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kSetSelectedRows(float* target, float* source, float* indices, int nRowIs, int nCols, int nTargetRows){
__shared__ int targetRowIndices[32];
const int startSourceRowI = blockIdx.x * 32;
const int tid = threadIdx.x;
const int localNRowIs = min(32, nRowIs-startSourceRowI);
// cooperatively load 32 row indices
if (tid < localNRowIs){
targetRowIndices[tid] = int(indices[startSourceRowI + tid]);
if (targetRowIndices[tid]<0)
targetRowIndices[tid] += nTargetRows;
if (targetRowIndices[tid]<0 || targetRowIndices[tid]>=nTargetRows)
targetRowIndices[tid] = -1;
}
__syncthreads();
// copy 32 rows
for (int i=0; i<localNRowIs; i++){
const int sourceRowI = startSourceRowI + i, targetRowI = targetRowIndices[i];
for (int colI=tid; colI<nCols; colI+=32)
target[targetRowI * nCols + colI] = targetRowI==-1 ? (1.0/0.0 -1.0/0.0) : source[sourceRowI * nCols + colI];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kSetSelectedRows(float* target, float* source, float* indices, int nRowIs, int nCols, int nTargetRows){
__shared__ int targetRowIndices[32];
const int startSourceRowI = blockIdx.x * 32;
const int tid = threadIdx.x;
const int localNRowIs = min(32, nRowIs-startSourceRowI);
// cooperatively load 32 row indices
if (tid < localNRowIs){
targetRowIndices[tid] = int(indices[startSourceRowI + tid]);
if (targetRowIndices[tid]<0)
targetRowIndices[tid] += nTargetRows;
if (targetRowIndices[tid]<0 || targetRowIndices[tid]>=nTargetRows)
targetRowIndices[tid] = -1;
}
__syncthreads();
// copy 32 rows
for (int i=0; i<localNRowIs; i++){
const int sourceRowI = startSourceRowI + i, targetRowI = targetRowIndices[i];
for (int colI=tid; colI<nCols; colI+=32)
target[targetRowI * nCols + colI] = targetRowI==-1 ? (1.0/0.0 -1.0/0.0) : source[sourceRowI * nCols + colI];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16kSetSelectedRowsPfS_S_iii
.globl _Z16kSetSelectedRowsPfS_S_iii
.p2align 8
.type _Z16kSetSelectedRowsPfS_S_iii,@function
_Z16kSetSelectedRowsPfS_S_iii:
s_load_b32 s2, s[0:1], 0x18
s_lshl_b32 s5, s15, 5
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_sub_i32 s3, s2, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_min_i32 s2, s3, 32
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x10
v_add_nc_u32_e32 v1, s5, v0
s_load_b32 s5, s[0:1], 0x20
v_lshlrev_b32_e32 v3, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_and_b32_e32 v2, s5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v2, v1
v_max_i32_e32 v2, -1, v1
v_cmp_gt_i32_e32 vcc_lo, s5, v1
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v1, -1, v2, vcc_lo
ds_store_b32 v3, v1
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_cmp_lt_i32 s3, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_12
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_max_i32 s8, s2, 1
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s0, s3, v0
s_mul_i32 s15, s15, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s9, s15, 5
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s11, s0
s_cbranch_execz .LBB0_10
s_lshl_b32 s1, s10, 2
s_mov_b32 s12, 0
v_mov_b32_e32 v1, s1
ds_load_b32 v2, v1
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, v2, s3
v_cmp_ne_u32_e64 s1, -1, v2
v_mov_b32_e32 v2, v0
s_branch .LBB0_8
.p2align 6
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, s9, v2
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v3, v[3:4], off
.LBB0_7:
v_add_nc_u32_e32 v4, v1, v2
v_add_nc_u32_e32 v2, 32, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_cmp_le_i32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_or_b32 s12, vcc_lo, s12
v_add_co_u32 v4, s2, s4, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s2, s5, v5, s2
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v3, off
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB0_10
.LBB0_8:
s_delay_alu instid0(VALU_DEP_2)
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccz .LBB0_6
v_mov_b32_e32 v3, 0x7fc00000
s_branch .LBB0_7
.p2align 6
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s11
s_add_i32 s10, s10, 1
s_add_i32 s9, s9, s3
s_cmp_eq_u32 s10, s8
s_cbranch_scc0 .LBB0_4
.LBB0_12:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16kSetSelectedRowsPfS_S_iii
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16kSetSelectedRowsPfS_S_iii, .Lfunc_end0-_Z16kSetSelectedRowsPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16kSetSelectedRowsPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16kSetSelectedRowsPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kSetSelectedRows(float* target, float* source, float* indices, int nRowIs, int nCols, int nTargetRows){
__shared__ int targetRowIndices[32];
const int startSourceRowI = blockIdx.x * 32;
const int tid = threadIdx.x;
const int localNRowIs = min(32, nRowIs-startSourceRowI);
// cooperatively load 32 row indices
if (tid < localNRowIs){
targetRowIndices[tid] = int(indices[startSourceRowI + tid]);
if (targetRowIndices[tid]<0)
targetRowIndices[tid] += nTargetRows;
if (targetRowIndices[tid]<0 || targetRowIndices[tid]>=nTargetRows)
targetRowIndices[tid] = -1;
}
__syncthreads();
// copy 32 rows
for (int i=0; i<localNRowIs; i++){
const int sourceRowI = startSourceRowI + i, targetRowI = targetRowIndices[i];
for (int colI=tid; colI<nCols; colI+=32)
target[targetRowI * nCols + colI] = targetRowI==-1 ? (1.0/0.0 -1.0/0.0) : source[sourceRowI * nCols + colI];
}
} | .text
.file "kSetSelectedRows.hip"
.globl _Z31__device_stub__kSetSelectedRowsPfS_S_iii # -- Begin function _Z31__device_stub__kSetSelectedRowsPfS_S_iii
.p2align 4, 0x90
.type _Z31__device_stub__kSetSelectedRowsPfS_S_iii,@function
_Z31__device_stub__kSetSelectedRowsPfS_S_iii: # @_Z31__device_stub__kSetSelectedRowsPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16kSetSelectedRowsPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z31__device_stub__kSetSelectedRowsPfS_S_iii, .Lfunc_end0-_Z31__device_stub__kSetSelectedRowsPfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16kSetSelectedRowsPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16kSetSelectedRowsPfS_S_iii,@object # @_Z16kSetSelectedRowsPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z16kSetSelectedRowsPfS_S_iii
.p2align 3, 0x0
_Z16kSetSelectedRowsPfS_S_iii:
.quad _Z31__device_stub__kSetSelectedRowsPfS_S_iii
.size _Z16kSetSelectedRowsPfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16kSetSelectedRowsPfS_S_iii"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__kSetSelectedRowsPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16kSetSelectedRowsPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16kSetSelectedRowsPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, -0x20 ; /* 0xffffffe0ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x170 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R2, R5, c[0x0][0x178] ; /* 0x00005e0002007624 */
/* 0x001fca00078e0205 */
/*0070*/ IMNMX R4, R0.reuse, 0x20, PT ; /* 0x0000002000047817 */
/* 0x040fe40003800200 */
/*0080*/ ISETP.GE.AND P1, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe40003f26270 */
/*0090*/ ISETP.GE.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x002fda0003f06270 */
/*00a0*/ @P0 BRA 0x160 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD R6, R2, 0x20, R3 ; /* 0x0000002002067824 */
/* 0x000fe400078e0203 */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*00d0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fcc00078e0207 */
/*00e0*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ F2I.TRUNC.NTZ R0, R6 ; /* 0x0000000600007305 */
/* 0x004e24000020f100 */
/*0100*/ ISETP.GE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f06270 */
/*0110*/ @!P0 IADD3 R0, R0, c[0x0][0x180], RZ ; /* 0x0000600000008a10 */
/* 0x000fc80007ffe0ff */
/*0120*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fc80003f06270 */
/*0130*/ ISETP.GT.AND P0, PT, R0, -0x1, !P0 ; /* 0xffffffff0000780c */
/* 0x000fc80004704270 */
/*0140*/ SEL R0, R0, 0xffffffff, P0 ; /* 0xffffffff00007807 */
/* 0x000fca0000000000 */
/*0150*/ STS [R3.X4], R0 ; /* 0x0000000003007388 */
/* 0x0001e80000004800 */
/*0160*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0170*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0180*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0190*/ LOP3.LUT R5, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff057212 */
/* 0x000fe200078e33ff */
/*01a0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*01b0*/ IADD3 R6, R3, 0x20, RZ ; /* 0x0000002003067810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ IADD3 R5, R5, c[0x0][0x17c], RZ ; /* 0x00005f0005057a10 */
/* 0x000fc40007ffe0ff */
/*01d0*/ IADD3 R7, R3, 0x40, RZ ; /* 0x0000004003077810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ LEA.HI R9, R5, 0x1, RZ, 0x1b ; /* 0x0000000105097811 */
/* 0x000fe400078fd8ff */
/*01f0*/ IADD3 R8, R3, 0x60, RZ ; /* 0x0000006003087810 */
/* 0x000fe40007ffe0ff */
/*0200*/ LOP3.LUT R9, R9, 0x3, RZ, 0xc0, !PT ; /* 0x0000000309097812 */
/* 0x000fe400078ec0ff */
/*0210*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fe20003f06270 */
/*0220*/ BSSY B0, 0x940 ; /* 0x0000071000007945 */
/* 0x000fd80003800000 */
/*0230*/ @P0 BRA 0x930 ; /* 0x000006f000000947 */
/* 0x003fea0003800000 */
/*0240*/ USHF.L.U32 UR5, UR4, 0x2, URZ ; /* 0x0000000204057899 */
/* 0x000fe2000800063f */
/*0250*/ IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; /* 0x00000004ff137424 */
/* 0x000fd000078e00ff */
/*0260*/ LDS R20, [UR5] ; /* 0x00000005ff147984 */
/* 0x000e640008000800 */
/*0270*/ ISETP.NE.AND P0, PT, R20.reuse, -0x1, PT ; /* 0xffffffff1400780c */
/* 0x042fe20003f05270 */
/*0280*/ IMAD R16, R20, c[0x0][0x17c], R3 ; /* 0x00005f0014107a24 */
/* 0x000fc800078e0203 */
/*0290*/ IMAD.WIDE R16, R16, R19, c[0x0][0x160] ; /* 0x0000580010107625 */
/* 0x000fd000078e0213 */
/*02a0*/ @!P0 BRA 0x600 ; /* 0x0000035000008947 */
/* 0x000fea0003800000 */
/*02b0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f05270 */
/*02c0*/ BSSY B1, 0x400 ; /* 0x0000013000017945 */
/* 0x000fe20003800000 */
/*02d0*/ LEA R0, R2, UR4, 0x5 ; /* 0x0000000402007c11 */
/* 0x001fe4000f8e28ff */
/*02e0*/ MOV R15, R3 ; /* 0x00000003000f7202 */
/* 0x000fd20000000f00 */
/*02f0*/ @!P0 BRA 0x3f0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0300*/ IMAD R10, R0, c[0x0][0x17c], R3 ; /* 0x00005f00000a7a24 */
/* 0x000fc800078e0203 */
/*0310*/ IMAD.WIDE R10, R10, R19, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x000fca00078e0213 */
/*0320*/ LDG.E R13, [R10.64] ; /* 0x000000060a0d7981 */
/* 0x000ea2000c1e1900 */
/*0330*/ ISETP.NE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe20003f05270 */
/*0340*/ IMAD.MOV.U32 R15, RZ, RZ, R6 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0006 */
/*0350*/ STG.E [R16.64], R13 ; /* 0x0000000d10007986 */
/* 0x0041f4000c101906 */
/*0360*/ @!P0 BRA 0x3f0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0370*/ LDG.E R13, [R10.64+0x80] ; /* 0x000080060a0d7981 */
/* 0x001ea2000c1e1900 */
/*0380*/ ISETP.NE.AND P0, PT, R9, 0x2, PT ; /* 0x000000020900780c */
/* 0x000fe20003f05270 */
/*0390*/ IMAD.MOV.U32 R15, RZ, RZ, R7 ; /* 0x000000ffff0f7224 */
/* 0x000fc400078e0007 */
/*03a0*/ STG.E [R16.64+0x80], R13 ; /* 0x0000800d10007986 */
/* 0x0041f4000c101906 */
/*03b0*/ @!P0 BRA 0x3f0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*03c0*/ LDG.E R11, [R10.64+0x100] ; /* 0x000100060a0b7981 */
/* 0x000ea2000c1e1900 */
/*03d0*/ IMAD.MOV.U32 R15, RZ, RZ, R8 ; /* 0x000000ffff0f7224 */
/* 0x000fc600078e0008 */
/*03e0*/ STG.E [R16.64+0x100], R11 ; /* 0x0001000b10007986 */
/* 0x0043e8000c101906 */
/*03f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0400*/ ISETP.GE.U32.AND P0, PT, R5, 0x60, PT ; /* 0x000000600500780c */
/* 0x000fe20003f06070 */
/*0410*/ BSSY B1, 0x5f0 ; /* 0x000001d000017945 */
/* 0x000fd80003800000 */
/*0420*/ @!P0 BRA 0x5e0 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0430*/ IMAD R10, R0, c[0x0][0x17c], R15.reuse ; /* 0x00005f00000a7a24 */
/* 0x100fe400078e020f */
/*0440*/ IMAD R27, R20, c[0x0][0x17c], R15 ; /* 0x00005f00141b7a24 */
/* 0x000fe400078e020f */
/*0450*/ IMAD.WIDE R10, R10, R19, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x002fc800078e0213 */
/*0460*/ IMAD.MOV.U32 R14, RZ, RZ, R10 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e000a */
/*0470*/ MOV R17, R11 ; /* 0x0000000b00117202 */
/* 0x001fe20000000f00 */
/*0480*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff007624 */
/* 0x000fe400078e00ff */
/*0490*/ IMAD.MOV.U32 R25, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff197624 */
/* 0x000fe400078e00ff */
/*04a0*/ IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e000e */
/*04b0*/ IMAD.MOV.U32 R11, RZ, RZ, R17 ; /* 0x000000ffff0b7224 */
/* 0x000fca00078e0011 */
/*04c0*/ LDG.E R17, [R10.64] ; /* 0x000000060a117981 */
/* 0x000ea2000c1e1900 */
/*04d0*/ MOV R12, R0 ; /* 0x00000000000c7202 */
/* 0x002fe20000000f00 */
/*04e0*/ IMAD.MOV.U32 R13, RZ, RZ, R25 ; /* 0x000000ffff0d7224 */
/* 0x000fc800078e0019 */
/*04f0*/ IMAD.WIDE R12, R27, 0x4, R12 ; /* 0x000000041b0c7825 */
/* 0x000fca00078e020c */
/*0500*/ STG.E [R12.64], R17 ; /* 0x000000110c007986 */
/* 0x0041e8000c101906 */
/*0510*/ LDG.E R19, [R10.64+0x80] ; /* 0x000080060a137981 */
/* 0x000ea8000c1e1900 */
/*0520*/ STG.E [R12.64+0x80], R19 ; /* 0x000080130c007986 */
/* 0x0043e8000c101906 */
/*0530*/ LDG.E R21, [R10.64+0x100] ; /* 0x000100060a157981 */
/* 0x000ea8000c1e1900 */
/*0540*/ STG.E [R12.64+0x100], R21 ; /* 0x000100150c007986 */
/* 0x0043e8000c101906 */
/*0550*/ LDG.E R23, [R10.64+0x180] ; /* 0x000180060a177981 */
/* 0x000ea2000c1e1900 */
/*0560*/ IADD3 R15, R15, 0x80, RZ ; /* 0x000000800f0f7810 */
/* 0x000fc40007ffe0ff */
/*0570*/ IADD3 R0, P1, R0, 0x200, RZ ; /* 0x0000020000007810 */
/* 0x000fe40007f3e0ff */
/*0580*/ ISETP.GE.AND P0, PT, R15, c[0x0][0x17c], PT ; /* 0x00005f000f007a0c */
/* 0x000fe40003f06270 */
/*0590*/ IADD3 R14, P2, R10, 0x200, RZ ; /* 0x000002000a0e7810 */
/* 0x000fe20007f5e0ff */
/*05a0*/ IMAD.X R25, RZ, RZ, R25, P1 ; /* 0x000000ffff197224 */
/* 0x000fc800008e0619 */
/*05b0*/ IMAD.X R17, RZ, RZ, R11, P2 ; /* 0x000000ffff117224 */
/* 0x001fe200010e060b */
/*05c0*/ STG.E [R12.64+0x180], R23 ; /* 0x000180170c007986 */
/* 0x0043ea000c101906 */
/*05d0*/ @!P0 BRA 0x4a0 ; /* 0xfffffec000008947 */
/* 0x000fea000383ffff */
/*05e0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*05f0*/ BRA 0x930 ; /* 0x0000033000007947 */
/* 0x000fea0003800000 */
/*0600*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f05270 */
/*0610*/ BSSY B1, 0x7f0 ; /* 0x000001d000017945 */
/* 0x000fe20003800000 */
/*0620*/ IMAD.MOV.U32 R21, RZ, RZ, R3 ; /* 0x000000ffff157224 */
/* 0x000fd600078e0003 */
/*0630*/ @!P0 BRA 0x7e0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0640*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe200000001ff */
/*0650*/ ISETP.NE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe20003f05270 */
/*0660*/ IMAD.MOV.U32 R19, RZ, RZ, -0x100000 ; /* 0xfff00000ff137424 */
/* 0x000fe200078e00ff */
/*0670*/ MOV R0, 0x690 ; /* 0x0000069000007802 */
/* 0x001fcc0000000f00 */
/*0680*/ CALL.REL.NOINC 0x980 ; /* 0x000002f000007944 */
/* 0x000fea0003c00000 */
/*0690*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x002fe400078e000c */
/*06a0*/ IMAD.MOV.U32 R11, RZ, RZ, R13 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e000d */
/*06b0*/ IMAD.MOV.U32 R21, RZ, RZ, R6 ; /* 0x000000ffff157224 */
/* 0x000fc800078e0006 */
/*06c0*/ DADD R10, R10, -R10 ; /* 0x000000000a0a7229 */
/* 0x000e14000000080a */
/*06d0*/ F2F.F32.F64 R11, R10 ; /* 0x0000000a000b7310 */
/* 0x001e240000301000 */
/*06e0*/ STG.E [R16.64], R11 ; /* 0x0000000b10007986 */
/* 0x0011e2000c101906 */
/*06f0*/ @!P0 BRA 0x7e0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0700*/ STG.E [R16.64+0x80], R11 ; /* 0x0000800b10007986 */
/* 0x0003e2000c101906 */
/*0710*/ ISETP.NE.AND P0, PT, R9, 0x2, PT ; /* 0x000000020900780c */
/* 0x000fe40003f05270 */
/*0720*/ MOV R21, R7 ; /* 0x0000000700157202 */
/* 0x000fd60000000f00 */
/*0730*/ @!P0 BRA 0x7e0 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*0740*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x002fe200078e00ff */
/*0750*/ MOV R0, 0x780 ; /* 0x0000078000007802 */
/* 0x000fe20000000f00 */
/*0760*/ IMAD.MOV.U32 R19, RZ, RZ, -0x100000 ; /* 0xfff00000ff137424 */
/* 0x000fe400078e00ff */
/*0770*/ CALL.REL.NOINC 0x980 ; /* 0x0000020000007944 */
/* 0x001fea0003c00000 */
/*0780*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x002fe200078e000c */
/*0790*/ MOV R21, R8 ; /* 0x0000000800157202 */
/* 0x000fe20000000f00 */
/*07a0*/ IMAD.MOV.U32 R11, RZ, RZ, R13 ; /* 0x000000ffff0b7224 */
/* 0x000fcc00078e000d */
/*07b0*/ DADD R10, R10, -R10 ; /* 0x000000000a0a7229 */
/* 0x000e14000000080a */
/*07c0*/ F2F.F32.F64 R11, R10 ; /* 0x0000000a000b7310 */
/* 0x001e240000301000 */
/*07d0*/ STG.E [R16.64+0x100], R11 ; /* 0x0001000b10007986 */
/* 0x0011e4000c101906 */
/*07e0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x002fea0003800000 */
/*07f0*/ ISETP.GE.U32.AND P0, PT, R5, 0x60, PT ; /* 0x000000600500780c */
/* 0x000fda0003f06070 */
/*0800*/ @!P0 BRA 0x930 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0810*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x001fe200078e00ff */
/*0820*/ MOV R0, 0x880 ; /* 0x0000088000007802 */
/* 0x000fe20000000f00 */
/*0830*/ IMAD R16, R20, c[0x0][0x17c], R21 ; /* 0x00005f0014107a24 */
/* 0x000fe400078e0215 */
/*0840*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e00ff */
/*0850*/ IMAD.MOV.U32 R19, RZ, RZ, -0x100000 ; /* 0xfff00000ff137424 */
/* 0x000fe400078e00ff */
/*0860*/ IMAD.WIDE R16, R16, R17, c[0x0][0x160] ; /* 0x0000580010107625 */
/* 0x000fc800078e0211 */
/*0870*/ CALL.REL.NOINC 0x980 ; /* 0x0000010000007944 */
/* 0x000fea0003c00000 */
/*0880*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x002fe200078e000c */
/*0890*/ MOV R11, R13 ; /* 0x0000000d000b7202 */
/* 0x000fe40000000f00 */
/*08a0*/ IADD3 R21, R21, 0x80, RZ ; /* 0x0000008015157810 */
/* 0x000fc80007ffe0ff */
/*08b0*/ DADD R10, R10, -R10 ; /* 0x000000000a0a7229 */
/* 0x000e22000000080a */
/*08c0*/ ISETP.GE.AND P0, PT, R21, c[0x0][0x17c], PT ; /* 0x00005f0015007a0c */
/* 0x000fd20003f06270 */
/*08d0*/ F2F.F32.F64 R11, R10 ; /* 0x0000000a000b7310 */
/* 0x001e240000301000 */
/*08e0*/ STG.E [R16.64], R11 ; /* 0x0000000b10007986 */
/* 0x0011e8000c101906 */
/*08f0*/ STG.E [R16.64+0x80], R11 ; /* 0x0000800b10007986 */
/* 0x0001e8000c101906 */
/*0900*/ STG.E [R16.64+0x100], R11 ; /* 0x0001000b10007986 */
/* 0x0001e8000c101906 */
/*0910*/ STG.E [R16.64+0x180], R11 ; /* 0x0001800b10007986 */
/* 0x0001e2000c101906 */
/*0920*/ @!P0 BRA 0x810 ; /* 0xfffffee000008947 */
/* 0x000fea000383ffff */
/*0930*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0940*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fcc000fffe03f */
/*0950*/ ISETP.LE.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fda000bf03270 */
/*0960*/ @!P0 BRA 0x210 ; /* 0xfffff8a000008947 */
/* 0x000fea000383ffff */
/*0970*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0980*/ IMAD.MOV.U32 R11, RZ, RZ, R10 ; /* 0x000000ffff0b7224 */
/* 0x000fcc00078e000a */
/*0990*/ DSETP.GTU.AND P1, PT, |R10|, +INF , PT ; /* 0x7ff000000a00742a */
/* 0x000e1c0003f2c200 */
/*09a0*/ @P1 BRA 0xbb0 ; /* 0x0000020000001947 */
/* 0x001fea0003800000 */
/*09b0*/ LOP3.LUT R14, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0a0e7812 */
/* 0x000fc800078ec0ff */
/*09c0*/ IADD3 R12, R14, -0x1, RZ ; /* 0xffffffff0e0c7810 */
/* 0x000fc80007ffe0ff */
/*09d0*/ ISETP.GE.U32.AND P1, PT, R12, 0x7fefffff, PT ; /* 0x7fefffff0c00780c */
/* 0x000fda0003f26070 */
/*09e0*/ @P1 LOP3.LUT R13, R11, 0x7ff00000, RZ, 0x3c, !PT ; /* 0x7ff000000b0d1812 */
/* 0x000fe200078e3cff */
/*09f0*/ @P1 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c1224 */
/* 0x000fe200078e00ff */
/*0a00*/ @P1 BRA 0xbd0 ; /* 0x000001c000001947 */
/* 0x000fea0003800000 */
/*0a10*/ ISETP.GE.U32.AND P1, PT, R14, 0x1000001, PT ; /* 0x010000010e00780c */
/* 0x000fda0003f26070 */
/*0a20*/ @!P1 BRA 0xb10 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*0a30*/ IADD3 R13, R11, -0x3fe00000, RZ ; /* 0xc02000000b0d7810 */
/* 0x000fe20007ffe0ff */
/*0a40*/ IMAD.MOV.U32 R12, RZ, RZ, R10 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e000a */
/*0a50*/ IMAD.MOV.U32 R14, RZ, RZ, R19 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0013 */
/*0a60*/ MUFU.RCP64H R15, R13 ; /* 0x0000000d000f7308 */
/* 0x000e2a0000001800 */
/*0a70*/ DFMA R18, -R12, R14, 1 ; /* 0x3ff000000c12742b */
/* 0x001e0c000000010e */
/*0a80*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*0a90*/ DFMA R18, R14, R18, R14 ; /* 0x000000120e12722b */
/* 0x001e0c000000000e */
/*0aa0*/ DFMA R14, -R12, R18, 1 ; /* 0x3ff000000c0e742b */
/* 0x001e0c0000000112 */
/*0ab0*/ DFMA R14, R18, R14, R18 ; /* 0x0000000e120e722b */
/* 0x001e0c0000000012 */
/*0ac0*/ DMUL R14, R14, 2.2250738585072013831e-308 ; /* 0x001000000e0e7828 */
/* 0x001e0c0000000000 */
/*0ad0*/ DFMA R10, -R10, R14, 1 ; /* 0x3ff000000a0a742b */
/* 0x001e0c000000010e */
/*0ae0*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0af0*/ DFMA R12, R14, R10, R14 ; /* 0x0000000a0e0c722b */
/* 0x001062000000000e */
/*0b00*/ BRA 0xbd0 ; /* 0x000000c000007947 */
/* 0x000fea0003800000 */
/*0b10*/ DMUL R14, R10, 8.11296384146066816958e+31 ; /* 0x469000000a0e7828 */
/* 0x0000640000000000 */
/*0b20*/ MOV R10, R19 ; /* 0x00000013000a7202 */
/* 0x001fc80000000f00 */
/*0b30*/ MUFU.RCP64H R11, R15 ; /* 0x0000000f000b7308 */
/* 0x002e240000001800 */
/*0b40*/ DFMA R12, -R14, R10, 1 ; /* 0x3ff000000e0c742b */
/* 0x001e0c000000010a */
/*0b50*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*0b60*/ DFMA R12, R10, R12, R10 ; /* 0x0000000c0a0c722b */
/* 0x001e0c000000000a */
/*0b70*/ DFMA R10, -R14, R12, 1 ; /* 0x3ff000000e0a742b */
/* 0x001e0c000000010c */
/*0b80*/ DFMA R10, R12, R10, R12 ; /* 0x0000000a0c0a722b */
/* 0x001e0c000000000c */
/*0b90*/ DMUL R12, R10, 8.11296384146066816958e+31 ; /* 0x469000000a0c7828 */
/* 0x0010620000000000 */
/*0ba0*/ BRA 0xbd0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0bb0*/ LOP3.LUT R13, R11, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000b0d7812 */
/* 0x000fe200078efcff */
/*0bc0*/ IMAD.MOV.U32 R12, RZ, RZ, R10 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e000a */
/*0bd0*/ IMAD.MOV.U32 R10, RZ, RZ, R0 ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e0000 */
/*0be0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; /* 0x00000000ff0b7424 */
/* 0x000fc800078e00ff */
/*0bf0*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff4000a007950 */
/* 0x000fea0003c3ffff */
/*0c00*/ BRA 0xc00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16kSetSelectedRowsPfS_S_iii
.globl _Z16kSetSelectedRowsPfS_S_iii
.p2align 8
.type _Z16kSetSelectedRowsPfS_S_iii,@function
_Z16kSetSelectedRowsPfS_S_iii:
s_load_b32 s2, s[0:1], 0x18
s_lshl_b32 s5, s15, 5
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_sub_i32 s3, s2, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_min_i32 s2, s3, 32
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x10
v_add_nc_u32_e32 v1, s5, v0
s_load_b32 s5, s[0:1], 0x20
v_lshlrev_b32_e32 v3, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_and_b32_e32 v2, s5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v2, v1
v_max_i32_e32 v2, -1, v1
v_cmp_gt_i32_e32 vcc_lo, s5, v1
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v1, -1, v2, vcc_lo
ds_store_b32 v3, v1
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_cmp_lt_i32 s3, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_12
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_max_i32 s8, s2, 1
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s0, s3, v0
s_mul_i32 s15, s15, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s9, s15, 5
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s11, s0
s_cbranch_execz .LBB0_10
s_lshl_b32 s1, s10, 2
s_mov_b32 s12, 0
v_mov_b32_e32 v1, s1
ds_load_b32 v2, v1
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, v2, s3
v_cmp_ne_u32_e64 s1, -1, v2
v_mov_b32_e32 v2, v0
s_branch .LBB0_8
.p2align 6
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, s9, v2
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v3, v[3:4], off
.LBB0_7:
v_add_nc_u32_e32 v4, v1, v2
v_add_nc_u32_e32 v2, 32, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_cmp_le_i32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_or_b32 s12, vcc_lo, s12
v_add_co_u32 v4, s2, s4, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s2, s5, v5, s2
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v3, off
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB0_10
.LBB0_8:
s_delay_alu instid0(VALU_DEP_2)
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccz .LBB0_6
v_mov_b32_e32 v3, 0x7fc00000
s_branch .LBB0_7
.p2align 6
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s11
s_add_i32 s10, s10, 1
s_add_i32 s9, s9, s3
s_cmp_eq_u32 s10, s8
s_cbranch_scc0 .LBB0_4
.LBB0_12:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16kSetSelectedRowsPfS_S_iii
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16kSetSelectedRowsPfS_S_iii, .Lfunc_end0-_Z16kSetSelectedRowsPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16kSetSelectedRowsPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16kSetSelectedRowsPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00139fcb_00000000-6_kSetSelectedRows.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z16kSetSelectedRowsPfS_S_iiiPfS_S_iii
.type _Z43__device_stub__Z16kSetSelectedRowsPfS_S_iiiPfS_S_iii, @function
_Z43__device_stub__Z16kSetSelectedRowsPfS_S_iiiPfS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16kSetSelectedRowsPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z16kSetSelectedRowsPfS_S_iiiPfS_S_iii, .-_Z43__device_stub__Z16kSetSelectedRowsPfS_S_iiiPfS_S_iii
.globl _Z16kSetSelectedRowsPfS_S_iii
.type _Z16kSetSelectedRowsPfS_S_iii, @function
_Z16kSetSelectedRowsPfS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z16kSetSelectedRowsPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16kSetSelectedRowsPfS_S_iii, .-_Z16kSetSelectedRowsPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16kSetSelectedRowsPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16kSetSelectedRowsPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kSetSelectedRows.hip"
.globl _Z31__device_stub__kSetSelectedRowsPfS_S_iii # -- Begin function _Z31__device_stub__kSetSelectedRowsPfS_S_iii
.p2align 4, 0x90
.type _Z31__device_stub__kSetSelectedRowsPfS_S_iii,@function
_Z31__device_stub__kSetSelectedRowsPfS_S_iii: # @_Z31__device_stub__kSetSelectedRowsPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16kSetSelectedRowsPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z31__device_stub__kSetSelectedRowsPfS_S_iii, .Lfunc_end0-_Z31__device_stub__kSetSelectedRowsPfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16kSetSelectedRowsPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16kSetSelectedRowsPfS_S_iii,@object # @_Z16kSetSelectedRowsPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z16kSetSelectedRowsPfS_S_iii
.p2align 3, 0x0
_Z16kSetSelectedRowsPfS_S_iii:
.quad _Z31__device_stub__kSetSelectedRowsPfS_S_iii
.size _Z16kSetSelectedRowsPfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16kSetSelectedRowsPfS_S_iii"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__kSetSelectedRowsPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16kSetSelectedRowsPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cstdlib>
#include <iostream>
#include <fstream>
#include <chrono>
#define TILE_DIM 64
void gpuMemTransfer(int* A_cpu, int* B_cpu, int* C_cpu, int N, int size, bool memCol);
void gpuNoMemTransfer(int* A_cpu, int* B_cpu, int* C_cpu, int N, int size, bool memCol);
// __global__ void matrixMul(int* A_gpu, int* B_gpu, int* C_gpu, int N) {
// // Row i of matrix C
// int row = blockIdx.y * blockDim.y + threadIdx.y;
// // Column j of matrix C
// int col = blockIdx.x * blockDim.x + threadIdx.x;
// int accu = 0;
// if(row<N && col<N) {
// for(int k=0; k<N; k++) {
// accu = accu + A_gpu[row*N+k] * B_gpu[k*N+col];
// }
// C_gpu[row*N+col] = accu;
// }
// }
__global__ void matrixMul(int* A_cpu, int* B_cpu, int* C_cpu, int N)
{
int accu = 0;
int row = blockIdx.y*TILE_DIM + threadIdx.y;
int col = blockIdx.x*TILE_DIM + threadIdx.x;
__shared__ int shd_A[TILE_DIM][TILE_DIM];
__shared__ int shd_B[TILE_DIM][TILE_DIM];
for (int k = 0; k < (TILE_DIM + N - 1)/TILE_DIM; k++) {
if (k*TILE_DIM + threadIdx.x < N && row < N)
shd_A[threadIdx.y][threadIdx.x] = A_cpu[row*N + k*TILE_DIM + threadIdx.x];
else
shd_A[threadIdx.y][threadIdx.x] = 0.0;
if (k*TILE_DIM + threadIdx.y < N && col < N)
shd_B[threadIdx.y][threadIdx.x] = B_cpu[(k*TILE_DIM + threadIdx.y)*N + col];
else
shd_B[threadIdx.y][threadIdx.x] = 0.0;
__syncthreads();
for (int k = 0; k<TILE_DIM; k++)
accu += shd_A[threadIdx.y][k] * shd_B[k][threadIdx.x];
__syncthreads();
}
if (row < N && col < N)
C_cpu[((blockIdx.y * blockDim.y + threadIdx.y)*N) +
(blockIdx.x * blockDim.x)+ threadIdx.x] = accu;
}
// __global__ void matrixMulCol(int* A_gpu, int* B_gpu, int* C_gpu, int N) {
// // Row i of matrix C
// int row = blockIdx.y * blockDim.y + threadIdx.y;
// // Column j of matrix C
// int col = blockIdx.x * blockDim.x + threadIdx.x;
// int accu = 0;
// if(row<N && col<N) {
// for(int k=0; k<N; k++) {
// accu = accu + A_gpu[k*N+row] * B_gpu[k*N+col];
// }
// C_gpu[row*N+col] = accu;
// }
// }
__global__ void matrixMulCol(int* A_cpu, int* B_cpu, int* C_cpu, int N)
{
int accu = 0;
int row = blockIdx.y*TILE_DIM + threadIdx.y;
int col = blockIdx.x*TILE_DIM + threadIdx.x;
__shared__ int shd_A[TILE_DIM][TILE_DIM];
__shared__ int shd_B[TILE_DIM][TILE_DIM];
for (int k = 0; k < (TILE_DIM + N - 1)/TILE_DIM; k++) {
if (k*TILE_DIM + threadIdx.x < N && row < N)
shd_A[threadIdx.y][threadIdx.x] = A_cpu[(k*TILE_DIM + threadIdx.x)*N + row];
else
shd_A[threadIdx.y][threadIdx.x] = 0.0;
if (k*TILE_DIM + threadIdx.y < N && col < N)
shd_B[threadIdx.y][threadIdx.x] = B_cpu[(k*TILE_DIM + threadIdx.y)*N + col];
else
shd_B[threadIdx.y][threadIdx.x] = 0.0;
__syncthreads();
for (int k=0; k<TILE_DIM; k++)
accu += shd_A[threadIdx.y][k] * shd_B[k][threadIdx.x];
__syncthreads();
}
if (row < N && col < N)
C_cpu[((blockIdx.y * blockDim.y + threadIdx.y)*N) +
(blockIdx.x * blockDim.x)+ threadIdx.x] = accu;
}
void random_ints(int* x, int size)
{
srand(time(0));
int i;
for (i=0;i<size;i++) {
x[i]=rand()%10;
//std::cout << x[i] << " ";
}
}
void matrixMulCPU(int* A_cpu, int* B_cpu, int* C_cpu, int N) {
for(int row=0; row<N; row++) {
for(int col=0; col<N; col++){
C_cpu[row*N+col] = 0;
for(int elm=0; elm<N; elm++) {
C_cpu[row*N+col] = C_cpu[row*N+col] + A_cpu[row*N+elm] * B_cpu[elm*N+col];
}
}
}
}
int main(int argc, char* argv[]){
//int N = 3;
int N = atoi(argv[1]);
bool memCol = false;
if (strcmp(argv[4],"MC")==0) {
memCol=true;
}
int NN = N*N;
//define A_cpu, B_cpu, C_cpu in the CPU memory
int *A_cpu, *B_cpu, *C_cpu;
int size = NN * sizeof(int);
// Setup input values
//std::cout << "A: ";
A_cpu = (int*)malloc(size); random_ints(A_cpu, NN);
//std::cout << "\nB: ";
B_cpu = (int*)malloc(size); random_ints(B_cpu, NN);
C_cpu = (int*)malloc(size);
if (strcmp(argv[2],"gpu")==0) {
if(strcmp(argv[3],"MT")==0) {
gpuMemTransfer(A_cpu, B_cpu, C_cpu, N, size, memCol);
}
else {
gpuNoMemTransfer(A_cpu, B_cpu, C_cpu, N, size, memCol);
}
}
else {
auto t1 = std::chrono::high_resolution_clock::now();
matrixMulCPU(A_cpu, B_cpu, C_cpu, N);
auto t2 = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::microseconds>( t2 - t1 ).count();
std::cout << "N: " << N << "\tCPU time: " << duration << "us" << std::endl;
}
//std::cout << "\nC: " << C_cpu[0] << " " << C_cpu[1] << " " <<C_cpu[2] << " " << C_cpu[3] << " " << C_cpu[4] <<" " << C_cpu[7] <<" " << C_cpu[8] <<"\n";
free(A_cpu); free(B_cpu); free(C_cpu);
return 0;
}
void gpuMemTransfer(int* A_cpu, int* B_cpu, int* C_cpu, int N, int size, bool memCol) {
//define A_gpu, B_gpu, C_gpu in the GPU memory
//std::cout << "\nMem Tr\n";
int *A_gpu, *B_gpu, *C_gpu;
cudaMalloc((void **)&A_gpu, size);
cudaMalloc((void **)&B_gpu, size);
cudaMalloc((void **)&C_gpu, size);
dim3 dimBlock(16, 16);
dim3 dimGrid((N+dimBlock.x-1)/dimBlock.x, (N+dimBlock.y-1)/dimBlock.y);
float time = 0;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
if (memCol==true) {
//std::cout << "MC\n";
cudaEventRecord( start, 0 );
// Copy inputs to device
cudaMemcpy(A_gpu, A_cpu, size, cudaMemcpyHostToDevice);
cudaMemcpy(B_gpu, B_cpu, size, cudaMemcpyHostToDevice);
matrixMulCol<<<dimGrid, dimBlock>>>(A_gpu,B_gpu,C_gpu,N);
//memcopy C_gpu to C_cpu
cudaMemcpy(C_cpu, C_gpu, size, cudaMemcpyDeviceToHost);
//stop time
cudaEventRecord( stop, 0 );
}
else {
//std::cout << "nmc\n";
cudaEventRecord( start, 0 );
// Copy inputs to device
cudaMemcpy(A_gpu, A_cpu, size, cudaMemcpyHostToDevice);
cudaMemcpy(B_gpu, B_cpu, size, cudaMemcpyHostToDevice);
matrixMul<<<dimGrid, dimBlock>>>(A_gpu,B_gpu,C_gpu,N);
//memcopy C_gpu to C_cpu
cudaMemcpy(C_cpu, C_gpu, size, cudaMemcpyDeviceToHost);
//stop time
cudaEventRecord( stop, 0 );
}
cudaEventSynchronize( stop );
cudaEventElapsedTime( &time, start, stop );
cudaEventDestroy( start );
cudaEventDestroy( stop );
cudaFree(A_gpu); cudaFree(B_gpu); cudaFree(C_gpu);
float microsec = (time)*1000;
std::cout << "N: " << N << "\tMT\t" << memCol << "\tGPU time: " << microsec << "us" << std::endl;
}
void gpuNoMemTransfer(int* A_cpu, int* B_cpu, int* C_cpu, int N, int size, bool memCol) {
//define A_gpu, B_gpu, C_gpu in the GPU memory
//std::cout << "\nNoMem Tr\n";
int *A_gpu, *B_gpu, *C_gpu;
cudaMalloc((void **)&A_gpu, size);
cudaMalloc((void **)&B_gpu, size);
cudaMalloc((void **)&C_gpu, size);
// Copy inputs to device
cudaMemcpy(A_gpu, A_cpu, size, cudaMemcpyHostToDevice);
cudaMemcpy(B_gpu, B_cpu, size, cudaMemcpyHostToDevice);
dim3 dimBlock(16, 16);
dim3 dimGrid((N+dimBlock.x-1)/dimBlock.x, (N+dimBlock.y-1)/dimBlock.y);
float time = 0;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
if (memCol==true) {
//std::cout << "MC\n";
cudaEventRecord( start, 0 );
matrixMulCol<<<dimGrid, dimBlock>>>(A_gpu,B_gpu,C_gpu,N);
cudaEventRecord( stop, 0 );
}
else {
//std::cout << "nmc\n";
cudaEventRecord( start, 0 );
matrixMul<<<dimGrid, dimBlock>>>(A_gpu,B_gpu,C_gpu,N);
cudaEventRecord( stop, 0 );
}
cudaEventSynchronize( stop );
cudaEventElapsedTime( &time, start, stop );
cudaEventDestroy( start );
cudaEventDestroy( stop );
//memcopy C_gpu to C_cpu
cudaMemcpy(C_cpu, C_gpu, size, cudaMemcpyDeviceToHost);
cudaFree(A_gpu); cudaFree(B_gpu); cudaFree(C_gpu);
float microsec = (time)*1000;
std::cout << "N: " << N << "\tnt\t" << memCol << "\tGPU time: " << microsec << "us" << std::endl;
} | .file "tmpxft_000368aa_00000000-6_tile.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3908:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3908:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB3899:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movl %esi, %ebp
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %ebp, %ebp
jle .L3
movq %r12, %rbx
movslq %ebp, %rbp
leaq (%r12,%rbp,4), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
.L3:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3899:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z12matrixMulCPUPiS_S_i
.type _Z12matrixMulCPUPiS_S_i, @function
_Z12matrixMulCPUPiS_S_i:
.LFB3900:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L16
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, %r8
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %ebp
movslq %ecx, %rdi
salq $2, %rdi
movq %r8, %rbx
addq %rdi, %r8
movl $0, %r14d
movl $0, %r15d
jmp .L10
.L13:
movl %eax, %r11d
.L12:
movq %r9, %rsi
movl $0, (%r9)
movq %r10, %rcx
movq %rbx, %rax
.L11:
movl (%rax), %edx
imull (%rcx), %edx
addl %edx, (%rsi)
addq $4, %rax
addq %rdi, %rcx
cmpq %r8, %rax
jne .L11
leal 1(%r11), %eax
addq $4, %r9
addq $4, %r10
cmpl %eax, %ebp
jne .L13
leal 1(%r14), %eax
addq %rdi, %rbx
addq %rdi, %r8
addq %rdi, %r12
cmpl %r11d, %r14d
je .L8
movl %eax, %r14d
.L10:
movq %r13, %r10
movq %r12, %r9
movl %r15d, %r11d
jmp .L12
.L8:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE3900:
.size _Z12matrixMulCPUPiS_S_i, .-_Z12matrixMulCPUPiS_S_i
.globl _Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i
.type _Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i:
.LFB3930:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9matrixMulPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3930:
.size _Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i
.globl _Z9matrixMulPiS_S_i
.type _Z9matrixMulPiS_S_i, @function
_Z9matrixMulPiS_S_i:
.LFB3931:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3931:
.size _Z9matrixMulPiS_S_i, .-_Z9matrixMulPiS_S_i
.globl _Z37__device_stub__Z12matrixMulColPiS_S_iPiS_S_i
.type _Z37__device_stub__Z12matrixMulColPiS_S_iPiS_S_i, @function
_Z37__device_stub__Z12matrixMulColPiS_S_iPiS_S_i:
.LFB3932:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12matrixMulColPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3932:
.size _Z37__device_stub__Z12matrixMulColPiS_S_iPiS_S_i, .-_Z37__device_stub__Z12matrixMulColPiS_S_iPiS_S_i
.globl _Z12matrixMulColPiS_S_i
.type _Z12matrixMulColPiS_S_i, @function
_Z12matrixMulColPiS_S_i:
.LFB3933:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12matrixMulColPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3933:
.size _Z12matrixMulColPiS_S_i, .-_Z12matrixMulColPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "N: "
.LC3:
.string "\tnt\t"
.LC4:
.string "\tGPU time: "
.LC5:
.string "us"
.text
.globl _Z16gpuNoMemTransferPiS_S_iib
.type _Z16gpuNoMemTransferPiS_S_iib, @function
_Z16gpuNoMemTransferPiS_S_iib:
.LFB3905:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rdi, %r15
movq %rsi, %r14
movq %rdx, %r13
movl %ecx, %r12d
movl %r9d, %ebp
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movslq %r8d, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 72(%rsp)
leal 15(%r12), %eax
shrl $4, %eax
movl %eax, 76(%rsp)
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
movl $0x00000000, 20(%rsp)
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
testb %bpl, %bpl
je .L36
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $16, 64(%rsp)
movl $16, 68(%rsp)
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L46
.L37:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
.L38:
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movss .LC1(%rip), %xmm0
mulss 20(%rsp), %xmm0
movss %xmm0, 12(%rsp)
movl $3, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $4, %edx
leaq .LC3(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movzbl %bpl, %esi
movq %rbx, %rdi
call _ZNSo9_M_insertIbEERSoT_@PLT
movq %rax, %rbx
movl $11, %edx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $2, %edx
leaq .LC5(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L47
cmpb $0, 56(%rbp)
je .L42
movzbl 67(%rbp), %esi
.L43:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
movl %r12d, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z37__device_stub__Z12matrixMulColPiS_S_iPiS_S_i
jmp .L37
.L36:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $16, 64(%rsp)
movl $16, 68(%rsp)
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L39:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
jmp .L38
.L49:
movl %r12d, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i
jmp .L39
.L47:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L50
call _ZSt16__throw_bad_castv@PLT
.L50:
call __stack_chk_fail@PLT
.L42:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3905:
.size _Z16gpuNoMemTransferPiS_S_iib, .-_Z16gpuNoMemTransferPiS_S_iib
.section .rodata.str1.1
.LC6:
.string "\tMT\t"
.text
.globl _Z14gpuMemTransferPiS_S_iib
.type _Z14gpuMemTransferPiS_S_iib, @function
_Z14gpuMemTransferPiS_S_iib:
.LFB3904:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rdi, %r15
movq %rsi, %r14
movq %rdx, %r13
movl %ecx, %r12d
movl %r9d, %ebp
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movslq %r8d, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, 72(%rsp)
leal 15(%r12), %eax
shrl $4, %eax
movl %eax, 76(%rsp)
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
movl $0x00000000, 20(%rsp)
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
testb %bpl, %bpl
je .L52
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 64(%rsp)
movl $16, 68(%rsp)
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L53:
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
.L54:
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movss .LC1(%rip), %xmm0
mulss 20(%rsp), %xmm0
movss %xmm0, 12(%rsp)
movl $3, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $4, %edx
leaq .LC6(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movzbl %bpl, %esi
movq %rbx, %rdi
call _ZNSo9_M_insertIbEERSoT_@PLT
movq %rax, %rbx
movl $11, %edx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $2, %edx
leaq .LC5(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L63
cmpb $0, 56(%rbp)
je .L58
movzbl 67(%rbp), %esi
.L59:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L64
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L62:
.cfi_restore_state
movl %r12d, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z37__device_stub__Z12matrixMulColPiS_S_iPiS_S_i
jmp .L53
.L52:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 64(%rsp)
movl $16, 68(%rsp)
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
.L55:
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
jmp .L54
.L65:
movl %r12d, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i
jmp .L55
.L63:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L66
call _ZSt16__throw_bad_castv@PLT
.L66:
call __stack_chk_fail@PLT
.L58:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L59
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3904:
.size _Z14gpuMemTransferPiS_S_iib, .-_Z14gpuMemTransferPiS_S_iib
.section .rodata.str1.1
.LC7:
.string "MC"
.LC8:
.string "gpu"
.LC9:
.string "MT"
.LC10:
.string "\tCPU time: "
.text
.globl main
.type main, @function
main:
.LFB3901:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbp
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, 8(%rsp)
movq 32(%rbp), %rdi
leaq .LC7(%rip), %rsi
call strcmp@PLT
movl %eax, 12(%rsp)
imull %ebx, %ebx
leal 0(,%rbx,4), %r14d
movslq %r14d, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r13
movl %ebx, %esi
movq %rax, %rdi
call _Z11random_intsPii
movq %r15, %rdi
call malloc@PLT
movq %rax, %r12
movl %ebx, %esi
movq %rax, %rdi
call _Z11random_intsPii
movq %r15, %rdi
call malloc@PLT
movq %rax, %rbx
movq 16(%rbp), %rdi
leaq .LC8(%rip), %rsi
call strcmp@PLT
testl %eax, %eax
jne .L68
cmpl $0, 12(%rsp)
sete %r15b
movq 24(%rbp), %rdi
leaq .LC9(%rip), %rsi
call strcmp@PLT
testl %eax, %eax
jne .L69
movl %r15d, %r9d
andl $1, %r9d
movl %r14d, %r8d
movl 8(%rsp), %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z14gpuMemTransferPiS_S_iib
.L70:
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L69:
.cfi_restore_state
movl %r15d, %r9d
andl $1, %r9d
movl %r14d, %r8d
movl 8(%rsp), %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z16gpuNoMemTransferPiS_S_iib
jmp .L70
.L68:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
movl 8(%rsp), %r14d
movl %r14d, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z12matrixMulCPUPiS_S_i
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbp, %rax
movl $1000, %ecx
cqto
idivq %rcx
movq %rax, %rbp
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r14d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC10(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L70
.cfi_endproc
.LFE3901:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z12matrixMulColPiS_S_i"
.LC12:
.string "_Z9matrixMulPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3935:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z12matrixMulColPiS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixMulPiS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3935:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cstdlib>
#include <iostream>
#include <fstream>
#include <chrono>
#define TILE_DIM 64
void gpuMemTransfer(int* A_cpu, int* B_cpu, int* C_cpu, int N, int size, bool memCol);
void gpuNoMemTransfer(int* A_cpu, int* B_cpu, int* C_cpu, int N, int size, bool memCol);
// __global__ void matrixMul(int* A_gpu, int* B_gpu, int* C_gpu, int N) {
// // Row i of matrix C
// int row = blockIdx.y * blockDim.y + threadIdx.y;
// // Column j of matrix C
// int col = blockIdx.x * blockDim.x + threadIdx.x;
// int accu = 0;
// if(row<N && col<N) {
// for(int k=0; k<N; k++) {
// accu = accu + A_gpu[row*N+k] * B_gpu[k*N+col];
// }
// C_gpu[row*N+col] = accu;
// }
// }
__global__ void matrixMul(int* A_cpu, int* B_cpu, int* C_cpu, int N)
{
int accu = 0;
int row = blockIdx.y*TILE_DIM + threadIdx.y;
int col = blockIdx.x*TILE_DIM + threadIdx.x;
__shared__ int shd_A[TILE_DIM][TILE_DIM];
__shared__ int shd_B[TILE_DIM][TILE_DIM];
for (int k = 0; k < (TILE_DIM + N - 1)/TILE_DIM; k++) {
if (k*TILE_DIM + threadIdx.x < N && row < N)
shd_A[threadIdx.y][threadIdx.x] = A_cpu[row*N + k*TILE_DIM + threadIdx.x];
else
shd_A[threadIdx.y][threadIdx.x] = 0.0;
if (k*TILE_DIM + threadIdx.y < N && col < N)
shd_B[threadIdx.y][threadIdx.x] = B_cpu[(k*TILE_DIM + threadIdx.y)*N + col];
else
shd_B[threadIdx.y][threadIdx.x] = 0.0;
__syncthreads();
for (int k = 0; k<TILE_DIM; k++)
accu += shd_A[threadIdx.y][k] * shd_B[k][threadIdx.x];
__syncthreads();
}
if (row < N && col < N)
C_cpu[((blockIdx.y * blockDim.y + threadIdx.y)*N) +
(blockIdx.x * blockDim.x)+ threadIdx.x] = accu;
}
// __global__ void matrixMulCol(int* A_gpu, int* B_gpu, int* C_gpu, int N) {
// // Row i of matrix C
// int row = blockIdx.y * blockDim.y + threadIdx.y;
// // Column j of matrix C
// int col = blockIdx.x * blockDim.x + threadIdx.x;
// int accu = 0;
// if(row<N && col<N) {
// for(int k=0; k<N; k++) {
// accu = accu + A_gpu[k*N+row] * B_gpu[k*N+col];
// }
// C_gpu[row*N+col] = accu;
// }
// }
__global__ void matrixMulCol(int* A_cpu, int* B_cpu, int* C_cpu, int N)
{
int accu = 0;
int row = blockIdx.y*TILE_DIM + threadIdx.y;
int col = blockIdx.x*TILE_DIM + threadIdx.x;
__shared__ int shd_A[TILE_DIM][TILE_DIM];
__shared__ int shd_B[TILE_DIM][TILE_DIM];
for (int k = 0; k < (TILE_DIM + N - 1)/TILE_DIM; k++) {
if (k*TILE_DIM + threadIdx.x < N && row < N)
shd_A[threadIdx.y][threadIdx.x] = A_cpu[(k*TILE_DIM + threadIdx.x)*N + row];
else
shd_A[threadIdx.y][threadIdx.x] = 0.0;
if (k*TILE_DIM + threadIdx.y < N && col < N)
shd_B[threadIdx.y][threadIdx.x] = B_cpu[(k*TILE_DIM + threadIdx.y)*N + col];
else
shd_B[threadIdx.y][threadIdx.x] = 0.0;
__syncthreads();
for (int k=0; k<TILE_DIM; k++)
accu += shd_A[threadIdx.y][k] * shd_B[k][threadIdx.x];
__syncthreads();
}
if (row < N && col < N)
C_cpu[((blockIdx.y * blockDim.y + threadIdx.y)*N) +
(blockIdx.x * blockDim.x)+ threadIdx.x] = accu;
}
void random_ints(int* x, int size)
{
srand(time(0));
int i;
for (i=0;i<size;i++) {
x[i]=rand()%10;
//std::cout << x[i] << " ";
}
}
void matrixMulCPU(int* A_cpu, int* B_cpu, int* C_cpu, int N) {
for(int row=0; row<N; row++) {
for(int col=0; col<N; col++){
C_cpu[row*N+col] = 0;
for(int elm=0; elm<N; elm++) {
C_cpu[row*N+col] = C_cpu[row*N+col] + A_cpu[row*N+elm] * B_cpu[elm*N+col];
}
}
}
}
int main(int argc, char* argv[]){
//int N = 3;
int N = atoi(argv[1]);
bool memCol = false;
if (strcmp(argv[4],"MC")==0) {
memCol=true;
}
int NN = N*N;
//define A_cpu, B_cpu, C_cpu in the CPU memory
int *A_cpu, *B_cpu, *C_cpu;
int size = NN * sizeof(int);
// Setup input values
//std::cout << "A: ";
A_cpu = (int*)malloc(size); random_ints(A_cpu, NN);
//std::cout << "\nB: ";
B_cpu = (int*)malloc(size); random_ints(B_cpu, NN);
C_cpu = (int*)malloc(size);
if (strcmp(argv[2],"gpu")==0) {
if(strcmp(argv[3],"MT")==0) {
gpuMemTransfer(A_cpu, B_cpu, C_cpu, N, size, memCol);
}
else {
gpuNoMemTransfer(A_cpu, B_cpu, C_cpu, N, size, memCol);
}
}
else {
auto t1 = std::chrono::high_resolution_clock::now();
matrixMulCPU(A_cpu, B_cpu, C_cpu, N);
auto t2 = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::microseconds>( t2 - t1 ).count();
std::cout << "N: " << N << "\tCPU time: " << duration << "us" << std::endl;
}
//std::cout << "\nC: " << C_cpu[0] << " " << C_cpu[1] << " " <<C_cpu[2] << " " << C_cpu[3] << " " << C_cpu[4] <<" " << C_cpu[7] <<" " << C_cpu[8] <<"\n";
free(A_cpu); free(B_cpu); free(C_cpu);
return 0;
}
void gpuMemTransfer(int* A_cpu, int* B_cpu, int* C_cpu, int N, int size, bool memCol) {
//define A_gpu, B_gpu, C_gpu in the GPU memory
//std::cout << "\nMem Tr\n";
int *A_gpu, *B_gpu, *C_gpu;
cudaMalloc((void **)&A_gpu, size);
cudaMalloc((void **)&B_gpu, size);
cudaMalloc((void **)&C_gpu, size);
dim3 dimBlock(16, 16);
dim3 dimGrid((N+dimBlock.x-1)/dimBlock.x, (N+dimBlock.y-1)/dimBlock.y);
float time = 0;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
if (memCol==true) {
//std::cout << "MC\n";
cudaEventRecord( start, 0 );
// Copy inputs to device
cudaMemcpy(A_gpu, A_cpu, size, cudaMemcpyHostToDevice);
cudaMemcpy(B_gpu, B_cpu, size, cudaMemcpyHostToDevice);
matrixMulCol<<<dimGrid, dimBlock>>>(A_gpu,B_gpu,C_gpu,N);
//memcopy C_gpu to C_cpu
cudaMemcpy(C_cpu, C_gpu, size, cudaMemcpyDeviceToHost);
//stop time
cudaEventRecord( stop, 0 );
}
else {
//std::cout << "nmc\n";
cudaEventRecord( start, 0 );
// Copy inputs to device
cudaMemcpy(A_gpu, A_cpu, size, cudaMemcpyHostToDevice);
cudaMemcpy(B_gpu, B_cpu, size, cudaMemcpyHostToDevice);
matrixMul<<<dimGrid, dimBlock>>>(A_gpu,B_gpu,C_gpu,N);
//memcopy C_gpu to C_cpu
cudaMemcpy(C_cpu, C_gpu, size, cudaMemcpyDeviceToHost);
//stop time
cudaEventRecord( stop, 0 );
}
cudaEventSynchronize( stop );
cudaEventElapsedTime( &time, start, stop );
cudaEventDestroy( start );
cudaEventDestroy( stop );
cudaFree(A_gpu); cudaFree(B_gpu); cudaFree(C_gpu);
float microsec = (time)*1000;
std::cout << "N: " << N << "\tMT\t" << memCol << "\tGPU time: " << microsec << "us" << std::endl;
}
void gpuNoMemTransfer(int* A_cpu, int* B_cpu, int* C_cpu, int N, int size, bool memCol) {
//define A_gpu, B_gpu, C_gpu in the GPU memory
//std::cout << "\nNoMem Tr\n";
int *A_gpu, *B_gpu, *C_gpu;
cudaMalloc((void **)&A_gpu, size);
cudaMalloc((void **)&B_gpu, size);
cudaMalloc((void **)&C_gpu, size);
// Copy inputs to device
cudaMemcpy(A_gpu, A_cpu, size, cudaMemcpyHostToDevice);
cudaMemcpy(B_gpu, B_cpu, size, cudaMemcpyHostToDevice);
dim3 dimBlock(16, 16);
dim3 dimGrid((N+dimBlock.x-1)/dimBlock.x, (N+dimBlock.y-1)/dimBlock.y);
float time = 0;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
if (memCol==true) {
//std::cout << "MC\n";
cudaEventRecord( start, 0 );
matrixMulCol<<<dimGrid, dimBlock>>>(A_gpu,B_gpu,C_gpu,N);
cudaEventRecord( stop, 0 );
}
else {
//std::cout << "nmc\n";
cudaEventRecord( start, 0 );
matrixMul<<<dimGrid, dimBlock>>>(A_gpu,B_gpu,C_gpu,N);
cudaEventRecord( stop, 0 );
}
cudaEventSynchronize( stop );
cudaEventElapsedTime( &time, start, stop );
cudaEventDestroy( start );
cudaEventDestroy( stop );
//memcopy C_gpu to C_cpu
cudaMemcpy(C_cpu, C_gpu, size, cudaMemcpyDeviceToHost);
cudaFree(A_gpu); cudaFree(B_gpu); cudaFree(C_gpu);
float microsec = (time)*1000;
std::cout << "N: " << N << "\tnt\t" << memCol << "\tGPU time: " << microsec << "us" << std::endl;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <cstdlib>
#include <iostream>
#include <fstream>
#include <chrono>
#define TILE_DIM 64
void gpuMemTransfer(int* A_cpu, int* B_cpu, int* C_cpu, int N, int size, bool memCol);
void gpuNoMemTransfer(int* A_cpu, int* B_cpu, int* C_cpu, int N, int size, bool memCol);
// __global__ void matrixMul(int* A_gpu, int* B_gpu, int* C_gpu, int N) {
// // Row i of matrix C
// int row = blockIdx.y * blockDim.y + threadIdx.y;
// // Column j of matrix C
// int col = blockIdx.x * blockDim.x + threadIdx.x;
// int accu = 0;
// if(row<N && col<N) {
// for(int k=0; k<N; k++) {
// accu = accu + A_gpu[row*N+k] * B_gpu[k*N+col];
// }
// C_gpu[row*N+col] = accu;
// }
// }
__global__ void matrixMul(int* A_cpu, int* B_cpu, int* C_cpu, int N)
{
int accu = 0;
int row = blockIdx.y*TILE_DIM + threadIdx.y;
int col = blockIdx.x*TILE_DIM + threadIdx.x;
__shared__ int shd_A[TILE_DIM][TILE_DIM];
__shared__ int shd_B[TILE_DIM][TILE_DIM];
for (int k = 0; k < (TILE_DIM + N - 1)/TILE_DIM; k++) {
if (k*TILE_DIM + threadIdx.x < N && row < N)
shd_A[threadIdx.y][threadIdx.x] = A_cpu[row*N + k*TILE_DIM + threadIdx.x];
else
shd_A[threadIdx.y][threadIdx.x] = 0.0;
if (k*TILE_DIM + threadIdx.y < N && col < N)
shd_B[threadIdx.y][threadIdx.x] = B_cpu[(k*TILE_DIM + threadIdx.y)*N + col];
else
shd_B[threadIdx.y][threadIdx.x] = 0.0;
__syncthreads();
for (int k = 0; k<TILE_DIM; k++)
accu += shd_A[threadIdx.y][k] * shd_B[k][threadIdx.x];
__syncthreads();
}
if (row < N && col < N)
C_cpu[((blockIdx.y * blockDim.y + threadIdx.y)*N) +
(blockIdx.x * blockDim.x)+ threadIdx.x] = accu;
}
// __global__ void matrixMulCol(int* A_gpu, int* B_gpu, int* C_gpu, int N) {
// // Row i of matrix C
// int row = blockIdx.y * blockDim.y + threadIdx.y;
// // Column j of matrix C
// int col = blockIdx.x * blockDim.x + threadIdx.x;
// int accu = 0;
// if(row<N && col<N) {
// for(int k=0; k<N; k++) {
// accu = accu + A_gpu[k*N+row] * B_gpu[k*N+col];
// }
// C_gpu[row*N+col] = accu;
// }
// }
__global__ void matrixMulCol(int* A_cpu, int* B_cpu, int* C_cpu, int N)
{
int accu = 0;
int row = blockIdx.y*TILE_DIM + threadIdx.y;
int col = blockIdx.x*TILE_DIM + threadIdx.x;
__shared__ int shd_A[TILE_DIM][TILE_DIM];
__shared__ int shd_B[TILE_DIM][TILE_DIM];
for (int k = 0; k < (TILE_DIM + N - 1)/TILE_DIM; k++) {
if (k*TILE_DIM + threadIdx.x < N && row < N)
shd_A[threadIdx.y][threadIdx.x] = A_cpu[(k*TILE_DIM + threadIdx.x)*N + row];
else
shd_A[threadIdx.y][threadIdx.x] = 0.0;
if (k*TILE_DIM + threadIdx.y < N && col < N)
shd_B[threadIdx.y][threadIdx.x] = B_cpu[(k*TILE_DIM + threadIdx.y)*N + col];
else
shd_B[threadIdx.y][threadIdx.x] = 0.0;
__syncthreads();
for (int k=0; k<TILE_DIM; k++)
accu += shd_A[threadIdx.y][k] * shd_B[k][threadIdx.x];
__syncthreads();
}
if (row < N && col < N)
C_cpu[((blockIdx.y * blockDim.y + threadIdx.y)*N) +
(blockIdx.x * blockDim.x)+ threadIdx.x] = accu;
}
void random_ints(int* x, int size)
{
srand(time(0));
int i;
for (i=0;i<size;i++) {
x[i]=rand()%10;
//std::cout << x[i] << " ";
}
}
void matrixMulCPU(int* A_cpu, int* B_cpu, int* C_cpu, int N) {
for(int row=0; row<N; row++) {
for(int col=0; col<N; col++){
C_cpu[row*N+col] = 0;
for(int elm=0; elm<N; elm++) {
C_cpu[row*N+col] = C_cpu[row*N+col] + A_cpu[row*N+elm] * B_cpu[elm*N+col];
}
}
}
}
int main(int argc, char* argv[]){
//int N = 3;
int N = atoi(argv[1]);
bool memCol = false;
if (strcmp(argv[4],"MC")==0) {
memCol=true;
}
int NN = N*N;
//define A_cpu, B_cpu, C_cpu in the CPU memory
int *A_cpu, *B_cpu, *C_cpu;
int size = NN * sizeof(int);
// Setup input values
//std::cout << "A: ";
A_cpu = (int*)malloc(size); random_ints(A_cpu, NN);
//std::cout << "\nB: ";
B_cpu = (int*)malloc(size); random_ints(B_cpu, NN);
C_cpu = (int*)malloc(size);
if (strcmp(argv[2],"gpu")==0) {
if(strcmp(argv[3],"MT")==0) {
gpuMemTransfer(A_cpu, B_cpu, C_cpu, N, size, memCol);
}
else {
gpuNoMemTransfer(A_cpu, B_cpu, C_cpu, N, size, memCol);
}
}
else {
auto t1 = std::chrono::high_resolution_clock::now();
matrixMulCPU(A_cpu, B_cpu, C_cpu, N);
auto t2 = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::microseconds>( t2 - t1 ).count();
std::cout << "N: " << N << "\tCPU time: " << duration << "us" << std::endl;
}
//std::cout << "\nC: " << C_cpu[0] << " " << C_cpu[1] << " " <<C_cpu[2] << " " << C_cpu[3] << " " << C_cpu[4] <<" " << C_cpu[7] <<" " << C_cpu[8] <<"\n";
free(A_cpu); free(B_cpu); free(C_cpu);
return 0;
}
void gpuMemTransfer(int* A_cpu, int* B_cpu, int* C_cpu, int N, int size, bool memCol) {
//define A_gpu, B_gpu, C_gpu in the GPU memory
//std::cout << "\nMem Tr\n";
int *A_gpu, *B_gpu, *C_gpu;
hipMalloc((void **)&A_gpu, size);
hipMalloc((void **)&B_gpu, size);
hipMalloc((void **)&C_gpu, size);
dim3 dimBlock(16, 16);
dim3 dimGrid((N+dimBlock.x-1)/dimBlock.x, (N+dimBlock.y-1)/dimBlock.y);
float time = 0;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
if (memCol==true) {
//std::cout << "MC\n";
hipEventRecord( start, 0 );
// Copy inputs to device
hipMemcpy(A_gpu, A_cpu, size, hipMemcpyHostToDevice);
hipMemcpy(B_gpu, B_cpu, size, hipMemcpyHostToDevice);
matrixMulCol<<<dimGrid, dimBlock>>>(A_gpu,B_gpu,C_gpu,N);
//memcopy C_gpu to C_cpu
hipMemcpy(C_cpu, C_gpu, size, hipMemcpyDeviceToHost);
//stop time
hipEventRecord( stop, 0 );
}
else {
//std::cout << "nmc\n";
hipEventRecord( start, 0 );
// Copy inputs to device
hipMemcpy(A_gpu, A_cpu, size, hipMemcpyHostToDevice);
hipMemcpy(B_gpu, B_cpu, size, hipMemcpyHostToDevice);
matrixMul<<<dimGrid, dimBlock>>>(A_gpu,B_gpu,C_gpu,N);
//memcopy C_gpu to C_cpu
hipMemcpy(C_cpu, C_gpu, size, hipMemcpyDeviceToHost);
//stop time
hipEventRecord( stop, 0 );
}
hipEventSynchronize( stop );
hipEventElapsedTime( &time, start, stop );
hipEventDestroy( start );
hipEventDestroy( stop );
hipFree(A_gpu); hipFree(B_gpu); hipFree(C_gpu);
float microsec = (time)*1000;
std::cout << "N: " << N << "\tMT\t" << memCol << "\tGPU time: " << microsec << "us" << std::endl;
}
void gpuNoMemTransfer(int* A_cpu, int* B_cpu, int* C_cpu, int N, int size, bool memCol) {
//define A_gpu, B_gpu, C_gpu in the GPU memory
//std::cout << "\nNoMem Tr\n";
int *A_gpu, *B_gpu, *C_gpu;
hipMalloc((void **)&A_gpu, size);
hipMalloc((void **)&B_gpu, size);
hipMalloc((void **)&C_gpu, size);
// Copy inputs to device
hipMemcpy(A_gpu, A_cpu, size, hipMemcpyHostToDevice);
hipMemcpy(B_gpu, B_cpu, size, hipMemcpyHostToDevice);
dim3 dimBlock(16, 16);
dim3 dimGrid((N+dimBlock.x-1)/dimBlock.x, (N+dimBlock.y-1)/dimBlock.y);
float time = 0;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
if (memCol==true) {
//std::cout << "MC\n";
hipEventRecord( start, 0 );
matrixMulCol<<<dimGrid, dimBlock>>>(A_gpu,B_gpu,C_gpu,N);
hipEventRecord( stop, 0 );
}
else {
//std::cout << "nmc\n";
hipEventRecord( start, 0 );
matrixMul<<<dimGrid, dimBlock>>>(A_gpu,B_gpu,C_gpu,N);
hipEventRecord( stop, 0 );
}
hipEventSynchronize( stop );
hipEventElapsedTime( &time, start, stop );
hipEventDestroy( start );
hipEventDestroy( stop );
//memcopy C_gpu to C_cpu
hipMemcpy(C_cpu, C_gpu, size, hipMemcpyDeviceToHost);
hipFree(A_gpu); hipFree(B_gpu); hipFree(C_gpu);
float microsec = (time)*1000;
std::cout << "N: " << N << "\tnt\t" << memCol << "\tGPU time: " << microsec << "us" << std::endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <cstdlib>
#include <iostream>
#include <fstream>
#include <chrono>
#define TILE_DIM 64
void gpuMemTransfer(int* A_cpu, int* B_cpu, int* C_cpu, int N, int size, bool memCol);
void gpuNoMemTransfer(int* A_cpu, int* B_cpu, int* C_cpu, int N, int size, bool memCol);
// __global__ void matrixMul(int* A_gpu, int* B_gpu, int* C_gpu, int N) {
// // Row i of matrix C
// int row = blockIdx.y * blockDim.y + threadIdx.y;
// // Column j of matrix C
// int col = blockIdx.x * blockDim.x + threadIdx.x;
// int accu = 0;
// if(row<N && col<N) {
// for(int k=0; k<N; k++) {
// accu = accu + A_gpu[row*N+k] * B_gpu[k*N+col];
// }
// C_gpu[row*N+col] = accu;
// }
// }
__global__ void matrixMul(int* A_cpu, int* B_cpu, int* C_cpu, int N)
{
int accu = 0;
int row = blockIdx.y*TILE_DIM + threadIdx.y;
int col = blockIdx.x*TILE_DIM + threadIdx.x;
__shared__ int shd_A[TILE_DIM][TILE_DIM];
__shared__ int shd_B[TILE_DIM][TILE_DIM];
for (int k = 0; k < (TILE_DIM + N - 1)/TILE_DIM; k++) {
if (k*TILE_DIM + threadIdx.x < N && row < N)
shd_A[threadIdx.y][threadIdx.x] = A_cpu[row*N + k*TILE_DIM + threadIdx.x];
else
shd_A[threadIdx.y][threadIdx.x] = 0.0;
if (k*TILE_DIM + threadIdx.y < N && col < N)
shd_B[threadIdx.y][threadIdx.x] = B_cpu[(k*TILE_DIM + threadIdx.y)*N + col];
else
shd_B[threadIdx.y][threadIdx.x] = 0.0;
__syncthreads();
for (int k = 0; k<TILE_DIM; k++)
accu += shd_A[threadIdx.y][k] * shd_B[k][threadIdx.x];
__syncthreads();
}
if (row < N && col < N)
C_cpu[((blockIdx.y * blockDim.y + threadIdx.y)*N) +
(blockIdx.x * blockDim.x)+ threadIdx.x] = accu;
}
// __global__ void matrixMulCol(int* A_gpu, int* B_gpu, int* C_gpu, int N) {
// // Row i of matrix C
// int row = blockIdx.y * blockDim.y + threadIdx.y;
// // Column j of matrix C
// int col = blockIdx.x * blockDim.x + threadIdx.x;
// int accu = 0;
// if(row<N && col<N) {
// for(int k=0; k<N; k++) {
// accu = accu + A_gpu[k*N+row] * B_gpu[k*N+col];
// }
// C_gpu[row*N+col] = accu;
// }
// }
__global__ void matrixMulCol(int* A_cpu, int* B_cpu, int* C_cpu, int N)
{
int accu = 0;
int row = blockIdx.y*TILE_DIM + threadIdx.y;
int col = blockIdx.x*TILE_DIM + threadIdx.x;
__shared__ int shd_A[TILE_DIM][TILE_DIM];
__shared__ int shd_B[TILE_DIM][TILE_DIM];
for (int k = 0; k < (TILE_DIM + N - 1)/TILE_DIM; k++) {
if (k*TILE_DIM + threadIdx.x < N && row < N)
shd_A[threadIdx.y][threadIdx.x] = A_cpu[(k*TILE_DIM + threadIdx.x)*N + row];
else
shd_A[threadIdx.y][threadIdx.x] = 0.0;
if (k*TILE_DIM + threadIdx.y < N && col < N)
shd_B[threadIdx.y][threadIdx.x] = B_cpu[(k*TILE_DIM + threadIdx.y)*N + col];
else
shd_B[threadIdx.y][threadIdx.x] = 0.0;
__syncthreads();
for (int k=0; k<TILE_DIM; k++)
accu += shd_A[threadIdx.y][k] * shd_B[k][threadIdx.x];
__syncthreads();
}
if (row < N && col < N)
C_cpu[((blockIdx.y * blockDim.y + threadIdx.y)*N) +
(blockIdx.x * blockDim.x)+ threadIdx.x] = accu;
}
void random_ints(int* x, int size)
{
srand(time(0));
int i;
for (i=0;i<size;i++) {
x[i]=rand()%10;
//std::cout << x[i] << " ";
}
}
void matrixMulCPU(int* A_cpu, int* B_cpu, int* C_cpu, int N) {
for(int row=0; row<N; row++) {
for(int col=0; col<N; col++){
C_cpu[row*N+col] = 0;
for(int elm=0; elm<N; elm++) {
C_cpu[row*N+col] = C_cpu[row*N+col] + A_cpu[row*N+elm] * B_cpu[elm*N+col];
}
}
}
}
int main(int argc, char* argv[]){
//int N = 3;
int N = atoi(argv[1]);
bool memCol = false;
if (strcmp(argv[4],"MC")==0) {
memCol=true;
}
int NN = N*N;
//define A_cpu, B_cpu, C_cpu in the CPU memory
int *A_cpu, *B_cpu, *C_cpu;
int size = NN * sizeof(int);
// Setup input values
//std::cout << "A: ";
A_cpu = (int*)malloc(size); random_ints(A_cpu, NN);
//std::cout << "\nB: ";
B_cpu = (int*)malloc(size); random_ints(B_cpu, NN);
C_cpu = (int*)malloc(size);
if (strcmp(argv[2],"gpu")==0) {
if(strcmp(argv[3],"MT")==0) {
gpuMemTransfer(A_cpu, B_cpu, C_cpu, N, size, memCol);
}
else {
gpuNoMemTransfer(A_cpu, B_cpu, C_cpu, N, size, memCol);
}
}
else {
auto t1 = std::chrono::high_resolution_clock::now();
matrixMulCPU(A_cpu, B_cpu, C_cpu, N);
auto t2 = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::microseconds>( t2 - t1 ).count();
std::cout << "N: " << N << "\tCPU time: " << duration << "us" << std::endl;
}
//std::cout << "\nC: " << C_cpu[0] << " " << C_cpu[1] << " " <<C_cpu[2] << " " << C_cpu[3] << " " << C_cpu[4] <<" " << C_cpu[7] <<" " << C_cpu[8] <<"\n";
free(A_cpu); free(B_cpu); free(C_cpu);
return 0;
}
void gpuMemTransfer(int* A_cpu, int* B_cpu, int* C_cpu, int N, int size, bool memCol) {
//define A_gpu, B_gpu, C_gpu in the GPU memory
//std::cout << "\nMem Tr\n";
int *A_gpu, *B_gpu, *C_gpu;
hipMalloc((void **)&A_gpu, size);
hipMalloc((void **)&B_gpu, size);
hipMalloc((void **)&C_gpu, size);
dim3 dimBlock(16, 16);
dim3 dimGrid((N+dimBlock.x-1)/dimBlock.x, (N+dimBlock.y-1)/dimBlock.y);
float time = 0;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
if (memCol==true) {
//std::cout << "MC\n";
hipEventRecord( start, 0 );
// Copy inputs to device
hipMemcpy(A_gpu, A_cpu, size, hipMemcpyHostToDevice);
hipMemcpy(B_gpu, B_cpu, size, hipMemcpyHostToDevice);
matrixMulCol<<<dimGrid, dimBlock>>>(A_gpu,B_gpu,C_gpu,N);
//memcopy C_gpu to C_cpu
hipMemcpy(C_cpu, C_gpu, size, hipMemcpyDeviceToHost);
//stop time
hipEventRecord( stop, 0 );
}
else {
//std::cout << "nmc\n";
hipEventRecord( start, 0 );
// Copy inputs to device
hipMemcpy(A_gpu, A_cpu, size, hipMemcpyHostToDevice);
hipMemcpy(B_gpu, B_cpu, size, hipMemcpyHostToDevice);
matrixMul<<<dimGrid, dimBlock>>>(A_gpu,B_gpu,C_gpu,N);
//memcopy C_gpu to C_cpu
hipMemcpy(C_cpu, C_gpu, size, hipMemcpyDeviceToHost);
//stop time
hipEventRecord( stop, 0 );
}
hipEventSynchronize( stop );
hipEventElapsedTime( &time, start, stop );
hipEventDestroy( start );
hipEventDestroy( stop );
hipFree(A_gpu); hipFree(B_gpu); hipFree(C_gpu);
float microsec = (time)*1000;
std::cout << "N: " << N << "\tMT\t" << memCol << "\tGPU time: " << microsec << "us" << std::endl;
}
void gpuNoMemTransfer(int* A_cpu, int* B_cpu, int* C_cpu, int N, int size, bool memCol) {
//define A_gpu, B_gpu, C_gpu in the GPU memory
//std::cout << "\nNoMem Tr\n";
int *A_gpu, *B_gpu, *C_gpu;
hipMalloc((void **)&A_gpu, size);
hipMalloc((void **)&B_gpu, size);
hipMalloc((void **)&C_gpu, size);
// Copy inputs to device
hipMemcpy(A_gpu, A_cpu, size, hipMemcpyHostToDevice);
hipMemcpy(B_gpu, B_cpu, size, hipMemcpyHostToDevice);
dim3 dimBlock(16, 16);
dim3 dimGrid((N+dimBlock.x-1)/dimBlock.x, (N+dimBlock.y-1)/dimBlock.y);
float time = 0;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
if (memCol==true) {
//std::cout << "MC\n";
hipEventRecord( start, 0 );
matrixMulCol<<<dimGrid, dimBlock>>>(A_gpu,B_gpu,C_gpu,N);
hipEventRecord( stop, 0 );
}
else {
//std::cout << "nmc\n";
hipEventRecord( start, 0 );
matrixMul<<<dimGrid, dimBlock>>>(A_gpu,B_gpu,C_gpu,N);
hipEventRecord( stop, 0 );
}
hipEventSynchronize( stop );
hipEventElapsedTime( &time, start, stop );
hipEventDestroy( start );
hipEventDestroy( stop );
//memcopy C_gpu to C_cpu
hipMemcpy(C_cpu, C_gpu, size, hipMemcpyDeviceToHost);
hipFree(A_gpu); hipFree(B_gpu); hipFree(C_gpu);
float microsec = (time)*1000;
std::cout << "N: " << N << "\tnt\t" << memCol << "\tGPU time: " << microsec << "us" << std::endl;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixMulPiS_S_i
.globl _Z9matrixMulPiS_S_i
.p2align 8
.type _Z9matrixMulPiS_S_i,@function
_Z9matrixMulPiS_S_i:
s_load_b32 s3, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v7, s15, 6, v1
v_lshl_add_u32 v2, s14, 6, v0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_13
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v6, 0 :: v_dual_lshlrev_b32 v3, 2, v0
v_lshlrev_b32_e32 v8, 8, v1
s_add_i32 s2, s3, 63
v_mad_u64_u32 v[4:5], null, v7, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_3)
v_or_b32_e32 v9, 0x4000, v3
s_lshr_b32 s8, s2, 6
v_cmp_gt_i32_e32 vcc_lo, s3, v7
v_cmp_gt_i32_e64 s2, s3, v2
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v10, v8, v3
v_add_nc_u32_e32 v11, v9, v8
s_max_i32 s8, s8, 1
s_mov_b32 s9, 0
s_xor_b32 s10, vcc_lo, -1
s_xor_b32 s2, s2, -1
.LBB0_2:
s_lshl_b32 s11, s9, 6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, s11, v0
v_cmp_le_u32_e32 vcc_lo, s3, v5
s_or_b32 s12, s10, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s13, s12
s_xor_b32 s12, exec_lo, s13
s_cbranch_execz .LBB0_4
ds_store_b32 v10, v6
.LBB0_4:
s_and_not1_saveexec_b32 s12, s12
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v5, s11, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v12, vcc_lo, s4, v12
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
global_load_b32 v5, v[12:13], off
s_waitcnt vmcnt(0)
ds_store_b32 v10, v5
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s12
v_add_nc_u32_e32 v5, s11, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s3, v5
s_or_b32 s11, s2, vcc_lo
s_and_saveexec_b32 s12, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s11, exec_lo, s12
s_cbranch_execz .LBB0_8
ds_store_b32 v11, v6
.LBB0_8:
s_and_not1_saveexec_b32 s11, s11
s_cbranch_execz .LBB0_10
v_mad_u64_u32 v[12:13], null, v5, s3, v[2:3]
v_mov_b32_e32 v13, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v12, vcc_lo, s6, v12
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
global_load_b32 v5, v[12:13], off
s_waitcnt vmcnt(0)
ds_store_b32 v11, v5
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s11
v_mov_b32_e32 v5, v9
s_mov_b32 s11, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_11:
v_add_nc_u32_e32 v12, s11, v8
s_add_i32 s11, s11, 4
ds_load_b32 v14, v5
ds_load_b32 v15, v12
v_add_nc_u32_e32 v5, 0x100, v5
s_cmpk_eq_i32 s11, 0x100
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[12:13], null, v14, v15, v[3:4]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v3, v12
s_cbranch_scc0 .LBB0_11
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, s8
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_14
.LBB0_13:
v_mov_b32_e32 v3, 0
.LBB0_14:
v_max_i32_e32 v2, v7, v2
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v2
s_cbranch_execz .LBB0_16
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[4:5], null, s15, s4, v[1:2]
s_mul_i32 s14, s14, s2
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v4, s3
v_add3_u32 v0, s14, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixMulPiS_S_i
.amdhsa_group_segment_fixed_size 32768
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matrixMulPiS_S_i, .Lfunc_end0-_Z9matrixMulPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12matrixMulColPiS_S_i
.globl _Z12matrixMulColPiS_S_i
.p2align 8
.type _Z12matrixMulColPiS_S_i,@function
_Z12matrixMulColPiS_S_i:
s_load_b32 s3, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v0, s15, 6, v1
v_lshl_add_u32 v2, s14, 6, v4
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB1_13
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v4
v_lshlrev_b32_e32 v5, 8, v1
s_add_i32 s2, s3, 63
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_lshr_b32 s8, s2, 6
v_or_b32_e32 v6, 0x4000, v3
v_cmp_gt_i32_e64 s2, s3, v2
v_add_nc_u32_e32 v7, v5, v3
v_mov_b32_e32 v9, 0
s_delay_alu instid0(VALU_DEP_4)
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v8, v6, v5
s_max_i32 s8, s8, 1
s_mov_b32 s9, 0
s_xor_b32 s10, vcc_lo, -1
s_xor_b32 s2, s2, -1
.LBB1_2:
s_lshl_b32 s11, s9, 6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v10, s11, v4
v_cmp_le_u32_e32 vcc_lo, s3, v10
s_or_b32 s12, s10, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s13, s12
s_xor_b32 s12, exec_lo, s13
s_cbranch_execz .LBB1_4
ds_store_b32 v7, v9
.LBB1_4:
s_and_not1_saveexec_b32 s12, s12
s_cbranch_execz .LBB1_6
v_mad_u64_u32 v[11:12], null, v10, s3, v[0:1]
v_mov_b32_e32 v12, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[11:12]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v10, vcc_lo, s4, v10
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
global_load_b32 v10, v[10:11], off
s_waitcnt vmcnt(0)
ds_store_b32 v7, v10
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s12
v_add_nc_u32_e32 v10, s11, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s3, v10
s_or_b32 s11, s2, vcc_lo
s_and_saveexec_b32 s12, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s11, exec_lo, s12
s_cbranch_execz .LBB1_8
ds_store_b32 v8, v9
.LBB1_8:
s_and_not1_saveexec_b32 s11, s11
s_cbranch_execz .LBB1_10
v_mad_u64_u32 v[11:12], null, v10, s3, v[2:3]
v_mov_b32_e32 v12, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[11:12]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v10, vcc_lo, s6, v10
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
global_load_b32 v10, v[10:11], off
s_waitcnt vmcnt(0)
ds_store_b32 v8, v10
.LBB1_10:
s_or_b32 exec_lo, exec_lo, s11
v_mov_b32_e32 v10, v6
s_mov_b32 s11, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB1_11:
v_add_nc_u32_e32 v11, s11, v5
s_add_i32 s11, s11, 4
ds_load_b32 v13, v10
ds_load_b32 v14, v11
s_cmpk_eq_i32 s11, 0x100
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[11:12], null, v13, v14, v[3:4]
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v3, v11 :: v_dual_add_nc_u32 v10, 0x100, v10
s_cbranch_scc0 .LBB1_11
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, s8
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_2
s_branch .LBB1_14
.LBB1_13:
v_mov_b32_e32 v3, 0
.LBB1_14:
v_max_i32_e32 v0, v0, v2
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB1_16
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[5:6], null, s15, s4, v[1:2]
s_mul_i32 s14, s14, s2
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v5, s3
v_add3_u32 v0, s14, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB1_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12matrixMulColPiS_S_i
.amdhsa_group_segment_fixed_size 32768
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12matrixMulColPiS_S_i, .Lfunc_end1-_Z12matrixMulColPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 32768
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixMulPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matrixMulPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 32768
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12matrixMulColPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12matrixMulColPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <cstdlib>
#include <iostream>
#include <fstream>
#include <chrono>
#define TILE_DIM 64
void gpuMemTransfer(int* A_cpu, int* B_cpu, int* C_cpu, int N, int size, bool memCol);
void gpuNoMemTransfer(int* A_cpu, int* B_cpu, int* C_cpu, int N, int size, bool memCol);
// __global__ void matrixMul(int* A_gpu, int* B_gpu, int* C_gpu, int N) {
// // Row i of matrix C
// int row = blockIdx.y * blockDim.y + threadIdx.y;
// // Column j of matrix C
// int col = blockIdx.x * blockDim.x + threadIdx.x;
// int accu = 0;
// if(row<N && col<N) {
// for(int k=0; k<N; k++) {
// accu = accu + A_gpu[row*N+k] * B_gpu[k*N+col];
// }
// C_gpu[row*N+col] = accu;
// }
// }
__global__ void matrixMul(int* A_cpu, int* B_cpu, int* C_cpu, int N)
{
int accu = 0;
int row = blockIdx.y*TILE_DIM + threadIdx.y;
int col = blockIdx.x*TILE_DIM + threadIdx.x;
__shared__ int shd_A[TILE_DIM][TILE_DIM];
__shared__ int shd_B[TILE_DIM][TILE_DIM];
for (int k = 0; k < (TILE_DIM + N - 1)/TILE_DIM; k++) {
if (k*TILE_DIM + threadIdx.x < N && row < N)
shd_A[threadIdx.y][threadIdx.x] = A_cpu[row*N + k*TILE_DIM + threadIdx.x];
else
shd_A[threadIdx.y][threadIdx.x] = 0.0;
if (k*TILE_DIM + threadIdx.y < N && col < N)
shd_B[threadIdx.y][threadIdx.x] = B_cpu[(k*TILE_DIM + threadIdx.y)*N + col];
else
shd_B[threadIdx.y][threadIdx.x] = 0.0;
__syncthreads();
for (int k = 0; k<TILE_DIM; k++)
accu += shd_A[threadIdx.y][k] * shd_B[k][threadIdx.x];
__syncthreads();
}
if (row < N && col < N)
C_cpu[((blockIdx.y * blockDim.y + threadIdx.y)*N) +
(blockIdx.x * blockDim.x)+ threadIdx.x] = accu;
}
// __global__ void matrixMulCol(int* A_gpu, int* B_gpu, int* C_gpu, int N) {
// // Row i of matrix C
// int row = blockIdx.y * blockDim.y + threadIdx.y;
// // Column j of matrix C
// int col = blockIdx.x * blockDim.x + threadIdx.x;
// int accu = 0;
// if(row<N && col<N) {
// for(int k=0; k<N; k++) {
// accu = accu + A_gpu[k*N+row] * B_gpu[k*N+col];
// }
// C_gpu[row*N+col] = accu;
// }
// }
__global__ void matrixMulCol(int* A_cpu, int* B_cpu, int* C_cpu, int N)
{
int accu = 0;
int row = blockIdx.y*TILE_DIM + threadIdx.y;
int col = blockIdx.x*TILE_DIM + threadIdx.x;
__shared__ int shd_A[TILE_DIM][TILE_DIM];
__shared__ int shd_B[TILE_DIM][TILE_DIM];
for (int k = 0; k < (TILE_DIM + N - 1)/TILE_DIM; k++) {
if (k*TILE_DIM + threadIdx.x < N && row < N)
shd_A[threadIdx.y][threadIdx.x] = A_cpu[(k*TILE_DIM + threadIdx.x)*N + row];
else
shd_A[threadIdx.y][threadIdx.x] = 0.0;
if (k*TILE_DIM + threadIdx.y < N && col < N)
shd_B[threadIdx.y][threadIdx.x] = B_cpu[(k*TILE_DIM + threadIdx.y)*N + col];
else
shd_B[threadIdx.y][threadIdx.x] = 0.0;
__syncthreads();
for (int k=0; k<TILE_DIM; k++)
accu += shd_A[threadIdx.y][k] * shd_B[k][threadIdx.x];
__syncthreads();
}
if (row < N && col < N)
C_cpu[((blockIdx.y * blockDim.y + threadIdx.y)*N) +
(blockIdx.x * blockDim.x)+ threadIdx.x] = accu;
}
void random_ints(int* x, int size)
{
srand(time(0));
int i;
for (i=0;i<size;i++) {
x[i]=rand()%10;
//std::cout << x[i] << " ";
}
}
void matrixMulCPU(int* A_cpu, int* B_cpu, int* C_cpu, int N) {
for(int row=0; row<N; row++) {
for(int col=0; col<N; col++){
C_cpu[row*N+col] = 0;
for(int elm=0; elm<N; elm++) {
C_cpu[row*N+col] = C_cpu[row*N+col] + A_cpu[row*N+elm] * B_cpu[elm*N+col];
}
}
}
}
int main(int argc, char* argv[]){
//int N = 3;
int N = atoi(argv[1]);
bool memCol = false;
if (strcmp(argv[4],"MC")==0) {
memCol=true;
}
int NN = N*N;
//define A_cpu, B_cpu, C_cpu in the CPU memory
int *A_cpu, *B_cpu, *C_cpu;
int size = NN * sizeof(int);
// Setup input values
//std::cout << "A: ";
A_cpu = (int*)malloc(size); random_ints(A_cpu, NN);
//std::cout << "\nB: ";
B_cpu = (int*)malloc(size); random_ints(B_cpu, NN);
C_cpu = (int*)malloc(size);
if (strcmp(argv[2],"gpu")==0) {
if(strcmp(argv[3],"MT")==0) {
gpuMemTransfer(A_cpu, B_cpu, C_cpu, N, size, memCol);
}
else {
gpuNoMemTransfer(A_cpu, B_cpu, C_cpu, N, size, memCol);
}
}
else {
auto t1 = std::chrono::high_resolution_clock::now();
matrixMulCPU(A_cpu, B_cpu, C_cpu, N);
auto t2 = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::microseconds>( t2 - t1 ).count();
std::cout << "N: " << N << "\tCPU time: " << duration << "us" << std::endl;
}
//std::cout << "\nC: " << C_cpu[0] << " " << C_cpu[1] << " " <<C_cpu[2] << " " << C_cpu[3] << " " << C_cpu[4] <<" " << C_cpu[7] <<" " << C_cpu[8] <<"\n";
free(A_cpu); free(B_cpu); free(C_cpu);
return 0;
}
void gpuMemTransfer(int* A_cpu, int* B_cpu, int* C_cpu, int N, int size, bool memCol) {
//define A_gpu, B_gpu, C_gpu in the GPU memory
//std::cout << "\nMem Tr\n";
int *A_gpu, *B_gpu, *C_gpu;
hipMalloc((void **)&A_gpu, size);
hipMalloc((void **)&B_gpu, size);
hipMalloc((void **)&C_gpu, size);
dim3 dimBlock(16, 16);
dim3 dimGrid((N+dimBlock.x-1)/dimBlock.x, (N+dimBlock.y-1)/dimBlock.y);
float time = 0;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
if (memCol==true) {
//std::cout << "MC\n";
hipEventRecord( start, 0 );
// Copy inputs to device
hipMemcpy(A_gpu, A_cpu, size, hipMemcpyHostToDevice);
hipMemcpy(B_gpu, B_cpu, size, hipMemcpyHostToDevice);
matrixMulCol<<<dimGrid, dimBlock>>>(A_gpu,B_gpu,C_gpu,N);
//memcopy C_gpu to C_cpu
hipMemcpy(C_cpu, C_gpu, size, hipMemcpyDeviceToHost);
//stop time
hipEventRecord( stop, 0 );
}
else {
//std::cout << "nmc\n";
hipEventRecord( start, 0 );
// Copy inputs to device
hipMemcpy(A_gpu, A_cpu, size, hipMemcpyHostToDevice);
hipMemcpy(B_gpu, B_cpu, size, hipMemcpyHostToDevice);
matrixMul<<<dimGrid, dimBlock>>>(A_gpu,B_gpu,C_gpu,N);
//memcopy C_gpu to C_cpu
hipMemcpy(C_cpu, C_gpu, size, hipMemcpyDeviceToHost);
//stop time
hipEventRecord( stop, 0 );
}
hipEventSynchronize( stop );
hipEventElapsedTime( &time, start, stop );
hipEventDestroy( start );
hipEventDestroy( stop );
hipFree(A_gpu); hipFree(B_gpu); hipFree(C_gpu);
float microsec = (time)*1000;
std::cout << "N: " << N << "\tMT\t" << memCol << "\tGPU time: " << microsec << "us" << std::endl;
}
void gpuNoMemTransfer(int* A_cpu, int* B_cpu, int* C_cpu, int N, int size, bool memCol) {
//define A_gpu, B_gpu, C_gpu in the GPU memory
//std::cout << "\nNoMem Tr\n";
int *A_gpu, *B_gpu, *C_gpu;
hipMalloc((void **)&A_gpu, size);
hipMalloc((void **)&B_gpu, size);
hipMalloc((void **)&C_gpu, size);
// Copy inputs to device
hipMemcpy(A_gpu, A_cpu, size, hipMemcpyHostToDevice);
hipMemcpy(B_gpu, B_cpu, size, hipMemcpyHostToDevice);
dim3 dimBlock(16, 16);
dim3 dimGrid((N+dimBlock.x-1)/dimBlock.x, (N+dimBlock.y-1)/dimBlock.y);
float time = 0;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
if (memCol==true) {
//std::cout << "MC\n";
hipEventRecord( start, 0 );
matrixMulCol<<<dimGrid, dimBlock>>>(A_gpu,B_gpu,C_gpu,N);
hipEventRecord( stop, 0 );
}
else {
//std::cout << "nmc\n";
hipEventRecord( start, 0 );
matrixMul<<<dimGrid, dimBlock>>>(A_gpu,B_gpu,C_gpu,N);
hipEventRecord( stop, 0 );
}
hipEventSynchronize( stop );
hipEventElapsedTime( &time, start, stop );
hipEventDestroy( start );
hipEventDestroy( stop );
//memcopy C_gpu to C_cpu
hipMemcpy(C_cpu, C_gpu, size, hipMemcpyDeviceToHost);
hipFree(A_gpu); hipFree(B_gpu); hipFree(C_gpu);
float microsec = (time)*1000;
std::cout << "N: " << N << "\tnt\t" << memCol << "\tGPU time: " << microsec << "us" << std::endl;
} | .text
.file "tile.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__matrixMulPiS_S_i # -- Begin function _Z24__device_stub__matrixMulPiS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__matrixMulPiS_S_i,@function
_Z24__device_stub__matrixMulPiS_S_i: # @_Z24__device_stub__matrixMulPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9matrixMulPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__matrixMulPiS_S_i, .Lfunc_end0-_Z24__device_stub__matrixMulPiS_S_i
.cfi_endproc
# -- End function
.globl _Z27__device_stub__matrixMulColPiS_S_i # -- Begin function _Z27__device_stub__matrixMulColPiS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__matrixMulColPiS_S_i,@function
_Z27__device_stub__matrixMulColPiS_S_i: # @_Z27__device_stub__matrixMulColPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12matrixMulColPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z27__device_stub__matrixMulColPiS_S_i, .Lfunc_end1-_Z27__device_stub__matrixMulColPiS_S_i
.cfi_endproc
# -- End function
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testl %ebp, %ebp
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB2_2
.LBB2_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z11random_intsPii, .Lfunc_end2-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl _Z12matrixMulCPUPiS_S_i # -- Begin function _Z12matrixMulCPUPiS_S_i
.p2align 4, 0x90
.type _Z12matrixMulCPUPiS_S_i,@function
_Z12matrixMulCPUPiS_S_i: # @_Z12matrixMulCPUPiS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, -8(%rsp) # 8-byte Spill
testl %ecx, %ecx
jle .LBB3_7
# %bb.1: # %.preheader.lr.ph
movl %ecx, %eax
leaq (,%rax,4), %r8
xorl %edx, %edx
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
# Child Loop BB3_4 Depth 3
movl %edx, %r11d
leaq (%rdi,%r11,4), %r11
movq %r10, %rbx
imulq %rax, %rbx
movq -8(%rsp), %r9 # 8-byte Reload
leaq (%r9,%rbx,4), %rbx
movq %rsi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_3: # %.lr.ph
# Parent Loop BB3_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_4 Depth 3
movl $0, (%rbx,%r15,4)
xorl %r12d, %r12d
movq %r14, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# Parent Loop BB3_3 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r13), %r9d
imull (%r11,%r12,4), %r9d
addl %r9d, %ebp
movl %ebp, (%rbx,%r15,4)
incq %r12
addq %r8, %r13
cmpq %r12, %rax
jne .LBB3_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB3_3 Depth=2
incq %r15
addq $4, %r14
cmpq %rax, %r15
jne .LBB3_3
# %bb.6: # %._crit_edge34
# in Loop: Header=BB3_2 Depth=1
incq %r10
addl %ecx, %edx
cmpq %rax, %r10
jne .LBB3_2
.LBB3_7: # %._crit_edge36
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z12matrixMulCPUPiS_S_i, .Lfunc_end3-_Z12matrixMulCPUPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq %rbx, 16(%rsp) # 8-byte Spill
movq 32(%rbx), %rdi
movl $.L.str, %esi
callq strcmp
movl %eax, 8(%rsp) # 4-byte Spill
movl %r15d, %r14d
imull %r14d, %r14d
leal (,%r14,4), %eax
movl %eax, 12(%rsp) # 4-byte Spill
movslq %eax, %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl %r14d, %ebp
movq %r15, (%rsp) # 8-byte Spill
testl %r15d, %r15d
je .LBB4_3
# %bb.1: # %.lr.ph.preheader.i
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq %r14, %rbp
jne .LBB4_2
.LBB4_3: # %_Z11random_intsPii.exit
movq %r12, %rdi
callq malloc
movq %rax, %r14
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
cmpl $0, (%rsp) # 4-byte Folded Reload
je .LBB4_6
# %bb.4: # %.lr.ph.preheader.i34
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_5: # %.lr.ph.i36
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r14,%r13,4)
incq %r13
cmpq %r13, %rbp
jne .LBB4_5
.LBB4_6: # %_Z11random_intsPii.exit40
movq %r12, %rdi
callq malloc
movq %rax, %r12
movq 16(%rsp), %r15 # 8-byte Reload
movq 16(%r15), %rdi
movl $.L.str.1, %esi
callq strcmp
testl %eax, %eax
je .LBB4_7
# %bb.10:
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, 16(%rsp) # 8-byte Spill
cmpl $0, (%rsp) # 4-byte Folded Reload
jle .LBB4_17
# %bb.11: # %.preheader.lr.ph.i
movl (%rsp), %eax # 4-byte Reload
leaq (,%rax,4), %rcx
xorl %edx, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB4_12: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_13 Depth 2
# Child Loop BB4_14 Depth 3
movl %edx, %edi
leaq (%rbx,%rdi,4), %rdi
movq %rsi, %r8
imulq %rax, %r8
movq %r12, %r15
leaq (%r12,%r8,4), %r8
movq %r14, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB4_13: # %.lr.ph.i41
# Parent Loop BB4_12 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_14 Depth 3
movl $0, (%r8,%r10,4)
xorl %r11d, %r11d
movq %r9, %rbp
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_14: # Parent Loop BB4_12 Depth=1
# Parent Loop BB4_13 Depth=2
# => This Inner Loop Header: Depth=3
movl (%rbp), %r12d
imull (%rdi,%r11), %r12d
addl %r12d, %r13d
addq $4, %r11
addq %rcx, %rbp
cmpq %r11, %rcx
jne .LBB4_14
# %bb.15: # %._crit_edge.i
# in Loop: Header=BB4_13 Depth=2
movl %r13d, (%r8,%r10,4)
incq %r10
addq $4, %r9
cmpq %rax, %r10
jne .LBB4_13
# %bb.16: # %._crit_edge34.i
# in Loop: Header=BB4_12 Depth=1
incq %rsi
addl (%rsp), %edx # 4-byte Folded Reload
cmpq %rax, %rsi
movq %r15, %r12
jne .LBB4_12
.LBB4_17: # %_Z12matrixMulCPUPiS_S_i.exit
callq _ZNSt6chrono3_V212system_clock3nowEv
subq 16(%rsp), %rax # 8-byte Folded Reload
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %r13
shrq $63, %r13
sarq $7, %rdx
addq %rdx, %r13
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movq (%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.4, %esi
movl $11, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r15, %rdi
movq %r13, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movq %rax, %r15
movl $.L.str.5, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r13
testq %r13, %r13
je .LBB4_23
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r13)
je .LBB4_20
# %bb.19:
movzbl 67(%r13), %eax
jmp .LBB4_21
.LBB4_7:
movq 24(%r15), %rdi
movl $.L.str.2, %esi
callq strcmp
xorl %r9d, %r9d
testl %eax, %eax
je .LBB4_8
# %bb.9:
cmpl $0, 8(%rsp) # 4-byte Folded Reload
sete %r9b
movq %rbx, %rdi
movq %r14, %rsi
movq %r12, %rdx
movq (%rsp), %rcx # 8-byte Reload
# kill: def $ecx killed $ecx killed $rcx
movl 12(%rsp), %r8d # 4-byte Reload
callq _Z16gpuNoMemTransferPiS_S_iib
jmp .LBB4_22
.LBB4_20:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_21: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB4_22:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_8:
.cfi_def_cfa_offset 80
cmpl $0, 8(%rsp) # 4-byte Folded Reload
sete %r9b
movq %rbx, %rdi
movq %r14, %rsi
movq %r12, %rdx
movq (%rsp), %rcx # 8-byte Reload
# kill: def $ecx killed $ecx killed $rcx
movl 12(%rsp), %r8d # 4-byte Reload
callq _Z14gpuMemTransferPiS_S_iib
jmp .LBB4_22
.LBB4_23:
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z14gpuMemTransferPiS_S_iib
.LCPI5_0:
.long 0x447a0000 # float 1000
.text
.globl _Z14gpuMemTransferPiS_S_iib
.p2align 4, 0x90
.type _Z14gpuMemTransferPiS_S_iib,@function
_Z14gpuMemTransferPiS_S_iib: # @_Z14gpuMemTransferPiS_S_iib
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movl %ecx, %r14d
movq %rdx, 32(%rsp) # 8-byte Spill
movq %rsi, %r13
movq %rdi, %rbp
movslq %r8d, %r15
leaq 56(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leal 15(%r14), %eax
shrl $4, %eax
movq %rax, %r12
shlq $32, %r12
orq %rax, %r12
movl $0, 28(%rsp)
leaq 64(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
callq hipEventCreate
movq 64(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 56(%rsp), %rdi
movq %rbp, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq %r13, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %ebx, %ebx
je .LBB5_3
# %bb.1:
testl %eax, %eax
jne .LBB5_6
# %bb.2:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %r14d, 12(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z12matrixMulColPiS_S_i, %edi
jmp .LBB5_5
.LBB5_3:
testl %eax, %eax
jne .LBB5_6
# %bb.4:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %r14d, 12(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z9matrixMulPiS_S_i, %edi
.LBB5_5:
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_6:
movq 16(%rsp), %rsi
movq 32(%rsp), %rdi # 8-byte Reload
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
callq hipEventSynchronize
movq 64(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 28(%rsp), %rdi
callq hipEventElapsedTime
movq 64(%rsp), %rdi
callq hipEventDestroy
movq 40(%rsp), %rdi
callq hipEventDestroy
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movss 28(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss .LCPI5_0(%rip), %xmm0
movss %xmm0, 32(%rsp) # 4-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.6, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movzbl %bl, %esi
movq %r14, %rdi
callq _ZNSo9_M_insertIbEERSoT_
movq %rax, %rbx
movl $.L.str.7, %esi
movl $11, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 32(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.5, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB5_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB5_9
# %bb.8:
movzbl 67(%r14), %eax
jmp .LBB5_10
.LBB5_9:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB5_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_11:
.cfi_def_cfa_offset 240
callq _ZSt16__throw_bad_castv
.Lfunc_end5:
.size _Z14gpuMemTransferPiS_S_iib, .Lfunc_end5-_Z14gpuMemTransferPiS_S_iib
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z16gpuNoMemTransferPiS_S_iib
.LCPI6_0:
.long 0x447a0000 # float 1000
.text
.globl _Z16gpuNoMemTransferPiS_S_iib
.p2align 4, 0x90
.type _Z16gpuNoMemTransferPiS_S_iib,@function
_Z16gpuNoMemTransferPiS_S_iib: # @_Z16gpuNoMemTransferPiS_S_iib
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movl %ecx, %r14d
movq %rdx, %r15
movq %rsi, %r13
movq %rdi, %rbp
movslq %r8d, %r12
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %rbp, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r13, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
leal 15(%r14), %eax
shrl $4, %eax
movq %rax, %r13
shlq $32, %r13
orq %rax, %r13
movl $0, 4(%rsp)
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %ebx, %ebx
je .LBB6_3
# %bb.1:
testl %eax, %eax
jne .LBB6_6
# %bb.2:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movq %rdx, 96(%rsp)
movl %r14d, (%rsp)
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 96(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12matrixMulColPiS_S_i, %edi
jmp .LBB6_5
.LBB6_3:
testl %eax, %eax
jne .LBB6_6
# %bb.4:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movq %rdx, 96(%rsp)
movl %r14d, (%rsp)
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 96(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z9matrixMulPiS_S_i, %edi
.LBB6_5:
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_6:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movq 40(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss .LCPI6_0(%rip), %xmm0
movss %xmm0, 124(%rsp) # 4-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.8, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movzbl %bl, %esi
movq %r14, %rdi
callq _ZNSo9_M_insertIbEERSoT_
movq %rax, %rbx
movl $.L.str.7, %esi
movl $11, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 124(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.5, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB6_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB6_9
# %bb.8:
movzbl 67(%r14), %eax
jmp .LBB6_10
.LBB6_9:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB6_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_11:
.cfi_def_cfa_offset 224
callq _ZSt16__throw_bad_castv
.Lfunc_end6:
.size _Z16gpuNoMemTransferPiS_S_iib, .Lfunc_end6-_Z16gpuNoMemTransferPiS_S_iib
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixMulPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12matrixMulColPiS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9matrixMulPiS_S_i,@object # @_Z9matrixMulPiS_S_i
.section .rodata,"a",@progbits
.globl _Z9matrixMulPiS_S_i
.p2align 3, 0x0
_Z9matrixMulPiS_S_i:
.quad _Z24__device_stub__matrixMulPiS_S_i
.size _Z9matrixMulPiS_S_i, 8
.type _Z12matrixMulColPiS_S_i,@object # @_Z12matrixMulColPiS_S_i
.globl _Z12matrixMulColPiS_S_i
.p2align 3, 0x0
_Z12matrixMulColPiS_S_i:
.quad _Z27__device_stub__matrixMulColPiS_S_i
.size _Z12matrixMulColPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "MC"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "gpu"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "MT"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "N: "
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\tCPU time: "
.size .L.str.4, 12
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "us"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\tMT\t"
.size .L.str.6, 5
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\tGPU time: "
.size .L.str.7, 12
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\tnt\t"
.size .L.str.8, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9matrixMulPiS_S_i"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12matrixMulColPiS_S_i"
.size .L__unnamed_2, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixMulPiS_S_i
.addrsig_sym _Z27__device_stub__matrixMulColPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixMulPiS_S_i
.addrsig_sym _Z12matrixMulColPiS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define NX 256
#include <stdio.h>
#include <stdlib.h>
#include <cufft.h>
int main(){
/* Define FFT variables */
cufftComplex *in, *out;
cufftHandle plan;
/* Set the GPU device */
cudaSetDevice(0);
/* Allocate memory on GPU for FFT data */
cudaMalloc((void**)&in, NX*sizeof(cufftComplex));
cudaMalloc((void**)&out, NX*sizeof(cufftComplex));
/* Create FFT plan */
cufftPlan1d(&plan, NX, CUFFT_C2C, 1);
/* Perform complex-to-complex FFT transformation */
cufftExecC2C(plan, in, out, CUFFT_FORWARD);
printf("Checking error: %s\n",cudaGetErrorString(cudaGetLastError()));
/* Destroy FFT plan */
cufftDestroy(plan);
/* Free the memory */
cudaFree(in);
cudaFree(out);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define NX 256
#include <stdio.h>
#include <stdlib.h>
#include <cufft.h>
int main(){
/* Define FFT variables */
cufftComplex *in, *out;
cufftHandle plan;
/* Set the GPU device */
cudaSetDevice(0);
/* Allocate memory on GPU for FFT data */
cudaMalloc((void**)&in, NX*sizeof(cufftComplex));
cudaMalloc((void**)&out, NX*sizeof(cufftComplex));
/* Create FFT plan */
cufftPlan1d(&plan, NX, CUFFT_C2C, 1);
/* Perform complex-to-complex FFT transformation */
cufftExecC2C(plan, in, out, CUFFT_FORWARD);
printf("Checking error: %s\n",cudaGetErrorString(cudaGetLastError()));
/* Destroy FFT plan */
cufftDestroy(plan);
/* Free the memory */
cudaFree(in);
cudaFree(out);
} | .file "tmpxft_000018aa_00000000-6_fft-gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Checking error: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2080:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 4(%rsp), %rdi
movl $1, %ecx
movl $41, %edx
movl $256, %esi
call cufftPlan1d@PLT
movl $-1, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl 4(%rsp), %edi
call cufftExecC2C@PLT
call cudaGetLastError@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 4(%rsp), %edi
call cufftDestroy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2080:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2106:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2106:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define NX 256
#include <stdio.h>
#include <stdlib.h>
#include <cufft.h>
int main(){
/* Define FFT variables */
cufftComplex *in, *out;
cufftHandle plan;
/* Set the GPU device */
cudaSetDevice(0);
/* Allocate memory on GPU for FFT data */
cudaMalloc((void**)&in, NX*sizeof(cufftComplex));
cudaMalloc((void**)&out, NX*sizeof(cufftComplex));
/* Create FFT plan */
cufftPlan1d(&plan, NX, CUFFT_C2C, 1);
/* Perform complex-to-complex FFT transformation */
cufftExecC2C(plan, in, out, CUFFT_FORWARD);
printf("Checking error: %s\n",cudaGetErrorString(cudaGetLastError()));
/* Destroy FFT plan */
cufftDestroy(plan);
/* Free the memory */
cudaFree(in);
cudaFree(out);
} | #define NX 256
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <hipfft/hipfft.h>
int main(){
/* Define FFT variables */
hipfftComplex *in, *out;
hipfftHandle plan;
/* Set the GPU device */
hipSetDevice(0);
/* Allocate memory on GPU for FFT data */
hipMalloc((void**)&in, NX*sizeof(hipfftComplex));
hipMalloc((void**)&out, NX*sizeof(hipfftComplex));
/* Create FFT plan */
hipfftPlan1d(&plan, NX, HIPFFT_C2C, 1);
/* Perform complex-to-complex FFT transformation */
hipfftExecC2C(plan, in, out, HIPFFT_FORWARD);
printf("Checking error: %s\n",hipGetErrorString(hipGetLastError()));
/* Destroy FFT plan */
hipfftDestroy(plan);
/* Free the memory */
hipFree(in);
hipFree(out);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #define NX 256
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <hipfft/hipfft.h>
int main(){
/* Define FFT variables */
hipfftComplex *in, *out;
hipfftHandle plan;
/* Set the GPU device */
hipSetDevice(0);
/* Allocate memory on GPU for FFT data */
hipMalloc((void**)&in, NX*sizeof(hipfftComplex));
hipMalloc((void**)&out, NX*sizeof(hipfftComplex));
/* Create FFT plan */
hipfftPlan1d(&plan, NX, HIPFFT_C2C, 1);
/* Perform complex-to-complex FFT transformation */
hipfftExecC2C(plan, in, out, HIPFFT_FORWARD);
printf("Checking error: %s\n",hipGetErrorString(hipGetLastError()));
/* Destroy FFT plan */
hipfftDestroy(plan);
/* Free the memory */
hipFree(in);
hipFree(out);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #define NX 256
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <hipfft/hipfft.h>
int main(){
/* Define FFT variables */
hipfftComplex *in, *out;
hipfftHandle plan;
/* Set the GPU device */
hipSetDevice(0);
/* Allocate memory on GPU for FFT data */
hipMalloc((void**)&in, NX*sizeof(hipfftComplex));
hipMalloc((void**)&out, NX*sizeof(hipfftComplex));
/* Create FFT plan */
hipfftPlan1d(&plan, NX, HIPFFT_C2C, 1);
/* Perform complex-to-complex FFT transformation */
hipfftExecC2C(plan, in, out, HIPFFT_FORWARD);
printf("Checking error: %s\n",hipGetErrorString(hipGetLastError()));
/* Destroy FFT plan */
hipfftDestroy(plan);
/* Free the memory */
hipFree(in);
hipFree(out);
} | .text
.file "fft-gpu.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
xorl %edi, %edi
callq hipSetDevice
leaq 16(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
leaq 8(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movq %rsp, %rdi
movl $256, %esi # imm = 0x100
movl $41, %edx
movl $1, %ecx
callq hipfftPlan1d
movq (%rsp), %rdi
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
movl $-1, %ecx
callq hipfftExecC2C
callq hipGetLastError
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
callq hipfftDestroy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Checking error: %s\n"
.size .L.str, 20
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000018aa_00000000-6_fft-gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Checking error: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2080:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 4(%rsp), %rdi
movl $1, %ecx
movl $41, %edx
movl $256, %esi
call cufftPlan1d@PLT
movl $-1, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl 4(%rsp), %edi
call cufftExecC2C@PLT
call cudaGetLastError@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 4(%rsp), %edi
call cufftDestroy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2080:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2106:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2106:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "fft-gpu.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
xorl %edi, %edi
callq hipSetDevice
leaq 16(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
leaq 8(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movq %rsp, %rdi
movl $256, %esi # imm = 0x100
movl $41, %edx
movl $1, %ecx
callq hipfftPlan1d
movq (%rsp), %rdi
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
movl $-1, %ecx
callq hipfftExecC2C
callq hipGetLastError
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
callq hipfftDestroy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Checking error: %s\n"
.size .L.str, 20
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cstdlib>
#include <sys/time.h>
using namespace std;
const int BLOCKSIZE = 32;
// Global variables to calculate sizes
int *sizes_gpu, *subtotals_gpu, *total_gpu; // For finding sums
// Stopwatch class
class Stopwatch {
private:
timeval initialTime;
public:
Stopwatch() {
reset();
}
void reset() {
gettimeofday(&initialTime, 0);
}
float elapsed() const {
timeval currentTime;
gettimeofday(¤tTime, 0);
return (float) (currentTime.tv_sec - initialTime.tv_sec) + ((float) (currentTime.tv_usec - initialTime.tv_usec))/1000000;
}
};
// Create an TownSet of size n with all false entries
void createTownSet(char *current, int n) {
char temp[n];
for (int i=0; i<n; i++)
temp[i] = 0;
cudaMemcpy(¤t, &temp, n, cudaMemcpyHostToDevice);
}
// Take a union of current_gpu and with specified townset and store it in current_gpu
__global__ void unionTownSet_gpu(char *current, char *townSets, int i, int n) {
int threadId = blockIdx.x*blockDim.x + threadIdx.x;
current[threadId] += townSets[i*n+threadId];
}
void unionTownSet(char *current, char *townSets, int i, int n) {
unionTownSet_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(current, townSets, i, n);
}
// Find the total population in all of the town sets
__global__ void sizeTownSet_gpu(char *current, int *pops, int n, int *sizes) {
int threadId = blockIdx.x*blockDim.x + threadIdx.x;
if (current[threadId] == 1)
sizes[threadId] = pops[threadId];
else
sizes[threadId] = 0;
}
__global__ void totals_gpu(int *output, int *input) {
__shared__ int temp[BLOCKSIZE];
int threadId = blockIdx.x*blockDim.x + threadIdx.x;
temp[threadIdx.x] = input[threadId];
__syncthreads();
for (int s=blockDim.x/2; s>0; s>>=1) {
if (threadIdx.x < s)
temp[threadIdx.x] += temp[threadIdx.x+s];
__syncthreads();
}
if (threadIdx.x == 0)
output[blockIdx.x] = temp[0];
}
int sizeTownSet(char *current, int *pops, int n) {
sizeTownSet_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(current, pops, n, sizes_gpu);
totals_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(subtotals_gpu, sizes_gpu); // Calculate subtotals
totals_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(total_gpu, subtotals_gpu); // Calculate subtotals
int result;
cudaMemcpy(total_gpu, &result, sizeof(int), cudaMemcpyDeviceToHost);
return result;
}
// Count number of towns in a set
__global__ void countTownSet_gpu(char *current, int n, int *sizes) {
int threadId = blockIdx.x*blockDim.x + threadIdx.x;
if (current[threadId] == 1)
sizes[threadId] = 1;
else
sizes[threadId] = 0;
}
int countTownSet(char *current, int n) {
countTownSet_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(current, n, sizes_gpu);
totals_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(subtotals_gpu, sizes_gpu); // Calculate subtotals
totals_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(total_gpu, subtotals_gpu); // Calculate subtotals
int result;
cudaMemcpy(total_gpu, &result, sizeof(int), cudaMemcpyDeviceToHost);
return result;
}
int main(int argc, char **argv) {
if (argc != 4) {
cout << "Usage: " << argv[0] << " mode size reps" << endl;
cout << " Mode is one of the following:" << endl;
cout << " a test full algorithm" << endl;
cout << " u test taking unions" << endl;
cout << " s test calculating sizes" << endl;
exit(0);
}
int size = atoi(argv[2]);
int reps = atoi(argv[3]);
char mode = argv[1][0];
// Initialize data
char townSets[size*size];
for (int i=0; i<size; i++) {
for (int j=0; j<size; j++) {
if (rand() < .1*RAND_MAX)
townSets[i*size+j] = 1;
else
townSets[i*size+j] = 0;
}
townSets[i*size+i] = 1;
}
int pops[size];
int totalPop = 0;
for (int i=0; i<size; i++) {
pops[i] = rand() % 256;
totalPop += pops[i];
}
// Perform the tests
int rounds, totalRounds;
Stopwatch timer;
// Copy the data to the GPU
char *townSets_gpu;
int *pops_gpu;
char *current_gpu; // Stores working townset
cudaMalloc((void**) &townSets_gpu, size*size);
cudaMemcpy(townSets_gpu, townSets, size*size, cudaMemcpyHostToDevice);
cudaMalloc((void**) &pops_gpu, size*sizeof(int));
cudaMemcpy(pops_gpu, pops, size*sizeof(int), cudaMemcpyHostToDevice);
cudaMalloc((void**) ¤t_gpu, size);
cudaMalloc((void**) &sizes_gpu, size);
cudaMalloc((void**) &subtotals_gpu, size/BLOCKSIZE);
cudaMalloc((void**) &total_gpu, 1);
// Do the simulation
switch (mode) {
case 'a':
totalRounds=0;
for (int r=0; r<reps; r++) {
createTownSet(current_gpu, size);
rounds = 0;
while (sizeTownSet(current_gpu, pops_gpu, size) <= totalPop/2) {
unionTownSet(current_gpu, townSets_gpu, rand()%size, size);
rounds++;
}
totalRounds += rounds;
}
cout << "Average number of rounds = " << ((float) totalRounds/reps) << endl;
break;
case 'u':
createTownSet(current_gpu, size);
for (int r=0; r<reps; r++)
unionTownSet(current_gpu, townSets_gpu, rand()%size, size);
break;
case 's':
int s;
for (int r=0; r<reps; r++)
s = sizeTownSet(current_gpu, pops_gpu, size);
break;
}
cout << "Elapsed time " << timer.elapsed() << endl;
} | code for sm_80
Function : _Z16countTownSet_gpuPciPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0050*/ IADD3 R4, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x000fc80007f1e0ff */
/*0060*/ LEA.HI.X.SX32 R5, R2, c[0x0][0x164], 0x1, P0 ; /* 0x0000590002057a11 */
/* 0x000fca00000f0eff */
/*0070*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1100 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fe200078e0203 */
/*00a0*/ ISETP.NE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x004fc80003f05270 */
/*00b0*/ SEL R7, RZ, 0x1, P0 ; /* 0x00000001ff077807 */
/* 0x000fca0000000000 */
/*00c0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10totals_gpuPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0060*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0203 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0090*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00a0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00b0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00c0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041e80000004800 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00e0*/ @!P1 BRA 0x1b0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x001fe200078e00ff */
/*0100*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fc80008000f00 */
/*0110*/ ISETP.GE.U32.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26070 */
/*0120*/ @!P1 IMAD R2, R3, 0x4, R0 ; /* 0x0000000403029824 */
/* 0x000fe200078e0200 */
/*0130*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */
/* 0x000fe20000004800 */
/*0140*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0150*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0160*/ @!P1 IADD3 R4, R4, R5, RZ ; /* 0x0000000504049210 */
/* 0x001fca0007ffe0ff */
/*0170*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */
/* 0x0001e80000004800 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*01a0*/ @P1 BRA 0x110 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*01c0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*01d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01e0*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fca00078e0003 */
/*01f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15sizeTownSet_gpuPcPiiS0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0050*/ SHF.R.S32.HI R7, RZ, 0x1f, R0 ; /* 0x0000001fff077819 */
/* 0x000fe40000011400 */
/*0060*/ IADD3 R4, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000047a10 */
/* 0x000fc80007f1e0ff */
/*0070*/ IADD3.X R5, R7, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590007057a10 */
/* 0x000fca00007fe4ff */
/*0080*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1100 */
/*0090*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*00a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fe200078e0203 */
/*00b0*/ ISETP.NE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x004fda0003f05270 */
/*00c0*/ @P0 STG.E [R2.64], RZ ; /* 0x000000ff02000986 */
/* 0x0001e2000c101904 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ LEA R4, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000047a11 */
/* 0x000fc800078010ff */
/*00f0*/ LEA.HI.X R5, R0, c[0x0][0x16c], R7, 0x2, P0 ; /* 0x00005b0000057a11 */
/* 0x000fcc00000f1407 */
/*0100*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0110*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z16unionTownSet_gpuPcS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R5, c[0x0][0x174] ; /* 0x00005d0000057a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD R5, R5, c[0x0][0x170], R0 ; /* 0x00005c0005057a24 */
/* 0x000fe200078e0200 */
/*0070*/ IADD3 R2, P1, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f3e0ff */
/*0080*/ IADD3 R4, P0, R5.reuse, c[0x0][0x168], RZ ; /* 0x00005a0005047a10 */
/* 0x040fe40007f1e0ff */
/*0090*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P1 ; /* 0x0000590000037a11 */
/* 0x000fe400008f0eff */
/*00a0*/ LEA.HI.X.SX32 R5, R5, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0005057a11 */
/* 0x000fc600000f0eff */
/*00b0*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea8000c1e1100 */
/*00c0*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1100 */
/*00d0*/ IMAD.IADD R7, R4, 0x1, R7 ; /* 0x0000000104077824 */
/* 0x004fca00078e0207 */
/*00e0*/ STG.E.U8 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101104 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cstdlib>
#include <sys/time.h>
using namespace std;
const int BLOCKSIZE = 32;
// Global variables to calculate sizes
int *sizes_gpu, *subtotals_gpu, *total_gpu; // For finding sums
// Stopwatch class
class Stopwatch {
private:
timeval initialTime;
public:
Stopwatch() {
reset();
}
void reset() {
gettimeofday(&initialTime, 0);
}
float elapsed() const {
timeval currentTime;
gettimeofday(¤tTime, 0);
return (float) (currentTime.tv_sec - initialTime.tv_sec) + ((float) (currentTime.tv_usec - initialTime.tv_usec))/1000000;
}
};
// Create an TownSet of size n with all false entries
void createTownSet(char *current, int n) {
char temp[n];
for (int i=0; i<n; i++)
temp[i] = 0;
cudaMemcpy(¤t, &temp, n, cudaMemcpyHostToDevice);
}
// Take a union of current_gpu and with specified townset and store it in current_gpu
__global__ void unionTownSet_gpu(char *current, char *townSets, int i, int n) {
int threadId = blockIdx.x*blockDim.x + threadIdx.x;
current[threadId] += townSets[i*n+threadId];
}
void unionTownSet(char *current, char *townSets, int i, int n) {
unionTownSet_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(current, townSets, i, n);
}
// Find the total population in all of the town sets
__global__ void sizeTownSet_gpu(char *current, int *pops, int n, int *sizes) {
int threadId = blockIdx.x*blockDim.x + threadIdx.x;
if (current[threadId] == 1)
sizes[threadId] = pops[threadId];
else
sizes[threadId] = 0;
}
__global__ void totals_gpu(int *output, int *input) {
__shared__ int temp[BLOCKSIZE];
int threadId = blockIdx.x*blockDim.x + threadIdx.x;
temp[threadIdx.x] = input[threadId];
__syncthreads();
for (int s=blockDim.x/2; s>0; s>>=1) {
if (threadIdx.x < s)
temp[threadIdx.x] += temp[threadIdx.x+s];
__syncthreads();
}
if (threadIdx.x == 0)
output[blockIdx.x] = temp[0];
}
int sizeTownSet(char *current, int *pops, int n) {
sizeTownSet_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(current, pops, n, sizes_gpu);
totals_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(subtotals_gpu, sizes_gpu); // Calculate subtotals
totals_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(total_gpu, subtotals_gpu); // Calculate subtotals
int result;
cudaMemcpy(total_gpu, &result, sizeof(int), cudaMemcpyDeviceToHost);
return result;
}
// Count number of towns in a set
__global__ void countTownSet_gpu(char *current, int n, int *sizes) {
int threadId = blockIdx.x*blockDim.x + threadIdx.x;
if (current[threadId] == 1)
sizes[threadId] = 1;
else
sizes[threadId] = 0;
}
int countTownSet(char *current, int n) {
countTownSet_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(current, n, sizes_gpu);
totals_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(subtotals_gpu, sizes_gpu); // Calculate subtotals
totals_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(total_gpu, subtotals_gpu); // Calculate subtotals
int result;
cudaMemcpy(total_gpu, &result, sizeof(int), cudaMemcpyDeviceToHost);
return result;
}
int main(int argc, char **argv) {
if (argc != 4) {
cout << "Usage: " << argv[0] << " mode size reps" << endl;
cout << " Mode is one of the following:" << endl;
cout << " a test full algorithm" << endl;
cout << " u test taking unions" << endl;
cout << " s test calculating sizes" << endl;
exit(0);
}
int size = atoi(argv[2]);
int reps = atoi(argv[3]);
char mode = argv[1][0];
// Initialize data
char townSets[size*size];
for (int i=0; i<size; i++) {
for (int j=0; j<size; j++) {
if (rand() < .1*RAND_MAX)
townSets[i*size+j] = 1;
else
townSets[i*size+j] = 0;
}
townSets[i*size+i] = 1;
}
int pops[size];
int totalPop = 0;
for (int i=0; i<size; i++) {
pops[i] = rand() % 256;
totalPop += pops[i];
}
// Perform the tests
int rounds, totalRounds;
Stopwatch timer;
// Copy the data to the GPU
char *townSets_gpu;
int *pops_gpu;
char *current_gpu; // Stores working townset
cudaMalloc((void**) &townSets_gpu, size*size);
cudaMemcpy(townSets_gpu, townSets, size*size, cudaMemcpyHostToDevice);
cudaMalloc((void**) &pops_gpu, size*sizeof(int));
cudaMemcpy(pops_gpu, pops, size*sizeof(int), cudaMemcpyHostToDevice);
cudaMalloc((void**) ¤t_gpu, size);
cudaMalloc((void**) &sizes_gpu, size);
cudaMalloc((void**) &subtotals_gpu, size/BLOCKSIZE);
cudaMalloc((void**) &total_gpu, 1);
// Do the simulation
switch (mode) {
case 'a':
totalRounds=0;
for (int r=0; r<reps; r++) {
createTownSet(current_gpu, size);
rounds = 0;
while (sizeTownSet(current_gpu, pops_gpu, size) <= totalPop/2) {
unionTownSet(current_gpu, townSets_gpu, rand()%size, size);
rounds++;
}
totalRounds += rounds;
}
cout << "Average number of rounds = " << ((float) totalRounds/reps) << endl;
break;
case 'u':
createTownSet(current_gpu, size);
for (int r=0; r<reps; r++)
unionTownSet(current_gpu, townSets_gpu, rand()%size, size);
break;
case 's':
int s;
for (int r=0; r<reps; r++)
s = sizeTownSet(current_gpu, pops_gpu, size);
break;
}
cout << "Elapsed time " << timer.elapsed() << endl;
} | .file "tmpxft_00151556_00000000-6_TownSet_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3681:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3681:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13createTownSetPci
.type _Z13createTownSetPci, @function
_Z13createTownSetPci:
.LFB3674:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
subq $32, %rsp
movq %rdi, -24(%rbp)
movq %fs:40, %rax
movq %rax, -8(%rbp)
xorl %eax, %eax
movslq %esi, %rdi
leaq 15(%rdi), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L4:
cmpq %rdx, %rsp
je .L5
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L4
.L5:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L6
orq $0, -8(%rsp,%rax)
.L6:
movq %rsp, %r8
testl %esi, %esi
jle .L7
movq %r8, %rax
leaq (%rdi,%r8), %rdx
.L8:
movb $0, (%rax)
addq $1, %rax
cmpq %rdx, %rax
jne .L8
.L7:
leaq -24(%rbp), %rax
movl $1, %ecx
movq %rdi, %rdx
movq %r8, %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movq -8(%rbp), %rax
subq %fs:40, %rax
jne .L12
leave
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3674:
.size _Z13createTownSetPci, .-_Z13createTownSetPci
.globl _Z40__device_stub__Z16unionTownSet_gpuPcS_iiPcS_ii
.type _Z40__device_stub__Z16unionTownSet_gpuPcS_iiPcS_ii, @function
_Z40__device_stub__Z16unionTownSet_gpuPcS_iiPcS_ii:
.LFB3703:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16unionTownSet_gpuPcS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3703:
.size _Z40__device_stub__Z16unionTownSet_gpuPcS_iiPcS_ii, .-_Z40__device_stub__Z16unionTownSet_gpuPcS_iiPcS_ii
.globl _Z16unionTownSet_gpuPcS_ii
.type _Z16unionTownSet_gpuPcS_ii, @function
_Z16unionTownSet_gpuPcS_ii:
.LFB3704:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z16unionTownSet_gpuPcS_iiPcS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _Z16unionTownSet_gpuPcS_ii, .-_Z16unionTownSet_gpuPcS_ii
.globl _Z12unionTownSetPcS_ii
.type _Z12unionTownSetPcS_ii, @function
_Z12unionTownSetPcS_ii:
.LFB3675:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %r12
movl %edx, %r13d
movl %ecx, %ebx
movl $32, 20(%rsp)
movl $1, 24(%rsp)
leal 31(%rcx), %eax
testl %ecx, %ecx
cmovns %ecx, %eax
sarl $5, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L21:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl %ebx, %ecx
movl %r13d, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _Z40__device_stub__Z16unionTownSet_gpuPcS_iiPcS_ii
jmp .L21
.cfi_endproc
.LFE3675:
.size _Z12unionTownSetPcS_ii, .-_Z12unionTownSetPcS_ii
.globl _Z41__device_stub__Z15sizeTownSet_gpuPcPiiS0_PcPiiS0_
.type _Z41__device_stub__Z15sizeTownSet_gpuPcPiiS0_PcPiiS0_, @function
_Z41__device_stub__Z15sizeTownSet_gpuPcPiiS0_PcPiiS0_:
.LFB3705:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15sizeTownSet_gpuPcPiiS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3705:
.size _Z41__device_stub__Z15sizeTownSet_gpuPcPiiS0_PcPiiS0_, .-_Z41__device_stub__Z15sizeTownSet_gpuPcPiiS0_PcPiiS0_
.globl _Z15sizeTownSet_gpuPcPiiS0_
.type _Z15sizeTownSet_gpuPcPiiS0_, @function
_Z15sizeTownSet_gpuPcPiiS0_:
.LFB3706:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15sizeTownSet_gpuPcPiiS0_PcPiiS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3706:
.size _Z15sizeTownSet_gpuPcPiiS0_, .-_Z15sizeTownSet_gpuPcPiiS0_
.globl _Z32__device_stub__Z10totals_gpuPiS_PiS_
.type _Z32__device_stub__Z10totals_gpuPiS_PiS_, @function
_Z32__device_stub__Z10totals_gpuPiS_PiS_:
.LFB3707:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10totals_gpuPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3707:
.size _Z32__device_stub__Z10totals_gpuPiS_PiS_, .-_Z32__device_stub__Z10totals_gpuPiS_PiS_
.globl _Z10totals_gpuPiS_
.type _Z10totals_gpuPiS_, @function
_Z10totals_gpuPiS_:
.LFB3708:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10totals_gpuPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3708:
.size _Z10totals_gpuPiS_, .-_Z10totals_gpuPiS_
.globl _Z11sizeTownSetPcPii
.type _Z11sizeTownSetPcPii, @function
_Z11sizeTownSetPcPii:
.LFB3676:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movq %rsi, %r13
movl %edx, %ebp
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $32, 12(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
leal 31(%rdx), %ebx
testl %edx, %edx
cmovns %edx, %ebx
sarl $5, %ebx
movl %ebx, (%rsp)
movl $1, 4(%rsp)
movl $1, 8(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 12(%rsp), %rdx
movl $1, %ecx
movq (%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L42:
movl $32, 12(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl %ebx, (%rsp)
movl $1, 4(%rsp)
movl $1, 8(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 12(%rsp), %rdx
movl $1, %ecx
movq (%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L43:
movl $32, 12(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl %ebx, (%rsp)
movl $1, 4(%rsp)
movl $1, 8(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 12(%rsp), %rdx
movl $1, %ecx
movq (%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L44:
leaq 12(%rsp), %rsi
movl $2, %ecx
movl $4, %edx
movq total_gpu(%rip), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %eax
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L50
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
movq sizes_gpu(%rip), %rcx
movl %ebp, %edx
movq %r13, %rsi
movq %r12, %rdi
call _Z41__device_stub__Z15sizeTownSet_gpuPcPiiS0_PcPiiS0_
jmp .L42
.L48:
movq sizes_gpu(%rip), %rsi
movq subtotals_gpu(%rip), %rdi
call _Z32__device_stub__Z10totals_gpuPiS_PiS_
jmp .L43
.L49:
movq subtotals_gpu(%rip), %rsi
movq total_gpu(%rip), %rdi
call _Z32__device_stub__Z10totals_gpuPiS_PiS_
jmp .L44
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3676:
.size _Z11sizeTownSetPcPii, .-_Z11sizeTownSetPcPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Usage: "
.LC1:
.string " mode size reps"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string " Mode is one of the following:"
.section .rodata.str1.1
.LC3:
.string " a test full algorithm"
.LC4:
.string " u test taking unions"
.LC5:
.string " s test calculating sizes"
.LC6:
.string "Average number of rounds = "
.LC7:
.string "Elapsed time "
.text
.globl main
.type main, @function
main:
.LFB3678:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $152, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
cmpl $4, %edi
je .L52
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%r12), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC2(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %edi
call exit@PLT
.L52:
movq 16(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, %ebx
movq 24(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, -184(%rbp)
movl %eax, -156(%rbp)
movq 8(%r12), %rax
movzbl (%rax), %eax
movb %al, -157(%rbp)
movl %r13d, %eax
imull %r13d, %eax
cltq
movq %rax, -176(%rbp)
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L53:
cmpq %rdx, %rsp
je .L54
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L53
.L54:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L55
orq $0, -8(%rsp,%rax)
.L55:
movq %rsp, %r12
testl %r13d, %r13d
jle .L56
movslq %r13d, %rax
movq %rax, -168(%rbp)
addq $1, %rax
movq %rax, -144(%rbp)
movl %r13d, -148(%rbp)
movl %r13d, -152(%rbp)
movl $0, %r14d
movq %r13, -192(%rbp)
movl %ebx, -136(%rbp)
movl %r13d, %ebx
movq %r12, %r15
jmp .L57
.L58:
movslq %r13d, %rax
movb $0, (%r12,%rax)
.L59:
addl $1, %r13d
cmpl %ebx, %r13d
je .L92
.L60:
call rand@PLT
cmpl $214748364, %eax
jg .L58
movslq %r13d, %rax
movb $1, (%r12,%rax)
jmp .L59
.L92:
movb $1, (%r15)
addl $1, %r14d
movq -144(%rbp), %rax
addq %rax, %r15
movl -148(%rbp), %eax
addl %eax, %ebx
movl -136(%rbp), %eax
cmpl %eax, %r14d
je .L61
.L57:
movl %ebx, %r13d
movl -152(%rbp), %eax
subl %eax, %r13d
jmp .L60
.L61:
movq -192(%rbp), %r13
movl -136(%rbp), %ebx
movq -168(%rbp), %rax
salq $2, %rax
movq %rax, -136(%rbp)
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L62:
cmpq %rdx, %rsp
je .L63
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L62
.L63:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L64
orq $0, -8(%rsp,%rax)
.L64:
movq %rsp, %rax
movq %rax, -144(%rbp)
movq %rax, %r14
movl %r13d, %edx
leaq (%rax,%rdx,4), %r15
movl $0, %r13d
.L65:
call rand@PLT
cltd
shrl $24, %edx
addl %edx, %eax
movzbl %al, %eax
subl %edx, %eax
movl %eax, (%r14)
addl %eax, %r13d
addq $4, %r14
cmpq %r15, %r14
jne .L65
.L79:
leaq -96(%rbp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq -120(%rbp), %rdi
movq -176(%rbp), %r15
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq -120(%rbp), %rdi
call cudaMemcpy@PLT
leaq -112(%rbp), %rdi
movq -136(%rbp), %r15
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq -144(%rbp), %rsi
movq -112(%rbp), %rdi
call cudaMemcpy@PLT
leaq -104(%rbp), %rdi
movq -168(%rbp), %r15
movq %r15, %rsi
call cudaMalloc@PLT
movq %r15, %rsi
leaq sizes_gpu(%rip), %rdi
call cudaMalloc@PLT
movl $32, %ecx
movl %ebx, %eax
cltd
idivl %ecx
movslq %eax, %rsi
leaq subtotals_gpu(%rip), %rdi
call cudaMalloc@PLT
movl $1, %esi
leaq total_gpu(%rip), %rdi
call cudaMalloc@PLT
movzbl -157(%rbp), %eax
cmpb $115, %al
je .L66
cmpb $117, %al
je .L67
cmpb $97, %al
je .L68
.L69:
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
leaq -80(%rbp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq -72(%rbp), %rax
subq -88(%rbp), %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC8(%rip), %xmm0
movq -80(%rbp), %rax
subq -96(%rbp), %rax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
addss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L93
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L66:
.cfi_restore_state
movl $0, %r12d
movl -156(%rbp), %r13d
cmpl $0, -184(%rbp)
jle .L69
.L70:
movl %ebx, %edx
movq -112(%rbp), %rsi
movq -104(%rbp), %rdi
call _Z11sizeTownSetPcPii
addl $1, %r12d
cmpl %r13d, %r12d
jne .L70
jmp .L69
.L68:
cmpl $0, -184(%rbp)
jle .L82
movl $2, %ecx
movl %r13d, %eax
cltd
idivl %ecx
movl %eax, %r13d
movl $0, %r14d
movl $0, %r15d
jmp .L74
.L73:
call rand@PLT
cltd
idivl %ebx
movl %ebx, %ecx
movq -120(%rbp), %rsi
movq -104(%rbp), %rdi
call _Z12unionTownSetPcS_ii
addl $1, %r12d
.L72:
movl %ebx, %edx
movq -112(%rbp), %rsi
movq -104(%rbp), %rdi
call _Z11sizeTownSetPcPii
cmpl %eax, %r13d
jge .L73
addl %r12d, %r15d
addl $1, %r14d
movl -156(%rbp), %eax
cmpl %eax, %r14d
je .L71
.L74:
movl %ebx, %esi
movq -104(%rbp), %rdi
call _Z13createTownSetPci
movl $0, %r12d
jmp .L72
.L82:
movl $0, %r15d
.L71:
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtsi2ssl %r15d, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl -184(%rbp), %xmm1
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L69
.L67:
movl %ebx, %esi
movq -104(%rbp), %rdi
call _Z13createTownSetPci
cmpl $0, -184(%rbp)
jle .L69
movl $0, %r12d
movl -156(%rbp), %r13d
.L75:
call rand@PLT
cltd
idivl %ebx
movl %ebx, %ecx
movq -120(%rbp), %rsi
movq -104(%rbp), %rdi
call _Z12unionTownSetPcS_ii
addl $1, %r12d
cmpl %r13d, %r12d
jne .L75
jmp .L69
.L56:
movslq %r13d, %rax
movq %rax, -168(%rbp)
salq $2, %rax
movq %rax, -136(%rbp)
leaq 15(%rax), %rdx
movq %rdx, %rax
andq $-16, %rax
andq $-4096, %rdx
movq %rsp, %rcx
subq %rdx, %rcx
.L76:
cmpq %rcx, %rsp
je .L77
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L76
.L77:
movq %rax, %rdx
andl $4095, %edx
subq %rdx, %rsp
testq %rdx, %rdx
je .L78
orq $0, -8(%rsp,%rdx)
.L78:
movq %rsp, -144(%rbp)
movl $0, %r13d
jmp .L79
.L93:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3678:
.size main, .-main
.globl _Z39__device_stub__Z16countTownSet_gpuPciPiPciPi
.type _Z39__device_stub__Z16countTownSet_gpuPciPiPciPi, @function
_Z39__device_stub__Z16countTownSet_gpuPciPiPciPi:
.LFB3709:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L98
.L94:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L99
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L98:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16countTownSet_gpuPciPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L94
.L99:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3709:
.size _Z39__device_stub__Z16countTownSet_gpuPciPiPciPi, .-_Z39__device_stub__Z16countTownSet_gpuPciPiPciPi
.globl _Z16countTownSet_gpuPciPi
.type _Z16countTownSet_gpuPciPi, @function
_Z16countTownSet_gpuPciPi:
.LFB3710:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16countTownSet_gpuPciPiPciPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3710:
.size _Z16countTownSet_gpuPciPi, .-_Z16countTownSet_gpuPciPi
.globl _Z12countTownSetPci
.type _Z12countTownSetPci, @function
_Z12countTownSetPci:
.LFB3677:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r12
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $32, 12(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
leal 31(%rsi), %ebx
testl %esi, %esi
cmovns %esi, %ebx
sarl $5, %ebx
movl %ebx, (%rsp)
movl $1, 4(%rsp)
movl $1, 8(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 12(%rsp), %rdx
movl $1, %ecx
movq (%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L108
.L103:
movl $32, 12(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl %ebx, (%rsp)
movl $1, 4(%rsp)
movl $1, 8(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 12(%rsp), %rdx
movl $1, %ecx
movq (%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L109
.L104:
movl $32, 12(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl %ebx, (%rsp)
movl $1, 4(%rsp)
movl $1, 8(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 12(%rsp), %rdx
movl $1, %ecx
movq (%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L110
.L105:
leaq 12(%rsp), %rsi
movl $2, %ecx
movl $4, %edx
movq total_gpu(%rip), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %eax
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L111
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L108:
.cfi_restore_state
movq sizes_gpu(%rip), %rdx
movl %ebp, %esi
movq %r12, %rdi
call _Z39__device_stub__Z16countTownSet_gpuPciPiPciPi
jmp .L103
.L109:
movq sizes_gpu(%rip), %rsi
movq subtotals_gpu(%rip), %rdi
call _Z32__device_stub__Z10totals_gpuPiS_PiS_
jmp .L104
.L110:
movq subtotals_gpu(%rip), %rsi
movq total_gpu(%rip), %rdi
call _Z32__device_stub__Z10totals_gpuPiS_PiS_
jmp .L105
.L111:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3677:
.size _Z12countTownSetPci, .-_Z12countTownSetPci
.section .rodata.str1.1
.LC9:
.string "_Z16countTownSet_gpuPciPi"
.LC10:
.string "_Z10totals_gpuPiS_"
.LC11:
.string "_Z15sizeTownSet_gpuPcPiiS0_"
.LC12:
.string "_Z16unionTownSet_gpuPcS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3712:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z16countTownSet_gpuPciPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z10totals_gpuPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z15sizeTownSet_gpuPcPiiS0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z16unionTownSet_gpuPcS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3712:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl total_gpu
.bss
.align 8
.type total_gpu, @object
.size total_gpu, 8
total_gpu:
.zero 8
.globl subtotals_gpu
.align 8
.type subtotals_gpu, @object
.size subtotals_gpu, 8
subtotals_gpu:
.zero 8
.globl sizes_gpu
.align 8
.type sizes_gpu, @object
.size sizes_gpu, 8
sizes_gpu:
.zero 8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC8:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cstdlib>
#include <sys/time.h>
using namespace std;
const int BLOCKSIZE = 32;
// Global variables to calculate sizes
int *sizes_gpu, *subtotals_gpu, *total_gpu; // For finding sums
// Stopwatch class
class Stopwatch {
private:
timeval initialTime;
public:
Stopwatch() {
reset();
}
void reset() {
gettimeofday(&initialTime, 0);
}
float elapsed() const {
timeval currentTime;
gettimeofday(¤tTime, 0);
return (float) (currentTime.tv_sec - initialTime.tv_sec) + ((float) (currentTime.tv_usec - initialTime.tv_usec))/1000000;
}
};
// Create an TownSet of size n with all false entries
void createTownSet(char *current, int n) {
char temp[n];
for (int i=0; i<n; i++)
temp[i] = 0;
cudaMemcpy(¤t, &temp, n, cudaMemcpyHostToDevice);
}
// Take a union of current_gpu and with specified townset and store it in current_gpu
__global__ void unionTownSet_gpu(char *current, char *townSets, int i, int n) {
int threadId = blockIdx.x*blockDim.x + threadIdx.x;
current[threadId] += townSets[i*n+threadId];
}
void unionTownSet(char *current, char *townSets, int i, int n) {
unionTownSet_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(current, townSets, i, n);
}
// Find the total population in all of the town sets
__global__ void sizeTownSet_gpu(char *current, int *pops, int n, int *sizes) {
int threadId = blockIdx.x*blockDim.x + threadIdx.x;
if (current[threadId] == 1)
sizes[threadId] = pops[threadId];
else
sizes[threadId] = 0;
}
__global__ void totals_gpu(int *output, int *input) {
__shared__ int temp[BLOCKSIZE];
int threadId = blockIdx.x*blockDim.x + threadIdx.x;
temp[threadIdx.x] = input[threadId];
__syncthreads();
for (int s=blockDim.x/2; s>0; s>>=1) {
if (threadIdx.x < s)
temp[threadIdx.x] += temp[threadIdx.x+s];
__syncthreads();
}
if (threadIdx.x == 0)
output[blockIdx.x] = temp[0];
}
int sizeTownSet(char *current, int *pops, int n) {
sizeTownSet_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(current, pops, n, sizes_gpu);
totals_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(subtotals_gpu, sizes_gpu); // Calculate subtotals
totals_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(total_gpu, subtotals_gpu); // Calculate subtotals
int result;
cudaMemcpy(total_gpu, &result, sizeof(int), cudaMemcpyDeviceToHost);
return result;
}
// Count number of towns in a set
__global__ void countTownSet_gpu(char *current, int n, int *sizes) {
int threadId = blockIdx.x*blockDim.x + threadIdx.x;
if (current[threadId] == 1)
sizes[threadId] = 1;
else
sizes[threadId] = 0;
}
int countTownSet(char *current, int n) {
countTownSet_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(current, n, sizes_gpu);
totals_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(subtotals_gpu, sizes_gpu); // Calculate subtotals
totals_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(total_gpu, subtotals_gpu); // Calculate subtotals
int result;
cudaMemcpy(total_gpu, &result, sizeof(int), cudaMemcpyDeviceToHost);
return result;
}
int main(int argc, char **argv) {
if (argc != 4) {
cout << "Usage: " << argv[0] << " mode size reps" << endl;
cout << " Mode is one of the following:" << endl;
cout << " a test full algorithm" << endl;
cout << " u test taking unions" << endl;
cout << " s test calculating sizes" << endl;
exit(0);
}
int size = atoi(argv[2]);
int reps = atoi(argv[3]);
char mode = argv[1][0];
// Initialize data
char townSets[size*size];
for (int i=0; i<size; i++) {
for (int j=0; j<size; j++) {
if (rand() < .1*RAND_MAX)
townSets[i*size+j] = 1;
else
townSets[i*size+j] = 0;
}
townSets[i*size+i] = 1;
}
int pops[size];
int totalPop = 0;
for (int i=0; i<size; i++) {
pops[i] = rand() % 256;
totalPop += pops[i];
}
// Perform the tests
int rounds, totalRounds;
Stopwatch timer;
// Copy the data to the GPU
char *townSets_gpu;
int *pops_gpu;
char *current_gpu; // Stores working townset
cudaMalloc((void**) &townSets_gpu, size*size);
cudaMemcpy(townSets_gpu, townSets, size*size, cudaMemcpyHostToDevice);
cudaMalloc((void**) &pops_gpu, size*sizeof(int));
cudaMemcpy(pops_gpu, pops, size*sizeof(int), cudaMemcpyHostToDevice);
cudaMalloc((void**) ¤t_gpu, size);
cudaMalloc((void**) &sizes_gpu, size);
cudaMalloc((void**) &subtotals_gpu, size/BLOCKSIZE);
cudaMalloc((void**) &total_gpu, 1);
// Do the simulation
switch (mode) {
case 'a':
totalRounds=0;
for (int r=0; r<reps; r++) {
createTownSet(current_gpu, size);
rounds = 0;
while (sizeTownSet(current_gpu, pops_gpu, size) <= totalPop/2) {
unionTownSet(current_gpu, townSets_gpu, rand()%size, size);
rounds++;
}
totalRounds += rounds;
}
cout << "Average number of rounds = " << ((float) totalRounds/reps) << endl;
break;
case 'u':
createTownSet(current_gpu, size);
for (int r=0; r<reps; r++)
unionTownSet(current_gpu, townSets_gpu, rand()%size, size);
break;
case 's':
int s;
for (int r=0; r<reps; r++)
s = sizeTownSet(current_gpu, pops_gpu, size);
break;
}
cout << "Elapsed time " << timer.elapsed() << endl;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <sys/time.h>
using namespace std;
const int BLOCKSIZE = 32;
// Global variables to calculate sizes
int *sizes_gpu, *subtotals_gpu, *total_gpu; // For finding sums
// Stopwatch class
class Stopwatch {
private:
timeval initialTime;
public:
Stopwatch() {
reset();
}
void reset() {
gettimeofday(&initialTime, 0);
}
float elapsed() const {
timeval currentTime;
gettimeofday(¤tTime, 0);
return (float) (currentTime.tv_sec - initialTime.tv_sec) + ((float) (currentTime.tv_usec - initialTime.tv_usec))/1000000;
}
};
// Create an TownSet of size n with all false entries
void createTownSet(char *current, int n) {
char temp[n];
for (int i=0; i<n; i++)
temp[i] = 0;
hipMemcpy(¤t, &temp, n, hipMemcpyHostToDevice);
}
// Take a union of current_gpu and with specified townset and store it in current_gpu
__global__ void unionTownSet_gpu(char *current, char *townSets, int i, int n) {
int threadId = blockIdx.x*blockDim.x + threadIdx.x;
current[threadId] += townSets[i*n+threadId];
}
void unionTownSet(char *current, char *townSets, int i, int n) {
unionTownSet_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(current, townSets, i, n);
}
// Find the total population in all of the town sets
__global__ void sizeTownSet_gpu(char *current, int *pops, int n, int *sizes) {
int threadId = blockIdx.x*blockDim.x + threadIdx.x;
if (current[threadId] == 1)
sizes[threadId] = pops[threadId];
else
sizes[threadId] = 0;
}
__global__ void totals_gpu(int *output, int *input) {
__shared__ int temp[BLOCKSIZE];
int threadId = blockIdx.x*blockDim.x + threadIdx.x;
temp[threadIdx.x] = input[threadId];
__syncthreads();
for (int s=blockDim.x/2; s>0; s>>=1) {
if (threadIdx.x < s)
temp[threadIdx.x] += temp[threadIdx.x+s];
__syncthreads();
}
if (threadIdx.x == 0)
output[blockIdx.x] = temp[0];
}
int sizeTownSet(char *current, int *pops, int n) {
sizeTownSet_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(current, pops, n, sizes_gpu);
totals_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(subtotals_gpu, sizes_gpu); // Calculate subtotals
totals_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(total_gpu, subtotals_gpu); // Calculate subtotals
int result;
hipMemcpy(total_gpu, &result, sizeof(int), hipMemcpyDeviceToHost);
return result;
}
// Count number of towns in a set
__global__ void countTownSet_gpu(char *current, int n, int *sizes) {
int threadId = blockIdx.x*blockDim.x + threadIdx.x;
if (current[threadId] == 1)
sizes[threadId] = 1;
else
sizes[threadId] = 0;
}
int countTownSet(char *current, int n) {
countTownSet_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(current, n, sizes_gpu);
totals_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(subtotals_gpu, sizes_gpu); // Calculate subtotals
totals_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(total_gpu, subtotals_gpu); // Calculate subtotals
int result;
hipMemcpy(total_gpu, &result, sizeof(int), hipMemcpyDeviceToHost);
return result;
}
int main(int argc, char **argv) {
if (argc != 4) {
cout << "Usage: " << argv[0] << " mode size reps" << endl;
cout << " Mode is one of the following:" << endl;
cout << " a test full algorithm" << endl;
cout << " u test taking unions" << endl;
cout << " s test calculating sizes" << endl;
exit(0);
}
int size = atoi(argv[2]);
int reps = atoi(argv[3]);
char mode = argv[1][0];
// Initialize data
char townSets[size*size];
for (int i=0; i<size; i++) {
for (int j=0; j<size; j++) {
if (rand() < .1*RAND_MAX)
townSets[i*size+j] = 1;
else
townSets[i*size+j] = 0;
}
townSets[i*size+i] = 1;
}
int pops[size];
int totalPop = 0;
for (int i=0; i<size; i++) {
pops[i] = rand() % 256;
totalPop += pops[i];
}
// Perform the tests
int rounds, totalRounds;
Stopwatch timer;
// Copy the data to the GPU
char *townSets_gpu;
int *pops_gpu;
char *current_gpu; // Stores working townset
hipMalloc((void**) &townSets_gpu, size*size);
hipMemcpy(townSets_gpu, townSets, size*size, hipMemcpyHostToDevice);
hipMalloc((void**) &pops_gpu, size*sizeof(int));
hipMemcpy(pops_gpu, pops, size*sizeof(int), hipMemcpyHostToDevice);
hipMalloc((void**) ¤t_gpu, size);
hipMalloc((void**) &sizes_gpu, size);
hipMalloc((void**) &subtotals_gpu, size/BLOCKSIZE);
hipMalloc((void**) &total_gpu, 1);
// Do the simulation
switch (mode) {
case 'a':
totalRounds=0;
for (int r=0; r<reps; r++) {
createTownSet(current_gpu, size);
rounds = 0;
while (sizeTownSet(current_gpu, pops_gpu, size) <= totalPop/2) {
unionTownSet(current_gpu, townSets_gpu, rand()%size, size);
rounds++;
}
totalRounds += rounds;
}
cout << "Average number of rounds = " << ((float) totalRounds/reps) << endl;
break;
case 'u':
createTownSet(current_gpu, size);
for (int r=0; r<reps; r++)
unionTownSet(current_gpu, townSets_gpu, rand()%size, size);
break;
case 's':
int s;
for (int r=0; r<reps; r++)
s = sizeTownSet(current_gpu, pops_gpu, size);
break;
}
cout << "Elapsed time " << timer.elapsed() << endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <sys/time.h>
using namespace std;
const int BLOCKSIZE = 32;
// Global variables to calculate sizes
int *sizes_gpu, *subtotals_gpu, *total_gpu; // For finding sums
// Stopwatch class
class Stopwatch {
private:
timeval initialTime;
public:
Stopwatch() {
reset();
}
void reset() {
gettimeofday(&initialTime, 0);
}
float elapsed() const {
timeval currentTime;
gettimeofday(¤tTime, 0);
return (float) (currentTime.tv_sec - initialTime.tv_sec) + ((float) (currentTime.tv_usec - initialTime.tv_usec))/1000000;
}
};
// Create an TownSet of size n with all false entries
void createTownSet(char *current, int n) {
char temp[n];
for (int i=0; i<n; i++)
temp[i] = 0;
hipMemcpy(¤t, &temp, n, hipMemcpyHostToDevice);
}
// Take a union of current_gpu and with specified townset and store it in current_gpu
__global__ void unionTownSet_gpu(char *current, char *townSets, int i, int n) {
int threadId = blockIdx.x*blockDim.x + threadIdx.x;
current[threadId] += townSets[i*n+threadId];
}
void unionTownSet(char *current, char *townSets, int i, int n) {
unionTownSet_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(current, townSets, i, n);
}
// Find the total population in all of the town sets
__global__ void sizeTownSet_gpu(char *current, int *pops, int n, int *sizes) {
int threadId = blockIdx.x*blockDim.x + threadIdx.x;
if (current[threadId] == 1)
sizes[threadId] = pops[threadId];
else
sizes[threadId] = 0;
}
__global__ void totals_gpu(int *output, int *input) {
__shared__ int temp[BLOCKSIZE];
int threadId = blockIdx.x*blockDim.x + threadIdx.x;
temp[threadIdx.x] = input[threadId];
__syncthreads();
for (int s=blockDim.x/2; s>0; s>>=1) {
if (threadIdx.x < s)
temp[threadIdx.x] += temp[threadIdx.x+s];
__syncthreads();
}
if (threadIdx.x == 0)
output[blockIdx.x] = temp[0];
}
int sizeTownSet(char *current, int *pops, int n) {
sizeTownSet_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(current, pops, n, sizes_gpu);
totals_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(subtotals_gpu, sizes_gpu); // Calculate subtotals
totals_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(total_gpu, subtotals_gpu); // Calculate subtotals
int result;
hipMemcpy(total_gpu, &result, sizeof(int), hipMemcpyDeviceToHost);
return result;
}
// Count number of towns in a set
__global__ void countTownSet_gpu(char *current, int n, int *sizes) {
int threadId = blockIdx.x*blockDim.x + threadIdx.x;
if (current[threadId] == 1)
sizes[threadId] = 1;
else
sizes[threadId] = 0;
}
int countTownSet(char *current, int n) {
countTownSet_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(current, n, sizes_gpu);
totals_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(subtotals_gpu, sizes_gpu); // Calculate subtotals
totals_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(total_gpu, subtotals_gpu); // Calculate subtotals
int result;
hipMemcpy(total_gpu, &result, sizeof(int), hipMemcpyDeviceToHost);
return result;
}
int main(int argc, char **argv) {
if (argc != 4) {
cout << "Usage: " << argv[0] << " mode size reps" << endl;
cout << " Mode is one of the following:" << endl;
cout << " a test full algorithm" << endl;
cout << " u test taking unions" << endl;
cout << " s test calculating sizes" << endl;
exit(0);
}
int size = atoi(argv[2]);
int reps = atoi(argv[3]);
char mode = argv[1][0];
// Initialize data
char townSets[size*size];
for (int i=0; i<size; i++) {
for (int j=0; j<size; j++) {
if (rand() < .1*RAND_MAX)
townSets[i*size+j] = 1;
else
townSets[i*size+j] = 0;
}
townSets[i*size+i] = 1;
}
int pops[size];
int totalPop = 0;
for (int i=0; i<size; i++) {
pops[i] = rand() % 256;
totalPop += pops[i];
}
// Perform the tests
int rounds, totalRounds;
Stopwatch timer;
// Copy the data to the GPU
char *townSets_gpu;
int *pops_gpu;
char *current_gpu; // Stores working townset
hipMalloc((void**) &townSets_gpu, size*size);
hipMemcpy(townSets_gpu, townSets, size*size, hipMemcpyHostToDevice);
hipMalloc((void**) &pops_gpu, size*sizeof(int));
hipMemcpy(pops_gpu, pops, size*sizeof(int), hipMemcpyHostToDevice);
hipMalloc((void**) ¤t_gpu, size);
hipMalloc((void**) &sizes_gpu, size);
hipMalloc((void**) &subtotals_gpu, size/BLOCKSIZE);
hipMalloc((void**) &total_gpu, 1);
// Do the simulation
switch (mode) {
case 'a':
totalRounds=0;
for (int r=0; r<reps; r++) {
createTownSet(current_gpu, size);
rounds = 0;
while (sizeTownSet(current_gpu, pops_gpu, size) <= totalPop/2) {
unionTownSet(current_gpu, townSets_gpu, rand()%size, size);
rounds++;
}
totalRounds += rounds;
}
cout << "Average number of rounds = " << ((float) totalRounds/reps) << endl;
break;
case 'u':
createTownSet(current_gpu, size);
for (int r=0; r<reps; r++)
unionTownSet(current_gpu, townSets_gpu, rand()%size, size);
break;
case 's':
int s;
for (int r=0; r<reps; r++)
s = sizeTownSet(current_gpu, pops_gpu, size);
break;
}
cout << "Elapsed time " << timer.elapsed() << endl;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16unionTownSet_gpuPcS_ii
.globl _Z16unionTownSet_gpuPcS_ii
.p2align 8
.type _Z16unionTownSet_gpuPcS_ii,@function
_Z16unionTownSet_gpuPcS_ii:
s_clause 0x2
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_mad_u64_u32 v[2:3], null, s5, s4, v[1:2]
v_ashrrev_i32_e32 v4, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v0, 31, v2
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v0, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v4, vcc_lo
global_load_u8 v2, v[2:3], off
global_load_u8 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u16 v2, v3, v2
global_store_b8 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16unionTownSet_gpuPcS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16unionTownSet_gpuPcS_ii, .Lfunc_end0-_Z16unionTownSet_gpuPcS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15sizeTownSet_gpuPcPiiS0_
.globl _Z15sizeTownSet_gpuPcPiiS0_
.p2align 8
.type _Z15sizeTownSet_gpuPcPiiS0_,@function
_Z15sizeTownSet_gpuPcPiiS0_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_add_co_u32 v3, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
global_load_u8 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 1, v0
v_mov_b32_e32 v0, 0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_2
s_load_b64 s[4:5], s[0:1], 0x8
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v0, v[3:4], off
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x18
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15sizeTownSet_gpuPcPiiS0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15sizeTownSet_gpuPcPiiS0_, .Lfunc_end1-_Z15sizeTownSet_gpuPcPiiS0_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10totals_gpuPiS_
.globl _Z10totals_gpuPiS_
.p2align 8
.type _Z10totals_gpuPiS_,@function
_Z10totals_gpuPiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x8
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_cmp_lt_u32 s3, 2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB2_2
.p2align 6
.LBB2_1:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB2_2:
buffer_gl0_inv
s_cbranch_scc1 .LBB2_5
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB2_1
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB2_1
.LBB2_5:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB2_7
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB2_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10totals_gpuPiS_
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z10totals_gpuPiS_, .Lfunc_end2-_Z10totals_gpuPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16countTownSet_gpuPciPi
.globl _Z16countTownSet_gpuPciPi
.p2align 8
.type _Z16countTownSet_gpuPciPi,@function
_Z16countTownSet_gpuPciPi:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_add_co_u32 v3, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
v_lshlrev_b64 v[0:1], 2, v[1:2]
global_load_u8 v3, v[3:4], off
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 1, v3
v_cndmask_b32_e64 v2, 0, 1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16countTownSet_gpuPciPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z16countTownSet_gpuPciPi, .Lfunc_end3-_Z16countTownSet_gpuPciPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16unionTownSet_gpuPcS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16unionTownSet_gpuPcS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15sizeTownSet_gpuPcPiiS0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15sizeTownSet_gpuPcPiiS0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10totals_gpuPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10totals_gpuPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16countTownSet_gpuPciPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16countTownSet_gpuPciPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <sys/time.h>
using namespace std;
const int BLOCKSIZE = 32;
// Global variables to calculate sizes
int *sizes_gpu, *subtotals_gpu, *total_gpu; // For finding sums
// Stopwatch class
class Stopwatch {
private:
timeval initialTime;
public:
Stopwatch() {
reset();
}
void reset() {
gettimeofday(&initialTime, 0);
}
float elapsed() const {
timeval currentTime;
gettimeofday(¤tTime, 0);
return (float) (currentTime.tv_sec - initialTime.tv_sec) + ((float) (currentTime.tv_usec - initialTime.tv_usec))/1000000;
}
};
// Create an TownSet of size n with all false entries
void createTownSet(char *current, int n) {
char temp[n];
for (int i=0; i<n; i++)
temp[i] = 0;
hipMemcpy(¤t, &temp, n, hipMemcpyHostToDevice);
}
// Take a union of current_gpu and with specified townset and store it in current_gpu
__global__ void unionTownSet_gpu(char *current, char *townSets, int i, int n) {
int threadId = blockIdx.x*blockDim.x + threadIdx.x;
current[threadId] += townSets[i*n+threadId];
}
void unionTownSet(char *current, char *townSets, int i, int n) {
unionTownSet_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(current, townSets, i, n);
}
// Find the total population in all of the town sets
__global__ void sizeTownSet_gpu(char *current, int *pops, int n, int *sizes) {
int threadId = blockIdx.x*blockDim.x + threadIdx.x;
if (current[threadId] == 1)
sizes[threadId] = pops[threadId];
else
sizes[threadId] = 0;
}
__global__ void totals_gpu(int *output, int *input) {
__shared__ int temp[BLOCKSIZE];
int threadId = blockIdx.x*blockDim.x + threadIdx.x;
temp[threadIdx.x] = input[threadId];
__syncthreads();
for (int s=blockDim.x/2; s>0; s>>=1) {
if (threadIdx.x < s)
temp[threadIdx.x] += temp[threadIdx.x+s];
__syncthreads();
}
if (threadIdx.x == 0)
output[blockIdx.x] = temp[0];
}
int sizeTownSet(char *current, int *pops, int n) {
sizeTownSet_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(current, pops, n, sizes_gpu);
totals_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(subtotals_gpu, sizes_gpu); // Calculate subtotals
totals_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(total_gpu, subtotals_gpu); // Calculate subtotals
int result;
hipMemcpy(total_gpu, &result, sizeof(int), hipMemcpyDeviceToHost);
return result;
}
// Count number of towns in a set
__global__ void countTownSet_gpu(char *current, int n, int *sizes) {
int threadId = blockIdx.x*blockDim.x + threadIdx.x;
if (current[threadId] == 1)
sizes[threadId] = 1;
else
sizes[threadId] = 0;
}
int countTownSet(char *current, int n) {
countTownSet_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(current, n, sizes_gpu);
totals_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(subtotals_gpu, sizes_gpu); // Calculate subtotals
totals_gpu<<<n/BLOCKSIZE, BLOCKSIZE>>>(total_gpu, subtotals_gpu); // Calculate subtotals
int result;
hipMemcpy(total_gpu, &result, sizeof(int), hipMemcpyDeviceToHost);
return result;
}
int main(int argc, char **argv) {
if (argc != 4) {
cout << "Usage: " << argv[0] << " mode size reps" << endl;
cout << " Mode is one of the following:" << endl;
cout << " a test full algorithm" << endl;
cout << " u test taking unions" << endl;
cout << " s test calculating sizes" << endl;
exit(0);
}
int size = atoi(argv[2]);
int reps = atoi(argv[3]);
char mode = argv[1][0];
// Initialize data
char townSets[size*size];
for (int i=0; i<size; i++) {
for (int j=0; j<size; j++) {
if (rand() < .1*RAND_MAX)
townSets[i*size+j] = 1;
else
townSets[i*size+j] = 0;
}
townSets[i*size+i] = 1;
}
int pops[size];
int totalPop = 0;
for (int i=0; i<size; i++) {
pops[i] = rand() % 256;
totalPop += pops[i];
}
// Perform the tests
int rounds, totalRounds;
Stopwatch timer;
// Copy the data to the GPU
char *townSets_gpu;
int *pops_gpu;
char *current_gpu; // Stores working townset
hipMalloc((void**) &townSets_gpu, size*size);
hipMemcpy(townSets_gpu, townSets, size*size, hipMemcpyHostToDevice);
hipMalloc((void**) &pops_gpu, size*sizeof(int));
hipMemcpy(pops_gpu, pops, size*sizeof(int), hipMemcpyHostToDevice);
hipMalloc((void**) ¤t_gpu, size);
hipMalloc((void**) &sizes_gpu, size);
hipMalloc((void**) &subtotals_gpu, size/BLOCKSIZE);
hipMalloc((void**) &total_gpu, 1);
// Do the simulation
switch (mode) {
case 'a':
totalRounds=0;
for (int r=0; r<reps; r++) {
createTownSet(current_gpu, size);
rounds = 0;
while (sizeTownSet(current_gpu, pops_gpu, size) <= totalPop/2) {
unionTownSet(current_gpu, townSets_gpu, rand()%size, size);
rounds++;
}
totalRounds += rounds;
}
cout << "Average number of rounds = " << ((float) totalRounds/reps) << endl;
break;
case 'u':
createTownSet(current_gpu, size);
for (int r=0; r<reps; r++)
unionTownSet(current_gpu, townSets_gpu, rand()%size, size);
break;
case 's':
int s;
for (int r=0; r<reps; r++)
s = sizeTownSet(current_gpu, pops_gpu, size);
break;
}
cout << "Elapsed time " << timer.elapsed() << endl;
} | .text
.file "TownSet_cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z13createTownSetPci # -- Begin function _Z13createTownSetPci
.p2align 4, 0x90
.type _Z13createTownSetPci,@function
_Z13createTownSetPci: # @_Z13createTownSetPci
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r14
pushq %rbx
subq $16, %rsp
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
movl %esi, %ebx
movq %rdi, -24(%rbp)
movl %esi, %edx
movq %rsp, %r14
leaq 15(%rdx), %rax
andq $-16, %rax
subq %rax, %r14
movq %r14, %rsp
testl %esi, %esi
jle .LBB0_2
# %bb.1: # %.lr.ph.preheader
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB0_2: # %._crit_edge
movslq %ebx, %rdx
leaq -24(%rbp), %rdi
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq -16(%rbp), %rsp
popq %rbx
popq %r14
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end0:
.size _Z13createTownSetPci, .Lfunc_end0-_Z13createTownSetPci
.cfi_endproc
# -- End function
.globl _Z31__device_stub__unionTownSet_gpuPcS_ii # -- Begin function _Z31__device_stub__unionTownSet_gpuPcS_ii
.p2align 4, 0x90
.type _Z31__device_stub__unionTownSet_gpuPcS_ii,@function
_Z31__device_stub__unionTownSet_gpuPcS_ii: # @_Z31__device_stub__unionTownSet_gpuPcS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16unionTownSet_gpuPcS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z31__device_stub__unionTownSet_gpuPcS_ii, .Lfunc_end1-_Z31__device_stub__unionTownSet_gpuPcS_ii
.cfi_endproc
# -- End function
.globl _Z12unionTownSetPcS_ii # -- Begin function _Z12unionTownSetPcS_ii
.p2align 4, 0x90
.type _Z12unionTownSetPcS_ii,@function
_Z12unionTownSetPcS_ii: # @_Z12unionTownSetPcS_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebx
movl %edx, %ebp
movq %rsi, %r14
movq %rdi, %r15
leal 31(%rbx), %edi
testl %ecx, %ecx
cmovnsl %ecx, %edi
sarl $5, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $32, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movl %ebp, 12(%rsp)
movl %ebx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16unionTownSet_gpuPcS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12unionTownSetPcS_ii, .Lfunc_end2-_Z12unionTownSetPcS_ii
.cfi_endproc
# -- End function
.globl _Z30__device_stub__sizeTownSet_gpuPcPiiS0_ # -- Begin function _Z30__device_stub__sizeTownSet_gpuPcPiiS0_
.p2align 4, 0x90
.type _Z30__device_stub__sizeTownSet_gpuPcPiiS0_,@function
_Z30__device_stub__sizeTownSet_gpuPcPiiS0_: # @_Z30__device_stub__sizeTownSet_gpuPcPiiS0_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15sizeTownSet_gpuPcPiiS0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z30__device_stub__sizeTownSet_gpuPcPiiS0_, .Lfunc_end3-_Z30__device_stub__sizeTownSet_gpuPcPiiS0_
.cfi_endproc
# -- End function
.globl _Z25__device_stub__totals_gpuPiS_ # -- Begin function _Z25__device_stub__totals_gpuPiS_
.p2align 4, 0x90
.type _Z25__device_stub__totals_gpuPiS_,@function
_Z25__device_stub__totals_gpuPiS_: # @_Z25__device_stub__totals_gpuPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10totals_gpuPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z25__device_stub__totals_gpuPiS_, .Lfunc_end4-_Z25__device_stub__totals_gpuPiS_
.cfi_endproc
# -- End function
.globl _Z11sizeTownSetPcPii # -- Begin function _Z11sizeTownSetPcPii
.p2align 4, 0x90
.type _Z11sizeTownSetPcPii,@function
_Z11sizeTownSetPcPii: # @_Z11sizeTownSetPcPii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edx, %r15d
movq %rsi, %r12
movq %rdi, %r13
movabsq $4294967328, %rbx # imm = 0x100000020
leal 31(%r15), %eax
testl %edx, %edx
cmovnsl %edx, %eax
sarl $5, %eax
leaq (%rax,%rbx), %r14
addq $-32, %r14
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq sizes_gpu(%rip), %rax
movq %r13, 64(%rsp)
movq %r12, 56(%rsp)
movl %r15d, 76(%rsp)
movq %rax, 16(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 76(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 8(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15sizeTownSet_gpuPcPiiS0_, %edi
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_4
# %bb.3:
movq subtotals_gpu(%rip), %rax
movq sizes_gpu(%rip), %rcx
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10totals_gpuPiS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_4:
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_6
# %bb.5:
movq total_gpu(%rip), %rax
movq subtotals_gpu(%rip), %rcx
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10totals_gpuPiS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_6:
movq total_gpu(%rip), %rdi
leaq 80(%rsp), %rsi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 80(%rsp), %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z11sizeTownSetPcPii, .Lfunc_end5-_Z11sizeTownSetPcPii
.cfi_endproc
# -- End function
.globl _Z31__device_stub__countTownSet_gpuPciPi # -- Begin function _Z31__device_stub__countTownSet_gpuPciPi
.p2align 4, 0x90
.type _Z31__device_stub__countTownSet_gpuPciPi,@function
_Z31__device_stub__countTownSet_gpuPciPi: # @_Z31__device_stub__countTownSet_gpuPciPi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16countTownSet_gpuPciPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end6:
.size _Z31__device_stub__countTownSet_gpuPciPi, .Lfunc_end6-_Z31__device_stub__countTownSet_gpuPciPi
.cfi_endproc
# -- End function
.globl _Z12countTownSetPci # -- Begin function _Z12countTownSetPci
.p2align 4, 0x90
.type _Z12countTownSetPci,@function
_Z12countTownSetPci: # @_Z12countTownSetPci
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %r15d
movq %rdi, %r12
movabsq $4294967328, %rbx # imm = 0x100000020
leal 31(%r15), %eax
testl %esi, %esi
cmovnsl %esi, %eax
sarl $5, %eax
leaq (%rax,%rbx), %r14
addq $-32, %r14
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_2
# %bb.1:
movq sizes_gpu(%rip), %rax
movq %r12, 56(%rsp)
movl %r15d, 100(%rsp)
movq %rax, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 100(%rsp), %rax
movq %rax, 72(%rsp)
leaq 48(%rsp), %rax
movq %rax, 80(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16countTownSet_gpuPciPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_2:
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_4
# %bb.3:
movq subtotals_gpu(%rip), %rax
movq sizes_gpu(%rip), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10totals_gpuPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_4:
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_6
# %bb.5:
movq total_gpu(%rip), %rax
movq subtotals_gpu(%rip), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10totals_gpuPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_6:
movq total_gpu(%rip), %rdi
leaq 64(%rsp), %rsi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 64(%rsp), %eax
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z12countTownSetPci, .Lfunc_end7-_Z12countTownSetPci
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI8_0:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $120, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movq %rsi, %r15
cmpl $4, %edi
jne .LBB8_35
# %bb.1:
movq 16(%r15), %rdi
xorl %eax, %eax
movq %rax, -64(%rbp) # 8-byte Spill
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, -112(%rbp) # 8-byte Spill
movq 8(%r15), %rax
movzbl (%rax), %eax
movl %eax, -92(%rbp) # 4-byte Spill
movl %ebx, %eax
imull %eax, %eax
movq %rax, -104(%rbp) # 8-byte Spill
addq $15, %rax
andq $-16, %rax
movq %rsp, %rcx
subq %rax, %rcx
movq %rcx, %rsp
movq %rbx, -56(%rbp) # 8-byte Spill
testl %ebx, %ebx
movq %rcx, -72(%rbp) # 8-byte Spill
jle .LBB8_6
# %bb.2: # %.preheader82.lr.ph
movq -56(%rbp), %rax # 8-byte Reload
movq %rax, %rdx
incq %rdx
movq %rdx, -120(%rbp) # 8-byte Spill
movl %eax, %r15d
xorl %ebx, %ebx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB8_3: # %.preheader82
# =>This Loop Header: Depth=1
# Child Loop BB8_4 Depth 2
movl %ebx, %r13d
addq %rcx, %r13
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB8_4: # Parent Loop BB8_3 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cmpl $214748365, %eax # imm = 0xCCCCCCD
setl (%r13,%r14)
incq %r14
cmpq %r14, %r15
jne .LBB8_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB8_3 Depth=1
movq -120(%rbp), %rax # 8-byte Reload
# kill: def $eax killed $eax killed $rax
imull %r12d, %eax
cltq
movq -72(%rbp), %rcx # 8-byte Reload
movb $1, (%rcx,%rax)
incq %r12
addl -56(%rbp), %ebx # 4-byte Folded Reload
cmpq %r15, %r12
jne .LBB8_3
.LBB8_6: # %._crit_edge85
movq -56(%rbp), %rbx # 8-byte Reload
movl %ebx, %eax
movq %rsp, %r13
leaq 15(,%rax,4), %rax
andq $-16, %rax
subq %rax, %r13
movq %r13, %rsp
testl %ebx, %ebx
jle .LBB8_10
# %bb.7: # %.lr.ph89.preheader
movl %ebx, %ebx
xorl %r12d, %r12d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB8_8: # %.lr.ph89
# =>This Inner Loop Header: Depth=1
callq rand
# kill: def $eax killed $eax def $rax
leal 255(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-256, %ecx
subl %ecx, %eax
movl %eax, (%r13,%r12,4)
addl %eax, %r15d
incq %r12
cmpq %r12, %rbx
jne .LBB8_8
# %bb.9: # %._crit_edge90.loopexit
movl %r15d, %eax
shrl $31, %eax
addl %r15d, %eax
sarl %eax
movq %rax, -64(%rbp) # 8-byte Spill
movq -56(%rbp), %rbx # 8-byte Reload
.LBB8_10: # %._crit_edge90
leaq -136(%rbp), %rdi
xorl %esi, %esi
callq gettimeofday
leaq -88(%rbp), %rdi
movq -104(%rbp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
movq -88(%rbp), %rdi
movq -72(%rbp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movslq %ebx, %r15
leaq (,%r15,4), %r12
leaq -80(%rbp), %rdi
movq %r12, %rsi
callq hipMalloc
movq -80(%rbp), %rdi
movq %r13, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
leaq -48(%rbp), %rdi
movq %r15, %rsi
callq hipMalloc
movl $sizes_gpu, %edi
movq %r15, %rsi
callq hipMalloc
leal 31(%rbx), %eax
testl %ebx, %ebx
cmovnsl %ebx, %eax
sarl $5, %eax
movslq %eax, %rsi
movl $subtotals_gpu, %edi
callq hipMalloc
movl $total_gpu, %edi
movl $1, %esi
callq hipMalloc
movl -92(%rbp), %eax # 4-byte Reload
cmpl $97, %eax
movq -112(%rbp), %r14 # 8-byte Reload
je .LBB8_15
# %bb.11: # %._crit_edge90
cmpl $117, %eax
je .LBB8_28
# %bb.12: # %._crit_edge90
cmpl $115, %eax
jne .LBB8_30
# %bb.13: # %.preheader80
testl %r14d, %r14d
jle .LBB8_30
.p2align 4, 0x90
.LBB8_14: # %.lr.ph92
# =>This Inner Loop Header: Depth=1
movq -48(%rbp), %rdi
movq -80(%rbp), %rsi
movl %ebx, %edx
callq _Z11sizeTownSetPcPii
decl %r14d
jne .LBB8_14
jmp .LBB8_30
.LBB8_28:
movq -48(%rbp), %rdi
movl %ebx, %esi
callq _Z13createTownSetPci
testl %r14d, %r14d
jle .LBB8_30
.p2align 4, 0x90
.LBB8_29: # %.lr.ph95
# =>This Inner Loop Header: Depth=1
movq -48(%rbp), %r15
movq -88(%rbp), %r12
callq rand
cltd
idivl %ebx
movq %r15, %rdi
movq %r12, %rsi
movl %ebx, %ecx
callq _Z12unionTownSetPcS_ii
decl %r14d
jne .LBB8_29
jmp .LBB8_30
.LBB8_15: # %.preheader
testl %r14d, %r14d
jle .LBB8_16
# %bb.23: # %.lr.ph104.preheader
xorl %eax, %eax
xorl %ecx, %ecx
movq -64(%rbp), %r15 # 8-byte Reload
jmp .LBB8_24
.p2align 4, 0x90
.LBB8_27: # %._crit_edge100
# in Loop: Header=BB8_24 Depth=1
movl -72(%rbp), %ecx # 4-byte Reload
addl %ebx, %ecx
movl -56(%rbp), %eax # 4-byte Reload
incl %eax
cmpl %r14d, %eax
movq %r13, %rbx
je .LBB8_17
.LBB8_24: # %.lr.ph104
# =>This Loop Header: Depth=1
# Child Loop BB8_26 Depth 2
movl %ecx, -72(%rbp) # 4-byte Spill
movl %eax, -56(%rbp) # 4-byte Spill
movq -48(%rbp), %rdi
movl %ebx, %esi
callq _Z13createTownSetPci
movq -48(%rbp), %rdi
movq -80(%rbp), %rsi
movl %ebx, %edx
callq _Z11sizeTownSetPcPii
movq %rbx, %r13
movl $0, %ebx
cmpl %r15d, %eax
jg .LBB8_27
# %bb.25: # %.lr.ph99.preheader
# in Loop: Header=BB8_24 Depth=1
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB8_26: # %.lr.ph99
# Parent Loop BB8_24 Depth=1
# => This Inner Loop Header: Depth=2
movq -48(%rbp), %r15
movq -88(%rbp), %r12
callq rand
cltd
idivl %r13d
movq %r15, %rdi
movq %r12, %rsi
movq -64(%rbp), %r15 # 8-byte Reload
movl %r13d, %ecx
callq _Z12unionTownSetPcS_ii
incl %ebx
movq -48(%rbp), %rdi
movq -80(%rbp), %rsi
movl %r13d, %edx
callq _Z11sizeTownSetPcPii
cmpl %r15d, %eax
jle .LBB8_26
jmp .LBB8_27
.LBB8_17: # %._crit_edge105.loopexit
cvtsi2ss %ecx, %xmm0
jmp .LBB8_18
.LBB8_16:
xorps %xmm0, %xmm0
.LBB8_18: # %._crit_edge105
movss %xmm0, -64(%rbp) # 4-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm0, %xmm0
cvtsi2ss %r14d, %xmm0
movss -64(%rbp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB8_36
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB8_21
# %bb.20:
movzbl 67(%rbx), %ecx
jmp .LBB8_22
.LBB8_21:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB8_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB8_30: # %.loopexit
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq -152(%rbp), %rdi
xorl %esi, %esi
callq gettimeofday
movq -152(%rbp), %rax
subq -136(%rbp), %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
movq -144(%rbp), %rax
subq -128(%rbp), %rax
xorps %xmm1, %xmm1
cvtsi2ss %rax, %xmm1
divss .LCPI8_0(%rip), %xmm1
addss %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB8_36
# %bb.31: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i76
cmpb $0, 56(%rbx)
je .LBB8_33
# %bb.32:
movzbl 67(%rbx), %ecx
jmp .LBB8_34
.LBB8_33:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB8_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit79
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB8_36:
.cfi_def_cfa %rbp, 16
callq _ZSt16__throw_bad_castv
.LBB8_35:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq (%r15), %rsi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
xorl %edi, %edi
callq exit
.Lfunc_end8:
.size main, .Lfunc_end8-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16unionTownSet_gpuPcS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15sizeTownSet_gpuPcPiiS0_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10totals_gpuPiS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16countTownSet_gpuPciPi, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type sizes_gpu,@object # @sizes_gpu
.bss
.globl sizes_gpu
.p2align 3, 0x0
sizes_gpu:
.quad 0
.size sizes_gpu, 8
.type subtotals_gpu,@object # @subtotals_gpu
.globl subtotals_gpu
.p2align 3, 0x0
subtotals_gpu:
.quad 0
.size subtotals_gpu, 8
.type total_gpu,@object # @total_gpu
.globl total_gpu
.p2align 3, 0x0
total_gpu:
.quad 0
.size total_gpu, 8
.type _Z16unionTownSet_gpuPcS_ii,@object # @_Z16unionTownSet_gpuPcS_ii
.section .rodata,"a",@progbits
.globl _Z16unionTownSet_gpuPcS_ii
.p2align 3, 0x0
_Z16unionTownSet_gpuPcS_ii:
.quad _Z31__device_stub__unionTownSet_gpuPcS_ii
.size _Z16unionTownSet_gpuPcS_ii, 8
.type _Z15sizeTownSet_gpuPcPiiS0_,@object # @_Z15sizeTownSet_gpuPcPiiS0_
.globl _Z15sizeTownSet_gpuPcPiiS0_
.p2align 3, 0x0
_Z15sizeTownSet_gpuPcPiiS0_:
.quad _Z30__device_stub__sizeTownSet_gpuPcPiiS0_
.size _Z15sizeTownSet_gpuPcPiiS0_, 8
.type _Z10totals_gpuPiS_,@object # @_Z10totals_gpuPiS_
.globl _Z10totals_gpuPiS_
.p2align 3, 0x0
_Z10totals_gpuPiS_:
.quad _Z25__device_stub__totals_gpuPiS_
.size _Z10totals_gpuPiS_, 8
.type _Z16countTownSet_gpuPciPi,@object # @_Z16countTownSet_gpuPciPi
.globl _Z16countTownSet_gpuPciPi
.p2align 3, 0x0
_Z16countTownSet_gpuPciPi:
.quad _Z31__device_stub__countTownSet_gpuPciPi
.size _Z16countTownSet_gpuPciPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage: "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " mode size reps"
.size .L.str.1, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " Mode is one of the following:"
.size .L.str.2, 32
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " a test full algorithm"
.size .L.str.3, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " u test taking unions"
.size .L.str.4, 26
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " s test calculating sizes"
.size .L.str.5, 30
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Average number of rounds = "
.size .L.str.6, 28
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Elapsed time "
.size .L.str.7, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16unionTownSet_gpuPcS_ii"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15sizeTownSet_gpuPcPiiS0_"
.size .L__unnamed_2, 28
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z10totals_gpuPiS_"
.size .L__unnamed_3, 19
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z16countTownSet_gpuPciPi"
.size .L__unnamed_4, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__unionTownSet_gpuPcS_ii
.addrsig_sym _Z30__device_stub__sizeTownSet_gpuPcPiiS0_
.addrsig_sym _Z25__device_stub__totals_gpuPiS_
.addrsig_sym _Z31__device_stub__countTownSet_gpuPciPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym sizes_gpu
.addrsig_sym subtotals_gpu
.addrsig_sym total_gpu
.addrsig_sym _Z16unionTownSet_gpuPcS_ii
.addrsig_sym _Z15sizeTownSet_gpuPcPiiS0_
.addrsig_sym _Z10totals_gpuPiS_
.addrsig_sym _Z16countTownSet_gpuPciPi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16countTownSet_gpuPciPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0050*/ IADD3 R4, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x000fc80007f1e0ff */
/*0060*/ LEA.HI.X.SX32 R5, R2, c[0x0][0x164], 0x1, P0 ; /* 0x0000590002057a11 */
/* 0x000fca00000f0eff */
/*0070*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1100 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fe200078e0203 */
/*00a0*/ ISETP.NE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x004fc80003f05270 */
/*00b0*/ SEL R7, RZ, 0x1, P0 ; /* 0x00000001ff077807 */
/* 0x000fca0000000000 */
/*00c0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10totals_gpuPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0060*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0203 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0090*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00a0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00b0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00c0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041e80000004800 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00e0*/ @!P1 BRA 0x1b0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x001fe200078e00ff */
/*0100*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fc80008000f00 */
/*0110*/ ISETP.GE.U32.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26070 */
/*0120*/ @!P1 IMAD R2, R3, 0x4, R0 ; /* 0x0000000403029824 */
/* 0x000fe200078e0200 */
/*0130*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */
/* 0x000fe20000004800 */
/*0140*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0150*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0160*/ @!P1 IADD3 R4, R4, R5, RZ ; /* 0x0000000504049210 */
/* 0x001fca0007ffe0ff */
/*0170*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */
/* 0x0001e80000004800 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*01a0*/ @P1 BRA 0x110 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*01c0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*01d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01e0*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fca00078e0003 */
/*01f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15sizeTownSet_gpuPcPiiS0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0050*/ SHF.R.S32.HI R7, RZ, 0x1f, R0 ; /* 0x0000001fff077819 */
/* 0x000fe40000011400 */
/*0060*/ IADD3 R4, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000047a10 */
/* 0x000fc80007f1e0ff */
/*0070*/ IADD3.X R5, R7, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590007057a10 */
/* 0x000fca00007fe4ff */
/*0080*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1100 */
/*0090*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*00a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fe200078e0203 */
/*00b0*/ ISETP.NE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x004fda0003f05270 */
/*00c0*/ @P0 STG.E [R2.64], RZ ; /* 0x000000ff02000986 */
/* 0x0001e2000c101904 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ LEA R4, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000047a11 */
/* 0x000fc800078010ff */
/*00f0*/ LEA.HI.X R5, R0, c[0x0][0x16c], R7, 0x2, P0 ; /* 0x00005b0000057a11 */
/* 0x000fcc00000f1407 */
/*0100*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0110*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z16unionTownSet_gpuPcS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R5, c[0x0][0x174] ; /* 0x00005d0000057a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD R5, R5, c[0x0][0x170], R0 ; /* 0x00005c0005057a24 */
/* 0x000fe200078e0200 */
/*0070*/ IADD3 R2, P1, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f3e0ff */
/*0080*/ IADD3 R4, P0, R5.reuse, c[0x0][0x168], RZ ; /* 0x00005a0005047a10 */
/* 0x040fe40007f1e0ff */
/*0090*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P1 ; /* 0x0000590000037a11 */
/* 0x000fe400008f0eff */
/*00a0*/ LEA.HI.X.SX32 R5, R5, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0005057a11 */
/* 0x000fc600000f0eff */
/*00b0*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea8000c1e1100 */
/*00c0*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1100 */
/*00d0*/ IMAD.IADD R7, R4, 0x1, R7 ; /* 0x0000000104077824 */
/* 0x004fca00078e0207 */
/*00e0*/ STG.E.U8 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101104 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16unionTownSet_gpuPcS_ii
.globl _Z16unionTownSet_gpuPcS_ii
.p2align 8
.type _Z16unionTownSet_gpuPcS_ii,@function
_Z16unionTownSet_gpuPcS_ii:
s_clause 0x2
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_mad_u64_u32 v[2:3], null, s5, s4, v[1:2]
v_ashrrev_i32_e32 v4, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v0, 31, v2
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v0, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v4, vcc_lo
global_load_u8 v2, v[2:3], off
global_load_u8 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u16 v2, v3, v2
global_store_b8 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16unionTownSet_gpuPcS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16unionTownSet_gpuPcS_ii, .Lfunc_end0-_Z16unionTownSet_gpuPcS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15sizeTownSet_gpuPcPiiS0_
.globl _Z15sizeTownSet_gpuPcPiiS0_
.p2align 8
.type _Z15sizeTownSet_gpuPcPiiS0_,@function
_Z15sizeTownSet_gpuPcPiiS0_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_add_co_u32 v3, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
global_load_u8 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 1, v0
v_mov_b32_e32 v0, 0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_2
s_load_b64 s[4:5], s[0:1], 0x8
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v0, v[3:4], off
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x18
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15sizeTownSet_gpuPcPiiS0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15sizeTownSet_gpuPcPiiS0_, .Lfunc_end1-_Z15sizeTownSet_gpuPcPiiS0_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10totals_gpuPiS_
.globl _Z10totals_gpuPiS_
.p2align 8
.type _Z10totals_gpuPiS_,@function
_Z10totals_gpuPiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x8
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_cmp_lt_u32 s3, 2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB2_2
.p2align 6
.LBB2_1:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB2_2:
buffer_gl0_inv
s_cbranch_scc1 .LBB2_5
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB2_1
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB2_1
.LBB2_5:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB2_7
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB2_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10totals_gpuPiS_
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z10totals_gpuPiS_, .Lfunc_end2-_Z10totals_gpuPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16countTownSet_gpuPciPi
.globl _Z16countTownSet_gpuPciPi
.p2align 8
.type _Z16countTownSet_gpuPciPi,@function
_Z16countTownSet_gpuPciPi:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_add_co_u32 v3, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
v_lshlrev_b64 v[0:1], 2, v[1:2]
global_load_u8 v3, v[3:4], off
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 1, v3
v_cndmask_b32_e64 v2, 0, 1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16countTownSet_gpuPciPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z16countTownSet_gpuPciPi, .Lfunc_end3-_Z16countTownSet_gpuPciPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16unionTownSet_gpuPcS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16unionTownSet_gpuPcS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15sizeTownSet_gpuPcPiiS0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15sizeTownSet_gpuPcPiiS0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10totals_gpuPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10totals_gpuPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16countTownSet_gpuPciPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16countTownSet_gpuPciPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void convolution_kernel(unsigned char *input_img, unsigned char *output_img, int height, int width)
{
__shared__ unsigned char input_shared[W][W]; //Shared Memory required for a tile and its halo elements(3 channels)
int chan;
for(chan=0;chan<3;chan++) //3 Channel Image
{
int tx = threadIdx.x;
int ty = threadIdx.y;
int output_row = blockIdx.x*TILE_WIDTH + tx;
int output_col = blockIdx.y*TILE_WIDTH + ty;
int input_row = output_row - MASK_WIDTH/2;
int input_col = output_col - MASK_WIDTH/2;
if((input_row >= 0) && (input_row < height) && (input_col >= 0) && (input_col < width))
{
input_shared[tx][ty] = input_img[(input_row*width + input_col)*3 + chan];
}
else
{
if(input_row<0 && input_col<0)
{
input_shared[tx][ty] = input_img[chan];
}
else if(input_row<0 && input_col<width)
{
input_shared[tx][ty] = input_img[3*input_col + chan];
}
else if(input_row<0)
{
input_shared[tx][ty] = input_img[3*(width-1) + chan];
}
else if(input_row<height && input_col<0)
{
input_shared[tx][ty] = input_img[input_row*width*3 + chan];
}
else if(input_row<height && input_col>width)
{
input_shared[tx][ty] = input_img[(input_row*width +width-1)*3 + chan];
}
else if(input_row>height && input_col<0)
{
input_shared[tx][ty] = input_img[width*(height-1)*3 + chan];
}
else if(input_row>height && input_col<width)
{
input_shared[tx][ty] = input_img[(width*(height-1)+input_col)*3 + chan];
}
else
{
input_shared[tx][ty] = input_img[(width*(height-1) + (width-1))*3 + chan];
}
}
__syncthreads();
int i;
if(tx<TILE_WIDTH && ty<TILE_WIDTH)
{
int j;
int freq[256];
for(i=0;i<256;i++)freq[i]=0;
for(i=0;i<MASK_WIDTH;i++)
{
for(j=0;j<MASK_WIDTH;j++)
{
freq[input_shared[tx+i][ty+j]]++;
}
}
j=0;
for(i=0;i<256;i++)
{
j=j+freq[i];
if(j>((MASK_WIDTH*MASK_WIDTH)/2))break;
}
}
if(output_row<height && output_col<width)
{
output_img[(output_row*width + output_col)*3 + chan] = i;
}
__syncthreads();
}
} | .file "tmpxft_0011c8e6_00000000-6_convolution_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z18convolution_kernelPhS_iiPhS_ii
.type _Z42__device_stub__Z18convolution_kernelPhS_iiPhS_ii, @function
_Z42__device_stub__Z18convolution_kernelPhS_iiPhS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18convolution_kernelPhS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z18convolution_kernelPhS_iiPhS_ii, .-_Z42__device_stub__Z18convolution_kernelPhS_iiPhS_ii
.globl _Z18convolution_kernelPhS_ii
.type _Z18convolution_kernelPhS_ii, @function
_Z18convolution_kernelPhS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18convolution_kernelPhS_iiPhS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18convolution_kernelPhS_ii, .-_Z18convolution_kernelPhS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18convolution_kernelPhS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18convolution_kernelPhS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void convolution_kernel(unsigned char *input_img, unsigned char *output_img, int height, int width)
{
__shared__ unsigned char input_shared[W][W]; //Shared Memory required for a tile and its halo elements(3 channels)
int chan;
for(chan=0;chan<3;chan++) //3 Channel Image
{
int tx = threadIdx.x;
int ty = threadIdx.y;
int output_row = blockIdx.x*TILE_WIDTH + tx;
int output_col = blockIdx.y*TILE_WIDTH + ty;
int input_row = output_row - MASK_WIDTH/2;
int input_col = output_col - MASK_WIDTH/2;
if((input_row >= 0) && (input_row < height) && (input_col >= 0) && (input_col < width))
{
input_shared[tx][ty] = input_img[(input_row*width + input_col)*3 + chan];
}
else
{
if(input_row<0 && input_col<0)
{
input_shared[tx][ty] = input_img[chan];
}
else if(input_row<0 && input_col<width)
{
input_shared[tx][ty] = input_img[3*input_col + chan];
}
else if(input_row<0)
{
input_shared[tx][ty] = input_img[3*(width-1) + chan];
}
else if(input_row<height && input_col<0)
{
input_shared[tx][ty] = input_img[input_row*width*3 + chan];
}
else if(input_row<height && input_col>width)
{
input_shared[tx][ty] = input_img[(input_row*width +width-1)*3 + chan];
}
else if(input_row>height && input_col<0)
{
input_shared[tx][ty] = input_img[width*(height-1)*3 + chan];
}
else if(input_row>height && input_col<width)
{
input_shared[tx][ty] = input_img[(width*(height-1)+input_col)*3 + chan];
}
else
{
input_shared[tx][ty] = input_img[(width*(height-1) + (width-1))*3 + chan];
}
}
__syncthreads();
int i;
if(tx<TILE_WIDTH && ty<TILE_WIDTH)
{
int j;
int freq[256];
for(i=0;i<256;i++)freq[i]=0;
for(i=0;i<MASK_WIDTH;i++)
{
for(j=0;j<MASK_WIDTH;j++)
{
freq[input_shared[tx+i][ty+j]]++;
}
}
j=0;
for(i=0;i<256;i++)
{
j=j+freq[i];
if(j>((MASK_WIDTH*MASK_WIDTH)/2))break;
}
}
if(output_row<height && output_col<width)
{
output_img[(output_row*width + output_col)*3 + chan] = i;
}
__syncthreads();
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convolution_kernel(unsigned char *input_img, unsigned char *output_img, int height, int width)
{
__shared__ unsigned char input_shared[W][W]; //Shared Memory required for a tile and its halo elements(3 channels)
int chan;
for(chan=0;chan<3;chan++) //3 Channel Image
{
int tx = threadIdx.x;
int ty = threadIdx.y;
int output_row = blockIdx.x*TILE_WIDTH + tx;
int output_col = blockIdx.y*TILE_WIDTH + ty;
int input_row = output_row - MASK_WIDTH/2;
int input_col = output_col - MASK_WIDTH/2;
if((input_row >= 0) && (input_row < height) && (input_col >= 0) && (input_col < width))
{
input_shared[tx][ty] = input_img[(input_row*width + input_col)*3 + chan];
}
else
{
if(input_row<0 && input_col<0)
{
input_shared[tx][ty] = input_img[chan];
}
else if(input_row<0 && input_col<width)
{
input_shared[tx][ty] = input_img[3*input_col + chan];
}
else if(input_row<0)
{
input_shared[tx][ty] = input_img[3*(width-1) + chan];
}
else if(input_row<height && input_col<0)
{
input_shared[tx][ty] = input_img[input_row*width*3 + chan];
}
else if(input_row<height && input_col>width)
{
input_shared[tx][ty] = input_img[(input_row*width +width-1)*3 + chan];
}
else if(input_row>height && input_col<0)
{
input_shared[tx][ty] = input_img[width*(height-1)*3 + chan];
}
else if(input_row>height && input_col<width)
{
input_shared[tx][ty] = input_img[(width*(height-1)+input_col)*3 + chan];
}
else
{
input_shared[tx][ty] = input_img[(width*(height-1) + (width-1))*3 + chan];
}
}
__syncthreads();
int i;
if(tx<TILE_WIDTH && ty<TILE_WIDTH)
{
int j;
int freq[256];
for(i=0;i<256;i++)freq[i]=0;
for(i=0;i<MASK_WIDTH;i++)
{
for(j=0;j<MASK_WIDTH;j++)
{
freq[input_shared[tx+i][ty+j]]++;
}
}
j=0;
for(i=0;i<256;i++)
{
j=j+freq[i];
if(j>((MASK_WIDTH*MASK_WIDTH)/2))break;
}
}
if(output_row<height && output_col<width)
{
output_img[(output_row*width + output_col)*3 + chan] = i;
}
__syncthreads();
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convolution_kernel(unsigned char *input_img, unsigned char *output_img, int height, int width)
{
__shared__ unsigned char input_shared[W][W]; //Shared Memory required for a tile and its halo elements(3 channels)
int chan;
for(chan=0;chan<3;chan++) //3 Channel Image
{
int tx = threadIdx.x;
int ty = threadIdx.y;
int output_row = blockIdx.x*TILE_WIDTH + tx;
int output_col = blockIdx.y*TILE_WIDTH + ty;
int input_row = output_row - MASK_WIDTH/2;
int input_col = output_col - MASK_WIDTH/2;
if((input_row >= 0) && (input_row < height) && (input_col >= 0) && (input_col < width))
{
input_shared[tx][ty] = input_img[(input_row*width + input_col)*3 + chan];
}
else
{
if(input_row<0 && input_col<0)
{
input_shared[tx][ty] = input_img[chan];
}
else if(input_row<0 && input_col<width)
{
input_shared[tx][ty] = input_img[3*input_col + chan];
}
else if(input_row<0)
{
input_shared[tx][ty] = input_img[3*(width-1) + chan];
}
else if(input_row<height && input_col<0)
{
input_shared[tx][ty] = input_img[input_row*width*3 + chan];
}
else if(input_row<height && input_col>width)
{
input_shared[tx][ty] = input_img[(input_row*width +width-1)*3 + chan];
}
else if(input_row>height && input_col<0)
{
input_shared[tx][ty] = input_img[width*(height-1)*3 + chan];
}
else if(input_row>height && input_col<width)
{
input_shared[tx][ty] = input_img[(width*(height-1)+input_col)*3 + chan];
}
else
{
input_shared[tx][ty] = input_img[(width*(height-1) + (width-1))*3 + chan];
}
}
__syncthreads();
int i;
if(tx<TILE_WIDTH && ty<TILE_WIDTH)
{
int j;
int freq[256];
for(i=0;i<256;i++)freq[i]=0;
for(i=0;i<MASK_WIDTH;i++)
{
for(j=0;j<MASK_WIDTH;j++)
{
freq[input_shared[tx+i][ty+j]]++;
}
}
j=0;
for(i=0;i<256;i++)
{
j=j+freq[i];
if(j>((MASK_WIDTH*MASK_WIDTH)/2))break;
}
}
if(output_row<height && output_col<width)
{
output_img[(output_row*width + output_col)*3 + chan] = i;
}
__syncthreads();
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18convolution_kernelPhS_ii
.globl _Z18convolution_kernelPhS_ii
.p2align 8
.type _Z18convolution_kernelPhS_ii,@function
_Z18convolution_kernelPhS_ii:
s_clause 0x1
s_load_b64 s[20:21], s[0:1], 0x10
s_load_b128 s[16:19], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v8, v0, 10, 10
s_mov_b32 s11, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v0, s14, 3, v2
v_lshl_add_u32 v1, s15, 3, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s1, 1, v0
v_cmp_gt_i32_e64 s2, 1, v1
v_add_nc_u32_e32 v4, -1, v0
v_add_nc_u32_e32 v5, -1, v1
v_cmp_lt_i32_e32 vcc_lo, 0, v0
v_cmp_lt_i32_e64 s3, 0, v1
s_and_b32 s8, s1, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s12, s8, -1
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v7, v0, s21
v_cmp_gt_i32_e64 s4, s20, v0
v_cmp_gt_i32_e64 s5, s21, v1
v_cmp_lt_i32_e64 s6, s20, v0
v_cmp_lt_i32_e64 s7, s21, v1
v_mul_lo_u32 v6, v4, s21
v_cmp_ge_i32_e64 s8, s21, v5
s_and_b32 s4, s4, s5
v_add_nc_u32_e32 v9, v7, v1
s_or_b32 s5, s6, s7
s_or_b32 s10, s7, vcc_lo
v_mad_u64_u32 v[0:1], null, v7, 3, -3
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v7, v9, 1, v9
v_mov_b32_e32 v9, 0
v_or_b32_e32 v3, v2, v8
s_or_b32 s13, s5, s2
s_xor_b32 s2, s10, -1
s_add_i32 s10, s20, -1
s_or_b32 s5, s3, s6
s_or_b32 s6, s6, s8
s_mul_i32 s8, s10, s21
v_cmp_gt_u32_e64 s0, 8, v3
v_lshl_add_u32 v3, v5, 1, v5
v_cmp_ge_i32_e64 s9, s20, v4
v_add_nc_u32_e32 v4, v6, v5
v_add_nc_u32_e32 v5, s8, v5
s_add_i32 s8, s21, s8
v_lshl_add_u32 v6, v6, 1, v6
v_mad_u32_u24 v8, v2, 10, v8
v_lshl_add_u32 v4, v4, 1, v4
v_lshl_add_u32 v5, v5, 1, v5
s_or_b32 s7, s7, s9
s_mul_i32 s8, s8, 3
s_mul_i32 s14, s21, 3
s_or_b32 s1, s1, s13
s_or_b32 s3, s3, s9
s_xor_b32 s7, s7, -1
s_add_i32 s8, s8, -3
s_mul_i32 s9, s14, s10
s_add_i32 s13, s14, -3
s_xor_b32 s14, s1, -1
s_mov_b32 s10, s11
s_branch .LBB0_2
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s15
s_add_i32 s10, s10, 1
s_waitcnt_vscnt null, 0x0
s_cmp_lg_u32 s10, 3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_48
.LBB0_2:
s_and_saveexec_b32 s1, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s1, exec_lo, s1
v_add_nc_u32_e32 v1, s10, v4
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
s_and_not1_saveexec_b32 s1, s1
s_cbranch_execz .LBB0_34
s_and_saveexec_b32 s15, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s15, exec_lo, s15
s_cbranch_execz .LBB0_31
s_and_saveexec_b32 s20, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s20, exec_lo, s20
v_add_nc_u32_e32 v1, s10, v3
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
s_and_not1_saveexec_b32 s20, s20
s_cbranch_execz .LBB0_30
s_and_saveexec_b32 s21, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s21, exec_lo, s21
s_cbranch_execz .LBB0_27
s_and_saveexec_b32 s22, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s22, exec_lo, s22
s_cbranch_execz .LBB0_24
s_and_saveexec_b32 s23, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s23, exec_lo, s23
s_cbranch_execz .LBB0_21
s_and_saveexec_b32 s24, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s24, exec_lo, s24
s_cbranch_execz .LBB0_18
s_and_saveexec_b32 s25, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s25, exec_lo, s25
v_add_nc_u32_e32 v1, s10, v5
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
s_and_not1_saveexec_b32 s25, s25
s_add_i32 s26, s10, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s27, s26, 31
v_dual_mov_b32 v1, s26 :: v_dual_mov_b32 v2, s27
s_or_b32 exec_lo, exec_lo, s25
.LBB0_18:
s_and_not1_saveexec_b32 s24, s24
s_add_i32 s26, s10, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s27, s26, 31
v_dual_mov_b32 v1, s26 :: v_dual_mov_b32 v2, s27
s_or_b32 exec_lo, exec_lo, s24
.LBB0_21:
s_and_not1_saveexec_b32 s23, s23
v_add_nc_u32_e32 v1, s10, v0
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
s_or_b32 exec_lo, exec_lo, s23
.LBB0_24:
s_and_not1_saveexec_b32 s22, s22
v_add_nc_u32_e32 v1, s10, v6
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
s_or_b32 exec_lo, exec_lo, s22
.LBB0_27:
s_and_not1_saveexec_b32 s21, s21
s_add_i32 s22, s13, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s23, s22, 31
v_dual_mov_b32 v1, s22 :: v_dual_mov_b32 v2, s23
s_or_b32 exec_lo, exec_lo, s21
.LBB0_30:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s20
.LBB0_31:
s_and_not1_saveexec_b32 s15, s15
v_dual_mov_b32 v1, s10 :: v_dual_mov_b32 v2, s11
s_or_b32 exec_lo, exec_lo, s15
.LBB0_34:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s1
v_add_co_u32 v1, s1, s16, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, s1, s17, v2, s1
global_load_u8 v1, v[1:2], off
s_waitcnt vmcnt(0)
ds_store_b8 v8, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s15, s0
s_cbranch_execz .LBB0_46
s_mov_b32 s1, 0
.LBB0_36:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s20, s1, 16
s_add_i32 s1, s1, 4
scratch_store_b32 off, v9, s20
s_cmpk_lg_i32 s1, 0x400
s_cbranch_scc1 .LBB0_36
v_mov_b32_e32 v1, v8
s_mov_b32 s1, 0
.p2align 6
.LBB0_38:
s_mov_b32 s20, 0
.LBB0_39:
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v2, s20, v1
s_add_i32 s20, s20, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s20, 3
ds_load_u8 v2, v2
s_waitcnt lgkmcnt(0)
v_lshlrev_b32_e32 v2, 2, v2
scratch_load_b32 v10, v2, off offset:16
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v10, 1, v10
scratch_store_b32 v2, v10, off offset:16
s_cbranch_scc1 .LBB0_39
v_add_nc_u32_e32 v1, 10, v1
s_add_i32 s1, s1, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s1, 3
s_cbranch_scc1 .LBB0_38
v_dual_mov_b32 v1, 16 :: v_dual_mov_b32 v2, 0
s_mov_b32 s20, 0
s_mov_b32 s21, 0
s_branch .LBB0_43
.p2align 6
.LBB0_42:
s_or_b32 exec_lo, exec_lo, s23
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, exec_lo, s22
s_or_b32 s20, s1, s20
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s20
s_cbranch_execz .LBB0_45
.LBB0_43:
scratch_load_b32 v10, v1, off
s_or_b32 s22, s22, exec_lo
s_mov_b32 s23, exec_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v10, v2
v_mov_b32_e32 v10, s21
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_i32_e32 5, v2
s_cbranch_execz .LBB0_42
s_add_i32 s21, s21, 1
v_dual_mov_b32 v10, 0x100 :: v_dual_add_nc_u32 v1, 4, v1
s_cmpk_eq_i32 s21, 0x100
s_cselect_b32 s1, -1, 0
s_and_not1_b32 s22, s22, exec_lo
s_and_b32 s1, s1, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s22, s22, s1
s_branch .LBB0_42
.LBB0_45:
s_or_b32 exec_lo, exec_lo, s20
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s15
s_and_saveexec_b32 s15, s4
s_cbranch_execz .LBB0_1
v_add_nc_u32_e32 v1, s10, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_add_co_u32 v1, s1, s18, v1
v_add_co_ci_u32_e64 v2, s1, s19, v2, s1
global_store_b8 v[1:2], v10, off
s_branch .LBB0_1
.LBB0_48:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18convolution_kernelPhS_ii
.amdhsa_group_segment_fixed_size 100
.amdhsa_private_segment_fixed_size 1040
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 28
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18convolution_kernelPhS_ii, .Lfunc_end0-_Z18convolution_kernelPhS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 100
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18convolution_kernelPhS_ii
.private_segment_fixed_size: 1040
.sgpr_count: 30
.sgpr_spill_count: 0
.symbol: _Z18convolution_kernelPhS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convolution_kernel(unsigned char *input_img, unsigned char *output_img, int height, int width)
{
__shared__ unsigned char input_shared[W][W]; //Shared Memory required for a tile and its halo elements(3 channels)
int chan;
for(chan=0;chan<3;chan++) //3 Channel Image
{
int tx = threadIdx.x;
int ty = threadIdx.y;
int output_row = blockIdx.x*TILE_WIDTH + tx;
int output_col = blockIdx.y*TILE_WIDTH + ty;
int input_row = output_row - MASK_WIDTH/2;
int input_col = output_col - MASK_WIDTH/2;
if((input_row >= 0) && (input_row < height) && (input_col >= 0) && (input_col < width))
{
input_shared[tx][ty] = input_img[(input_row*width + input_col)*3 + chan];
}
else
{
if(input_row<0 && input_col<0)
{
input_shared[tx][ty] = input_img[chan];
}
else if(input_row<0 && input_col<width)
{
input_shared[tx][ty] = input_img[3*input_col + chan];
}
else if(input_row<0)
{
input_shared[tx][ty] = input_img[3*(width-1) + chan];
}
else if(input_row<height && input_col<0)
{
input_shared[tx][ty] = input_img[input_row*width*3 + chan];
}
else if(input_row<height && input_col>width)
{
input_shared[tx][ty] = input_img[(input_row*width +width-1)*3 + chan];
}
else if(input_row>height && input_col<0)
{
input_shared[tx][ty] = input_img[width*(height-1)*3 + chan];
}
else if(input_row>height && input_col<width)
{
input_shared[tx][ty] = input_img[(width*(height-1)+input_col)*3 + chan];
}
else
{
input_shared[tx][ty] = input_img[(width*(height-1) + (width-1))*3 + chan];
}
}
__syncthreads();
int i;
if(tx<TILE_WIDTH && ty<TILE_WIDTH)
{
int j;
int freq[256];
for(i=0;i<256;i++)freq[i]=0;
for(i=0;i<MASK_WIDTH;i++)
{
for(j=0;j<MASK_WIDTH;j++)
{
freq[input_shared[tx+i][ty+j]]++;
}
}
j=0;
for(i=0;i<256;i++)
{
j=j+freq[i];
if(j>((MASK_WIDTH*MASK_WIDTH)/2))break;
}
}
if(output_row<height && output_col<width)
{
output_img[(output_row*width + output_col)*3 + chan] = i;
}
__syncthreads();
}
} | .text
.file "convolution_kernel.hip"
.globl _Z33__device_stub__convolution_kernelPhS_ii # -- Begin function _Z33__device_stub__convolution_kernelPhS_ii
.p2align 4, 0x90
.type _Z33__device_stub__convolution_kernelPhS_ii,@function
_Z33__device_stub__convolution_kernelPhS_ii: # @_Z33__device_stub__convolution_kernelPhS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18convolution_kernelPhS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__convolution_kernelPhS_ii, .Lfunc_end0-_Z33__device_stub__convolution_kernelPhS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18convolution_kernelPhS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18convolution_kernelPhS_ii,@object # @_Z18convolution_kernelPhS_ii
.section .rodata,"a",@progbits
.globl _Z18convolution_kernelPhS_ii
.p2align 3, 0x0
_Z18convolution_kernelPhS_ii:
.quad _Z33__device_stub__convolution_kernelPhS_ii
.size _Z18convolution_kernelPhS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18convolution_kernelPhS_ii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__convolution_kernelPhS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18convolution_kernelPhS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011c8e6_00000000-6_convolution_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z18convolution_kernelPhS_iiPhS_ii
.type _Z42__device_stub__Z18convolution_kernelPhS_iiPhS_ii, @function
_Z42__device_stub__Z18convolution_kernelPhS_iiPhS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18convolution_kernelPhS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z18convolution_kernelPhS_iiPhS_ii, .-_Z42__device_stub__Z18convolution_kernelPhS_iiPhS_ii
.globl _Z18convolution_kernelPhS_ii
.type _Z18convolution_kernelPhS_ii, @function
_Z18convolution_kernelPhS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18convolution_kernelPhS_iiPhS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18convolution_kernelPhS_ii, .-_Z18convolution_kernelPhS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18convolution_kernelPhS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18convolution_kernelPhS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "convolution_kernel.hip"
.globl _Z33__device_stub__convolution_kernelPhS_ii # -- Begin function _Z33__device_stub__convolution_kernelPhS_ii
.p2align 4, 0x90
.type _Z33__device_stub__convolution_kernelPhS_ii,@function
_Z33__device_stub__convolution_kernelPhS_ii: # @_Z33__device_stub__convolution_kernelPhS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18convolution_kernelPhS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__convolution_kernelPhS_ii, .Lfunc_end0-_Z33__device_stub__convolution_kernelPhS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18convolution_kernelPhS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18convolution_kernelPhS_ii,@object # @_Z18convolution_kernelPhS_ii
.section .rodata,"a",@progbits
.globl _Z18convolution_kernelPhS_ii
.p2align 3, 0x0
_Z18convolution_kernelPhS_ii:
.quad _Z33__device_stub__convolution_kernelPhS_ii
.size _Z18convolution_kernelPhS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18convolution_kernelPhS_ii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__convolution_kernelPhS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18convolution_kernelPhS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void cuda_Cal_Gfw(float *GfW, float2 *Grf, float2 *Gcf, int nRows, int nCols) {
unsigned int Tidx = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int Tidy = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int index;
float GfW_temp;
float2 Grf_temp, Gcf_temp;
if ((Tidx < nCols) && (Tidy < nRows)) {
index = Tidx + Tidy * nCols;
Grf_temp = Grf[index];
Gcf_temp = Gcf[index];
GfW_temp = Grf_temp.x * Grf_temp.x + Grf_temp.y * Grf_temp.y +
Gcf_temp.x * Gcf_temp.x + Gcf_temp.y * Gcf_temp.y;
GfW[index] = GfW_temp;
}
} | code for sm_80
Function : _Z12cuda_Cal_GfwPfP6float2S1_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x17c], R0 ; /* 0x00005f0003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0005 */
/*00e0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fe400078e0005 */
/*00f0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0100*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1b00 */
/*0110*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0120*/ FMUL R7, R3, R3 ; /* 0x0000000303077220 */
/* 0x004fc80000400000 */
/*0130*/ FFMA R7, R2, R2, R7 ; /* 0x0000000202077223 */
/* 0x000fc80000000007 */
/*0140*/ FFMA R8, R4, R4, R7 ; /* 0x0000000404087223 */
/* 0x008fe40000000007 */
/*0150*/ IMAD.WIDE.U32 R6, R0, R9, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e0009 */
/*0160*/ FFMA R9, R5, R5, R8 ; /* 0x0000000505097223 */
/* 0x000fca0000000008 */
/*0170*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void cuda_Cal_Gfw(float *GfW, float2 *Grf, float2 *Gcf, int nRows, int nCols) {
unsigned int Tidx = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int Tidy = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int index;
float GfW_temp;
float2 Grf_temp, Gcf_temp;
if ((Tidx < nCols) && (Tidy < nRows)) {
index = Tidx + Tidy * nCols;
Grf_temp = Grf[index];
Gcf_temp = Gcf[index];
GfW_temp = Grf_temp.x * Grf_temp.x + Grf_temp.y * Grf_temp.y +
Gcf_temp.x * Gcf_temp.x + Gcf_temp.y * Gcf_temp.y;
GfW[index] = GfW_temp;
}
} | .file "tmpxft_001a46ec_00000000-6_cuda_Cal_Gfw.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z12cuda_Cal_GfwPfP6float2S1_iiPfP6float2S1_ii
.type _Z45__device_stub__Z12cuda_Cal_GfwPfP6float2S1_iiPfP6float2S1_ii, @function
_Z45__device_stub__Z12cuda_Cal_GfwPfP6float2S1_iiPfP6float2S1_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12cuda_Cal_GfwPfP6float2S1_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z12cuda_Cal_GfwPfP6float2S1_iiPfP6float2S1_ii, .-_Z45__device_stub__Z12cuda_Cal_GfwPfP6float2S1_iiPfP6float2S1_ii
.globl _Z12cuda_Cal_GfwPfP6float2S1_ii
.type _Z12cuda_Cal_GfwPfP6float2S1_ii, @function
_Z12cuda_Cal_GfwPfP6float2S1_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z12cuda_Cal_GfwPfP6float2S1_iiPfP6float2S1_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12cuda_Cal_GfwPfP6float2S1_ii, .-_Z12cuda_Cal_GfwPfP6float2S1_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z12cuda_Cal_GfwPfP6float2S1_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12cuda_Cal_GfwPfP6float2S1_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void cuda_Cal_Gfw(float *GfW, float2 *Grf, float2 *Gcf, int nRows, int nCols) {
unsigned int Tidx = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int Tidy = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int index;
float GfW_temp;
float2 Grf_temp, Gcf_temp;
if ((Tidx < nCols) && (Tidy < nRows)) {
index = Tidx + Tidy * nCols;
Grf_temp = Grf[index];
Gcf_temp = Gcf[index];
GfW_temp = Grf_temp.x * Grf_temp.x + Grf_temp.y * Grf_temp.y +
Gcf_temp.x * Gcf_temp.x + Gcf_temp.y * Gcf_temp.y;
GfW[index] = GfW_temp;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_Cal_Gfw(float *GfW, float2 *Grf, float2 *Gcf, int nRows, int nCols) {
unsigned int Tidx = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int Tidy = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int index;
float GfW_temp;
float2 Grf_temp, Gcf_temp;
if ((Tidx < nCols) && (Tidy < nRows)) {
index = Tidx + Tidy * nCols;
Grf_temp = Grf[index];
Gcf_temp = Gcf[index];
GfW_temp = Grf_temp.x * Grf_temp.x + Grf_temp.y * Grf_temp.y +
Gcf_temp.x * Gcf_temp.x + Gcf_temp.y * Gcf_temp.y;
GfW[index] = GfW_temp;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_Cal_Gfw(float *GfW, float2 *Grf, float2 *Gcf, int nRows, int nCols) {
unsigned int Tidx = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int Tidy = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int index;
float GfW_temp;
float2 Grf_temp, Gcf_temp;
if ((Tidx < nCols) && (Tidy < nRows)) {
index = Tidx + Tidy * nCols;
Grf_temp = Grf[index];
Gcf_temp = Gcf[index];
GfW_temp = Grf_temp.x * Grf_temp.x + Grf_temp.y * Grf_temp.y +
Gcf_temp.x * Gcf_temp.x + Gcf_temp.y * Gcf_temp.y;
GfW[index] = GfW_temp;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii
.globl _Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii
.p2align 8
.type _Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii,@function
_Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s2, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
v_mov_b32_e32 v3, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 3, v[2:3]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[0:1], v[0:1], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v5, v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v4, v4
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v5, v0, v0
v_add_co_u32 v0, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_fmac_f32_e32 v5, v1, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
global_store_b32 v[0:1], v5, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii, .Lfunc_end0-_Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_Cal_Gfw(float *GfW, float2 *Grf, float2 *Gcf, int nRows, int nCols) {
unsigned int Tidx = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int Tidy = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int index;
float GfW_temp;
float2 Grf_temp, Gcf_temp;
if ((Tidx < nCols) && (Tidy < nRows)) {
index = Tidx + Tidy * nCols;
Grf_temp = Grf[index];
Gcf_temp = Gcf[index];
GfW_temp = Grf_temp.x * Grf_temp.x + Grf_temp.y * Grf_temp.y +
Gcf_temp.x * Gcf_temp.x + Gcf_temp.y * Gcf_temp.y;
GfW[index] = GfW_temp;
}
} | .text
.file "cuda_Cal_Gfw.hip"
.globl _Z27__device_stub__cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii # -- Begin function _Z27__device_stub__cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii
.p2align 4, 0x90
.type _Z27__device_stub__cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii,@function
_Z27__device_stub__cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii: # @_Z27__device_stub__cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii, .Lfunc_end0-_Z27__device_stub__cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii,@object # @_Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii
.section .rodata,"a",@progbits
.globl _Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii
.p2align 3, 0x0
_Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii:
.quad _Z27__device_stub__cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii
.size _Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii"
.size .L__unnamed_1, 49
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12cuda_Cal_GfwPfP6float2S1_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x17c], R0 ; /* 0x00005f0003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0005 */
/*00e0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fe400078e0005 */
/*00f0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0100*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1b00 */
/*0110*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0120*/ FMUL R7, R3, R3 ; /* 0x0000000303077220 */
/* 0x004fc80000400000 */
/*0130*/ FFMA R7, R2, R2, R7 ; /* 0x0000000202077223 */
/* 0x000fc80000000007 */
/*0140*/ FFMA R8, R4, R4, R7 ; /* 0x0000000404087223 */
/* 0x008fe40000000007 */
/*0150*/ IMAD.WIDE.U32 R6, R0, R9, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e0009 */
/*0160*/ FFMA R9, R5, R5, R8 ; /* 0x0000000505097223 */
/* 0x000fca0000000008 */
/*0170*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii
.globl _Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii
.p2align 8
.type _Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii,@function
_Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s2, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
v_mov_b32_e32 v3, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 3, v[2:3]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[0:1], v[0:1], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v5, v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v4, v4
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v5, v0, v0
v_add_co_u32 v0, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_fmac_f32_e32 v5, v1, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
global_store_b32 v[0:1], v5, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii, .Lfunc_end0-_Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a46ec_00000000-6_cuda_Cal_Gfw.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z12cuda_Cal_GfwPfP6float2S1_iiPfP6float2S1_ii
.type _Z45__device_stub__Z12cuda_Cal_GfwPfP6float2S1_iiPfP6float2S1_ii, @function
_Z45__device_stub__Z12cuda_Cal_GfwPfP6float2S1_iiPfP6float2S1_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12cuda_Cal_GfwPfP6float2S1_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z12cuda_Cal_GfwPfP6float2S1_iiPfP6float2S1_ii, .-_Z45__device_stub__Z12cuda_Cal_GfwPfP6float2S1_iiPfP6float2S1_ii
.globl _Z12cuda_Cal_GfwPfP6float2S1_ii
.type _Z12cuda_Cal_GfwPfP6float2S1_ii, @function
_Z12cuda_Cal_GfwPfP6float2S1_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z12cuda_Cal_GfwPfP6float2S1_iiPfP6float2S1_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12cuda_Cal_GfwPfP6float2S1_ii, .-_Z12cuda_Cal_GfwPfP6float2S1_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z12cuda_Cal_GfwPfP6float2S1_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12cuda_Cal_GfwPfP6float2S1_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_Cal_Gfw.hip"
.globl _Z27__device_stub__cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii # -- Begin function _Z27__device_stub__cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii
.p2align 4, 0x90
.type _Z27__device_stub__cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii,@function
_Z27__device_stub__cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii: # @_Z27__device_stub__cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii, .Lfunc_end0-_Z27__device_stub__cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii,@object # @_Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii
.section .rodata,"a",@progbits
.globl _Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii
.p2align 3, 0x0
_Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii:
.quad _Z27__device_stub__cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii
.size _Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii"
.size .L__unnamed_1, 49
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12cuda_Cal_GfwPfP15HIP_vector_typeIfLj2EES2_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
// Define your kernels in this file you may use more than one kernel if you
// need to
// INSERT KERNEL(S) HERE
__global__ void histo_kernel(unsigned int *buffer, long size, unsigned int *histo, unsigned int num_bins)
{
extern __shared__ unsigned int histo_private[];
unsigned int i = threadIdx.x + blockIdx.x * blockDim.x;
// stride is total number of threads
unsigned int stride = blockDim.x * gridDim.x;
// All threads handle blockDim.x * gridDim.x
// consecutive elements
//inititialize private histogram
for (int j = 0; j < (num_bins-1)/blockDim.x+1; ++j)
if (blockDim.x*j+threadIdx.x<num_bins)
histo_private[blockDim.x*j+threadIdx.x]=0;
__syncthreads();
//populate private histogram
while (i < size) {
atomicAdd(&(histo_private[buffer[i]]), 1);
i += stride;
}
__syncthreads();
//Transfer data from shared memories to global memory
for (int k = 0; k < (num_bins-1)/blockDim.x+1; ++k)
if (blockDim.x*k+threadIdx.x<num_bins)
atomicAdd(&(histo[blockDim.x*k+threadIdx.x]),
histo_private[blockDim.x*k+threadIdx.x]);
}
/******************************************************************************
Setup and invoke your kernel(s) in this function. You may also allocate more
GPU memory if you need to
*******************************************************************************/
void histogram(unsigned int* input, unsigned int* bins, unsigned int num_elements,
unsigned int num_bins) {
// INSERT CODE HERE
const int BLOCK_SIZE = 512;
histo_kernel<<<(num_elements-1)/BLOCK_SIZE+1,BLOCK_SIZE,num_bins*sizeof(unsigned int)>>>(input,num_elements,bins,num_bins);
} | code for sm_80
Function : _Z12histo_kernelPjlS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.U32.RP R4, c[0x0][0x0] ; /* 0x0000000000047b06 */
/* 0x000e220000209000 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe20003f45070 */
/*0040*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fc600078e00ff */
/*0050*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*0060*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0070*/ IADD3 R3, R4, 0xffffffe, RZ ; /* 0x0ffffffe04037810 */
/* 0x001fcc0007ffe0ff */
/*0080*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e24000021f000 */
/*0090*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x001fc800078e0a03 */
/*00a0*/ IMAD R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a24 */
/* 0x000fc800078e02ff */
/*00b0*/ IMAD.HI.U32 R5, R3, R5, R2 ; /* 0x0000000503057227 */
/* 0x000fcc00078e0002 */
/*00c0*/ IMAD.HI.U32 R2, R5, R0, RZ ; /* 0x0000000005027227 */
/* 0x000fca00078e00ff */
/*00d0*/ IADD3 R5, -R2, RZ, RZ ; /* 0x000000ff02057210 */
/* 0x000fca0007ffe1ff */
/*00e0*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x000fe400078e0200 */
/*00f0*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e260000002500 */
/*0100*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fda0003f06070 */
/*0110*/ @P0 IADD3 R0, R0, -c[0x0][0x0], RZ ; /* 0x8000000000000a10 */
/* 0x000fe40007ffe0ff */
/*0120*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*0130*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fe40003f26070 */
/*0140*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e360000002100 */
/*0150*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fc40007ffe0ff */
/*0160*/ @!P2 LOP3.LUT R2, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff02aa12 */
/* 0x000fc800078e33ff */
/*0170*/ IADD3 R3, R2, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x000fc80007ffe0ff */
/*0180*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f25270 */
/*0190*/ IMAD R6, R5, c[0x0][0x0], R0 ; /* 0x0000000005067a24 */
/* 0x001fd800078e0200 */
/*01a0*/ @!P1 BRA 0x4c0 ; /* 0x0000031000009947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GE.U32.AND P2, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f46070 */
/*01c0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*01d0*/ LOP3.LUT R4, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303047812 */
/* 0x000fc800078ec0ff */
/*01e0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fce0003f05270 */
/*01f0*/ @!P2 BRA 0x410 ; /* 0x000002100000a947 */
/* 0x000fec0003800000 */
/*0200*/ IMAD.MOV.U32 R5, RZ, RZ, 0x2 ; /* 0x00000002ff057424 */
/* 0x000fe200078e00ff */
/*0210*/ IADD3 R8, R0, c[0x0][0x0], RZ ; /* 0x0000000000087a10 */
/* 0x000fe20007ffe0ff */
/*0220*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fe200078e00ff */
/*0230*/ IADD3 R7, R3, -R4, RZ ; /* 0x8000000403077210 */
/* 0x000fe20007ffe0ff */
/*0240*/ IMAD R10, R5, c[0x0][0x0], R0.reuse ; /* 0x00000000050a7a24 */
/* 0x100fe400078e0200 */
/*0250*/ IMAD R12, R9, 0x3, R0 ; /* 0x00000003090c7824 */
/* 0x000fe200078e0200 */
/*0260*/ SHF.L.U32 R9, R8, 0x2, RZ ; /* 0x0000000208097819 */
/* 0x000fe200000006ff */
/*0270*/ IMAD.SHL.U32 R14, R0, 0x4, RZ ; /* 0x00000004000e7824 */
/* 0x000fe400078e00ff */
/*0280*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fc400078e00ff */
/*0290*/ IMAD.MOV.U32 R15, RZ, RZ, R0 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0000 */
/*02a0*/ IMAD.SHL.U32 R11, R10, 0x4, RZ ; /* 0x000000040a0b7824 */
/* 0x000fe400078e00ff */
/*02b0*/ IMAD.SHL.U32 R13, R12, 0x4, RZ ; /* 0x000000040c0d7824 */
/* 0x000fe400078e00ff */
/*02c0*/ ISETP.GE.U32.AND P2, PT, R15, c[0x0][0x178], PT ; /* 0x00005e000f007a0c */
/* 0x000fe20003f46070 */
/*02d0*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff107624 */
/* 0x000fe200078e00ff */
/*02e0*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fe40007ffe0ff */
/*02f0*/ ISETP.GE.U32.AND P3, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fe20003f66070 */
/*0300*/ IMAD R15, R16, 0x4, R15 ; /* 0x00000004100f7824 */
/* 0x000fe200078e020f */
/*0310*/ ISETP.GE.U32.AND P4, PT, R10, c[0x0][0x178], PT ; /* 0x00005e000a007a0c */
/* 0x000fe20003f86070 */
/*0320*/ IMAD R10, R16, 0x4, R10 ; /* 0x00000004100a7824 */
/* 0x000fe200078e020a */
/*0330*/ ISETP.GE.U32.AND P5, PT, R12, c[0x0][0x178], PT ; /* 0x00005e000c007a0c */
/* 0x000fe20003fa6070 */
/*0340*/ IMAD R12, R16.reuse, 0x4, R12 ; /* 0x00000004100c7824 */
/* 0x040fe200078e020c */
/*0350*/ LEA R8, R16, R8, 0x2 ; /* 0x0000000810087211 */
/* 0x000fc400078e10ff */
/*0360*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe20007ffe0ff */
/*0370*/ @!P2 STS [R14], RZ ; /* 0x000000ff0e00a388 */
/* 0x0001e20000000800 */
/*0380*/ ISETP.NE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc60003f45270 */
/*0390*/ @!P3 STS [R9], RZ ; /* 0x000000ff0900b388 */
/* 0x0003e80000000800 */
/*03a0*/ @!P4 STS [R11], RZ ; /* 0x000000ff0b00c388 */
/* 0x0005e20000000800 */
/*03b0*/ LEA R14, R16, R14, 0x4 ; /* 0x0000000e100e7211 */
/* 0x001fc600078e20ff */
/*03c0*/ @!P5 STS [R13], RZ ; /* 0x000000ff0d00d388 */
/* 0x0001e20000000800 */
/*03d0*/ IMAD R9, R16.reuse, 0x10, R9 ; /* 0x0000001010097824 */
/* 0x042fe400078e0209 */
/*03e0*/ IMAD R11, R16.reuse, 0x10, R11 ; /* 0x00000010100b7824 */
/* 0x044fe400078e020b */
/*03f0*/ IMAD R13, R16, 0x10, R13 ; /* 0x00000010100d7824 */
/* 0x001fe200078e020d */
/*0400*/ @P2 BRA 0x2c0 ; /* 0xfffffeb000002947 */
/* 0x000fea000383ffff */
/*0410*/ @!P0 BRA 0x4c0 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*0420*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x000fe200078e0200 */
/*0430*/ MOV R8, c[0x0][0x0] ; /* 0x0000000000087a02 */
/* 0x000fc60000000f00 */
/*0440*/ IMAD.SHL.U32 R7, R5, 0x4, RZ ; /* 0x0000000405077824 */
/* 0x000fe400078e00ff */
/*0450*/ ISETP.GE.U32.AND P0, PT, R5.reuse, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x040fe40003f06070 */
/*0460*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0470*/ IADD3 R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a10 */
/* 0x000fd20007ffe0ff */
/*0480*/ @!P0 STS [R7], RZ ; /* 0x000000ff07008388 */
/* 0x0001e20000000800 */
/*0490*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*04a0*/ IMAD R7, R8, 0x4, R7 ; /* 0x0000000408077824 */
/* 0x001fd800078e0207 */
/*04b0*/ @P0 BRA 0x450 ; /* 0xffffff9000000947 */
/* 0x000fea000383ffff */
/*04c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04d0*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fc80003f06070 */
/*04e0*/ ISETP.GE.AND.EX P0, PT, RZ, c[0x0][0x16c], PT, P0 ; /* 0x00005b00ff007a0c */
/* 0x000fe20003f06300 */
/*04f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*0500*/ @P0 BRA 0x5c0 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0510*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*0520*/ LEA R4, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006047a11 */
/* 0x001fc800078010ff */
/*0530*/ LEA.HI.X R5, R6, c[0x0][0x164], R7, 0x2, P0 ; /* 0x0000590006057a11 */
/* 0x000fca00000f1407 */
/*0540*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0550*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fe20000000f00 */
/*0560*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe80003800000 */
/*0570*/ IMAD R6, R9, c[0x0][0xc], R6 ; /* 0x0000030009067a24 */
/* 0x000fca00078e0206 */
/*0580*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fc80003f06070 */
/*0590*/ ISETP.GE.AND.EX P0, PT, RZ, c[0x0][0x16c], PT, P0 ; /* 0x00005b00ff007a0c */
/* 0x000fe20003f06300 */
/*05a0*/ ATOMS.POPC.INC.32 RZ, [R4.X4+URZ] ; /* 0x0000000004ff7f8c */
/* 0x0041d8000d00403f */
/*05b0*/ @!P0 BRA 0x520 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*05c0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*05d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05e0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*05f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0600*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0610*/ LOP3.LUT R2, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303027812 */
/* 0x000fd600078ec0ff */
/*0620*/ @!P0 BRA 0x9b0 ; /* 0x0000038000008947 */
/* 0x000fea0003800000 */
/*0630*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x000fe200078e00ff */
/*0640*/ IADD3 R5, R0.reuse, c[0x0][0x0], RZ ; /* 0x0000000000057a10 */
/* 0x040fe20007ffe0ff */
/*0650*/ IMAD.IADD R6, R3, 0x1, -R2 ; /* 0x0000000103067824 */
/* 0x000fe200078e0a02 */
/*0660*/ SHF.L.U32 R3, R0, 0x2, RZ ; /* 0x0000000200037819 */
/* 0x000fe200000006ff */
/*0670*/ IMAD R4, R7, 0x2, R0.reuse ; /* 0x0000000207047824 */
/* 0x101fe200078e0200 */
/*0680*/ SHF.L.U32 R10, R5, 0x2, RZ ; /* 0x00000002050a7819 */
/* 0x000fe200000006ff */
/*0690*/ IMAD R12, R7, 0x3, R0.reuse ; /* 0x00000003070c7824 */
/* 0x100fe400078e0200 */
/*06a0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*06b0*/ IMAD.MOV.U32 R14, RZ, RZ, R0 ; /* 0x000000ffff0e7224 */
/* 0x000fc400078e0000 */
/*06c0*/ IMAD.SHL.U32 R11, R4, 0x4, RZ ; /* 0x00000004040b7824 */
/* 0x000fe400078e00ff */
/*06d0*/ IMAD.SHL.U32 R13, R12, 0x4, RZ ; /* 0x000000040c0d7824 */
/* 0x000fe400078e00ff */
/*06e0*/ ISETP.GE.U32.AND P0, PT, R14, c[0x0][0x178], PT ; /* 0x00005e000e007a0c */
/* 0x000fe20003f06070 */
/*06f0*/ BSSY B0, 0x790 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0700*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fe40003f26070 */
/*0710*/ ISETP.GE.U32.AND P2, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fe40003f46070 */
/*0720*/ ISETP.GE.U32.AND P3, PT, R12, c[0x0][0x178], PT ; /* 0x00005e000c007a0c */
/* 0x000fce0003f66070 */
/*0730*/ @P0 BRA 0x780 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0740*/ LDS R15, [R3] ; /* 0x00000000030f7984 */
/* 0x000e220000000800 */
/*0750*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*0760*/ IMAD.WIDE.U32 R8, R14, R9, c[0x0][0x170] ; /* 0x00005c000e087625 */
/* 0x000fca00078e0009 */
/*0770*/ RED.E.ADD.STRONG.GPU [R8.64], R15 ; /* 0x0000000f0800798e */
/* 0x0011e4000c10e184 */
/*0780*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0790*/ BSSY B0, 0x800 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*07a0*/ @P1 BRA 0x7f0 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*07b0*/ LDS R15, [R10] ; /* 0x000000000a0f7984 */
/* 0x001e220000000800 */
/*07c0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fd400000001ff */
/*07d0*/ IMAD.WIDE.U32 R8, R5, R8, c[0x0][0x170] ; /* 0x00005c0005087625 */
/* 0x000fca00078e0008 */
/*07e0*/ RED.E.ADD.STRONG.GPU [R8.64], R15 ; /* 0x0000000f0800798e */
/* 0x0011e4000c10e184 */
/*07f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0800*/ BSSY B0, 0x870 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0810*/ @P2 BRA 0x860 ; /* 0x0000004000002947 */
/* 0x000fea0003800000 */
/*0820*/ LDS R15, [R11] ; /* 0x000000000b0f7984 */
/* 0x001e220000000800 */
/*0830*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*0840*/ IMAD.WIDE.U32 R8, R4, R9, c[0x0][0x170] ; /* 0x00005c0004087625 */
/* 0x000fca00078e0009 */
/*0850*/ RED.E.ADD.STRONG.GPU [R8.64], R15 ; /* 0x0000000f0800798e */
/* 0x0011e4000c10e184 */
/*0860*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0870*/ BSSY B0, 0x8e0 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0880*/ @P3 BRA 0x8d0 ; /* 0x0000004000003947 */
/* 0x000fea0003800000 */
/*0890*/ LDS R15, [R13] ; /* 0x000000000d0f7984 */
/* 0x001e220000000800 */
/*08a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*08b0*/ IMAD.WIDE.U32 R8, R12, R9, c[0x0][0x170] ; /* 0x00005c000c087625 */
/* 0x000fca00078e0009 */
/*08c0*/ RED.E.ADD.STRONG.GPU [R8.64], R15 ; /* 0x0000000f0800798e */
/* 0x0011e4000c10e184 */
/*08d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08e0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fe20007ffe0ff */
/*08f0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff087624 */
/* 0x001fe200078e00ff */
/*0900*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe40007ffe0ff */
/*0910*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0920*/ IMAD R10, R8.reuse, 0x10, R10 ; /* 0x00000010080a7824 */
/* 0x040fe200078e020a */
/*0930*/ LEA R5, R8.reuse, R5, 0x2 ; /* 0x0000000508057211 */
/* 0x040fe200078e10ff */
/*0940*/ IMAD R4, R8.reuse, 0x4, R4 ; /* 0x0000000408047824 */
/* 0x040fe200078e0204 */
/*0950*/ LEA R12, R8.reuse, R12, 0x2 ; /* 0x0000000c080c7211 */
/* 0x040fe200078e10ff */
/*0960*/ IMAD R11, R8.reuse, 0x10, R11 ; /* 0x00000010080b7824 */
/* 0x040fe200078e020b */
/*0970*/ LEA R14, R8.reuse, R14, 0x2 ; /* 0x0000000e080e7211 */
/* 0x040fe200078e10ff */
/*0980*/ IMAD R13, R8, 0x10, R13 ; /* 0x00000010080d7824 */
/* 0x000fc400078e020d */
/*0990*/ IMAD R3, R8, 0x10, R3 ; /* 0x0000001008037824 */
/* 0x000fc800078e0203 */
/*09a0*/ @P0 BRA 0x6e0 ; /* 0xfffffd3000000947 */
/* 0x000fea000383ffff */
/*09b0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*09c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*09d0*/ IMAD R0, R7, c[0x0][0x0], R0 ; /* 0x0000000007007a24 */
/* 0x000fe400078e0200 */
/*09e0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff067624 */
/* 0x000fe400078e00ff */
/*09f0*/ IMAD.SHL.U32 R3, R0, 0x4, RZ ; /* 0x0000000400037824 */
/* 0x000fe400078e00ff */
/*0a00*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06070 */
/*0a10*/ BSSY B0, 0xaa0 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0a20*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fc80007ffe0ff */
/*0a30*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f25270 */
/*0a40*/ @P0 BRA 0xa90 ; /* 0x0000004000000947 */
/* 0x001fea0003800000 */
/*0a50*/ LDS R7, [R3] ; /* 0x0000000003077984 */
/* 0x000e620000000800 */
/*0a60*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fca0000000f00 */
/*0a70*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x001fca00078e0005 */
/*0a80*/ RED.E.ADD.STRONG.GPU [R4.64], R7 ; /* 0x000000070400798e */
/* 0x0021e4000c10e184 */
/*0a90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0aa0*/ IMAD R3, R6, 0x4, R3 ; /* 0x0000000406037824 */
/* 0x000fe200078e0203 */
/*0ab0*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fe20007ffe0ff */
/*0ac0*/ @P1 BRA 0xa00 ; /* 0xffffff3000001947 */
/* 0x000fea000383ffff */
/*0ad0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ae0*/ BRA 0xae0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
// Define your kernels in this file you may use more than one kernel if you
// need to
// INSERT KERNEL(S) HERE
__global__ void histo_kernel(unsigned int *buffer, long size, unsigned int *histo, unsigned int num_bins)
{
extern __shared__ unsigned int histo_private[];
unsigned int i = threadIdx.x + blockIdx.x * blockDim.x;
// stride is total number of threads
unsigned int stride = blockDim.x * gridDim.x;
// All threads handle blockDim.x * gridDim.x
// consecutive elements
//inititialize private histogram
for (int j = 0; j < (num_bins-1)/blockDim.x+1; ++j)
if (blockDim.x*j+threadIdx.x<num_bins)
histo_private[blockDim.x*j+threadIdx.x]=0;
__syncthreads();
//populate private histogram
while (i < size) {
atomicAdd(&(histo_private[buffer[i]]), 1);
i += stride;
}
__syncthreads();
//Transfer data from shared memories to global memory
for (int k = 0; k < (num_bins-1)/blockDim.x+1; ++k)
if (blockDim.x*k+threadIdx.x<num_bins)
atomicAdd(&(histo[blockDim.x*k+threadIdx.x]),
histo_private[blockDim.x*k+threadIdx.x]);
}
/******************************************************************************
Setup and invoke your kernel(s) in this function. You may also allocate more
GPU memory if you need to
*******************************************************************************/
void histogram(unsigned int* input, unsigned int* bins, unsigned int num_elements,
unsigned int num_bins) {
// INSERT CODE HERE
const int BLOCK_SIZE = 512;
histo_kernel<<<(num_elements-1)/BLOCK_SIZE+1,BLOCK_SIZE,num_bins*sizeof(unsigned int)>>>(input,num_elements,bins,num_bins);
} | .file "tmpxft_00182ae2_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z12histo_kernelPjlS_jPjlS_j
.type _Z36__device_stub__Z12histo_kernelPjlS_jPjlS_j, @function
_Z36__device_stub__Z12histo_kernelPjlS_jPjlS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12histo_kernelPjlS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z36__device_stub__Z12histo_kernelPjlS_jPjlS_j, .-_Z36__device_stub__Z12histo_kernelPjlS_jPjlS_j
.globl _Z12histo_kernelPjlS_j
.type _Z12histo_kernelPjlS_j, @function
_Z12histo_kernelPjlS_j:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12histo_kernelPjlS_jPjlS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z12histo_kernelPjlS_j, .-_Z12histo_kernelPjlS_j
.globl _Z9histogramPjS_jj
.type _Z9histogramPjS_jj, @function
_Z9histogramPjS_jj:
.LFB2027:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movq %rsi, %r13
movl %edx, %ebx
movl %ecx, %ebp
movl $512, 20(%rsp)
movl $1, 24(%rsp)
leal -1(%rdx), %eax
shrl $9, %eax
addl $1, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl %ecx, %eax
movl $0, %r9d
leaq 0(,%rax,4), %r8
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %ebx, %esi
movl %ebp, %ecx
movq %r13, %rdx
movq %r12, %rdi
call _Z36__device_stub__Z12histo_kernelPjlS_jPjlS_j
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z9histogramPjS_jj, .-_Z9histogramPjS_jj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12histo_kernelPjlS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12histo_kernelPjlS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
// Define your kernels in this file you may use more than one kernel if you
// need to
// INSERT KERNEL(S) HERE
__global__ void histo_kernel(unsigned int *buffer, long size, unsigned int *histo, unsigned int num_bins)
{
extern __shared__ unsigned int histo_private[];
unsigned int i = threadIdx.x + blockIdx.x * blockDim.x;
// stride is total number of threads
unsigned int stride = blockDim.x * gridDim.x;
// All threads handle blockDim.x * gridDim.x
// consecutive elements
//inititialize private histogram
for (int j = 0; j < (num_bins-1)/blockDim.x+1; ++j)
if (blockDim.x*j+threadIdx.x<num_bins)
histo_private[blockDim.x*j+threadIdx.x]=0;
__syncthreads();
//populate private histogram
while (i < size) {
atomicAdd(&(histo_private[buffer[i]]), 1);
i += stride;
}
__syncthreads();
//Transfer data from shared memories to global memory
for (int k = 0; k < (num_bins-1)/blockDim.x+1; ++k)
if (blockDim.x*k+threadIdx.x<num_bins)
atomicAdd(&(histo[blockDim.x*k+threadIdx.x]),
histo_private[blockDim.x*k+threadIdx.x]);
}
/******************************************************************************
Setup and invoke your kernel(s) in this function. You may also allocate more
GPU memory if you need to
*******************************************************************************/
void histogram(unsigned int* input, unsigned int* bins, unsigned int num_elements,
unsigned int num_bins) {
// INSERT CODE HERE
const int BLOCK_SIZE = 512;
histo_kernel<<<(num_elements-1)/BLOCK_SIZE+1,BLOCK_SIZE,num_bins*sizeof(unsigned int)>>>(input,num_elements,bins,num_bins);
} | #include <hip/hip_runtime.h>
/******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
// Define your kernels in this file you may use more than one kernel if you
// need to
// INSERT KERNEL(S) HERE
__global__ void histo_kernel(unsigned int *buffer, long size, unsigned int *histo, unsigned int num_bins)
{
extern __shared__ unsigned int histo_private[];
unsigned int i = threadIdx.x + blockIdx.x * blockDim.x;
// stride is total number of threads
unsigned int stride = blockDim.x * gridDim.x;
// All threads handle blockDim.x * gridDim.x
// consecutive elements
//inititialize private histogram
for (int j = 0; j < (num_bins-1)/blockDim.x+1; ++j)
if (blockDim.x*j+threadIdx.x<num_bins)
histo_private[blockDim.x*j+threadIdx.x]=0;
__syncthreads();
//populate private histogram
while (i < size) {
atomicAdd(&(histo_private[buffer[i]]), 1);
i += stride;
}
__syncthreads();
//Transfer data from shared memories to global memory
for (int k = 0; k < (num_bins-1)/blockDim.x+1; ++k)
if (blockDim.x*k+threadIdx.x<num_bins)
atomicAdd(&(histo[blockDim.x*k+threadIdx.x]),
histo_private[blockDim.x*k+threadIdx.x]);
}
/******************************************************************************
Setup and invoke your kernel(s) in this function. You may also allocate more
GPU memory if you need to
*******************************************************************************/
void histogram(unsigned int* input, unsigned int* bins, unsigned int num_elements,
unsigned int num_bins) {
// INSERT CODE HERE
const int BLOCK_SIZE = 512;
histo_kernel<<<(num_elements-1)/BLOCK_SIZE+1,BLOCK_SIZE,num_bins*sizeof(unsigned int)>>>(input,num_elements,bins,num_bins);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
// Define your kernels in this file you may use more than one kernel if you
// need to
// INSERT KERNEL(S) HERE
__global__ void histo_kernel(unsigned int *buffer, long size, unsigned int *histo, unsigned int num_bins)
{
extern __shared__ unsigned int histo_private[];
unsigned int i = threadIdx.x + blockIdx.x * blockDim.x;
// stride is total number of threads
unsigned int stride = blockDim.x * gridDim.x;
// All threads handle blockDim.x * gridDim.x
// consecutive elements
//inititialize private histogram
for (int j = 0; j < (num_bins-1)/blockDim.x+1; ++j)
if (blockDim.x*j+threadIdx.x<num_bins)
histo_private[blockDim.x*j+threadIdx.x]=0;
__syncthreads();
//populate private histogram
while (i < size) {
atomicAdd(&(histo_private[buffer[i]]), 1);
i += stride;
}
__syncthreads();
//Transfer data from shared memories to global memory
for (int k = 0; k < (num_bins-1)/blockDim.x+1; ++k)
if (blockDim.x*k+threadIdx.x<num_bins)
atomicAdd(&(histo[blockDim.x*k+threadIdx.x]),
histo_private[blockDim.x*k+threadIdx.x]);
}
/******************************************************************************
Setup and invoke your kernel(s) in this function. You may also allocate more
GPU memory if you need to
*******************************************************************************/
void histogram(unsigned int* input, unsigned int* bins, unsigned int num_elements,
unsigned int num_bins) {
// INSERT CODE HERE
const int BLOCK_SIZE = 512;
histo_kernel<<<(num_elements-1)/BLOCK_SIZE+1,BLOCK_SIZE,num_bins*sizeof(unsigned int)>>>(input,num_elements,bins,num_bins);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12histo_kernelPjlS_j
.globl _Z12histo_kernelPjlS_j
.p2align 8
.type _Z12histo_kernelPjlS_j,@function
_Z12histo_kernelPjlS_j:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s9, s[0:1], 0x20
s_load_b32 s7, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s2, 0xffff
s_add_i32 s4, s7, -1
v_cvt_f32_u32_e32 v1, s6
s_sub_i32 s3, 0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s2, v1
s_mul_i32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s3, s2, s3
s_add_i32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s2, s4, s2
s_mul_i32 s3, s2, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s3, s4, s3
s_add_i32 s4, s2, 1
s_sub_i32 s5, s3, s6
s_cmp_ge_u32 s3, s6
s_cselect_b32 s2, s4, s2
s_cselect_b32 s3, s5, s3
s_add_i32 s4, s2, 1
s_cmp_ge_u32 s3, s6
s_cselect_b32 s2, s4, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s2, s2, 1
s_and_b32 vcc_lo, exec_lo, s2
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_1)
v_readfirstlane_b32 s8, v1
s_cbranch_vccnz .LBB0_5
v_lshl_add_u32 v1, v0, 2, 0
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, v0
s_lshl_b32 s3, s6, 2
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
v_add_nc_u32_e32 v1, s3, v1
v_add_nc_u32_e32 v3, s6, v3
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s2, s8
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s7, v3
s_cbranch_execz .LBB0_2
ds_store_b32 v1, v2
s_branch .LBB0_2
.LBB0_5:
s_load_b64 s[2:3], s[0:1], 0x8
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_8
s_load_b64 s[4:5], s[0:1], 0x0
s_add_i32 s15, s15, s9
v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
v_mad_u64_u32 v[6:7], null, s15, s6, v[0:1]
v_mov_b32_e32 v5, 1
s_mul_i32 s9, s9, s6
s_mov_b32 s11, 0
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v1, v6
.p2align 6
.LBB0_7:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_cmp_le_i64_e32 vcc_lo, s[2:3], v[1:2]
global_load_b32 v3, v[3:4], off
s_or_b32 s11, vcc_lo, s11
s_waitcnt vmcnt(0)
v_lshl_add_u32 v3, v3, 2, 0
ds_add_u32 v3, v5
v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
v_add_nc_u32_e32 v1, s9, v1
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_7
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s10
s_cmp_eq_u32 s8, 0
s_mov_b32 s2, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_13
s_load_b64 s[0:1], s[0:1], 0x10
v_lshl_add_u32 v2, v0, 2, 0
v_mov_b32_e32 v1, 0
s_lshl_b32 s3, s6, 2
s_branch .LBB0_11
.p2align 6
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s4
v_add_nc_u32_e32 v2, s3, v2
v_add_nc_u32_e32 v0, s6, v0
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s2, s8
s_cbranch_scc1 .LBB0_13
.LBB0_11:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s7, v0
s_cbranch_execz .LBB0_10
ds_load_b32 v5, v2
v_lshlrev_b64 v[3:4], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_atomic_add_u32 v[3:4], v5, off
s_branch .LBB0_10
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12histo_kernelPjlS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12histo_kernelPjlS_j, .Lfunc_end0-_Z12histo_kernelPjlS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym histo_private
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12histo_kernelPjlS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12histo_kernelPjlS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
// Define your kernels in this file you may use more than one kernel if you
// need to
// INSERT KERNEL(S) HERE
__global__ void histo_kernel(unsigned int *buffer, long size, unsigned int *histo, unsigned int num_bins)
{
extern __shared__ unsigned int histo_private[];
unsigned int i = threadIdx.x + blockIdx.x * blockDim.x;
// stride is total number of threads
unsigned int stride = blockDim.x * gridDim.x;
// All threads handle blockDim.x * gridDim.x
// consecutive elements
//inititialize private histogram
for (int j = 0; j < (num_bins-1)/blockDim.x+1; ++j)
if (blockDim.x*j+threadIdx.x<num_bins)
histo_private[blockDim.x*j+threadIdx.x]=0;
__syncthreads();
//populate private histogram
while (i < size) {
atomicAdd(&(histo_private[buffer[i]]), 1);
i += stride;
}
__syncthreads();
//Transfer data from shared memories to global memory
for (int k = 0; k < (num_bins-1)/blockDim.x+1; ++k)
if (blockDim.x*k+threadIdx.x<num_bins)
atomicAdd(&(histo[blockDim.x*k+threadIdx.x]),
histo_private[blockDim.x*k+threadIdx.x]);
}
/******************************************************************************
Setup and invoke your kernel(s) in this function. You may also allocate more
GPU memory if you need to
*******************************************************************************/
void histogram(unsigned int* input, unsigned int* bins, unsigned int num_elements,
unsigned int num_bins) {
// INSERT CODE HERE
const int BLOCK_SIZE = 512;
histo_kernel<<<(num_elements-1)/BLOCK_SIZE+1,BLOCK_SIZE,num_bins*sizeof(unsigned int)>>>(input,num_elements,bins,num_bins);
} | .text
.file "kernel.hip"
.globl _Z27__device_stub__histo_kernelPjlS_j # -- Begin function _Z27__device_stub__histo_kernelPjlS_j
.p2align 4, 0x90
.type _Z27__device_stub__histo_kernelPjlS_j,@function
_Z27__device_stub__histo_kernelPjlS_j: # @_Z27__device_stub__histo_kernelPjlS_j
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12histo_kernelPjlS_j, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__histo_kernelPjlS_j, .Lfunc_end0-_Z27__device_stub__histo_kernelPjlS_j
.cfi_endproc
# -- End function
.globl _Z9histogramPjS_jj # -- Begin function _Z9histogramPjS_jj
.p2align 4, 0x90
.type _Z9histogramPjS_jj,@function
_Z9histogramPjS_jj: # @_Z9histogramPjS_jj
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %ebx
movl %edx, %r12d
movq %rsi, %r14
movq %rdi, %r15
leal -1(%r12), %eax
shrl $9, %eax
movl %ecx, %r8d
shlq $2, %r8
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%rdx,%rax), %rdi
incq %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movl %r12d, %eax
movq %r15, 72(%rsp)
movq %rax, 64(%rsp)
movq %r14, 56(%rsp)
movl %ebx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12histo_kernelPjlS_j, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9histogramPjS_jj, .Lfunc_end1-_Z9histogramPjS_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12histo_kernelPjlS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12histo_kernelPjlS_j,@object # @_Z12histo_kernelPjlS_j
.section .rodata,"a",@progbits
.globl _Z12histo_kernelPjlS_j
.p2align 3, 0x0
_Z12histo_kernelPjlS_j:
.quad _Z27__device_stub__histo_kernelPjlS_j
.size _Z12histo_kernelPjlS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12histo_kernelPjlS_j"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__histo_kernelPjlS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12histo_kernelPjlS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12histo_kernelPjlS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.U32.RP R4, c[0x0][0x0] ; /* 0x0000000000047b06 */
/* 0x000e220000209000 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe20003f45070 */
/*0040*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fc600078e00ff */
/*0050*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*0060*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0070*/ IADD3 R3, R4, 0xffffffe, RZ ; /* 0x0ffffffe04037810 */
/* 0x001fcc0007ffe0ff */
/*0080*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e24000021f000 */
/*0090*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x001fc800078e0a03 */
/*00a0*/ IMAD R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a24 */
/* 0x000fc800078e02ff */
/*00b0*/ IMAD.HI.U32 R5, R3, R5, R2 ; /* 0x0000000503057227 */
/* 0x000fcc00078e0002 */
/*00c0*/ IMAD.HI.U32 R2, R5, R0, RZ ; /* 0x0000000005027227 */
/* 0x000fca00078e00ff */
/*00d0*/ IADD3 R5, -R2, RZ, RZ ; /* 0x000000ff02057210 */
/* 0x000fca0007ffe1ff */
/*00e0*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x000fe400078e0200 */
/*00f0*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e260000002500 */
/*0100*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fda0003f06070 */
/*0110*/ @P0 IADD3 R0, R0, -c[0x0][0x0], RZ ; /* 0x8000000000000a10 */
/* 0x000fe40007ffe0ff */
/*0120*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*0130*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fe40003f26070 */
/*0140*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e360000002100 */
/*0150*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fc40007ffe0ff */
/*0160*/ @!P2 LOP3.LUT R2, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff02aa12 */
/* 0x000fc800078e33ff */
/*0170*/ IADD3 R3, R2, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x000fc80007ffe0ff */
/*0180*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f25270 */
/*0190*/ IMAD R6, R5, c[0x0][0x0], R0 ; /* 0x0000000005067a24 */
/* 0x001fd800078e0200 */
/*01a0*/ @!P1 BRA 0x4c0 ; /* 0x0000031000009947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GE.U32.AND P2, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f46070 */
/*01c0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*01d0*/ LOP3.LUT R4, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303047812 */
/* 0x000fc800078ec0ff */
/*01e0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fce0003f05270 */
/*01f0*/ @!P2 BRA 0x410 ; /* 0x000002100000a947 */
/* 0x000fec0003800000 */
/*0200*/ IMAD.MOV.U32 R5, RZ, RZ, 0x2 ; /* 0x00000002ff057424 */
/* 0x000fe200078e00ff */
/*0210*/ IADD3 R8, R0, c[0x0][0x0], RZ ; /* 0x0000000000087a10 */
/* 0x000fe20007ffe0ff */
/*0220*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fe200078e00ff */
/*0230*/ IADD3 R7, R3, -R4, RZ ; /* 0x8000000403077210 */
/* 0x000fe20007ffe0ff */
/*0240*/ IMAD R10, R5, c[0x0][0x0], R0.reuse ; /* 0x00000000050a7a24 */
/* 0x100fe400078e0200 */
/*0250*/ IMAD R12, R9, 0x3, R0 ; /* 0x00000003090c7824 */
/* 0x000fe200078e0200 */
/*0260*/ SHF.L.U32 R9, R8, 0x2, RZ ; /* 0x0000000208097819 */
/* 0x000fe200000006ff */
/*0270*/ IMAD.SHL.U32 R14, R0, 0x4, RZ ; /* 0x00000004000e7824 */
/* 0x000fe400078e00ff */
/*0280*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fc400078e00ff */
/*0290*/ IMAD.MOV.U32 R15, RZ, RZ, R0 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0000 */
/*02a0*/ IMAD.SHL.U32 R11, R10, 0x4, RZ ; /* 0x000000040a0b7824 */
/* 0x000fe400078e00ff */
/*02b0*/ IMAD.SHL.U32 R13, R12, 0x4, RZ ; /* 0x000000040c0d7824 */
/* 0x000fe400078e00ff */
/*02c0*/ ISETP.GE.U32.AND P2, PT, R15, c[0x0][0x178], PT ; /* 0x00005e000f007a0c */
/* 0x000fe20003f46070 */
/*02d0*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff107624 */
/* 0x000fe200078e00ff */
/*02e0*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fe40007ffe0ff */
/*02f0*/ ISETP.GE.U32.AND P3, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fe20003f66070 */
/*0300*/ IMAD R15, R16, 0x4, R15 ; /* 0x00000004100f7824 */
/* 0x000fe200078e020f */
/*0310*/ ISETP.GE.U32.AND P4, PT, R10, c[0x0][0x178], PT ; /* 0x00005e000a007a0c */
/* 0x000fe20003f86070 */
/*0320*/ IMAD R10, R16, 0x4, R10 ; /* 0x00000004100a7824 */
/* 0x000fe200078e020a */
/*0330*/ ISETP.GE.U32.AND P5, PT, R12, c[0x0][0x178], PT ; /* 0x00005e000c007a0c */
/* 0x000fe20003fa6070 */
/*0340*/ IMAD R12, R16.reuse, 0x4, R12 ; /* 0x00000004100c7824 */
/* 0x040fe200078e020c */
/*0350*/ LEA R8, R16, R8, 0x2 ; /* 0x0000000810087211 */
/* 0x000fc400078e10ff */
/*0360*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe20007ffe0ff */
/*0370*/ @!P2 STS [R14], RZ ; /* 0x000000ff0e00a388 */
/* 0x0001e20000000800 */
/*0380*/ ISETP.NE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc60003f45270 */
/*0390*/ @!P3 STS [R9], RZ ; /* 0x000000ff0900b388 */
/* 0x0003e80000000800 */
/*03a0*/ @!P4 STS [R11], RZ ; /* 0x000000ff0b00c388 */
/* 0x0005e20000000800 */
/*03b0*/ LEA R14, R16, R14, 0x4 ; /* 0x0000000e100e7211 */
/* 0x001fc600078e20ff */
/*03c0*/ @!P5 STS [R13], RZ ; /* 0x000000ff0d00d388 */
/* 0x0001e20000000800 */
/*03d0*/ IMAD R9, R16.reuse, 0x10, R9 ; /* 0x0000001010097824 */
/* 0x042fe400078e0209 */
/*03e0*/ IMAD R11, R16.reuse, 0x10, R11 ; /* 0x00000010100b7824 */
/* 0x044fe400078e020b */
/*03f0*/ IMAD R13, R16, 0x10, R13 ; /* 0x00000010100d7824 */
/* 0x001fe200078e020d */
/*0400*/ @P2 BRA 0x2c0 ; /* 0xfffffeb000002947 */
/* 0x000fea000383ffff */
/*0410*/ @!P0 BRA 0x4c0 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*0420*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x000fe200078e0200 */
/*0430*/ MOV R8, c[0x0][0x0] ; /* 0x0000000000087a02 */
/* 0x000fc60000000f00 */
/*0440*/ IMAD.SHL.U32 R7, R5, 0x4, RZ ; /* 0x0000000405077824 */
/* 0x000fe400078e00ff */
/*0450*/ ISETP.GE.U32.AND P0, PT, R5.reuse, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x040fe40003f06070 */
/*0460*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0470*/ IADD3 R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a10 */
/* 0x000fd20007ffe0ff */
/*0480*/ @!P0 STS [R7], RZ ; /* 0x000000ff07008388 */
/* 0x0001e20000000800 */
/*0490*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*04a0*/ IMAD R7, R8, 0x4, R7 ; /* 0x0000000408077824 */
/* 0x001fd800078e0207 */
/*04b0*/ @P0 BRA 0x450 ; /* 0xffffff9000000947 */
/* 0x000fea000383ffff */
/*04c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04d0*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fc80003f06070 */
/*04e0*/ ISETP.GE.AND.EX P0, PT, RZ, c[0x0][0x16c], PT, P0 ; /* 0x00005b00ff007a0c */
/* 0x000fe20003f06300 */
/*04f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*0500*/ @P0 BRA 0x5c0 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0510*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*0520*/ LEA R4, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006047a11 */
/* 0x001fc800078010ff */
/*0530*/ LEA.HI.X R5, R6, c[0x0][0x164], R7, 0x2, P0 ; /* 0x0000590006057a11 */
/* 0x000fca00000f1407 */
/*0540*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0550*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fe20000000f00 */
/*0560*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe80003800000 */
/*0570*/ IMAD R6, R9, c[0x0][0xc], R6 ; /* 0x0000030009067a24 */
/* 0x000fca00078e0206 */
/*0580*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fc80003f06070 */
/*0590*/ ISETP.GE.AND.EX P0, PT, RZ, c[0x0][0x16c], PT, P0 ; /* 0x00005b00ff007a0c */
/* 0x000fe20003f06300 */
/*05a0*/ ATOMS.POPC.INC.32 RZ, [R4.X4+URZ] ; /* 0x0000000004ff7f8c */
/* 0x0041d8000d00403f */
/*05b0*/ @!P0 BRA 0x520 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*05c0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*05d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05e0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*05f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0600*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0610*/ LOP3.LUT R2, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303027812 */
/* 0x000fd600078ec0ff */
/*0620*/ @!P0 BRA 0x9b0 ; /* 0x0000038000008947 */
/* 0x000fea0003800000 */
/*0630*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x000fe200078e00ff */
/*0640*/ IADD3 R5, R0.reuse, c[0x0][0x0], RZ ; /* 0x0000000000057a10 */
/* 0x040fe20007ffe0ff */
/*0650*/ IMAD.IADD R6, R3, 0x1, -R2 ; /* 0x0000000103067824 */
/* 0x000fe200078e0a02 */
/*0660*/ SHF.L.U32 R3, R0, 0x2, RZ ; /* 0x0000000200037819 */
/* 0x000fe200000006ff */
/*0670*/ IMAD R4, R7, 0x2, R0.reuse ; /* 0x0000000207047824 */
/* 0x101fe200078e0200 */
/*0680*/ SHF.L.U32 R10, R5, 0x2, RZ ; /* 0x00000002050a7819 */
/* 0x000fe200000006ff */
/*0690*/ IMAD R12, R7, 0x3, R0.reuse ; /* 0x00000003070c7824 */
/* 0x100fe400078e0200 */
/*06a0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*06b0*/ IMAD.MOV.U32 R14, RZ, RZ, R0 ; /* 0x000000ffff0e7224 */
/* 0x000fc400078e0000 */
/*06c0*/ IMAD.SHL.U32 R11, R4, 0x4, RZ ; /* 0x00000004040b7824 */
/* 0x000fe400078e00ff */
/*06d0*/ IMAD.SHL.U32 R13, R12, 0x4, RZ ; /* 0x000000040c0d7824 */
/* 0x000fe400078e00ff */
/*06e0*/ ISETP.GE.U32.AND P0, PT, R14, c[0x0][0x178], PT ; /* 0x00005e000e007a0c */
/* 0x000fe20003f06070 */
/*06f0*/ BSSY B0, 0x790 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0700*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fe40003f26070 */
/*0710*/ ISETP.GE.U32.AND P2, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fe40003f46070 */
/*0720*/ ISETP.GE.U32.AND P3, PT, R12, c[0x0][0x178], PT ; /* 0x00005e000c007a0c */
/* 0x000fce0003f66070 */
/*0730*/ @P0 BRA 0x780 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0740*/ LDS R15, [R3] ; /* 0x00000000030f7984 */
/* 0x000e220000000800 */
/*0750*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*0760*/ IMAD.WIDE.U32 R8, R14, R9, c[0x0][0x170] ; /* 0x00005c000e087625 */
/* 0x000fca00078e0009 */
/*0770*/ RED.E.ADD.STRONG.GPU [R8.64], R15 ; /* 0x0000000f0800798e */
/* 0x0011e4000c10e184 */
/*0780*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0790*/ BSSY B0, 0x800 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*07a0*/ @P1 BRA 0x7f0 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*07b0*/ LDS R15, [R10] ; /* 0x000000000a0f7984 */
/* 0x001e220000000800 */
/*07c0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fd400000001ff */
/*07d0*/ IMAD.WIDE.U32 R8, R5, R8, c[0x0][0x170] ; /* 0x00005c0005087625 */
/* 0x000fca00078e0008 */
/*07e0*/ RED.E.ADD.STRONG.GPU [R8.64], R15 ; /* 0x0000000f0800798e */
/* 0x0011e4000c10e184 */
/*07f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0800*/ BSSY B0, 0x870 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0810*/ @P2 BRA 0x860 ; /* 0x0000004000002947 */
/* 0x000fea0003800000 */
/*0820*/ LDS R15, [R11] ; /* 0x000000000b0f7984 */
/* 0x001e220000000800 */
/*0830*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*0840*/ IMAD.WIDE.U32 R8, R4, R9, c[0x0][0x170] ; /* 0x00005c0004087625 */
/* 0x000fca00078e0009 */
/*0850*/ RED.E.ADD.STRONG.GPU [R8.64], R15 ; /* 0x0000000f0800798e */
/* 0x0011e4000c10e184 */
/*0860*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0870*/ BSSY B0, 0x8e0 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0880*/ @P3 BRA 0x8d0 ; /* 0x0000004000003947 */
/* 0x000fea0003800000 */
/*0890*/ LDS R15, [R13] ; /* 0x000000000d0f7984 */
/* 0x001e220000000800 */
/*08a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*08b0*/ IMAD.WIDE.U32 R8, R12, R9, c[0x0][0x170] ; /* 0x00005c000c087625 */
/* 0x000fca00078e0009 */
/*08c0*/ RED.E.ADD.STRONG.GPU [R8.64], R15 ; /* 0x0000000f0800798e */
/* 0x0011e4000c10e184 */
/*08d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08e0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fe20007ffe0ff */
/*08f0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff087624 */
/* 0x001fe200078e00ff */
/*0900*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe40007ffe0ff */
/*0910*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0920*/ IMAD R10, R8.reuse, 0x10, R10 ; /* 0x00000010080a7824 */
/* 0x040fe200078e020a */
/*0930*/ LEA R5, R8.reuse, R5, 0x2 ; /* 0x0000000508057211 */
/* 0x040fe200078e10ff */
/*0940*/ IMAD R4, R8.reuse, 0x4, R4 ; /* 0x0000000408047824 */
/* 0x040fe200078e0204 */
/*0950*/ LEA R12, R8.reuse, R12, 0x2 ; /* 0x0000000c080c7211 */
/* 0x040fe200078e10ff */
/*0960*/ IMAD R11, R8.reuse, 0x10, R11 ; /* 0x00000010080b7824 */
/* 0x040fe200078e020b */
/*0970*/ LEA R14, R8.reuse, R14, 0x2 ; /* 0x0000000e080e7211 */
/* 0x040fe200078e10ff */
/*0980*/ IMAD R13, R8, 0x10, R13 ; /* 0x00000010080d7824 */
/* 0x000fc400078e020d */
/*0990*/ IMAD R3, R8, 0x10, R3 ; /* 0x0000001008037824 */
/* 0x000fc800078e0203 */
/*09a0*/ @P0 BRA 0x6e0 ; /* 0xfffffd3000000947 */
/* 0x000fea000383ffff */
/*09b0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*09c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*09d0*/ IMAD R0, R7, c[0x0][0x0], R0 ; /* 0x0000000007007a24 */
/* 0x000fe400078e0200 */
/*09e0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff067624 */
/* 0x000fe400078e00ff */
/*09f0*/ IMAD.SHL.U32 R3, R0, 0x4, RZ ; /* 0x0000000400037824 */
/* 0x000fe400078e00ff */
/*0a00*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06070 */
/*0a10*/ BSSY B0, 0xaa0 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0a20*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fc80007ffe0ff */
/*0a30*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f25270 */
/*0a40*/ @P0 BRA 0xa90 ; /* 0x0000004000000947 */
/* 0x001fea0003800000 */
/*0a50*/ LDS R7, [R3] ; /* 0x0000000003077984 */
/* 0x000e620000000800 */
/*0a60*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fca0000000f00 */
/*0a70*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x001fca00078e0005 */
/*0a80*/ RED.E.ADD.STRONG.GPU [R4.64], R7 ; /* 0x000000070400798e */
/* 0x0021e4000c10e184 */
/*0a90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0aa0*/ IMAD R3, R6, 0x4, R3 ; /* 0x0000000406037824 */
/* 0x000fe200078e0203 */
/*0ab0*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fe20007ffe0ff */
/*0ac0*/ @P1 BRA 0xa00 ; /* 0xffffff3000001947 */
/* 0x000fea000383ffff */
/*0ad0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ae0*/ BRA 0xae0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12histo_kernelPjlS_j
.globl _Z12histo_kernelPjlS_j
.p2align 8
.type _Z12histo_kernelPjlS_j,@function
_Z12histo_kernelPjlS_j:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s9, s[0:1], 0x20
s_load_b32 s7, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s2, 0xffff
s_add_i32 s4, s7, -1
v_cvt_f32_u32_e32 v1, s6
s_sub_i32 s3, 0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s2, v1
s_mul_i32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s3, s2, s3
s_add_i32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s2, s4, s2
s_mul_i32 s3, s2, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s3, s4, s3
s_add_i32 s4, s2, 1
s_sub_i32 s5, s3, s6
s_cmp_ge_u32 s3, s6
s_cselect_b32 s2, s4, s2
s_cselect_b32 s3, s5, s3
s_add_i32 s4, s2, 1
s_cmp_ge_u32 s3, s6
s_cselect_b32 s2, s4, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s2, s2, 1
s_and_b32 vcc_lo, exec_lo, s2
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_1)
v_readfirstlane_b32 s8, v1
s_cbranch_vccnz .LBB0_5
v_lshl_add_u32 v1, v0, 2, 0
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, v0
s_lshl_b32 s3, s6, 2
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
v_add_nc_u32_e32 v1, s3, v1
v_add_nc_u32_e32 v3, s6, v3
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s2, s8
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s7, v3
s_cbranch_execz .LBB0_2
ds_store_b32 v1, v2
s_branch .LBB0_2
.LBB0_5:
s_load_b64 s[2:3], s[0:1], 0x8
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_8
s_load_b64 s[4:5], s[0:1], 0x0
s_add_i32 s15, s15, s9
v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
v_mad_u64_u32 v[6:7], null, s15, s6, v[0:1]
v_mov_b32_e32 v5, 1
s_mul_i32 s9, s9, s6
s_mov_b32 s11, 0
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v1, v6
.p2align 6
.LBB0_7:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_cmp_le_i64_e32 vcc_lo, s[2:3], v[1:2]
global_load_b32 v3, v[3:4], off
s_or_b32 s11, vcc_lo, s11
s_waitcnt vmcnt(0)
v_lshl_add_u32 v3, v3, 2, 0
ds_add_u32 v3, v5
v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
v_add_nc_u32_e32 v1, s9, v1
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_7
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s10
s_cmp_eq_u32 s8, 0
s_mov_b32 s2, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_13
s_load_b64 s[0:1], s[0:1], 0x10
v_lshl_add_u32 v2, v0, 2, 0
v_mov_b32_e32 v1, 0
s_lshl_b32 s3, s6, 2
s_branch .LBB0_11
.p2align 6
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s4
v_add_nc_u32_e32 v2, s3, v2
v_add_nc_u32_e32 v0, s6, v0
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s2, s8
s_cbranch_scc1 .LBB0_13
.LBB0_11:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s7, v0
s_cbranch_execz .LBB0_10
ds_load_b32 v5, v2
v_lshlrev_b64 v[3:4], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_atomic_add_u32 v[3:4], v5, off
s_branch .LBB0_10
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12histo_kernelPjlS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12histo_kernelPjlS_j, .Lfunc_end0-_Z12histo_kernelPjlS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym histo_private
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12histo_kernelPjlS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12histo_kernelPjlS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00182ae2_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z12histo_kernelPjlS_jPjlS_j
.type _Z36__device_stub__Z12histo_kernelPjlS_jPjlS_j, @function
_Z36__device_stub__Z12histo_kernelPjlS_jPjlS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12histo_kernelPjlS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z36__device_stub__Z12histo_kernelPjlS_jPjlS_j, .-_Z36__device_stub__Z12histo_kernelPjlS_jPjlS_j
.globl _Z12histo_kernelPjlS_j
.type _Z12histo_kernelPjlS_j, @function
_Z12histo_kernelPjlS_j:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12histo_kernelPjlS_jPjlS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z12histo_kernelPjlS_j, .-_Z12histo_kernelPjlS_j
.globl _Z9histogramPjS_jj
.type _Z9histogramPjS_jj, @function
_Z9histogramPjS_jj:
.LFB2027:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movq %rsi, %r13
movl %edx, %ebx
movl %ecx, %ebp
movl $512, 20(%rsp)
movl $1, 24(%rsp)
leal -1(%rdx), %eax
shrl $9, %eax
addl $1, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl %ecx, %eax
movl $0, %r9d
leaq 0(,%rax,4), %r8
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %ebx, %esi
movl %ebp, %ecx
movq %r13, %rdx
movq %r12, %rdi
call _Z36__device_stub__Z12histo_kernelPjlS_jPjlS_j
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z9histogramPjS_jj, .-_Z9histogramPjS_jj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12histo_kernelPjlS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12histo_kernelPjlS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z27__device_stub__histo_kernelPjlS_j # -- Begin function _Z27__device_stub__histo_kernelPjlS_j
.p2align 4, 0x90
.type _Z27__device_stub__histo_kernelPjlS_j,@function
_Z27__device_stub__histo_kernelPjlS_j: # @_Z27__device_stub__histo_kernelPjlS_j
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12histo_kernelPjlS_j, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__histo_kernelPjlS_j, .Lfunc_end0-_Z27__device_stub__histo_kernelPjlS_j
.cfi_endproc
# -- End function
.globl _Z9histogramPjS_jj # -- Begin function _Z9histogramPjS_jj
.p2align 4, 0x90
.type _Z9histogramPjS_jj,@function
_Z9histogramPjS_jj: # @_Z9histogramPjS_jj
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %ebx
movl %edx, %r12d
movq %rsi, %r14
movq %rdi, %r15
leal -1(%r12), %eax
shrl $9, %eax
movl %ecx, %r8d
shlq $2, %r8
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%rdx,%rax), %rdi
incq %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movl %r12d, %eax
movq %r15, 72(%rsp)
movq %rax, 64(%rsp)
movq %r14, 56(%rsp)
movl %ebx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12histo_kernelPjlS_j, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9histogramPjS_jj, .Lfunc_end1-_Z9histogramPjS_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12histo_kernelPjlS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12histo_kernelPjlS_j,@object # @_Z12histo_kernelPjlS_j
.section .rodata,"a",@progbits
.globl _Z12histo_kernelPjlS_j
.p2align 3, 0x0
_Z12histo_kernelPjlS_j:
.quad _Z27__device_stub__histo_kernelPjlS_j
.size _Z12histo_kernelPjlS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12histo_kernelPjlS_j"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__histo_kernelPjlS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12histo_kernelPjlS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
Code adapted from book "CUDA by Example: An Introduction to General-Purpose GPU Programming"
This code computes a visualization of the Julia set. Two-dimenansional "bitman" data which can be plotted is computed by the function kernel.
The data can be viewed with gnuplot.
The Julia set iteration is:
z= z**2 + C
If it converges, then the initial point z is in the Julia set.
*/
#include <stdio.h>
#include <cuda.h>
#define DIM 1000
__device__ int d_arr[DIM*DIM];
__device__ int julia( int x, int y ) {
const float scale = 1.5;
float jx = scale * (float)(DIM/2 - x)/(DIM/2);
float jy = scale * (float)(DIM/2 - y)/(DIM/2);
float cr=-0.8f;
float ci=0.156f;
float ar=jx;
float ai=jy;
float artmp;
int i = 0;
for (i=0; i<200; i++) {
artmp = ar;
ar =(ar*ar-ai*ai) +cr;
ai = 2.0f*artmp*ai + ci;
if ( (ar*ar+ai*ai) > 1000)
return 0;
}
return 1;
}
/*
void kernel( int *arr ){
for (int y=0; y<DIM; y++) {
for (int x=0; x<DIM; x++) {
int offset = x + y * DIM;
int juliaValue = julia( x, y );
arr[offset] = juliaValue;
}
}
}
*/
__global__ void kernel_gpu(int n){
//for (int y=0; y<DIM; y++) {
// for (int x=0; x<DIM; x++) {
//int offset = x + y * DIM;
//int offset = threadIdx.x+blockDim.x*(blockIdx.x);
int offset =blockIdx.x+n*(blockIdx.y);
//int juliaValue = julia( x, y );
int juliaValue = julia( blockIdx.x, blockIdx.y);
d_arr[offset] = juliaValue;
// }
//}
}
int main( void ) {
int h_arr[DIM*DIM];
// __device__ int d_arr[DIM*DIM];
FILE *out;
int n =DIM*DIM;
int blockSize;
// dim3 nBlocks;
size_t memsize;
memsize = n*sizeof(int);
blockSize = 1;
//nBlocks = n / blockSize + (n % blockSize > 0);
dim3 nBlocks(DIM,DIM,1);
kernel_gpu<<<nBlocks,blockSize>>>(DIM);
cudaMemcpy(h_arr,d_arr,memsize,cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
out = fopen( "julia_gpu.dat", "w" );
for (int y=0; y<DIM; y++) {
for (int x=0; x<DIM; x++) {
int offset = x + y * DIM;
if(h_arr[offset]==1){
fprintf(out,"%d %d \n",x,y); }
}
}
fclose(out);
} | code for sm_80
Function : _Z10kernel_gpui
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0.87646484375, 0.000785350799560546875 ; /* 0x3b03126fff077435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R5, 0x43fa0000 ; /* 0x43fa000000057802 */
/* 0x000fe40000000f00 */
/*0040*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e6e0000002600 */
/*0050*/ FFMA R0, R7, -R5, 1 ; /* 0x3f80000007007423 */
/* 0x000fc80000000805 */
/*0060*/ FFMA R7, R0, R7, 0.0020000000949949026108 ; /* 0x3b03126f00077423 */
/* 0x000fe20000000007 */
/*0070*/ IADD3 R2, -R10, 0x1f4, RZ ; /* 0x000001f40a027810 */
/* 0x001fe20007ffe1ff */
/*0080*/ IMAD R0, R3, c[0x0][0x160], R10 ; /* 0x0000580003007a24 */
/* 0x002fca00078e020a */
/*0090*/ I2F R2, R2 ; /* 0x0000000200027306 */
/* 0x000e240000201400 */
/*00a0*/ FMUL R4, R2, 1.5 ; /* 0x3fc0000002047820 */
/* 0x001fcc0000400000 */
/*00b0*/ FCHK P0, R4, 500 ; /* 0x43fa000004007902 */
/* 0x000e220000000000 */
/*00c0*/ FFMA R6, R4, R7, RZ ; /* 0x0000000704067223 */
/* 0x000fc800000000ff */
/*00d0*/ FFMA R8, R6, -500, R4 ; /* 0xc3fa000006087823 */
/* 0x000fc80000000004 */
/*00e0*/ FFMA R2, R7, R8, R6 ; /* 0x0000000807027223 */
/* 0x000fe20000000006 */
/*00f0*/ @!P0 BRA 0x140 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*0100*/ MOV R10, R4 ; /* 0x00000004000a7202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R4, 0x130 ; /* 0x0000013000047802 */
/* 0x000fe40000000f00 */
/*0120*/ CALL.REL.NOINC 0xd90 ; /* 0x00000c6000007944 */
/* 0x000fea0003c00000 */
/*0130*/ MOV R2, R6 ; /* 0x0000000600027202 */
/* 0x000fe40000000f00 */
/*0140*/ IADD3 R3, -R3, 0x1f4, RZ ; /* 0x000001f403037810 */
/* 0x000fe40007ffe1ff */
/*0150*/ MOV R6, 0x3b03126f ; /* 0x3b03126f00067802 */
/* 0x000fe40000000f00 */
/*0160*/ MOV R5, 0x43fa0000 ; /* 0x43fa000000057802 */
/* 0x000fe40000000f00 */
/*0170*/ I2F R3, R3 ; /* 0x0000000300037306 */
/* 0x000e260000201400 */
/*0180*/ FFMA R7, R6, -R5, 1 ; /* 0x3f80000006077423 */
/* 0x000fc80000000805 */
/*0190*/ FFMA R9, R7, R6, 0.0020000000949949026108 ; /* 0x3b03126f07097423 */
/* 0x000fe40000000006 */
/*01a0*/ FMUL R4, R3, 1.5 ; /* 0x3fc0000003047820 */
/* 0x001fc80000400000 */
/*01b0*/ FCHK P0, R4, 500 ; /* 0x43fa000004007902 */
/* 0x000e220000000000 */
/*01c0*/ FFMA R7, R9, R4, RZ ; /* 0x0000000409077223 */
/* 0x000fc800000000ff */
/*01d0*/ FFMA R6, R7, -500, R4 ; /* 0xc3fa000007067823 */
/* 0x000fc80000000004 */
/*01e0*/ FFMA R6, R9, R6, R7 ; /* 0x0000000609067223 */
/* 0x000fe20000000007 */
/*01f0*/ @!P0 BRA 0x230 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0200*/ MOV R10, R4 ; /* 0x00000004000a7202 */
/* 0x000fe40000000f00 */
/*0210*/ MOV R4, 0x230 ; /* 0x0000023000047802 */
/* 0x000fe40000000f00 */
/*0220*/ CALL.REL.NOINC 0xd90 ; /* 0x00000b6000007944 */
/* 0x000fea0003c00000 */
/*0230*/ FMUL R3, R6, R6 ; /* 0x0000000606037220 */
/* 0x000fe20000400000 */
/*0240*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0250*/ FADD R5, R2.reuse, R2 ; /* 0x0000000202057221 */
/* 0x040fe40000000000 */
/*0260*/ FFMA R3, R2, R2, -R3 ; /* 0x0000000202037223 */
/* 0x000fe40000000803 */
/*0270*/ FFMA R5, R5, R6, 0.15600000321865081787 ; /* 0x3e1fbe7705057423 */
/* 0x000fe40000000006 */
/*0280*/ FADD R3, R3, -0.80000001192092895508 ; /* 0xbf4ccccd03037421 */
/* 0x000fc40000000000 */
/*0290*/ FMUL R7, R5, R5 ; /* 0x0000000505077220 */
/* 0x000fe40000400000 */
/*02a0*/ FMUL R4, R3, R3 ; /* 0x0000000303047220 */
/* 0x000fc80000400000 */
/*02b0*/ FADD R2, R4, R7 ; /* 0x0000000704027221 */
/* 0x000fca0000000000 */
/*02c0*/ FSETP.GT.AND P0, PT, R2, 1000, PT ; /* 0x447a00000200780b */
/* 0x000fe20003f04000 */
/*02d0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fd800000001ff */
/*02e0*/ @P0 BRA 0xd50 ; /* 0x00000a6000000947 */
/* 0x000fea0003800000 */
/*02f0*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fe40000000f00 */
/*0300*/ FADD R4, -R7, R4 ; /* 0x0000000407047221 */
/* 0x000fe40000000100 */
/*0310*/ FADD R2, R3, R3 ; /* 0x0000000303027221 */
/* 0x000fe40000000000 */
/*0320*/ FADD R4, R4, -0.80000001192092895508 ; /* 0xbf4ccccd04047421 */
/* 0x000fe40000000000 */
/*0330*/ FFMA R8, R2, R5, 0.15600000321865081787 ; /* 0x3e1fbe7702087423 */
/* 0x000fe40000000005 */
/*0340*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fe40000400000 */
/*0350*/ FMUL R10, R8, R8 ; /* 0x00000008080a7220 */
/* 0x000fc80000400000 */
/*0360*/ FADD R2, R3, R10 ; /* 0x0000000a03027221 */
/* 0x000fca0000000000 */
/*0370*/ FSETP.GT.AND P0, PT, R2, 1000, PT ; /* 0x447a00000200780b */
/* 0x000fe20003f04000 */
/*0380*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fd800000001ff */
/*0390*/ @P0 BRA 0xd50 ; /* 0x000009b000000947 */
/* 0x000fea0003800000 */
/*03a0*/ FADD R2, R3, -R10 ; /* 0x8000000a03027221 */
/* 0x000fe40000000000 */
/*03b0*/ FADD R3, R4, R4 ; /* 0x0000000404037221 */
/* 0x000fe40000000000 */
/*03c0*/ FADD R4, R2, -0.80000001192092895508 ; /* 0xbf4ccccd02047421 */
/* 0x000fe40000000000 */
/*03d0*/ FFMA R8, R8, R3, 0.15600000321865081787 ; /* 0x3e1fbe7708087423 */
/* 0x000fe40000000003 */
/*03e0*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fe40000400000 */
/*03f0*/ FMUL R10, R8, R8 ; /* 0x00000008080a7220 */
/* 0x000fc80000400000 */
/*0400*/ FADD R2, R3, R10 ; /* 0x0000000a03027221 */
/* 0x000fca0000000000 */
/*0410*/ FSETP.GT.AND P0, PT, R2, 1000, PT ; /* 0x447a00000200780b */
/* 0x000fe40003f04000 */
/*0420*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd60000000f00 */
/*0430*/ @P0 BRA 0xd50 ; /* 0x0000091000000947 */
/* 0x000fea0003800000 */
/*0440*/ FADD R2, R3, -R10 ; /* 0x8000000a03027221 */
/* 0x000fe40000000000 */
/*0450*/ FADD R3, R4, R4 ; /* 0x0000000404037221 */
/* 0x000fe40000000000 */
/*0460*/ FADD R4, R2, -0.80000001192092895508 ; /* 0xbf4ccccd02047421 */
/* 0x000fe40000000000 */
/*0470*/ FFMA R8, R8, R3, 0.15600000321865081787 ; /* 0x3e1fbe7708087423 */
/* 0x000fe40000000003 */
/*0480*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fe40000400000 */
/*0490*/ FMUL R10, R8, R8 ; /* 0x00000008080a7220 */
/* 0x000fc80000400000 */
/*04a0*/ FADD R2, R3, R10 ; /* 0x0000000a03027221 */
/* 0x000fca0000000000 */
/*04b0*/ FSETP.GT.AND P0, PT, R2, 1000, PT ; /* 0x447a00000200780b */
/* 0x000fe40003f04000 */
/*04c0*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd60000000f00 */
/*04d0*/ @P0 BRA 0xd50 ; /* 0x0000087000000947 */
/* 0x000fea0003800000 */
/*04e0*/ FADD R2, R3, -R10 ; /* 0x8000000a03027221 */
/* 0x000fe40000000000 */
/*04f0*/ FADD R3, R4, R4 ; /* 0x0000000404037221 */
/* 0x000fe40000000000 */
/*0500*/ FADD R4, R2, -0.80000001192092895508 ; /* 0xbf4ccccd02047421 */
/* 0x000fe40000000000 */
/*0510*/ FFMA R8, R8, R3, 0.15600000321865081787 ; /* 0x3e1fbe7708087423 */
/* 0x000fe40000000003 */
/*0520*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fe40000400000 */
/*0530*/ FMUL R10, R8, R8 ; /* 0x00000008080a7220 */
/* 0x000fc80000400000 */
/*0540*/ FADD R2, R3, R10 ; /* 0x0000000a03027221 */
/* 0x000fca0000000000 */
/*0550*/ FSETP.GT.AND P0, PT, R2, 1000, PT ; /* 0x447a00000200780b */
/* 0x000fe20003f04000 */
/*0560*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fd800000001ff */
/*0570*/ @P0 BRA 0xd50 ; /* 0x000007d000000947 */
/* 0x000fea0003800000 */
/*0580*/ FADD R2, R3, -R10 ; /* 0x8000000a03027221 */
/* 0x000fe40000000000 */
/*0590*/ FADD R3, R4, R4 ; /* 0x0000000404037221 */
/* 0x000fe40000000000 */
/*05a0*/ FADD R4, R2, -0.80000001192092895508 ; /* 0xbf4ccccd02047421 */
/* 0x000fe40000000000 */
/*05b0*/ FFMA R8, R8, R3, 0.15600000321865081787 ; /* 0x3e1fbe7708087423 */
/* 0x000fe40000000003 */
/*05c0*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fe40000400000 */
/*05d0*/ FMUL R10, R8, R8 ; /* 0x00000008080a7220 */
/* 0x000fc80000400000 */
/*05e0*/ FADD R2, R3, R10 ; /* 0x0000000a03027221 */
/* 0x000fca0000000000 */
/*05f0*/ FSETP.GT.AND P0, PT, R2, 1000, PT ; /* 0x447a00000200780b */
/* 0x000fe40003f04000 */
/*0600*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd60000000f00 */
/*0610*/ @P0 BRA 0xd50 ; /* 0x0000073000000947 */
/* 0x000fea0003800000 */
/*0620*/ FADD R2, R3, -R10 ; /* 0x8000000a03027221 */
/* 0x000fe40000000000 */
/*0630*/ FADD R3, R4, R4 ; /* 0x0000000404037221 */
/* 0x000fe40000000000 */
/*0640*/ FADD R4, R2, -0.80000001192092895508 ; /* 0xbf4ccccd02047421 */
/* 0x000fe40000000000 */
/*0650*/ FFMA R8, R8, R3, 0.15600000321865081787 ; /* 0x3e1fbe7708087423 */
/* 0x000fe40000000003 */
/*0660*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fe40000400000 */
/*0670*/ FMUL R10, R8, R8 ; /* 0x00000008080a7220 */
/* 0x000fc80000400000 */
/*0680*/ FADD R2, R3, R10 ; /* 0x0000000a03027221 */
/* 0x000fca0000000000 */
/*0690*/ FSETP.GT.AND P0, PT, R2, 1000, PT ; /* 0x447a00000200780b */
/* 0x000fe40003f04000 */
/*06a0*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd60000000f00 */
/*06b0*/ @P0 BRA 0xd50 ; /* 0x0000069000000947 */
/* 0x000fea0003800000 */
/*06c0*/ FADD R2, R3, -R10 ; /* 0x8000000a03027221 */
/* 0x000fe40000000000 */
/*06d0*/ FADD R3, R4, R4 ; /* 0x0000000404037221 */
/* 0x000fe40000000000 */
/*06e0*/ FADD R4, R2, -0.80000001192092895508 ; /* 0xbf4ccccd02047421 */
/* 0x000fe40000000000 */
/*06f0*/ FFMA R8, R8, R3, 0.15600000321865081787 ; /* 0x3e1fbe7708087423 */
/* 0x000fe40000000003 */
/*0700*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fe40000400000 */
/*0710*/ FMUL R10, R8, R8 ; /* 0x00000008080a7220 */
/* 0x000fc80000400000 */
/*0720*/ FADD R2, R3, R10 ; /* 0x0000000a03027221 */
/* 0x000fca0000000000 */
/*0730*/ FSETP.GT.AND P0, PT, R2, 1000, PT ; /* 0x447a00000200780b */
/* 0x000fe20003f04000 */
/*0740*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fd800000001ff */
/*0750*/ @P0 BRA 0xd50 ; /* 0x000005f000000947 */
/* 0x000fea0003800000 */
/*0760*/ IADD3 R2, R6, 0x8, RZ ; /* 0x0000000806027810 */
/* 0x000fc80007ffe0ff */
/*0770*/ ISETP.GT.U32.AND P0, PT, R2, 0xc7, PT ; /* 0x000000c70200780c */
/* 0x000fe40003f04070 */
/*0780*/ MOV R2, 0x1 ; /* 0x0000000100027802 */
/* 0x000fd60000000f00 */
/*0790*/ @P0 BRA 0xd50 ; /* 0x000005b000000947 */
/* 0x000fea0003800000 */
/*07a0*/ FADD R2, R3, -R10 ; /* 0x8000000a03027221 */
/* 0x000fe40000000000 */
/*07b0*/ FADD R3, R4, R4 ; /* 0x0000000404037221 */
/* 0x000fe40000000000 */
/*07c0*/ FADD R4, R2, -0.80000001192092895508 ; /* 0xbf4ccccd02047421 */
/* 0x000fe40000000000 */
/*07d0*/ FFMA R8, R8, R3, 0.15600000321865081787 ; /* 0x3e1fbe7708087423 */
/* 0x000fe40000000003 */
/*07e0*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fe40000400000 */
/*07f0*/ FMUL R10, R8, R8 ; /* 0x00000008080a7220 */
/* 0x000fc80000400000 */
/*0800*/ FADD R2, R3, R10 ; /* 0x0000000a03027221 */
/* 0x000fca0000000000 */
/*0810*/ FSETP.GT.AND P0, PT, R2, 1000, PT ; /* 0x447a00000200780b */
/* 0x000fe40003f04000 */
/*0820*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd60000000f00 */
/*0830*/ @P0 BRA 0xd50 ; /* 0x0000051000000947 */
/* 0x000fea0003800000 */
/*0840*/ FADD R2, R3, -R10 ; /* 0x8000000a03027221 */
/* 0x000fe40000000000 */
/*0850*/ FADD R3, R4, R4 ; /* 0x0000000404037221 */
/* 0x000fe40000000000 */
/*0860*/ FADD R4, R2, -0.80000001192092895508 ; /* 0xbf4ccccd02047421 */
/* 0x000fe40000000000 */
/*0870*/ FFMA R8, R8, R3, 0.15600000321865081787 ; /* 0x3e1fbe7708087423 */
/* 0x000fe40000000003 */
/*0880*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fe40000400000 */
/*0890*/ FMUL R10, R8, R8 ; /* 0x00000008080a7220 */
/* 0x000fc80000400000 */
/*08a0*/ FADD R2, R3, R10 ; /* 0x0000000a03027221 */
/* 0x000fca0000000000 */
/*08b0*/ FSETP.GT.AND P0, PT, R2, 1000, PT ; /* 0x447a00000200780b */
/* 0x000fe20003f04000 */
/*08c0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fd800000001ff */
/*08d0*/ @P0 BRA 0xd50 ; /* 0x0000047000000947 */
/* 0x000fea0003800000 */
/*08e0*/ FADD R2, R3, -R10 ; /* 0x8000000a03027221 */
/* 0x000fe40000000000 */
/*08f0*/ FADD R3, R4, R4 ; /* 0x0000000404037221 */
/* 0x000fe40000000000 */
/*0900*/ FADD R4, R2, -0.80000001192092895508 ; /* 0xbf4ccccd02047421 */
/* 0x000fe40000000000 */
/*0910*/ FFMA R8, R8, R3, 0.15600000321865081787 ; /* 0x3e1fbe7708087423 */
/* 0x000fe40000000003 */
/*0920*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fe40000400000 */
/*0930*/ FMUL R10, R8, R8 ; /* 0x00000008080a7220 */
/* 0x000fc80000400000 */
/*0940*/ FADD R2, R3, R10 ; /* 0x0000000a03027221 */
/* 0x000fca0000000000 */
/*0950*/ FSETP.GT.AND P0, PT, R2, 1000, PT ; /* 0x447a00000200780b */
/* 0x000fe40003f04000 */
/*0960*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd60000000f00 */
/*0970*/ @P0 BRA 0xd50 ; /* 0x000003d000000947 */
/* 0x000fea0003800000 */
/*0980*/ FADD R2, R3, -R10 ; /* 0x8000000a03027221 */
/* 0x000fe40000000000 */
/*0990*/ FADD R3, R4, R4 ; /* 0x0000000404037221 */
/* 0x000fe40000000000 */
/*09a0*/ FADD R4, R2, -0.80000001192092895508 ; /* 0xbf4ccccd02047421 */
/* 0x000fe40000000000 */
/*09b0*/ FFMA R8, R8, R3, 0.15600000321865081787 ; /* 0x3e1fbe7708087423 */
/* 0x000fe40000000003 */
/*09c0*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fe40000400000 */
/*09d0*/ FMUL R10, R8, R8 ; /* 0x00000008080a7220 */
/* 0x000fc80000400000 */
/*09e0*/ FADD R2, R3, R10 ; /* 0x0000000a03027221 */
/* 0x000fca0000000000 */
/*09f0*/ FSETP.GT.AND P0, PT, R2, 1000, PT ; /* 0x447a00000200780b */
/* 0x000fe40003f04000 */
/*0a00*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd60000000f00 */
/*0a10*/ @P0 BRA 0xd50 ; /* 0x0000033000000947 */
/* 0x000fea0003800000 */
/*0a20*/ FADD R2, R3, -R10 ; /* 0x8000000a03027221 */
/* 0x000fe40000000000 */
/*0a30*/ FADD R3, R4, R4 ; /* 0x0000000404037221 */
/* 0x000fe40000000000 */
/*0a40*/ FADD R4, R2, -0.80000001192092895508 ; /* 0xbf4ccccd02047421 */
/* 0x000fe40000000000 */
/*0a50*/ FFMA R8, R8, R3, 0.15600000321865081787 ; /* 0x3e1fbe7708087423 */
/* 0x000fe40000000003 */
/*0a60*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fe40000400000 */
/*0a70*/ FMUL R10, R8, R8 ; /* 0x00000008080a7220 */
/* 0x000fc80000400000 */
/*0a80*/ FADD R2, R3, R10 ; /* 0x0000000a03027221 */
/* 0x000fca0000000000 */
/*0a90*/ FSETP.GT.AND P0, PT, R2, 1000, PT ; /* 0x447a00000200780b */
/* 0x000fe20003f04000 */
/*0aa0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fd800000001ff */
/*0ab0*/ @P0 BRA 0xd50 ; /* 0x0000029000000947 */
/* 0x000fea0003800000 */
/*0ac0*/ FADD R2, R3, -R10 ; /* 0x8000000a03027221 */
/* 0x000fe40000000000 */
/*0ad0*/ FADD R3, R4, R4 ; /* 0x0000000404037221 */
/* 0x000fe40000000000 */
/*0ae0*/ FADD R4, R2, -0.80000001192092895508 ; /* 0xbf4ccccd02047421 */
/* 0x000fe40000000000 */
/*0af0*/ FFMA R8, R8, R3, 0.15600000321865081787 ; /* 0x3e1fbe7708087423 */
/* 0x000fe40000000003 */
/*0b00*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fe40000400000 */
/*0b10*/ FMUL R10, R8, R8 ; /* 0x00000008080a7220 */
/* 0x000fc80000400000 */
/*0b20*/ FADD R2, R3, R10 ; /* 0x0000000a03027221 */
/* 0x000fca0000000000 */
/*0b30*/ FSETP.GT.AND P0, PT, R2, 1000, PT ; /* 0x447a00000200780b */
/* 0x000fe40003f04000 */
/*0b40*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd60000000f00 */
/*0b50*/ @P0 BRA 0xd50 ; /* 0x000001f000000947 */
/* 0x000fea0003800000 */
/*0b60*/ FADD R2, R3, -R10 ; /* 0x8000000a03027221 */
/* 0x000fe40000000000 */
/*0b70*/ FADD R3, R4, R4 ; /* 0x0000000404037221 */
/* 0x000fe40000000000 */
/*0b80*/ FADD R4, R2, -0.80000001192092895508 ; /* 0xbf4ccccd02047421 */
/* 0x000fe40000000000 */
/*0b90*/ FFMA R8, R8, R3, 0.15600000321865081787 ; /* 0x3e1fbe7708087423 */
/* 0x000fe40000000003 */
/*0ba0*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fe40000400000 */
/*0bb0*/ FMUL R10, R8, R8 ; /* 0x00000008080a7220 */
/* 0x000fc80000400000 */
/*0bc0*/ FADD R2, R3, R10 ; /* 0x0000000a03027221 */
/* 0x000fca0000000000 */
/*0bd0*/ FSETP.GT.AND P0, PT, R2, 1000, PT ; /* 0x447a00000200780b */
/* 0x000fe40003f04000 */
/*0be0*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd60000000f00 */
/*0bf0*/ @P0 BRA 0xd50 ; /* 0x0000015000000947 */
/* 0x000fea0003800000 */
/*0c00*/ FADD R2, R3, -R10 ; /* 0x8000000a03027221 */
/* 0x000fe40000000000 */
/*0c10*/ FADD R3, R4, R4 ; /* 0x0000000404037221 */
/* 0x000fe40000000000 */
/*0c20*/ FADD R7, R2, -0.80000001192092895508 ; /* 0xbf4ccccd02077421 */
/* 0x000fe40000000000 */
/*0c30*/ FFMA R3, R8, R3, 0.15600000321865081787 ; /* 0x3e1fbe7708037423 */
/* 0x000fe40000000003 */
/*0c40*/ FMUL R2, R7, R7 ; /* 0x0000000707027220 */
/* 0x000fc80000400000 */
/*0c50*/ FFMA R2, R3, R3, R2 ; /* 0x0000000303027223 */
/* 0x000fca0000000002 */
/*0c60*/ FSETP.GT.AND P0, PT, R2, 1000, PT ; /* 0x447a00000200780b */
/* 0x000fe20003f04000 */
/*0c70*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fd800000001ff */
/*0c80*/ @P0 BRA 0xd50 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*0c90*/ FMUL R2, R3, R3 ; /* 0x0000000303027220 */
/* 0x000fe20000400000 */
/*0ca0*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe20007ffe0ff */
/*0cb0*/ FADD R5, R7.reuse, R7 ; /* 0x0000000707057221 */
/* 0x040fe40000000000 */
/*0cc0*/ FFMA R2, R7, R7, -R2 ; /* 0x0000000707027223 */
/* 0x000fe40000000802 */
/*0cd0*/ FFMA R5, R3, R5, 0.15600000321865081787 ; /* 0x3e1fbe7703057423 */
/* 0x000fe40000000005 */
/*0ce0*/ FADD R3, R2, -0.80000001192092895508 ; /* 0xbf4ccccd02037421 */
/* 0x000fe40000000000 */
/*0cf0*/ FMUL R7, R5, R5 ; /* 0x0000000505077220 */
/* 0x000fc40000400000 */
/*0d00*/ FMUL R4, R3, R3 ; /* 0x0000000303047220 */
/* 0x000fc80000400000 */
/*0d10*/ FADD R2, R4, R7 ; /* 0x0000000704027221 */
/* 0x000fca0000000000 */
/*0d20*/ FSETP.GT.AND P0, PT, R2, 1000, PT ; /* 0x447a00000200780b */
/* 0x000fda0003f04000 */
/*0d30*/ @!P0 BRA 0x300 ; /* 0xfffff5c000008947 */
/* 0x000fea000383ffff */
/*0d40*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fe40000000f00 */
/*0d50*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fca0000000f00 */
/*0d60*/ IMAD.WIDE R4, R0, R5, c[0x4][0x0] ; /* 0x0100000000047625 */
/* 0x000fca00078e0205 */
/*0d70*/ STG.E [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x000fe2000c101904 */
/*0d80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d90*/ SHF.R.U32.HI R7, RZ, 0x17, R5 ; /* 0x00000017ff077819 */
/* 0x000fe40000011605 */
/*0da0*/ SHF.R.U32.HI R6, RZ, 0x17, R10 ; /* 0x00000017ff067819 */
/* 0x000fe4000001160a */
/*0db0*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fe400078ec0ff */
/*0dc0*/ LOP3.LUT R9, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06097812 */
/* 0x000fe400078ec0ff */
/*0dd0*/ IADD3 R11, R7, -0x1, RZ ; /* 0xffffffff070b7810 */
/* 0x000fe40007ffe0ff */
/*0de0*/ IADD3 R12, R9, -0x1, RZ ; /* 0xffffffff090c7810 */
/* 0x000fc40007ffe0ff */
/*0df0*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fe40003f04070 */
/*0e00*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe40000000f00 */
/*0e10*/ ISETP.GT.U32.OR P0, PT, R12, 0xfd, P0 ; /* 0x000000fd0c00780c */
/* 0x000fda0000704470 */
/*0e20*/ @!P0 MOV R8, RZ ; /* 0x000000ff00088202 */
/* 0x000fe20000000f00 */
/*0e30*/ @!P0 BRA 0xfb0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0e40*/ FSETP.GTU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fe40003f1c200 */
/*0e50*/ FSETP.GTU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fc80003f3c200 */
/*0e60*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0e70*/ @P0 BRA 0x1390 ; /* 0x0000051000000947 */
/* 0x000fea0003800000 */
/*0e80*/ LOP3.LUT P0, RZ, R5, 0x7fffffff, R6, 0xc8, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fda000780c806 */
/*0e90*/ @!P0 BRA 0x1370 ; /* 0x000004d000008947 */
/* 0x000fea0003800000 */
/*0ea0*/ FSETP.NEU.FTZ.AND P2, PT, |R10|.reuse, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x040fe40003f5d200 */
/*0eb0*/ FSETP.NEU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f3d200 */
/*0ec0*/ FSETP.NEU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fd60003f1d200 */
/*0ed0*/ @!P1 BRA !P2, 0x1370 ; /* 0x0000049000009947 */
/* 0x000fea0005000000 */
/*0ee0*/ LOP3.LUT P2, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000784c0ff */
/*0ef0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0f00*/ @P1 BRA 0x1350 ; /* 0x0000044000001947 */
/* 0x000fea0003800000 */
/*0f10*/ LOP3.LUT P1, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000782c0ff */
/*0f20*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0f30*/ @P0 BRA 0x1320 ; /* 0x000003e000000947 */
/* 0x000fea0003800000 */
/*0f40*/ ISETP.GE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f06270 */
/*0f50*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*0f60*/ @P0 MOV R8, RZ ; /* 0x000000ff00080202 */
/* 0x000fe20000000f00 */
/*0f70*/ @!P0 FFMA R6, R10, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000a068823 */
/* 0x000fe200000000ff */
/*0f80*/ @!P0 MOV R8, 0xffffffc0 ; /* 0xffffffc000088802 */
/* 0x000fe20000000f00 */
/*0f90*/ @!P1 FFMA R5, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005059823 */
/* 0x000fc600000000ff */
/*0fa0*/ @!P1 IADD3 R8, R8, 0x40, RZ ; /* 0x0000004008089810 */
/* 0x000fe40007ffe0ff */
/*0fb0*/ LEA R10, R7, 0xc0800000, 0x17 ; /* 0xc0800000070a7811 */
/* 0x000fe400078eb8ff */
/*0fc0*/ IADD3 R9, R9, -0x7f, RZ ; /* 0xffffff8109097810 */
/* 0x000fe40007ffe0ff */
/*0fd0*/ IADD3 R10, -R10, R5, RZ ; /* 0x000000050a0a7210 */
/* 0x000fe40007ffe1ff */
/*0fe0*/ IADD3 R7, R9.reuse, 0x7f, -R7 ; /* 0x0000007f09077810 */
/* 0x040fe20007ffe807 */
/*0ff0*/ IMAD R6, R9, -0x800000, R6 ; /* 0xff80000009067824 */
/* 0x000fe200078e0206 */
/*1000*/ MUFU.RCP R5, R10 ; /* 0x0000000a00057308 */
/* 0x000e220000001000 */
/*1010*/ FADD.FTZ R11, -R10, -RZ ; /* 0x800000ff0a0b7221 */
/* 0x000fe20000010100 */
/*1020*/ IADD3 R7, R7, R8, RZ ; /* 0x0000000807077210 */
/* 0x000fc60007ffe0ff */
/*1030*/ FFMA R12, R5, R11, 1 ; /* 0x3f800000050c7423 */
/* 0x001fc8000000000b */
/*1040*/ FFMA R13, R5, R12, R5 ; /* 0x0000000c050d7223 */
/* 0x000fc80000000005 */
/*1050*/ FFMA R5, R6, R13, RZ ; /* 0x0000000d06057223 */
/* 0x000fc800000000ff */
/*1060*/ FFMA R12, R11, R5, R6 ; /* 0x000000050b0c7223 */
/* 0x000fc80000000006 */
/*1070*/ FFMA R12, R13, R12, R5 ; /* 0x0000000c0d0c7223 */
/* 0x000fc80000000005 */
/*1080*/ FFMA R11, R11, R12, R6 ; /* 0x0000000c0b0b7223 */
/* 0x000fc80000000006 */
/*1090*/ FFMA R5, R13, R11, R12 ; /* 0x0000000b0d057223 */
/* 0x000fca000000000c */
/*10a0*/ SHF.R.U32.HI R6, RZ, 0x17, R5 ; /* 0x00000017ff067819 */
/* 0x000fc80000011605 */
/*10b0*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fc800078ec0ff */
/*10c0*/ IADD3 R10, R6, R7, RZ ; /* 0x00000007060a7210 */
/* 0x000fc80007ffe0ff */
/*10d0*/ IADD3 R6, R10, -0x1, RZ ; /* 0xffffffff0a067810 */
/* 0x000fc80007ffe0ff */
/*10e0*/ ISETP.GE.U32.AND P0, PT, R6, 0xfe, PT ; /* 0x000000fe0600780c */
/* 0x000fda0003f06070 */
/*10f0*/ @!P0 BRA 0x1300 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*1100*/ ISETP.GT.AND P0, PT, R10, 0xfe, PT ; /* 0x000000fe0a00780c */
/* 0x000fda0003f04270 */
/*1110*/ @P0 BRA 0x12d0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*1120*/ ISETP.GE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fda0003f06270 */
/*1130*/ @P0 BRA 0x13a0 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*1140*/ ISETP.GE.AND P0, PT, R10, -0x18, PT ; /* 0xffffffe80a00780c */
/* 0x000fe40003f06270 */
/*1150*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fd600078ec0ff */
/*1160*/ @!P0 BRA 0x13a0 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*1170*/ FFMA.RZ R6, R13.reuse, R11.reuse, R12.reuse ; /* 0x0000000b0d067223 */
/* 0x1c0fe2000000c00c */
/*1180*/ IADD3 R9, R10.reuse, 0x20, RZ ; /* 0x000000200a097810 */
/* 0x040fe20007ffe0ff */
/*1190*/ FFMA.RM R7, R13.reuse, R11.reuse, R12.reuse ; /* 0x0000000b0d077223 */
/* 0x1c0fe2000000400c */
/*11a0*/ ISETP.NE.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f45270 */
/*11b0*/ LOP3.LUT R8, R6, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff06087812 */
/* 0x000fe200078ec0ff */
/*11c0*/ FFMA.RP R6, R13, R11, R12 ; /* 0x0000000b0d067223 */
/* 0x000fe2000000800c */
/*11d0*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f25270 */
/*11e0*/ LOP3.LUT R8, R8, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000008087812 */
/* 0x000fe400078efcff */
/*11f0*/ IADD3 R10, -R10, RZ, RZ ; /* 0x000000ff0a0a7210 */
/* 0x000fc40007ffe1ff */
/*1200*/ SHF.L.U32 R9, R8, R9, RZ ; /* 0x0000000908097219 */
/* 0x000fe400000006ff */
/*1210*/ FSETP.NEU.FTZ.AND P0, PT, R6, R7, PT ; /* 0x000000070600720b */
/* 0x000fe40003f1d000 */
/*1220*/ SEL R7, R10, RZ, P2 ; /* 0x000000ff0a077207 */
/* 0x000fe40001000000 */
/*1230*/ ISETP.NE.AND P1, PT, R9, RZ, P1 ; /* 0x000000ff0900720c */
/* 0x000fe40000f25270 */
/*1240*/ SHF.R.U32.HI R7, RZ, R7, R8 ; /* 0x00000007ff077219 */
/* 0x000fe40000011608 */
/*1250*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*1260*/ SHF.R.U32.HI R9, RZ, 0x1, R7 ; /* 0x00000001ff097819 */
/* 0x000fe40000011607 */
/*1270*/ SEL R6, RZ, 0x1, !P0 ; /* 0x00000001ff067807 */
/* 0x000fc80004000000 */
/*1280*/ LOP3.LUT R6, R6, 0x1, R9, 0xf8, !PT ; /* 0x0000000106067812 */
/* 0x000fc800078ef809 */
/*1290*/ LOP3.LUT R6, R6, R7, RZ, 0xc0, !PT ; /* 0x0000000706067212 */
/* 0x000fc800078ec0ff */
/*12a0*/ IADD3 R6, R9, R6, RZ ; /* 0x0000000609067210 */
/* 0x000fc80007ffe0ff */
/*12b0*/ LOP3.LUT R5, R6, R5, RZ, 0xfc, !PT ; /* 0x0000000506057212 */
/* 0x000fe200078efcff */
/*12c0*/ BRA 0x13a0 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*12d0*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fc800078ec0ff */
/*12e0*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*12f0*/ BRA 0x13a0 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*1300*/ LEA R5, R7, R5, 0x17 ; /* 0x0000000507057211 */
/* 0x000fe200078eb8ff */
/*1310*/ BRA 0x13a0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*1320*/ LOP3.LUT R5, R5, 0x80000000, R6, 0x48, !PT ; /* 0x8000000005057812 */
/* 0x000fc800078e4806 */
/*1330*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*1340*/ BRA 0x13a0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*1350*/ LOP3.LUT R5, R5, 0x80000000, R6, 0x48, !PT ; /* 0x8000000005057812 */
/* 0x000fe200078e4806 */
/*1360*/ BRA 0x13a0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*1370*/ MUFU.RSQ R5, -QNAN ; /* 0xffc0000000057908 */
/* 0x000e220000001400 */
/*1380*/ BRA 0x13a0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1390*/ FADD.FTZ R5, R10, R5 ; /* 0x000000050a057221 */
/* 0x000fca0000010000 */
/*13a0*/ MOV R6, R5 ; /* 0x0000000500067202 */
/* 0x001fe20000000f00 */
/*13b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fcc00000001ff */
/*13c0*/ RET.REL.NODEC R4 0x0 ; /* 0xffffec3004007950 */
/* 0x000fea0003c3ffff */
/*13d0*/ BRA 0x13d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*13e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Code adapted from book "CUDA by Example: An Introduction to General-Purpose GPU Programming"
This code computes a visualization of the Julia set. Two-dimenansional "bitman" data which can be plotted is computed by the function kernel.
The data can be viewed with gnuplot.
The Julia set iteration is:
z= z**2 + C
If it converges, then the initial point z is in the Julia set.
*/
#include <stdio.h>
#include <cuda.h>
#define DIM 1000
__device__ int d_arr[DIM*DIM];
__device__ int julia( int x, int y ) {
const float scale = 1.5;
float jx = scale * (float)(DIM/2 - x)/(DIM/2);
float jy = scale * (float)(DIM/2 - y)/(DIM/2);
float cr=-0.8f;
float ci=0.156f;
float ar=jx;
float ai=jy;
float artmp;
int i = 0;
for (i=0; i<200; i++) {
artmp = ar;
ar =(ar*ar-ai*ai) +cr;
ai = 2.0f*artmp*ai + ci;
if ( (ar*ar+ai*ai) > 1000)
return 0;
}
return 1;
}
/*
void kernel( int *arr ){
for (int y=0; y<DIM; y++) {
for (int x=0; x<DIM; x++) {
int offset = x + y * DIM;
int juliaValue = julia( x, y );
arr[offset] = juliaValue;
}
}
}
*/
__global__ void kernel_gpu(int n){
//for (int y=0; y<DIM; y++) {
// for (int x=0; x<DIM; x++) {
//int offset = x + y * DIM;
//int offset = threadIdx.x+blockDim.x*(blockIdx.x);
int offset =blockIdx.x+n*(blockIdx.y);
//int juliaValue = julia( x, y );
int juliaValue = julia( blockIdx.x, blockIdx.y);
d_arr[offset] = juliaValue;
// }
//}
}
int main( void ) {
int h_arr[DIM*DIM];
// __device__ int d_arr[DIM*DIM];
FILE *out;
int n =DIM*DIM;
int blockSize;
// dim3 nBlocks;
size_t memsize;
memsize = n*sizeof(int);
blockSize = 1;
//nBlocks = n / blockSize + (n % blockSize > 0);
dim3 nBlocks(DIM,DIM,1);
kernel_gpu<<<nBlocks,blockSize>>>(DIM);
cudaMemcpy(h_arr,d_arr,memsize,cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
out = fopen( "julia_gpu.dat", "w" );
for (int y=0; y<DIM; y++) {
for (int x=0; x<DIM; x++) {
int offset = x + y * DIM;
if(h_arr[offset]==1){
fprintf(out,"%d %d \n",x,y); }
}
}
fclose(out);
} | .file "tmpxft_00135164_00000000-6_julia_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5juliaii
.type _Z5juliaii, @function
_Z5juliaii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z5juliaii, .-_Z5juliaii
.globl _Z29__device_stub__Z10kernel_gpuii
.type _Z29__device_stub__Z10kernel_gpuii, @function
_Z29__device_stub__Z10kernel_gpuii:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10kernel_gpui(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z29__device_stub__Z10kernel_gpuii, .-_Z29__device_stub__Z10kernel_gpuii
.globl _Z10kernel_gpui
.type _Z10kernel_gpui, @function
_Z10kernel_gpui:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10kernel_gpuii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10kernel_gpui, .-_Z10kernel_gpui
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "w"
.LC1:
.string "julia_gpu.dat"
.LC2:
.string "%d %d \n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
leaq -3997696(%rsp), %r11
.cfi_def_cfa 11, 3997744
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $2352, %rsp
.cfi_def_cfa_offset 4000096
movq %fs:40, %rax
movq %rax, 4000040(%rsp)
xorl %eax, %eax
movl $1000, 8(%rsp)
movl $1000, 12(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L14:
leaq 32(%rsp), %rbp
movl $2, %ecx
movl $4000000, %edx
leaq _ZL5d_arr(%rip), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %r13
movl $0, %r12d
leaq .LC2(%rip), %r14
jmp .L15
.L22:
movl $1000, %edi
call _Z29__device_stub__Z10kernel_gpuii
jmp .L14
.L16:
addq $1, %rbx
cmpq $1000, %rbx
je .L23
.L17:
cmpl $1, 0(%rbp,%rbx,4)
jne .L16
movl %r12d, %r8d
movl %ebx, %ecx
movq %r14, %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L16
.L23:
addl $1, %r12d
addq $4000, %rbp
cmpl $1000, %r12d
je .L18
.L15:
movl $0, %ebx
jmp .L17
.L18:
movq %r13, %rdi
call fclose@PLT
movq 4000040(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $4000048, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z10kernel_gpui"
.LC4:
.string "d_arr"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kernel_gpui(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4000000, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5d_arr(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL5d_arr
.comm _ZL5d_arr,4000000,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Code adapted from book "CUDA by Example: An Introduction to General-Purpose GPU Programming"
This code computes a visualization of the Julia set. Two-dimenansional "bitman" data which can be plotted is computed by the function kernel.
The data can be viewed with gnuplot.
The Julia set iteration is:
z= z**2 + C
If it converges, then the initial point z is in the Julia set.
*/
#include <stdio.h>
#include <cuda.h>
#define DIM 1000
__device__ int d_arr[DIM*DIM];
__device__ int julia( int x, int y ) {
const float scale = 1.5;
float jx = scale * (float)(DIM/2 - x)/(DIM/2);
float jy = scale * (float)(DIM/2 - y)/(DIM/2);
float cr=-0.8f;
float ci=0.156f;
float ar=jx;
float ai=jy;
float artmp;
int i = 0;
for (i=0; i<200; i++) {
artmp = ar;
ar =(ar*ar-ai*ai) +cr;
ai = 2.0f*artmp*ai + ci;
if ( (ar*ar+ai*ai) > 1000)
return 0;
}
return 1;
}
/*
void kernel( int *arr ){
for (int y=0; y<DIM; y++) {
for (int x=0; x<DIM; x++) {
int offset = x + y * DIM;
int juliaValue = julia( x, y );
arr[offset] = juliaValue;
}
}
}
*/
__global__ void kernel_gpu(int n){
//for (int y=0; y<DIM; y++) {
// for (int x=0; x<DIM; x++) {
//int offset = x + y * DIM;
//int offset = threadIdx.x+blockDim.x*(blockIdx.x);
int offset =blockIdx.x+n*(blockIdx.y);
//int juliaValue = julia( x, y );
int juliaValue = julia( blockIdx.x, blockIdx.y);
d_arr[offset] = juliaValue;
// }
//}
}
int main( void ) {
int h_arr[DIM*DIM];
// __device__ int d_arr[DIM*DIM];
FILE *out;
int n =DIM*DIM;
int blockSize;
// dim3 nBlocks;
size_t memsize;
memsize = n*sizeof(int);
blockSize = 1;
//nBlocks = n / blockSize + (n % blockSize > 0);
dim3 nBlocks(DIM,DIM,1);
kernel_gpu<<<nBlocks,blockSize>>>(DIM);
cudaMemcpy(h_arr,d_arr,memsize,cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
out = fopen( "julia_gpu.dat", "w" );
for (int y=0; y<DIM; y++) {
for (int x=0; x<DIM; x++) {
int offset = x + y * DIM;
if(h_arr[offset]==1){
fprintf(out,"%d %d \n",x,y); }
}
}
fclose(out);
} | /*
Code adapted from book "CUDA by Example: An Introduction to General-Purpose GPU Programming"
This code computes a visualization of the Julia set. Two-dimenansional "bitman" data which can be plotted is computed by the function kernel.
The data can be viewed with gnuplot.
The Julia set iteration is:
z= z**2 + C
If it converges, then the initial point z is in the Julia set.
*/
#include <stdio.h>
#include <hip/hip_runtime.h>
#define DIM 1000
__device__ int d_arr[DIM*DIM];
__device__ int julia( int x, int y ) {
const float scale = 1.5;
float jx = scale * (float)(DIM/2 - x)/(DIM/2);
float jy = scale * (float)(DIM/2 - y)/(DIM/2);
float cr=-0.8f;
float ci=0.156f;
float ar=jx;
float ai=jy;
float artmp;
int i = 0;
for (i=0; i<200; i++) {
artmp = ar;
ar =(ar*ar-ai*ai) +cr;
ai = 2.0f*artmp*ai + ci;
if ( (ar*ar+ai*ai) > 1000)
return 0;
}
return 1;
}
/*
void kernel( int *arr ){
for (int y=0; y<DIM; y++) {
for (int x=0; x<DIM; x++) {
int offset = x + y * DIM;
int juliaValue = julia( x, y );
arr[offset] = juliaValue;
}
}
}
*/
__global__ void kernel_gpu(int n){
//for (int y=0; y<DIM; y++) {
// for (int x=0; x<DIM; x++) {
//int offset = x + y * DIM;
//int offset = threadIdx.x+blockDim.x*(blockIdx.x);
int offset =blockIdx.x+n*(blockIdx.y);
//int juliaValue = julia( x, y );
int juliaValue = julia( blockIdx.x, blockIdx.y);
d_arr[offset] = juliaValue;
// }
//}
}
int main( void ) {
int h_arr[DIM*DIM];
// __device__ int d_arr[DIM*DIM];
FILE *out;
int n =DIM*DIM;
int blockSize;
// dim3 nBlocks;
size_t memsize;
memsize = n*sizeof(int);
blockSize = 1;
//nBlocks = n / blockSize + (n % blockSize > 0);
dim3 nBlocks(DIM,DIM,1);
kernel_gpu<<<nBlocks,blockSize>>>(DIM);
hipMemcpy(h_arr,d_arr,memsize,hipMemcpyDeviceToHost);
hipDeviceSynchronize();
out = fopen( "julia_gpu.dat", "w" );
for (int y=0; y<DIM; y++) {
for (int x=0; x<DIM; x++) {
int offset = x + y * DIM;
if(h_arr[offset]==1){
fprintf(out,"%d %d \n",x,y); }
}
}
fclose(out);
} |
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