system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
// Lets you use the Cuda FFT library
cudaError_t mathWithCuda(float *output, float *input1, float *input2, unsigned int size, int oper);
// Using __global__ to declare function as device code (GPU)
// Do the math inside here:
// Helper function for using CUDA to add vectors in parallel.
__global__ void mathKernel(float *output, float *input1, float *input2, int n, int oper)
{
// Allocate elements to threads
int i = threadIdx.x + blockIdx.x * blockDim.x;
// Avoid access beyond the end of the array
if (i < n)
{
// No for-loop needed, CUDA runtime will thread this
switch (oper)
{
case 1: // Addition
output[i] = input1[i] + input2[i];
break;
case 2: // Subtraction
output[i] = input1[i] - input2[i];
break;
case 3: // Multiplication
output[i] = input1[i] * input2[i];
break;
case 4: // Division
output[i] = input1[i] / input2[i];
break;
// Add more operations here:
case 5:
break;
case 6:
break;
case 7:
break;
default:
return;
}
// Ensure all the data is available
__syncthreads(); // Gives a syntax "error" but this doesn't give build errors
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
// Lets you use the Cuda FFT library
hipError_t mathWithCuda(float *output, float *input1, float *input2, unsigned int size, int oper);
// Using __global__ to declare function as device code (GPU)
// Do the math inside here:
// Helper function for using CUDA to add vectors in parallel.
__global__ void mathKernel(float *output, float *input1, float *input2, int n, int oper)
{
// Allocate elements to threads
int i = threadIdx.x + blockIdx.x * blockDim.x;
// Avoid access beyond the end of the array
if (i < n)
{
// No for-loop needed, CUDA runtime will thread this
switch (oper)
{
case 1: // Addition
output[i] = input1[i] + input2[i];
break;
case 2: // Subtraction
output[i] = input1[i] - input2[i];
break;
case 3: // Multiplication
output[i] = input1[i] * input2[i];
break;
case 4: // Division
output[i] = input1[i] / input2[i];
break;
// Add more operations here:
case 5:
break;
case 6:
break;
case 7:
break;
default:
return;
}
// Ensure all the data is available
__syncthreads(); // Gives a syntax "error" but this doesn't give build errors
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// Lets you use the Cuda FFT library
hipError_t mathWithCuda(float *output, float *input1, float *input2, unsigned int size, int oper);
// Using __global__ to declare function as device code (GPU)
// Do the math inside here:
// Helper function for using CUDA to add vectors in parallel.
__global__ void mathKernel(float *output, float *input1, float *input2, int n, int oper)
{
// Allocate elements to threads
int i = threadIdx.x + blockIdx.x * blockDim.x;
// Avoid access beyond the end of the array
if (i < n)
{
// No for-loop needed, CUDA runtime will thread this
switch (oper)
{
case 1: // Addition
output[i] = input1[i] + input2[i];
break;
case 2: // Subtraction
output[i] = input1[i] - input2[i];
break;
case 3: // Multiplication
output[i] = input1[i] * input2[i];
break;
case 4: // Division
output[i] = input1[i] / input2[i];
break;
// Add more operations here:
case 5:
break;
case 6:
break;
case 7:
break;
default:
return;
}
// Ensure all the data is available
__syncthreads(); // Gives a syntax "error" but this doesn't give build errors
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10mathKernelPfS_S_ii
.globl _Z10mathKernelPfS_S_ii
.p2align 8
.type _Z10mathKernelPfS_S_ii,@function
_Z10mathKernelPfS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_21
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x8
s_mov_b32 s9, -1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 3
s_cbranch_scc1 .LBB0_7
s_cmp_gt_i32 s3, 3
s_cbranch_scc0 .LBB0_8
s_mov_b32 s8, 0
s_cmp_gt_i32 s3, 4
s_mov_b32 s2, 0
s_cbranch_scc0 .LBB0_5
s_cmp_lt_i32 s3, 8
s_mov_b32 s9, 0
s_cselect_b32 s2, -1, 0
.LBB0_5:
s_and_not1_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz .LBB0_10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s8, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v5, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v0, v[5:6], off
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v4, null, v3, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v0, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v5
v_fma_f32 v8, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v5
v_fma_f32 v4, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v4, v4, v5, v7
v_div_fixup_f32 v0, v4, v3, v0
s_branch .LBB0_11
.LBB0_7:
s_mov_b32 s2, 0
s_mov_b32 s8, 0
s_and_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz .LBB0_12
s_branch .LBB0_17
.LBB0_8:
s_mov_b32 s2, 0
s_mov_b32 s8, 0
s_and_b32 vcc_lo, exec_lo, s9
s_cbranch_vccz .LBB0_11
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s8, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v5, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v0, v[5:6], off
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v0, v0, v3
s_branch .LBB0_17
.LBB0_10:
.LBB0_11:
s_branch .LBB0_17
.LBB0_12:
s_cmp_gt_i32 s3, 1
s_cbranch_scc0 .LBB0_14
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s8, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v5, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v0, v[5:6], off
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v0, v0, v3
s_cbranch_execz .LBB0_15
s_branch .LBB0_17
.LBB0_14:
.LBB0_15:
s_cmp_eq_u32 s3, 1
s_cbranch_scc0 .LBB0_22
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s8, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v5, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v0, v[5:6], off
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v3
.LBB0_17:
s_and_b32 vcc_lo, exec_lo, s8
s_cbranch_vccz .LBB0_19
.LBB0_18:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_mov_b32 s2, -1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_19:
s_and_not1_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_21
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB0_21:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_22:
s_and_b32 vcc_lo, exec_lo, s8
s_cbranch_vccnz .LBB0_18
s_branch .LBB0_19
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10mathKernelPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10mathKernelPfS_S_ii, .Lfunc_end0-_Z10mathKernelPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10mathKernelPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10mathKernelPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// Lets you use the Cuda FFT library
hipError_t mathWithCuda(float *output, float *input1, float *input2, unsigned int size, int oper);
// Using __global__ to declare function as device code (GPU)
// Do the math inside here:
// Helper function for using CUDA to add vectors in parallel.
__global__ void mathKernel(float *output, float *input1, float *input2, int n, int oper)
{
// Allocate elements to threads
int i = threadIdx.x + blockIdx.x * blockDim.x;
// Avoid access beyond the end of the array
if (i < n)
{
// No for-loop needed, CUDA runtime will thread this
switch (oper)
{
case 1: // Addition
output[i] = input1[i] + input2[i];
break;
case 2: // Subtraction
output[i] = input1[i] - input2[i];
break;
case 3: // Multiplication
output[i] = input1[i] * input2[i];
break;
case 4: // Division
output[i] = input1[i] / input2[i];
break;
// Add more operations here:
case 5:
break;
case 6:
break;
case 7:
break;
default:
return;
}
// Ensure all the data is available
__syncthreads(); // Gives a syntax "error" but this doesn't give build errors
}
} | .text
.file "mathKernel.hip"
.globl _Z25__device_stub__mathKernelPfS_S_ii # -- Begin function _Z25__device_stub__mathKernelPfS_S_ii
.p2align 4, 0x90
.type _Z25__device_stub__mathKernelPfS_S_ii,@function
_Z25__device_stub__mathKernelPfS_S_ii: # @_Z25__device_stub__mathKernelPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10mathKernelPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__mathKernelPfS_S_ii, .Lfunc_end0-_Z25__device_stub__mathKernelPfS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10mathKernelPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10mathKernelPfS_S_ii,@object # @_Z10mathKernelPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z10mathKernelPfS_S_ii
.p2align 3, 0x0
_Z10mathKernelPfS_S_ii:
.quad _Z25__device_stub__mathKernelPfS_S_ii
.size _Z10mathKernelPfS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10mathKernelPfS_S_ii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__mathKernelPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10mathKernelPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10mathKernelPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff007624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0090*/ ISETP.GT.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f04270 */
/*00a0*/ IMAD.WIDE R4, R2, R3, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x000fc800078e0203 */
/*00b0*/ IMAD.WIDE R6, R2, R3, c[0x0][0x170] ; /* 0x00005c0002067625 */
/* 0x000fc800078e0203 */
/*00c0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0203 */
/*00d0*/ @P0 BRA 0x230 ; /* 0x0000015000000947 */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*00f0*/ IMNMX.U32 R0, R0, 0x3, PT ; /* 0x0000000300007817 */
/* 0x000fca0003800000 */
/*0100*/ IMAD.SHL.U32 R0, R0, 0x4, RZ ; /* 0x0000000400007824 */
/* 0x000fc800078e00ff */
/*0110*/ LDC R8, c[0x2][R0] ; /* 0x0080000000087b82 */
/* 0x000e240000000800 */
/*0120*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x001fc80000011408 */
/*0130*/ BRX R8 -0x140 ; /* 0xfffffec008007949 */
/* 0x000fea000383ffff */
/*0140*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea4000c1e1900 */
/*0160*/ FMUL R9, R4, R7 ; /* 0x0000000704097220 */
/* 0x004fca0000400000 */
/*0170*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e2000c101904 */
/*0180*/ BRA 0x370 ; /* 0x000001e000007947 */
/* 0x000fea0003800000 */
/*0190*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea4000c1e1900 */
/*01b0*/ FADD R9, R4, R7 ; /* 0x0000000704097221 */
/* 0x004fca0000000000 */
/*01c0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e2000c101904 */
/*01d0*/ BRA 0x370 ; /* 0x0000019000007947 */
/* 0x000fea0003800000 */
/*01e0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea4000c1e1900 */
/*0200*/ FADD R9, R4, -R7 ; /* 0x8000000704097221 */
/* 0x004fca0000000000 */
/*0210*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e2000c101904 */
/*0220*/ BRA 0x370 ; /* 0x0000014000007947 */
/* 0x000fea0003800000 */
/*0230*/ IADD3 R8, R0, -0x5, RZ ; /* 0xfffffffb00087810 */
/* 0x000fc80007ffe0ff */
/*0240*/ ISETP.GE.U32.AND P0, PT, R8, 0x3, PT ; /* 0x000000030800780c */
/* 0x000fda0003f06070 */
/*0250*/ @!P0 BRA 0x370 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0260*/ ISETP.NE.AND P0, PT, R0, 0x4, PT ; /* 0x000000040000780c */
/* 0x000fda0003f05270 */
/*0270*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0280*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea8000c1e1900 */
/*0290*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1900 */
/*02a0*/ BSSY B0, 0x360 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*02b0*/ MUFU.RCP R0, R7 ; /* 0x0000000700007308 */
/* 0x004e300000001000 */
/*02c0*/ FCHK P0, R4, R7 ; /* 0x0000000704007302 */
/* 0x008e620000000000 */
/*02d0*/ FFMA R9, -R7, R0, 1 ; /* 0x3f80000007097423 */
/* 0x001fc80000000100 */
/*02e0*/ FFMA R9, R0, R9, R0 ; /* 0x0000000900097223 */
/* 0x000fc80000000000 */
/*02f0*/ FFMA R0, R4, R9, RZ ; /* 0x0000000904007223 */
/* 0x000fc800000000ff */
/*0300*/ FFMA R8, -R7, R0, R4 ; /* 0x0000000007087223 */
/* 0x000fc80000000104 */
/*0310*/ FFMA R9, R9, R8, R0 ; /* 0x0000000809097223 */
/* 0x000fe20000000000 */
/*0320*/ @!P0 BRA 0x350 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*0330*/ MOV R0, 0x350 ; /* 0x0000035000007802 */
/* 0x000fe40000000f00 */
/*0340*/ CALL.REL.NOINC 0x390 ; /* 0x0000004000007944 */
/* 0x000fea0003c00000 */
/*0350*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0360*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e4000c101904 */
/*0370*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0380*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0390*/ SHF.R.U32.HI R6, RZ, 0x17, R7.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011607 */
/*03a0*/ BSSY B1, 0x9f0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*03b0*/ SHF.R.U32.HI R5, RZ, 0x17, R4.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011604 */
/*03c0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*03d0*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe200078ec0ff */
/*03e0*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0007 */
/*03f0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*0400*/ IADD3 R12, R6, -0x1, RZ ; /* 0xffffffff060c7810 */
/* 0x000fe40007ffe0ff */
/*0410*/ IADD3 R11, R5, -0x1, RZ ; /* 0xffffffff050b7810 */
/* 0x000fc40007ffe0ff */
/*0420*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*0430*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*0440*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*0450*/ @!P0 BRA 0x5d0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0460*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f1c200 */
/*0470*/ FSETP.GTU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fc80003f3c200 */
/*0480*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0490*/ @P0 BRA 0x9d0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*04a0*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, R8, 0xc8, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c808 */
/*04b0*/ @!P0 BRA 0x9b0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*04c0*/ FSETP.NEU.FTZ.AND P2, PT, |R4|.reuse, +INF , PT ; /* 0x7f8000000400780b */
/* 0x040fe40003f5d200 */
/*04d0*/ FSETP.NEU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe40003f3d200 */
/*04e0*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fd60003f1d200 */
/*04f0*/ @!P1 BRA !P2, 0x9b0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0500*/ LOP3.LUT P2, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000784c0ff */
/*0510*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0520*/ @P1 BRA 0x990 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0530*/ LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000782c0ff */
/*0540*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0550*/ @P0 BRA 0x960 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0560*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*0570*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0580*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*0590*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*05a0*/ @!P0 FFMA R8, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004088823 */
/* 0x000fe400000000ff */
/*05b0*/ @!P1 FFMA R9, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007099823 */
/* 0x000fe200000000ff */
/*05c0*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*05d0*/ LEA R4, R6, 0xc0800000, 0x17 ; /* 0xc080000006047811 */
/* 0x000fe200078eb8ff */
/*05e0*/ BSSY B2, 0x950 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*05f0*/ IADD3 R5, R5, -0x7f, RZ ; /* 0xffffff8105057810 */
/* 0x000fc60007ffe0ff */
/*0600*/ IMAD.IADD R9, R9, 0x1, -R4 ; /* 0x0000000109097824 */
/* 0x000fe400078e0a04 */
/*0610*/ IMAD R8, R5, -0x800000, R8 ; /* 0xff80000005087824 */
/* 0x000fe400078e0208 */
/*0620*/ MUFU.RCP R4, R9 ; /* 0x0000000900047308 */
/* 0x000e220000001000 */
/*0630*/ FADD.FTZ R7, -R9, -RZ ; /* 0x800000ff09077221 */
/* 0x000fc80000010100 */
/*0640*/ FFMA R11, R4, R7, 1 ; /* 0x3f800000040b7423 */
/* 0x001fc80000000007 */
/*0650*/ FFMA R13, R4, R11, R4 ; /* 0x0000000b040d7223 */
/* 0x000fc80000000004 */
/*0660*/ FFMA R4, R8, R13, RZ ; /* 0x0000000d08047223 */
/* 0x000fc800000000ff */
/*0670*/ FFMA R11, R7, R4, R8 ; /* 0x00000004070b7223 */
/* 0x000fc80000000008 */
/*0680*/ FFMA R12, R13, R11, R4 ; /* 0x0000000b0d0c7223 */
/* 0x000fc80000000004 */
/*0690*/ FFMA R8, R7, R12, R8 ; /* 0x0000000c07087223 */
/* 0x000fe20000000008 */
/*06a0*/ IADD3 R7, R5, 0x7f, -R6 ; /* 0x0000007f05077810 */
/* 0x000fc60007ffe806 */
/*06b0*/ FFMA R4, R13, R8, R12 ; /* 0x000000080d047223 */
/* 0x000fe4000000000c */
/*06c0*/ IMAD.IADD R7, R7, 0x1, R10 ; /* 0x0000000107077824 */
/* 0x000fc600078e020a */
/*06d0*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fc80000011604 */
/*06e0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*06f0*/ IMAD.IADD R9, R5, 0x1, R7 ; /* 0x0000000105097824 */
/* 0x000fca00078e0207 */
/*0700*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*0710*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0720*/ @!P0 BRA 0x930 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0730*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*0740*/ @P0 BRA 0x900 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0750*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*0760*/ @P0 BRA 0x940 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0770*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*0780*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*0790*/ @!P0 BRA 0x940 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*07a0*/ FFMA.RZ R5, R13, R8.reuse, R12.reuse ; /* 0x000000080d057223 */
/* 0x180fe2000000c00c */
/*07b0*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f45270 */
/*07c0*/ FFMA.RM R6, R13, R8.reuse, R12.reuse ; /* 0x000000080d067223 */
/* 0x180fe2000000400c */
/*07d0*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*07e0*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*07f0*/ FFMA.RP R5, R13, R8, R12 ; /* 0x000000080d057223 */
/* 0x000fe2000000800c */
/*0800*/ IADD3 R8, R9, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x000fe20007ffe0ff */
/*0810*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*0820*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*0830*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*0840*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*0850*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*0860*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0870*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*0880*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0890*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*08a0*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*08b0*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*08c0*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*08d0*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fca00078e0205 */
/*08e0*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*08f0*/ BRA 0x940 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0900*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*0910*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0920*/ BRA 0x940 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0930*/ IMAD R4, R7, 0x800000, R4 ; /* 0x0080000007047824 */
/* 0x000fe400078e0204 */
/*0940*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0950*/ BRA 0x9e0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0960*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fc800078e4808 */
/*0970*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0980*/ BRA 0x9e0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0990*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fe200078e4808 */
/*09a0*/ BRA 0x9e0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*09b0*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*09c0*/ BRA 0x9e0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*09d0*/ FADD.FTZ R4, R4, R7 ; /* 0x0000000704047221 */
/* 0x000fe40000010000 */
/*09e0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*09f0*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x001fe400078e0004 */
/*0a00*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0a10*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0a20*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff5d004007950 */
/* 0x000fea0003c3ffff */
/*0a30*/ BRA 0xa30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10mathKernelPfS_S_ii
.globl _Z10mathKernelPfS_S_ii
.p2align 8
.type _Z10mathKernelPfS_S_ii,@function
_Z10mathKernelPfS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_21
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x8
s_mov_b32 s9, -1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 3
s_cbranch_scc1 .LBB0_7
s_cmp_gt_i32 s3, 3
s_cbranch_scc0 .LBB0_8
s_mov_b32 s8, 0
s_cmp_gt_i32 s3, 4
s_mov_b32 s2, 0
s_cbranch_scc0 .LBB0_5
s_cmp_lt_i32 s3, 8
s_mov_b32 s9, 0
s_cselect_b32 s2, -1, 0
.LBB0_5:
s_and_not1_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz .LBB0_10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s8, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v5, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v0, v[5:6], off
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v4, null, v3, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v0, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v5
v_fma_f32 v8, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v5
v_fma_f32 v4, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v4, v4, v5, v7
v_div_fixup_f32 v0, v4, v3, v0
s_branch .LBB0_11
.LBB0_7:
s_mov_b32 s2, 0
s_mov_b32 s8, 0
s_and_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz .LBB0_12
s_branch .LBB0_17
.LBB0_8:
s_mov_b32 s2, 0
s_mov_b32 s8, 0
s_and_b32 vcc_lo, exec_lo, s9
s_cbranch_vccz .LBB0_11
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s8, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v5, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v0, v[5:6], off
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v0, v0, v3
s_branch .LBB0_17
.LBB0_10:
.LBB0_11:
s_branch .LBB0_17
.LBB0_12:
s_cmp_gt_i32 s3, 1
s_cbranch_scc0 .LBB0_14
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s8, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v5, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v0, v[5:6], off
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v0, v0, v3
s_cbranch_execz .LBB0_15
s_branch .LBB0_17
.LBB0_14:
.LBB0_15:
s_cmp_eq_u32 s3, 1
s_cbranch_scc0 .LBB0_22
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s8, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v5, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v0, v[5:6], off
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v3
.LBB0_17:
s_and_b32 vcc_lo, exec_lo, s8
s_cbranch_vccz .LBB0_19
.LBB0_18:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_mov_b32 s2, -1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_19:
s_and_not1_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_21
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB0_21:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_22:
s_and_b32 vcc_lo, exec_lo, s8
s_cbranch_vccnz .LBB0_18
s_branch .LBB0_19
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10mathKernelPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10mathKernelPfS_S_ii, .Lfunc_end0-_Z10mathKernelPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10mathKernelPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10mathKernelPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b258e_00000000-6_mathKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z10mathKernelPfS_S_iiPfS_S_ii
.type _Z36__device_stub__Z10mathKernelPfS_S_iiPfS_S_ii, @function
_Z36__device_stub__Z10mathKernelPfS_S_iiPfS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10mathKernelPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z10mathKernelPfS_S_iiPfS_S_ii, .-_Z36__device_stub__Z10mathKernelPfS_S_iiPfS_S_ii
.globl _Z10mathKernelPfS_S_ii
.type _Z10mathKernelPfS_S_ii, @function
_Z10mathKernelPfS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10mathKernelPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10mathKernelPfS_S_ii, .-_Z10mathKernelPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10mathKernelPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10mathKernelPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mathKernel.hip"
.globl _Z25__device_stub__mathKernelPfS_S_ii # -- Begin function _Z25__device_stub__mathKernelPfS_S_ii
.p2align 4, 0x90
.type _Z25__device_stub__mathKernelPfS_S_ii,@function
_Z25__device_stub__mathKernelPfS_S_ii: # @_Z25__device_stub__mathKernelPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10mathKernelPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__mathKernelPfS_S_ii, .Lfunc_end0-_Z25__device_stub__mathKernelPfS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10mathKernelPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10mathKernelPfS_S_ii,@object # @_Z10mathKernelPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z10mathKernelPfS_S_ii
.p2align 3, 0x0
_Z10mathKernelPfS_S_ii:
.quad _Z25__device_stub__mathKernelPfS_S_ii
.size _Z10mathKernelPfS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10mathKernelPfS_S_ii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__mathKernelPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10mathKernelPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __device__ void color(float r, float g, float b, unsigned char* buffer){
if(r>255)
buffer[0] = 255;
else
buffer[0] = (unsigned char)(r);
if(r>255)
buffer[1] = 255;
else
buffer[1] = (unsigned char)(g);
if(r>255)
buffer[2] = 255;
else
buffer[2] = (unsigned char)(b);
}
__device__ struct mat2{
float N[2];
float M[2];
__device__ mat2(float a, float b, float c, float d)
{
N[0] = a;
N[1] = b;
M[0] = c;
M[1] = d;
}
};
__device__ struct vec2{
float x;
float y;
__device__ vec2 (){}
__device__ vec2 (float x, float y): x(x), y(y){}
__device__ vec2 ( float a): x(a),y(a){}
__device__ vec2 operator+(const vec2& v) const
{
return {v.x+x,v.y+y};
}
__device__ vec2 operator-(const vec2& v) const
{
return {x-v.x,y-v.y};
}
};
//vec2 calculations except operators
__device__ float length(vec2 v){
return sqrt(v.x*v.x + v.y*v.y);}
__device__ float dist(vec2 posa, vec2 posb){
float dx,dy;
dx = posa.x - posb.x;
dy = posa.y -posb.y;
return sqrt(dx*dx + dy*dy);}
__device__ vec2 abs(vec2 v){
return {abs(v.x),abs(v.y)};}
//vec3 can begin
__device__ struct vec3 {
float x;
float y;
float z;
//Constructors in different ways
__device__ vec3 (){}
__device__ vec3 (float x, float y, float z):x(x),y(y),z(z){}
__device__ vec3(float a):x(a),y(a),z(a){}
__device__ vec3(vec2 v, float z):x(v.x),y(v.y),z(z){}
__device__ vec3 operator+(const vec3& a) const{
return {a.x + x, a.y+y, a.z+z};}
__device__ vec3 operator-(const vec3& a) const{
return {x-a.x,y-a.y, z-a.z};}
__device__ vec3 operator*(const vec3& a) const{
return {a.x*x, a.y*y , a.z*z };
}
__device__ vec3 operator*(const float a) const{
return {x*a, y*a, z*a};}
__device__ vec3 operator/(const float a) const{
return {x/a, y/a, z/a};}
};
__device__ vec3 cross(vec3 a, vec3 b){
return {a.y*b.z - b.y * a.z, a.z*b.x - b.z*a.x, a.x*b.y -b.x*a.y};
}
__device__ void color(vec3 c, unsigned char* buffer){
if (c.x < 0)
buffer[0] = 0;
else if (c.x > 255)
buffer[0] = 255;
else
buffer[0] = (unsigned char)(c.x);
if (c.y < 0)
buffer[1] = 0;
else if (c.y > 255)
buffer[1] = 255;
else
buffer[1] = (unsigned char)(c.y);
if (c.z < 0)
buffer[2] = 0;
else if (c.z > 255)
buffer[2] = 255;
else
buffer[2] = (unsigned char)(c.z);
}
__device__ float dot(vec3 a, vec3 b){
return a.x*b.x + a.y*b.y + a.z*b.z;}
// I is the Incident vector (direction) and N the Normal vector of the surface
__device__ vec3 reflect(vec3 I, vec3 N){
return I - N *dot(N,I)*2;
}
//can i put this to perators????
__device__ vec3 abs(vec3 v){
return {abs(v.x),abs(v.y),abs(v.z)};}
__device__ float length(vec3 v){
return sqrt(v.x*v.x + v.y*v.y + v.z*v.z);}
__device__ float dist(vec3 a, vec3 b){
float dx,dy,dz;
dx = a.x-b.x;
dy = a.y-b.y;
dz = a.z-b.z;
return sqrt(dx*dx+dy*dy+dz*dz);}
__device__ vec3 normalize(vec3 v){
float betrag = length(v);
return {v.x/betrag,v.y/betrag,v.z/betrag};}
//not sure about the following 2 formulas, a max between a vector and a float seems weird to me
__device__ float mb(float a, float mx){
return a > mx ? a : mx;
}
__device__ vec3 max(vec3 v, float d){
return {mb(v.x,d),
mb(v.y,d),
mb(v.z,d)};}
//i still wonder what i need a 4th dimension for, but we will see
__device__ struct vec4{
float x;
float y;
float z;
float w;
__device__ vec4(){}
__device__ vec4(float x, float y, float z, float w):x(x),y(y),z(z),w(w){}
__device__ vec4(vec3 v, float w): x(v.x), y(v.y), z(v.y), w(w){}
__device__ vec4(float a):x(a),y(a),z(a),w(a){}
__device__ vec4(vec2 v1, vec2 v2): x(v1.x),y(v1.y),z(v2.x),w(v2.y){}
};
//init global rot variable and the functions to set during runtime
//remember that __host__ function always has to be inside extern "C" to be accessed by C-types
//btw check if there might be a less dirty way to acess the __device__ variable from __host__ function
__device__ unsigned short int rot = 0;
__global__ void rotation(unsigned short int angle){
rot = angle;}
extern "C"{__host__ void rotate(unsigned short int angle){
rotation<<<1,1>>>(angle);}}
//same here with the frame
__device__ float frame = 0;
__device__ float sinfr = 0;
__device__ float cosfr = 0;
__global__ void set_frame_g(unsigned int f){
frame = (float)f;
sinfr = sin(frame*M_PI/180);
cosfr = cos(frame*M_PI/180);}
extern "C"{__host__ void set_frame(unsigned int f){
set_frame_g<<<1,1>>>(f);}}
__device__ vec2 mouse;
__global__ void set_mouse_g(float x, float y){
mouse.x = x*2;
mouse.y = y*2;}
extern "C"{__host__ void set_mouse(float x, float y){
set_mouse_g<<<1,1>>>(x,y);}}
__device__ vec2 window;
__device__ vec2 windowD2;
__global__ void set_window_g(int x, int y){
window.x = (float)(x);
window.y = (float)(y);
windowD2.x = (float)(x)/2;
windowD2.y = (float)(y)/2;}
extern "C"{ __host__ void set_window(int x, int y){
set_window_g<<<1,1>>>(x,y);}}
//nice functionalities for floats to have in Shady programming
__device__ float fract(float f){
return f - floor(f);}
__device__ float step(float a, float b){
if (abs(a) < abs(b))
return 1;
else
return 0;}
__device__ float clamp(float x, float minVal, float maxVal){
return min(max(x,minVal),maxVal);}
__device__ vec2 min(vec2 v1, vec2 v2){
if (v1.x<v2.x)
return v1;
else
return v2;
// vec2.y soll in dem Falle die Variable für "solid/glas/mirror" sein, die abstandtsfunktion und so müssen von float auf vec2 geändert werden
//eine neue Funktion dann auch für raymarch innerhalb glas
// und eine für spiegelung
//alternativ eine raymarch funktion erst für glas, dann für spiegel, dann für solids erstellen
}
__device__ vec2 max(vec2 v1, vec2 v2){
if (v1.x>v2.x)
return v1;
else
return v2;
}
__device__ float mix(float v1,float v2, float a){
return v1* (1-a) + v2*a;}
//define smin for vec2 returns....
__device__ float smin(float a, float b, float k){//smooth min, very nice
float h = clamp(0.5 + 0.5 * (b-a)/k,0.1,1.0);
return mix(b,a,h) - k*h*(1.0-h);} | .file "tmpxft_00169bb5_00000000-6_shader.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2100:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2100:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5colorfffPh
.type _Z5colorfffPh, @function
_Z5colorfffPh:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z5colorfffPh, .-_Z5colorfffPh
.globl _Z6length4vec2
.type _Z6length4vec2, @function
_Z6length4vec2:
.LFB2042:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2042:
.size _Z6length4vec2, .-_Z6length4vec2
.globl _Z4dist4vec2S_
.type _Z4dist4vec2S_, @function
_Z4dist4vec2S_:
.LFB2043:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2043:
.size _Z4dist4vec2S_, .-_Z4dist4vec2S_
.globl _Z3abs4vec2
.type _Z3abs4vec2, @function
_Z3abs4vec2:
.LFB2044:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2044:
.size _Z3abs4vec2, .-_Z3abs4vec2
.globl _Z5cross4vec3S_
.type _Z5cross4vec3S_, @function
_Z5cross4vec3S_:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %xmm0, 16(%rsp)
movss %xmm1, 24(%rsp)
movq %xmm2, (%rsp)
movss %xmm3, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z5cross4vec3S_, .-_Z5cross4vec3S_
.globl _Z5color4vec3Ph
.type _Z5color4vec3Ph, @function
_Z5color4vec3Ph:
.LFB2063:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2063:
.size _Z5color4vec3Ph, .-_Z5color4vec3Ph
.globl _Z3dot4vec3S_
.type _Z3dot4vec3S_, @function
_Z3dot4vec3S_:
.LFB2064:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %xmm0, 16(%rsp)
movss %xmm1, 24(%rsp)
movq %xmm2, (%rsp)
movss %xmm3, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2064:
.size _Z3dot4vec3S_, .-_Z3dot4vec3S_
.globl _Z7reflect4vec3S_
.type _Z7reflect4vec3S_, @function
_Z7reflect4vec3S_:
.LFB2065:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %xmm0, 16(%rsp)
movss %xmm1, 24(%rsp)
movq %xmm2, (%rsp)
movss %xmm3, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2065:
.size _Z7reflect4vec3S_, .-_Z7reflect4vec3S_
.globl _Z3abs4vec3
.type _Z3abs4vec3, @function
_Z3abs4vec3:
.LFB2066:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2066:
.size _Z3abs4vec3, .-_Z3abs4vec3
.globl _Z6length4vec3
.type _Z6length4vec3, @function
_Z6length4vec3:
.LFB2067:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2067:
.size _Z6length4vec3, .-_Z6length4vec3
.globl _Z4dist4vec3S_
.type _Z4dist4vec3S_, @function
_Z4dist4vec3S_:
.LFB2068:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %xmm0, 16(%rsp)
movss %xmm1, 24(%rsp)
movq %xmm2, (%rsp)
movss %xmm3, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2068:
.size _Z4dist4vec3S_, .-_Z4dist4vec3S_
.globl _Z9normalize4vec3
.type _Z9normalize4vec3, @function
_Z9normalize4vec3:
.LFB2069:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2069:
.size _Z9normalize4vec3, .-_Z9normalize4vec3
.globl _Z2mbff
.type _Z2mbff, @function
_Z2mbff:
.LFB2070:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2070:
.size _Z2mbff, .-_Z2mbff
.globl _Z3max4vec3f
.type _Z3max4vec3f, @function
_Z3max4vec3f:
.LFB2071:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2071:
.size _Z3max4vec3f, .-_Z3max4vec3f
.globl _Z5fractf
.type _Z5fractf, @function
_Z5fractf:
.LFB2091:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2091:
.size _Z5fractf, .-_Z5fractf
.globl _Z4stepff
.type _Z4stepff, @function
_Z4stepff:
.LFB2092:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2092:
.size _Z4stepff, .-_Z4stepff
.globl _Z5clampfff
.type _Z5clampfff, @function
_Z5clampfff:
.LFB2093:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2093:
.size _Z5clampfff, .-_Z5clampfff
.globl _Z3min4vec2S_
.type _Z3min4vec2S_, @function
_Z3min4vec2S_:
.LFB2094:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2094:
.size _Z3min4vec2S_, .-_Z3min4vec2S_
.globl _Z3max4vec2S_
.type _Z3max4vec2S_, @function
_Z3max4vec2S_:
.LFB2095:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2095:
.size _Z3max4vec2S_, .-_Z3max4vec2S_
.globl _Z3mixfff
.type _Z3mixfff, @function
_Z3mixfff:
.LFB2096:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2096:
.size _Z3mixfff, .-_Z3mixfff
.globl _Z4sminfff
.type _Z4sminfff, @function
_Z4sminfff:
.LFB2097:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2097:
.size _Z4sminfff, .-_Z4sminfff
.globl _Z26__device_stub__Z8rotationtt
.type _Z26__device_stub__Z8rotationtt, @function
_Z26__device_stub__Z8rotationtt:
.LFB2122:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movw %di, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L49
.L45:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8rotationt(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L45
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2122:
.size _Z26__device_stub__Z8rotationtt, .-_Z26__device_stub__Z8rotationtt
.globl _Z8rotationt
.type _Z8rotationt, @function
_Z8rotationt:
.LFB2123:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzwl %di, %edi
call _Z26__device_stub__Z8rotationtt
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2123:
.size _Z8rotationt, .-_Z8rotationt
.globl rotate
.type rotate, @function
rotate:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L56
.L53:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
movzwl %bx, %edi
call _Z26__device_stub__Z8rotationtt
jmp .L53
.cfi_endproc
.LFE2087:
.size rotate, .-rotate
.globl _Z30__device_stub__Z11set_frame_gjj
.type _Z30__device_stub__Z11set_frame_gjj, @function
_Z30__device_stub__Z11set_frame_gjj:
.LFB2124:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L61
.L57:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L62
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11set_frame_gj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L57
.L62:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2124:
.size _Z30__device_stub__Z11set_frame_gjj, .-_Z30__device_stub__Z11set_frame_gjj
.globl _Z11set_frame_gj
.type _Z11set_frame_gj, @function
_Z11set_frame_gj:
.LFB2125:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z11set_frame_gjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2125:
.size _Z11set_frame_gj, .-_Z11set_frame_gj
.globl set_frame
.type set_frame, @function
set_frame:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L68
.L65:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
movl %ebx, %edi
call _Z30__device_stub__Z11set_frame_gjj
jmp .L65
.cfi_endproc
.LFE2088:
.size set_frame, .-set_frame
.globl _Z31__device_stub__Z11set_mouse_gffff
.type _Z31__device_stub__Z11set_mouse_gffff, @function
_Z31__device_stub__Z11set_mouse_gffff:
.LFB2126:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L73
.L69:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L74
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L73:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11set_mouse_gff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L69
.L74:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2126:
.size _Z31__device_stub__Z11set_mouse_gffff, .-_Z31__device_stub__Z11set_mouse_gffff
.globl _Z11set_mouse_gff
.type _Z11set_mouse_gff, @function
_Z11set_mouse_gff:
.LFB2127:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z11set_mouse_gffff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2127:
.size _Z11set_mouse_gff, .-_Z11set_mouse_gff
.globl set_mouse
.type set_mouse, @function
set_mouse:
.LFB2089:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movss %xmm0, 8(%rsp)
movss %xmm1, 12(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L80
.L77:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L80:
.cfi_restore_state
movss 12(%rsp), %xmm1
movss 8(%rsp), %xmm0
call _Z31__device_stub__Z11set_mouse_gffff
jmp .L77
.cfi_endproc
.LFE2089:
.size set_mouse, .-set_mouse
.globl _Z32__device_stub__Z12set_window_giiii
.type _Z32__device_stub__Z12set_window_giiii, @function
_Z32__device_stub__Z12set_window_giiii:
.LFB2128:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L85
.L81:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L86
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L85:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12set_window_gii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L81
.L86:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2128:
.size _Z32__device_stub__Z12set_window_giiii, .-_Z32__device_stub__Z12set_window_giiii
.globl _Z12set_window_gii
.type _Z12set_window_gii, @function
_Z12set_window_gii:
.LFB2129:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z12set_window_giiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2129:
.size _Z12set_window_gii, .-_Z12set_window_gii
.globl set_window
.type set_window, @function
set_window:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movl %edi, %ebx
movl %esi, %ebp
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L92
.L89:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L92:
.cfi_restore_state
movl %ebp, %esi
movl %ebx, %edi
call _Z32__device_stub__Z12set_window_giiii
jmp .L89
.cfi_endproc
.LFE2090:
.size set_window, .-set_window
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12set_window_gii"
.LC1:
.string "_Z11set_mouse_gff"
.LC2:
.string "_Z11set_frame_gj"
.LC3:
.string "_Z8rotationt"
.LC4:
.string "rot"
.LC5:
.string "frame"
.LC6:
.string "sinfr"
.LC7:
.string "cosfr"
.LC8:
.string "mouse"
.LC9:
.string "window"
.LC10:
.string "windowD2"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2131:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12set_window_gii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11set_mouse_gff(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z11set_frame_gj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8rotationt(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3rot(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5frame(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5sinfr(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5cosfr(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5mouse(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6window(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8windowD2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2131:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.text
.type _GLOBAL__sub_I__Z5colorfffPh, @function
_GLOBAL__sub_I__Z5colorfffPh:
.LFB2248:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq $0, 8(%rsp)
movq 8(%rsp), %rdi
call free@PLT
movq $0, 16(%rsp)
movq 16(%rsp), %rdi
call free@PLT
movq $0, 24(%rsp)
movq 24(%rsp), %rdi
call free@PLT
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2248:
.size _GLOBAL__sub_I__Z5colorfffPh, .-_GLOBAL__sub_I__Z5colorfffPh
.section .init_array
.align 8
.quad _GLOBAL__sub_I__Z5colorfffPh
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL8windowD2
.comm _ZL8windowD2,8,8
.local _ZL6window
.comm _ZL6window,8,8
.local _ZL5mouse
.comm _ZL5mouse,8,8
.local _ZL5cosfr
.comm _ZL5cosfr,4,4
.local _ZL5sinfr
.comm _ZL5sinfr,4,4
.local _ZL5frame
.comm _ZL5frame,4,4
.local _ZL3rot
.comm _ZL3rot,2,2
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __device__ void color(float r, float g, float b, unsigned char* buffer){
if(r>255)
buffer[0] = 255;
else
buffer[0] = (unsigned char)(r);
if(r>255)
buffer[1] = 255;
else
buffer[1] = (unsigned char)(g);
if(r>255)
buffer[2] = 255;
else
buffer[2] = (unsigned char)(b);
}
__device__ struct mat2{
float N[2];
float M[2];
__device__ mat2(float a, float b, float c, float d)
{
N[0] = a;
N[1] = b;
M[0] = c;
M[1] = d;
}
};
__device__ struct vec2{
float x;
float y;
__device__ vec2 (){}
__device__ vec2 (float x, float y): x(x), y(y){}
__device__ vec2 ( float a): x(a),y(a){}
__device__ vec2 operator+(const vec2& v) const
{
return {v.x+x,v.y+y};
}
__device__ vec2 operator-(const vec2& v) const
{
return {x-v.x,y-v.y};
}
};
//vec2 calculations except operators
__device__ float length(vec2 v){
return sqrt(v.x*v.x + v.y*v.y);}
__device__ float dist(vec2 posa, vec2 posb){
float dx,dy;
dx = posa.x - posb.x;
dy = posa.y -posb.y;
return sqrt(dx*dx + dy*dy);}
__device__ vec2 abs(vec2 v){
return {abs(v.x),abs(v.y)};}
//vec3 can begin
__device__ struct vec3 {
float x;
float y;
float z;
//Constructors in different ways
__device__ vec3 (){}
__device__ vec3 (float x, float y, float z):x(x),y(y),z(z){}
__device__ vec3(float a):x(a),y(a),z(a){}
__device__ vec3(vec2 v, float z):x(v.x),y(v.y),z(z){}
__device__ vec3 operator+(const vec3& a) const{
return {a.x + x, a.y+y, a.z+z};}
__device__ vec3 operator-(const vec3& a) const{
return {x-a.x,y-a.y, z-a.z};}
__device__ vec3 operator*(const vec3& a) const{
return {a.x*x, a.y*y , a.z*z };
}
__device__ vec3 operator*(const float a) const{
return {x*a, y*a, z*a};}
__device__ vec3 operator/(const float a) const{
return {x/a, y/a, z/a};}
};
__device__ vec3 cross(vec3 a, vec3 b){
return {a.y*b.z - b.y * a.z, a.z*b.x - b.z*a.x, a.x*b.y -b.x*a.y};
}
__device__ void color(vec3 c, unsigned char* buffer){
if (c.x < 0)
buffer[0] = 0;
else if (c.x > 255)
buffer[0] = 255;
else
buffer[0] = (unsigned char)(c.x);
if (c.y < 0)
buffer[1] = 0;
else if (c.y > 255)
buffer[1] = 255;
else
buffer[1] = (unsigned char)(c.y);
if (c.z < 0)
buffer[2] = 0;
else if (c.z > 255)
buffer[2] = 255;
else
buffer[2] = (unsigned char)(c.z);
}
__device__ float dot(vec3 a, vec3 b){
return a.x*b.x + a.y*b.y + a.z*b.z;}
// I is the Incident vector (direction) and N the Normal vector of the surface
__device__ vec3 reflect(vec3 I, vec3 N){
return I - N *dot(N,I)*2;
}
//can i put this to perators????
__device__ vec3 abs(vec3 v){
return {abs(v.x),abs(v.y),abs(v.z)};}
__device__ float length(vec3 v){
return sqrt(v.x*v.x + v.y*v.y + v.z*v.z);}
__device__ float dist(vec3 a, vec3 b){
float dx,dy,dz;
dx = a.x-b.x;
dy = a.y-b.y;
dz = a.z-b.z;
return sqrt(dx*dx+dy*dy+dz*dz);}
__device__ vec3 normalize(vec3 v){
float betrag = length(v);
return {v.x/betrag,v.y/betrag,v.z/betrag};}
//not sure about the following 2 formulas, a max between a vector and a float seems weird to me
__device__ float mb(float a, float mx){
return a > mx ? a : mx;
}
__device__ vec3 max(vec3 v, float d){
return {mb(v.x,d),
mb(v.y,d),
mb(v.z,d)};}
//i still wonder what i need a 4th dimension for, but we will see
__device__ struct vec4{
float x;
float y;
float z;
float w;
__device__ vec4(){}
__device__ vec4(float x, float y, float z, float w):x(x),y(y),z(z),w(w){}
__device__ vec4(vec3 v, float w): x(v.x), y(v.y), z(v.y), w(w){}
__device__ vec4(float a):x(a),y(a),z(a),w(a){}
__device__ vec4(vec2 v1, vec2 v2): x(v1.x),y(v1.y),z(v2.x),w(v2.y){}
};
//init global rot variable and the functions to set during runtime
//remember that __host__ function always has to be inside extern "C" to be accessed by C-types
//btw check if there might be a less dirty way to acess the __device__ variable from __host__ function
__device__ unsigned short int rot = 0;
__global__ void rotation(unsigned short int angle){
rot = angle;}
extern "C"{__host__ void rotate(unsigned short int angle){
rotation<<<1,1>>>(angle);}}
//same here with the frame
__device__ float frame = 0;
__device__ float sinfr = 0;
__device__ float cosfr = 0;
__global__ void set_frame_g(unsigned int f){
frame = (float)f;
sinfr = sin(frame*M_PI/180);
cosfr = cos(frame*M_PI/180);}
extern "C"{__host__ void set_frame(unsigned int f){
set_frame_g<<<1,1>>>(f);}}
__device__ vec2 mouse;
__global__ void set_mouse_g(float x, float y){
mouse.x = x*2;
mouse.y = y*2;}
extern "C"{__host__ void set_mouse(float x, float y){
set_mouse_g<<<1,1>>>(x,y);}}
__device__ vec2 window;
__device__ vec2 windowD2;
__global__ void set_window_g(int x, int y){
window.x = (float)(x);
window.y = (float)(y);
windowD2.x = (float)(x)/2;
windowD2.y = (float)(y)/2;}
extern "C"{ __host__ void set_window(int x, int y){
set_window_g<<<1,1>>>(x,y);}}
//nice functionalities for floats to have in Shady programming
__device__ float fract(float f){
return f - floor(f);}
__device__ float step(float a, float b){
if (abs(a) < abs(b))
return 1;
else
return 0;}
__device__ float clamp(float x, float minVal, float maxVal){
return min(max(x,minVal),maxVal);}
__device__ vec2 min(vec2 v1, vec2 v2){
if (v1.x<v2.x)
return v1;
else
return v2;
// vec2.y soll in dem Falle die Variable für "solid/glas/mirror" sein, die abstandtsfunktion und so müssen von float auf vec2 geändert werden
//eine neue Funktion dann auch für raymarch innerhalb glas
// und eine für spiegelung
//alternativ eine raymarch funktion erst für glas, dann für spiegel, dann für solids erstellen
}
__device__ vec2 max(vec2 v1, vec2 v2){
if (v1.x>v2.x)
return v1;
else
return v2;
}
__device__ float mix(float v1,float v2, float a){
return v1* (1-a) + v2*a;}
//define smin for vec2 returns....
__device__ float smin(float a, float b, float k){//smooth min, very nice
float h = clamp(0.5 + 0.5 * (b-a)/k,0.1,1.0);
return mix(b,a,h) - k*h*(1.0-h);} | #include <hip/hip_runtime.h>
__device__ void color(float r, float g, float b, unsigned char* buffer){
if(r>255)
buffer[0] = 255;
else
buffer[0] = (unsigned char)(r);
if(r>255)
buffer[1] = 255;
else
buffer[1] = (unsigned char)(g);
if(r>255)
buffer[2] = 255;
else
buffer[2] = (unsigned char)(b);
}
__device__ struct mat2{
float N[2];
float M[2];
__device__ mat2(float a, float b, float c, float d)
{
N[0] = a;
N[1] = b;
M[0] = c;
M[1] = d;
}
};
__device__ struct vec2{
float x;
float y;
__device__ vec2 (){}
__device__ vec2 (float x, float y): x(x), y(y){}
__device__ vec2 ( float a): x(a),y(a){}
__device__ vec2 operator+(const vec2& v) const
{
return {v.x+x,v.y+y};
}
__device__ vec2 operator-(const vec2& v) const
{
return {x-v.x,y-v.y};
}
};
//vec2 calculations except operators
__device__ float length(vec2 v){
return sqrt(v.x*v.x + v.y*v.y);}
__device__ float dist(vec2 posa, vec2 posb){
float dx,dy;
dx = posa.x - posb.x;
dy = posa.y -posb.y;
return sqrt(dx*dx + dy*dy);}
__device__ vec2 abs(vec2 v){
return {abs(v.x),abs(v.y)};}
//vec3 can begin
__device__ struct vec3 {
float x;
float y;
float z;
//Constructors in different ways
__device__ vec3 (){}
__device__ vec3 (float x, float y, float z):x(x),y(y),z(z){}
__device__ vec3(float a):x(a),y(a),z(a){}
__device__ vec3(vec2 v, float z):x(v.x),y(v.y),z(z){}
__device__ vec3 operator+(const vec3& a) const{
return {a.x + x, a.y+y, a.z+z};}
__device__ vec3 operator-(const vec3& a) const{
return {x-a.x,y-a.y, z-a.z};}
__device__ vec3 operator*(const vec3& a) const{
return {a.x*x, a.y*y , a.z*z };
}
__device__ vec3 operator*(const float a) const{
return {x*a, y*a, z*a};}
__device__ vec3 operator/(const float a) const{
return {x/a, y/a, z/a};}
};
__device__ vec3 cross(vec3 a, vec3 b){
return {a.y*b.z - b.y * a.z, a.z*b.x - b.z*a.x, a.x*b.y -b.x*a.y};
}
__device__ void color(vec3 c, unsigned char* buffer){
if (c.x < 0)
buffer[0] = 0;
else if (c.x > 255)
buffer[0] = 255;
else
buffer[0] = (unsigned char)(c.x);
if (c.y < 0)
buffer[1] = 0;
else if (c.y > 255)
buffer[1] = 255;
else
buffer[1] = (unsigned char)(c.y);
if (c.z < 0)
buffer[2] = 0;
else if (c.z > 255)
buffer[2] = 255;
else
buffer[2] = (unsigned char)(c.z);
}
__device__ float dot(vec3 a, vec3 b){
return a.x*b.x + a.y*b.y + a.z*b.z;}
// I is the Incident vector (direction) and N the Normal vector of the surface
__device__ vec3 reflect(vec3 I, vec3 N){
return I - N *dot(N,I)*2;
}
//can i put this to perators????
__device__ vec3 abs(vec3 v){
return {abs(v.x),abs(v.y),abs(v.z)};}
__device__ float length(vec3 v){
return sqrt(v.x*v.x + v.y*v.y + v.z*v.z);}
__device__ float dist(vec3 a, vec3 b){
float dx,dy,dz;
dx = a.x-b.x;
dy = a.y-b.y;
dz = a.z-b.z;
return sqrt(dx*dx+dy*dy+dz*dz);}
__device__ vec3 normalize(vec3 v){
float betrag = length(v);
return {v.x/betrag,v.y/betrag,v.z/betrag};}
//not sure about the following 2 formulas, a max between a vector and a float seems weird to me
__device__ float mb(float a, float mx){
return a > mx ? a : mx;
}
__device__ vec3 max(vec3 v, float d){
return {mb(v.x,d),
mb(v.y,d),
mb(v.z,d)};}
//i still wonder what i need a 4th dimension for, but we will see
__device__ struct vec4{
float x;
float y;
float z;
float w;
__device__ vec4(){}
__device__ vec4(float x, float y, float z, float w):x(x),y(y),z(z),w(w){}
__device__ vec4(vec3 v, float w): x(v.x), y(v.y), z(v.y), w(w){}
__device__ vec4(float a):x(a),y(a),z(a),w(a){}
__device__ vec4(vec2 v1, vec2 v2): x(v1.x),y(v1.y),z(v2.x),w(v2.y){}
};
//init global rot variable and the functions to set during runtime
//remember that __host__ function always has to be inside extern "C" to be accessed by C-types
//btw check if there might be a less dirty way to acess the __device__ variable from __host__ function
__device__ unsigned short int rot = 0;
__global__ void rotation(unsigned short int angle){
rot = angle;}
extern "C"{__host__ void rotate(unsigned short int angle){
rotation<<<1,1>>>(angle);}}
//same here with the frame
__device__ float frame = 0;
__device__ float sinfr = 0;
__device__ float cosfr = 0;
__global__ void set_frame_g(unsigned int f){
frame = (float)f;
sinfr = sin(frame*M_PI/180);
cosfr = cos(frame*M_PI/180);}
extern "C"{__host__ void set_frame(unsigned int f){
set_frame_g<<<1,1>>>(f);}}
__device__ vec2 mouse;
__global__ void set_mouse_g(float x, float y){
mouse.x = x*2;
mouse.y = y*2;}
extern "C"{__host__ void set_mouse(float x, float y){
set_mouse_g<<<1,1>>>(x,y);}}
__device__ vec2 window;
__device__ vec2 windowD2;
__global__ void set_window_g(int x, int y){
window.x = (float)(x);
window.y = (float)(y);
windowD2.x = (float)(x)/2;
windowD2.y = (float)(y)/2;}
extern "C"{ __host__ void set_window(int x, int y){
set_window_g<<<1,1>>>(x,y);}}
//nice functionalities for floats to have in Shady programming
__device__ float fract(float f){
return f - floor(f);}
__device__ float step(float a, float b){
if (abs(a) < abs(b))
return 1;
else
return 0;}
__device__ float clamp(float x, float minVal, float maxVal){
return min(max(x,minVal),maxVal);}
__device__ vec2 min(vec2 v1, vec2 v2){
if (v1.x<v2.x)
return v1;
else
return v2;
// vec2.y soll in dem Falle die Variable für "solid/glas/mirror" sein, die abstandtsfunktion und so müssen von float auf vec2 geändert werden
//eine neue Funktion dann auch für raymarch innerhalb glas
// und eine für spiegelung
//alternativ eine raymarch funktion erst für glas, dann für spiegel, dann für solids erstellen
}
__device__ vec2 max(vec2 v1, vec2 v2){
if (v1.x>v2.x)
return v1;
else
return v2;
}
__device__ float mix(float v1,float v2, float a){
return v1* (1-a) + v2*a;}
//define smin for vec2 returns....
__device__ float smin(float a, float b, float k){//smooth min, very nice
float h = clamp(0.5 + 0.5 * (b-a)/k,0.1,1.0);
return mix(b,a,h) - k*h*(1.0-h);} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__device__ void color(float r, float g, float b, unsigned char* buffer){
if(r>255)
buffer[0] = 255;
else
buffer[0] = (unsigned char)(r);
if(r>255)
buffer[1] = 255;
else
buffer[1] = (unsigned char)(g);
if(r>255)
buffer[2] = 255;
else
buffer[2] = (unsigned char)(b);
}
__device__ struct mat2{
float N[2];
float M[2];
__device__ mat2(float a, float b, float c, float d)
{
N[0] = a;
N[1] = b;
M[0] = c;
M[1] = d;
}
};
__device__ struct vec2{
float x;
float y;
__device__ vec2 (){}
__device__ vec2 (float x, float y): x(x), y(y){}
__device__ vec2 ( float a): x(a),y(a){}
__device__ vec2 operator+(const vec2& v) const
{
return {v.x+x,v.y+y};
}
__device__ vec2 operator-(const vec2& v) const
{
return {x-v.x,y-v.y};
}
};
//vec2 calculations except operators
__device__ float length(vec2 v){
return sqrt(v.x*v.x + v.y*v.y);}
__device__ float dist(vec2 posa, vec2 posb){
float dx,dy;
dx = posa.x - posb.x;
dy = posa.y -posb.y;
return sqrt(dx*dx + dy*dy);}
__device__ vec2 abs(vec2 v){
return {abs(v.x),abs(v.y)};}
//vec3 can begin
__device__ struct vec3 {
float x;
float y;
float z;
//Constructors in different ways
__device__ vec3 (){}
__device__ vec3 (float x, float y, float z):x(x),y(y),z(z){}
__device__ vec3(float a):x(a),y(a),z(a){}
__device__ vec3(vec2 v, float z):x(v.x),y(v.y),z(z){}
__device__ vec3 operator+(const vec3& a) const{
return {a.x + x, a.y+y, a.z+z};}
__device__ vec3 operator-(const vec3& a) const{
return {x-a.x,y-a.y, z-a.z};}
__device__ vec3 operator*(const vec3& a) const{
return {a.x*x, a.y*y , a.z*z };
}
__device__ vec3 operator*(const float a) const{
return {x*a, y*a, z*a};}
__device__ vec3 operator/(const float a) const{
return {x/a, y/a, z/a};}
};
__device__ vec3 cross(vec3 a, vec3 b){
return {a.y*b.z - b.y * a.z, a.z*b.x - b.z*a.x, a.x*b.y -b.x*a.y};
}
__device__ void color(vec3 c, unsigned char* buffer){
if (c.x < 0)
buffer[0] = 0;
else if (c.x > 255)
buffer[0] = 255;
else
buffer[0] = (unsigned char)(c.x);
if (c.y < 0)
buffer[1] = 0;
else if (c.y > 255)
buffer[1] = 255;
else
buffer[1] = (unsigned char)(c.y);
if (c.z < 0)
buffer[2] = 0;
else if (c.z > 255)
buffer[2] = 255;
else
buffer[2] = (unsigned char)(c.z);
}
__device__ float dot(vec3 a, vec3 b){
return a.x*b.x + a.y*b.y + a.z*b.z;}
// I is the Incident vector (direction) and N the Normal vector of the surface
__device__ vec3 reflect(vec3 I, vec3 N){
return I - N *dot(N,I)*2;
}
//can i put this to perators????
__device__ vec3 abs(vec3 v){
return {abs(v.x),abs(v.y),abs(v.z)};}
__device__ float length(vec3 v){
return sqrt(v.x*v.x + v.y*v.y + v.z*v.z);}
__device__ float dist(vec3 a, vec3 b){
float dx,dy,dz;
dx = a.x-b.x;
dy = a.y-b.y;
dz = a.z-b.z;
return sqrt(dx*dx+dy*dy+dz*dz);}
__device__ vec3 normalize(vec3 v){
float betrag = length(v);
return {v.x/betrag,v.y/betrag,v.z/betrag};}
//not sure about the following 2 formulas, a max between a vector and a float seems weird to me
__device__ float mb(float a, float mx){
return a > mx ? a : mx;
}
__device__ vec3 max(vec3 v, float d){
return {mb(v.x,d),
mb(v.y,d),
mb(v.z,d)};}
//i still wonder what i need a 4th dimension for, but we will see
__device__ struct vec4{
float x;
float y;
float z;
float w;
__device__ vec4(){}
__device__ vec4(float x, float y, float z, float w):x(x),y(y),z(z),w(w){}
__device__ vec4(vec3 v, float w): x(v.x), y(v.y), z(v.y), w(w){}
__device__ vec4(float a):x(a),y(a),z(a),w(a){}
__device__ vec4(vec2 v1, vec2 v2): x(v1.x),y(v1.y),z(v2.x),w(v2.y){}
};
//init global rot variable and the functions to set during runtime
//remember that __host__ function always has to be inside extern "C" to be accessed by C-types
//btw check if there might be a less dirty way to acess the __device__ variable from __host__ function
__device__ unsigned short int rot = 0;
__global__ void rotation(unsigned short int angle){
rot = angle;}
extern "C"{__host__ void rotate(unsigned short int angle){
rotation<<<1,1>>>(angle);}}
//same here with the frame
__device__ float frame = 0;
__device__ float sinfr = 0;
__device__ float cosfr = 0;
__global__ void set_frame_g(unsigned int f){
frame = (float)f;
sinfr = sin(frame*M_PI/180);
cosfr = cos(frame*M_PI/180);}
extern "C"{__host__ void set_frame(unsigned int f){
set_frame_g<<<1,1>>>(f);}}
__device__ vec2 mouse;
__global__ void set_mouse_g(float x, float y){
mouse.x = x*2;
mouse.y = y*2;}
extern "C"{__host__ void set_mouse(float x, float y){
set_mouse_g<<<1,1>>>(x,y);}}
__device__ vec2 window;
__device__ vec2 windowD2;
__global__ void set_window_g(int x, int y){
window.x = (float)(x);
window.y = (float)(y);
windowD2.x = (float)(x)/2;
windowD2.y = (float)(y)/2;}
extern "C"{ __host__ void set_window(int x, int y){
set_window_g<<<1,1>>>(x,y);}}
//nice functionalities for floats to have in Shady programming
__device__ float fract(float f){
return f - floor(f);}
__device__ float step(float a, float b){
if (abs(a) < abs(b))
return 1;
else
return 0;}
__device__ float clamp(float x, float minVal, float maxVal){
return min(max(x,minVal),maxVal);}
__device__ vec2 min(vec2 v1, vec2 v2){
if (v1.x<v2.x)
return v1;
else
return v2;
// vec2.y soll in dem Falle die Variable für "solid/glas/mirror" sein, die abstandtsfunktion und so müssen von float auf vec2 geändert werden
//eine neue Funktion dann auch für raymarch innerhalb glas
// und eine für spiegelung
//alternativ eine raymarch funktion erst für glas, dann für spiegel, dann für solids erstellen
}
__device__ vec2 max(vec2 v1, vec2 v2){
if (v1.x>v2.x)
return v1;
else
return v2;
}
__device__ float mix(float v1,float v2, float a){
return v1* (1-a) + v2*a;}
//define smin for vec2 returns....
__device__ float smin(float a, float b, float k){//smooth min, very nice
float h = clamp(0.5 + 0.5 * (b-a)/k,0.1,1.0);
return mix(b,a,h) - k*h*(1.0-h);} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8rotationt
.globl _Z8rotationt
.p2align 8
.type _Z8rotationt,@function
_Z8rotationt:
s_load_b32 s2, s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, rot@rel32@lo+4
s_addc_u32 s1, s1, rot@rel32@hi+12
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v1, s2
global_store_b16 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8rotationt
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 4
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 3
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8rotationt, .Lfunc_end0-_Z8rotationt
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11set_frame_gj
.globl _Z11set_frame_gj
.p2align 8
.type _Z11set_frame_gj,@function
_Z11set_frame_gj:
s_load_b32 s0, s[0:1], 0x0
s_mov_b32 s3, 0x400921fb
s_mov_b32 s2, 0x54442d18
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, frame@rel32@lo+4
s_addc_u32 s5, s5, frame@rel32@hi+12
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v10, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[0:1], v10
v_mul_f64 v[0:1], v[0:1], s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[2:3], null, 0x40668000, 0x40668000, v[0:1]
v_rcp_f64_e32 v[4:5], v[2:3]
s_waitcnt_depctr 0xfff
v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
v_div_scale_f64 v[6:7], vcc_lo, v[0:1], 0x40668000, v[0:1]
v_mul_f64 v[8:9], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], -v[2:3], v[8:9], v[6:7]
v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_div_fixup_f64 v[0:1], v[2:3], 0x40668000, v[0:1]
v_mov_b32_e32 v2, 0
global_store_b32 v2, v10, s[4:5]
v_cmp_ngt_f64_e32 vcc_lo, 0x41d00000, v[0:1]
s_and_b32 s1, exec_lo, vcc_lo
s_mov_b32 vcc_lo, s1
s_cbranch_vccz .LBB1_2
v_ldexp_f64 v[2:3], v[0:1], 0xffffff80
v_cmp_le_f64_e32 vcc_lo, 0x7b000000, v[0:1]
v_trig_preop_f64 v[4:5], v[0:1], 0
v_trig_preop_f64 v[6:7], v[0:1], 1
v_trig_preop_f64 v[16:17], v[0:1], 2
s_mov_b32 s4, 0
s_mov_b32 s3, 0x3ff921fb
s_mov_b32 s7, 0x3c91a626
s_mov_b32 s6, 0x33145c07
v_dual_cndmask_b32 v3, v1, v3 :: v_dual_cndmask_b32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f64 v[8:9], v[4:5], v[2:3]
v_mul_f64 v[10:11], v[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[22:23], v[16:17], v[2:3]
v_fma_f64 v[4:5], v[4:5], v[2:3], -v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[6:7], v[6:7], v[2:3], -v[10:11]
v_fma_f64 v[2:3], v[16:17], v[2:3], -v[22:23]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[12:13], v[10:11], v[4:5]
v_add_f64 v[14:15], v[12:13], -v[10:11]
v_add_f64 v[20:21], v[8:9], v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[18:19], v[12:13], -v[14:15]
v_add_f64 v[4:5], v[4:5], -v[14:15]
v_ldexp_f64 v[14:15], v[20:21], -2
v_add_f64 v[8:9], v[20:21], -v[8:9]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[10:11], v[10:11], -v[18:19]
v_add_f64 v[18:19], v[22:23], v[6:7]
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[14:15]|
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[8:9], v[12:13], -v[8:9]
v_add_f64 v[4:5], v[4:5], v[10:11]
v_fract_f64_e32 v[10:11], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[12:13], v[18:19], v[4:5]
v_dual_cndmask_b32 v11, 0, v11 :: v_dual_cndmask_b32 v10, 0, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ldexp_f64 v[10:11], v[10:11], 2
v_add_f64 v[14:15], v[8:9], v[12:13]
v_add_f64 v[24:25], v[12:13], -v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[20:21], v[14:15], v[10:11]
v_add_f64 v[30:31], v[12:13], -v[24:25]
v_add_f64 v[4:5], v[4:5], -v[24:25]
v_add_f64 v[8:9], v[14:15], -v[8:9]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, 0, v[20:21]
v_add_f64 v[20:21], v[18:19], -v[22:23]
s_and_b32 s0, vcc_lo, exec_lo
s_cselect_b32 s5, 0x40100000, 0
v_add_f64 v[28:29], v[18:19], -v[20:21]
v_add_f64 v[10:11], v[10:11], s[4:5]
v_add_f64 v[6:7], v[6:7], -v[20:21]
v_add_f64 v[18:19], v[18:19], -v[30:31]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[20:21], v[22:23], -v[28:29]
v_add_f64 v[26:27], v[14:15], v[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[4:5], v[4:5], v[18:19]
v_add_f64 v[6:7], v[6:7], v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f64_e32 v26, v[26:27]
v_add_f64 v[4:5], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cvt_f64_i32_e32 v[24:25], v26
v_add_f64 v[6:7], v[12:13], -v[8:9]
v_add_f64 v[2:3], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[10:11], -v[24:25]
v_add_f64 v[2:3], v[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[16:17], v[14:15], v[10:11]
v_add_f64 v[4:5], v[16:17], -v[10:11]
v_cmp_le_f64_e32 vcc_lo, 0.5, v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[14:15], -v[4:5]
s_and_b32 s0, vcc_lo, exec_lo
s_cselect_b32 s5, 0x3ff00000, 0
v_add_co_ci_u32_e64 v6, s0, 0, v26, vcc_lo
v_add_f64 v[2:3], v[2:3], v[4:5]
v_add_f64 v[4:5], v[16:17], -s[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[4:5], v[2:3]
v_mul_f64 v[9:10], v[7:8], s[2:3]
v_add_f64 v[4:5], v[7:8], -v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[11:12], v[7:8], s[2:3], -v[9:10]
v_add_f64 v[2:3], v[2:3], -v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], v[7:8], s[6:7], v[11:12]
v_fma_f64 v[4:5], v[2:3], s[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[9:10], v[4:5]
v_add_f64 v[7:8], v[2:3], -v[9:10]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], -v[7:8]
s_cbranch_execz .LBB1_3
s_branch .LBB1_4
.LBB1_2:
.LBB1_3:
s_mov_b32 s3, 0x3fe45f30
s_mov_b32 s2, 0x6dc9c883
s_mov_b32 s5, 0xbc91a626
v_mul_f64 v[2:3], v[0:1], s[2:3]
s_mov_b32 s3, 0xbff921fb
s_mov_b32 s2, 0x54442d18
s_mov_b32 s4, 0x33145c00
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[6:7], v[2:3]
v_fma_f64 v[2:3], v[6:7], s[2:3], v[0:1]
v_mul_f64 v[4:5], v[6:7], s[4:5]
s_mov_b32 s3, 0xb97b839a
s_mov_b32 s2, 0x252049c0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[6:7], s[4:5], v[2:3]
v_add_f64 v[8:9], v[2:3], v[4:5]
s_mov_b32 s5, 0x3c91a626
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[2:3], v[2:3], -v[8:9]
v_add_f64 v[8:9], v[8:9], -v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[2:3], v[2:3], v[4:5]
v_fma_f64 v[4:5], v[6:7], s[4:5], v[4:5]
v_add_f64 v[2:3], v[8:9], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], -v[4:5]
v_fma_f64 v[4:5], v[6:7], s[2:3], v[2:3]
v_cvt_i32_f64_e32 v6, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[10:11], v[4:5]
v_add_f64 v[8:9], v[2:3], -v[10:11]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], -v[8:9]
.LBB1_4:
v_mul_f64 v[7:8], v[2:3], v[2:3]
s_mov_b32 s3, 0xbe5ae600
s_mov_b32 s2, 0xb42fdfa7
s_mov_b32 s5, 0x3de5e0b2
s_mov_b32 s4, 0xf9a43bb8
s_mov_b32 s7, 0x3ec71de3
s_mov_b32 s6, 0x796cde01
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f64 v[17:18], v[4:5], 0.5
v_cmp_lg_f64_e64 s0, 0x7ff00000, v[0:1]
v_fma_f64 v[9:10], v[7:8], s[4:5], s[2:3]
s_mov_b32 s3, 0x3e21eeb6
s_mov_b32 s2, 0x9037ab78
s_mov_b32 s5, 0xbda907db
s_mov_b32 s4, 0x46cc5e42
v_mul_f64 v[13:14], v[7:8], 0.5
v_fma_f64 v[11:12], v[7:8], s[4:5], s[2:3]
s_mov_b32 s3, 0xbe927e4f
s_mov_b32 s2, 0xa17f65f6
s_mov_b32 s5, 0xbf2a01a0
s_mov_b32 s4, 0x19e83e5c
v_mul_f64 v[19:20], v[2:3], -v[7:8]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[9:10], v[7:8], v[9:10], s[6:7]
v_add_f64 v[15:16], -v[13:14], 1.0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[11:12], v[7:8], v[11:12], s[2:3]
s_mov_b32 s3, 0x3efa01a0
s_mov_b32 s2, 0x19f4ec90
v_fma_f64 v[9:10], v[7:8], v[9:10], s[4:5]
s_mov_b32 s5, 0x3f811111
s_mov_b32 s4, 0x11110bb3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[21:22], -v[15:16], 1.0
v_fma_f64 v[11:12], v[7:8], v[11:12], s[2:3]
s_mov_b32 s3, 0xbf56c16c
s_mov_b32 s2, 0x16c16967
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_fma_f64 v[9:10], v[7:8], v[9:10], s[4:5]
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, sinfr@rel32@lo+4
s_addc_u32 s5, s5, sinfr@rel32@hi+12
v_add_f64 v[13:14], v[21:22], -v[13:14]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[11:12], v[7:8], v[11:12], s[2:3]
s_mov_b32 s3, 0x3fa55555
s_mov_b32 s2, 0x55555555
v_fma_f64 v[9:10], v[19:20], v[9:10], v[17:18]
v_mul_f64 v[17:18], v[7:8], v[7:8]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[13:14], v[2:3], -v[4:5], v[13:14]
v_fma_f64 v[11:12], v[7:8], v[11:12], s[2:3]
s_mov_b32 s3, 0xbfc55555
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[4:5], v[7:8], v[9:10], -v[4:5]
v_fma_f64 v[7:8], v[17:18], v[11:12], v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[4:5], v[19:20], s[2:3], v[4:5]
s_mov_b32 s2, 0
v_add_f64 v[7:8], v[15:16], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], -v[4:5]
v_and_b32_e32 v4, 1, v6
v_cmp_eq_u32_e32 vcc_lo, 0, v4
v_lshlrev_b32_e32 v4, 30, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v4, v4, v1
v_dual_cndmask_b32 v3, v8, v3 :: v_dual_and_b32 v4, 0x80000000, v4
v_cndmask_b32_e32 v2, v7, v2, vcc_lo
s_mov_b32 vcc_lo, s1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v3, v3, v4
v_cndmask_b32_e64 v2, 0, v2, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, 0x7ff80000, v3, s0
v_cvt_f32_f64_e32 v2, v[2:3]
v_mov_b32_e32 v3, 0
global_store_b32 v3, v2, s[4:5]
s_cbranch_vccz .LBB1_6
v_ldexp_f64 v[2:3], v[0:1], 0xffffff80
v_cmp_le_f64_e32 vcc_lo, 0x7b000000, v[0:1]
v_trig_preop_f64 v[4:5], v[0:1], 0
v_trig_preop_f64 v[6:7], v[0:1], 1
v_trig_preop_f64 v[16:17], v[0:1], 2
s_mov_b32 s5, 0x3ff921fb
s_mov_b32 s4, 0x54442d18
s_mov_b32 s7, 0x3c91a626
s_mov_b32 s6, 0x33145c07
v_dual_cndmask_b32 v3, v1, v3 :: v_dual_cndmask_b32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f64 v[8:9], v[4:5], v[2:3]
v_mul_f64 v[10:11], v[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[22:23], v[16:17], v[2:3]
v_fma_f64 v[4:5], v[4:5], v[2:3], -v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[6:7], v[6:7], v[2:3], -v[10:11]
v_fma_f64 v[2:3], v[16:17], v[2:3], -v[22:23]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[12:13], v[10:11], v[4:5]
v_add_f64 v[14:15], v[12:13], -v[10:11]
v_add_f64 v[20:21], v[8:9], v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[18:19], v[12:13], -v[14:15]
v_add_f64 v[4:5], v[4:5], -v[14:15]
v_ldexp_f64 v[14:15], v[20:21], -2
v_add_f64 v[8:9], v[20:21], -v[8:9]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[10:11], v[10:11], -v[18:19]
v_add_f64 v[18:19], v[22:23], v[6:7]
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[14:15]|
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[8:9], v[12:13], -v[8:9]
v_add_f64 v[4:5], v[4:5], v[10:11]
v_fract_f64_e32 v[10:11], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[12:13], v[18:19], v[4:5]
v_dual_cndmask_b32 v11, 0, v11 :: v_dual_cndmask_b32 v10, 0, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ldexp_f64 v[10:11], v[10:11], 2
v_add_f64 v[14:15], v[8:9], v[12:13]
v_add_f64 v[24:25], v[12:13], -v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[20:21], v[14:15], v[10:11]
v_add_f64 v[30:31], v[12:13], -v[24:25]
v_add_f64 v[4:5], v[4:5], -v[24:25]
v_add_f64 v[8:9], v[14:15], -v[8:9]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, 0, v[20:21]
v_add_f64 v[20:21], v[18:19], -v[22:23]
s_and_b32 s1, vcc_lo, exec_lo
s_cselect_b32 s3, 0x40100000, 0
v_add_f64 v[28:29], v[18:19], -v[20:21]
v_add_f64 v[10:11], v[10:11], s[2:3]
v_add_f64 v[6:7], v[6:7], -v[20:21]
v_add_f64 v[18:19], v[18:19], -v[30:31]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[20:21], v[22:23], -v[28:29]
v_add_f64 v[26:27], v[14:15], v[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[4:5], v[4:5], v[18:19]
v_add_f64 v[6:7], v[6:7], v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f64_e32 v26, v[26:27]
v_add_f64 v[4:5], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cvt_f64_i32_e32 v[24:25], v26
v_add_f64 v[6:7], v[12:13], -v[8:9]
v_add_f64 v[2:3], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[10:11], -v[24:25]
v_add_f64 v[2:3], v[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[16:17], v[14:15], v[10:11]
v_add_f64 v[4:5], v[16:17], -v[10:11]
v_cmp_le_f64_e32 vcc_lo, 0.5, v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[14:15], -v[4:5]
s_and_b32 s1, vcc_lo, exec_lo
s_cselect_b32 s3, 0x3ff00000, 0
v_add_co_ci_u32_e64 v6, s1, 0, v26, vcc_lo
v_add_f64 v[2:3], v[2:3], v[4:5]
v_add_f64 v[4:5], v[16:17], -s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[4:5], v[2:3]
v_mul_f64 v[9:10], v[7:8], s[4:5]
v_add_f64 v[4:5], v[7:8], -v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[11:12], v[7:8], s[4:5], -v[9:10]
v_add_f64 v[2:3], v[2:3], -v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], v[7:8], s[6:7], v[11:12]
v_fma_f64 v[4:5], v[2:3], s[4:5], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[9:10], v[4:5]
v_add_f64 v[7:8], v[2:3], -v[9:10]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], -v[7:8]
s_and_not1_b32 vcc_lo, exec_lo, s2
s_cbranch_vccz .LBB1_7
s_branch .LBB1_8
.LBB1_6:
.LBB1_7:
s_mov_b32 s3, 0x3fe45f30
s_mov_b32 s2, 0x6dc9c883
s_mov_b32 s5, 0xbc91a626
v_mul_f64 v[2:3], v[0:1], s[2:3]
s_mov_b32 s3, 0xbff921fb
s_mov_b32 s2, 0x54442d18
s_mov_b32 s4, 0x33145c00
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[6:7], v[2:3]
v_fma_f64 v[0:1], v[6:7], s[2:3], v[0:1]
v_mul_f64 v[2:3], v[6:7], s[4:5]
s_mov_b32 s3, 0xb97b839a
s_mov_b32 s2, 0x252049c0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[8:9], v[6:7], s[4:5], v[0:1]
v_add_f64 v[4:5], v[0:1], v[2:3]
s_mov_b32 s5, 0x3c91a626
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[0:1], v[0:1], -v[4:5]
v_add_f64 v[4:5], v[4:5], -v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[0:1], v[0:1], v[2:3]
v_fma_f64 v[2:3], v[6:7], s[4:5], v[2:3]
v_add_f64 v[0:1], v[4:5], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], -v[2:3]
v_fma_f64 v[0:1], v[6:7], s[2:3], v[0:1]
v_cvt_i32_f64_e32 v6, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[8:9], v[0:1]
v_add_f64 v[4:5], v[2:3], -v[8:9]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[4:5], v[0:1], -v[4:5]
.LBB1_8:
v_mul_f64 v[0:1], v[2:3], v[2:3]
s_mov_b32 s3, 0xbe5ae600
s_mov_b32 s2, 0xb42fdfa7
s_mov_b32 s5, 0x3de5e0b2
s_mov_b32 s4, 0xf9a43bb8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[15:16], v[4:5], 0.5
v_fma_f64 v[7:8], v[0:1], s[4:5], s[2:3]
s_mov_b32 s5, 0x3ec71de3
s_mov_b32 s4, 0x796cde01
s_mov_b32 s3, 0x3e21eeb6
s_mov_b32 s2, 0x9037ab78
v_mul_f64 v[11:12], v[0:1], 0.5
v_mul_f64 v[17:18], v[2:3], -v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[7:8], v[0:1], v[7:8], s[4:5]
s_mov_b32 s5, 0xbda907db
s_mov_b32 s4, 0x46cc5e42
v_fma_f64 v[9:10], v[0:1], s[4:5], s[2:3]
s_mov_b32 s3, 0xbf2a01a0
s_mov_b32 s2, 0x19e83e5c
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[13:14], -v[11:12], 1.0
v_fma_f64 v[7:8], v[0:1], v[7:8], s[2:3]
s_mov_b32 s3, 0xbe927e4f
s_mov_b32 s2, 0xa17f65f6
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
v_fma_f64 v[9:10], v[0:1], v[9:10], s[2:3]
s_mov_b32 s3, 0x3f811111
s_mov_b32 s2, 0x11110bb3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[19:20], -v[13:14], 1.0
v_fma_f64 v[7:8], v[0:1], v[7:8], s[2:3]
s_mov_b32 s3, 0x3efa01a0
s_mov_b32 s2, 0x19f4ec90
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
v_fma_f64 v[9:10], v[0:1], v[9:10], s[2:3]
s_mov_b32 s3, 0xbf56c16c
s_mov_b32 s2, 0x16c16967
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[11:12], v[19:20], -v[11:12]
v_fma_f64 v[7:8], v[17:18], v[7:8], v[15:16]
v_mul_f64 v[15:16], v[0:1], v[0:1]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[9:10], v[0:1], v[9:10], s[2:3]
s_mov_b32 s3, 0x3fa55555
s_mov_b32 s2, 0x55555555
v_fma_f64 v[7:8], v[0:1], v[7:8], -v[4:5]
v_fma_f64 v[4:5], v[2:3], -v[4:5], v[11:12]
s_delay_alu instid0(VALU_DEP_3)
v_fma_f64 v[0:1], v[0:1], v[9:10], s[2:3]
s_mov_b32 s3, 0xbfc55555
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
v_fma_f64 v[7:8], v[17:18], s[2:3], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[0:1], v[15:16], v[0:1], v[4:5]
v_add_f64 v[2:3], v[2:3], -v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[0:1], v[13:14], v[0:1]
v_xor_b32_e32 v3, 0x80000000, v3
v_and_b32_e32 v4, 1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cmp_eq_u32_e32 vcc_lo, 0, v4
v_lshlrev_b32_e32 v4, 30, v6
v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, 0x80000000, v4
v_cndmask_b32_e64 v0, 0, v0, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v2
v_cndmask_b32_e64 v1, 0x7ff80000, v1, s0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, cosfr@rel32@lo+4
s_addc_u32 s1, s1, cosfr@rel32@hi+12
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v0, v[0:1]
v_mov_b32_e32 v1, 0
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11set_frame_gj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 4
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11set_frame_gj, .Lfunc_end1-_Z11set_frame_gj
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11set_mouse_gff
.globl _Z11set_mouse_gff
.p2align 8
.type _Z11set_mouse_gff,@function
_Z11set_mouse_gff:
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, mouse@rel32@lo+4
s_addc_u32 s3, s3, mouse@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, mouse@rel32@lo+8
s_addc_u32 s5, s5, mouse@rel32@hi+16
s_waitcnt lgkmcnt(0)
v_add_f32_e64 v1, s0, s0
v_add_f32_e64 v2, s1, s1
s_clause 0x1
global_store_b32 v0, v1, s[2:3]
global_store_b32 v0, v2, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11set_mouse_gff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 6
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z11set_mouse_gff, .Lfunc_end2-_Z11set_mouse_gff
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12set_window_gii
.globl _Z12set_window_gii
.p2align 8
.type _Z12set_window_gii,@function
_Z12set_window_gii:
s_load_b64 s[0:1], s[0:1], 0x0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, window@rel32@lo+4
s_addc_u32 s3, s3, window@rel32@hi+12
s_waitcnt lgkmcnt(0)
v_cvt_f32_i32_e32 v1, s0
v_cvt_f32_i32_e32 v2, s1
v_mov_b32_e32 v0, 0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, window@rel32@lo+8
s_addc_u32 s1, s1, window@rel32@hi+16
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, windowD2@rel32@lo+4
s_addc_u32 s5, s5, windowD2@rel32@hi+12
v_mul_f32_e32 v3, 0.5, v1
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, windowD2@rel32@lo+8
s_addc_u32 s7, s7, windowD2@rel32@hi+16
v_mul_f32_e32 v4, 0.5, v2
s_clause 0x3
global_store_b32 v0, v1, s[2:3]
global_store_b32 v0, v2, s[0:1]
global_store_b32 v0, v3, s[4:5]
global_store_b32 v0, v4, s[6:7]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12set_window_gii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z12set_window_gii, .Lfunc_end3-_Z12set_window_gii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected rot
.type rot,@object
.section .bss,"aw",@nobits
.globl rot
.p2align 1, 0x0
rot:
.short 0
.size rot, 2
.protected frame
.type frame,@object
.globl frame
.p2align 2, 0x0
frame:
.long 0x00000000
.size frame, 4
.protected sinfr
.type sinfr,@object
.globl sinfr
.p2align 2, 0x0
sinfr:
.long 0x00000000
.size sinfr, 4
.protected cosfr
.type cosfr,@object
.globl cosfr
.p2align 2, 0x0
cosfr:
.long 0x00000000
.size cosfr, 4
.protected mouse
.type mouse,@object
.globl mouse
.p2align 2, 0x0
mouse:
.zero 8
.size mouse, 8
.protected window
.type window,@object
.globl window
.p2align 2, 0x0
window:
.zero 8
.size window, 8
.protected windowD2
.type windowD2,@object
.globl windowD2
.p2align 2, 0x0
windowD2:
.zero 8
.size windowD2, 8
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym rot
.addrsig_sym frame
.addrsig_sym sinfr
.addrsig_sym cosfr
.addrsig_sym mouse
.addrsig_sym window
.addrsig_sym windowD2
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 2
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 4
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8rotationt
.private_segment_fixed_size: 0
.sgpr_count: 3
.sgpr_spill_count: 0
.symbol: _Z8rotationt.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 4
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11set_frame_gj
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z11set_frame_gj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11set_mouse_gff
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z11set_mouse_gff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12set_window_gii
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z12set_window_gii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__device__ void color(float r, float g, float b, unsigned char* buffer){
if(r>255)
buffer[0] = 255;
else
buffer[0] = (unsigned char)(r);
if(r>255)
buffer[1] = 255;
else
buffer[1] = (unsigned char)(g);
if(r>255)
buffer[2] = 255;
else
buffer[2] = (unsigned char)(b);
}
__device__ struct mat2{
float N[2];
float M[2];
__device__ mat2(float a, float b, float c, float d)
{
N[0] = a;
N[1] = b;
M[0] = c;
M[1] = d;
}
};
__device__ struct vec2{
float x;
float y;
__device__ vec2 (){}
__device__ vec2 (float x, float y): x(x), y(y){}
__device__ vec2 ( float a): x(a),y(a){}
__device__ vec2 operator+(const vec2& v) const
{
return {v.x+x,v.y+y};
}
__device__ vec2 operator-(const vec2& v) const
{
return {x-v.x,y-v.y};
}
};
//vec2 calculations except operators
__device__ float length(vec2 v){
return sqrt(v.x*v.x + v.y*v.y);}
__device__ float dist(vec2 posa, vec2 posb){
float dx,dy;
dx = posa.x - posb.x;
dy = posa.y -posb.y;
return sqrt(dx*dx + dy*dy);}
__device__ vec2 abs(vec2 v){
return {abs(v.x),abs(v.y)};}
//vec3 can begin
__device__ struct vec3 {
float x;
float y;
float z;
//Constructors in different ways
__device__ vec3 (){}
__device__ vec3 (float x, float y, float z):x(x),y(y),z(z){}
__device__ vec3(float a):x(a),y(a),z(a){}
__device__ vec3(vec2 v, float z):x(v.x),y(v.y),z(z){}
__device__ vec3 operator+(const vec3& a) const{
return {a.x + x, a.y+y, a.z+z};}
__device__ vec3 operator-(const vec3& a) const{
return {x-a.x,y-a.y, z-a.z};}
__device__ vec3 operator*(const vec3& a) const{
return {a.x*x, a.y*y , a.z*z };
}
__device__ vec3 operator*(const float a) const{
return {x*a, y*a, z*a};}
__device__ vec3 operator/(const float a) const{
return {x/a, y/a, z/a};}
};
__device__ vec3 cross(vec3 a, vec3 b){
return {a.y*b.z - b.y * a.z, a.z*b.x - b.z*a.x, a.x*b.y -b.x*a.y};
}
__device__ void color(vec3 c, unsigned char* buffer){
if (c.x < 0)
buffer[0] = 0;
else if (c.x > 255)
buffer[0] = 255;
else
buffer[0] = (unsigned char)(c.x);
if (c.y < 0)
buffer[1] = 0;
else if (c.y > 255)
buffer[1] = 255;
else
buffer[1] = (unsigned char)(c.y);
if (c.z < 0)
buffer[2] = 0;
else if (c.z > 255)
buffer[2] = 255;
else
buffer[2] = (unsigned char)(c.z);
}
__device__ float dot(vec3 a, vec3 b){
return a.x*b.x + a.y*b.y + a.z*b.z;}
// I is the Incident vector (direction) and N the Normal vector of the surface
__device__ vec3 reflect(vec3 I, vec3 N){
return I - N *dot(N,I)*2;
}
//can i put this to perators????
__device__ vec3 abs(vec3 v){
return {abs(v.x),abs(v.y),abs(v.z)};}
__device__ float length(vec3 v){
return sqrt(v.x*v.x + v.y*v.y + v.z*v.z);}
__device__ float dist(vec3 a, vec3 b){
float dx,dy,dz;
dx = a.x-b.x;
dy = a.y-b.y;
dz = a.z-b.z;
return sqrt(dx*dx+dy*dy+dz*dz);}
__device__ vec3 normalize(vec3 v){
float betrag = length(v);
return {v.x/betrag,v.y/betrag,v.z/betrag};}
//not sure about the following 2 formulas, a max between a vector and a float seems weird to me
__device__ float mb(float a, float mx){
return a > mx ? a : mx;
}
__device__ vec3 max(vec3 v, float d){
return {mb(v.x,d),
mb(v.y,d),
mb(v.z,d)};}
//i still wonder what i need a 4th dimension for, but we will see
__device__ struct vec4{
float x;
float y;
float z;
float w;
__device__ vec4(){}
__device__ vec4(float x, float y, float z, float w):x(x),y(y),z(z),w(w){}
__device__ vec4(vec3 v, float w): x(v.x), y(v.y), z(v.y), w(w){}
__device__ vec4(float a):x(a),y(a),z(a),w(a){}
__device__ vec4(vec2 v1, vec2 v2): x(v1.x),y(v1.y),z(v2.x),w(v2.y){}
};
//init global rot variable and the functions to set during runtime
//remember that __host__ function always has to be inside extern "C" to be accessed by C-types
//btw check if there might be a less dirty way to acess the __device__ variable from __host__ function
__device__ unsigned short int rot = 0;
__global__ void rotation(unsigned short int angle){
rot = angle;}
extern "C"{__host__ void rotate(unsigned short int angle){
rotation<<<1,1>>>(angle);}}
//same here with the frame
__device__ float frame = 0;
__device__ float sinfr = 0;
__device__ float cosfr = 0;
__global__ void set_frame_g(unsigned int f){
frame = (float)f;
sinfr = sin(frame*M_PI/180);
cosfr = cos(frame*M_PI/180);}
extern "C"{__host__ void set_frame(unsigned int f){
set_frame_g<<<1,1>>>(f);}}
__device__ vec2 mouse;
__global__ void set_mouse_g(float x, float y){
mouse.x = x*2;
mouse.y = y*2;}
extern "C"{__host__ void set_mouse(float x, float y){
set_mouse_g<<<1,1>>>(x,y);}}
__device__ vec2 window;
__device__ vec2 windowD2;
__global__ void set_window_g(int x, int y){
window.x = (float)(x);
window.y = (float)(y);
windowD2.x = (float)(x)/2;
windowD2.y = (float)(y)/2;}
extern "C"{ __host__ void set_window(int x, int y){
set_window_g<<<1,1>>>(x,y);}}
//nice functionalities for floats to have in Shady programming
__device__ float fract(float f){
return f - floor(f);}
__device__ float step(float a, float b){
if (abs(a) < abs(b))
return 1;
else
return 0;}
__device__ float clamp(float x, float minVal, float maxVal){
return min(max(x,minVal),maxVal);}
__device__ vec2 min(vec2 v1, vec2 v2){
if (v1.x<v2.x)
return v1;
else
return v2;
// vec2.y soll in dem Falle die Variable für "solid/glas/mirror" sein, die abstandtsfunktion und so müssen von float auf vec2 geändert werden
//eine neue Funktion dann auch für raymarch innerhalb glas
// und eine für spiegelung
//alternativ eine raymarch funktion erst für glas, dann für spiegel, dann für solids erstellen
}
__device__ vec2 max(vec2 v1, vec2 v2){
if (v1.x>v2.x)
return v1;
else
return v2;
}
__device__ float mix(float v1,float v2, float a){
return v1* (1-a) + v2*a;}
//define smin for vec2 returns....
__device__ float smin(float a, float b, float k){//smooth min, very nice
float h = clamp(0.5 + 0.5 * (b-a)/k,0.1,1.0);
return mix(b,a,h) - k*h*(1.0-h);} | .text
.file "shader.hip"
.globl _Z23__device_stub__rotationt # -- Begin function _Z23__device_stub__rotationt
.p2align 4, 0x90
.type _Z23__device_stub__rotationt,@function
_Z23__device_stub__rotationt: # @_Z23__device_stub__rotationt
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movw %di, 14(%rsp)
leaq 14(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z8rotationt, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z23__device_stub__rotationt, .Lfunc_end0-_Z23__device_stub__rotationt
.cfi_endproc
# -- End function
.globl rotate # -- Begin function rotate
.p2align 4, 0x90
.type rotate,@function
rotate: # @rotate
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
movl %edi, %ebx
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movw %bx, 14(%rsp)
leaq 14(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z8rotationt, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size rotate, .Lfunc_end1-rotate
.cfi_endproc
# -- End function
.globl _Z26__device_stub__set_frame_gj # -- Begin function _Z26__device_stub__set_frame_gj
.p2align 4, 0x90
.type _Z26__device_stub__set_frame_gj,@function
_Z26__device_stub__set_frame_gj: # @_Z26__device_stub__set_frame_gj
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z11set_frame_gj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z26__device_stub__set_frame_gj, .Lfunc_end2-_Z26__device_stub__set_frame_gj
.cfi_endproc
# -- End function
.globl set_frame # -- Begin function set_frame
.p2align 4, 0x90
.type set_frame,@function
set_frame: # @set_frame
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
movl %edi, %ebx
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movl %ebx, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z11set_frame_gj, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size set_frame, .Lfunc_end3-set_frame
.cfi_endproc
# -- End function
.globl _Z26__device_stub__set_mouse_gff # -- Begin function _Z26__device_stub__set_mouse_gff
.p2align 4, 0x90
.type _Z26__device_stub__set_mouse_gff,@function
_Z26__device_stub__set_mouse_gff: # @_Z26__device_stub__set_mouse_gff
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
leaq 12(%rsp), %rax
movq %rax, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11set_mouse_gff, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z26__device_stub__set_mouse_gff, .Lfunc_end4-_Z26__device_stub__set_mouse_gff
.cfi_endproc
# -- End function
.globl set_mouse # -- Begin function set_mouse
.p2align 4, 0x90
.type set_mouse,@function
set_mouse: # @set_mouse
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movss %xmm1, 4(%rsp) # 4-byte Spill
movss %xmm0, (%rsp) # 4-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB5_1
# %bb.2:
addq $88, %rsp
.cfi_def_cfa_offset 8
retq
.LBB5_1:
.cfi_def_cfa_offset 96
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 12(%rsp)
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 8(%rsp)
leaq 12(%rsp), %rax
movq %rax, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11set_mouse_gff, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
addq $88, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size set_mouse, .Lfunc_end5-set_mouse
.cfi_endproc
# -- End function
.globl _Z27__device_stub__set_window_gii # -- Begin function _Z27__device_stub__set_window_gii
.p2align 4, 0x90
.type _Z27__device_stub__set_window_gii,@function
_Z27__device_stub__set_window_gii: # @_Z27__device_stub__set_window_gii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
leaq 12(%rsp), %rax
movq %rax, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12set_window_gii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end6:
.size _Z27__device_stub__set_window_gii, .Lfunc_end6-_Z27__device_stub__set_window_gii
.cfi_endproc
# -- End function
.globl set_window # -- Begin function set_window
.p2align 4, 0x90
.type set_window,@function
set_window: # @set_window
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movl %edi, %ebp
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_2
# %bb.1:
movl %ebp, 12(%rsp)
movl %ebx, 8(%rsp)
leaq 12(%rsp), %rax
movq %rax, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12set_window_gii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_2:
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size set_window, .Lfunc_end7-set_window
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8rotationt, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11set_frame_gj, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11set_mouse_gff, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12set_window_gii, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $rot, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $2, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $frame, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $sinfr, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $cosfr, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $mouse, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $window, %esi
movl $.L__unnamed_10, %edx
movl $.L__unnamed_10, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $windowD2, %esi
movl $.L__unnamed_11, %edx
movl $.L__unnamed_11, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type rot,@object # @rot
.local rot
.comm rot,2,2
.type _Z8rotationt,@object # @_Z8rotationt
.section .rodata,"a",@progbits
.globl _Z8rotationt
.p2align 3, 0x0
_Z8rotationt:
.quad _Z23__device_stub__rotationt
.size _Z8rotationt, 8
.type frame,@object # @frame
.local frame
.comm frame,4,4
.type sinfr,@object # @sinfr
.local sinfr
.comm sinfr,4,4
.type cosfr,@object # @cosfr
.local cosfr
.comm cosfr,4,4
.type _Z11set_frame_gj,@object # @_Z11set_frame_gj
.globl _Z11set_frame_gj
.p2align 3, 0x0
_Z11set_frame_gj:
.quad _Z26__device_stub__set_frame_gj
.size _Z11set_frame_gj, 8
.type mouse,@object # @mouse
.local mouse
.comm mouse,8,4
.type _Z11set_mouse_gff,@object # @_Z11set_mouse_gff
.globl _Z11set_mouse_gff
.p2align 3, 0x0
_Z11set_mouse_gff:
.quad _Z26__device_stub__set_mouse_gff
.size _Z11set_mouse_gff, 8
.type window,@object # @window
.local window
.comm window,8,4
.type windowD2,@object # @windowD2
.local windowD2
.comm windowD2,8,4
.type _Z12set_window_gii,@object # @_Z12set_window_gii
.globl _Z12set_window_gii
.p2align 3, 0x0
_Z12set_window_gii:
.quad _Z27__device_stub__set_window_gii
.size _Z12set_window_gii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8rotationt"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11set_frame_gj"
.size .L__unnamed_2, 17
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z11set_mouse_gff"
.size .L__unnamed_3, 18
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z12set_window_gii"
.size .L__unnamed_4, 19
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "rot"
.size .L__unnamed_5, 4
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "frame"
.size .L__unnamed_6, 6
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "sinfr"
.size .L__unnamed_7, 6
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "cosfr"
.size .L__unnamed_8, 6
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "mouse"
.size .L__unnamed_9, 6
.type .L__unnamed_10,@object # @9
.L__unnamed_10:
.asciz "window"
.size .L__unnamed_10, 7
.type .L__unnamed_11,@object # @10
.L__unnamed_11:
.asciz "windowD2"
.size .L__unnamed_11, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__rotationt
.addrsig_sym _Z26__device_stub__set_frame_gj
.addrsig_sym _Z26__device_stub__set_mouse_gff
.addrsig_sym _Z27__device_stub__set_window_gii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym rot
.addrsig_sym _Z8rotationt
.addrsig_sym frame
.addrsig_sym sinfr
.addrsig_sym cosfr
.addrsig_sym _Z11set_frame_gj
.addrsig_sym mouse
.addrsig_sym _Z11set_mouse_gff
.addrsig_sym window
.addrsig_sym windowD2
.addrsig_sym _Z12set_window_gii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00169bb5_00000000-6_shader.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2100:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2100:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5colorfffPh
.type _Z5colorfffPh, @function
_Z5colorfffPh:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z5colorfffPh, .-_Z5colorfffPh
.globl _Z6length4vec2
.type _Z6length4vec2, @function
_Z6length4vec2:
.LFB2042:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2042:
.size _Z6length4vec2, .-_Z6length4vec2
.globl _Z4dist4vec2S_
.type _Z4dist4vec2S_, @function
_Z4dist4vec2S_:
.LFB2043:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2043:
.size _Z4dist4vec2S_, .-_Z4dist4vec2S_
.globl _Z3abs4vec2
.type _Z3abs4vec2, @function
_Z3abs4vec2:
.LFB2044:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2044:
.size _Z3abs4vec2, .-_Z3abs4vec2
.globl _Z5cross4vec3S_
.type _Z5cross4vec3S_, @function
_Z5cross4vec3S_:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %xmm0, 16(%rsp)
movss %xmm1, 24(%rsp)
movq %xmm2, (%rsp)
movss %xmm3, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z5cross4vec3S_, .-_Z5cross4vec3S_
.globl _Z5color4vec3Ph
.type _Z5color4vec3Ph, @function
_Z5color4vec3Ph:
.LFB2063:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2063:
.size _Z5color4vec3Ph, .-_Z5color4vec3Ph
.globl _Z3dot4vec3S_
.type _Z3dot4vec3S_, @function
_Z3dot4vec3S_:
.LFB2064:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %xmm0, 16(%rsp)
movss %xmm1, 24(%rsp)
movq %xmm2, (%rsp)
movss %xmm3, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2064:
.size _Z3dot4vec3S_, .-_Z3dot4vec3S_
.globl _Z7reflect4vec3S_
.type _Z7reflect4vec3S_, @function
_Z7reflect4vec3S_:
.LFB2065:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %xmm0, 16(%rsp)
movss %xmm1, 24(%rsp)
movq %xmm2, (%rsp)
movss %xmm3, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2065:
.size _Z7reflect4vec3S_, .-_Z7reflect4vec3S_
.globl _Z3abs4vec3
.type _Z3abs4vec3, @function
_Z3abs4vec3:
.LFB2066:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2066:
.size _Z3abs4vec3, .-_Z3abs4vec3
.globl _Z6length4vec3
.type _Z6length4vec3, @function
_Z6length4vec3:
.LFB2067:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2067:
.size _Z6length4vec3, .-_Z6length4vec3
.globl _Z4dist4vec3S_
.type _Z4dist4vec3S_, @function
_Z4dist4vec3S_:
.LFB2068:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %xmm0, 16(%rsp)
movss %xmm1, 24(%rsp)
movq %xmm2, (%rsp)
movss %xmm3, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2068:
.size _Z4dist4vec3S_, .-_Z4dist4vec3S_
.globl _Z9normalize4vec3
.type _Z9normalize4vec3, @function
_Z9normalize4vec3:
.LFB2069:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2069:
.size _Z9normalize4vec3, .-_Z9normalize4vec3
.globl _Z2mbff
.type _Z2mbff, @function
_Z2mbff:
.LFB2070:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2070:
.size _Z2mbff, .-_Z2mbff
.globl _Z3max4vec3f
.type _Z3max4vec3f, @function
_Z3max4vec3f:
.LFB2071:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2071:
.size _Z3max4vec3f, .-_Z3max4vec3f
.globl _Z5fractf
.type _Z5fractf, @function
_Z5fractf:
.LFB2091:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2091:
.size _Z5fractf, .-_Z5fractf
.globl _Z4stepff
.type _Z4stepff, @function
_Z4stepff:
.LFB2092:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2092:
.size _Z4stepff, .-_Z4stepff
.globl _Z5clampfff
.type _Z5clampfff, @function
_Z5clampfff:
.LFB2093:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2093:
.size _Z5clampfff, .-_Z5clampfff
.globl _Z3min4vec2S_
.type _Z3min4vec2S_, @function
_Z3min4vec2S_:
.LFB2094:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2094:
.size _Z3min4vec2S_, .-_Z3min4vec2S_
.globl _Z3max4vec2S_
.type _Z3max4vec2S_, @function
_Z3max4vec2S_:
.LFB2095:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2095:
.size _Z3max4vec2S_, .-_Z3max4vec2S_
.globl _Z3mixfff
.type _Z3mixfff, @function
_Z3mixfff:
.LFB2096:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2096:
.size _Z3mixfff, .-_Z3mixfff
.globl _Z4sminfff
.type _Z4sminfff, @function
_Z4sminfff:
.LFB2097:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2097:
.size _Z4sminfff, .-_Z4sminfff
.globl _Z26__device_stub__Z8rotationtt
.type _Z26__device_stub__Z8rotationtt, @function
_Z26__device_stub__Z8rotationtt:
.LFB2122:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movw %di, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L49
.L45:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8rotationt(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L45
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2122:
.size _Z26__device_stub__Z8rotationtt, .-_Z26__device_stub__Z8rotationtt
.globl _Z8rotationt
.type _Z8rotationt, @function
_Z8rotationt:
.LFB2123:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzwl %di, %edi
call _Z26__device_stub__Z8rotationtt
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2123:
.size _Z8rotationt, .-_Z8rotationt
.globl rotate
.type rotate, @function
rotate:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L56
.L53:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
movzwl %bx, %edi
call _Z26__device_stub__Z8rotationtt
jmp .L53
.cfi_endproc
.LFE2087:
.size rotate, .-rotate
.globl _Z30__device_stub__Z11set_frame_gjj
.type _Z30__device_stub__Z11set_frame_gjj, @function
_Z30__device_stub__Z11set_frame_gjj:
.LFB2124:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L61
.L57:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L62
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11set_frame_gj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L57
.L62:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2124:
.size _Z30__device_stub__Z11set_frame_gjj, .-_Z30__device_stub__Z11set_frame_gjj
.globl _Z11set_frame_gj
.type _Z11set_frame_gj, @function
_Z11set_frame_gj:
.LFB2125:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z11set_frame_gjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2125:
.size _Z11set_frame_gj, .-_Z11set_frame_gj
.globl set_frame
.type set_frame, @function
set_frame:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L68
.L65:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
movl %ebx, %edi
call _Z30__device_stub__Z11set_frame_gjj
jmp .L65
.cfi_endproc
.LFE2088:
.size set_frame, .-set_frame
.globl _Z31__device_stub__Z11set_mouse_gffff
.type _Z31__device_stub__Z11set_mouse_gffff, @function
_Z31__device_stub__Z11set_mouse_gffff:
.LFB2126:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L73
.L69:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L74
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L73:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11set_mouse_gff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L69
.L74:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2126:
.size _Z31__device_stub__Z11set_mouse_gffff, .-_Z31__device_stub__Z11set_mouse_gffff
.globl _Z11set_mouse_gff
.type _Z11set_mouse_gff, @function
_Z11set_mouse_gff:
.LFB2127:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z11set_mouse_gffff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2127:
.size _Z11set_mouse_gff, .-_Z11set_mouse_gff
.globl set_mouse
.type set_mouse, @function
set_mouse:
.LFB2089:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movss %xmm0, 8(%rsp)
movss %xmm1, 12(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L80
.L77:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L80:
.cfi_restore_state
movss 12(%rsp), %xmm1
movss 8(%rsp), %xmm0
call _Z31__device_stub__Z11set_mouse_gffff
jmp .L77
.cfi_endproc
.LFE2089:
.size set_mouse, .-set_mouse
.globl _Z32__device_stub__Z12set_window_giiii
.type _Z32__device_stub__Z12set_window_giiii, @function
_Z32__device_stub__Z12set_window_giiii:
.LFB2128:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L85
.L81:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L86
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L85:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12set_window_gii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L81
.L86:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2128:
.size _Z32__device_stub__Z12set_window_giiii, .-_Z32__device_stub__Z12set_window_giiii
.globl _Z12set_window_gii
.type _Z12set_window_gii, @function
_Z12set_window_gii:
.LFB2129:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z12set_window_giiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2129:
.size _Z12set_window_gii, .-_Z12set_window_gii
.globl set_window
.type set_window, @function
set_window:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movl %edi, %ebx
movl %esi, %ebp
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L92
.L89:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L92:
.cfi_restore_state
movl %ebp, %esi
movl %ebx, %edi
call _Z32__device_stub__Z12set_window_giiii
jmp .L89
.cfi_endproc
.LFE2090:
.size set_window, .-set_window
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12set_window_gii"
.LC1:
.string "_Z11set_mouse_gff"
.LC2:
.string "_Z11set_frame_gj"
.LC3:
.string "_Z8rotationt"
.LC4:
.string "rot"
.LC5:
.string "frame"
.LC6:
.string "sinfr"
.LC7:
.string "cosfr"
.LC8:
.string "mouse"
.LC9:
.string "window"
.LC10:
.string "windowD2"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2131:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12set_window_gii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11set_mouse_gff(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z11set_frame_gj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8rotationt(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3rot(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5frame(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5sinfr(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5cosfr(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5mouse(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6window(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8windowD2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2131:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.text
.type _GLOBAL__sub_I__Z5colorfffPh, @function
_GLOBAL__sub_I__Z5colorfffPh:
.LFB2248:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq $0, 8(%rsp)
movq 8(%rsp), %rdi
call free@PLT
movq $0, 16(%rsp)
movq 16(%rsp), %rdi
call free@PLT
movq $0, 24(%rsp)
movq 24(%rsp), %rdi
call free@PLT
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2248:
.size _GLOBAL__sub_I__Z5colorfffPh, .-_GLOBAL__sub_I__Z5colorfffPh
.section .init_array
.align 8
.quad _GLOBAL__sub_I__Z5colorfffPh
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL8windowD2
.comm _ZL8windowD2,8,8
.local _ZL6window
.comm _ZL6window,8,8
.local _ZL5mouse
.comm _ZL5mouse,8,8
.local _ZL5cosfr
.comm _ZL5cosfr,4,4
.local _ZL5sinfr
.comm _ZL5sinfr,4,4
.local _ZL5frame
.comm _ZL5frame,4,4
.local _ZL3rot
.comm _ZL3rot,2,2
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "shader.hip"
.globl _Z23__device_stub__rotationt # -- Begin function _Z23__device_stub__rotationt
.p2align 4, 0x90
.type _Z23__device_stub__rotationt,@function
_Z23__device_stub__rotationt: # @_Z23__device_stub__rotationt
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movw %di, 14(%rsp)
leaq 14(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z8rotationt, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z23__device_stub__rotationt, .Lfunc_end0-_Z23__device_stub__rotationt
.cfi_endproc
# -- End function
.globl rotate # -- Begin function rotate
.p2align 4, 0x90
.type rotate,@function
rotate: # @rotate
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
movl %edi, %ebx
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movw %bx, 14(%rsp)
leaq 14(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z8rotationt, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size rotate, .Lfunc_end1-rotate
.cfi_endproc
# -- End function
.globl _Z26__device_stub__set_frame_gj # -- Begin function _Z26__device_stub__set_frame_gj
.p2align 4, 0x90
.type _Z26__device_stub__set_frame_gj,@function
_Z26__device_stub__set_frame_gj: # @_Z26__device_stub__set_frame_gj
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z11set_frame_gj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z26__device_stub__set_frame_gj, .Lfunc_end2-_Z26__device_stub__set_frame_gj
.cfi_endproc
# -- End function
.globl set_frame # -- Begin function set_frame
.p2align 4, 0x90
.type set_frame,@function
set_frame: # @set_frame
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
movl %edi, %ebx
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movl %ebx, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z11set_frame_gj, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size set_frame, .Lfunc_end3-set_frame
.cfi_endproc
# -- End function
.globl _Z26__device_stub__set_mouse_gff # -- Begin function _Z26__device_stub__set_mouse_gff
.p2align 4, 0x90
.type _Z26__device_stub__set_mouse_gff,@function
_Z26__device_stub__set_mouse_gff: # @_Z26__device_stub__set_mouse_gff
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
leaq 12(%rsp), %rax
movq %rax, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11set_mouse_gff, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z26__device_stub__set_mouse_gff, .Lfunc_end4-_Z26__device_stub__set_mouse_gff
.cfi_endproc
# -- End function
.globl set_mouse # -- Begin function set_mouse
.p2align 4, 0x90
.type set_mouse,@function
set_mouse: # @set_mouse
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movss %xmm1, 4(%rsp) # 4-byte Spill
movss %xmm0, (%rsp) # 4-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB5_1
# %bb.2:
addq $88, %rsp
.cfi_def_cfa_offset 8
retq
.LBB5_1:
.cfi_def_cfa_offset 96
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 12(%rsp)
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 8(%rsp)
leaq 12(%rsp), %rax
movq %rax, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11set_mouse_gff, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
addq $88, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size set_mouse, .Lfunc_end5-set_mouse
.cfi_endproc
# -- End function
.globl _Z27__device_stub__set_window_gii # -- Begin function _Z27__device_stub__set_window_gii
.p2align 4, 0x90
.type _Z27__device_stub__set_window_gii,@function
_Z27__device_stub__set_window_gii: # @_Z27__device_stub__set_window_gii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
leaq 12(%rsp), %rax
movq %rax, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12set_window_gii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end6:
.size _Z27__device_stub__set_window_gii, .Lfunc_end6-_Z27__device_stub__set_window_gii
.cfi_endproc
# -- End function
.globl set_window # -- Begin function set_window
.p2align 4, 0x90
.type set_window,@function
set_window: # @set_window
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movl %edi, %ebp
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_2
# %bb.1:
movl %ebp, 12(%rsp)
movl %ebx, 8(%rsp)
leaq 12(%rsp), %rax
movq %rax, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12set_window_gii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_2:
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size set_window, .Lfunc_end7-set_window
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8rotationt, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11set_frame_gj, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11set_mouse_gff, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12set_window_gii, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $rot, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $2, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $frame, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $sinfr, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $cosfr, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $mouse, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $window, %esi
movl $.L__unnamed_10, %edx
movl $.L__unnamed_10, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $windowD2, %esi
movl $.L__unnamed_11, %edx
movl $.L__unnamed_11, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type rot,@object # @rot
.local rot
.comm rot,2,2
.type _Z8rotationt,@object # @_Z8rotationt
.section .rodata,"a",@progbits
.globl _Z8rotationt
.p2align 3, 0x0
_Z8rotationt:
.quad _Z23__device_stub__rotationt
.size _Z8rotationt, 8
.type frame,@object # @frame
.local frame
.comm frame,4,4
.type sinfr,@object # @sinfr
.local sinfr
.comm sinfr,4,4
.type cosfr,@object # @cosfr
.local cosfr
.comm cosfr,4,4
.type _Z11set_frame_gj,@object # @_Z11set_frame_gj
.globl _Z11set_frame_gj
.p2align 3, 0x0
_Z11set_frame_gj:
.quad _Z26__device_stub__set_frame_gj
.size _Z11set_frame_gj, 8
.type mouse,@object # @mouse
.local mouse
.comm mouse,8,4
.type _Z11set_mouse_gff,@object # @_Z11set_mouse_gff
.globl _Z11set_mouse_gff
.p2align 3, 0x0
_Z11set_mouse_gff:
.quad _Z26__device_stub__set_mouse_gff
.size _Z11set_mouse_gff, 8
.type window,@object # @window
.local window
.comm window,8,4
.type windowD2,@object # @windowD2
.local windowD2
.comm windowD2,8,4
.type _Z12set_window_gii,@object # @_Z12set_window_gii
.globl _Z12set_window_gii
.p2align 3, 0x0
_Z12set_window_gii:
.quad _Z27__device_stub__set_window_gii
.size _Z12set_window_gii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8rotationt"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11set_frame_gj"
.size .L__unnamed_2, 17
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z11set_mouse_gff"
.size .L__unnamed_3, 18
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z12set_window_gii"
.size .L__unnamed_4, 19
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "rot"
.size .L__unnamed_5, 4
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "frame"
.size .L__unnamed_6, 6
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "sinfr"
.size .L__unnamed_7, 6
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "cosfr"
.size .L__unnamed_8, 6
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "mouse"
.size .L__unnamed_9, 6
.type .L__unnamed_10,@object # @9
.L__unnamed_10:
.asciz "window"
.size .L__unnamed_10, 7
.type .L__unnamed_11,@object # @10
.L__unnamed_11:
.asciz "windowD2"
.size .L__unnamed_11, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__rotationt
.addrsig_sym _Z26__device_stub__set_frame_gj
.addrsig_sym _Z26__device_stub__set_mouse_gff
.addrsig_sym _Z27__device_stub__set_window_gii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym rot
.addrsig_sym _Z8rotationt
.addrsig_sym frame
.addrsig_sym sinfr
.addrsig_sym cosfr
.addrsig_sym _Z11set_frame_gj
.addrsig_sym mouse
.addrsig_sym _Z11set_mouse_gff
.addrsig_sym window
.addrsig_sym windowD2
.addrsig_sym _Z12set_window_gii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void UnpackPointers(int *minmax, int *ptrs, int w, int h, int maxPts)
{
const int tx = threadIdx.x;
int numPts = 0;
for (int y=0;y<h/32;y++) {
for (int x=0;x<w;x+=16) {
unsigned int val = minmax[y*w+x+tx];
if (val) {
for (int k=0;k<32;k++) {
if (val&0x1 && numPts<maxPts) {
ptrs[16*numPts+tx] = (y*32+k)*w + x+tx;
numPts++;
}
val >>= 1;
}
}
}
}
} | code for sm_80
Function : _Z14UnpackPointersPiS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe40000000a00 */
/*0020*/ UISETP.GE.AND UP0, UPT, UR6, 0x1, UPT ; /* 0x000000010600788c */
/* 0x000fc8000bf06270 */
/*0030*/ UISETP.LT.OR UP0, UPT, UR7, 0x20, !UP0 ; /* 0x000000200700788c */
/* 0x000fcc000c701670 */
/*0040*/ PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0003f0f008 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0070*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR7 ; /* 0x0000001f3f047899 */
/* 0x000fe20008011407 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC UR5, c[0x0][0x174] ; /* 0x00005d0000057ab9 */
/* 0x000fe40000000800 */
/*00a0*/ ULEA.HI UR4, UR4, UR5, URZ, 0x5 ; /* 0x0000000504047291 */
/* 0x000fe4000f8f283f */
/*00b0*/ USHF.L.U32 UR7, UR6, 0x5, URZ ; /* 0x0000000506077899 */
/* 0x000fe4000800063f */
/*00c0*/ USHF.R.S32.HI UR8, URZ, 0x5, UR4 ; /* 0x000000053f087899 */
/* 0x000fe40008011404 */
/*00d0*/ ULDC.64 UR14, c[0x0][0x118] ; /* 0x00004600000e7ab9 */
/* 0x000fc40000000a00 */
/*00e0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*00f0*/ USHF.L.U32 UR5, UR4, 0x5, URZ ; /* 0x0000000504057899 */
/* 0x000fe2000800063f */
/*0100*/ IMAD.U32 R4, RZ, RZ, UR7 ; /* 0x00000007ff047e24 */
/* 0x000fe4000f8e00ff */
/*0110*/ IMAD.U32 R2, RZ, RZ, UR4 ; /* 0x00000004ff027e24 */
/* 0x000fe2000f8e00ff */
/*0120*/ UIADD3 UR6, UR5, 0x7, URZ ; /* 0x0000000705067890 */
/* 0x000fe2000fffe03f */
/*0130*/ IMAD R4, R4, UR4, R3.reuse ; /* 0x0000000404047c24 */
/* 0x101fe2000f8e0203 */
/*0140*/ UIADD3 UR9, UR5, 0x6, URZ ; /* 0x0000000605097890 */
/* 0x000fe2000fffe03f */
/*0150*/ IMAD R2, R2, c[0x0][0x170], R3.reuse ; /* 0x00005c0002027a24 */
/* 0x100fe200078e0203 */
/*0160*/ UIADD3 UR10, UR5, 0x5, URZ ; /* 0x00000005050a7890 */
/* 0x000fe4000fffe03f */
/*0170*/ UIADD3 UR11, UR5, 0x4, URZ ; /* 0x00000004050b7890 */
/* 0x000fe2000fffe03f */
/*0180*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0190*/ UIADD3 UR12, UR5, 0x3, URZ ; /* 0x00000003050c7890 */
/* 0x000fe2000fffe03f */
/*01a0*/ IMAD.U32 R8, RZ, RZ, UR9 ; /* 0x00000009ff087e24 */
/* 0x000fe2000f8e00ff */
/*01b0*/ UIADD3 UR13, UR5, 0x2, URZ ; /* 0x00000002050d7890 */
/* 0x000fe2000fffe03f */
/*01c0*/ IMAD.U32 R10, RZ, RZ, UR10 ; /* 0x0000000aff0a7e24 */
/* 0x000fe2000f8e00ff */
/*01d0*/ UIADD3 UR5, UR5, 0x1, URZ ; /* 0x0000000105057890 */
/* 0x000fe2000fffe03f */
/*01e0*/ IMAD.U32 R12, RZ, RZ, UR11 ; /* 0x0000000bff0c7e24 */
/* 0x000fe2000f8e00ff */
/*01f0*/ MOV R14, UR12 ; /* 0x0000000c000e7c02 */
/* 0x000fe20008000f00 */
/*0200*/ IMAD R5, R6, c[0x0][0x170], R3 ; /* 0x00005c0006057a24 */
/* 0x000fe200078e0203 */
/*0210*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0220*/ IMAD.U32 R16, RZ, RZ, UR13 ; /* 0x0000000dff107e24 */
/* 0x000fc4000f8e00ff */
/*0230*/ IMAD.U32 R18, RZ, RZ, UR5 ; /* 0x00000005ff127e24 */
/* 0x000fe2000f8e00ff */
/*0240*/ UISETP.GE.AND UP0, UPT, UR4, UR8, UPT ; /* 0x000000080400728c */
/* 0x000fe2000bf06270 */
/*0250*/ IMAD R6, R8, c[0x0][0x170], R3.reuse ; /* 0x00005c0008067a24 */
/* 0x100fe200078e0203 */
/*0260*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*0270*/ IMAD R7, R10, c[0x0][0x170], R3.reuse ; /* 0x00005c000a077a24 */
/* 0x100fe400078e0203 */
/*0280*/ IMAD R8, R12, c[0x0][0x170], R3.reuse ; /* 0x00005c000c087a24 */
/* 0x100fe400078e0203 */
/*0290*/ IMAD R9, R14, c[0x0][0x170], R3.reuse ; /* 0x00005c000e097a24 */
/* 0x100fe400078e0203 */
/*02a0*/ IMAD R10, R16, c[0x0][0x170], R3 ; /* 0x00005c00100a7a24 */
/* 0x000fc400078e0203 */
/*02b0*/ IMAD R11, R18, c[0x0][0x170], R3 ; /* 0x00005c00120b7a24 */
/* 0x000fe400078e0203 */
/*02c0*/ IADD3 R12, R2, UR5, RZ ; /* 0x00000005020c7c10 */
/* 0x000fe2000fffe0ff */
/*02d0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fc800078e00ff */
/*02e0*/ IMAD.WIDE R12, R12, R13, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fcc00078e020d */
/*02f0*/ LDG.E R13, [R12.64] ; /* 0x0000000e0c0d7981 */
/* 0x000ea2000c1e1900 */
/*0300*/ BSSY B0, 0x840 ; /* 0x0000053000007945 */
/* 0x000fe20003800000 */
/*0310*/ ISETP.NE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x004fda0003f05270 */
/*0320*/ @!P0 BRA 0x830 ; /* 0x0000050000008947 */
/* 0x000fea0003800000 */
/*0330*/ IADD3 R23, R5, UR5, RZ ; /* 0x0000000505177c10 */
/* 0x000fe2000fffe0ff */
/*0340*/ UMOV UR6, URZ ; /* 0x0000003f00067c82 */
/* 0x000fe20008000000 */
/*0350*/ IADD3 R25, R6, UR5, RZ ; /* 0x0000000506197c10 */
/* 0x000fe4000fffe0ff */
/*0360*/ IADD3 R27, R7, UR5, RZ ; /* 0x00000005071b7c10 */
/* 0x000fe4000fffe0ff */
/*0370*/ IADD3 R29, R8, UR5, RZ ; /* 0x00000005081d7c10 */
/* 0x000fe4000fffe0ff */
/*0380*/ IADD3 R22, R9, UR5, RZ ; /* 0x0000000509167c10 */
/* 0x000fe4000fffe0ff */
/*0390*/ IADD3 R24, R10, UR5, RZ ; /* 0x000000050a187c10 */
/* 0x000fc4000fffe0ff */
/*03a0*/ IADD3 R12, R11, UR5, RZ ; /* 0x000000050b0c7c10 */
/* 0x000fe4000fffe0ff */
/*03b0*/ IADD3 R26, R4, UR5, RZ ; /* 0x00000005041a7c10 */
/* 0x000fe4000fffe0ff */
/*03c0*/ LOP3.LUT R14, R13.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x000000010d0e7812 */
/* 0x040fe200078ec0ff */
/*03d0*/ UIADD3 UR6, UR6, 0x8, URZ ; /* 0x0000000806067890 */
/* 0x000fe2000fffe03f */
/*03e0*/ LOP3.LUT P4, RZ, R13.reuse, 0x2, RZ, 0xc0, !PT ; /* 0x000000020dff7812 */
/* 0x040fe4000788c0ff */
/*03f0*/ ISETP.NE.U32.AND P1, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fe20003f25070 */
/*0400*/ UISETP.NE.AND UP1, UPT, UR6, 0x20, UPT ; /* 0x000000200600788c */
/* 0x000fe2000bf25270 */
/*0410*/ LOP3.LUT P3, RZ, R13, 0x4, RZ, 0xc0, !PT ; /* 0x000000040dff7812 */
/* 0x000fe4000786c0ff */
/*0420*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x178], P1 ; /* 0x00005e0000007a0c */
/* 0x000fc40000f26670 */
/*0430*/ LOP3.LUT P2, RZ, R13.reuse, 0x8, RZ, 0xc0, !PT ; /* 0x000000080dff7812 */
/* 0x040fe4000784c0ff */
/*0440*/ LOP3.LUT P0, RZ, R13, 0x10, RZ, 0xc0, !PT ; /* 0x000000100dff7812 */
/* 0x000fd2000780c0ff */
/*0450*/ @!P1 LEA R16, R0.reuse, R3, 0x4 ; /* 0x0000000300109211 */
/* 0x040fe400078e20ff */
/*0460*/ @!P1 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100009810 */
/* 0x000fe40007ffe0ff */
/*0470*/ @!P1 MOV R17, 0x4 ; /* 0x0000000400119802 */
/* 0x000fe40000000f00 */
/*0480*/ ISETP.GE.OR P4, PT, R0, c[0x0][0x178], !P4 ; /* 0x00005e0000007a0c */
/* 0x000fc60006786670 */
/*0490*/ @!P1 IMAD.WIDE R16, R16, R17, c[0x0][0x168] ; /* 0x00005a0010109625 */
/* 0x000fca00078e0211 */
/*04a0*/ @!P1 STG.E [R16.64], R26 ; /* 0x0000001a10009986 */
/* 0x000fe2000c10190e */
/*04b0*/ LOP3.LUT P1, RZ, R13, 0x20, RZ, 0xc0, !PT ; /* 0x000000200dff7812 */
/* 0x000fc8000782c0ff */
/*04c0*/ @!P4 IMAD R14, R0.reuse, 0x10, R3 ; /* 0x00000010000ec824 */
/* 0x040fe200078e0203 */
/*04d0*/ @!P4 IADD3 R0, R0, 0x1, RZ ; /* 0x000000010000c810 */
/* 0x000fe20007ffe0ff */
/*04e0*/ @!P4 IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0fc424 */
/* 0x000fc600078e00ff */
/*04f0*/ ISETP.GE.OR P3, PT, R0, c[0x0][0x178], !P3 ; /* 0x00005e0000007a0c */
/* 0x000fe20005f66670 */
/*0500*/ @!P4 IMAD.WIDE R14, R14, R15, c[0x0][0x168] ; /* 0x00005a000e0ec625 */
/* 0x000fca00078e020f */
/*0510*/ @!P4 STG.E [R14.64], R12 ; /* 0x0000000c0e00c986 */
/* 0x0001e2000c10190e */
/*0520*/ LOP3.LUT P4, RZ, R13, 0x40, RZ, 0xc0, !PT ; /* 0x000000400dff7812 */
/* 0x000fcc000788c0ff */
/*0530*/ @!P3 IMAD R20, R0.reuse, 0x10, R3 ; /* 0x000000100014b824 */
/* 0x040fe200078e0203 */
/*0540*/ @!P3 IADD3 R0, R0, 0x1, RZ ; /* 0x000000010000b810 */
/* 0x000fe40007ffe0ff */
/*0550*/ @!P3 MOV R21, 0x4 ; /* 0x000000040015b802 */
/* 0x000fe40000000f00 */
/*0560*/ ISETP.GE.OR P2, PT, R0, c[0x0][0x178], !P2 ; /* 0x00005e0000007a0c */
/* 0x000fc60005746670 */
/*0570*/ @!P3 IMAD.WIDE R20, R20, R21, c[0x0][0x168] ; /* 0x00005a001414b625 */
/* 0x000fca00078e0215 */
/*0580*/ @!P3 STG.E [R20.64], R24 ; /* 0x000000181400b986 */
/* 0x000fe2000c10190e */
/*0590*/ LOP3.LUT P3, RZ, R13, 0x80, RZ, 0xc0, !PT ; /* 0x000000800dff7812 */
/* 0x000fe4000786c0ff */
/*05a0*/ SHF.R.U32.HI R13, RZ, 0x8, R13 ; /* 0x00000008ff0d7819 */
/* 0x000fe4000001160d */
/*05b0*/ @!P2 IMAD R18, R0.reuse, 0x10, R3 ; /* 0x000000100012a824 */
/* 0x040fe200078e0203 */
/*05c0*/ @!P2 IADD3 R0, R0, 0x1, RZ ; /* 0x000000010000a810 */
/* 0x000fe20007ffe0ff */
/*05d0*/ @!P2 IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; /* 0x00000004ff13a424 */
/* 0x000fc600078e00ff */
/*05e0*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], !P0 ; /* 0x00005e0000007a0c */
/* 0x000fe20004706670 */
/*05f0*/ @!P2 IMAD.WIDE R18, R18, R19, c[0x0][0x168] ; /* 0x00005a001212a625 */
/* 0x000fca00078e0213 */
/*0600*/ @!P2 STG.E [R18.64], R22 ; /* 0x000000161200a986 */
/* 0x000fee000c10190e */
/*0610*/ @!P0 IMAD R28, R0.reuse, 0x10, R3 ; /* 0x00000010001c8824 */
/* 0x040fe200078e0203 */
/*0620*/ @!P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100008810 */
/* 0x000fe20007ffe0ff */
/*0630*/ @!P0 IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f8424 */
/* 0x001fc600078e00ff */
/*0640*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x178], !P1 ; /* 0x00005e0000007a0c */
/* 0x000fe20004f26670 */
/*0650*/ @!P0 IMAD.WIDE R14, R28, R15, c[0x0][0x168] ; /* 0x00005a001c0e8625 */
/* 0x000fca00078e020f */
/*0660*/ @!P0 STG.E [R14.64], R29 ; /* 0x0000001d0e008986 */
/* 0x0001e2000c10190e */
/*0670*/ PLOP3.LUT P0, PT, PT, PT, UP1, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fcc0003f0f018 */
/*0680*/ @!P1 IMAD R16, R0.reuse, 0x10, R3 ; /* 0x0000001000109824 */
/* 0x040fe200078e0203 */
/*0690*/ @!P1 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100009810 */
/* 0x000fe40007ffe0ff */
/*06a0*/ @!P1 MOV R17, 0x4 ; /* 0x0000000400119802 */
/* 0x000fe40000000f00 */
/*06b0*/ ISETP.GE.OR P4, PT, R0, c[0x0][0x178], !P4 ; /* 0x00005e0000007a0c */
/* 0x000fe40006786670 */
/*06c0*/ MOV R14, c[0x0][0x170] ; /* 0x00005c00000e7a02 */
/* 0x001fe20000000f00 */
/*06d0*/ @!P1 IMAD.WIDE R16, R16, R17, c[0x0][0x168] ; /* 0x00005a0010109625 */
/* 0x000fc600078e0211 */
/*06e0*/ LEA R22, R14.reuse, R22, 0x3 ; /* 0x000000160e167211 */
/* 0x040fe200078e18ff */
/*06f0*/ IMAD R26, R14.reuse, 0x8, R26 ; /* 0x000000080e1a7824 */
/* 0x040fe200078e021a */
/*0700*/ @!P1 STG.E [R16.64], R27 ; /* 0x0000001b10009986 */
/* 0x0001e2000c10190e */
/*0710*/ IMAD R12, R14.reuse, 0x8, R12 ; /* 0x000000080e0c7824 */
/* 0x040fe400078e020c */
/*0720*/ IMAD R24, R14, 0x8, R24 ; /* 0x000000080e187824 */
/* 0x000fe400078e0218 */
/*0730*/ @!P4 IMAD R20, R0.reuse, 0x10, R3 ; /* 0x000000100014c824 */
/* 0x040fe200078e0203 */
/*0740*/ @!P4 IADD3 R0, R0, 0x1, RZ ; /* 0x000000010000c810 */
/* 0x000fe20007ffe0ff */
/*0750*/ @!P4 IMAD.MOV.U32 R21, RZ, RZ, 0x4 ; /* 0x00000004ff15c424 */
/* 0x000fe400078e00ff */
/*0760*/ IMAD R29, R14, 0x8, R29 ; /* 0x000000080e1d7824 */
/* 0x000fe200078e021d */
/*0770*/ ISETP.GE.OR P2, PT, R0, c[0x0][0x178], !P3 ; /* 0x00005e0000007a0c */
/* 0x000fe20005f46670 */
/*0780*/ @!P4 IMAD.WIDE R18, R20, R21, c[0x0][0x168] ; /* 0x00005a001412c625 */
/* 0x000fc800078e0215 */
/*0790*/ IMAD R27, R14, 0x8, R27 ; /* 0x000000080e1b7824 */
/* 0x001fe200078e021b */
/*07a0*/ @!P4 STG.E [R18.64], R25 ; /* 0x000000191200c986 */
/* 0x0001ee000c10190e */
/*07b0*/ @!P2 IMAD R28, R0.reuse, 0x10, R3 ; /* 0x00000010001ca824 */
/* 0x040fe200078e0203 */
/*07c0*/ @!P2 IADD3 R0, R0, 0x1, RZ ; /* 0x000000010000a810 */
/* 0x000fe20007ffe0ff */
/*07d0*/ @!P2 IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0fa424 */
/* 0x000fe200078e00ff */
/*07e0*/ LEA R25, R14, R25, 0x3 ; /* 0x000000190e197211 */
/* 0x001fc600078e18ff */
/*07f0*/ @!P2 IMAD.WIDE R20, R28, R15, c[0x0][0x168] ; /* 0x00005a001c14a625 */
/* 0x000fca00078e020f */
/*0800*/ @!P2 STG.E [R20.64], R23 ; /* 0x000000171400a986 */
/* 0x0001e4000c10190e */
/*0810*/ IMAD R23, R14, 0x8, R23 ; /* 0x000000080e177824 */
/* 0x001fe200078e0217 */
/*0820*/ @P0 BRA 0x3c0 ; /* 0xfffffb9000000947 */
/* 0x000fea000383ffff */
/*0830*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0840*/ UIADD3 UR5, UR5, 0x10, URZ ; /* 0x0000001005057890 */
/* 0x000fe4000fffe03f */
/*0850*/ ULDC UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe40000000800 */
/*0860*/ UISETP.GE.AND UP1, UPT, UR5, UR6, UPT ; /* 0x000000060500728c */
/* 0x000fcc000bf26270 */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, UP1, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0003f0f018 */
/*0880*/ @!P0 BRA 0x2c0 ; /* 0xfffffa3000008947 */
/* 0x000fea000383ffff */
/*0890*/ PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0003f0f008 */
/*08a0*/ @!P0 BRA 0xf0 ; /* 0xfffff84000008947 */
/* 0x000fea000383ffff */
/*08b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08c0*/ BRA 0x8c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void UnpackPointers(int *minmax, int *ptrs, int w, int h, int maxPts)
{
const int tx = threadIdx.x;
int numPts = 0;
for (int y=0;y<h/32;y++) {
for (int x=0;x<w;x+=16) {
unsigned int val = minmax[y*w+x+tx];
if (val) {
for (int k=0;k<32;k++) {
if (val&0x1 && numPts<maxPts) {
ptrs[16*numPts+tx] = (y*32+k)*w + x+tx;
numPts++;
}
val >>= 1;
}
}
}
}
} | .file "tmpxft_0004bb9a_00000000-6_UnpackPointers.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z14UnpackPointersPiS_iiiPiS_iii
.type _Z39__device_stub__Z14UnpackPointersPiS_iiiPiS_iii, @function
_Z39__device_stub__Z14UnpackPointersPiS_iiiPiS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14UnpackPointersPiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z14UnpackPointersPiS_iiiPiS_iii, .-_Z39__device_stub__Z14UnpackPointersPiS_iiiPiS_iii
.globl _Z14UnpackPointersPiS_iii
.type _Z14UnpackPointersPiS_iii, @function
_Z14UnpackPointersPiS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14UnpackPointersPiS_iiiPiS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14UnpackPointersPiS_iii, .-_Z14UnpackPointersPiS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14UnpackPointersPiS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14UnpackPointersPiS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void UnpackPointers(int *minmax, int *ptrs, int w, int h, int maxPts)
{
const int tx = threadIdx.x;
int numPts = 0;
for (int y=0;y<h/32;y++) {
for (int x=0;x<w;x+=16) {
unsigned int val = minmax[y*w+x+tx];
if (val) {
for (int k=0;k<32;k++) {
if (val&0x1 && numPts<maxPts) {
ptrs[16*numPts+tx] = (y*32+k)*w + x+tx;
numPts++;
}
val >>= 1;
}
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void UnpackPointers(int *minmax, int *ptrs, int w, int h, int maxPts)
{
const int tx = threadIdx.x;
int numPts = 0;
for (int y=0;y<h/32;y++) {
for (int x=0;x<w;x+=16) {
unsigned int val = minmax[y*w+x+tx];
if (val) {
for (int k=0;k<32;k++) {
if (val&0x1 && numPts<maxPts) {
ptrs[16*numPts+tx] = (y*32+k)*w + x+tx;
numPts++;
}
val >>= 1;
}
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void UnpackPointers(int *minmax, int *ptrs, int w, int h, int maxPts)
{
const int tx = threadIdx.x;
int numPts = 0;
for (int y=0;y<h/32;y++) {
for (int x=0;x<w;x+=16) {
unsigned int val = minmax[y*w+x+tx];
if (val) {
for (int k=0;k<32;k++) {
if (val&0x1 && numPts<maxPts) {
ptrs[16*numPts+tx] = (y*32+k)*w + x+tx;
numPts++;
}
val >>= 1;
}
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14UnpackPointersPiS_iii
.globl _Z14UnpackPointersPiS_iii
.p2align 8
.type _Z14UnpackPointersPiS_iii,@function
_Z14UnpackPointersPiS_iii:
s_load_b32 s3, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 32
s_cbranch_scc1 .LBB0_11
s_clause 0x2
s_load_b32 s2, s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s1, s[0:1], 0x18
s_ashr_i32 s0, s3, 31
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, v0
s_lshr_b32 s0, s0, 27
s_mov_b32 s9, 0
s_add_i32 s3, s3, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s3, s3, 5
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s2, 0
s_cselect_b32 s8, -1, 0
s_lshl_b32 s10, s2, 5
s_branch .LBB0_3
.LBB0_2:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v4, s10, v4
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, s3
s_cbranch_scc1 .LBB0_11
.LBB0_3:
s_and_not1_b32 vcc_lo, exec_lo, s8
s_cbranch_vccnz .LBB0_2
v_mad_u64_u32 v[1:2], null, s9, s2, v[0:1]
v_mov_b32_e32 v2, v4
s_mov_b32 s11, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s12
v_add_nc_u32_e32 v2, 16, v2
s_add_i32 s11, s11, 16
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s11, s2
s_cbranch_scc1 .LBB0_2
.LBB0_6:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, s11, v1
s_mov_b32 s12, exec_lo
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e32 0, v5
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v6, v2
s_mov_b32 s13, 32
s_branch .LBB0_9
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s0
v_lshrrev_b32_e32 v5, 1, v5
v_add_nc_u32_e32 v6, s2, v6
s_add_i32 s13, s13, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s13, 0
s_cbranch_scc0 .LBB0_5
.LBB0_9:
v_and_b32_e32 v7, 1, v5
v_cmp_gt_i32_e64 s0, s1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e32 vcc_lo, 1, v7
s_and_b32 s14, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s14
s_cbranch_execz .LBB0_8
v_lshl_add_u32 v7, v3, 4, v0
v_add_nc_u32_e32 v3, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_store_b32 v[7:8], v6, off
s_branch .LBB0_8
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14UnpackPointersPiS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 15
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14UnpackPointersPiS_iii, .Lfunc_end0-_Z14UnpackPointersPiS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14UnpackPointersPiS_iii
.private_segment_fixed_size: 0
.sgpr_count: 17
.sgpr_spill_count: 0
.symbol: _Z14UnpackPointersPiS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void UnpackPointers(int *minmax, int *ptrs, int w, int h, int maxPts)
{
const int tx = threadIdx.x;
int numPts = 0;
for (int y=0;y<h/32;y++) {
for (int x=0;x<w;x+=16) {
unsigned int val = minmax[y*w+x+tx];
if (val) {
for (int k=0;k<32;k++) {
if (val&0x1 && numPts<maxPts) {
ptrs[16*numPts+tx] = (y*32+k)*w + x+tx;
numPts++;
}
val >>= 1;
}
}
}
}
} | .text
.file "UnpackPointers.hip"
.globl _Z29__device_stub__UnpackPointersPiS_iii # -- Begin function _Z29__device_stub__UnpackPointersPiS_iii
.p2align 4, 0x90
.type _Z29__device_stub__UnpackPointersPiS_iii,@function
_Z29__device_stub__UnpackPointersPiS_iii: # @_Z29__device_stub__UnpackPointersPiS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14UnpackPointersPiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__UnpackPointersPiS_iii, .Lfunc_end0-_Z29__device_stub__UnpackPointersPiS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14UnpackPointersPiS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14UnpackPointersPiS_iii,@object # @_Z14UnpackPointersPiS_iii
.section .rodata,"a",@progbits
.globl _Z14UnpackPointersPiS_iii
.p2align 3, 0x0
_Z14UnpackPointersPiS_iii:
.quad _Z29__device_stub__UnpackPointersPiS_iii
.size _Z14UnpackPointersPiS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14UnpackPointersPiS_iii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__UnpackPointersPiS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14UnpackPointersPiS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14UnpackPointersPiS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe40000000a00 */
/*0020*/ UISETP.GE.AND UP0, UPT, UR6, 0x1, UPT ; /* 0x000000010600788c */
/* 0x000fc8000bf06270 */
/*0030*/ UISETP.LT.OR UP0, UPT, UR7, 0x20, !UP0 ; /* 0x000000200700788c */
/* 0x000fcc000c701670 */
/*0040*/ PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0003f0f008 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0070*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR7 ; /* 0x0000001f3f047899 */
/* 0x000fe20008011407 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC UR5, c[0x0][0x174] ; /* 0x00005d0000057ab9 */
/* 0x000fe40000000800 */
/*00a0*/ ULEA.HI UR4, UR4, UR5, URZ, 0x5 ; /* 0x0000000504047291 */
/* 0x000fe4000f8f283f */
/*00b0*/ USHF.L.U32 UR7, UR6, 0x5, URZ ; /* 0x0000000506077899 */
/* 0x000fe4000800063f */
/*00c0*/ USHF.R.S32.HI UR8, URZ, 0x5, UR4 ; /* 0x000000053f087899 */
/* 0x000fe40008011404 */
/*00d0*/ ULDC.64 UR14, c[0x0][0x118] ; /* 0x00004600000e7ab9 */
/* 0x000fc40000000a00 */
/*00e0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*00f0*/ USHF.L.U32 UR5, UR4, 0x5, URZ ; /* 0x0000000504057899 */
/* 0x000fe2000800063f */
/*0100*/ IMAD.U32 R4, RZ, RZ, UR7 ; /* 0x00000007ff047e24 */
/* 0x000fe4000f8e00ff */
/*0110*/ IMAD.U32 R2, RZ, RZ, UR4 ; /* 0x00000004ff027e24 */
/* 0x000fe2000f8e00ff */
/*0120*/ UIADD3 UR6, UR5, 0x7, URZ ; /* 0x0000000705067890 */
/* 0x000fe2000fffe03f */
/*0130*/ IMAD R4, R4, UR4, R3.reuse ; /* 0x0000000404047c24 */
/* 0x101fe2000f8e0203 */
/*0140*/ UIADD3 UR9, UR5, 0x6, URZ ; /* 0x0000000605097890 */
/* 0x000fe2000fffe03f */
/*0150*/ IMAD R2, R2, c[0x0][0x170], R3.reuse ; /* 0x00005c0002027a24 */
/* 0x100fe200078e0203 */
/*0160*/ UIADD3 UR10, UR5, 0x5, URZ ; /* 0x00000005050a7890 */
/* 0x000fe4000fffe03f */
/*0170*/ UIADD3 UR11, UR5, 0x4, URZ ; /* 0x00000004050b7890 */
/* 0x000fe2000fffe03f */
/*0180*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0190*/ UIADD3 UR12, UR5, 0x3, URZ ; /* 0x00000003050c7890 */
/* 0x000fe2000fffe03f */
/*01a0*/ IMAD.U32 R8, RZ, RZ, UR9 ; /* 0x00000009ff087e24 */
/* 0x000fe2000f8e00ff */
/*01b0*/ UIADD3 UR13, UR5, 0x2, URZ ; /* 0x00000002050d7890 */
/* 0x000fe2000fffe03f */
/*01c0*/ IMAD.U32 R10, RZ, RZ, UR10 ; /* 0x0000000aff0a7e24 */
/* 0x000fe2000f8e00ff */
/*01d0*/ UIADD3 UR5, UR5, 0x1, URZ ; /* 0x0000000105057890 */
/* 0x000fe2000fffe03f */
/*01e0*/ IMAD.U32 R12, RZ, RZ, UR11 ; /* 0x0000000bff0c7e24 */
/* 0x000fe2000f8e00ff */
/*01f0*/ MOV R14, UR12 ; /* 0x0000000c000e7c02 */
/* 0x000fe20008000f00 */
/*0200*/ IMAD R5, R6, c[0x0][0x170], R3 ; /* 0x00005c0006057a24 */
/* 0x000fe200078e0203 */
/*0210*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0220*/ IMAD.U32 R16, RZ, RZ, UR13 ; /* 0x0000000dff107e24 */
/* 0x000fc4000f8e00ff */
/*0230*/ IMAD.U32 R18, RZ, RZ, UR5 ; /* 0x00000005ff127e24 */
/* 0x000fe2000f8e00ff */
/*0240*/ UISETP.GE.AND UP0, UPT, UR4, UR8, UPT ; /* 0x000000080400728c */
/* 0x000fe2000bf06270 */
/*0250*/ IMAD R6, R8, c[0x0][0x170], R3.reuse ; /* 0x00005c0008067a24 */
/* 0x100fe200078e0203 */
/*0260*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*0270*/ IMAD R7, R10, c[0x0][0x170], R3.reuse ; /* 0x00005c000a077a24 */
/* 0x100fe400078e0203 */
/*0280*/ IMAD R8, R12, c[0x0][0x170], R3.reuse ; /* 0x00005c000c087a24 */
/* 0x100fe400078e0203 */
/*0290*/ IMAD R9, R14, c[0x0][0x170], R3.reuse ; /* 0x00005c000e097a24 */
/* 0x100fe400078e0203 */
/*02a0*/ IMAD R10, R16, c[0x0][0x170], R3 ; /* 0x00005c00100a7a24 */
/* 0x000fc400078e0203 */
/*02b0*/ IMAD R11, R18, c[0x0][0x170], R3 ; /* 0x00005c00120b7a24 */
/* 0x000fe400078e0203 */
/*02c0*/ IADD3 R12, R2, UR5, RZ ; /* 0x00000005020c7c10 */
/* 0x000fe2000fffe0ff */
/*02d0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fc800078e00ff */
/*02e0*/ IMAD.WIDE R12, R12, R13, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fcc00078e020d */
/*02f0*/ LDG.E R13, [R12.64] ; /* 0x0000000e0c0d7981 */
/* 0x000ea2000c1e1900 */
/*0300*/ BSSY B0, 0x840 ; /* 0x0000053000007945 */
/* 0x000fe20003800000 */
/*0310*/ ISETP.NE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x004fda0003f05270 */
/*0320*/ @!P0 BRA 0x830 ; /* 0x0000050000008947 */
/* 0x000fea0003800000 */
/*0330*/ IADD3 R23, R5, UR5, RZ ; /* 0x0000000505177c10 */
/* 0x000fe2000fffe0ff */
/*0340*/ UMOV UR6, URZ ; /* 0x0000003f00067c82 */
/* 0x000fe20008000000 */
/*0350*/ IADD3 R25, R6, UR5, RZ ; /* 0x0000000506197c10 */
/* 0x000fe4000fffe0ff */
/*0360*/ IADD3 R27, R7, UR5, RZ ; /* 0x00000005071b7c10 */
/* 0x000fe4000fffe0ff */
/*0370*/ IADD3 R29, R8, UR5, RZ ; /* 0x00000005081d7c10 */
/* 0x000fe4000fffe0ff */
/*0380*/ IADD3 R22, R9, UR5, RZ ; /* 0x0000000509167c10 */
/* 0x000fe4000fffe0ff */
/*0390*/ IADD3 R24, R10, UR5, RZ ; /* 0x000000050a187c10 */
/* 0x000fc4000fffe0ff */
/*03a0*/ IADD3 R12, R11, UR5, RZ ; /* 0x000000050b0c7c10 */
/* 0x000fe4000fffe0ff */
/*03b0*/ IADD3 R26, R4, UR5, RZ ; /* 0x00000005041a7c10 */
/* 0x000fe4000fffe0ff */
/*03c0*/ LOP3.LUT R14, R13.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x000000010d0e7812 */
/* 0x040fe200078ec0ff */
/*03d0*/ UIADD3 UR6, UR6, 0x8, URZ ; /* 0x0000000806067890 */
/* 0x000fe2000fffe03f */
/*03e0*/ LOP3.LUT P4, RZ, R13.reuse, 0x2, RZ, 0xc0, !PT ; /* 0x000000020dff7812 */
/* 0x040fe4000788c0ff */
/*03f0*/ ISETP.NE.U32.AND P1, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fe20003f25070 */
/*0400*/ UISETP.NE.AND UP1, UPT, UR6, 0x20, UPT ; /* 0x000000200600788c */
/* 0x000fe2000bf25270 */
/*0410*/ LOP3.LUT P3, RZ, R13, 0x4, RZ, 0xc0, !PT ; /* 0x000000040dff7812 */
/* 0x000fe4000786c0ff */
/*0420*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x178], P1 ; /* 0x00005e0000007a0c */
/* 0x000fc40000f26670 */
/*0430*/ LOP3.LUT P2, RZ, R13.reuse, 0x8, RZ, 0xc0, !PT ; /* 0x000000080dff7812 */
/* 0x040fe4000784c0ff */
/*0440*/ LOP3.LUT P0, RZ, R13, 0x10, RZ, 0xc0, !PT ; /* 0x000000100dff7812 */
/* 0x000fd2000780c0ff */
/*0450*/ @!P1 LEA R16, R0.reuse, R3, 0x4 ; /* 0x0000000300109211 */
/* 0x040fe400078e20ff */
/*0460*/ @!P1 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100009810 */
/* 0x000fe40007ffe0ff */
/*0470*/ @!P1 MOV R17, 0x4 ; /* 0x0000000400119802 */
/* 0x000fe40000000f00 */
/*0480*/ ISETP.GE.OR P4, PT, R0, c[0x0][0x178], !P4 ; /* 0x00005e0000007a0c */
/* 0x000fc60006786670 */
/*0490*/ @!P1 IMAD.WIDE R16, R16, R17, c[0x0][0x168] ; /* 0x00005a0010109625 */
/* 0x000fca00078e0211 */
/*04a0*/ @!P1 STG.E [R16.64], R26 ; /* 0x0000001a10009986 */
/* 0x000fe2000c10190e */
/*04b0*/ LOP3.LUT P1, RZ, R13, 0x20, RZ, 0xc0, !PT ; /* 0x000000200dff7812 */
/* 0x000fc8000782c0ff */
/*04c0*/ @!P4 IMAD R14, R0.reuse, 0x10, R3 ; /* 0x00000010000ec824 */
/* 0x040fe200078e0203 */
/*04d0*/ @!P4 IADD3 R0, R0, 0x1, RZ ; /* 0x000000010000c810 */
/* 0x000fe20007ffe0ff */
/*04e0*/ @!P4 IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0fc424 */
/* 0x000fc600078e00ff */
/*04f0*/ ISETP.GE.OR P3, PT, R0, c[0x0][0x178], !P3 ; /* 0x00005e0000007a0c */
/* 0x000fe20005f66670 */
/*0500*/ @!P4 IMAD.WIDE R14, R14, R15, c[0x0][0x168] ; /* 0x00005a000e0ec625 */
/* 0x000fca00078e020f */
/*0510*/ @!P4 STG.E [R14.64], R12 ; /* 0x0000000c0e00c986 */
/* 0x0001e2000c10190e */
/*0520*/ LOP3.LUT P4, RZ, R13, 0x40, RZ, 0xc0, !PT ; /* 0x000000400dff7812 */
/* 0x000fcc000788c0ff */
/*0530*/ @!P3 IMAD R20, R0.reuse, 0x10, R3 ; /* 0x000000100014b824 */
/* 0x040fe200078e0203 */
/*0540*/ @!P3 IADD3 R0, R0, 0x1, RZ ; /* 0x000000010000b810 */
/* 0x000fe40007ffe0ff */
/*0550*/ @!P3 MOV R21, 0x4 ; /* 0x000000040015b802 */
/* 0x000fe40000000f00 */
/*0560*/ ISETP.GE.OR P2, PT, R0, c[0x0][0x178], !P2 ; /* 0x00005e0000007a0c */
/* 0x000fc60005746670 */
/*0570*/ @!P3 IMAD.WIDE R20, R20, R21, c[0x0][0x168] ; /* 0x00005a001414b625 */
/* 0x000fca00078e0215 */
/*0580*/ @!P3 STG.E [R20.64], R24 ; /* 0x000000181400b986 */
/* 0x000fe2000c10190e */
/*0590*/ LOP3.LUT P3, RZ, R13, 0x80, RZ, 0xc0, !PT ; /* 0x000000800dff7812 */
/* 0x000fe4000786c0ff */
/*05a0*/ SHF.R.U32.HI R13, RZ, 0x8, R13 ; /* 0x00000008ff0d7819 */
/* 0x000fe4000001160d */
/*05b0*/ @!P2 IMAD R18, R0.reuse, 0x10, R3 ; /* 0x000000100012a824 */
/* 0x040fe200078e0203 */
/*05c0*/ @!P2 IADD3 R0, R0, 0x1, RZ ; /* 0x000000010000a810 */
/* 0x000fe20007ffe0ff */
/*05d0*/ @!P2 IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; /* 0x00000004ff13a424 */
/* 0x000fc600078e00ff */
/*05e0*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], !P0 ; /* 0x00005e0000007a0c */
/* 0x000fe20004706670 */
/*05f0*/ @!P2 IMAD.WIDE R18, R18, R19, c[0x0][0x168] ; /* 0x00005a001212a625 */
/* 0x000fca00078e0213 */
/*0600*/ @!P2 STG.E [R18.64], R22 ; /* 0x000000161200a986 */
/* 0x000fee000c10190e */
/*0610*/ @!P0 IMAD R28, R0.reuse, 0x10, R3 ; /* 0x00000010001c8824 */
/* 0x040fe200078e0203 */
/*0620*/ @!P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100008810 */
/* 0x000fe20007ffe0ff */
/*0630*/ @!P0 IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f8424 */
/* 0x001fc600078e00ff */
/*0640*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x178], !P1 ; /* 0x00005e0000007a0c */
/* 0x000fe20004f26670 */
/*0650*/ @!P0 IMAD.WIDE R14, R28, R15, c[0x0][0x168] ; /* 0x00005a001c0e8625 */
/* 0x000fca00078e020f */
/*0660*/ @!P0 STG.E [R14.64], R29 ; /* 0x0000001d0e008986 */
/* 0x0001e2000c10190e */
/*0670*/ PLOP3.LUT P0, PT, PT, PT, UP1, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fcc0003f0f018 */
/*0680*/ @!P1 IMAD R16, R0.reuse, 0x10, R3 ; /* 0x0000001000109824 */
/* 0x040fe200078e0203 */
/*0690*/ @!P1 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100009810 */
/* 0x000fe40007ffe0ff */
/*06a0*/ @!P1 MOV R17, 0x4 ; /* 0x0000000400119802 */
/* 0x000fe40000000f00 */
/*06b0*/ ISETP.GE.OR P4, PT, R0, c[0x0][0x178], !P4 ; /* 0x00005e0000007a0c */
/* 0x000fe40006786670 */
/*06c0*/ MOV R14, c[0x0][0x170] ; /* 0x00005c00000e7a02 */
/* 0x001fe20000000f00 */
/*06d0*/ @!P1 IMAD.WIDE R16, R16, R17, c[0x0][0x168] ; /* 0x00005a0010109625 */
/* 0x000fc600078e0211 */
/*06e0*/ LEA R22, R14.reuse, R22, 0x3 ; /* 0x000000160e167211 */
/* 0x040fe200078e18ff */
/*06f0*/ IMAD R26, R14.reuse, 0x8, R26 ; /* 0x000000080e1a7824 */
/* 0x040fe200078e021a */
/*0700*/ @!P1 STG.E [R16.64], R27 ; /* 0x0000001b10009986 */
/* 0x0001e2000c10190e */
/*0710*/ IMAD R12, R14.reuse, 0x8, R12 ; /* 0x000000080e0c7824 */
/* 0x040fe400078e020c */
/*0720*/ IMAD R24, R14, 0x8, R24 ; /* 0x000000080e187824 */
/* 0x000fe400078e0218 */
/*0730*/ @!P4 IMAD R20, R0.reuse, 0x10, R3 ; /* 0x000000100014c824 */
/* 0x040fe200078e0203 */
/*0740*/ @!P4 IADD3 R0, R0, 0x1, RZ ; /* 0x000000010000c810 */
/* 0x000fe20007ffe0ff */
/*0750*/ @!P4 IMAD.MOV.U32 R21, RZ, RZ, 0x4 ; /* 0x00000004ff15c424 */
/* 0x000fe400078e00ff */
/*0760*/ IMAD R29, R14, 0x8, R29 ; /* 0x000000080e1d7824 */
/* 0x000fe200078e021d */
/*0770*/ ISETP.GE.OR P2, PT, R0, c[0x0][0x178], !P3 ; /* 0x00005e0000007a0c */
/* 0x000fe20005f46670 */
/*0780*/ @!P4 IMAD.WIDE R18, R20, R21, c[0x0][0x168] ; /* 0x00005a001412c625 */
/* 0x000fc800078e0215 */
/*0790*/ IMAD R27, R14, 0x8, R27 ; /* 0x000000080e1b7824 */
/* 0x001fe200078e021b */
/*07a0*/ @!P4 STG.E [R18.64], R25 ; /* 0x000000191200c986 */
/* 0x0001ee000c10190e */
/*07b0*/ @!P2 IMAD R28, R0.reuse, 0x10, R3 ; /* 0x00000010001ca824 */
/* 0x040fe200078e0203 */
/*07c0*/ @!P2 IADD3 R0, R0, 0x1, RZ ; /* 0x000000010000a810 */
/* 0x000fe20007ffe0ff */
/*07d0*/ @!P2 IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0fa424 */
/* 0x000fe200078e00ff */
/*07e0*/ LEA R25, R14, R25, 0x3 ; /* 0x000000190e197211 */
/* 0x001fc600078e18ff */
/*07f0*/ @!P2 IMAD.WIDE R20, R28, R15, c[0x0][0x168] ; /* 0x00005a001c14a625 */
/* 0x000fca00078e020f */
/*0800*/ @!P2 STG.E [R20.64], R23 ; /* 0x000000171400a986 */
/* 0x0001e4000c10190e */
/*0810*/ IMAD R23, R14, 0x8, R23 ; /* 0x000000080e177824 */
/* 0x001fe200078e0217 */
/*0820*/ @P0 BRA 0x3c0 ; /* 0xfffffb9000000947 */
/* 0x000fea000383ffff */
/*0830*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0840*/ UIADD3 UR5, UR5, 0x10, URZ ; /* 0x0000001005057890 */
/* 0x000fe4000fffe03f */
/*0850*/ ULDC UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe40000000800 */
/*0860*/ UISETP.GE.AND UP1, UPT, UR5, UR6, UPT ; /* 0x000000060500728c */
/* 0x000fcc000bf26270 */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, UP1, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0003f0f018 */
/*0880*/ @!P0 BRA 0x2c0 ; /* 0xfffffa3000008947 */
/* 0x000fea000383ffff */
/*0890*/ PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0003f0f008 */
/*08a0*/ @!P0 BRA 0xf0 ; /* 0xfffff84000008947 */
/* 0x000fea000383ffff */
/*08b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08c0*/ BRA 0x8c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14UnpackPointersPiS_iii
.globl _Z14UnpackPointersPiS_iii
.p2align 8
.type _Z14UnpackPointersPiS_iii,@function
_Z14UnpackPointersPiS_iii:
s_load_b32 s3, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 32
s_cbranch_scc1 .LBB0_11
s_clause 0x2
s_load_b32 s2, s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s1, s[0:1], 0x18
s_ashr_i32 s0, s3, 31
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, v0
s_lshr_b32 s0, s0, 27
s_mov_b32 s9, 0
s_add_i32 s3, s3, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s3, s3, 5
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s2, 0
s_cselect_b32 s8, -1, 0
s_lshl_b32 s10, s2, 5
s_branch .LBB0_3
.LBB0_2:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v4, s10, v4
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, s3
s_cbranch_scc1 .LBB0_11
.LBB0_3:
s_and_not1_b32 vcc_lo, exec_lo, s8
s_cbranch_vccnz .LBB0_2
v_mad_u64_u32 v[1:2], null, s9, s2, v[0:1]
v_mov_b32_e32 v2, v4
s_mov_b32 s11, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s12
v_add_nc_u32_e32 v2, 16, v2
s_add_i32 s11, s11, 16
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s11, s2
s_cbranch_scc1 .LBB0_2
.LBB0_6:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, s11, v1
s_mov_b32 s12, exec_lo
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e32 0, v5
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v6, v2
s_mov_b32 s13, 32
s_branch .LBB0_9
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s0
v_lshrrev_b32_e32 v5, 1, v5
v_add_nc_u32_e32 v6, s2, v6
s_add_i32 s13, s13, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s13, 0
s_cbranch_scc0 .LBB0_5
.LBB0_9:
v_and_b32_e32 v7, 1, v5
v_cmp_gt_i32_e64 s0, s1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e32 vcc_lo, 1, v7
s_and_b32 s14, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s14
s_cbranch_execz .LBB0_8
v_lshl_add_u32 v7, v3, 4, v0
v_add_nc_u32_e32 v3, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_store_b32 v[7:8], v6, off
s_branch .LBB0_8
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14UnpackPointersPiS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 15
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14UnpackPointersPiS_iii, .Lfunc_end0-_Z14UnpackPointersPiS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14UnpackPointersPiS_iii
.private_segment_fixed_size: 0
.sgpr_count: 17
.sgpr_spill_count: 0
.symbol: _Z14UnpackPointersPiS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004bb9a_00000000-6_UnpackPointers.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z14UnpackPointersPiS_iiiPiS_iii
.type _Z39__device_stub__Z14UnpackPointersPiS_iiiPiS_iii, @function
_Z39__device_stub__Z14UnpackPointersPiS_iiiPiS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14UnpackPointersPiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z14UnpackPointersPiS_iiiPiS_iii, .-_Z39__device_stub__Z14UnpackPointersPiS_iiiPiS_iii
.globl _Z14UnpackPointersPiS_iii
.type _Z14UnpackPointersPiS_iii, @function
_Z14UnpackPointersPiS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14UnpackPointersPiS_iiiPiS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14UnpackPointersPiS_iii, .-_Z14UnpackPointersPiS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14UnpackPointersPiS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14UnpackPointersPiS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "UnpackPointers.hip"
.globl _Z29__device_stub__UnpackPointersPiS_iii # -- Begin function _Z29__device_stub__UnpackPointersPiS_iii
.p2align 4, 0x90
.type _Z29__device_stub__UnpackPointersPiS_iii,@function
_Z29__device_stub__UnpackPointersPiS_iii: # @_Z29__device_stub__UnpackPointersPiS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14UnpackPointersPiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__UnpackPointersPiS_iii, .Lfunc_end0-_Z29__device_stub__UnpackPointersPiS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14UnpackPointersPiS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14UnpackPointersPiS_iii,@object # @_Z14UnpackPointersPiS_iii
.section .rodata,"a",@progbits
.globl _Z14UnpackPointersPiS_iii
.p2align 3, 0x0
_Z14UnpackPointersPiS_iii:
.quad _Z29__device_stub__UnpackPointersPiS_iii
.size _Z14UnpackPointersPiS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14UnpackPointersPiS_iii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__UnpackPointersPiS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14UnpackPointersPiS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
struct some_data {
some_data(float a_, int b_) {
a = a_;
b = b_;
}
float a;
int b;
__device__ float other_func() {
return a * (float)b;
}
};
// Kernel that executes on the CUDA device
__global__ void square_array(float *a, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx<N) a[idx] = a[idx] * a[idx];
}
__global__ void square_array(some_data* a, int N) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx < N) {
//a[idx].a = a[idx].a * a[idx].a;
//a[idx].b = a[idx].b * a[idx].b;
a[idx].a = a[idx].other_func();
}
}
// main routine that executes on the host
int main(void)
{
some_data *a_h; // Pointer to host & device arrays
const int N = 10; // Number of elements in arrays
size_t size = N * sizeof(some_data);
cudaMallocManaged((void **) &a_h, size); // Allocate array on device
cudaDeviceSynchronize();
// Initialize host array and copy it to CUDA device
for (int i=0; i<N; i++){
//a_h[i].a = (float)i;
//a_h[i].b = i+2;
a_h[i] = some_data((float)i, i + 2);
}
// Do calculation on device:
int block_size = 4;
int n_blocks = N/block_size + (N%block_size == 0 ? 0:1);
square_array <<< n_blocks, block_size >>> (a_h, N);
cudaDeviceSynchronize();
// Print results
for (int i=0; i<N; i++){
printf("%d %f %d\n", i, a_h[i].a, a_h[i].b);
}
// Cleanup
cudaFree(a_h);
} | code for sm_80
Function : _Z12square_arrayP9some_datai
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ee2000c1e1900 */
/*00b0*/ I2F R0, R0 ; /* 0x0000000000007306 */
/* 0x004ee40000201400 */
/*00c0*/ FMUL R5, R0, R5 ; /* 0x0000000500057220 */
/* 0x008fca0000400000 */
/*00d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z12square_arrayPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FMUL R5, R0, R0 ; /* 0x0000000000057220 */
/* 0x004fca0000400000 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
struct some_data {
some_data(float a_, int b_) {
a = a_;
b = b_;
}
float a;
int b;
__device__ float other_func() {
return a * (float)b;
}
};
// Kernel that executes on the CUDA device
__global__ void square_array(float *a, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx<N) a[idx] = a[idx] * a[idx];
}
__global__ void square_array(some_data* a, int N) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx < N) {
//a[idx].a = a[idx].a * a[idx].a;
//a[idx].b = a[idx].b * a[idx].b;
a[idx].a = a[idx].other_func();
}
}
// main routine that executes on the host
int main(void)
{
some_data *a_h; // Pointer to host & device arrays
const int N = 10; // Number of elements in arrays
size_t size = N * sizeof(some_data);
cudaMallocManaged((void **) &a_h, size); // Allocate array on device
cudaDeviceSynchronize();
// Initialize host array and copy it to CUDA device
for (int i=0; i<N; i++){
//a_h[i].a = (float)i;
//a_h[i].b = i+2;
a_h[i] = some_data((float)i, i + 2);
}
// Do calculation on device:
int block_size = 4;
int n_blocks = N/block_size + (N%block_size == 0 ? 0:1);
square_array <<< n_blocks, block_size >>> (a_h, N);
cudaDeviceSynchronize();
// Print results
for (int i=0; i<N; i++){
printf("%d %f %d\n", i, a_h[i].a, a_h[i].b);
}
// Cleanup
cudaFree(a_h);
} | .file "tmpxft_000621b7_00000000-6_mycuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z12square_arrayPfiPfi
.type _Z33__device_stub__Z12square_arrayPfiPfi, @function
_Z33__device_stub__Z12square_arrayPfiPfi:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12square_arrayPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z33__device_stub__Z12square_arrayPfiPfi, .-_Z33__device_stub__Z12square_arrayPfiPfi
.globl _Z12square_arrayPfi
.type _Z12square_arrayPfi, @function
_Z12square_arrayPfi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12square_arrayPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z12square_arrayPfi, .-_Z12square_arrayPfi
.globl _Z42__device_stub__Z12square_arrayP9some_dataiP9some_datai
.type _Z42__device_stub__Z12square_arrayP9some_dataiP9some_datai, @function
_Z42__device_stub__Z12square_arrayP9some_dataiP9some_datai:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12square_arrayP9some_datai(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z42__device_stub__Z12square_arrayP9some_dataiP9some_datai, .-_Z42__device_stub__Z12square_arrayP9some_dataiP9some_datai
.globl _Z12square_arrayP9some_datai
.type _Z12square_arrayP9some_datai, @function
_Z12square_arrayP9some_datai:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z12square_arrayP9some_dataiP9some_datai
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z12square_arrayP9some_datai, .-_Z12square_arrayP9some_datai
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d %f %d\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $80, %esi
call cudaMallocManaged@PLT
call cudaDeviceSynchronize@PLT
movl $0, %eax
.L20:
movq 8(%rsp), %rdx
leaq (%rdx,%rax,8), %rdx
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rdx)
leal 2(%rax), %ecx
movl %ecx, 4(%rdx)
addq $1, %rax
cmpq $10, %rax
jne .L20
movl $4, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $3, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L21:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L22:
movq 8(%rsp), %rax
leaq (%rax,%rbx,8), %rax
movl 4(%rax), %ecx
pxor %xmm0, %xmm0
cvtss2sd (%rax), %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L22
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movl $10, %esi
movq 8(%rsp), %rdi
call _Z42__device_stub__Z12square_arrayP9some_dataiP9some_datai
jmp .L21
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z12square_arrayP9some_datai"
.LC2:
.string "_Z12square_arrayPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12square_arrayP9some_datai(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z12square_arrayPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
struct some_data {
some_data(float a_, int b_) {
a = a_;
b = b_;
}
float a;
int b;
__device__ float other_func() {
return a * (float)b;
}
};
// Kernel that executes on the CUDA device
__global__ void square_array(float *a, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx<N) a[idx] = a[idx] * a[idx];
}
__global__ void square_array(some_data* a, int N) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx < N) {
//a[idx].a = a[idx].a * a[idx].a;
//a[idx].b = a[idx].b * a[idx].b;
a[idx].a = a[idx].other_func();
}
}
// main routine that executes on the host
int main(void)
{
some_data *a_h; // Pointer to host & device arrays
const int N = 10; // Number of elements in arrays
size_t size = N * sizeof(some_data);
cudaMallocManaged((void **) &a_h, size); // Allocate array on device
cudaDeviceSynchronize();
// Initialize host array and copy it to CUDA device
for (int i=0; i<N; i++){
//a_h[i].a = (float)i;
//a_h[i].b = i+2;
a_h[i] = some_data((float)i, i + 2);
}
// Do calculation on device:
int block_size = 4;
int n_blocks = N/block_size + (N%block_size == 0 ? 0:1);
square_array <<< n_blocks, block_size >>> (a_h, N);
cudaDeviceSynchronize();
// Print results
for (int i=0; i<N; i++){
printf("%d %f %d\n", i, a_h[i].a, a_h[i].b);
}
// Cleanup
cudaFree(a_h);
} | #include <stdio.h>
#include <hip/hip_runtime.h>
struct some_data {
some_data(float a_, int b_) {
a = a_;
b = b_;
}
float a;
int b;
__device__ float other_func() {
return a * (float)b;
}
};
// Kernel that executes on the CUDA device
__global__ void square_array(float *a, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx<N) a[idx] = a[idx] * a[idx];
}
__global__ void square_array(some_data* a, int N) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx < N) {
//a[idx].a = a[idx].a * a[idx].a;
//a[idx].b = a[idx].b * a[idx].b;
a[idx].a = a[idx].other_func();
}
}
// main routine that executes on the host
int main(void)
{
some_data *a_h; // Pointer to host & device arrays
const int N = 10; // Number of elements in arrays
size_t size = N * sizeof(some_data);
hipMallocManaged((void **) &a_h, size); // Allocate array on device
hipDeviceSynchronize();
// Initialize host array and copy it to CUDA device
for (int i=0; i<N; i++){
//a_h[i].a = (float)i;
//a_h[i].b = i+2;
a_h[i] = some_data((float)i, i + 2);
}
// Do calculation on device:
int block_size = 4;
int n_blocks = N/block_size + (N%block_size == 0 ? 0:1);
square_array <<< n_blocks, block_size >>> (a_h, N);
hipDeviceSynchronize();
// Print results
for (int i=0; i<N; i++){
printf("%d %f %d\n", i, a_h[i].a, a_h[i].b);
}
// Cleanup
hipFree(a_h);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
struct some_data {
some_data(float a_, int b_) {
a = a_;
b = b_;
}
float a;
int b;
__device__ float other_func() {
return a * (float)b;
}
};
// Kernel that executes on the CUDA device
__global__ void square_array(float *a, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx<N) a[idx] = a[idx] * a[idx];
}
__global__ void square_array(some_data* a, int N) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx < N) {
//a[idx].a = a[idx].a * a[idx].a;
//a[idx].b = a[idx].b * a[idx].b;
a[idx].a = a[idx].other_func();
}
}
// main routine that executes on the host
int main(void)
{
some_data *a_h; // Pointer to host & device arrays
const int N = 10; // Number of elements in arrays
size_t size = N * sizeof(some_data);
hipMallocManaged((void **) &a_h, size); // Allocate array on device
hipDeviceSynchronize();
// Initialize host array and copy it to CUDA device
for (int i=0; i<N; i++){
//a_h[i].a = (float)i;
//a_h[i].b = i+2;
a_h[i] = some_data((float)i, i + 2);
}
// Do calculation on device:
int block_size = 4;
int n_blocks = N/block_size + (N%block_size == 0 ? 0:1);
square_array <<< n_blocks, block_size >>> (a_h, N);
hipDeviceSynchronize();
// Print results
for (int i=0; i<N; i++){
printf("%d %f %d\n", i, a_h[i].a, a_h[i].b);
}
// Cleanup
hipFree(a_h);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12square_arrayPfi
.globl _Z12square_arrayPfi
.p2align 8
.type _Z12square_arrayPfi,@function
_Z12square_arrayPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12square_arrayPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12square_arrayPfi, .Lfunc_end0-_Z12square_arrayPfi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12square_arrayP9some_datai
.globl _Z12square_arrayP9some_datai
.p2align 8
.type _Z12square_arrayP9some_datai,@function
_Z12square_arrayP9some_datai:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v3, v3
v_mul_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12square_arrayP9some_datai
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12square_arrayP9some_datai, .Lfunc_end1-_Z12square_arrayP9some_datai
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12square_arrayPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12square_arrayPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12square_arrayP9some_datai
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12square_arrayP9some_datai.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
struct some_data {
some_data(float a_, int b_) {
a = a_;
b = b_;
}
float a;
int b;
__device__ float other_func() {
return a * (float)b;
}
};
// Kernel that executes on the CUDA device
__global__ void square_array(float *a, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx<N) a[idx] = a[idx] * a[idx];
}
__global__ void square_array(some_data* a, int N) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx < N) {
//a[idx].a = a[idx].a * a[idx].a;
//a[idx].b = a[idx].b * a[idx].b;
a[idx].a = a[idx].other_func();
}
}
// main routine that executes on the host
int main(void)
{
some_data *a_h; // Pointer to host & device arrays
const int N = 10; // Number of elements in arrays
size_t size = N * sizeof(some_data);
hipMallocManaged((void **) &a_h, size); // Allocate array on device
hipDeviceSynchronize();
// Initialize host array and copy it to CUDA device
for (int i=0; i<N; i++){
//a_h[i].a = (float)i;
//a_h[i].b = i+2;
a_h[i] = some_data((float)i, i + 2);
}
// Do calculation on device:
int block_size = 4;
int n_blocks = N/block_size + (N%block_size == 0 ? 0:1);
square_array <<< n_blocks, block_size >>> (a_h, N);
hipDeviceSynchronize();
// Print results
for (int i=0; i<N; i++){
printf("%d %f %d\n", i, a_h[i].a, a_h[i].b);
}
// Cleanup
hipFree(a_h);
} | .text
.file "mycuda.hip"
.globl _Z27__device_stub__square_arrayPfi # -- Begin function _Z27__device_stub__square_arrayPfi
.p2align 4, 0x90
.type _Z27__device_stub__square_arrayPfi,@function
_Z27__device_stub__square_arrayPfi: # @_Z27__device_stub__square_arrayPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12square_arrayPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__square_arrayPfi, .Lfunc_end0-_Z27__device_stub__square_arrayPfi
.cfi_endproc
# -- End function
.globl _Z27__device_stub__square_arrayP9some_datai # -- Begin function _Z27__device_stub__square_arrayP9some_datai
.p2align 4, 0x90
.type _Z27__device_stub__square_arrayP9some_datai,@function
_Z27__device_stub__square_arrayP9some_datai: # @_Z27__device_stub__square_arrayP9some_datai
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12square_arrayP9some_datai, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z27__device_stub__square_arrayP9some_datai, .Lfunc_end1-_Z27__device_stub__square_arrayP9some_datai
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $96, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -16
leaq 8(%rsp), %rdi
movl $80, %esi
movl $1, %edx
callq hipMallocManaged
callq hipDeviceSynchronize
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movq 8(%rsp), %rcx
movss %xmm0, (%rcx,%rax,8)
leal 2(%rax), %edx
movl %edx, 4(%rcx,%rax,8)
incq %rax
cmpq $10, %rax
jne .LBB2_1
# %bb.2:
movabsq $4294967299, %rdi # imm = 0x100000003
leaq 1(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $10, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12square_arrayP9some_datai, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movss (%rax,%rbx,8), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl 4(%rax,%rbx,8), %edx
movl $.L.str, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB2_5
# %bb.6:
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12square_arrayPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12square_arrayP9some_datai, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12square_arrayPfi,@object # @_Z12square_arrayPfi
.section .rodata,"a",@progbits
.globl _Z12square_arrayPfi
.p2align 3, 0x0
_Z12square_arrayPfi:
.quad _Z27__device_stub__square_arrayPfi
.size _Z12square_arrayPfi, 8
.type _Z12square_arrayP9some_datai,@object # @_Z12square_arrayP9some_datai
.globl _Z12square_arrayP9some_datai
.p2align 3, 0x0
_Z12square_arrayP9some_datai:
.quad _Z27__device_stub__square_arrayP9some_datai
.size _Z12square_arrayP9some_datai, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d %f %d\n"
.size .L.str, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12square_arrayPfi"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12square_arrayP9some_datai"
.size .L__unnamed_2, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__square_arrayPfi
.addrsig_sym _Z27__device_stub__square_arrayP9some_datai
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12square_arrayPfi
.addrsig_sym _Z12square_arrayP9some_datai
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12square_arrayP9some_datai
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ee2000c1e1900 */
/*00b0*/ I2F R0, R0 ; /* 0x0000000000007306 */
/* 0x004ee40000201400 */
/*00c0*/ FMUL R5, R0, R5 ; /* 0x0000000500057220 */
/* 0x008fca0000400000 */
/*00d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z12square_arrayPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FMUL R5, R0, R0 ; /* 0x0000000000057220 */
/* 0x004fca0000400000 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12square_arrayPfi
.globl _Z12square_arrayPfi
.p2align 8
.type _Z12square_arrayPfi,@function
_Z12square_arrayPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12square_arrayPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12square_arrayPfi, .Lfunc_end0-_Z12square_arrayPfi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12square_arrayP9some_datai
.globl _Z12square_arrayP9some_datai
.p2align 8
.type _Z12square_arrayP9some_datai,@function
_Z12square_arrayP9some_datai:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v3, v3
v_mul_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12square_arrayP9some_datai
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12square_arrayP9some_datai, .Lfunc_end1-_Z12square_arrayP9some_datai
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12square_arrayPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12square_arrayPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12square_arrayP9some_datai
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12square_arrayP9some_datai.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000621b7_00000000-6_mycuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z12square_arrayPfiPfi
.type _Z33__device_stub__Z12square_arrayPfiPfi, @function
_Z33__device_stub__Z12square_arrayPfiPfi:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12square_arrayPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z33__device_stub__Z12square_arrayPfiPfi, .-_Z33__device_stub__Z12square_arrayPfiPfi
.globl _Z12square_arrayPfi
.type _Z12square_arrayPfi, @function
_Z12square_arrayPfi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12square_arrayPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z12square_arrayPfi, .-_Z12square_arrayPfi
.globl _Z42__device_stub__Z12square_arrayP9some_dataiP9some_datai
.type _Z42__device_stub__Z12square_arrayP9some_dataiP9some_datai, @function
_Z42__device_stub__Z12square_arrayP9some_dataiP9some_datai:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12square_arrayP9some_datai(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z42__device_stub__Z12square_arrayP9some_dataiP9some_datai, .-_Z42__device_stub__Z12square_arrayP9some_dataiP9some_datai
.globl _Z12square_arrayP9some_datai
.type _Z12square_arrayP9some_datai, @function
_Z12square_arrayP9some_datai:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z12square_arrayP9some_dataiP9some_datai
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z12square_arrayP9some_datai, .-_Z12square_arrayP9some_datai
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d %f %d\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $80, %esi
call cudaMallocManaged@PLT
call cudaDeviceSynchronize@PLT
movl $0, %eax
.L20:
movq 8(%rsp), %rdx
leaq (%rdx,%rax,8), %rdx
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rdx)
leal 2(%rax), %ecx
movl %ecx, 4(%rdx)
addq $1, %rax
cmpq $10, %rax
jne .L20
movl $4, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $3, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L21:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L22:
movq 8(%rsp), %rax
leaq (%rax,%rbx,8), %rax
movl 4(%rax), %ecx
pxor %xmm0, %xmm0
cvtss2sd (%rax), %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L22
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movl $10, %esi
movq 8(%rsp), %rdi
call _Z42__device_stub__Z12square_arrayP9some_dataiP9some_datai
jmp .L21
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z12square_arrayP9some_datai"
.LC2:
.string "_Z12square_arrayPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12square_arrayP9some_datai(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z12square_arrayPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mycuda.hip"
.globl _Z27__device_stub__square_arrayPfi # -- Begin function _Z27__device_stub__square_arrayPfi
.p2align 4, 0x90
.type _Z27__device_stub__square_arrayPfi,@function
_Z27__device_stub__square_arrayPfi: # @_Z27__device_stub__square_arrayPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12square_arrayPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__square_arrayPfi, .Lfunc_end0-_Z27__device_stub__square_arrayPfi
.cfi_endproc
# -- End function
.globl _Z27__device_stub__square_arrayP9some_datai # -- Begin function _Z27__device_stub__square_arrayP9some_datai
.p2align 4, 0x90
.type _Z27__device_stub__square_arrayP9some_datai,@function
_Z27__device_stub__square_arrayP9some_datai: # @_Z27__device_stub__square_arrayP9some_datai
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12square_arrayP9some_datai, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z27__device_stub__square_arrayP9some_datai, .Lfunc_end1-_Z27__device_stub__square_arrayP9some_datai
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $96, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -16
leaq 8(%rsp), %rdi
movl $80, %esi
movl $1, %edx
callq hipMallocManaged
callq hipDeviceSynchronize
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movq 8(%rsp), %rcx
movss %xmm0, (%rcx,%rax,8)
leal 2(%rax), %edx
movl %edx, 4(%rcx,%rax,8)
incq %rax
cmpq $10, %rax
jne .LBB2_1
# %bb.2:
movabsq $4294967299, %rdi # imm = 0x100000003
leaq 1(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $10, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12square_arrayP9some_datai, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movss (%rax,%rbx,8), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl 4(%rax,%rbx,8), %edx
movl $.L.str, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB2_5
# %bb.6:
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12square_arrayPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12square_arrayP9some_datai, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12square_arrayPfi,@object # @_Z12square_arrayPfi
.section .rodata,"a",@progbits
.globl _Z12square_arrayPfi
.p2align 3, 0x0
_Z12square_arrayPfi:
.quad _Z27__device_stub__square_arrayPfi
.size _Z12square_arrayPfi, 8
.type _Z12square_arrayP9some_datai,@object # @_Z12square_arrayP9some_datai
.globl _Z12square_arrayP9some_datai
.p2align 3, 0x0
_Z12square_arrayP9some_datai:
.quad _Z27__device_stub__square_arrayP9some_datai
.size _Z12square_arrayP9some_datai, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d %f %d\n"
.size .L.str, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12square_arrayPfi"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12square_arrayP9some_datai"
.size .L__unnamed_2, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__square_arrayPfi
.addrsig_sym _Z27__device_stub__square_arrayP9some_datai
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12square_arrayPfi
.addrsig_sym _Z12square_arrayP9some_datai
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <malloc.h>
#include <stdlib.h>
#include <sys/time.h>
//CUDA
#include <cuda.h>
double wtime(void)
{
static struct timeval tv0;
double time_;
gettimeofday(&tv0,(struct timezone*)0);
time_=(double)((tv0.tv_usec + (tv0.tv_sec)*1000000));
return( time_/1000000);
}
void init_matrix(float *M, int hM, int wM, float k)
{
int i,j;
for (i=0; i<hM; i++)
for (j=0; j<wM; j++)
if (i==j)
M[i*wM+j] = k*k*1.0f;
else
M[i*wM+j] = -k*1.0f;
}
void print_matrix(float *M, int hM, int wM)
{
int i,j;
for (i=0; i<hM; i++){
printf("Line %i: ", i);
for (j=0; j<wM; j++)
printf("%4.1f ", M[i*wM+j]);
printf("\n");
}
}
int check_matrix(float *h, float *d, int hM, int wM)
{
int i,j;
for (i=0; i<hM; i++){
for (j=0; j<wM; j++)
if (fabsf(h[i*wM+j]-d[i*wM+j])>1e-5)
{
printf("device!=host %f!=%f in (%i,%i)\n", h[i*wM+j], d[i*wM+j], i, j);
return(0);
}
}
return (1);
}
void Mul(float *A, float *B, int hA, int wA, int wB, float *C)
{
int i,j,k;
for(i = 0; i < hA; i++){//recorre las filas de A
for(j = 0; j < wB; j++){
C[i*wB+j] = 0;
for(k = 0; k < wA; k++){
C[i*wB+j] += A[i*wA+k]*B[j+k*wB];
//printf(" %d _ %d ", (i*wA)+k, j+(k*wB));
//printf(" %f * %f ", A[i*wA+k], B[j+k*wB]);
}
//printf("\n");
//printf(" %d ",i*wB+j);
}
}
}
__global__ void mulMatrixGPU(float *A, float *B, float *C, int wa, int wb, int ha )
{
int k, sum = 0;
int col = threadIdx.x + blockDim.x * blockIdx.x; //i
int fil = threadIdx.y + blockDim.y * blockIdx.y; //j
if (col < wb && fil < ha) { //ojo no son cuadradas !!
for (k = 0; k < wa; k++) {
sum += A[fil * wa + k] * B[k * wb + col];
}
C[fil * wb + col] = sum;
}
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv)
{
// Matrix variables
float *A, *B, *C, *C_host;
float *A_GPU, *B_GPU, *C_GPU;
int hA, wA, hB, wB;
double t0, t1;
setbuf(stdout, NULL);
if (argc!=4){
printf("./exec hA hB/WA wB\n");
exit(-1);
}
hA = atoi(argv[1]);
hB = wA = atoi(argv[2]);
wB = atoi(argv[3]);
// Init A and B, malloc C
int size_A = wA * hA;
A = (float*)malloc(size_A*sizeof(float));
init_matrix(A, hA, wA,2.0);
int size_B = wB * hB;
B = (float*)malloc(size_B*sizeof(float));
init_matrix(B, hB, wB,1.0);
int size_C = wB * hA;
C = (float*)malloc(size_C*sizeof(float));
t0 = wtime();
Mul(A, B, hA, wA, wB, C);
t1 = wtime(); printf("Time CPU=%f\n", t1-t0);
/* Mallocs GPU */
cudaMalloc((void **) &A_GPU, size_A*sizeof(float));
cudaMalloc((void **) &B_GPU, size_B*sizeof(float));
cudaMalloc((void **) &C_GPU, size_C*sizeof(float));
/* CPU -> GPU */
cudaMemcpy(B_GPU, B, size_B*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(A_GPU, A, size_A*sizeof(float), cudaMemcpyHostToDevice);
/*****************/
/* Add Matrix GPU*/
/*****************/
dim3 dimBlock(16,16); // nThreads por bloque
dim3 dimGrid(hA,wB);//numBloques
t0 = wtime();
mulMatrixGPU<<<dimGrid,dimBlock>>>(A_GPU, B_GPU, C_GPU, wA, wB,hA);// si las matrices no son cuadradas necesito ambos anchos CREO
cudaThreadSynchronize();
t1 = wtime(); printf("Time GPU=%f\n", t1-t0);
/* GPU->CPU */
C_host = (float*)malloc(size_C*sizeof(float));
cudaMemcpy(C_host, C_GPU, size_C*sizeof(float), cudaMemcpyDeviceToHost);
check_matrix(C, C_host, hA, wB);
// print Matrix
//printf("\n\nMATRIX A\n");print_matrix(A, hA, wA);
//printf("\n\nMATRIX B\n");print_matrix(B, hB, wB);
//printf("\n\nMATRIX C\n");print_matrix(C, hA, wB);
//printf("\n\nMATRIX *C\n");print_matrix(C_host, hA, wB);
/* Free CPU */
free(A);
free(B);
free(C);
free(C_host);
/* Free GPU */
cudaFree(A_GPU);
cudaFree(B_GPU);
cudaFree(C_GPU);
return (1);
} | code for sm_80
Function : _Z12mulMatrixGPUPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x17c], P0 ; /* 0x00005f0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R22, -RZ, RZ, 0, 0 ; /* 0x00000000ff167435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0x1000 ; /* 0x00000f1000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R22, RZ ; /* 0x000000ff00167202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xeb0 ; /* 0x00000d6000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, -R2, c[0x0][0x178], RZ ; /* 0x00005e0002057a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R16, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff107435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ HFMA2.MMA R22, -RZ, RZ, 0, 0 ; /* 0x00000000ff167435 */
/* 0x000fe200000001ff */
/*0190*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD R6, R0, c[0x0][0x178], RZ ; /* 0x00005e0000067a24 */
/* 0x000fe200078e02ff */
/*01b0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R16, R3, R16, c[0x0][0x168] ; /* 0x00005a0003107625 */
/* 0x000fcc00078e0210 */
/*01d0*/ @!P0 BRA 0xc90 ; /* 0x00000ab000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x8c0 ; /* 0x000006b000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R14, UR6 ; /* 0x00000006000e7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R23, [R16.64] ; /* 0x0000000410177981 */
/* 0x0010a2000c1e1900 */
/*0240*/ MOV R15, UR7 ; /* 0x00000007000f7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R14, R6, 0x4, R14 ; /* 0x00000004060e7825 */
/* 0x000fca00078e020e */
/*0260*/ LDG.E R28, [R14.64] ; /* 0x000000040e1c7981 */
/* 0x000ea2000c1e1900 */
/*0270*/ MOV R7, c[0x0][0x17c] ; /* 0x00005f0000077a02 */
/* 0x000fc60000000f00 */
/*0280*/ LDG.E R9, [R14.64+0x4] ; /* 0x000004040e097981 */
/* 0x000ee4000c1e1900 */
/*0290*/ IMAD.WIDE R26, R7.reuse, 0x4, R16 ; /* 0x00000004071a7825 */
/* 0x040fe400078e0210 */
/*02a0*/ LDG.E R11, [R14.64+0x8] ; /* 0x000008040e0b7981 */
/* 0x000f28000c1e1900 */
/*02b0*/ LDG.E R8, [R26.64] ; /* 0x000000041a087981 */
/* 0x0022e2000c1e1900 */
/*02c0*/ IMAD.WIDE R20, R7, 0x4, R26 ; /* 0x0000000407147825 */
/* 0x000fc600078e021a */
/*02d0*/ LDG.E R12, [R14.64+0xc] ; /* 0x00000c040e0c7981 */
/* 0x000f68000c1e1900 */
/*02e0*/ LDG.E R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000322000c1e1900 */
/*02f0*/ IMAD.WIDE R18, R7, 0x4, R20 ; /* 0x0000000407127825 */
/* 0x000fc600078e0214 */
/*0300*/ LDG.E R24, [R14.64+0x10] ; /* 0x000010040e187981 */
/* 0x000ee8000c1e1900 */
/*0310*/ LDG.E R13, [R18.64] ; /* 0x00000004120d7981 */
/* 0x000362000c1e1900 */
/*0320*/ IMAD.WIDE R16, R7, 0x4, R18 ; /* 0x0000000407107825 */
/* 0x001fc600078e0212 */
/*0330*/ LDG.E R27, [R14.64+0x14] ; /* 0x000014040e1b7981 */
/* 0x002ee8000c1e1900 */
/*0340*/ LDG.E R25, [R16.64] ; /* 0x0000000410197981 */
/* 0x0000e2000c1e1900 */
/*0350*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fca00078e0210 */
/*0360*/ LDG.E R26, [R18.64] ; /* 0x00000004121a7981 */
/* 0x000522000c1e1900 */
/*0370*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*0380*/ LDG.E R16, [R14.64+0x18] ; /* 0x000018040e107981 */
/* 0x001f28000c1e1900 */
/*0390*/ LDG.E R29, [R20.64] ; /* 0x00000004141d7981 */
/* 0x000128000c1e1900 */
/*03a0*/ LDG.E R17, [R14.64+0x1c] ; /* 0x00001c040e117981 */
/* 0x000f22000c1e1900 */
/*03b0*/ FFMA R18, R23, R28, R22 ; /* 0x0000001c17127223 */
/* 0x004fe40000000016 */
/*03c0*/ IMAD.WIDE R22, R7, 0x4, R20 ; /* 0x0000000407167825 */
/* 0x000fca00078e0214 */
/*03d0*/ LDG.E R28, [R22.64] ; /* 0x00000004161c7981 */
/* 0x0002a2000c1e1900 */
/*03e0*/ F2I.TRUNC.NTZ R21, R18 ; /* 0x0000001200157305 */
/* 0x001066000020f100 */
/*03f0*/ LDG.E R18, [R14.64+0x20] ; /* 0x000020040e127981 */
/* 0x001eaa000c1e1900 */
/*0400*/ I2F R21, R21 ; /* 0x0000001500157306 */
/* 0x002ee40000201400 */
/*0410*/ FFMA R19, R8, R9, R21 ; /* 0x0000000908137223 */
/* 0x008fc40000000015 */
/*0420*/ IMAD.WIDE R8, R7, 0x4, R22 ; /* 0x0000000407087825 */
/* 0x000fc800078e0216 */
/*0430*/ F2I.TRUNC.NTZ R22, R19 ; /* 0x0000001300167305 */
/* 0x000064000020f100 */
/*0440*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x0010ec000c1e1900 */
/*0450*/ I2F R20, R22 ; /* 0x0000001600147306 */
/* 0x002f240000201400 */
/*0460*/ FFMA R20, R10, R11, R20 ; /* 0x0000000b0a147223 */
/* 0x010fc40000000014 */
/*0470*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fc800078e0208 */
/*0480*/ F2I.TRUNC.NTZ R23, R20 ; /* 0x0000001400177305 */
/* 0x000322000020f100 */
/*0490*/ LDG.E R21, [R10.64] ; /* 0x000000040a157981 */
/* 0x0000e8000c1e1900 */
/*04a0*/ LDG.E R20, [R14.64+0x24] ; /* 0x000024040e147981 */
/* 0x002ee6000c1e1900 */
/*04b0*/ I2F R23, R23 ; /* 0x0000001700177306 */
/* 0x010f640000201400 */
/*04c0*/ FFMA R23, R13, R12, R23 ; /* 0x0000000c0d177223 */
/* 0x020fc40000000017 */
/*04d0*/ IMAD.WIDE R12, R7, 0x4, R10 ; /* 0x00000004070c7825 */
/* 0x000fc800078e020a */
/*04e0*/ F2I.TRUNC.NTZ R8, R23 ; /* 0x0000001700087305 */
/* 0x001062000020f100 */
/*04f0*/ LDG.E R22, [R12.64] ; /* 0x000000040c167981 */
/* 0x000968000c1e1900 */
/*0500*/ LDG.E R23, [R14.64+0x28] ; /* 0x000028040e177981 */
/* 0x001f66000c1e1900 */
/*0510*/ I2F R8, R8 ; /* 0x0000000800087306 */
/* 0x002e240000201400 */
/*0520*/ FFMA R24, R25, R24, R8 ; /* 0x0000001819187223 */
/* 0x001fc40000000008 */
/*0530*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fe200078e020c */
/*0540*/ LDG.E R25, [R14.64+0x2c] ; /* 0x00002c040e197981 */
/* 0x000166000c1e1900 */
/*0550*/ F2I.TRUNC.NTZ R11, R24 ; /* 0x00000018000b7305 */
/* 0x000224000020f100 */
/*0560*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x00236c000c1e1900 */
/*0570*/ I2F R11, R11 ; /* 0x0000000b000b7306 */
/* 0x001e240000201400 */
/*0580*/ FFMA R26, R26, R27, R11 ; /* 0x0000001b1a1a7223 */
/* 0x001fc4000000000b */
/*0590*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*05a0*/ LDG.E R27, [R14.64+0x30] ; /* 0x000030040e1b7981 */
/* 0x000166000c1e1900 */
/*05b0*/ F2I.TRUNC.NTZ R9, R26 ; /* 0x0000001a00097305 */
/* 0x002324000020f100 */
/*05c0*/ LDG.E R26, [R10.64] ; /* 0x000000040a1a7981 */
/* 0x00236c000c1e1900 */
/*05d0*/ I2F R12, R9 ; /* 0x00000009000c7306 */
/* 0x010f240000201400 */
/*05e0*/ FFMA R29, R29, R16, R12 ; /* 0x000000101d1d7223 */
/* 0x010fc4000000000c */
/*05f0*/ IMAD.WIDE R12, R7, 0x4, R10 ; /* 0x00000004070c7825 */
/* 0x000fc800078e020a */
/*0600*/ F2I.TRUNC.NTZ R8, R29 ; /* 0x0000001d00087305 */
/* 0x000822000020f100 */
/*0610*/ LDG.E R10, [R14.64+0x34] ; /* 0x000034040e0a7981 */
/* 0x002368000c1e1900 */
/*0620*/ LDG.E R29, [R12.64] ; /* 0x000000040c1d7981 */
/* 0x010966000c1e1900 */
/*0630*/ I2F R8, R8 ; /* 0x0000000800087306 */
/* 0x001ea40000201400 */
/*0640*/ FFMA R28, R28, R17, R8 ; /* 0x000000111c1c7223 */
/* 0x004fc40000000008 */
/*0650*/ IMAD.WIDE R16, R7.reuse, 0x4, R12 ; /* 0x0000000407107825 */
/* 0x040fe400078e020c */
/*0660*/ LDG.E R12, [R14.64+0x38] ; /* 0x000038040e0c7981 */
/* 0x0102a8000c1e1900 */
/*0670*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x0000a2000c1e1900 */
/*0680*/ IMAD.WIDE R8, R7, 0x4, R16 ; /* 0x0000000407087825 */
/* 0x000fe200078e0210 */
/*0690*/ F2I.TRUNC.NTZ R28, R28 ; /* 0x0000001c001c7305 */
/* 0x000f28000020f100 */
/*06a0*/ LDG.E R13, [R8.64] ; /* 0x00000004080d7981 */
/* 0x000ea8000c1e1900 */
/*06b0*/ LDG.E R16, [R14.64+0x3c] ; /* 0x00003c040e107981 */
/* 0x0012a2000c1e1900 */
/*06c0*/ I2F R28, R28 ; /* 0x0000001c001c7306 */
/* 0x010ee40000201400 */
/*06d0*/ FFMA R18, R19, R18, R28 ; /* 0x0000001213127223 */
/* 0x008fcc000000001c */
/*06e0*/ F2I.TRUNC.NTZ R18, R18 ; /* 0x0000001200127305 */
/* 0x000e30000020f100 */
/*06f0*/ I2F R19, R18 ; /* 0x0000001200137306 */
/* 0x001e240000201400 */
/*0700*/ FFMA R19, R21, R20, R19 ; /* 0x0000001415137223 */
/* 0x001fcc0000000013 */
/*0710*/ F2I.TRUNC.NTZ R19, R19 ; /* 0x0000001300137305 */
/* 0x000e30000020f100 */
/*0720*/ I2F R17, R19 ; /* 0x0000001300117306 */
/* 0x001f640000201400 */
/*0730*/ FFMA R17, R22, R23, R17 ; /* 0x0000001716117223 */
/* 0x020fcc0000000011 */
/*0740*/ F2I.TRUNC.NTZ R17, R17 ; /* 0x0000001100117305 */
/* 0x000e70000020f100 */
/*0750*/ I2F R14, R17 ; /* 0x00000011000e7306 */
/* 0x002e240000201400 */
/*0760*/ FFMA R14, R24, R25, R14 ; /* 0x00000019180e7223 */
/* 0x001fcc000000000e */
/*0770*/ F2I.TRUNC.NTZ R14, R14 ; /* 0x0000000e000e7305 */
/* 0x000e30000020f100 */
/*0780*/ I2F R15, R14 ; /* 0x0000000e000f7306 */
/* 0x001e240000201400 */
/*0790*/ FFMA R15, R26, R27, R15 ; /* 0x0000001b1a0f7223 */
/* 0x001fcc000000000f */
/*07a0*/ F2I.TRUNC.NTZ R15, R15 ; /* 0x0000000f000f7305 */
/* 0x000e30000020f100 */
/*07b0*/ I2F R18, R15 ; /* 0x0000000f00127306 */
/* 0x001e240000201400 */
/*07c0*/ FFMA R10, R29, R10, R18 ; /* 0x0000000a1d0a7223 */
/* 0x001fcc0000000012 */
/*07d0*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000e30000020f100 */
/*07e0*/ I2F R18, R10 ; /* 0x0000000a00127306 */
/* 0x001ea40000201400 */
/*07f0*/ FFMA R11, R11, R12, R18 ; /* 0x0000000c0b0b7223 */
/* 0x004fcc0000000012 */
/*0800*/ F2I.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b7305 */
/* 0x000e30000020f100 */
/*0810*/ I2F R12, R11 ; /* 0x0000000b000c7306 */
/* 0x001e220000201400 */
/*0820*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fe20007ffe0ff */
/*0830*/ FFMA R12, R13, R16, R12 ; /* 0x000000100d0c7223 */
/* 0x001fcc000000000c */
/*0840*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x000e22000020f100 */
/*0850*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe20003f24270 */
/*0860*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0870*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc600078e0208 */
/*0880*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*0890*/ I2F R22, R12 ; /* 0x0000000c00167306 */
/* 0x0010620000201400 */
/*08a0*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fca0007ffe0ff */
/*08b0*/ @P1 BRA 0x220 ; /* 0xfffff96000001947 */
/* 0x000fea000383ffff */
/*08c0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*08d0*/ @!P1 BRA 0xc70 ; /* 0x0000039000009947 */
/* 0x000fea0003800000 */
/*08e0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*08f0*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x0004e2000c1e1900 */
/*0900*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fca0008000f00 */
/*0910*/ IMAD.WIDE R8, R6, 0x4, R8 ; /* 0x0000000406087825 */
/* 0x000fca00078e0208 */
/*0920*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x000ee2000c1e1900 */
/*0930*/ MOV R7, c[0x0][0x17c] ; /* 0x00005f0000077a02 */
/* 0x000fc60000000f00 */
/*0940*/ LDG.E R23, [R8.64+0x4] ; /* 0x0000040408177981 */
/* 0x000f24000c1e1900 */
/*0950*/ IMAD.WIDE R18, R7.reuse, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x040fe400078e0210 */
/*0960*/ LDG.E R24, [R8.64+0x8] ; /* 0x0000080408187981 */
/* 0x000f68000c1e1900 */
/*0970*/ LDG.E R26, [R18.64] ; /* 0x00000004121a7981 */
/* 0x000122000c1e1900 */
/*0980*/ IMAD.WIDE R10, R7, 0x4, R18 ; /* 0x00000004070a7825 */
/* 0x000fc600078e0212 */
/*0990*/ LDG.E R28, [R8.64+0xc] ; /* 0x00000c04081c7981 */
/* 0x000f28000c1e1900 */
/*09a0*/ LDG.E R25, [R10.64] ; /* 0x000000040a197981 */
/* 0x000362000c1e1900 */
/*09b0*/ IMAD.WIDE R12, R7, 0x4, R10 ; /* 0x00000004070c7825 */
/* 0x001fca00078e020a */
/*09c0*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000122000c1e1900 */
/*09d0*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fca00078e020c */
/*09e0*/ LDG.E R29, [R14.64] ; /* 0x000000040e1d7981 */
/* 0x000328000c1e1900 */
/*09f0*/ LDG.E R12, [R8.64+0x10] ; /* 0x00001004080c7981 */
/* 0x001122000c1e1900 */
/*0a00*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x004fc600078e020e */
/*0a10*/ LDG.E R14, [R8.64+0x14] ; /* 0x00001404080e7981 */
/* 0x0020a8000c1e1900 */
/*0a20*/ LDG.E R13, [R16.64] ; /* 0x00000004100d7981 */
/* 0x0002a2000c1e1900 */
/*0a30*/ IMAD.WIDE R10, R7, 0x4, R16 ; /* 0x00000004070a7825 */
/* 0x000fca00078e0210 */
/*0a40*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0000a8000c1e1900 */
/*0a50*/ LDG.E R16, [R8.64+0x18] ; /* 0x0000180408107981 */
/* 0x0022a2000c1e1900 */
/*0a60*/ IMAD.WIDE R18, R7, 0x4, R10 ; /* 0x0000000407127825 */
/* 0x000fc600078e020a */
/*0a70*/ LDG.E R11, [R8.64+0x1c] ; /* 0x00001c04080b7981 */
/* 0x0012a8000c1e1900 */
/*0a80*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x000ea2000c1e1900 */
/*0a90*/ FFMA R20, R20, R21, R22 ; /* 0x0000001514147223 */
/* 0x008fcc0000000016 */
/*0aa0*/ F2I.TRUNC.NTZ R20, R20 ; /* 0x0000001400147305 */
/* 0x000e30000020f100 */
/*0ab0*/ I2F R21, R20 ; /* 0x0000001400157306 */
/* 0x001f240000201400 */
/*0ac0*/ FFMA R21, R26, R23, R21 ; /* 0x000000171a157223 */
/* 0x010fcc0000000015 */
/*0ad0*/ F2I.TRUNC.NTZ R21, R21 ; /* 0x0000001500157305 */
/* 0x000e30000020f100 */
/*0ae0*/ I2F R17, R21 ; /* 0x0000001500117306 */
/* 0x001f640000201400 */
/*0af0*/ FFMA R17, R25, R24, R17 ; /* 0x0000001819117223 */
/* 0x020fcc0000000011 */
/*0b00*/ F2I.TRUNC.NTZ R17, R17 ; /* 0x0000001100117305 */
/* 0x000e30000020f100 */
/*0b10*/ I2F R22, R17 ; /* 0x0000001100167306 */
/* 0x001e240000201400 */
/*0b20*/ FFMA R22, R27, R28, R22 ; /* 0x0000001c1b167223 */
/* 0x001fcc0000000016 */
/*0b30*/ F2I.TRUNC.NTZ R22, R22 ; /* 0x0000001600167305 */
/* 0x000e70000020f100 */
/*0b40*/ I2F R8, R22 ; /* 0x0000001600087306 */
/* 0x002e240000201400 */
/*0b50*/ FFMA R8, R29, R12, R8 ; /* 0x0000000c1d087223 */
/* 0x001fcc0000000008 */
/*0b60*/ F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000e30000020f100 */
/*0b70*/ I2F R9, R8 ; /* 0x0000000800097306 */
/* 0x001ea40000201400 */
/*0b80*/ FFMA R9, R13, R14, R9 ; /* 0x0000000e0d097223 */
/* 0x004fcc0000000009 */
/*0b90*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e30000020f100 */
/*0ba0*/ I2F R12, R9 ; /* 0x00000009000c7306 */
/* 0x001e240000201400 */
/*0bb0*/ FFMA R12, R15, R16, R12 ; /* 0x000000100f0c7223 */
/* 0x001fcc000000000c */
/*0bc0*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x000e30000020f100 */
/*0bd0*/ I2F R13, R12 ; /* 0x0000000c000d7306 */
/* 0x001e240000201400 */
/*0be0*/ FFMA R10, R10, R11, R13 ; /* 0x0000000b0a0a7223 */
/* 0x001fcc000000000d */
/*0bf0*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000e22000020f100 */
/*0c00*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0c10*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0c20*/ IMAD.WIDE R16, R7, 0x4, R18 ; /* 0x0000000407107825 */
/* 0x000fe200078e0212 */
/*0c30*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fc80007ffe0ff */
/*0c40*/ I2F R22, R10 ; /* 0x0000000a00167306 */
/* 0x0010620000201400 */
/*0c50*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*0c60*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fcc00087fe43f */
/*0c70*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0c80*/ @!P0 BRA 0xeb0 ; /* 0x0000022000008947 */
/* 0x000fea0003800000 */
/*0c90*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0ca0*/ LDG.E R19, [R16.64] ; /* 0x0000000410137981 */
/* 0x0004e2000c1e1900 */
/*0cb0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fca0008000f00 */
/*0cc0*/ IMAD.WIDE R8, R6, 0x4, R8 ; /* 0x0000000406087825 */
/* 0x000fca00078e0208 */
/*0cd0*/ LDG.E R18, [R8.64] ; /* 0x0000000408127981 */
/* 0x000ee2000c1e1900 */
/*0ce0*/ MOV R7, c[0x0][0x17c] ; /* 0x00005f0000077a02 */
/* 0x000fc60000000f00 */
/*0cf0*/ LDG.E R20, [R8.64+0x4] ; /* 0x0000040408147981 */
/* 0x000f24000c1e1900 */
/*0d00*/ IMAD.WIDE R14, R7.reuse, 0x4, R16 ; /* 0x00000004070e7825 */
/* 0x040fe400078e0210 */
/*0d10*/ LDG.E R24, [R8.64+0x8] ; /* 0x0000080408187981 */
/* 0x000f68000c1e1900 */
/*0d20*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x000f22000c1e1900 */
/*0d30*/ IMAD.WIDE R12, R7, 0x4, R14 ; /* 0x00000004070c7825 */
/* 0x001fc600078e020e */
/*0d40*/ LDG.E R25, [R8.64+0xc] ; /* 0x00000c0408197981 */
/* 0x000f28000c1e1900 */
/*0d50*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000f62000c1e1900 */
/*0d60*/ IMAD.WIDE R10, R7, 0x4, R12 ; /* 0x00000004070a7825 */
/* 0x000fca00078e020c */
/*0d70*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x004ea2000c1e1900 */
/*0d80*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0d90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0da0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0db0*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0dc0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0dd0*/ FFMA R18, R19, R18, R22 ; /* 0x0000001213127223 */
/* 0x00afcc0000000016 */
/*0de0*/ F2I.TRUNC.NTZ R18, R18 ; /* 0x0000001200127305 */
/* 0x000e30000020f100 */
/*0df0*/ I2F R16, R18 ; /* 0x0000001200107306 */
/* 0x001f240000201400 */
/*0e00*/ FFMA R16, R21, R20, R16 ; /* 0x0000001415107223 */
/* 0x010fcc0000000010 */
/*0e10*/ F2I.TRUNC.NTZ R16, R16 ; /* 0x0000001000107305 */
/* 0x000e30000020f100 */
/*0e20*/ I2F R14, R16 ; /* 0x00000010000e7306 */
/* 0x001f640000201400 */
/*0e30*/ FFMA R14, R23, R24, R14 ; /* 0x00000018170e7223 */
/* 0x020fcc000000000e */
/*0e40*/ F2I.TRUNC.NTZ R14, R14 ; /* 0x0000000e000e7305 */
/* 0x000e30000020f100 */
/*0e50*/ I2F R12, R14 ; /* 0x0000000e000c7306 */
/* 0x001ea40000201400 */
/*0e60*/ FFMA R12, R17, R25, R12 ; /* 0x00000019110c7223 */
/* 0x004fcc000000000c */
/*0e70*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x000e22000020f100 */
/*0e80*/ IMAD.WIDE R16, R7, 0x4, R10 ; /* 0x0000000407107825 */
/* 0x000fce00078e020a */
/*0e90*/ I2F R22, R12 ; /* 0x0000000c00167306 */
/* 0x0010640000201400 */
/*0ea0*/ @P0 BRA 0xc90 ; /* 0xfffffde000000947 */
/* 0x003fea000383ffff */
/*0eb0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0ec0*/ @!P0 BRA 0x1000 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0ed0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0ee0*/ IMAD R5, R0, c[0x0][0x178], R4 ; /* 0x00005e0000057a24 */
/* 0x000fe400078e0204 */
/*0ef0*/ IMAD R6, R4, c[0x0][0x17c], R3 ; /* 0x00005f0004067a24 */
/* 0x000fce00078e0203 */
/*0f00*/ IMAD.WIDE R4, R5, R7, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fc800078e0207 */
/*0f10*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe200078e0207 */
/*0f20*/ MOV R8, R4 ; /* 0x0000000400087202 */
/* 0x000fc80000000f00 */
/*0f30*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x000fe20000000f00 */
/*0f40*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x0064ea000c1e1900 */
/*0f50*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0008e2000c1e1900 */
/*0f60*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0f70*/ MOV R11, c[0x0][0x17c] ; /* 0x00005f00000b7a02 */
/* 0x000fc40000000f00 */
/*0f80*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f05270 */
/*0f90*/ IADD3 R8, P1, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe20007f3e0ff */
/*0fa0*/ IMAD.WIDE R6, R11, 0x4, R6 ; /* 0x000000040b067825 */
/* 0x004fc600078e0206 */
/*0fb0*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x010fe20000ffe4ff */
/*0fc0*/ FFMA R9, R9, R4, R22 ; /* 0x0000000409097223 */
/* 0x00afcc0000000016 */
/*0fd0*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e70000020f100 */
/*0fe0*/ I2F R22, R9 ; /* 0x0000000900167306 */
/* 0x0022a20000201400 */
/*0ff0*/ @P0 BRA 0xf30 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*1000*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*1010*/ IMAD R3, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000037a24 */
/* 0x000fc800078e0203 */
/*1020*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*1030*/ STG.E [R2.64], R22 ; /* 0x0000001602007986 */
/* 0x006fe2000c101904 */
/*1040*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1050*/ BRA 0x1050; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <malloc.h>
#include <stdlib.h>
#include <sys/time.h>
//CUDA
#include <cuda.h>
double wtime(void)
{
static struct timeval tv0;
double time_;
gettimeofday(&tv0,(struct timezone*)0);
time_=(double)((tv0.tv_usec + (tv0.tv_sec)*1000000));
return( time_/1000000);
}
void init_matrix(float *M, int hM, int wM, float k)
{
int i,j;
for (i=0; i<hM; i++)
for (j=0; j<wM; j++)
if (i==j)
M[i*wM+j] = k*k*1.0f;
else
M[i*wM+j] = -k*1.0f;
}
void print_matrix(float *M, int hM, int wM)
{
int i,j;
for (i=0; i<hM; i++){
printf("Line %i: ", i);
for (j=0; j<wM; j++)
printf("%4.1f ", M[i*wM+j]);
printf("\n");
}
}
int check_matrix(float *h, float *d, int hM, int wM)
{
int i,j;
for (i=0; i<hM; i++){
for (j=0; j<wM; j++)
if (fabsf(h[i*wM+j]-d[i*wM+j])>1e-5)
{
printf("device!=host %f!=%f in (%i,%i)\n", h[i*wM+j], d[i*wM+j], i, j);
return(0);
}
}
return (1);
}
void Mul(float *A, float *B, int hA, int wA, int wB, float *C)
{
int i,j,k;
for(i = 0; i < hA; i++){//recorre las filas de A
for(j = 0; j < wB; j++){
C[i*wB+j] = 0;
for(k = 0; k < wA; k++){
C[i*wB+j] += A[i*wA+k]*B[j+k*wB];
//printf(" %d _ %d ", (i*wA)+k, j+(k*wB));
//printf(" %f * %f ", A[i*wA+k], B[j+k*wB]);
}
//printf("\n");
//printf(" %d ",i*wB+j);
}
}
}
__global__ void mulMatrixGPU(float *A, float *B, float *C, int wa, int wb, int ha )
{
int k, sum = 0;
int col = threadIdx.x + blockDim.x * blockIdx.x; //i
int fil = threadIdx.y + blockDim.y * blockIdx.y; //j
if (col < wb && fil < ha) { //ojo no son cuadradas !!
for (k = 0; k < wa; k++) {
sum += A[fil * wa + k] * B[k * wb + col];
}
C[fil * wb + col] = sum;
}
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv)
{
// Matrix variables
float *A, *B, *C, *C_host;
float *A_GPU, *B_GPU, *C_GPU;
int hA, wA, hB, wB;
double t0, t1;
setbuf(stdout, NULL);
if (argc!=4){
printf("./exec hA hB/WA wB\n");
exit(-1);
}
hA = atoi(argv[1]);
hB = wA = atoi(argv[2]);
wB = atoi(argv[3]);
// Init A and B, malloc C
int size_A = wA * hA;
A = (float*)malloc(size_A*sizeof(float));
init_matrix(A, hA, wA,2.0);
int size_B = wB * hB;
B = (float*)malloc(size_B*sizeof(float));
init_matrix(B, hB, wB,1.0);
int size_C = wB * hA;
C = (float*)malloc(size_C*sizeof(float));
t0 = wtime();
Mul(A, B, hA, wA, wB, C);
t1 = wtime(); printf("Time CPU=%f\n", t1-t0);
/* Mallocs GPU */
cudaMalloc((void **) &A_GPU, size_A*sizeof(float));
cudaMalloc((void **) &B_GPU, size_B*sizeof(float));
cudaMalloc((void **) &C_GPU, size_C*sizeof(float));
/* CPU -> GPU */
cudaMemcpy(B_GPU, B, size_B*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(A_GPU, A, size_A*sizeof(float), cudaMemcpyHostToDevice);
/*****************/
/* Add Matrix GPU*/
/*****************/
dim3 dimBlock(16,16); // nThreads por bloque
dim3 dimGrid(hA,wB);//numBloques
t0 = wtime();
mulMatrixGPU<<<dimGrid,dimBlock>>>(A_GPU, B_GPU, C_GPU, wA, wB,hA);// si las matrices no son cuadradas necesito ambos anchos CREO
cudaThreadSynchronize();
t1 = wtime(); printf("Time GPU=%f\n", t1-t0);
/* GPU->CPU */
C_host = (float*)malloc(size_C*sizeof(float));
cudaMemcpy(C_host, C_GPU, size_C*sizeof(float), cudaMemcpyDeviceToHost);
check_matrix(C, C_host, hA, wB);
// print Matrix
//printf("\n\nMATRIX A\n");print_matrix(A, hA, wA);
//printf("\n\nMATRIX B\n");print_matrix(B, hB, wB);
//printf("\n\nMATRIX C\n");print_matrix(C, hA, wB);
//printf("\n\nMATRIX *C\n");print_matrix(C_host, hA, wB);
/* Free CPU */
free(A);
free(B);
free(C);
free(C_host);
/* Free GPU */
cudaFree(A_GPU);
cudaFree(B_GPU);
cudaFree(C_GPU);
return (1);
} | .file "tmpxft_000c416d_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5wtimev
.type _Z5wtimev, @function
_Z5wtimev:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $0, %esi
leaq _ZZ5wtimevE3tv0(%rip), %rdi
call gettimeofday@PLT
imulq $1000000, _ZZ5wtimevE3tv0(%rip), %rax
addq 8+_ZZ5wtimevE3tv0(%rip), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z5wtimev, .-_Z5wtimev
.globl _Z11init_matrixPfiif
.type _Z11init_matrixPfiif, @function
_Z11init_matrixPfiif:
.LFB2058:
.cfi_startproc
endbr64
movq %rdi, %r9
testl %esi, %esi
jle .L5
movl $0, %r8d
movl $0, %edi
movaps %xmm0, %xmm1
xorps .LC1(%rip), %xmm1
jmp .L7
.L15:
leal (%rax,%r8), %ecx
movslq %ecx, %rcx
movaps %xmm0, %xmm2
mulss %xmm0, %xmm2
movss %xmm2, (%r9,%rcx,4)
.L9:
addl $1, %eax
cmpl %eax, %edx
je .L11
.L10:
cmpl %eax, %edi
je .L15
leal (%rax,%r8), %ecx
movslq %ecx, %rcx
movss %xmm1, (%r9,%rcx,4)
jmp .L9
.L11:
addl $1, %edi
addl %edx, %r8d
cmpl %edi, %esi
je .L5
.L7:
movl $0, %eax
testl %edx, %edx
jg .L10
jmp .L11
.L5:
ret
.cfi_endproc
.LFE2058:
.size _Z11init_matrixPfiif, .-_Z11init_matrixPfiif
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Line %i: "
.LC3:
.string "%4.1f "
.LC4:
.string "\n"
.text
.globl _Z12print_matrixPfii
.type _Z12print_matrixPfii, @function
_Z12print_matrixPfii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L16
movl %edx, %r15d
movl $0, %r14d
movl $0, %r13d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq .LC3(%rip), %r12
.L20:
movl %r13d, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %r15d, %r15d
jle .L18
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L19:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L19
.L18:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
jne .L20
.L16:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z12print_matrixPfii, .-_Z12print_matrixPfii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "device!=host %f!=%f in (%i,%i)\n"
.text
.globl _Z12check_matrixPfS_ii
.type _Z12check_matrixPfS_ii, @function
_Z12check_matrixPfS_ii:
.LFB2060:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L32
movq %rsi, %r9
movl %edx, %r10d
movl %ecx, %esi
movl $0, %r11d
movl $0, %r8d
movslq %ecx, %rdx
movss .LC5(%rip), %xmm4
movsd .LC6(%rip), %xmm3
.L38:
testl %esi, %esi
jle .L44
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
jmp .L30
.L45:
cvtss2sd %xmm0, %xmm0
movl %r8d, %edx
cvtss2sd %xmm1, %xmm1
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl $0, %eax
.L24:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
testl %esi, %esi
jle .L31
.L30:
movslq %r11d, %rax
salq $2, %rax
leaq (%rdi,%rax), %rbx
addq %r9, %rax
movl $0, %ecx
.L29:
movss (%rbx,%rcx,4), %xmm0
movss (%rax,%rcx,4), %xmm1
movaps %xmm0, %xmm2
subss %xmm1, %xmm2
andps %xmm4, %xmm2
cvtss2sd %xmm2, %xmm2
comisd %xmm3, %xmm2
ja .L45
addq $1, %rcx
cmpq %rdx, %rcx
jne .L29
.L31:
addl $1, %r8d
addl %esi, %r11d
cmpl %r8d, %r10d
jne .L46
movl $1, %eax
jmp .L24
.L32:
.cfi_def_cfa_offset 8
.cfi_restore 3
movl $1, %eax
ret
.L44:
addl $1, %r8d
addl %esi, %r11d
cmpl %r8d, %r10d
jne .L38
movl $1, %eax
ret
.cfi_endproc
.LFE2060:
.size _Z12check_matrixPfS_ii, .-_Z12check_matrixPfS_ii
.globl _Z3MulPfS_iiiS_
.type _Z3MulPfS_iiiS_, @function
_Z3MulPfS_iiiS_:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rsi, -8(%rsp)
movl %edx, -12(%rsp)
testl %edx, %edx
jle .L47
movq %rdi, %rbx
movl %ecx, %ebp
movl %r8d, %r11d
movslq %r8d, %rdi
salq $2, %rdi
movl $0, %r13d
movl $0, %ecx
movl $0, %edx
movslq %ebp, %r14
movq %r9, %r8
movq %r14, %rsi
jmp .L49
.L53:
movslq %ecx, %rax
leaq (%r8,%rax,4), %r10
movq -8(%rsp), %r14
movslq %r13d, %rax
leaq (%rbx,%rax,4), %r15
addq %rsi, %rax
leaq (%rbx,%rax,4), %r9
movl $0, %r12d
movl %edx, -20(%rsp)
movl %ecx, -16(%rsp)
.L52:
movq %r10, %rcx
movl $0x00000000, (%r10)
testl %ebp, %ebp
jle .L50
movq %r14, %rdx
movq %r15, %rax
.L51:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss (%rcx), %xmm0
movss %xmm0, (%rcx)
addq $4, %rax
addq %rdi, %rdx
cmpq %r9, %rax
jne .L51
.L50:
addl $1, %r12d
addq $4, %r10
addq $4, %r14
cmpl %r12d, %r11d
jne .L52
movl -20(%rsp), %edx
movl -16(%rsp), %ecx
.L54:
addl $1, %edx
addl %r11d, %ecx
addl %ebp, %r13d
cmpl %edx, -12(%rsp)
je .L47
.L49:
testl %r11d, %r11d
jg .L53
jmp .L54
.L47:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z3MulPfS_iiiS_, .-_Z3MulPfS_iiiS_
.globl _Z39__device_stub__Z12mulMatrixGPUPfS_S_iiiPfS_S_iii
.type _Z39__device_stub__Z12mulMatrixGPUPfS_S_iiiPfS_S_iii, @function
_Z39__device_stub__Z12mulMatrixGPUPfS_S_iiiPfS_S_iii:
.LFB2087:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L62
.L58:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L63
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L62:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12mulMatrixGPUPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L58
.L63:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z39__device_stub__Z12mulMatrixGPUPfS_S_iiiPfS_S_iii, .-_Z39__device_stub__Z12mulMatrixGPUPfS_S_iiiPfS_S_iii
.globl _Z12mulMatrixGPUPfS_S_iii
.type _Z12mulMatrixGPUPfS_S_iii, @function
_Z12mulMatrixGPUPfS_S_iii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z12mulMatrixGPUPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z12mulMatrixGPUPfS_S_iii, .-_Z12mulMatrixGPUPfS_S_iii
.section .rodata.str1.1
.LC9:
.string "./exec hA hB/WA wB\n"
.LC12:
.string "Time CPU=%f\n"
.LC13:
.string "Time GPU=%f\n"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movl %edi, %ebx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $0, %esi
movq stdout(%rip), %rdi
call setbuf@PLT
cmpl $4, %ebx
jne .L71
movq 8(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movl %eax, 32(%rsp)
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, 12(%rsp)
movq 24(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, 36(%rsp)
movl %r14d, %r13d
imull %ebx, %r13d
movslq %r13d, %r13
salq $2, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r15
movss .LC10(%rip), %xmm0
movl 12(%rsp), %ebp
movl %ebp, %edx
movl 32(%rsp), %esi
movq %rax, %rdi
call _Z11init_matrixPfiif
imull %r12d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movss .LC11(%rip), %xmm0
movl 36(%rsp), %edx
movl %ebp, 12(%rsp)
movl %ebp, %esi
movq %rax, 16(%rsp)
movq %rax, %rdi
call _Z11init_matrixPfiif
movl %r14d, %ebp
imull %r12d, %ebp
movslq %ebp, %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
call _Z5wtimev
movsd %xmm0, 40(%rsp)
movq 24(%rsp), %r9
movl %r12d, %r8d
movl 12(%rsp), %ecx
movl 32(%rsp), %edx
movq 16(%rsp), %rsi
movq %r15, %rdi
call _Z3MulPfS_iiiS_
call _Z5wtimev
subsd 40(%rsp), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 56(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r15, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 80(%rsp)
movl $16, 84(%rsp)
movl $1, 88(%rsp)
movl %r14d, 92(%rsp)
movl %r12d, 96(%rsp)
movl $1, 100(%rsp)
call _Z5wtimev
movsd %xmm0, 40(%rsp)
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L72
.L68:
call cudaThreadSynchronize@PLT
call _Z5wtimev
subsd 40(%rsp), %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movq %rbp, %rdx
movq 72(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movl 36(%rsp), %ecx
movl 32(%rsp), %edx
movq %rbx, %rsi
movq 24(%rsp), %r14
movq %r14, %rdi
call _Z12check_matrixPfS_ii
movq %r15, %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L73
movl $1, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L71:
.cfi_restore_state
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L72:
movl %r14d, %r9d
movl %r12d, %r8d
movl 12(%rsp), %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z39__device_stub__Z12mulMatrixGPUPfS_S_iiiPfS_S_iii
jmp .L68
.L73:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z12mulMatrixGPUPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z12mulMatrixGPUPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZ5wtimevE3tv0
.comm _ZZ5wtimevE3tv0,16,16
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC1:
.long -2147483648
.long 0
.long 0
.long 0
.align 16
.LC5:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC6:
.long -1998362383
.long 1055193269
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC10:
.long 1073741824
.align 4
.LC11:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <malloc.h>
#include <stdlib.h>
#include <sys/time.h>
//CUDA
#include <cuda.h>
double wtime(void)
{
static struct timeval tv0;
double time_;
gettimeofday(&tv0,(struct timezone*)0);
time_=(double)((tv0.tv_usec + (tv0.tv_sec)*1000000));
return( time_/1000000);
}
void init_matrix(float *M, int hM, int wM, float k)
{
int i,j;
for (i=0; i<hM; i++)
for (j=0; j<wM; j++)
if (i==j)
M[i*wM+j] = k*k*1.0f;
else
M[i*wM+j] = -k*1.0f;
}
void print_matrix(float *M, int hM, int wM)
{
int i,j;
for (i=0; i<hM; i++){
printf("Line %i: ", i);
for (j=0; j<wM; j++)
printf("%4.1f ", M[i*wM+j]);
printf("\n");
}
}
int check_matrix(float *h, float *d, int hM, int wM)
{
int i,j;
for (i=0; i<hM; i++){
for (j=0; j<wM; j++)
if (fabsf(h[i*wM+j]-d[i*wM+j])>1e-5)
{
printf("device!=host %f!=%f in (%i,%i)\n", h[i*wM+j], d[i*wM+j], i, j);
return(0);
}
}
return (1);
}
void Mul(float *A, float *B, int hA, int wA, int wB, float *C)
{
int i,j,k;
for(i = 0; i < hA; i++){//recorre las filas de A
for(j = 0; j < wB; j++){
C[i*wB+j] = 0;
for(k = 0; k < wA; k++){
C[i*wB+j] += A[i*wA+k]*B[j+k*wB];
//printf(" %d _ %d ", (i*wA)+k, j+(k*wB));
//printf(" %f * %f ", A[i*wA+k], B[j+k*wB]);
}
//printf("\n");
//printf(" %d ",i*wB+j);
}
}
}
__global__ void mulMatrixGPU(float *A, float *B, float *C, int wa, int wb, int ha )
{
int k, sum = 0;
int col = threadIdx.x + blockDim.x * blockIdx.x; //i
int fil = threadIdx.y + blockDim.y * blockIdx.y; //j
if (col < wb && fil < ha) { //ojo no son cuadradas !!
for (k = 0; k < wa; k++) {
sum += A[fil * wa + k] * B[k * wb + col];
}
C[fil * wb + col] = sum;
}
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv)
{
// Matrix variables
float *A, *B, *C, *C_host;
float *A_GPU, *B_GPU, *C_GPU;
int hA, wA, hB, wB;
double t0, t1;
setbuf(stdout, NULL);
if (argc!=4){
printf("./exec hA hB/WA wB\n");
exit(-1);
}
hA = atoi(argv[1]);
hB = wA = atoi(argv[2]);
wB = atoi(argv[3]);
// Init A and B, malloc C
int size_A = wA * hA;
A = (float*)malloc(size_A*sizeof(float));
init_matrix(A, hA, wA,2.0);
int size_B = wB * hB;
B = (float*)malloc(size_B*sizeof(float));
init_matrix(B, hB, wB,1.0);
int size_C = wB * hA;
C = (float*)malloc(size_C*sizeof(float));
t0 = wtime();
Mul(A, B, hA, wA, wB, C);
t1 = wtime(); printf("Time CPU=%f\n", t1-t0);
/* Mallocs GPU */
cudaMalloc((void **) &A_GPU, size_A*sizeof(float));
cudaMalloc((void **) &B_GPU, size_B*sizeof(float));
cudaMalloc((void **) &C_GPU, size_C*sizeof(float));
/* CPU -> GPU */
cudaMemcpy(B_GPU, B, size_B*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(A_GPU, A, size_A*sizeof(float), cudaMemcpyHostToDevice);
/*****************/
/* Add Matrix GPU*/
/*****************/
dim3 dimBlock(16,16); // nThreads por bloque
dim3 dimGrid(hA,wB);//numBloques
t0 = wtime();
mulMatrixGPU<<<dimGrid,dimBlock>>>(A_GPU, B_GPU, C_GPU, wA, wB,hA);// si las matrices no son cuadradas necesito ambos anchos CREO
cudaThreadSynchronize();
t1 = wtime(); printf("Time GPU=%f\n", t1-t0);
/* GPU->CPU */
C_host = (float*)malloc(size_C*sizeof(float));
cudaMemcpy(C_host, C_GPU, size_C*sizeof(float), cudaMemcpyDeviceToHost);
check_matrix(C, C_host, hA, wB);
// print Matrix
//printf("\n\nMATRIX A\n");print_matrix(A, hA, wA);
//printf("\n\nMATRIX B\n");print_matrix(B, hB, wB);
//printf("\n\nMATRIX C\n");print_matrix(C, hA, wB);
//printf("\n\nMATRIX *C\n");print_matrix(C_host, hA, wB);
/* Free CPU */
free(A);
free(B);
free(C);
free(C_host);
/* Free GPU */
cudaFree(A_GPU);
cudaFree(B_GPU);
cudaFree(C_GPU);
return (1);
} | #include <stdio.h>
#include <malloc.h>
#include <stdlib.h>
#include <sys/time.h>
//CUDA
#include <hip/hip_runtime.h>
double wtime(void)
{
static struct timeval tv0;
double time_;
gettimeofday(&tv0,(struct timezone*)0);
time_=(double)((tv0.tv_usec + (tv0.tv_sec)*1000000));
return( time_/1000000);
}
void init_matrix(float *M, int hM, int wM, float k)
{
int i,j;
for (i=0; i<hM; i++)
for (j=0; j<wM; j++)
if (i==j)
M[i*wM+j] = k*k*1.0f;
else
M[i*wM+j] = -k*1.0f;
}
void print_matrix(float *M, int hM, int wM)
{
int i,j;
for (i=0; i<hM; i++){
printf("Line %i: ", i);
for (j=0; j<wM; j++)
printf("%4.1f ", M[i*wM+j]);
printf("\n");
}
}
int check_matrix(float *h, float *d, int hM, int wM)
{
int i,j;
for (i=0; i<hM; i++){
for (j=0; j<wM; j++)
if (fabsf(h[i*wM+j]-d[i*wM+j])>1e-5)
{
printf("device!=host %f!=%f in (%i,%i)\n", h[i*wM+j], d[i*wM+j], i, j);
return(0);
}
}
return (1);
}
void Mul(float *A, float *B, int hA, int wA, int wB, float *C)
{
int i,j,k;
for(i = 0; i < hA; i++){//recorre las filas de A
for(j = 0; j < wB; j++){
C[i*wB+j] = 0;
for(k = 0; k < wA; k++){
C[i*wB+j] += A[i*wA+k]*B[j+k*wB];
//printf(" %d _ %d ", (i*wA)+k, j+(k*wB));
//printf(" %f * %f ", A[i*wA+k], B[j+k*wB]);
}
//printf("\n");
//printf(" %d ",i*wB+j);
}
}
}
__global__ void mulMatrixGPU(float *A, float *B, float *C, int wa, int wb, int ha )
{
int k, sum = 0;
int col = threadIdx.x + blockDim.x * blockIdx.x; //i
int fil = threadIdx.y + blockDim.y * blockIdx.y; //j
if (col < wb && fil < ha) { //ojo no son cuadradas !!
for (k = 0; k < wa; k++) {
sum += A[fil * wa + k] * B[k * wb + col];
}
C[fil * wb + col] = sum;
}
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv)
{
// Matrix variables
float *A, *B, *C, *C_host;
float *A_GPU, *B_GPU, *C_GPU;
int hA, wA, hB, wB;
double t0, t1;
setbuf(stdout, NULL);
if (argc!=4){
printf("./exec hA hB/WA wB\n");
exit(-1);
}
hA = atoi(argv[1]);
hB = wA = atoi(argv[2]);
wB = atoi(argv[3]);
// Init A and B, malloc C
int size_A = wA * hA;
A = (float*)malloc(size_A*sizeof(float));
init_matrix(A, hA, wA,2.0);
int size_B = wB * hB;
B = (float*)malloc(size_B*sizeof(float));
init_matrix(B, hB, wB,1.0);
int size_C = wB * hA;
C = (float*)malloc(size_C*sizeof(float));
t0 = wtime();
Mul(A, B, hA, wA, wB, C);
t1 = wtime(); printf("Time CPU=%f\n", t1-t0);
/* Mallocs GPU */
hipMalloc((void **) &A_GPU, size_A*sizeof(float));
hipMalloc((void **) &B_GPU, size_B*sizeof(float));
hipMalloc((void **) &C_GPU, size_C*sizeof(float));
/* CPU -> GPU */
hipMemcpy(B_GPU, B, size_B*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(A_GPU, A, size_A*sizeof(float), hipMemcpyHostToDevice);
/*****************/
/* Add Matrix GPU*/
/*****************/
dim3 dimBlock(16,16); // nThreads por bloque
dim3 dimGrid(hA,wB);//numBloques
t0 = wtime();
mulMatrixGPU<<<dimGrid,dimBlock>>>(A_GPU, B_GPU, C_GPU, wA, wB,hA);// si las matrices no son cuadradas necesito ambos anchos CREO
hipDeviceSynchronize();
t1 = wtime(); printf("Time GPU=%f\n", t1-t0);
/* GPU->CPU */
C_host = (float*)malloc(size_C*sizeof(float));
hipMemcpy(C_host, C_GPU, size_C*sizeof(float), hipMemcpyDeviceToHost);
check_matrix(C, C_host, hA, wB);
// print Matrix
//printf("\n\nMATRIX A\n");print_matrix(A, hA, wA);
//printf("\n\nMATRIX B\n");print_matrix(B, hB, wB);
//printf("\n\nMATRIX C\n");print_matrix(C, hA, wB);
//printf("\n\nMATRIX *C\n");print_matrix(C_host, hA, wB);
/* Free CPU */
free(A);
free(B);
free(C);
free(C_host);
/* Free GPU */
hipFree(A_GPU);
hipFree(B_GPU);
hipFree(C_GPU);
return (1);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <malloc.h>
#include <stdlib.h>
#include <sys/time.h>
//CUDA
#include <hip/hip_runtime.h>
double wtime(void)
{
static struct timeval tv0;
double time_;
gettimeofday(&tv0,(struct timezone*)0);
time_=(double)((tv0.tv_usec + (tv0.tv_sec)*1000000));
return( time_/1000000);
}
void init_matrix(float *M, int hM, int wM, float k)
{
int i,j;
for (i=0; i<hM; i++)
for (j=0; j<wM; j++)
if (i==j)
M[i*wM+j] = k*k*1.0f;
else
M[i*wM+j] = -k*1.0f;
}
void print_matrix(float *M, int hM, int wM)
{
int i,j;
for (i=0; i<hM; i++){
printf("Line %i: ", i);
for (j=0; j<wM; j++)
printf("%4.1f ", M[i*wM+j]);
printf("\n");
}
}
int check_matrix(float *h, float *d, int hM, int wM)
{
int i,j;
for (i=0; i<hM; i++){
for (j=0; j<wM; j++)
if (fabsf(h[i*wM+j]-d[i*wM+j])>1e-5)
{
printf("device!=host %f!=%f in (%i,%i)\n", h[i*wM+j], d[i*wM+j], i, j);
return(0);
}
}
return (1);
}
void Mul(float *A, float *B, int hA, int wA, int wB, float *C)
{
int i,j,k;
for(i = 0; i < hA; i++){//recorre las filas de A
for(j = 0; j < wB; j++){
C[i*wB+j] = 0;
for(k = 0; k < wA; k++){
C[i*wB+j] += A[i*wA+k]*B[j+k*wB];
//printf(" %d _ %d ", (i*wA)+k, j+(k*wB));
//printf(" %f * %f ", A[i*wA+k], B[j+k*wB]);
}
//printf("\n");
//printf(" %d ",i*wB+j);
}
}
}
__global__ void mulMatrixGPU(float *A, float *B, float *C, int wa, int wb, int ha )
{
int k, sum = 0;
int col = threadIdx.x + blockDim.x * blockIdx.x; //i
int fil = threadIdx.y + blockDim.y * blockIdx.y; //j
if (col < wb && fil < ha) { //ojo no son cuadradas !!
for (k = 0; k < wa; k++) {
sum += A[fil * wa + k] * B[k * wb + col];
}
C[fil * wb + col] = sum;
}
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv)
{
// Matrix variables
float *A, *B, *C, *C_host;
float *A_GPU, *B_GPU, *C_GPU;
int hA, wA, hB, wB;
double t0, t1;
setbuf(stdout, NULL);
if (argc!=4){
printf("./exec hA hB/WA wB\n");
exit(-1);
}
hA = atoi(argv[1]);
hB = wA = atoi(argv[2]);
wB = atoi(argv[3]);
// Init A and B, malloc C
int size_A = wA * hA;
A = (float*)malloc(size_A*sizeof(float));
init_matrix(A, hA, wA,2.0);
int size_B = wB * hB;
B = (float*)malloc(size_B*sizeof(float));
init_matrix(B, hB, wB,1.0);
int size_C = wB * hA;
C = (float*)malloc(size_C*sizeof(float));
t0 = wtime();
Mul(A, B, hA, wA, wB, C);
t1 = wtime(); printf("Time CPU=%f\n", t1-t0);
/* Mallocs GPU */
hipMalloc((void **) &A_GPU, size_A*sizeof(float));
hipMalloc((void **) &B_GPU, size_B*sizeof(float));
hipMalloc((void **) &C_GPU, size_C*sizeof(float));
/* CPU -> GPU */
hipMemcpy(B_GPU, B, size_B*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(A_GPU, A, size_A*sizeof(float), hipMemcpyHostToDevice);
/*****************/
/* Add Matrix GPU*/
/*****************/
dim3 dimBlock(16,16); // nThreads por bloque
dim3 dimGrid(hA,wB);//numBloques
t0 = wtime();
mulMatrixGPU<<<dimGrid,dimBlock>>>(A_GPU, B_GPU, C_GPU, wA, wB,hA);// si las matrices no son cuadradas necesito ambos anchos CREO
hipDeviceSynchronize();
t1 = wtime(); printf("Time GPU=%f\n", t1-t0);
/* GPU->CPU */
C_host = (float*)malloc(size_C*sizeof(float));
hipMemcpy(C_host, C_GPU, size_C*sizeof(float), hipMemcpyDeviceToHost);
check_matrix(C, C_host, hA, wB);
// print Matrix
//printf("\n\nMATRIX A\n");print_matrix(A, hA, wA);
//printf("\n\nMATRIX B\n");print_matrix(B, hB, wB);
//printf("\n\nMATRIX C\n");print_matrix(C, hA, wB);
//printf("\n\nMATRIX *C\n");print_matrix(C_host, hA, wB);
/* Free CPU */
free(A);
free(B);
free(C);
free(C_host);
/* Free GPU */
hipFree(A_GPU);
hipFree(B_GPU);
hipFree(C_GPU);
return (1);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12mulMatrixGPUPfS_S_iii
.globl _Z12mulMatrixGPUPfS_S_iii
.p2align 8
.type _Z12mulMatrixGPUPfS_S_iii,@function
_Z12mulMatrixGPUPfS_S_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x1c
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s9, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_7
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cvt_f32_i32_e32 v6, v6
s_add_i32 s2, s2, -1
s_cmp_lg_u32 s2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s8, v4
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v6, v6
s_cbranch_scc1 .LBB0_3
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_i32_e32 v2, v6
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v2, 0
.LBB0_6:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v1, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12mulMatrixGPUPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12mulMatrixGPUPfS_S_iii, .Lfunc_end0-_Z12mulMatrixGPUPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12mulMatrixGPUPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12mulMatrixGPUPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <malloc.h>
#include <stdlib.h>
#include <sys/time.h>
//CUDA
#include <hip/hip_runtime.h>
double wtime(void)
{
static struct timeval tv0;
double time_;
gettimeofday(&tv0,(struct timezone*)0);
time_=(double)((tv0.tv_usec + (tv0.tv_sec)*1000000));
return( time_/1000000);
}
void init_matrix(float *M, int hM, int wM, float k)
{
int i,j;
for (i=0; i<hM; i++)
for (j=0; j<wM; j++)
if (i==j)
M[i*wM+j] = k*k*1.0f;
else
M[i*wM+j] = -k*1.0f;
}
void print_matrix(float *M, int hM, int wM)
{
int i,j;
for (i=0; i<hM; i++){
printf("Line %i: ", i);
for (j=0; j<wM; j++)
printf("%4.1f ", M[i*wM+j]);
printf("\n");
}
}
int check_matrix(float *h, float *d, int hM, int wM)
{
int i,j;
for (i=0; i<hM; i++){
for (j=0; j<wM; j++)
if (fabsf(h[i*wM+j]-d[i*wM+j])>1e-5)
{
printf("device!=host %f!=%f in (%i,%i)\n", h[i*wM+j], d[i*wM+j], i, j);
return(0);
}
}
return (1);
}
void Mul(float *A, float *B, int hA, int wA, int wB, float *C)
{
int i,j,k;
for(i = 0; i < hA; i++){//recorre las filas de A
for(j = 0; j < wB; j++){
C[i*wB+j] = 0;
for(k = 0; k < wA; k++){
C[i*wB+j] += A[i*wA+k]*B[j+k*wB];
//printf(" %d _ %d ", (i*wA)+k, j+(k*wB));
//printf(" %f * %f ", A[i*wA+k], B[j+k*wB]);
}
//printf("\n");
//printf(" %d ",i*wB+j);
}
}
}
__global__ void mulMatrixGPU(float *A, float *B, float *C, int wa, int wb, int ha )
{
int k, sum = 0;
int col = threadIdx.x + blockDim.x * blockIdx.x; //i
int fil = threadIdx.y + blockDim.y * blockIdx.y; //j
if (col < wb && fil < ha) { //ojo no son cuadradas !!
for (k = 0; k < wa; k++) {
sum += A[fil * wa + k] * B[k * wb + col];
}
C[fil * wb + col] = sum;
}
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv)
{
// Matrix variables
float *A, *B, *C, *C_host;
float *A_GPU, *B_GPU, *C_GPU;
int hA, wA, hB, wB;
double t0, t1;
setbuf(stdout, NULL);
if (argc!=4){
printf("./exec hA hB/WA wB\n");
exit(-1);
}
hA = atoi(argv[1]);
hB = wA = atoi(argv[2]);
wB = atoi(argv[3]);
// Init A and B, malloc C
int size_A = wA * hA;
A = (float*)malloc(size_A*sizeof(float));
init_matrix(A, hA, wA,2.0);
int size_B = wB * hB;
B = (float*)malloc(size_B*sizeof(float));
init_matrix(B, hB, wB,1.0);
int size_C = wB * hA;
C = (float*)malloc(size_C*sizeof(float));
t0 = wtime();
Mul(A, B, hA, wA, wB, C);
t1 = wtime(); printf("Time CPU=%f\n", t1-t0);
/* Mallocs GPU */
hipMalloc((void **) &A_GPU, size_A*sizeof(float));
hipMalloc((void **) &B_GPU, size_B*sizeof(float));
hipMalloc((void **) &C_GPU, size_C*sizeof(float));
/* CPU -> GPU */
hipMemcpy(B_GPU, B, size_B*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(A_GPU, A, size_A*sizeof(float), hipMemcpyHostToDevice);
/*****************/
/* Add Matrix GPU*/
/*****************/
dim3 dimBlock(16,16); // nThreads por bloque
dim3 dimGrid(hA,wB);//numBloques
t0 = wtime();
mulMatrixGPU<<<dimGrid,dimBlock>>>(A_GPU, B_GPU, C_GPU, wA, wB,hA);// si las matrices no son cuadradas necesito ambos anchos CREO
hipDeviceSynchronize();
t1 = wtime(); printf("Time GPU=%f\n", t1-t0);
/* GPU->CPU */
C_host = (float*)malloc(size_C*sizeof(float));
hipMemcpy(C_host, C_GPU, size_C*sizeof(float), hipMemcpyDeviceToHost);
check_matrix(C, C_host, hA, wB);
// print Matrix
//printf("\n\nMATRIX A\n");print_matrix(A, hA, wA);
//printf("\n\nMATRIX B\n");print_matrix(B, hB, wB);
//printf("\n\nMATRIX C\n");print_matrix(C, hA, wB);
//printf("\n\nMATRIX *C\n");print_matrix(C_host, hA, wB);
/* Free CPU */
free(A);
free(B);
free(C);
free(C_host);
/* Free GPU */
hipFree(A_GPU);
hipFree(B_GPU);
hipFree(C_GPU);
return (1);
} | .text
.file "main.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z5wtimev
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z5wtimev
.p2align 4, 0x90
.type _Z5wtimev,@function
_Z5wtimev: # @_Z5wtimev
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $_ZZ5wtimevE3tv0, %edi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, _ZZ5wtimevE3tv0(%rip), %rax # imm = 0xF4240
addq _ZZ5wtimevE3tv0+8(%rip), %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI0_0(%rip), %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z5wtimev, .Lfunc_end0-_Z5wtimev
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z11init_matrixPfiif
.LCPI1_0:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.text
.globl _Z11init_matrixPfiif
.p2align 4, 0x90
.type _Z11init_matrixPfiif,@function
_Z11init_matrixPfiif: # @_Z11init_matrixPfiif
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_8
# %bb.1: # %.preheader.lr.ph
movaps .LCPI1_0(%rip), %xmm1 # xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
xorps %xmm0, %xmm1
mulss %xmm0, %xmm0
movl %esi, %eax
movl %edx, %ecx
xorl %esi, %esi
xorl %r8d, %r8d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_7: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r8
addl %edx, %esi
cmpq %rax, %r8
je .LBB1_8
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %edx, %edx
jle .LBB1_7
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %esi, %r9d
leaq (%rdi,%r9,4), %r9
xorl %r10d, %r10d
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_6: # in Loop: Header=BB1_4 Depth=2
movss %xmm2, (%r9,%r10,4)
incq %r10
cmpq %r10, %rcx
je .LBB1_7
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movaps %xmm0, %xmm2
cmpq %r10, %r8
je .LBB1_6
# %bb.5: # in Loop: Header=BB1_4 Depth=2
movaps %xmm1, %xmm2
jmp .LBB1_6
.LBB1_8: # %._crit_edge22
retq
.Lfunc_end1:
.size _Z11init_matrixPfiif, .Lfunc_end1-_Z11init_matrixPfiif
.cfi_endproc
# -- End function
.globl _Z12print_matrixPfii # -- Begin function _Z12print_matrixPfii
.p2align 4, 0x90
.type _Z12print_matrixPfii,@function
_Z12print_matrixPfii: # @_Z12print_matrixPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB2_6
# %bb.1: # %.lr.ph15
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %r13d
xorl %ebp, %ebp
xorl %r15d, %r15d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addl %ebx, %ebp
cmpq 16(%rsp), %r15 # 8-byte Folded Reload
je .LBB2_6
.LBB2_2: # =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
movl $.L.str, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
testl %ebx, %ebx
jle .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %ebp, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r12
cmpq %r12, %r13
jne .LBB2_4
jmp .LBB2_5
.LBB2_6: # %._crit_edge16
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12print_matrixPfii, .Lfunc_end2-_Z12print_matrixPfii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z12check_matrixPfS_ii
.LCPI3_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI3_1:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.text
.globl _Z12check_matrixPfS_ii
.p2align 4, 0x90
.type _Z12check_matrixPfS_ii,@function
_Z12check_matrixPfS_ii: # @_Z12check_matrixPfS_ii
.cfi_startproc
# %bb.0:
movl $1, %eax
testl %edx, %edx
jle .LBB3_9
# %bb.1: # %.preheader.lr.ph
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edx, %r9d
movl %ecx, %r10d
xorl %r11d, %r11d
movaps .LCPI3_0(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero
xorl %r8d, %r8d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_7: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incq %r8
addl %ecx, %r11d
cmpq %r9, %r8
je .LBB3_8
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
testl %ecx, %ecx
jle .LBB3_7
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %r11d, %edx
leaq (%rsi,%rdx,4), %rbx
leaq (%rdi,%rdx,4), %r14
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%rdx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss (%rbx,%rdx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
movaps %xmm2, %xmm4
subss %xmm3, %xmm4
andps %xmm0, %xmm4
cvtss2sd %xmm4, %xmm4
ucomisd %xmm1, %xmm4
ja .LBB3_5
# %bb.6: # in Loop: Header=BB3_4 Depth=2
incq %rdx
cmpq %rdx, %r10
jne .LBB3_4
jmp .LBB3_7
.LBB3_5:
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm3, %xmm1
movl $.L.str.3, %edi
movl %r8d, %esi
# kill: def $edx killed $edx killed $rdx
movb $2, %al
callq printf
xorl %eax, %eax
.LBB3_8:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB3_9: # %.loopexit
retq
.Lfunc_end3:
.size _Z12check_matrixPfS_ii, .Lfunc_end3-_Z12check_matrixPfS_ii
.cfi_endproc
# -- End function
.globl _Z3MulPfS_iiiS_ # -- Begin function _Z3MulPfS_iiiS_
.p2align 4, 0x90
.type _Z3MulPfS_iiiS_,@function
_Z3MulPfS_iiiS_: # @_Z3MulPfS_iiiS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, -8(%rsp) # 8-byte Spill
movq %rsi, -16(%rsp) # 8-byte Spill
movq %rdi, -24(%rsp) # 8-byte Spill
testl %edx, %edx
jle .LBB4_9
# %bb.1: # %.preheader.lr.ph
movslq %r8d, %rdi
movl %edx, %edx
movl %edi, %r10d
movl %ecx, %r11d
leaq (,%rdi,4), %rbx
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_8: # %._crit_edge31
# in Loop: Header=BB4_2 Depth=1
incq %r15
addl %ecx, %r14d
cmpq %rdx, %r15
je .LBB4_9
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
# Child Loop BB4_6 Depth 3
testl %r8d, %r8d
jle .LBB4_8
# %bb.3: # %.lr.ph30
# in Loop: Header=BB4_2 Depth=1
movl %r14d, %eax
movq -24(%rsp), %rsi # 8-byte Reload
leaq (%rsi,%rax,4), %r12
movq %r15, %rax
imulq %rdi, %rax
movq -8(%rsp), %rsi # 8-byte Reload
leaq (%rsi,%rax,4), %r13
movq -16(%rsp), %rsi # 8-byte Reload
xorl %eax, %eax
jmp .LBB4_4
.p2align 4, 0x90
.LBB4_7: # %._crit_edge
# in Loop: Header=BB4_4 Depth=2
incq %rax
addq $4, %rsi
cmpq %r10, %rax
je .LBB4_8
.LBB4_4: # Parent Loop BB4_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_6 Depth 3
movl $0, (%r13,%rax,4)
testl %ecx, %ecx
jle .LBB4_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB4_4 Depth=2
movss (%r13,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rsi, %rbp
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB4_6: # Parent Loop BB4_2 Depth=1
# Parent Loop BB4_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r12,%r9,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rbp), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%r13,%rax,4)
incq %r9
addq %rbx, %rbp
cmpq %r9, %r11
jne .LBB4_6
jmp .LBB4_7
.LBB4_9: # %._crit_edge33
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z3MulPfS_iiiS_, .Lfunc_end4-_Z3MulPfS_iiiS_
.cfi_endproc
# -- End function
.globl _Z27__device_stub__mulMatrixGPUPfS_S_iii # -- Begin function _Z27__device_stub__mulMatrixGPUPfS_S_iii
.p2align 4, 0x90
.type _Z27__device_stub__mulMatrixGPUPfS_S_iii,@function
_Z27__device_stub__mulMatrixGPUPfS_S_iii: # @_Z27__device_stub__mulMatrixGPUPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12mulMatrixGPUPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end5:
.size _Z27__device_stub__mulMatrixGPUPfS_S_iii, .Lfunc_end5-_Z27__device_stub__mulMatrixGPUPfS_S_iii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI6_0:
.long 0xc0000000 # float -2
.long 0x40800000 # float 4
.LCPI6_1:
.long 0xbf800000 # float -1
.long 0x3f800000 # float 1
.LCPI6_2:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI6_4:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI6_3:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movq stdout(%rip), %rdi
xorl %esi, %esi
callq setbuf
cmpl $4, %ebp
jne .LBB6_34
# %bb.1:
movq 8(%rbx), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movl %r12d, %eax
imull %ebp, %eax
movslq %eax, %rdi
shlq $2, %rdi
movq %rdi, 96(%rsp) # 8-byte Spill
callq malloc
testl %r12d, %r12d
jle .LBB6_7
# %bb.2: # %.preheader.lr.ph.i
movl %r12d, %r9d
movl %ebp, %ecx
xorl %edx, %edx
jmp .LBB6_3
.p2align 4, 0x90
.LBB6_6: # %._crit_edge.i
# in Loop: Header=BB6_3 Depth=1
incq %rdx
addl %ebp, %r15d
cmpq %r9, %rdx
je .LBB6_7
.LBB6_3: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB6_5 Depth 2
testl %ebp, %ebp
jle .LBB6_6
# %bb.4: # %.lr.ph.i
# in Loop: Header=BB6_3 Depth=1
movl %r15d, %esi
leaq (%rax,%rsi,4), %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB6_5: # Parent Loop BB6_3 Depth=1
# => This Inner Loop Header: Depth=2
xorl %r8d, %r8d
cmpq %rdi, %rdx
sete %r8b
movss .LCPI6_0(,%r8,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rsi,%rdi,4)
incq %rdi
cmpq %rdi, %rcx
jne .LBB6_5
jmp .LBB6_6
.LBB6_7: # %_Z11init_matrixPfiif.exit
movq %rax, 16(%rsp) # 8-byte Spill
movl %ebp, %eax
imull %r14d, %eax
movslq %eax, %rdi
shlq $2, %rdi
movq %rdi, 88(%rsp) # 8-byte Spill
callq malloc
testl %ebp, %ebp
jle .LBB6_13
# %bb.8: # %.preheader.lr.ph.i58
movl %ebp, %r10d
movl %r14d, %ecx
xorl %edx, %edx
xorl %esi, %esi
jmp .LBB6_9
.p2align 4, 0x90
.LBB6_12: # %._crit_edge.i62
# in Loop: Header=BB6_9 Depth=1
incq %rsi
addl %r14d, %edx
cmpq %r10, %rsi
je .LBB6_13
.LBB6_9: # %.preheader.i60
# =>This Loop Header: Depth=1
# Child Loop BB6_11 Depth 2
testl %r14d, %r14d
jle .LBB6_12
# %bb.10: # %.lr.ph.i65
# in Loop: Header=BB6_9 Depth=1
movl %edx, %edi
leaq (%rax,%rdi,4), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB6_11: # Parent Loop BB6_9 Depth=1
# => This Inner Loop Header: Depth=2
xorl %r9d, %r9d
cmpq %r8, %rsi
sete %r9b
movss .LCPI6_1(,%r9,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rdi,%r8,4)
incq %r8
cmpq %r8, %rcx
jne .LBB6_11
jmp .LBB6_12
.LBB6_13: # %_Z11init_matrixPfiif.exit70
movq %rax, 8(%rsp) # 8-byte Spill
movl %r12d, %eax
imull %r14d, %eax
movslq %eax, %rbx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, 24(%rsp) # 8-byte Spill
xorl %r15d, %r15d
movl $_ZZ5wtimevE3tv0, %edi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, _ZZ5wtimevE3tv0(%rip), %rax # imm = 0xF4240
addq _ZZ5wtimevE3tv0+8(%rip), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI6_2(%rip), %xmm0
movsd %xmm0, 80(%rsp) # 8-byte Spill
movq %r12, 72(%rsp) # 8-byte Spill
testl %r12d, %r12d
jle .LBB6_23
# %bb.14: # %.preheader.lr.ph.i71
movslq %r14d, %rax
movl 72(%rsp), %ecx # 4-byte Reload
movl %eax, %edx
movl %ebp, %esi
movq %rax, (%rsp) # 8-byte Spill
leaq (,%rax,4), %rdi
xorl %r8d, %r8d
jmp .LBB6_15
.p2align 4, 0x90
.LBB6_22: # %._crit_edge31.i
# in Loop: Header=BB6_15 Depth=1
incq %r8
addl %ebp, %r15d
cmpq %rcx, %r8
je .LBB6_23
.LBB6_15: # %.preheader.i72
# =>This Loop Header: Depth=1
# Child Loop BB6_17 Depth 2
# Child Loop BB6_19 Depth 3
testl %r14d, %r14d
jle .LBB6_22
# %bb.16: # %.lr.ph30.i
# in Loop: Header=BB6_15 Depth=1
movl %r15d, %r9d
movq 16(%rsp), %r10 # 8-byte Reload
leaq (%r10,%r9,4), %r9
movq %r8, %r10
imulq (%rsp), %r10 # 8-byte Folded Reload
movq 24(%rsp), %r11 # 8-byte Reload
leaq (%r11,%r10,4), %r10
movq 8(%rsp), %r12 # 8-byte Reload
xorl %r13d, %r13d
jmp .LBB6_17
.p2align 4, 0x90
.LBB6_20: # %._crit_edge.i73.loopexit
# in Loop: Header=BB6_17 Depth=2
movss %xmm0, (%r10,%r13,4)
movq %rax, %rbx
.LBB6_21: # %._crit_edge.i73
# in Loop: Header=BB6_17 Depth=2
incq %r13
addq $4, %r12
cmpq %rdx, %r13
je .LBB6_22
.LBB6_17: # Parent Loop BB6_15 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_19 Depth 3
movl $0, (%r10,%r13,4)
testl %ebp, %ebp
jle .LBB6_21
# %bb.18: # %.lr.ph.i74
# in Loop: Header=BB6_17 Depth=2
movq %rbx, %rax
xorpd %xmm0, %xmm0
movq %r12, %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB6_19: # Parent Loop BB6_15 Depth=1
# Parent Loop BB6_17 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r9,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r11), %xmm1
addss %xmm1, %xmm0
incq %rbx
addq %rdi, %r11
cmpq %rbx, %rsi
jne .LBB6_19
jmp .LBB6_20
.LBB6_23: # %_Z3MulPfS_iiiS_.exit
movl $_ZZ5wtimevE3tv0, %edi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, _ZZ5wtimevE3tv0(%rip), %rax # imm = 0xF4240
addq _ZZ5wtimevE3tv0+8(%rip), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI6_2(%rip), %xmm0
subsd 80(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.5, %edi
movb $1, %al
callq printf
leaq 48(%rsp), %rdi
movq 96(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq 88(%rsp), %r12 # 8-byte Reload
movq %r12, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq 8(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq 16(%rsp), %rsi # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 72(%rsp), %r12 # 8-byte Reload
movl %r12d, %eax
movq %r14, %r15
shlq $32, %r15
movq %rax, %r13
orq %rax, %r15
movl $_ZZ5wtimevE3tv0, %edi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, _ZZ5wtimevE3tv0(%rip), %rax # imm = 0xF4240
addq _ZZ5wtimevE3tv0+8(%rip), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI6_2(%rip), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_25
# %bb.24:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %ebp, 68(%rsp)
movl %r14d, 64(%rsp)
movl %r12d, 60(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 68(%rsp), %rax
movq %rax, 200(%rsp)
leaq 64(%rsp), %rax
movq %rax, 208(%rsp)
leaq 60(%rsp), %rax
movq %rax, 216(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z12mulMatrixGPUPfS_S_iii, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_25:
callq hipDeviceSynchronize
xorl %ebp, %ebp
movl $_ZZ5wtimevE3tv0, %edi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, _ZZ5wtimevE3tv0(%rip), %rax # imm = 0xF4240
addq _ZZ5wtimevE3tv0+8(%rip), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI6_2(%rip), %xmm0
subsd (%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq malloc
movq %rax, %r15
movq 32(%rsp), %rsi
movq %rax, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testl %r12d, %r12d
jle .LBB6_33
# %bb.26: # %.preheader.lr.ph.i79
movl %r14d, %eax
movaps .LCPI6_3(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI6_4(%rip), %xmm1 # xmm1 = mem[0],zero
xorl %esi, %esi
jmp .LBB6_27
.p2align 4, 0x90
.LBB6_32: # %._crit_edge.i81
# in Loop: Header=BB6_27 Depth=1
incq %rsi
addl %r14d, %ebp
cmpq %r13, %rsi
je .LBB6_33
.LBB6_27: # %.preheader.i80
# =>This Loop Header: Depth=1
# Child Loop BB6_29 Depth 2
testl %r14d, %r14d
jle .LBB6_32
# %bb.28: # %.lr.ph.i82
# in Loop: Header=BB6_27 Depth=1
movl %ebp, %edx
leaq (%r15,%rdx,4), %rcx
movq 24(%rsp), %rdi # 8-byte Reload
leaq (%rdi,%rdx,4), %rdi
xorl %edx, %edx
.p2align 4, 0x90
.LBB6_29: # Parent Loop BB6_27 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdi,%rdx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss (%rcx,%rdx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
movaps %xmm2, %xmm4
subss %xmm3, %xmm4
andps %xmm0, %xmm4
cvtss2sd %xmm4, %xmm4
ucomisd %xmm1, %xmm4
ja .LBB6_30
# %bb.31: # in Loop: Header=BB6_29 Depth=2
incq %rdx
cmpq %rdx, %rax
jne .LBB6_29
jmp .LBB6_32
.LBB6_30:
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm3, %xmm1
movl $.L.str.3, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
movb $2, %al
callq printf
.LBB6_33: # %_Z12check_matrixPfS_ii.exit
movq 16(%rsp), %rdi # 8-byte Reload
callq free
movq 8(%rsp), %rdi # 8-byte Reload
callq free
movq 24(%rsp), %rdi # 8-byte Reload
callq free
movq %r15, %rdi
callq free
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movl $1, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_34:
.cfi_def_cfa_offset 288
movl $.Lstr, %edi
callq puts@PLT
movl $-1, %edi
callq exit
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12mulMatrixGPUPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZZ5wtimevE3tv0,@object # @_ZZ5wtimevE3tv0
.local _ZZ5wtimevE3tv0
.comm _ZZ5wtimevE3tv0,16,8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Line %i: "
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%4.1f "
.size .L.str.1, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "device!=host %f!=%f in (%i,%i)\n"
.size .L.str.3, 32
.type _Z12mulMatrixGPUPfS_S_iii,@object # @_Z12mulMatrixGPUPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z12mulMatrixGPUPfS_S_iii
.p2align 3, 0x0
_Z12mulMatrixGPUPfS_S_iii:
.quad _Z27__device_stub__mulMatrixGPUPfS_S_iii
.size _Z12mulMatrixGPUPfS_S_iii, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "Time CPU=%f\n"
.size .L.str.5, 13
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Time GPU=%f\n"
.size .L.str.6, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12mulMatrixGPUPfS_S_iii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "./exec hA hB/WA wB"
.size .Lstr, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__mulMatrixGPUPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZZ5wtimevE3tv0
.addrsig_sym _Z12mulMatrixGPUPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12mulMatrixGPUPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x17c], P0 ; /* 0x00005f0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R22, -RZ, RZ, 0, 0 ; /* 0x00000000ff167435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0x1000 ; /* 0x00000f1000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R22, RZ ; /* 0x000000ff00167202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xeb0 ; /* 0x00000d6000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, -R2, c[0x0][0x178], RZ ; /* 0x00005e0002057a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R16, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff107435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ HFMA2.MMA R22, -RZ, RZ, 0, 0 ; /* 0x00000000ff167435 */
/* 0x000fe200000001ff */
/*0190*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD R6, R0, c[0x0][0x178], RZ ; /* 0x00005e0000067a24 */
/* 0x000fe200078e02ff */
/*01b0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R16, R3, R16, c[0x0][0x168] ; /* 0x00005a0003107625 */
/* 0x000fcc00078e0210 */
/*01d0*/ @!P0 BRA 0xc90 ; /* 0x00000ab000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x8c0 ; /* 0x000006b000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R14, UR6 ; /* 0x00000006000e7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R23, [R16.64] ; /* 0x0000000410177981 */
/* 0x0010a2000c1e1900 */
/*0240*/ MOV R15, UR7 ; /* 0x00000007000f7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R14, R6, 0x4, R14 ; /* 0x00000004060e7825 */
/* 0x000fca00078e020e */
/*0260*/ LDG.E R28, [R14.64] ; /* 0x000000040e1c7981 */
/* 0x000ea2000c1e1900 */
/*0270*/ MOV R7, c[0x0][0x17c] ; /* 0x00005f0000077a02 */
/* 0x000fc60000000f00 */
/*0280*/ LDG.E R9, [R14.64+0x4] ; /* 0x000004040e097981 */
/* 0x000ee4000c1e1900 */
/*0290*/ IMAD.WIDE R26, R7.reuse, 0x4, R16 ; /* 0x00000004071a7825 */
/* 0x040fe400078e0210 */
/*02a0*/ LDG.E R11, [R14.64+0x8] ; /* 0x000008040e0b7981 */
/* 0x000f28000c1e1900 */
/*02b0*/ LDG.E R8, [R26.64] ; /* 0x000000041a087981 */
/* 0x0022e2000c1e1900 */
/*02c0*/ IMAD.WIDE R20, R7, 0x4, R26 ; /* 0x0000000407147825 */
/* 0x000fc600078e021a */
/*02d0*/ LDG.E R12, [R14.64+0xc] ; /* 0x00000c040e0c7981 */
/* 0x000f68000c1e1900 */
/*02e0*/ LDG.E R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000322000c1e1900 */
/*02f0*/ IMAD.WIDE R18, R7, 0x4, R20 ; /* 0x0000000407127825 */
/* 0x000fc600078e0214 */
/*0300*/ LDG.E R24, [R14.64+0x10] ; /* 0x000010040e187981 */
/* 0x000ee8000c1e1900 */
/*0310*/ LDG.E R13, [R18.64] ; /* 0x00000004120d7981 */
/* 0x000362000c1e1900 */
/*0320*/ IMAD.WIDE R16, R7, 0x4, R18 ; /* 0x0000000407107825 */
/* 0x001fc600078e0212 */
/*0330*/ LDG.E R27, [R14.64+0x14] ; /* 0x000014040e1b7981 */
/* 0x002ee8000c1e1900 */
/*0340*/ LDG.E R25, [R16.64] ; /* 0x0000000410197981 */
/* 0x0000e2000c1e1900 */
/*0350*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fca00078e0210 */
/*0360*/ LDG.E R26, [R18.64] ; /* 0x00000004121a7981 */
/* 0x000522000c1e1900 */
/*0370*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*0380*/ LDG.E R16, [R14.64+0x18] ; /* 0x000018040e107981 */
/* 0x001f28000c1e1900 */
/*0390*/ LDG.E R29, [R20.64] ; /* 0x00000004141d7981 */
/* 0x000128000c1e1900 */
/*03a0*/ LDG.E R17, [R14.64+0x1c] ; /* 0x00001c040e117981 */
/* 0x000f22000c1e1900 */
/*03b0*/ FFMA R18, R23, R28, R22 ; /* 0x0000001c17127223 */
/* 0x004fe40000000016 */
/*03c0*/ IMAD.WIDE R22, R7, 0x4, R20 ; /* 0x0000000407167825 */
/* 0x000fca00078e0214 */
/*03d0*/ LDG.E R28, [R22.64] ; /* 0x00000004161c7981 */
/* 0x0002a2000c1e1900 */
/*03e0*/ F2I.TRUNC.NTZ R21, R18 ; /* 0x0000001200157305 */
/* 0x001066000020f100 */
/*03f0*/ LDG.E R18, [R14.64+0x20] ; /* 0x000020040e127981 */
/* 0x001eaa000c1e1900 */
/*0400*/ I2F R21, R21 ; /* 0x0000001500157306 */
/* 0x002ee40000201400 */
/*0410*/ FFMA R19, R8, R9, R21 ; /* 0x0000000908137223 */
/* 0x008fc40000000015 */
/*0420*/ IMAD.WIDE R8, R7, 0x4, R22 ; /* 0x0000000407087825 */
/* 0x000fc800078e0216 */
/*0430*/ F2I.TRUNC.NTZ R22, R19 ; /* 0x0000001300167305 */
/* 0x000064000020f100 */
/*0440*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x0010ec000c1e1900 */
/*0450*/ I2F R20, R22 ; /* 0x0000001600147306 */
/* 0x002f240000201400 */
/*0460*/ FFMA R20, R10, R11, R20 ; /* 0x0000000b0a147223 */
/* 0x010fc40000000014 */
/*0470*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fc800078e0208 */
/*0480*/ F2I.TRUNC.NTZ R23, R20 ; /* 0x0000001400177305 */
/* 0x000322000020f100 */
/*0490*/ LDG.E R21, [R10.64] ; /* 0x000000040a157981 */
/* 0x0000e8000c1e1900 */
/*04a0*/ LDG.E R20, [R14.64+0x24] ; /* 0x000024040e147981 */
/* 0x002ee6000c1e1900 */
/*04b0*/ I2F R23, R23 ; /* 0x0000001700177306 */
/* 0x010f640000201400 */
/*04c0*/ FFMA R23, R13, R12, R23 ; /* 0x0000000c0d177223 */
/* 0x020fc40000000017 */
/*04d0*/ IMAD.WIDE R12, R7, 0x4, R10 ; /* 0x00000004070c7825 */
/* 0x000fc800078e020a */
/*04e0*/ F2I.TRUNC.NTZ R8, R23 ; /* 0x0000001700087305 */
/* 0x001062000020f100 */
/*04f0*/ LDG.E R22, [R12.64] ; /* 0x000000040c167981 */
/* 0x000968000c1e1900 */
/*0500*/ LDG.E R23, [R14.64+0x28] ; /* 0x000028040e177981 */
/* 0x001f66000c1e1900 */
/*0510*/ I2F R8, R8 ; /* 0x0000000800087306 */
/* 0x002e240000201400 */
/*0520*/ FFMA R24, R25, R24, R8 ; /* 0x0000001819187223 */
/* 0x001fc40000000008 */
/*0530*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fe200078e020c */
/*0540*/ LDG.E R25, [R14.64+0x2c] ; /* 0x00002c040e197981 */
/* 0x000166000c1e1900 */
/*0550*/ F2I.TRUNC.NTZ R11, R24 ; /* 0x00000018000b7305 */
/* 0x000224000020f100 */
/*0560*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x00236c000c1e1900 */
/*0570*/ I2F R11, R11 ; /* 0x0000000b000b7306 */
/* 0x001e240000201400 */
/*0580*/ FFMA R26, R26, R27, R11 ; /* 0x0000001b1a1a7223 */
/* 0x001fc4000000000b */
/*0590*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*05a0*/ LDG.E R27, [R14.64+0x30] ; /* 0x000030040e1b7981 */
/* 0x000166000c1e1900 */
/*05b0*/ F2I.TRUNC.NTZ R9, R26 ; /* 0x0000001a00097305 */
/* 0x002324000020f100 */
/*05c0*/ LDG.E R26, [R10.64] ; /* 0x000000040a1a7981 */
/* 0x00236c000c1e1900 */
/*05d0*/ I2F R12, R9 ; /* 0x00000009000c7306 */
/* 0x010f240000201400 */
/*05e0*/ FFMA R29, R29, R16, R12 ; /* 0x000000101d1d7223 */
/* 0x010fc4000000000c */
/*05f0*/ IMAD.WIDE R12, R7, 0x4, R10 ; /* 0x00000004070c7825 */
/* 0x000fc800078e020a */
/*0600*/ F2I.TRUNC.NTZ R8, R29 ; /* 0x0000001d00087305 */
/* 0x000822000020f100 */
/*0610*/ LDG.E R10, [R14.64+0x34] ; /* 0x000034040e0a7981 */
/* 0x002368000c1e1900 */
/*0620*/ LDG.E R29, [R12.64] ; /* 0x000000040c1d7981 */
/* 0x010966000c1e1900 */
/*0630*/ I2F R8, R8 ; /* 0x0000000800087306 */
/* 0x001ea40000201400 */
/*0640*/ FFMA R28, R28, R17, R8 ; /* 0x000000111c1c7223 */
/* 0x004fc40000000008 */
/*0650*/ IMAD.WIDE R16, R7.reuse, 0x4, R12 ; /* 0x0000000407107825 */
/* 0x040fe400078e020c */
/*0660*/ LDG.E R12, [R14.64+0x38] ; /* 0x000038040e0c7981 */
/* 0x0102a8000c1e1900 */
/*0670*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x0000a2000c1e1900 */
/*0680*/ IMAD.WIDE R8, R7, 0x4, R16 ; /* 0x0000000407087825 */
/* 0x000fe200078e0210 */
/*0690*/ F2I.TRUNC.NTZ R28, R28 ; /* 0x0000001c001c7305 */
/* 0x000f28000020f100 */
/*06a0*/ LDG.E R13, [R8.64] ; /* 0x00000004080d7981 */
/* 0x000ea8000c1e1900 */
/*06b0*/ LDG.E R16, [R14.64+0x3c] ; /* 0x00003c040e107981 */
/* 0x0012a2000c1e1900 */
/*06c0*/ I2F R28, R28 ; /* 0x0000001c001c7306 */
/* 0x010ee40000201400 */
/*06d0*/ FFMA R18, R19, R18, R28 ; /* 0x0000001213127223 */
/* 0x008fcc000000001c */
/*06e0*/ F2I.TRUNC.NTZ R18, R18 ; /* 0x0000001200127305 */
/* 0x000e30000020f100 */
/*06f0*/ I2F R19, R18 ; /* 0x0000001200137306 */
/* 0x001e240000201400 */
/*0700*/ FFMA R19, R21, R20, R19 ; /* 0x0000001415137223 */
/* 0x001fcc0000000013 */
/*0710*/ F2I.TRUNC.NTZ R19, R19 ; /* 0x0000001300137305 */
/* 0x000e30000020f100 */
/*0720*/ I2F R17, R19 ; /* 0x0000001300117306 */
/* 0x001f640000201400 */
/*0730*/ FFMA R17, R22, R23, R17 ; /* 0x0000001716117223 */
/* 0x020fcc0000000011 */
/*0740*/ F2I.TRUNC.NTZ R17, R17 ; /* 0x0000001100117305 */
/* 0x000e70000020f100 */
/*0750*/ I2F R14, R17 ; /* 0x00000011000e7306 */
/* 0x002e240000201400 */
/*0760*/ FFMA R14, R24, R25, R14 ; /* 0x00000019180e7223 */
/* 0x001fcc000000000e */
/*0770*/ F2I.TRUNC.NTZ R14, R14 ; /* 0x0000000e000e7305 */
/* 0x000e30000020f100 */
/*0780*/ I2F R15, R14 ; /* 0x0000000e000f7306 */
/* 0x001e240000201400 */
/*0790*/ FFMA R15, R26, R27, R15 ; /* 0x0000001b1a0f7223 */
/* 0x001fcc000000000f */
/*07a0*/ F2I.TRUNC.NTZ R15, R15 ; /* 0x0000000f000f7305 */
/* 0x000e30000020f100 */
/*07b0*/ I2F R18, R15 ; /* 0x0000000f00127306 */
/* 0x001e240000201400 */
/*07c0*/ FFMA R10, R29, R10, R18 ; /* 0x0000000a1d0a7223 */
/* 0x001fcc0000000012 */
/*07d0*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000e30000020f100 */
/*07e0*/ I2F R18, R10 ; /* 0x0000000a00127306 */
/* 0x001ea40000201400 */
/*07f0*/ FFMA R11, R11, R12, R18 ; /* 0x0000000c0b0b7223 */
/* 0x004fcc0000000012 */
/*0800*/ F2I.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b7305 */
/* 0x000e30000020f100 */
/*0810*/ I2F R12, R11 ; /* 0x0000000b000c7306 */
/* 0x001e220000201400 */
/*0820*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fe20007ffe0ff */
/*0830*/ FFMA R12, R13, R16, R12 ; /* 0x000000100d0c7223 */
/* 0x001fcc000000000c */
/*0840*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x000e22000020f100 */
/*0850*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe20003f24270 */
/*0860*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0870*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc600078e0208 */
/*0880*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*0890*/ I2F R22, R12 ; /* 0x0000000c00167306 */
/* 0x0010620000201400 */
/*08a0*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fca0007ffe0ff */
/*08b0*/ @P1 BRA 0x220 ; /* 0xfffff96000001947 */
/* 0x000fea000383ffff */
/*08c0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*08d0*/ @!P1 BRA 0xc70 ; /* 0x0000039000009947 */
/* 0x000fea0003800000 */
/*08e0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*08f0*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x0004e2000c1e1900 */
/*0900*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fca0008000f00 */
/*0910*/ IMAD.WIDE R8, R6, 0x4, R8 ; /* 0x0000000406087825 */
/* 0x000fca00078e0208 */
/*0920*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x000ee2000c1e1900 */
/*0930*/ MOV R7, c[0x0][0x17c] ; /* 0x00005f0000077a02 */
/* 0x000fc60000000f00 */
/*0940*/ LDG.E R23, [R8.64+0x4] ; /* 0x0000040408177981 */
/* 0x000f24000c1e1900 */
/*0950*/ IMAD.WIDE R18, R7.reuse, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x040fe400078e0210 */
/*0960*/ LDG.E R24, [R8.64+0x8] ; /* 0x0000080408187981 */
/* 0x000f68000c1e1900 */
/*0970*/ LDG.E R26, [R18.64] ; /* 0x00000004121a7981 */
/* 0x000122000c1e1900 */
/*0980*/ IMAD.WIDE R10, R7, 0x4, R18 ; /* 0x00000004070a7825 */
/* 0x000fc600078e0212 */
/*0990*/ LDG.E R28, [R8.64+0xc] ; /* 0x00000c04081c7981 */
/* 0x000f28000c1e1900 */
/*09a0*/ LDG.E R25, [R10.64] ; /* 0x000000040a197981 */
/* 0x000362000c1e1900 */
/*09b0*/ IMAD.WIDE R12, R7, 0x4, R10 ; /* 0x00000004070c7825 */
/* 0x001fca00078e020a */
/*09c0*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000122000c1e1900 */
/*09d0*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fca00078e020c */
/*09e0*/ LDG.E R29, [R14.64] ; /* 0x000000040e1d7981 */
/* 0x000328000c1e1900 */
/*09f0*/ LDG.E R12, [R8.64+0x10] ; /* 0x00001004080c7981 */
/* 0x001122000c1e1900 */
/*0a00*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x004fc600078e020e */
/*0a10*/ LDG.E R14, [R8.64+0x14] ; /* 0x00001404080e7981 */
/* 0x0020a8000c1e1900 */
/*0a20*/ LDG.E R13, [R16.64] ; /* 0x00000004100d7981 */
/* 0x0002a2000c1e1900 */
/*0a30*/ IMAD.WIDE R10, R7, 0x4, R16 ; /* 0x00000004070a7825 */
/* 0x000fca00078e0210 */
/*0a40*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0000a8000c1e1900 */
/*0a50*/ LDG.E R16, [R8.64+0x18] ; /* 0x0000180408107981 */
/* 0x0022a2000c1e1900 */
/*0a60*/ IMAD.WIDE R18, R7, 0x4, R10 ; /* 0x0000000407127825 */
/* 0x000fc600078e020a */
/*0a70*/ LDG.E R11, [R8.64+0x1c] ; /* 0x00001c04080b7981 */
/* 0x0012a8000c1e1900 */
/*0a80*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x000ea2000c1e1900 */
/*0a90*/ FFMA R20, R20, R21, R22 ; /* 0x0000001514147223 */
/* 0x008fcc0000000016 */
/*0aa0*/ F2I.TRUNC.NTZ R20, R20 ; /* 0x0000001400147305 */
/* 0x000e30000020f100 */
/*0ab0*/ I2F R21, R20 ; /* 0x0000001400157306 */
/* 0x001f240000201400 */
/*0ac0*/ FFMA R21, R26, R23, R21 ; /* 0x000000171a157223 */
/* 0x010fcc0000000015 */
/*0ad0*/ F2I.TRUNC.NTZ R21, R21 ; /* 0x0000001500157305 */
/* 0x000e30000020f100 */
/*0ae0*/ I2F R17, R21 ; /* 0x0000001500117306 */
/* 0x001f640000201400 */
/*0af0*/ FFMA R17, R25, R24, R17 ; /* 0x0000001819117223 */
/* 0x020fcc0000000011 */
/*0b00*/ F2I.TRUNC.NTZ R17, R17 ; /* 0x0000001100117305 */
/* 0x000e30000020f100 */
/*0b10*/ I2F R22, R17 ; /* 0x0000001100167306 */
/* 0x001e240000201400 */
/*0b20*/ FFMA R22, R27, R28, R22 ; /* 0x0000001c1b167223 */
/* 0x001fcc0000000016 */
/*0b30*/ F2I.TRUNC.NTZ R22, R22 ; /* 0x0000001600167305 */
/* 0x000e70000020f100 */
/*0b40*/ I2F R8, R22 ; /* 0x0000001600087306 */
/* 0x002e240000201400 */
/*0b50*/ FFMA R8, R29, R12, R8 ; /* 0x0000000c1d087223 */
/* 0x001fcc0000000008 */
/*0b60*/ F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000e30000020f100 */
/*0b70*/ I2F R9, R8 ; /* 0x0000000800097306 */
/* 0x001ea40000201400 */
/*0b80*/ FFMA R9, R13, R14, R9 ; /* 0x0000000e0d097223 */
/* 0x004fcc0000000009 */
/*0b90*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e30000020f100 */
/*0ba0*/ I2F R12, R9 ; /* 0x00000009000c7306 */
/* 0x001e240000201400 */
/*0bb0*/ FFMA R12, R15, R16, R12 ; /* 0x000000100f0c7223 */
/* 0x001fcc000000000c */
/*0bc0*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x000e30000020f100 */
/*0bd0*/ I2F R13, R12 ; /* 0x0000000c000d7306 */
/* 0x001e240000201400 */
/*0be0*/ FFMA R10, R10, R11, R13 ; /* 0x0000000b0a0a7223 */
/* 0x001fcc000000000d */
/*0bf0*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000e22000020f100 */
/*0c00*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0c10*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0c20*/ IMAD.WIDE R16, R7, 0x4, R18 ; /* 0x0000000407107825 */
/* 0x000fe200078e0212 */
/*0c30*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fc80007ffe0ff */
/*0c40*/ I2F R22, R10 ; /* 0x0000000a00167306 */
/* 0x0010620000201400 */
/*0c50*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*0c60*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fcc00087fe43f */
/*0c70*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0c80*/ @!P0 BRA 0xeb0 ; /* 0x0000022000008947 */
/* 0x000fea0003800000 */
/*0c90*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0ca0*/ LDG.E R19, [R16.64] ; /* 0x0000000410137981 */
/* 0x0004e2000c1e1900 */
/*0cb0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fca0008000f00 */
/*0cc0*/ IMAD.WIDE R8, R6, 0x4, R8 ; /* 0x0000000406087825 */
/* 0x000fca00078e0208 */
/*0cd0*/ LDG.E R18, [R8.64] ; /* 0x0000000408127981 */
/* 0x000ee2000c1e1900 */
/*0ce0*/ MOV R7, c[0x0][0x17c] ; /* 0x00005f0000077a02 */
/* 0x000fc60000000f00 */
/*0cf0*/ LDG.E R20, [R8.64+0x4] ; /* 0x0000040408147981 */
/* 0x000f24000c1e1900 */
/*0d00*/ IMAD.WIDE R14, R7.reuse, 0x4, R16 ; /* 0x00000004070e7825 */
/* 0x040fe400078e0210 */
/*0d10*/ LDG.E R24, [R8.64+0x8] ; /* 0x0000080408187981 */
/* 0x000f68000c1e1900 */
/*0d20*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x000f22000c1e1900 */
/*0d30*/ IMAD.WIDE R12, R7, 0x4, R14 ; /* 0x00000004070c7825 */
/* 0x001fc600078e020e */
/*0d40*/ LDG.E R25, [R8.64+0xc] ; /* 0x00000c0408197981 */
/* 0x000f28000c1e1900 */
/*0d50*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000f62000c1e1900 */
/*0d60*/ IMAD.WIDE R10, R7, 0x4, R12 ; /* 0x00000004070a7825 */
/* 0x000fca00078e020c */
/*0d70*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x004ea2000c1e1900 */
/*0d80*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0d90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0da0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0db0*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0dc0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0dd0*/ FFMA R18, R19, R18, R22 ; /* 0x0000001213127223 */
/* 0x00afcc0000000016 */
/*0de0*/ F2I.TRUNC.NTZ R18, R18 ; /* 0x0000001200127305 */
/* 0x000e30000020f100 */
/*0df0*/ I2F R16, R18 ; /* 0x0000001200107306 */
/* 0x001f240000201400 */
/*0e00*/ FFMA R16, R21, R20, R16 ; /* 0x0000001415107223 */
/* 0x010fcc0000000010 */
/*0e10*/ F2I.TRUNC.NTZ R16, R16 ; /* 0x0000001000107305 */
/* 0x000e30000020f100 */
/*0e20*/ I2F R14, R16 ; /* 0x00000010000e7306 */
/* 0x001f640000201400 */
/*0e30*/ FFMA R14, R23, R24, R14 ; /* 0x00000018170e7223 */
/* 0x020fcc000000000e */
/*0e40*/ F2I.TRUNC.NTZ R14, R14 ; /* 0x0000000e000e7305 */
/* 0x000e30000020f100 */
/*0e50*/ I2F R12, R14 ; /* 0x0000000e000c7306 */
/* 0x001ea40000201400 */
/*0e60*/ FFMA R12, R17, R25, R12 ; /* 0x00000019110c7223 */
/* 0x004fcc000000000c */
/*0e70*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x000e22000020f100 */
/*0e80*/ IMAD.WIDE R16, R7, 0x4, R10 ; /* 0x0000000407107825 */
/* 0x000fce00078e020a */
/*0e90*/ I2F R22, R12 ; /* 0x0000000c00167306 */
/* 0x0010640000201400 */
/*0ea0*/ @P0 BRA 0xc90 ; /* 0xfffffde000000947 */
/* 0x003fea000383ffff */
/*0eb0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0ec0*/ @!P0 BRA 0x1000 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0ed0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0ee0*/ IMAD R5, R0, c[0x0][0x178], R4 ; /* 0x00005e0000057a24 */
/* 0x000fe400078e0204 */
/*0ef0*/ IMAD R6, R4, c[0x0][0x17c], R3 ; /* 0x00005f0004067a24 */
/* 0x000fce00078e0203 */
/*0f00*/ IMAD.WIDE R4, R5, R7, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fc800078e0207 */
/*0f10*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe200078e0207 */
/*0f20*/ MOV R8, R4 ; /* 0x0000000400087202 */
/* 0x000fc80000000f00 */
/*0f30*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x000fe20000000f00 */
/*0f40*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x0064ea000c1e1900 */
/*0f50*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0008e2000c1e1900 */
/*0f60*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0f70*/ MOV R11, c[0x0][0x17c] ; /* 0x00005f00000b7a02 */
/* 0x000fc40000000f00 */
/*0f80*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f05270 */
/*0f90*/ IADD3 R8, P1, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe20007f3e0ff */
/*0fa0*/ IMAD.WIDE R6, R11, 0x4, R6 ; /* 0x000000040b067825 */
/* 0x004fc600078e0206 */
/*0fb0*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x010fe20000ffe4ff */
/*0fc0*/ FFMA R9, R9, R4, R22 ; /* 0x0000000409097223 */
/* 0x00afcc0000000016 */
/*0fd0*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e70000020f100 */
/*0fe0*/ I2F R22, R9 ; /* 0x0000000900167306 */
/* 0x0022a20000201400 */
/*0ff0*/ @P0 BRA 0xf30 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*1000*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*1010*/ IMAD R3, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000037a24 */
/* 0x000fc800078e0203 */
/*1020*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*1030*/ STG.E [R2.64], R22 ; /* 0x0000001602007986 */
/* 0x006fe2000c101904 */
/*1040*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1050*/ BRA 0x1050; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12mulMatrixGPUPfS_S_iii
.globl _Z12mulMatrixGPUPfS_S_iii
.p2align 8
.type _Z12mulMatrixGPUPfS_S_iii,@function
_Z12mulMatrixGPUPfS_S_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x1c
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s9, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_7
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cvt_f32_i32_e32 v6, v6
s_add_i32 s2, s2, -1
s_cmp_lg_u32 s2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s8, v4
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v6, v6
s_cbranch_scc1 .LBB0_3
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_i32_e32 v2, v6
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v2, 0
.LBB0_6:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v1, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12mulMatrixGPUPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12mulMatrixGPUPfS_S_iii, .Lfunc_end0-_Z12mulMatrixGPUPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12mulMatrixGPUPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12mulMatrixGPUPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c416d_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5wtimev
.type _Z5wtimev, @function
_Z5wtimev:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $0, %esi
leaq _ZZ5wtimevE3tv0(%rip), %rdi
call gettimeofday@PLT
imulq $1000000, _ZZ5wtimevE3tv0(%rip), %rax
addq 8+_ZZ5wtimevE3tv0(%rip), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z5wtimev, .-_Z5wtimev
.globl _Z11init_matrixPfiif
.type _Z11init_matrixPfiif, @function
_Z11init_matrixPfiif:
.LFB2058:
.cfi_startproc
endbr64
movq %rdi, %r9
testl %esi, %esi
jle .L5
movl $0, %r8d
movl $0, %edi
movaps %xmm0, %xmm1
xorps .LC1(%rip), %xmm1
jmp .L7
.L15:
leal (%rax,%r8), %ecx
movslq %ecx, %rcx
movaps %xmm0, %xmm2
mulss %xmm0, %xmm2
movss %xmm2, (%r9,%rcx,4)
.L9:
addl $1, %eax
cmpl %eax, %edx
je .L11
.L10:
cmpl %eax, %edi
je .L15
leal (%rax,%r8), %ecx
movslq %ecx, %rcx
movss %xmm1, (%r9,%rcx,4)
jmp .L9
.L11:
addl $1, %edi
addl %edx, %r8d
cmpl %edi, %esi
je .L5
.L7:
movl $0, %eax
testl %edx, %edx
jg .L10
jmp .L11
.L5:
ret
.cfi_endproc
.LFE2058:
.size _Z11init_matrixPfiif, .-_Z11init_matrixPfiif
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Line %i: "
.LC3:
.string "%4.1f "
.LC4:
.string "\n"
.text
.globl _Z12print_matrixPfii
.type _Z12print_matrixPfii, @function
_Z12print_matrixPfii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L16
movl %edx, %r15d
movl $0, %r14d
movl $0, %r13d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq .LC3(%rip), %r12
.L20:
movl %r13d, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %r15d, %r15d
jle .L18
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L19:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L19
.L18:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
jne .L20
.L16:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z12print_matrixPfii, .-_Z12print_matrixPfii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "device!=host %f!=%f in (%i,%i)\n"
.text
.globl _Z12check_matrixPfS_ii
.type _Z12check_matrixPfS_ii, @function
_Z12check_matrixPfS_ii:
.LFB2060:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L32
movq %rsi, %r9
movl %edx, %r10d
movl %ecx, %esi
movl $0, %r11d
movl $0, %r8d
movslq %ecx, %rdx
movss .LC5(%rip), %xmm4
movsd .LC6(%rip), %xmm3
.L38:
testl %esi, %esi
jle .L44
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
jmp .L30
.L45:
cvtss2sd %xmm0, %xmm0
movl %r8d, %edx
cvtss2sd %xmm1, %xmm1
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl $0, %eax
.L24:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
testl %esi, %esi
jle .L31
.L30:
movslq %r11d, %rax
salq $2, %rax
leaq (%rdi,%rax), %rbx
addq %r9, %rax
movl $0, %ecx
.L29:
movss (%rbx,%rcx,4), %xmm0
movss (%rax,%rcx,4), %xmm1
movaps %xmm0, %xmm2
subss %xmm1, %xmm2
andps %xmm4, %xmm2
cvtss2sd %xmm2, %xmm2
comisd %xmm3, %xmm2
ja .L45
addq $1, %rcx
cmpq %rdx, %rcx
jne .L29
.L31:
addl $1, %r8d
addl %esi, %r11d
cmpl %r8d, %r10d
jne .L46
movl $1, %eax
jmp .L24
.L32:
.cfi_def_cfa_offset 8
.cfi_restore 3
movl $1, %eax
ret
.L44:
addl $1, %r8d
addl %esi, %r11d
cmpl %r8d, %r10d
jne .L38
movl $1, %eax
ret
.cfi_endproc
.LFE2060:
.size _Z12check_matrixPfS_ii, .-_Z12check_matrixPfS_ii
.globl _Z3MulPfS_iiiS_
.type _Z3MulPfS_iiiS_, @function
_Z3MulPfS_iiiS_:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rsi, -8(%rsp)
movl %edx, -12(%rsp)
testl %edx, %edx
jle .L47
movq %rdi, %rbx
movl %ecx, %ebp
movl %r8d, %r11d
movslq %r8d, %rdi
salq $2, %rdi
movl $0, %r13d
movl $0, %ecx
movl $0, %edx
movslq %ebp, %r14
movq %r9, %r8
movq %r14, %rsi
jmp .L49
.L53:
movslq %ecx, %rax
leaq (%r8,%rax,4), %r10
movq -8(%rsp), %r14
movslq %r13d, %rax
leaq (%rbx,%rax,4), %r15
addq %rsi, %rax
leaq (%rbx,%rax,4), %r9
movl $0, %r12d
movl %edx, -20(%rsp)
movl %ecx, -16(%rsp)
.L52:
movq %r10, %rcx
movl $0x00000000, (%r10)
testl %ebp, %ebp
jle .L50
movq %r14, %rdx
movq %r15, %rax
.L51:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss (%rcx), %xmm0
movss %xmm0, (%rcx)
addq $4, %rax
addq %rdi, %rdx
cmpq %r9, %rax
jne .L51
.L50:
addl $1, %r12d
addq $4, %r10
addq $4, %r14
cmpl %r12d, %r11d
jne .L52
movl -20(%rsp), %edx
movl -16(%rsp), %ecx
.L54:
addl $1, %edx
addl %r11d, %ecx
addl %ebp, %r13d
cmpl %edx, -12(%rsp)
je .L47
.L49:
testl %r11d, %r11d
jg .L53
jmp .L54
.L47:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z3MulPfS_iiiS_, .-_Z3MulPfS_iiiS_
.globl _Z39__device_stub__Z12mulMatrixGPUPfS_S_iiiPfS_S_iii
.type _Z39__device_stub__Z12mulMatrixGPUPfS_S_iiiPfS_S_iii, @function
_Z39__device_stub__Z12mulMatrixGPUPfS_S_iiiPfS_S_iii:
.LFB2087:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L62
.L58:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L63
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L62:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12mulMatrixGPUPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L58
.L63:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z39__device_stub__Z12mulMatrixGPUPfS_S_iiiPfS_S_iii, .-_Z39__device_stub__Z12mulMatrixGPUPfS_S_iiiPfS_S_iii
.globl _Z12mulMatrixGPUPfS_S_iii
.type _Z12mulMatrixGPUPfS_S_iii, @function
_Z12mulMatrixGPUPfS_S_iii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z12mulMatrixGPUPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z12mulMatrixGPUPfS_S_iii, .-_Z12mulMatrixGPUPfS_S_iii
.section .rodata.str1.1
.LC9:
.string "./exec hA hB/WA wB\n"
.LC12:
.string "Time CPU=%f\n"
.LC13:
.string "Time GPU=%f\n"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movl %edi, %ebx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $0, %esi
movq stdout(%rip), %rdi
call setbuf@PLT
cmpl $4, %ebx
jne .L71
movq 8(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movl %eax, 32(%rsp)
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, 12(%rsp)
movq 24(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, 36(%rsp)
movl %r14d, %r13d
imull %ebx, %r13d
movslq %r13d, %r13
salq $2, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r15
movss .LC10(%rip), %xmm0
movl 12(%rsp), %ebp
movl %ebp, %edx
movl 32(%rsp), %esi
movq %rax, %rdi
call _Z11init_matrixPfiif
imull %r12d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movss .LC11(%rip), %xmm0
movl 36(%rsp), %edx
movl %ebp, 12(%rsp)
movl %ebp, %esi
movq %rax, 16(%rsp)
movq %rax, %rdi
call _Z11init_matrixPfiif
movl %r14d, %ebp
imull %r12d, %ebp
movslq %ebp, %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
call _Z5wtimev
movsd %xmm0, 40(%rsp)
movq 24(%rsp), %r9
movl %r12d, %r8d
movl 12(%rsp), %ecx
movl 32(%rsp), %edx
movq 16(%rsp), %rsi
movq %r15, %rdi
call _Z3MulPfS_iiiS_
call _Z5wtimev
subsd 40(%rsp), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 56(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r15, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 80(%rsp)
movl $16, 84(%rsp)
movl $1, 88(%rsp)
movl %r14d, 92(%rsp)
movl %r12d, 96(%rsp)
movl $1, 100(%rsp)
call _Z5wtimev
movsd %xmm0, 40(%rsp)
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L72
.L68:
call cudaThreadSynchronize@PLT
call _Z5wtimev
subsd 40(%rsp), %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movq %rbp, %rdx
movq 72(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movl 36(%rsp), %ecx
movl 32(%rsp), %edx
movq %rbx, %rsi
movq 24(%rsp), %r14
movq %r14, %rdi
call _Z12check_matrixPfS_ii
movq %r15, %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L73
movl $1, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L71:
.cfi_restore_state
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L72:
movl %r14d, %r9d
movl %r12d, %r8d
movl 12(%rsp), %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z39__device_stub__Z12mulMatrixGPUPfS_S_iiiPfS_S_iii
jmp .L68
.L73:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z12mulMatrixGPUPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z12mulMatrixGPUPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZ5wtimevE3tv0
.comm _ZZ5wtimevE3tv0,16,16
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC1:
.long -2147483648
.long 0
.long 0
.long 0
.align 16
.LC5:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC6:
.long -1998362383
.long 1055193269
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC10:
.long 1073741824
.align 4
.LC11:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z5wtimev
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z5wtimev
.p2align 4, 0x90
.type _Z5wtimev,@function
_Z5wtimev: # @_Z5wtimev
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $_ZZ5wtimevE3tv0, %edi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, _ZZ5wtimevE3tv0(%rip), %rax # imm = 0xF4240
addq _ZZ5wtimevE3tv0+8(%rip), %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI0_0(%rip), %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z5wtimev, .Lfunc_end0-_Z5wtimev
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z11init_matrixPfiif
.LCPI1_0:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.text
.globl _Z11init_matrixPfiif
.p2align 4, 0x90
.type _Z11init_matrixPfiif,@function
_Z11init_matrixPfiif: # @_Z11init_matrixPfiif
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_8
# %bb.1: # %.preheader.lr.ph
movaps .LCPI1_0(%rip), %xmm1 # xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
xorps %xmm0, %xmm1
mulss %xmm0, %xmm0
movl %esi, %eax
movl %edx, %ecx
xorl %esi, %esi
xorl %r8d, %r8d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_7: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r8
addl %edx, %esi
cmpq %rax, %r8
je .LBB1_8
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %edx, %edx
jle .LBB1_7
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %esi, %r9d
leaq (%rdi,%r9,4), %r9
xorl %r10d, %r10d
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_6: # in Loop: Header=BB1_4 Depth=2
movss %xmm2, (%r9,%r10,4)
incq %r10
cmpq %r10, %rcx
je .LBB1_7
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movaps %xmm0, %xmm2
cmpq %r10, %r8
je .LBB1_6
# %bb.5: # in Loop: Header=BB1_4 Depth=2
movaps %xmm1, %xmm2
jmp .LBB1_6
.LBB1_8: # %._crit_edge22
retq
.Lfunc_end1:
.size _Z11init_matrixPfiif, .Lfunc_end1-_Z11init_matrixPfiif
.cfi_endproc
# -- End function
.globl _Z12print_matrixPfii # -- Begin function _Z12print_matrixPfii
.p2align 4, 0x90
.type _Z12print_matrixPfii,@function
_Z12print_matrixPfii: # @_Z12print_matrixPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB2_6
# %bb.1: # %.lr.ph15
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %r13d
xorl %ebp, %ebp
xorl %r15d, %r15d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addl %ebx, %ebp
cmpq 16(%rsp), %r15 # 8-byte Folded Reload
je .LBB2_6
.LBB2_2: # =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
movl $.L.str, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
testl %ebx, %ebx
jle .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %ebp, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r12
cmpq %r12, %r13
jne .LBB2_4
jmp .LBB2_5
.LBB2_6: # %._crit_edge16
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12print_matrixPfii, .Lfunc_end2-_Z12print_matrixPfii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z12check_matrixPfS_ii
.LCPI3_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI3_1:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.text
.globl _Z12check_matrixPfS_ii
.p2align 4, 0x90
.type _Z12check_matrixPfS_ii,@function
_Z12check_matrixPfS_ii: # @_Z12check_matrixPfS_ii
.cfi_startproc
# %bb.0:
movl $1, %eax
testl %edx, %edx
jle .LBB3_9
# %bb.1: # %.preheader.lr.ph
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edx, %r9d
movl %ecx, %r10d
xorl %r11d, %r11d
movaps .LCPI3_0(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero
xorl %r8d, %r8d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_7: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incq %r8
addl %ecx, %r11d
cmpq %r9, %r8
je .LBB3_8
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
testl %ecx, %ecx
jle .LBB3_7
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %r11d, %edx
leaq (%rsi,%rdx,4), %rbx
leaq (%rdi,%rdx,4), %r14
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%rdx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss (%rbx,%rdx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
movaps %xmm2, %xmm4
subss %xmm3, %xmm4
andps %xmm0, %xmm4
cvtss2sd %xmm4, %xmm4
ucomisd %xmm1, %xmm4
ja .LBB3_5
# %bb.6: # in Loop: Header=BB3_4 Depth=2
incq %rdx
cmpq %rdx, %r10
jne .LBB3_4
jmp .LBB3_7
.LBB3_5:
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm3, %xmm1
movl $.L.str.3, %edi
movl %r8d, %esi
# kill: def $edx killed $edx killed $rdx
movb $2, %al
callq printf
xorl %eax, %eax
.LBB3_8:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB3_9: # %.loopexit
retq
.Lfunc_end3:
.size _Z12check_matrixPfS_ii, .Lfunc_end3-_Z12check_matrixPfS_ii
.cfi_endproc
# -- End function
.globl _Z3MulPfS_iiiS_ # -- Begin function _Z3MulPfS_iiiS_
.p2align 4, 0x90
.type _Z3MulPfS_iiiS_,@function
_Z3MulPfS_iiiS_: # @_Z3MulPfS_iiiS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, -8(%rsp) # 8-byte Spill
movq %rsi, -16(%rsp) # 8-byte Spill
movq %rdi, -24(%rsp) # 8-byte Spill
testl %edx, %edx
jle .LBB4_9
# %bb.1: # %.preheader.lr.ph
movslq %r8d, %rdi
movl %edx, %edx
movl %edi, %r10d
movl %ecx, %r11d
leaq (,%rdi,4), %rbx
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_8: # %._crit_edge31
# in Loop: Header=BB4_2 Depth=1
incq %r15
addl %ecx, %r14d
cmpq %rdx, %r15
je .LBB4_9
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
# Child Loop BB4_6 Depth 3
testl %r8d, %r8d
jle .LBB4_8
# %bb.3: # %.lr.ph30
# in Loop: Header=BB4_2 Depth=1
movl %r14d, %eax
movq -24(%rsp), %rsi # 8-byte Reload
leaq (%rsi,%rax,4), %r12
movq %r15, %rax
imulq %rdi, %rax
movq -8(%rsp), %rsi # 8-byte Reload
leaq (%rsi,%rax,4), %r13
movq -16(%rsp), %rsi # 8-byte Reload
xorl %eax, %eax
jmp .LBB4_4
.p2align 4, 0x90
.LBB4_7: # %._crit_edge
# in Loop: Header=BB4_4 Depth=2
incq %rax
addq $4, %rsi
cmpq %r10, %rax
je .LBB4_8
.LBB4_4: # Parent Loop BB4_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_6 Depth 3
movl $0, (%r13,%rax,4)
testl %ecx, %ecx
jle .LBB4_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB4_4 Depth=2
movss (%r13,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rsi, %rbp
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB4_6: # Parent Loop BB4_2 Depth=1
# Parent Loop BB4_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r12,%r9,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rbp), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%r13,%rax,4)
incq %r9
addq %rbx, %rbp
cmpq %r9, %r11
jne .LBB4_6
jmp .LBB4_7
.LBB4_9: # %._crit_edge33
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z3MulPfS_iiiS_, .Lfunc_end4-_Z3MulPfS_iiiS_
.cfi_endproc
# -- End function
.globl _Z27__device_stub__mulMatrixGPUPfS_S_iii # -- Begin function _Z27__device_stub__mulMatrixGPUPfS_S_iii
.p2align 4, 0x90
.type _Z27__device_stub__mulMatrixGPUPfS_S_iii,@function
_Z27__device_stub__mulMatrixGPUPfS_S_iii: # @_Z27__device_stub__mulMatrixGPUPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12mulMatrixGPUPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end5:
.size _Z27__device_stub__mulMatrixGPUPfS_S_iii, .Lfunc_end5-_Z27__device_stub__mulMatrixGPUPfS_S_iii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI6_0:
.long 0xc0000000 # float -2
.long 0x40800000 # float 4
.LCPI6_1:
.long 0xbf800000 # float -1
.long 0x3f800000 # float 1
.LCPI6_2:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI6_4:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI6_3:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movq stdout(%rip), %rdi
xorl %esi, %esi
callq setbuf
cmpl $4, %ebp
jne .LBB6_34
# %bb.1:
movq 8(%rbx), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movl %r12d, %eax
imull %ebp, %eax
movslq %eax, %rdi
shlq $2, %rdi
movq %rdi, 96(%rsp) # 8-byte Spill
callq malloc
testl %r12d, %r12d
jle .LBB6_7
# %bb.2: # %.preheader.lr.ph.i
movl %r12d, %r9d
movl %ebp, %ecx
xorl %edx, %edx
jmp .LBB6_3
.p2align 4, 0x90
.LBB6_6: # %._crit_edge.i
# in Loop: Header=BB6_3 Depth=1
incq %rdx
addl %ebp, %r15d
cmpq %r9, %rdx
je .LBB6_7
.LBB6_3: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB6_5 Depth 2
testl %ebp, %ebp
jle .LBB6_6
# %bb.4: # %.lr.ph.i
# in Loop: Header=BB6_3 Depth=1
movl %r15d, %esi
leaq (%rax,%rsi,4), %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB6_5: # Parent Loop BB6_3 Depth=1
# => This Inner Loop Header: Depth=2
xorl %r8d, %r8d
cmpq %rdi, %rdx
sete %r8b
movss .LCPI6_0(,%r8,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rsi,%rdi,4)
incq %rdi
cmpq %rdi, %rcx
jne .LBB6_5
jmp .LBB6_6
.LBB6_7: # %_Z11init_matrixPfiif.exit
movq %rax, 16(%rsp) # 8-byte Spill
movl %ebp, %eax
imull %r14d, %eax
movslq %eax, %rdi
shlq $2, %rdi
movq %rdi, 88(%rsp) # 8-byte Spill
callq malloc
testl %ebp, %ebp
jle .LBB6_13
# %bb.8: # %.preheader.lr.ph.i58
movl %ebp, %r10d
movl %r14d, %ecx
xorl %edx, %edx
xorl %esi, %esi
jmp .LBB6_9
.p2align 4, 0x90
.LBB6_12: # %._crit_edge.i62
# in Loop: Header=BB6_9 Depth=1
incq %rsi
addl %r14d, %edx
cmpq %r10, %rsi
je .LBB6_13
.LBB6_9: # %.preheader.i60
# =>This Loop Header: Depth=1
# Child Loop BB6_11 Depth 2
testl %r14d, %r14d
jle .LBB6_12
# %bb.10: # %.lr.ph.i65
# in Loop: Header=BB6_9 Depth=1
movl %edx, %edi
leaq (%rax,%rdi,4), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB6_11: # Parent Loop BB6_9 Depth=1
# => This Inner Loop Header: Depth=2
xorl %r9d, %r9d
cmpq %r8, %rsi
sete %r9b
movss .LCPI6_1(,%r9,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rdi,%r8,4)
incq %r8
cmpq %r8, %rcx
jne .LBB6_11
jmp .LBB6_12
.LBB6_13: # %_Z11init_matrixPfiif.exit70
movq %rax, 8(%rsp) # 8-byte Spill
movl %r12d, %eax
imull %r14d, %eax
movslq %eax, %rbx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, 24(%rsp) # 8-byte Spill
xorl %r15d, %r15d
movl $_ZZ5wtimevE3tv0, %edi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, _ZZ5wtimevE3tv0(%rip), %rax # imm = 0xF4240
addq _ZZ5wtimevE3tv0+8(%rip), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI6_2(%rip), %xmm0
movsd %xmm0, 80(%rsp) # 8-byte Spill
movq %r12, 72(%rsp) # 8-byte Spill
testl %r12d, %r12d
jle .LBB6_23
# %bb.14: # %.preheader.lr.ph.i71
movslq %r14d, %rax
movl 72(%rsp), %ecx # 4-byte Reload
movl %eax, %edx
movl %ebp, %esi
movq %rax, (%rsp) # 8-byte Spill
leaq (,%rax,4), %rdi
xorl %r8d, %r8d
jmp .LBB6_15
.p2align 4, 0x90
.LBB6_22: # %._crit_edge31.i
# in Loop: Header=BB6_15 Depth=1
incq %r8
addl %ebp, %r15d
cmpq %rcx, %r8
je .LBB6_23
.LBB6_15: # %.preheader.i72
# =>This Loop Header: Depth=1
# Child Loop BB6_17 Depth 2
# Child Loop BB6_19 Depth 3
testl %r14d, %r14d
jle .LBB6_22
# %bb.16: # %.lr.ph30.i
# in Loop: Header=BB6_15 Depth=1
movl %r15d, %r9d
movq 16(%rsp), %r10 # 8-byte Reload
leaq (%r10,%r9,4), %r9
movq %r8, %r10
imulq (%rsp), %r10 # 8-byte Folded Reload
movq 24(%rsp), %r11 # 8-byte Reload
leaq (%r11,%r10,4), %r10
movq 8(%rsp), %r12 # 8-byte Reload
xorl %r13d, %r13d
jmp .LBB6_17
.p2align 4, 0x90
.LBB6_20: # %._crit_edge.i73.loopexit
# in Loop: Header=BB6_17 Depth=2
movss %xmm0, (%r10,%r13,4)
movq %rax, %rbx
.LBB6_21: # %._crit_edge.i73
# in Loop: Header=BB6_17 Depth=2
incq %r13
addq $4, %r12
cmpq %rdx, %r13
je .LBB6_22
.LBB6_17: # Parent Loop BB6_15 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_19 Depth 3
movl $0, (%r10,%r13,4)
testl %ebp, %ebp
jle .LBB6_21
# %bb.18: # %.lr.ph.i74
# in Loop: Header=BB6_17 Depth=2
movq %rbx, %rax
xorpd %xmm0, %xmm0
movq %r12, %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB6_19: # Parent Loop BB6_15 Depth=1
# Parent Loop BB6_17 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r9,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r11), %xmm1
addss %xmm1, %xmm0
incq %rbx
addq %rdi, %r11
cmpq %rbx, %rsi
jne .LBB6_19
jmp .LBB6_20
.LBB6_23: # %_Z3MulPfS_iiiS_.exit
movl $_ZZ5wtimevE3tv0, %edi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, _ZZ5wtimevE3tv0(%rip), %rax # imm = 0xF4240
addq _ZZ5wtimevE3tv0+8(%rip), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI6_2(%rip), %xmm0
subsd 80(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.5, %edi
movb $1, %al
callq printf
leaq 48(%rsp), %rdi
movq 96(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq 88(%rsp), %r12 # 8-byte Reload
movq %r12, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq 8(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq 16(%rsp), %rsi # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 72(%rsp), %r12 # 8-byte Reload
movl %r12d, %eax
movq %r14, %r15
shlq $32, %r15
movq %rax, %r13
orq %rax, %r15
movl $_ZZ5wtimevE3tv0, %edi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, _ZZ5wtimevE3tv0(%rip), %rax # imm = 0xF4240
addq _ZZ5wtimevE3tv0+8(%rip), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI6_2(%rip), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_25
# %bb.24:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %ebp, 68(%rsp)
movl %r14d, 64(%rsp)
movl %r12d, 60(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 68(%rsp), %rax
movq %rax, 200(%rsp)
leaq 64(%rsp), %rax
movq %rax, 208(%rsp)
leaq 60(%rsp), %rax
movq %rax, 216(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z12mulMatrixGPUPfS_S_iii, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_25:
callq hipDeviceSynchronize
xorl %ebp, %ebp
movl $_ZZ5wtimevE3tv0, %edi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, _ZZ5wtimevE3tv0(%rip), %rax # imm = 0xF4240
addq _ZZ5wtimevE3tv0+8(%rip), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI6_2(%rip), %xmm0
subsd (%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq malloc
movq %rax, %r15
movq 32(%rsp), %rsi
movq %rax, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testl %r12d, %r12d
jle .LBB6_33
# %bb.26: # %.preheader.lr.ph.i79
movl %r14d, %eax
movaps .LCPI6_3(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI6_4(%rip), %xmm1 # xmm1 = mem[0],zero
xorl %esi, %esi
jmp .LBB6_27
.p2align 4, 0x90
.LBB6_32: # %._crit_edge.i81
# in Loop: Header=BB6_27 Depth=1
incq %rsi
addl %r14d, %ebp
cmpq %r13, %rsi
je .LBB6_33
.LBB6_27: # %.preheader.i80
# =>This Loop Header: Depth=1
# Child Loop BB6_29 Depth 2
testl %r14d, %r14d
jle .LBB6_32
# %bb.28: # %.lr.ph.i82
# in Loop: Header=BB6_27 Depth=1
movl %ebp, %edx
leaq (%r15,%rdx,4), %rcx
movq 24(%rsp), %rdi # 8-byte Reload
leaq (%rdi,%rdx,4), %rdi
xorl %edx, %edx
.p2align 4, 0x90
.LBB6_29: # Parent Loop BB6_27 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdi,%rdx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss (%rcx,%rdx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
movaps %xmm2, %xmm4
subss %xmm3, %xmm4
andps %xmm0, %xmm4
cvtss2sd %xmm4, %xmm4
ucomisd %xmm1, %xmm4
ja .LBB6_30
# %bb.31: # in Loop: Header=BB6_29 Depth=2
incq %rdx
cmpq %rdx, %rax
jne .LBB6_29
jmp .LBB6_32
.LBB6_30:
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm3, %xmm1
movl $.L.str.3, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
movb $2, %al
callq printf
.LBB6_33: # %_Z12check_matrixPfS_ii.exit
movq 16(%rsp), %rdi # 8-byte Reload
callq free
movq 8(%rsp), %rdi # 8-byte Reload
callq free
movq 24(%rsp), %rdi # 8-byte Reload
callq free
movq %r15, %rdi
callq free
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movl $1, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_34:
.cfi_def_cfa_offset 288
movl $.Lstr, %edi
callq puts@PLT
movl $-1, %edi
callq exit
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12mulMatrixGPUPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZZ5wtimevE3tv0,@object # @_ZZ5wtimevE3tv0
.local _ZZ5wtimevE3tv0
.comm _ZZ5wtimevE3tv0,16,8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Line %i: "
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%4.1f "
.size .L.str.1, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "device!=host %f!=%f in (%i,%i)\n"
.size .L.str.3, 32
.type _Z12mulMatrixGPUPfS_S_iii,@object # @_Z12mulMatrixGPUPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z12mulMatrixGPUPfS_S_iii
.p2align 3, 0x0
_Z12mulMatrixGPUPfS_S_iii:
.quad _Z27__device_stub__mulMatrixGPUPfS_S_iii
.size _Z12mulMatrixGPUPfS_S_iii, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "Time CPU=%f\n"
.size .L.str.5, 13
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Time GPU=%f\n"
.size .L.str.6, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12mulMatrixGPUPfS_S_iii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "./exec hA hB/WA wB"
.size .Lstr, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__mulMatrixGPUPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZZ5wtimevE3tv0
.addrsig_sym _Z12mulMatrixGPUPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
/* square root of number of threads in a block (the number of threads in a block is NT^2) */
#define NT 32
/* length of the target domain */
#define L 10.0
/* number of division for the discretization of the target domain */
#define N 256
/* dimensionless time step size (theta = D * dt / dx^2) */
#define THETA 0.1
/* number of iterations */
#define M 2000
/* constants on a GPU */
__device__ __constant__ int n;
__device__ __constant__ double theta;
//GPU functions-----------------------------------------------------------------
__global__ void diffusion_global(double *field_device, double *field_device_new) {
int i_global;
int j_global;
int i_left, i_right;
int j_top, j_bottom;
i_global = blockDim.x * blockIdx.x + threadIdx.x;
if(i_global < n) {
i_right = (i_global + 1) % n;
i_left = (i_global - 1 + n) % n;
for(j_global = threadIdx.y; j_global < n; j_global += NT) {
j_top = (j_global + 1) % n;
j_bottom = (j_global - 1 + n) % n;
field_device_new[i_global * n + j_global] = field_device[i_global * n + j_global]
+ theta * (field_device[i_right * n + j_global] + field_device[i_left * n + j_global]
+ field_device[i_global * n + j_top] + field_device[i_global * n + j_bottom]
- 4.0 * field_device[i_global * n + j_global]);
}
}
}
__global__ void diffusion_shared(double *field_device, double *field_device_new) {
int i_global;
int j_global;
int i_shared;
int j_shared;
int i_left, i_right;
int j_top, j_bottom;
double field_register;
__shared__ double field_shared[(NT + 2) * (NT + 2)];
i_global = blockDim.x * blockIdx.x + threadIdx.x;
i_shared = threadIdx.x + 1;
j_shared = threadIdx.y + 1;
if(i_global < n) {
for(j_global = threadIdx.y; j_global < n; j_global += NT) {
//copy field from global to shared----------------------
field_register = field_device[i_global * n + j_global];
field_shared[i_shared * (NT + 2) + j_shared] = field_register;
if(i_shared == 1) {
i_left = (i_global - 1 + n) % n;
field_shared[0 * (NT + 2) + j_shared] = field_device[i_left * n + j_global];
} else if(i_shared == NT) {
i_right = (i_global + 1) % n;
field_shared[(NT + 1) * (NT + 2) + j_shared] = field_device[i_right * n + j_global];
}
if(j_shared == 1) {
j_bottom = (j_global - 1 + n) % n;
field_shared[i_shared * (NT + 2) + 0] = field_device[i_global * n + j_bottom];
} else if(j_shared == NT) {
j_top = (j_global + 1) % n;
field_shared[i_shared * (NT + 2) + (NT + 1)] = field_device[i_global * n + j_top];
}
__syncthreads();
//calculate field evolution-----------------------------
field_device_new[i_global * n + j_global] = field_register
+ theta * (field_shared[(i_shared + 1) * (NT + 2) + j_shared] + field_shared[(i_shared - 1) * (NT + 2) + j_shared]
+ field_shared[i_shared * (NT + 2) + (j_shared + 1)] + field_shared[i_shared * (NT + 2) + (j_shared - 1)]
- 4.0 * field_register);
}
}
}
//Host functions----------------------------------------------------------------
void init_field(double *field_host, int n_host, int l_host) {
int i;
int j;
double x;
double y;
double dx = l_host / (double)n_host;
double dy = l_host / (double)n_host;
double midst = l_host * 0.5;
for(i = 0; i < n_host; i += 1) {
x = (double)i * dx;
for(j = 0; j < n_host; j += 1) {
y = (double)j * dy;
if((x > midst && y > midst) || (x < midst && y < midst)) {
field_host[n_host * j + i] = 1.0;
} else {
field_host[n_host * j + i] = 0.0;
}
}
}
}
void flip_ij(int *i, int *j) {
int i_temp;
i_temp = *i;
*i = *j;
*j = i_temp;
}
void print_field(FILE *file_write, double *field, int n, double l) {
int i;
int j;
double x;
double y;
double d = l/(double)n;
for(i = 0; i < N; i += 1) {
y = (double)j * d;
for(j = 0; j < N; j += 1) {
x = (double)i * d;
fprintf(file_write, "%f %f %f\n", x, y, field[i * n + j]);
}
}
}
void diffusion_host(double *field_host, double *field_host_new, int n_host, double theta_host) {
int i;
int j;
int i_right, i_left;
int j_top, j_bottom;
for(i = 0; i < n_host; i += 1) {
i_right = (i + 1) % n_host;
i_left = (i - 1 + n_host) % n_host;
for(j = 0; j < n_host; j += 1) {
j_top = (j + 1) % n_host;
j_bottom = (j - 1 + n_host) % n_host;
field_host_new[i * n_host + j] = field_host[i * n_host + j]
+ theta_host * (field_host[i_right * n_host + j] + field_host[i_left * n_host + j]
+ field_host[i * n_host + j_top] + field_host[i * n_host + j_bottom]
- 4.0 * field_host[i * n_host + j]);
}
}
}
double check_residue(double *field_host, double *field_device, int n_host) {
int i;
double residue = 0.0;
for(i = 0; i < n_host * n_host; i += 1) {
residue += (field_host[i] - field_device[i]) * (field_host[i] - field_device[i]);;
}
return residue;
}
int main(void) {
//delcare variavles-------------------------------------------------------------
int i;
int j;
int k;
int n_host;
int n_square;
int iteration;
int n_blocks;
double l_host;
double theta_host;
dim3 dim_threads;
double *field_host[2];
double *field_device[2];
double *result_host;
double *result_global_host;
double *result_shared_host;
FILE *file_write;
char filename_write[256];
clock_t start, end;
//initialize--------------------------------------------------------------------
//set variables---------------------------------------------------------
n_host = N;
n_square = N * N;
l_host = L;
theta_host = THETA;
dim_threads.x = NT;
dim_threads.y = NT;
dim_threads.z = 1;
n_blocks = (int)(ceil((double)n_host / NT));
iteration = M;
//allocate memories-----------------------------------------------------
cudaMemcpyToSymbol(n, &n_host, sizeof(int), 0, cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(theta, &theta_host, sizeof(double), 0, cudaMemcpyHostToDevice);
cudaHostAlloc((void **)&field_host[0], n_square * sizeof(double), cudaHostAllocMapped);
cudaHostAlloc((void **)&field_host[1], n_square * sizeof(double), cudaHostAllocMapped);
cudaHostAlloc((void **)&result_global_host, n_square * sizeof(double), cudaHostAllocMapped);
cudaHostAlloc((void **)&result_shared_host, n_square * sizeof(double), cudaHostAllocMapped);
cudaMalloc((void **)&field_device[0], n_square * sizeof(double));
cudaMalloc((void **)&field_device[1], n_square * sizeof(double));
result_host = (double *)malloc(n_square * sizeof(double));
//calculate on CPU--------------------------------------------------------------
//initialize field------------------------------------------------------
init_field(field_host[0], n_host, l_host);
start = clock();
//iteration-------------------------------------------------------------
i = 0;
j = 1;
for(k = 0; k < iteration; k += 1) {
diffusion_host(field_host[i], field_host[j], n_host, theta_host);
flip_ij(&i, &j);
}
//save and print out----------------------------------------------------
memcpy(result_host, field_host[i], n_square * sizeof(double));
end = clock();
printf("host:%ld\n", end - start);
/*sprintf(filename_write, "result_host.txt");
file_write = fopen(filename_write, "w");
print_field(file_write, result_host, n_host, l_host);
fclose(file_write);*/
//calculate using only global memory--------------------------------------------
//initialize field------------------------------------------------------
init_field(field_host[0], n_host, l_host);
start = clock();
cudaMemcpy(field_device[0], field_host[0], n_square * sizeof(double), cudaMemcpyHostToDevice);
//iteration-------------------------------------------------------------
i = 0;
j = 1;
for(k = 0; k < iteration; k += 1) {
diffusion_global<<<n_blocks, dim_threads>>>(field_device[i], field_device[j]);
cudaDeviceSynchronize();
flip_ij(&i, &j);
}
//copy to host and print out--------------------------------------------
cudaMemcpy(result_global_host, field_device[i], n_square * sizeof(double), cudaMemcpyDeviceToHost);
end = clock();
printf("global:%ld\n", end - start);
/*sprintf(filename_write, "result_global.txt");
file_write = fopen(filename_write, "w");
print_field(file_write, result_global_host, n_host, l_host);
fclose(file_write);*/
//calculate using shared memory-------------------------------------------------
//initialize field------------------------------------------------------
init_field(field_host[0], n_host, l_host);
start = clock();
cudaMemcpy(field_device[0], field_host[0], n_square * sizeof(double), cudaMemcpyHostToDevice);
//iteration-------------------------------------------------------------
i = 0;
j = 1;
for(k = 0; k < iteration; k += 1) {
diffusion_shared<<<n_blocks, dim_threads>>>(field_device[i], field_device[j]);
cudaDeviceSynchronize();
flip_ij(&i, &j);
}
//copy to host and print out--------------------------------------------
cudaMemcpy(result_shared_host, field_device[i], n_square * sizeof(double), cudaMemcpyDeviceToHost);
end = clock();
printf("shared:%ld\n", end - start);
/*sprintf(filename_write, "result_shared.txt");
file_write = fopen(filename_write, "w");
print_field(file_write, result_shared_host, n_host, l_host);
fclose(file_write);*/
//check answers-----------------------------------------------------------------
printf("answers\n");
printf("global:%f\n", check_residue(result_host, result_global_host, n_host));
printf("shared:%f\n", check_residue(result_host, result_shared_host, n_host));
//finalize----------------------------------------------------------------------
cudaFreeHost(field_host[0]);
cudaFreeHost(field_host[1]);
cudaFreeHost(result_global_host);
cudaFreeHost(result_shared_host);
cudaFree(field_device[0]);
cudaFree(field_device[1]);
free(result_host);
return 0;
} | .file "tmpxft_001891f2_00000000-6_diffusion_me.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10init_fieldPdii
.type _Z10init_fieldPdii, @function
_Z10init_fieldPdii:
.LFB2057:
.cfi_startproc
endbr64
pxor %xmm1, %xmm1
cvtsi2sdl %edx, %xmm1
pxor %xmm0, %xmm0
cvtsi2sdl %esi, %xmm0
movapd %xmm1, %xmm3
divsd %xmm0, %xmm3
mulsd .LC0(%rip), %xmm1
testl %esi, %esi
jle .L3
movl $0, %r8d
movl $0, %r9d
movsd .LC1(%rip), %xmm4
jmp .L13
.L18:
comisd %xmm2, %xmm1
jbe .L8
comisd %xmm0, %xmm1
ja .L7
.L8:
movslq %edx, %rcx
movq $0x000000000, (%rdi,%rcx,8)
.L11:
leal 1(%rax), %ecx
addl %esi, %edx
cmpl %ecx, %esi
je .L19
movl %ecx, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd %xmm3, %xmm0
comisd %xmm1, %xmm2
jbe .L18
comisd %xmm1, %xmm0
jbe .L8
.L7:
movslq %edx, %rcx
movsd %xmm4, (%rdi,%rcx,8)
jmp .L11
.L19:
leal 1(%r8), %edx
cmpl %eax, %r8d
je .L3
movl %edx, %r8d
.L13:
pxor %xmm2, %xmm2
cvtsi2sdl %r8d, %xmm2
mulsd %xmm3, %xmm2
movl %r8d, %edx
movl %r9d, %eax
jmp .L12
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z10init_fieldPdii, .-_Z10init_fieldPdii
.globl _Z7flip_ijPiS_
.type _Z7flip_ijPiS_, @function
_Z7flip_ijPiS_:
.LFB2058:
.cfi_startproc
endbr64
movl (%rdi), %eax
movl (%rsi), %edx
movl %edx, (%rdi)
movl %eax, (%rsi)
ret
.cfi_endproc
.LFE2058:
.size _Z7flip_ijPiS_, .-_Z7flip_ijPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "%f %f %f\n"
.text
.globl _Z11print_fieldP8_IO_FILEPdid
.type _Z11print_fieldP8_IO_FILEPdid, @function
_Z11print_fieldP8_IO_FILEPdid:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movl %edx, %eax
movapd %xmm0, %xmm1
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
divsd %xmm0, %xmm1
movsd %xmm1, 24(%rsp)
mulsd .LC3(%rip), %xmm1
movsd %xmm1, 16(%rsp)
cltq
leaq 0(,%rax,8), %r15
leaq 2048(%rsi), %rbp
movl $0, %r14d
leaq .LC4(%rip), %r13
.L23:
pxor %xmm0, %xmm0
cvtsi2sdl %r14d, %xmm0
mulsd 24(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
leaq -2048(%rbp), %rbx
.L22:
movsd (%rbx), %xmm2
movsd 16(%rsp), %xmm1
movsd 8(%rsp), %xmm0
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $3, %eax
call __fprintf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L22
addl $1, %r14d
addq %r15, %rbp
cmpl $256, %r14d
jne .L23
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z11print_fieldP8_IO_FILEPdid, .-_Z11print_fieldP8_IO_FILEPdid
.globl _Z14diffusion_hostPdS_id
.type _Z14diffusion_hostPdS_id, @function
_Z14diffusion_hostPdS_id:
.LFB2060:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L34
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, %r8
movl %edx, %edi
movslq %edx, %r14
leaq 0(,%r14,8), %r15
movq %r8, %r10
movq %rsi, %r9
movl $0, %r13d
movl $0, %r12d
leal -2(%rdx), %r11d
movsd .LC5(%rip), %xmm4
.L30:
addl $1, %r12d
movl %r13d, %esi
movl %r12d, %eax
cltd
idivl %edi
imull %edi, %edx
movslq %edx, %rdx
leaq (%r8,%rdx,8), %rbp
leal (%r12,%r11), %eax
cltd
idivl %edi
imull %edi, %edx
movslq %edx, %rdx
leaq (%r8,%rdx,8), %rbx
movl $1, %ecx
.L29:
movsd -8(%r10,%rcx,8), %xmm3
movl %ecx, %eax
cltd
idivl %edi
addl %esi, %edx
movslq %edx, %rdx
movsd -8(%rbp,%rcx,8), %xmm2
addsd -8(%rbx,%rcx,8), %xmm2
addsd (%r8,%rdx,8), %xmm2
leal (%r11,%rcx), %eax
cltd
idivl %edi
addl %esi, %edx
movslq %edx, %rdx
movapd %xmm2, %xmm1
addsd (%r8,%rdx,8), %xmm1
movapd %xmm3, %xmm2
mulsd %xmm4, %xmm2
subsd %xmm2, %xmm1
mulsd %xmm0, %xmm1
addsd %xmm3, %xmm1
movsd %xmm1, -8(%r9,%rcx,8)
movq %rcx, %rax
addq $1, %rcx
cmpq %r14, %rax
jne .L29
addl %edi, %r13d
addq %r15, %r10
addq %r15, %r9
cmpl %edi, %r12d
jne .L30
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2060:
.size _Z14diffusion_hostPdS_id, .-_Z14diffusion_hostPdS_id
.globl _Z13check_residuePdS_i
.type _Z13check_residuePdS_i, @function
_Z13check_residuePdS_i:
.LFB2061:
.cfi_startproc
endbr64
imull %edx, %edx
testl %edx, %edx
jle .L40
movslq %edx, %rdx
salq $3, %rdx
movl $0, %eax
pxor %xmm1, %xmm1
.L39:
movsd (%rdi,%rax), %xmm0
subsd (%rsi,%rax), %xmm0
mulsd %xmm0, %xmm0
addsd %xmm0, %xmm1
addq $8, %rax
cmpq %rdx, %rax
jne .L39
.L37:
movapd %xmm1, %xmm0
ret
.L40:
pxor %xmm1, %xmm1
jmp .L37
.cfi_endproc
.LFE2061:
.size _Z13check_residuePdS_i, .-_Z13check_residuePdS_i
.globl _Z38__device_stub__Z16diffusion_globalPdS_PdS_
.type _Z38__device_stub__Z16diffusion_globalPdS_PdS_, @function
_Z38__device_stub__Z16diffusion_globalPdS_PdS_:
.LFB2087:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L46
.L42:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L47
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16diffusion_globalPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L42
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z38__device_stub__Z16diffusion_globalPdS_PdS_, .-_Z38__device_stub__Z16diffusion_globalPdS_PdS_
.globl _Z16diffusion_globalPdS_
.type _Z16diffusion_globalPdS_, @function
_Z16diffusion_globalPdS_:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z16diffusion_globalPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z16diffusion_globalPdS_, .-_Z16diffusion_globalPdS_
.globl _Z38__device_stub__Z16diffusion_sharedPdS_PdS_
.type _Z38__device_stub__Z16diffusion_sharedPdS_PdS_, @function
_Z38__device_stub__Z16diffusion_sharedPdS_PdS_:
.LFB2089:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L54
.L50:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L55
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16diffusion_sharedPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L50
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z38__device_stub__Z16diffusion_sharedPdS_PdS_, .-_Z38__device_stub__Z16diffusion_sharedPdS_PdS_
.globl _Z16diffusion_sharedPdS_
.type _Z16diffusion_sharedPdS_, @function
_Z16diffusion_sharedPdS_:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z16diffusion_sharedPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z16diffusion_sharedPdS_, .-_Z16diffusion_sharedPdS_
.section .rodata.str1.1
.LC7:
.string "host:%ld\n"
.LC8:
.string "global:%ld\n"
.LC9:
.string "shared:%ld\n"
.LC10:
.string "answers\n"
.LC11:
.string "global:%f\n"
.LC12:
.string "shared:%f\n"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $112, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $1, 48(%rsp)
movl $256, 12(%rsp)
movq .LC6(%rip), %rax
movq %rax, 16(%rsp)
movl $32, 40(%rsp)
movl $32, 44(%rsp)
leaq 12(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL1n(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 16(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $8, %edx
leaq _ZL5theta(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 64(%rsp), %rdi
movl $2, %edx
movl $524288, %esi
call cudaHostAlloc@PLT
leaq 72(%rsp), %rdi
movl $2, %edx
movl $524288, %esi
call cudaHostAlloc@PLT
leaq 24(%rsp), %rdi
movl $2, %edx
movl $524288, %esi
call cudaHostAlloc@PLT
leaq 32(%rsp), %rdi
movl $2, %edx
movl $524288, %esi
call cudaHostAlloc@PLT
leaq 80(%rsp), %rdi
movl $524288, %esi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movl $524288, %esi
call cudaMalloc@PLT
movl $524288, %edi
call malloc@PLT
movq %rax, %r12
movl $10, %edx
movl 12(%rsp), %esi
movq 64(%rsp), %rdi
call _Z10init_fieldPdii
call clock@PLT
movq %rax, %r14
movl $2000, %ebp
movl $1, %ebx
movl $0, %r13d
jmp .L59
.L65:
movl %r13d, %eax
movl %ebx, %r13d
movl %eax, %ebx
.L59:
movslq %ebx, %rax
movq 64(%rsp,%rax,8), %rsi
movslq %r13d, %rax
movq 64(%rsp,%rax,8), %rdi
movsd 16(%rsp), %xmm0
movl 12(%rsp), %edx
call _Z14diffusion_hostPdS_id
subl $1, %ebp
jne .L65
movslq %ebx, %rbx
movq 64(%rsp,%rbx,8), %rsi
movl $524288, %edx
movq %r12, %rdi
call memcpy@PLT
call clock@PLT
subq %r14, %rax
movq %rax, %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, %edx
movl 12(%rsp), %esi
movq 64(%rsp), %rdi
call _Z10init_fieldPdii
call clock@PLT
movq %rax, %r14
movl $1, %ecx
movl $524288, %edx
movq 64(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $2000, %ebx
movl $1, %ebp
movl $0, %r13d
jmp .L61
.L60:
call cudaDeviceSynchronize@PLT
subl $1, %ebx
je .L69
movl %r13d, %eax
movl %ebp, %r13d
movl %eax, %ebp
.L61:
movl $8, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl 48(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L60
movslq %ebp, %rax
movq 80(%rsp,%rax,8), %rsi
movslq %r13d, %rax
movq 80(%rsp,%rax,8), %rdi
call _Z38__device_stub__Z16diffusion_globalPdS_PdS_
jmp .L60
.L69:
movslq %ebp, %rbp
movq 80(%rsp,%rbp,8), %rsi
movl $2, %ecx
movl $524288, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
subq %r14, %rax
movq %rax, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, %edx
movl 12(%rsp), %esi
movq 64(%rsp), %rdi
call _Z10init_fieldPdii
call clock@PLT
movq %rax, %r14
movl $1, %ecx
movl $524288, %edx
movq 64(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $2000, %ebx
movl $1, %ebp
movl $0, %r13d
jmp .L63
.L62:
call cudaDeviceSynchronize@PLT
subl $1, %ebx
je .L70
movl %r13d, %eax
movl %ebp, %r13d
movl %eax, %ebp
.L63:
movl $8, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl 48(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L62
movslq %ebp, %rax
movq 80(%rsp,%rax,8), %rsi
movslq %r13d, %rax
movq 80(%rsp,%rax,8), %rdi
call _Z38__device_stub__Z16diffusion_sharedPdS_PdS_
jmp .L62
.L70:
movslq %ebp, %rbp
movq 80(%rsp,%rbp,8), %rsi
movl $2, %ecx
movl $524288, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
subq %r14, %rax
movq %rax, %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call _Z13check_residuePdS_i
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 12(%rsp), %edx
movq 32(%rsp), %rsi
movq %r12, %rdi
call _Z13check_residuePdS_i
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 64(%rsp), %rdi
call cudaFreeHost@PLT
movq 72(%rsp), %rdi
call cudaFreeHost@PLT
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
movq 32(%rsp), %rdi
call cudaFreeHost@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L71
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L71:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z16diffusion_sharedPdS_"
.LC14:
.string "_Z16diffusion_globalPdS_"
.LC15:
.string "n"
.LC16:
.string "theta"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z16diffusion_sharedPdS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z16diffusion_globalPdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1n(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5theta(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL5theta
.comm _ZL5theta,8,8
.local _ZL1n
.comm _ZL1n,4,4
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1071644672
.align 8
.LC1:
.long 0
.long 1072693248
.align 8
.LC3:
.long 0
.long 1081081856
.align 8
.LC5:
.long 0
.long 1074790400
.align 8
.LC6:
.long -1717986918
.long 1069128089
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
/* square root of number of threads in a block (the number of threads in a block is NT^2) */
#define NT 32
/* length of the target domain */
#define L 10.0
/* number of division for the discretization of the target domain */
#define N 256
/* dimensionless time step size (theta = D * dt / dx^2) */
#define THETA 0.1
/* number of iterations */
#define M 2000
/* constants on a GPU */
__device__ __constant__ int n;
__device__ __constant__ double theta;
//GPU functions-----------------------------------------------------------------
__global__ void diffusion_global(double *field_device, double *field_device_new) {
int i_global;
int j_global;
int i_left, i_right;
int j_top, j_bottom;
i_global = blockDim.x * blockIdx.x + threadIdx.x;
if(i_global < n) {
i_right = (i_global + 1) % n;
i_left = (i_global - 1 + n) % n;
for(j_global = threadIdx.y; j_global < n; j_global += NT) {
j_top = (j_global + 1) % n;
j_bottom = (j_global - 1 + n) % n;
field_device_new[i_global * n + j_global] = field_device[i_global * n + j_global]
+ theta * (field_device[i_right * n + j_global] + field_device[i_left * n + j_global]
+ field_device[i_global * n + j_top] + field_device[i_global * n + j_bottom]
- 4.0 * field_device[i_global * n + j_global]);
}
}
}
__global__ void diffusion_shared(double *field_device, double *field_device_new) {
int i_global;
int j_global;
int i_shared;
int j_shared;
int i_left, i_right;
int j_top, j_bottom;
double field_register;
__shared__ double field_shared[(NT + 2) * (NT + 2)];
i_global = blockDim.x * blockIdx.x + threadIdx.x;
i_shared = threadIdx.x + 1;
j_shared = threadIdx.y + 1;
if(i_global < n) {
for(j_global = threadIdx.y; j_global < n; j_global += NT) {
//copy field from global to shared----------------------
field_register = field_device[i_global * n + j_global];
field_shared[i_shared * (NT + 2) + j_shared] = field_register;
if(i_shared == 1) {
i_left = (i_global - 1 + n) % n;
field_shared[0 * (NT + 2) + j_shared] = field_device[i_left * n + j_global];
} else if(i_shared == NT) {
i_right = (i_global + 1) % n;
field_shared[(NT + 1) * (NT + 2) + j_shared] = field_device[i_right * n + j_global];
}
if(j_shared == 1) {
j_bottom = (j_global - 1 + n) % n;
field_shared[i_shared * (NT + 2) + 0] = field_device[i_global * n + j_bottom];
} else if(j_shared == NT) {
j_top = (j_global + 1) % n;
field_shared[i_shared * (NT + 2) + (NT + 1)] = field_device[i_global * n + j_top];
}
__syncthreads();
//calculate field evolution-----------------------------
field_device_new[i_global * n + j_global] = field_register
+ theta * (field_shared[(i_shared + 1) * (NT + 2) + j_shared] + field_shared[(i_shared - 1) * (NT + 2) + j_shared]
+ field_shared[i_shared * (NT + 2) + (j_shared + 1)] + field_shared[i_shared * (NT + 2) + (j_shared - 1)]
- 4.0 * field_register);
}
}
}
//Host functions----------------------------------------------------------------
void init_field(double *field_host, int n_host, int l_host) {
int i;
int j;
double x;
double y;
double dx = l_host / (double)n_host;
double dy = l_host / (double)n_host;
double midst = l_host * 0.5;
for(i = 0; i < n_host; i += 1) {
x = (double)i * dx;
for(j = 0; j < n_host; j += 1) {
y = (double)j * dy;
if((x > midst && y > midst) || (x < midst && y < midst)) {
field_host[n_host * j + i] = 1.0;
} else {
field_host[n_host * j + i] = 0.0;
}
}
}
}
void flip_ij(int *i, int *j) {
int i_temp;
i_temp = *i;
*i = *j;
*j = i_temp;
}
void print_field(FILE *file_write, double *field, int n, double l) {
int i;
int j;
double x;
double y;
double d = l/(double)n;
for(i = 0; i < N; i += 1) {
y = (double)j * d;
for(j = 0; j < N; j += 1) {
x = (double)i * d;
fprintf(file_write, "%f %f %f\n", x, y, field[i * n + j]);
}
}
}
void diffusion_host(double *field_host, double *field_host_new, int n_host, double theta_host) {
int i;
int j;
int i_right, i_left;
int j_top, j_bottom;
for(i = 0; i < n_host; i += 1) {
i_right = (i + 1) % n_host;
i_left = (i - 1 + n_host) % n_host;
for(j = 0; j < n_host; j += 1) {
j_top = (j + 1) % n_host;
j_bottom = (j - 1 + n_host) % n_host;
field_host_new[i * n_host + j] = field_host[i * n_host + j]
+ theta_host * (field_host[i_right * n_host + j] + field_host[i_left * n_host + j]
+ field_host[i * n_host + j_top] + field_host[i * n_host + j_bottom]
- 4.0 * field_host[i * n_host + j]);
}
}
}
double check_residue(double *field_host, double *field_device, int n_host) {
int i;
double residue = 0.0;
for(i = 0; i < n_host * n_host; i += 1) {
residue += (field_host[i] - field_device[i]) * (field_host[i] - field_device[i]);;
}
return residue;
}
int main(void) {
//delcare variavles-------------------------------------------------------------
int i;
int j;
int k;
int n_host;
int n_square;
int iteration;
int n_blocks;
double l_host;
double theta_host;
dim3 dim_threads;
double *field_host[2];
double *field_device[2];
double *result_host;
double *result_global_host;
double *result_shared_host;
FILE *file_write;
char filename_write[256];
clock_t start, end;
//initialize--------------------------------------------------------------------
//set variables---------------------------------------------------------
n_host = N;
n_square = N * N;
l_host = L;
theta_host = THETA;
dim_threads.x = NT;
dim_threads.y = NT;
dim_threads.z = 1;
n_blocks = (int)(ceil((double)n_host / NT));
iteration = M;
//allocate memories-----------------------------------------------------
cudaMemcpyToSymbol(n, &n_host, sizeof(int), 0, cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(theta, &theta_host, sizeof(double), 0, cudaMemcpyHostToDevice);
cudaHostAlloc((void **)&field_host[0], n_square * sizeof(double), cudaHostAllocMapped);
cudaHostAlloc((void **)&field_host[1], n_square * sizeof(double), cudaHostAllocMapped);
cudaHostAlloc((void **)&result_global_host, n_square * sizeof(double), cudaHostAllocMapped);
cudaHostAlloc((void **)&result_shared_host, n_square * sizeof(double), cudaHostAllocMapped);
cudaMalloc((void **)&field_device[0], n_square * sizeof(double));
cudaMalloc((void **)&field_device[1], n_square * sizeof(double));
result_host = (double *)malloc(n_square * sizeof(double));
//calculate on CPU--------------------------------------------------------------
//initialize field------------------------------------------------------
init_field(field_host[0], n_host, l_host);
start = clock();
//iteration-------------------------------------------------------------
i = 0;
j = 1;
for(k = 0; k < iteration; k += 1) {
diffusion_host(field_host[i], field_host[j], n_host, theta_host);
flip_ij(&i, &j);
}
//save and print out----------------------------------------------------
memcpy(result_host, field_host[i], n_square * sizeof(double));
end = clock();
printf("host:%ld\n", end - start);
/*sprintf(filename_write, "result_host.txt");
file_write = fopen(filename_write, "w");
print_field(file_write, result_host, n_host, l_host);
fclose(file_write);*/
//calculate using only global memory--------------------------------------------
//initialize field------------------------------------------------------
init_field(field_host[0], n_host, l_host);
start = clock();
cudaMemcpy(field_device[0], field_host[0], n_square * sizeof(double), cudaMemcpyHostToDevice);
//iteration-------------------------------------------------------------
i = 0;
j = 1;
for(k = 0; k < iteration; k += 1) {
diffusion_global<<<n_blocks, dim_threads>>>(field_device[i], field_device[j]);
cudaDeviceSynchronize();
flip_ij(&i, &j);
}
//copy to host and print out--------------------------------------------
cudaMemcpy(result_global_host, field_device[i], n_square * sizeof(double), cudaMemcpyDeviceToHost);
end = clock();
printf("global:%ld\n", end - start);
/*sprintf(filename_write, "result_global.txt");
file_write = fopen(filename_write, "w");
print_field(file_write, result_global_host, n_host, l_host);
fclose(file_write);*/
//calculate using shared memory-------------------------------------------------
//initialize field------------------------------------------------------
init_field(field_host[0], n_host, l_host);
start = clock();
cudaMemcpy(field_device[0], field_host[0], n_square * sizeof(double), cudaMemcpyHostToDevice);
//iteration-------------------------------------------------------------
i = 0;
j = 1;
for(k = 0; k < iteration; k += 1) {
diffusion_shared<<<n_blocks, dim_threads>>>(field_device[i], field_device[j]);
cudaDeviceSynchronize();
flip_ij(&i, &j);
}
//copy to host and print out--------------------------------------------
cudaMemcpy(result_shared_host, field_device[i], n_square * sizeof(double), cudaMemcpyDeviceToHost);
end = clock();
printf("shared:%ld\n", end - start);
/*sprintf(filename_write, "result_shared.txt");
file_write = fopen(filename_write, "w");
print_field(file_write, result_shared_host, n_host, l_host);
fclose(file_write);*/
//check answers-----------------------------------------------------------------
printf("answers\n");
printf("global:%f\n", check_residue(result_host, result_global_host, n_host));
printf("shared:%f\n", check_residue(result_host, result_shared_host, n_host));
//finalize----------------------------------------------------------------------
cudaFreeHost(field_host[0]);
cudaFreeHost(field_host[1]);
cudaFreeHost(result_global_host);
cudaFreeHost(result_shared_host);
cudaFree(field_device[0]);
cudaFree(field_device[1]);
free(result_host);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
/* square root of number of threads in a block (the number of threads in a block is NT^2) */
#define NT 32
/* length of the target domain */
#define L 10.0
/* number of division for the discretization of the target domain */
#define N 256
/* dimensionless time step size (theta = D * dt / dx^2) */
#define THETA 0.1
/* number of iterations */
#define M 2000
/* constants on a GPU */
__device__ __constant__ int n;
__device__ __constant__ double theta;
//GPU functions-----------------------------------------------------------------
__global__ void diffusion_global(double *field_device, double *field_device_new) {
int i_global;
int j_global;
int i_left, i_right;
int j_top, j_bottom;
i_global = blockDim.x * blockIdx.x + threadIdx.x;
if(i_global < n) {
i_right = (i_global + 1) % n;
i_left = (i_global - 1 + n) % n;
for(j_global = threadIdx.y; j_global < n; j_global += NT) {
j_top = (j_global + 1) % n;
j_bottom = (j_global - 1 + n) % n;
field_device_new[i_global * n + j_global] = field_device[i_global * n + j_global]
+ theta * (field_device[i_right * n + j_global] + field_device[i_left * n + j_global]
+ field_device[i_global * n + j_top] + field_device[i_global * n + j_bottom]
- 4.0 * field_device[i_global * n + j_global]);
}
}
}
__global__ void diffusion_shared(double *field_device, double *field_device_new) {
int i_global;
int j_global;
int i_shared;
int j_shared;
int i_left, i_right;
int j_top, j_bottom;
double field_register;
__shared__ double field_shared[(NT + 2) * (NT + 2)];
i_global = blockDim.x * blockIdx.x + threadIdx.x;
i_shared = threadIdx.x + 1;
j_shared = threadIdx.y + 1;
if(i_global < n) {
for(j_global = threadIdx.y; j_global < n; j_global += NT) {
//copy field from global to shared----------------------
field_register = field_device[i_global * n + j_global];
field_shared[i_shared * (NT + 2) + j_shared] = field_register;
if(i_shared == 1) {
i_left = (i_global - 1 + n) % n;
field_shared[0 * (NT + 2) + j_shared] = field_device[i_left * n + j_global];
} else if(i_shared == NT) {
i_right = (i_global + 1) % n;
field_shared[(NT + 1) * (NT + 2) + j_shared] = field_device[i_right * n + j_global];
}
if(j_shared == 1) {
j_bottom = (j_global - 1 + n) % n;
field_shared[i_shared * (NT + 2) + 0] = field_device[i_global * n + j_bottom];
} else if(j_shared == NT) {
j_top = (j_global + 1) % n;
field_shared[i_shared * (NT + 2) + (NT + 1)] = field_device[i_global * n + j_top];
}
__syncthreads();
//calculate field evolution-----------------------------
field_device_new[i_global * n + j_global] = field_register
+ theta * (field_shared[(i_shared + 1) * (NT + 2) + j_shared] + field_shared[(i_shared - 1) * (NT + 2) + j_shared]
+ field_shared[i_shared * (NT + 2) + (j_shared + 1)] + field_shared[i_shared * (NT + 2) + (j_shared - 1)]
- 4.0 * field_register);
}
}
}
//Host functions----------------------------------------------------------------
void init_field(double *field_host, int n_host, int l_host) {
int i;
int j;
double x;
double y;
double dx = l_host / (double)n_host;
double dy = l_host / (double)n_host;
double midst = l_host * 0.5;
for(i = 0; i < n_host; i += 1) {
x = (double)i * dx;
for(j = 0; j < n_host; j += 1) {
y = (double)j * dy;
if((x > midst && y > midst) || (x < midst && y < midst)) {
field_host[n_host * j + i] = 1.0;
} else {
field_host[n_host * j + i] = 0.0;
}
}
}
}
void flip_ij(int *i, int *j) {
int i_temp;
i_temp = *i;
*i = *j;
*j = i_temp;
}
void print_field(FILE *file_write, double *field, int n, double l) {
int i;
int j;
double x;
double y;
double d = l/(double)n;
for(i = 0; i < N; i += 1) {
y = (double)j * d;
for(j = 0; j < N; j += 1) {
x = (double)i * d;
fprintf(file_write, "%f %f %f\n", x, y, field[i * n + j]);
}
}
}
void diffusion_host(double *field_host, double *field_host_new, int n_host, double theta_host) {
int i;
int j;
int i_right, i_left;
int j_top, j_bottom;
for(i = 0; i < n_host; i += 1) {
i_right = (i + 1) % n_host;
i_left = (i - 1 + n_host) % n_host;
for(j = 0; j < n_host; j += 1) {
j_top = (j + 1) % n_host;
j_bottom = (j - 1 + n_host) % n_host;
field_host_new[i * n_host + j] = field_host[i * n_host + j]
+ theta_host * (field_host[i_right * n_host + j] + field_host[i_left * n_host + j]
+ field_host[i * n_host + j_top] + field_host[i * n_host + j_bottom]
- 4.0 * field_host[i * n_host + j]);
}
}
}
double check_residue(double *field_host, double *field_device, int n_host) {
int i;
double residue = 0.0;
for(i = 0; i < n_host * n_host; i += 1) {
residue += (field_host[i] - field_device[i]) * (field_host[i] - field_device[i]);;
}
return residue;
}
int main(void) {
//delcare variavles-------------------------------------------------------------
int i;
int j;
int k;
int n_host;
int n_square;
int iteration;
int n_blocks;
double l_host;
double theta_host;
dim3 dim_threads;
double *field_host[2];
double *field_device[2];
double *result_host;
double *result_global_host;
double *result_shared_host;
FILE *file_write;
char filename_write[256];
clock_t start, end;
//initialize--------------------------------------------------------------------
//set variables---------------------------------------------------------
n_host = N;
n_square = N * N;
l_host = L;
theta_host = THETA;
dim_threads.x = NT;
dim_threads.y = NT;
dim_threads.z = 1;
n_blocks = (int)(ceil((double)n_host / NT));
iteration = M;
//allocate memories-----------------------------------------------------
hipMemcpyToSymbol(HIP_SYMBOL(n), &n_host, sizeof(int), 0, hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(theta), &theta_host, sizeof(double), 0, hipMemcpyHostToDevice);
hipHostAlloc((void **)&field_host[0], n_square * sizeof(double), hipHostMallocMapped);
hipHostAlloc((void **)&field_host[1], n_square * sizeof(double), hipHostMallocMapped);
hipHostAlloc((void **)&result_global_host, n_square * sizeof(double), hipHostMallocMapped);
hipHostAlloc((void **)&result_shared_host, n_square * sizeof(double), hipHostMallocMapped);
hipMalloc((void **)&field_device[0], n_square * sizeof(double));
hipMalloc((void **)&field_device[1], n_square * sizeof(double));
result_host = (double *)malloc(n_square * sizeof(double));
//calculate on CPU--------------------------------------------------------------
//initialize field------------------------------------------------------
init_field(field_host[0], n_host, l_host);
start = clock();
//iteration-------------------------------------------------------------
i = 0;
j = 1;
for(k = 0; k < iteration; k += 1) {
diffusion_host(field_host[i], field_host[j], n_host, theta_host);
flip_ij(&i, &j);
}
//save and print out----------------------------------------------------
memcpy(result_host, field_host[i], n_square * sizeof(double));
end = clock();
printf("host:%ld\n", end - start);
/*sprintf(filename_write, "result_host.txt");
file_write = fopen(filename_write, "w");
print_field(file_write, result_host, n_host, l_host);
fclose(file_write);*/
//calculate using only global memory--------------------------------------------
//initialize field------------------------------------------------------
init_field(field_host[0], n_host, l_host);
start = clock();
hipMemcpy(field_device[0], field_host[0], n_square * sizeof(double), hipMemcpyHostToDevice);
//iteration-------------------------------------------------------------
i = 0;
j = 1;
for(k = 0; k < iteration; k += 1) {
diffusion_global<<<n_blocks, dim_threads>>>(field_device[i], field_device[j]);
hipDeviceSynchronize();
flip_ij(&i, &j);
}
//copy to host and print out--------------------------------------------
hipMemcpy(result_global_host, field_device[i], n_square * sizeof(double), hipMemcpyDeviceToHost);
end = clock();
printf("global:%ld\n", end - start);
/*sprintf(filename_write, "result_global.txt");
file_write = fopen(filename_write, "w");
print_field(file_write, result_global_host, n_host, l_host);
fclose(file_write);*/
//calculate using shared memory-------------------------------------------------
//initialize field------------------------------------------------------
init_field(field_host[0], n_host, l_host);
start = clock();
hipMemcpy(field_device[0], field_host[0], n_square * sizeof(double), hipMemcpyHostToDevice);
//iteration-------------------------------------------------------------
i = 0;
j = 1;
for(k = 0; k < iteration; k += 1) {
diffusion_shared<<<n_blocks, dim_threads>>>(field_device[i], field_device[j]);
hipDeviceSynchronize();
flip_ij(&i, &j);
}
//copy to host and print out--------------------------------------------
hipMemcpy(result_shared_host, field_device[i], n_square * sizeof(double), hipMemcpyDeviceToHost);
end = clock();
printf("shared:%ld\n", end - start);
/*sprintf(filename_write, "result_shared.txt");
file_write = fopen(filename_write, "w");
print_field(file_write, result_shared_host, n_host, l_host);
fclose(file_write);*/
//check answers-----------------------------------------------------------------
printf("answers\n");
printf("global:%f\n", check_residue(result_host, result_global_host, n_host));
printf("shared:%f\n", check_residue(result_host, result_shared_host, n_host));
//finalize----------------------------------------------------------------------
hipHostFree(field_host[0]);
hipHostFree(field_host[1]);
hipHostFree(result_global_host);
hipHostFree(result_shared_host);
hipFree(field_device[0]);
hipFree(field_device[1]);
free(result_host);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
/* square root of number of threads in a block (the number of threads in a block is NT^2) */
#define NT 32
/* length of the target domain */
#define L 10.0
/* number of division for the discretization of the target domain */
#define N 256
/* dimensionless time step size (theta = D * dt / dx^2) */
#define THETA 0.1
/* number of iterations */
#define M 2000
/* constants on a GPU */
__device__ __constant__ int n;
__device__ __constant__ double theta;
//GPU functions-----------------------------------------------------------------
__global__ void diffusion_global(double *field_device, double *field_device_new) {
int i_global;
int j_global;
int i_left, i_right;
int j_top, j_bottom;
i_global = blockDim.x * blockIdx.x + threadIdx.x;
if(i_global < n) {
i_right = (i_global + 1) % n;
i_left = (i_global - 1 + n) % n;
for(j_global = threadIdx.y; j_global < n; j_global += NT) {
j_top = (j_global + 1) % n;
j_bottom = (j_global - 1 + n) % n;
field_device_new[i_global * n + j_global] = field_device[i_global * n + j_global]
+ theta * (field_device[i_right * n + j_global] + field_device[i_left * n + j_global]
+ field_device[i_global * n + j_top] + field_device[i_global * n + j_bottom]
- 4.0 * field_device[i_global * n + j_global]);
}
}
}
__global__ void diffusion_shared(double *field_device, double *field_device_new) {
int i_global;
int j_global;
int i_shared;
int j_shared;
int i_left, i_right;
int j_top, j_bottom;
double field_register;
__shared__ double field_shared[(NT + 2) * (NT + 2)];
i_global = blockDim.x * blockIdx.x + threadIdx.x;
i_shared = threadIdx.x + 1;
j_shared = threadIdx.y + 1;
if(i_global < n) {
for(j_global = threadIdx.y; j_global < n; j_global += NT) {
//copy field from global to shared----------------------
field_register = field_device[i_global * n + j_global];
field_shared[i_shared * (NT + 2) + j_shared] = field_register;
if(i_shared == 1) {
i_left = (i_global - 1 + n) % n;
field_shared[0 * (NT + 2) + j_shared] = field_device[i_left * n + j_global];
} else if(i_shared == NT) {
i_right = (i_global + 1) % n;
field_shared[(NT + 1) * (NT + 2) + j_shared] = field_device[i_right * n + j_global];
}
if(j_shared == 1) {
j_bottom = (j_global - 1 + n) % n;
field_shared[i_shared * (NT + 2) + 0] = field_device[i_global * n + j_bottom];
} else if(j_shared == NT) {
j_top = (j_global + 1) % n;
field_shared[i_shared * (NT + 2) + (NT + 1)] = field_device[i_global * n + j_top];
}
__syncthreads();
//calculate field evolution-----------------------------
field_device_new[i_global * n + j_global] = field_register
+ theta * (field_shared[(i_shared + 1) * (NT + 2) + j_shared] + field_shared[(i_shared - 1) * (NT + 2) + j_shared]
+ field_shared[i_shared * (NT + 2) + (j_shared + 1)] + field_shared[i_shared * (NT + 2) + (j_shared - 1)]
- 4.0 * field_register);
}
}
}
//Host functions----------------------------------------------------------------
void init_field(double *field_host, int n_host, int l_host) {
int i;
int j;
double x;
double y;
double dx = l_host / (double)n_host;
double dy = l_host / (double)n_host;
double midst = l_host * 0.5;
for(i = 0; i < n_host; i += 1) {
x = (double)i * dx;
for(j = 0; j < n_host; j += 1) {
y = (double)j * dy;
if((x > midst && y > midst) || (x < midst && y < midst)) {
field_host[n_host * j + i] = 1.0;
} else {
field_host[n_host * j + i] = 0.0;
}
}
}
}
void flip_ij(int *i, int *j) {
int i_temp;
i_temp = *i;
*i = *j;
*j = i_temp;
}
void print_field(FILE *file_write, double *field, int n, double l) {
int i;
int j;
double x;
double y;
double d = l/(double)n;
for(i = 0; i < N; i += 1) {
y = (double)j * d;
for(j = 0; j < N; j += 1) {
x = (double)i * d;
fprintf(file_write, "%f %f %f\n", x, y, field[i * n + j]);
}
}
}
void diffusion_host(double *field_host, double *field_host_new, int n_host, double theta_host) {
int i;
int j;
int i_right, i_left;
int j_top, j_bottom;
for(i = 0; i < n_host; i += 1) {
i_right = (i + 1) % n_host;
i_left = (i - 1 + n_host) % n_host;
for(j = 0; j < n_host; j += 1) {
j_top = (j + 1) % n_host;
j_bottom = (j - 1 + n_host) % n_host;
field_host_new[i * n_host + j] = field_host[i * n_host + j]
+ theta_host * (field_host[i_right * n_host + j] + field_host[i_left * n_host + j]
+ field_host[i * n_host + j_top] + field_host[i * n_host + j_bottom]
- 4.0 * field_host[i * n_host + j]);
}
}
}
double check_residue(double *field_host, double *field_device, int n_host) {
int i;
double residue = 0.0;
for(i = 0; i < n_host * n_host; i += 1) {
residue += (field_host[i] - field_device[i]) * (field_host[i] - field_device[i]);;
}
return residue;
}
int main(void) {
//delcare variavles-------------------------------------------------------------
int i;
int j;
int k;
int n_host;
int n_square;
int iteration;
int n_blocks;
double l_host;
double theta_host;
dim3 dim_threads;
double *field_host[2];
double *field_device[2];
double *result_host;
double *result_global_host;
double *result_shared_host;
FILE *file_write;
char filename_write[256];
clock_t start, end;
//initialize--------------------------------------------------------------------
//set variables---------------------------------------------------------
n_host = N;
n_square = N * N;
l_host = L;
theta_host = THETA;
dim_threads.x = NT;
dim_threads.y = NT;
dim_threads.z = 1;
n_blocks = (int)(ceil((double)n_host / NT));
iteration = M;
//allocate memories-----------------------------------------------------
hipMemcpyToSymbol(HIP_SYMBOL(n), &n_host, sizeof(int), 0, hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(theta), &theta_host, sizeof(double), 0, hipMemcpyHostToDevice);
hipHostAlloc((void **)&field_host[0], n_square * sizeof(double), hipHostMallocMapped);
hipHostAlloc((void **)&field_host[1], n_square * sizeof(double), hipHostMallocMapped);
hipHostAlloc((void **)&result_global_host, n_square * sizeof(double), hipHostMallocMapped);
hipHostAlloc((void **)&result_shared_host, n_square * sizeof(double), hipHostMallocMapped);
hipMalloc((void **)&field_device[0], n_square * sizeof(double));
hipMalloc((void **)&field_device[1], n_square * sizeof(double));
result_host = (double *)malloc(n_square * sizeof(double));
//calculate on CPU--------------------------------------------------------------
//initialize field------------------------------------------------------
init_field(field_host[0], n_host, l_host);
start = clock();
//iteration-------------------------------------------------------------
i = 0;
j = 1;
for(k = 0; k < iteration; k += 1) {
diffusion_host(field_host[i], field_host[j], n_host, theta_host);
flip_ij(&i, &j);
}
//save and print out----------------------------------------------------
memcpy(result_host, field_host[i], n_square * sizeof(double));
end = clock();
printf("host:%ld\n", end - start);
/*sprintf(filename_write, "result_host.txt");
file_write = fopen(filename_write, "w");
print_field(file_write, result_host, n_host, l_host);
fclose(file_write);*/
//calculate using only global memory--------------------------------------------
//initialize field------------------------------------------------------
init_field(field_host[0], n_host, l_host);
start = clock();
hipMemcpy(field_device[0], field_host[0], n_square * sizeof(double), hipMemcpyHostToDevice);
//iteration-------------------------------------------------------------
i = 0;
j = 1;
for(k = 0; k < iteration; k += 1) {
diffusion_global<<<n_blocks, dim_threads>>>(field_device[i], field_device[j]);
hipDeviceSynchronize();
flip_ij(&i, &j);
}
//copy to host and print out--------------------------------------------
hipMemcpy(result_global_host, field_device[i], n_square * sizeof(double), hipMemcpyDeviceToHost);
end = clock();
printf("global:%ld\n", end - start);
/*sprintf(filename_write, "result_global.txt");
file_write = fopen(filename_write, "w");
print_field(file_write, result_global_host, n_host, l_host);
fclose(file_write);*/
//calculate using shared memory-------------------------------------------------
//initialize field------------------------------------------------------
init_field(field_host[0], n_host, l_host);
start = clock();
hipMemcpy(field_device[0], field_host[0], n_square * sizeof(double), hipMemcpyHostToDevice);
//iteration-------------------------------------------------------------
i = 0;
j = 1;
for(k = 0; k < iteration; k += 1) {
diffusion_shared<<<n_blocks, dim_threads>>>(field_device[i], field_device[j]);
hipDeviceSynchronize();
flip_ij(&i, &j);
}
//copy to host and print out--------------------------------------------
hipMemcpy(result_shared_host, field_device[i], n_square * sizeof(double), hipMemcpyDeviceToHost);
end = clock();
printf("shared:%ld\n", end - start);
/*sprintf(filename_write, "result_shared.txt");
file_write = fopen(filename_write, "w");
print_field(file_write, result_shared_host, n_host, l_host);
fclose(file_write);*/
//check answers-----------------------------------------------------------------
printf("answers\n");
printf("global:%f\n", check_residue(result_host, result_global_host, n_host));
printf("shared:%f\n", check_residue(result_host, result_shared_host, n_host));
//finalize----------------------------------------------------------------------
hipHostFree(field_host[0]);
hipHostFree(field_host[1]);
hipHostFree(result_global_host);
hipHostFree(result_shared_host);
hipFree(field_device[0]);
hipFree(field_device[1]);
free(result_host);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16diffusion_globalPdS_
.globl _Z16diffusion_globalPdS_
.p2align 8
.type _Z16diffusion_globalPdS_,@function
_Z16diffusion_globalPdS_:
s_load_b32 s4, s[0:1], 0x1c
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, n@rel32@lo+4
s_addc_u32 s3, s3, n@rel32@hi+12
v_and_b32_e32 v3, 0x3ff, v0
s_load_b32 s8, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_4
v_bfe_u32 v0, v0, 10, 10
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s8, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_4
s_ashr_i32 s2, s8, 31
s_add_i32 s9, s8, -1
s_add_i32 s3, s8, s2
v_add_nc_u32_e32 v5, 1, v1
s_xor_b32 s4, s3, s2
v_add_nc_u32_e32 v3, s9, v1
v_cvt_f32_u32_e32 v2, s4
s_sub_i32 s2, 0, s4
v_ashrrev_i32_e32 v7, 31, v5
v_mul_lo_u32 v1, v1, s8
v_ashrrev_i32_e32 v6, 31, v3
v_rcp_iflag_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, v5, v7
v_add_nc_u32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_xor_b32_e32 v3, v3, v6
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v4, s2, v2
s_ashr_i32 s2, s8, 31
s_add_i32 s3, s8, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s10, s3, s2
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, theta@rel32@lo+4
s_addc_u32 s3, s3, theta@rel32@hi+12
v_cvt_f32_u32_e32 v8, s10
v_mul_hi_u32 v4, v2, v4
s_sub_i32 s5, 0, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v2, v4
v_xor_b32_e32 v4, v5, v7
v_mul_hi_u32 v5, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v5, s4
v_sub_nc_u32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v3
v_cmp_le_u32_e32 vcc_lo, s4, v3
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
v_mul_hi_u32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v3
v_mul_lo_u32 v2, v2, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v4, v2
v_rcp_iflag_f32_e32 v4, v8
v_subrev_nc_u32_e32 v8, s4, v2
v_cmp_le_u32_e32 vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v8, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s4, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
v_subrev_nc_u32_e32 v8, s4, v2
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_u32_f32_e32 v4, v4
v_xor_b32_e32 v3, v3, v6
v_cndmask_b32_e32 v2, v2, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_mul_lo_u32 v5, s5, v4
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[2:3], 0x0
s_mov_b32 s1, 0
v_sub_nc_u32_e32 v3, v3, v6
v_xor_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v4, v5
v_sub_nc_u32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, v3, s8
v_mul_lo_u32 v2, v2, s8
s_delay_alu instid0(VALU_DEP_4)
v_add_nc_u32_e32 v4, v4, v5
.LBB0_3:
v_add_nc_u32_e32 v11, s9, v0
v_cmp_ne_u32_e32 vcc_lo, s9, v0
v_add_nc_u32_e32 v5, v1, v0
v_add_nc_u32_e32 v7, v2, v0
v_add_nc_u32_e32 v9, v3, v0
v_ashrrev_i32_e32 v15, 31, v11
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v10, 31, v9
v_add_nc_u32_e32 v14, v11, v15
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[5:6], 3, v[5:6]
v_lshlrev_b64 v[7:8], 3, v[7:8]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[9:10], 3, v[9:10]
v_xor_b32_e32 v16, v14, v15
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, s0, s4, v5
v_mul_hi_u32 v14, v16, v4
v_add_co_ci_u32_e64 v12, s0, s5, v6, s0
v_add_co_u32 v7, s0, s4, v7
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v8, s0, s5, v8, s0
v_add_co_u32 v9, s0, s4, v9
v_mul_lo_u32 v17, v14, s10
v_add_co_ci_u32_e64 v10, s0, s5, v10, s0
s_clause 0x2
global_load_b64 v[11:12], v[11:12], off
global_load_b64 v[7:8], v[7:8], off
global_load_b64 v[9:10], v[9:10], off
v_sub_nc_u32_e32 v16, v16, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v17, s10, v16
v_cmp_le_u32_e64 s0, s10, v16
v_cndmask_b32_e64 v16, v16, v17, s0
v_add_co_u32 v5, s0, s6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v6, s0, s7, v6, s0
v_subrev_nc_u32_e32 v17, s10, v16
v_add_nc_u32_e32 v13, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v13, 0, v13 :: v_dual_add_nc_u32 v0, 32, v0
v_add_nc_u32_e32 v13, v13, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[13:14], 3, v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v13, vcc_lo, s4, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s10, v16
global_load_b64 v[13:14], v[13:14], off
v_cndmask_b32_e32 v16, v16, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v16, v16, v15
v_sub_nc_u32_e32 v15, v16, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v15, v15, v1
v_ashrrev_i32_e32 v16, 31, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[15:16], 3, v[15:16]
v_add_co_u32 v15, vcc_lo, s4, v15
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v16, vcc_lo, s5, v16, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s8, v0
global_load_b64 v[15:16], v[15:16], off
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(2)
v_add_f64 v[7:8], v[7:8], v[9:10]
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[7:8], v[13:14]
s_waitcnt vmcnt(0)
v_add_f64 v[7:8], v[7:8], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[11:12], -4.0, v[7:8]
v_fma_f64 v[7:8], s[2:3], v[7:8], v[11:12]
global_store_b64 v[5:6], v[7:8], off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16diffusion_globalPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16diffusion_globalPdS_, .Lfunc_end0-_Z16diffusion_globalPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16diffusion_sharedPdS_
.globl _Z16diffusion_sharedPdS_
.p2align 8
.type _Z16diffusion_sharedPdS_,@function
_Z16diffusion_sharedPdS_:
s_load_b32 s4, s[0:1], 0x1c
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, n@rel32@lo+4
s_addc_u32 s3, s3, n@rel32@hi+12
v_and_b32_e32 v3, 0x3ff, v0
s_load_b32 s10, s[2:3], 0x0
v_bfe_u32 v6, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v0, v1, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v0
s_cbranch_execz .LBB1_11
v_add_nc_u32_e32 v0, 1, v3
v_add_nc_u32_e32 v4, 1, v6
v_mul_lo_u32 v7, v1, s10
s_load_b128 s[4:7], s[0:1], 0x0
v_lshl_add_u32 v5, v6, 3, 0x2318
v_mul_u32_u24_e32 v13, 34, v0
v_cmp_eq_u32_e64 s1, 32, v0
v_lshlrev_b32_e32 v0, 3, v4
v_cmp_eq_u32_e64 s2, 0, v3
s_add_i32 s3, s10, -1
v_add_nc_u32_e32 v2, v6, v7
v_mul_u32_u24_e32 v12, 34, v3
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, theta@rel32@lo+4
s_addc_u32 s9, s9, theta@rel32@hi+12
v_cndmask_b32_e64 v11, v5, v0, s2
v_cndmask_b32_e64 v0, 1, s3, s2
v_ashrrev_i32_e32 v3, 31, v2
v_cmp_eq_u32_e64 s0, 32, v4
v_add_lshl_u32 v9, v13, v4, 3
v_add_lshl_u32 v12, v12, v4, 3
s_load_b64 s[8:9], s[8:9], 0x0
v_add_nc_u32_e32 v4, v0, v1
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_lshlrev_b32_e32 v8, 3, v13
v_add_lshl_u32 v13, v13, v6, 3
v_cmp_ne_u32_e32 vcc_lo, 0, v6
v_ashrrev_i32_e32 v17, 31, v4
v_add_nc_u32_e32 v14, 0x220, v12
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, s3, s6, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, s3, s7, v3, s3
v_add_nc_u32_e32 v4, v4, v17
v_add_co_u32 v2, s3, s4, v2
v_add_nc_u32_e32 v10, 0x108, v8
v_dual_mov_b32 v16, 0 :: v_dual_add_nc_u32 v15, 16, v13
v_add_co_ci_u32_e64 v3, s3, s5, v3, s3
v_xor_b32_e32 v18, v4, v17
s_mov_b32 s3, 0
s_or_b32 s6, s2, s1
s_branch .LBB1_3
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b64 v[19:20], v14
ds_load_b64 v[21:22], v12
ds_load_b64 v[23:24], v15
ds_load_b64 v[25:26], v13
v_add_co_u32 v6, s1, v6, 32
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v16, s1, 0, v16, s1
v_cmp_le_i32_e64 s1, s10, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_or_b32 s3, s1, s3
s_waitcnt lgkmcnt(2)
v_add_f64 v[19:20], v[19:20], v[21:22]
s_waitcnt lgkmcnt(1)
v_add_f64 v[19:20], v[19:20], v[23:24]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[19:20], v[19:20], v[25:26]
v_fma_f64 v[19:20], v[4:5], -4.0, v[19:20]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], s[8:9], v[19:20], v[4:5]
global_store_b64 v[0:1], v[4:5], off
v_add_co_u32 v0, s2, v0, 0x100
v_add_co_ci_u32_e64 v1, s2, 0, v1, s2
v_add_co_u32 v2, s2, v2, 0x100
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s2, 0, v3, s2
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB1_11
.LBB1_3:
global_load_b64 v[4:5], v[2:3], off
s_waitcnt vmcnt(0)
ds_store_b64 v9, v[4:5]
s_and_saveexec_b32 s2, s6
s_cbranch_execz .LBB1_5
s_ashr_i32 s1, s10, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s10, s1
s_xor_b32 s7, s7, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v19, s7
s_sub_i32 s1, 0, s7
v_rcp_iflag_f32_e32 v19, v19
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v19, 0x4f7ffffe, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v19, v19
v_mul_lo_u32 v20, s1, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v20, v19, v20
v_add_nc_u32_e32 v19, v19, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v19, v18, v19
v_mul_lo_u32 v19, v19, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v19, v18, v19
v_subrev_nc_u32_e32 v20, s7, v19
v_cmp_le_u32_e64 s1, s7, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v19, v19, v20, s1
v_subrev_nc_u32_e32 v20, s7, v19
v_cmp_le_u32_e64 s1, s7, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v19, v19, v20, s1
v_xor_b32_e32 v19, v19, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v19, v19, v17
v_mul_lo_u32 v19, v19, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v20, 31, v19
v_add_co_u32 v19, s1, v6, v19
v_add_co_ci_u32_e64 v20, s1, v16, v20, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[19:20], 3, v[19:20]
v_add_co_u32 v19, s1, s4, v19
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v20, s1, s5, v20, s1
global_load_b64 v[19:20], v[19:20], off
s_waitcnt vmcnt(0)
ds_store_b64 v11, v[19:20]
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s1, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s1
s_cbranch_execz .LBB1_9
s_and_saveexec_b32 s7, s0
s_cbranch_execz .LBB1_8
s_ashr_i32 s1, s10, 31
v_add_nc_u32_e32 v21, 1, v6
s_add_i32 s11, s10, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s11, s11, s1
v_cvt_f32_u32_e32 v19, s11
s_sub_i32 s1, 0, s11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v19, v19
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v19, 0x4f7ffffe, v19
v_cvt_u32_f32_e32 v19, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v20, s1, v19
v_mul_hi_u32 v20, v19, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v19, v19, v20
v_mul_hi_u32 v19, v21, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v19, v19, s11
v_sub_nc_u32_e32 v19, v21, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v20, s11, v19
v_cmp_le_u32_e64 s1, s11, v19
v_cndmask_b32_e64 v19, v19, v20, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v20, s11, v19
v_cmp_le_u32_e64 s1, s11, v19
v_cndmask_b32_e64 v19, v19, v20, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v19, v19, v7
v_ashrrev_i32_e32 v20, 31, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[19:20], 3, v[19:20]
v_add_co_u32 v19, s1, s4, v19
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v20, s1, s5, v20, s1
global_load_b64 v[19:20], v[19:20], off
s_waitcnt vmcnt(0)
ds_store_b64 v10, v[19:20]
.LBB1_8:
s_or_b32 exec_lo, exec_lo, s7
.LBB1_9:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB1_2
s_ashr_i32 s1, s10, 31
v_add3_u32 v21, s10, v6, -1
s_add_i32 s7, s10, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s7, s7, s1
v_ashrrev_i32_e32 v22, 31, v21
v_cvt_f32_u32_e32 v19, s7
s_sub_i32 s1, 0, s7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v21, v21, v22
v_rcp_iflag_f32_e32 v19, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_xor_b32_e32 v21, v21, v22
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v19, 0x4f7ffffe, v19
v_cvt_u32_f32_e32 v19, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v20, s1, v19
v_mul_hi_u32 v20, v19, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v19, v19, v20
v_mul_hi_u32 v19, v21, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v19, v19, s7
v_sub_nc_u32_e32 v19, v21, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v20, s7, v19
v_cmp_le_u32_e64 s1, s7, v19
v_cndmask_b32_e64 v19, v19, v20, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v20, s7, v19
v_cmp_le_u32_e64 s1, s7, v19
v_cndmask_b32_e64 v19, v19, v20, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v19, v19, v22
v_sub_nc_u32_e32 v19, v19, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v19, v19, v7
v_ashrrev_i32_e32 v20, 31, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[19:20], 3, v[19:20]
v_add_co_u32 v19, s1, s4, v19
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v20, s1, s5, v20, s1
global_load_b64 v[19:20], v[19:20], off
s_waitcnt vmcnt(0)
ds_store_b64 v8, v[19:20]
s_branch .LBB1_2
.LBB1_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16diffusion_sharedPdS_
.amdhsa_group_segment_fixed_size 9248
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 27
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z16diffusion_sharedPdS_, .Lfunc_end1-_Z16diffusion_sharedPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected n
.type n,@object
.section .bss,"aw",@nobits
.globl n
.p2align 2, 0x0
n:
.long 0
.size n, 4
.protected theta
.type theta,@object
.globl theta
.p2align 3, 0x0
theta:
.quad 0x0000000000000000
.size theta, 8
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym n
.addrsig_sym theta
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16diffusion_globalPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16diffusion_globalPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 9248
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16diffusion_sharedPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16diffusion_sharedPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 27
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
/* square root of number of threads in a block (the number of threads in a block is NT^2) */
#define NT 32
/* length of the target domain */
#define L 10.0
/* number of division for the discretization of the target domain */
#define N 256
/* dimensionless time step size (theta = D * dt / dx^2) */
#define THETA 0.1
/* number of iterations */
#define M 2000
/* constants on a GPU */
__device__ __constant__ int n;
__device__ __constant__ double theta;
//GPU functions-----------------------------------------------------------------
__global__ void diffusion_global(double *field_device, double *field_device_new) {
int i_global;
int j_global;
int i_left, i_right;
int j_top, j_bottom;
i_global = blockDim.x * blockIdx.x + threadIdx.x;
if(i_global < n) {
i_right = (i_global + 1) % n;
i_left = (i_global - 1 + n) % n;
for(j_global = threadIdx.y; j_global < n; j_global += NT) {
j_top = (j_global + 1) % n;
j_bottom = (j_global - 1 + n) % n;
field_device_new[i_global * n + j_global] = field_device[i_global * n + j_global]
+ theta * (field_device[i_right * n + j_global] + field_device[i_left * n + j_global]
+ field_device[i_global * n + j_top] + field_device[i_global * n + j_bottom]
- 4.0 * field_device[i_global * n + j_global]);
}
}
}
__global__ void diffusion_shared(double *field_device, double *field_device_new) {
int i_global;
int j_global;
int i_shared;
int j_shared;
int i_left, i_right;
int j_top, j_bottom;
double field_register;
__shared__ double field_shared[(NT + 2) * (NT + 2)];
i_global = blockDim.x * blockIdx.x + threadIdx.x;
i_shared = threadIdx.x + 1;
j_shared = threadIdx.y + 1;
if(i_global < n) {
for(j_global = threadIdx.y; j_global < n; j_global += NT) {
//copy field from global to shared----------------------
field_register = field_device[i_global * n + j_global];
field_shared[i_shared * (NT + 2) + j_shared] = field_register;
if(i_shared == 1) {
i_left = (i_global - 1 + n) % n;
field_shared[0 * (NT + 2) + j_shared] = field_device[i_left * n + j_global];
} else if(i_shared == NT) {
i_right = (i_global + 1) % n;
field_shared[(NT + 1) * (NT + 2) + j_shared] = field_device[i_right * n + j_global];
}
if(j_shared == 1) {
j_bottom = (j_global - 1 + n) % n;
field_shared[i_shared * (NT + 2) + 0] = field_device[i_global * n + j_bottom];
} else if(j_shared == NT) {
j_top = (j_global + 1) % n;
field_shared[i_shared * (NT + 2) + (NT + 1)] = field_device[i_global * n + j_top];
}
__syncthreads();
//calculate field evolution-----------------------------
field_device_new[i_global * n + j_global] = field_register
+ theta * (field_shared[(i_shared + 1) * (NT + 2) + j_shared] + field_shared[(i_shared - 1) * (NT + 2) + j_shared]
+ field_shared[i_shared * (NT + 2) + (j_shared + 1)] + field_shared[i_shared * (NT + 2) + (j_shared - 1)]
- 4.0 * field_register);
}
}
}
//Host functions----------------------------------------------------------------
void init_field(double *field_host, int n_host, int l_host) {
int i;
int j;
double x;
double y;
double dx = l_host / (double)n_host;
double dy = l_host / (double)n_host;
double midst = l_host * 0.5;
for(i = 0; i < n_host; i += 1) {
x = (double)i * dx;
for(j = 0; j < n_host; j += 1) {
y = (double)j * dy;
if((x > midst && y > midst) || (x < midst && y < midst)) {
field_host[n_host * j + i] = 1.0;
} else {
field_host[n_host * j + i] = 0.0;
}
}
}
}
void flip_ij(int *i, int *j) {
int i_temp;
i_temp = *i;
*i = *j;
*j = i_temp;
}
void print_field(FILE *file_write, double *field, int n, double l) {
int i;
int j;
double x;
double y;
double d = l/(double)n;
for(i = 0; i < N; i += 1) {
y = (double)j * d;
for(j = 0; j < N; j += 1) {
x = (double)i * d;
fprintf(file_write, "%f %f %f\n", x, y, field[i * n + j]);
}
}
}
void diffusion_host(double *field_host, double *field_host_new, int n_host, double theta_host) {
int i;
int j;
int i_right, i_left;
int j_top, j_bottom;
for(i = 0; i < n_host; i += 1) {
i_right = (i + 1) % n_host;
i_left = (i - 1 + n_host) % n_host;
for(j = 0; j < n_host; j += 1) {
j_top = (j + 1) % n_host;
j_bottom = (j - 1 + n_host) % n_host;
field_host_new[i * n_host + j] = field_host[i * n_host + j]
+ theta_host * (field_host[i_right * n_host + j] + field_host[i_left * n_host + j]
+ field_host[i * n_host + j_top] + field_host[i * n_host + j_bottom]
- 4.0 * field_host[i * n_host + j]);
}
}
}
double check_residue(double *field_host, double *field_device, int n_host) {
int i;
double residue = 0.0;
for(i = 0; i < n_host * n_host; i += 1) {
residue += (field_host[i] - field_device[i]) * (field_host[i] - field_device[i]);;
}
return residue;
}
int main(void) {
//delcare variavles-------------------------------------------------------------
int i;
int j;
int k;
int n_host;
int n_square;
int iteration;
int n_blocks;
double l_host;
double theta_host;
dim3 dim_threads;
double *field_host[2];
double *field_device[2];
double *result_host;
double *result_global_host;
double *result_shared_host;
FILE *file_write;
char filename_write[256];
clock_t start, end;
//initialize--------------------------------------------------------------------
//set variables---------------------------------------------------------
n_host = N;
n_square = N * N;
l_host = L;
theta_host = THETA;
dim_threads.x = NT;
dim_threads.y = NT;
dim_threads.z = 1;
n_blocks = (int)(ceil((double)n_host / NT));
iteration = M;
//allocate memories-----------------------------------------------------
hipMemcpyToSymbol(HIP_SYMBOL(n), &n_host, sizeof(int), 0, hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(theta), &theta_host, sizeof(double), 0, hipMemcpyHostToDevice);
hipHostAlloc((void **)&field_host[0], n_square * sizeof(double), hipHostMallocMapped);
hipHostAlloc((void **)&field_host[1], n_square * sizeof(double), hipHostMallocMapped);
hipHostAlloc((void **)&result_global_host, n_square * sizeof(double), hipHostMallocMapped);
hipHostAlloc((void **)&result_shared_host, n_square * sizeof(double), hipHostMallocMapped);
hipMalloc((void **)&field_device[0], n_square * sizeof(double));
hipMalloc((void **)&field_device[1], n_square * sizeof(double));
result_host = (double *)malloc(n_square * sizeof(double));
//calculate on CPU--------------------------------------------------------------
//initialize field------------------------------------------------------
init_field(field_host[0], n_host, l_host);
start = clock();
//iteration-------------------------------------------------------------
i = 0;
j = 1;
for(k = 0; k < iteration; k += 1) {
diffusion_host(field_host[i], field_host[j], n_host, theta_host);
flip_ij(&i, &j);
}
//save and print out----------------------------------------------------
memcpy(result_host, field_host[i], n_square * sizeof(double));
end = clock();
printf("host:%ld\n", end - start);
/*sprintf(filename_write, "result_host.txt");
file_write = fopen(filename_write, "w");
print_field(file_write, result_host, n_host, l_host);
fclose(file_write);*/
//calculate using only global memory--------------------------------------------
//initialize field------------------------------------------------------
init_field(field_host[0], n_host, l_host);
start = clock();
hipMemcpy(field_device[0], field_host[0], n_square * sizeof(double), hipMemcpyHostToDevice);
//iteration-------------------------------------------------------------
i = 0;
j = 1;
for(k = 0; k < iteration; k += 1) {
diffusion_global<<<n_blocks, dim_threads>>>(field_device[i], field_device[j]);
hipDeviceSynchronize();
flip_ij(&i, &j);
}
//copy to host and print out--------------------------------------------
hipMemcpy(result_global_host, field_device[i], n_square * sizeof(double), hipMemcpyDeviceToHost);
end = clock();
printf("global:%ld\n", end - start);
/*sprintf(filename_write, "result_global.txt");
file_write = fopen(filename_write, "w");
print_field(file_write, result_global_host, n_host, l_host);
fclose(file_write);*/
//calculate using shared memory-------------------------------------------------
//initialize field------------------------------------------------------
init_field(field_host[0], n_host, l_host);
start = clock();
hipMemcpy(field_device[0], field_host[0], n_square * sizeof(double), hipMemcpyHostToDevice);
//iteration-------------------------------------------------------------
i = 0;
j = 1;
for(k = 0; k < iteration; k += 1) {
diffusion_shared<<<n_blocks, dim_threads>>>(field_device[i], field_device[j]);
hipDeviceSynchronize();
flip_ij(&i, &j);
}
//copy to host and print out--------------------------------------------
hipMemcpy(result_shared_host, field_device[i], n_square * sizeof(double), hipMemcpyDeviceToHost);
end = clock();
printf("shared:%ld\n", end - start);
/*sprintf(filename_write, "result_shared.txt");
file_write = fopen(filename_write, "w");
print_field(file_write, result_shared_host, n_host, l_host);
fclose(file_write);*/
//check answers-----------------------------------------------------------------
printf("answers\n");
printf("global:%f\n", check_residue(result_host, result_global_host, n_host));
printf("shared:%f\n", check_residue(result_host, result_shared_host, n_host));
//finalize----------------------------------------------------------------------
hipHostFree(field_host[0]);
hipHostFree(field_host[1]);
hipHostFree(result_global_host);
hipHostFree(result_shared_host);
hipFree(field_device[0]);
hipFree(field_device[1]);
free(result_host);
return 0;
} | .text
.file "diffusion_me.hip"
.globl _Z31__device_stub__diffusion_globalPdS_ # -- Begin function _Z31__device_stub__diffusion_globalPdS_
.p2align 4, 0x90
.type _Z31__device_stub__diffusion_globalPdS_,@function
_Z31__device_stub__diffusion_globalPdS_: # @_Z31__device_stub__diffusion_globalPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16diffusion_globalPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z31__device_stub__diffusion_globalPdS_, .Lfunc_end0-_Z31__device_stub__diffusion_globalPdS_
.cfi_endproc
# -- End function
.globl _Z31__device_stub__diffusion_sharedPdS_ # -- Begin function _Z31__device_stub__diffusion_sharedPdS_
.p2align 4, 0x90
.type _Z31__device_stub__diffusion_sharedPdS_,@function
_Z31__device_stub__diffusion_sharedPdS_: # @_Z31__device_stub__diffusion_sharedPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16diffusion_sharedPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z31__device_stub__diffusion_sharedPdS_, .Lfunc_end1-_Z31__device_stub__diffusion_sharedPdS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z10init_fieldPdii
.LCPI2_0:
.quad 0x3fe0000000000000 # double 0.5
.LCPI2_1:
.quad 0x3ff0000000000000 # double 1
.text
.globl _Z10init_fieldPdii
.p2align 4, 0x90
.type _Z10init_fieldPdii,@function
_Z10init_fieldPdii: # @_Z10init_fieldPdii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_5
# %bb.1: # %.lr.ph37
cvtsi2sd %edx, %xmm0
cvtsi2sd %esi, %xmm2
movapd %xmm0, %xmm1
divsd %xmm2, %xmm1
mulsd .LCPI2_0(%rip), %xmm0
movl %esi, %eax
leaq (,%rax,8), %rcx
xorl %edx, %edx
movsd .LCPI2_1(%rip), %xmm2 # xmm2 = mem[0],zero
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
xorps %xmm3, %xmm3
cvtsi2sd %edx, %xmm3
mulsd %xmm1, %xmm3
movapd %xmm0, %xmm4
cmpltsd %xmm3, %xmm4
cmpltsd %xmm0, %xmm3
movq %rdi, %rsi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm5, %xmm5
cvtsi2sd %r8d, %xmm5
mulsd %xmm1, %xmm5
movapd %xmm0, %xmm6
cmpltsd %xmm5, %xmm6
cmpltsd %xmm0, %xmm5
andpd %xmm2, %xmm5
andpd %xmm3, %xmm5
movapd %xmm4, %xmm7
andnpd %xmm5, %xmm7
movapd %xmm6, %xmm8
andnpd %xmm5, %xmm8
andpd %xmm2, %xmm6
orpd %xmm8, %xmm6
andpd %xmm4, %xmm6
orpd %xmm7, %xmm6
movlpd %xmm6, (%rsi)
incq %r8
addq %rcx, %rsi
cmpq %r8, %rax
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %rdx
addq $8, %rdi
cmpq %rax, %rdx
jne .LBB2_2
.LBB2_5: # %._crit_edge38
retq
.Lfunc_end2:
.size _Z10init_fieldPdii, .Lfunc_end2-_Z10init_fieldPdii
.cfi_endproc
# -- End function
.globl _Z7flip_ijPiS_ # -- Begin function _Z7flip_ijPiS_
.p2align 4, 0x90
.type _Z7flip_ijPiS_,@function
_Z7flip_ijPiS_: # @_Z7flip_ijPiS_
.cfi_startproc
# %bb.0:
movl (%rdi), %eax
movl (%rsi), %ecx
movl %ecx, (%rdi)
movl %eax, (%rsi)
retq
.Lfunc_end3:
.size _Z7flip_ijPiS_, .Lfunc_end3-_Z7flip_ijPiS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z11print_fieldP8_IO_FILEPdid
.LCPI4_0:
.quad 0x4070000000000000 # double 256
.text
.globl _Z11print_fieldP8_IO_FILEPdid
.p2align 4, 0x90
.type _Z11print_fieldP8_IO_FILEPdid,@function
_Z11print_fieldP8_IO_FILEPdid: # @_Z11print_fieldP8_IO_FILEPdid
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
cvtsi2sd %edx, %xmm1
divsd %xmm1, %xmm0
movslq %edx, %r15
movsd .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero
movsd %xmm0, 8(%rsp) # 8-byte Spill
mulsd %xmm0, %xmm1
shlq $3, %r15
xorl %r12d, %r12d
movsd %xmm1, 16(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB4_1: # =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
xorps %xmm0, %xmm0
cvtsi2sd %r12d, %xmm0
mulsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 24(%rsp) # 8-byte Spill
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rbx,%r13,8), %xmm2 # xmm2 = mem[0],zero
movl $.L.str, %esi
movq %r14, %rdi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movb $3, %al
callq fprintf
incq %r13
cmpq $256, %r13 # imm = 0x100
jne .LBB4_2
# %bb.3: # in Loop: Header=BB4_1 Depth=1
incq %r12
addq %r15, %rbx
cmpq $256, %r12 # imm = 0x100
jne .LBB4_1
# %bb.4:
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z11print_fieldP8_IO_FILEPdid, .Lfunc_end4-_Z11print_fieldP8_IO_FILEPdid
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z14diffusion_hostPdS_id
.LCPI5_0:
.quad 0xc010000000000000 # double -4
.text
.globl _Z14diffusion_hostPdS_id
.p2align 4, 0x90
.type _Z14diffusion_hostPdS_id,@function
_Z14diffusion_hostPdS_id: # @_Z14diffusion_hostPdS_id
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB5_6
# %bb.1: # %.lr.ph48
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ecx
movl %edx, %r8d
leal -1(%rcx), %eax
movq %rax, -8(%rsp) # 8-byte Spill
leaq (,%r8,8), %rax
movq %rax, -16(%rsp) # 8-byte Spill
movq %r8, %r11
negq %r11
xorl %ebx, %ebx
movsd .LCPI5_0(%rip), %xmm1 # xmm1 = mem[0],zero
movq %rdi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_3: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB5_4 Depth 2
movq %r15, %r12
incq %r15
movq -8(%rsp), %rax # 8-byte Reload
addl %r12d, %eax
cltd
idivl %ecx
cmpq %r8, %r15
movl %r15d, %eax
cmovel %ebx, %eax
imulq %r8, %r12
imull %ecx, %eax
imull %ecx, %edx
cltq
movslq %edx, %rdx
leaq (%rdi,%rax,8), %r13
leaq (%rdi,%rdx,8), %rbp
leaq (%rdi,%r12,8), %r9
movl $1, %r10d
.p2align 4, 0x90
.LBB5_4: # Parent Loop BB5_3 Depth=1
# => This Inner Loop Header: Depth=2
leal (%r8,%r10), %eax
addl $-2, %eax
cltd
idivl %r8d
cmpq %r10, %r8
movsd -8(%r13,%r10,8), %xmm2 # xmm2 = mem[0],zero
addsd -8(%rbp,%r10,8), %xmm2
movsd -8(%r14,%r10,8), %xmm3 # xmm3 = mem[0],zero
movl %r10d, %eax
cmovel %ebx, %eax
addl %r12d, %eax
addsd (%rdi,%rax,8), %xmm2
movslq %edx, %rax
addsd (%r9,%rax,8), %xmm2
movapd %xmm3, %xmm4
mulsd %xmm1, %xmm4
addsd %xmm2, %xmm4
mulsd %xmm0, %xmm4
addsd %xmm3, %xmm4
movsd %xmm4, -8(%rsi,%r10,8)
leaq (%r11,%r10), %rax
incq %rax
incq %r10
cmpq $1, %rax
jne .LBB5_4
# %bb.2: # %.loopexit
# in Loop: Header=BB5_3 Depth=1
movq -16(%rsp), %rax # 8-byte Reload
addq %rax, %rsi
addq %rax, %r14
cmpq %r8, %r15
jne .LBB5_3
# %bb.5:
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB5_6: # %._crit_edge
retq
.Lfunc_end5:
.size _Z14diffusion_hostPdS_id, .Lfunc_end5-_Z14diffusion_hostPdS_id
.cfi_endproc
# -- End function
.globl _Z13check_residuePdS_i # -- Begin function _Z13check_residuePdS_i
.p2align 4, 0x90
.type _Z13check_residuePdS_i,@function
_Z13check_residuePdS_i: # @_Z13check_residuePdS_i
.cfi_startproc
# %bb.0:
# kill: def $edx killed $edx def $rdx
testl %edx, %edx
je .LBB6_1
# %bb.2: # %.lr.ph.preheader
imull %edx, %edx
cmpl $1, %edx
adcl $0, %edx
xorpd %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB6_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%rdi,%rax,8), %xmm1 # xmm1 = mem[0],zero
subsd (%rsi,%rax,8), %xmm1
mulsd %xmm1, %xmm1
addsd %xmm1, %xmm0
incq %rax
cmpq %rax, %rdx
jne .LBB6_3
# %bb.4: # %._crit_edge
retq
.LBB6_1:
xorps %xmm0, %xmm0
retq
.Lfunc_end6:
.size _Z13check_residuePdS_i, .Lfunc_end6-_Z13check_residuePdS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI7_0:
.quad 0x4024000000000000 # double 10
.LCPI7_1:
.quad 0x4014000000000000 # double 5
.LCPI7_2:
.quad 0x3ff0000000000000 # double 1
.LCPI7_3:
.quad 0xc010000000000000 # double -4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $256, 12(%rsp) # imm = 0x100
movabsq $4591870180066957722, %rax # imm = 0x3FB999999999999A
movq %rax, 200(%rsp)
xorl %ebx, %ebx
leaq 12(%rsp), %rsi
movl $1, %ebp
movl $n, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 200(%rsp), %rsi
movl $theta, %edi
movl $8, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 32(%rsp), %rdi
movl $524288, %esi # imm = 0x80000
movl $2, %edx
callq hipHostAlloc
leaq 40(%rsp), %rdi
movl $524288, %esi # imm = 0x80000
movl $2, %edx
callq hipHostAlloc
leaq 80(%rsp), %rdi
movl $524288, %esi # imm = 0x80000
movl $2, %edx
callq hipHostAlloc
leaq 72(%rsp), %rdi
movl $524288, %esi # imm = 0x80000
movl $2, %edx
callq hipHostAlloc
leaq 16(%rsp), %rdi
movl $524288, %esi # imm = 0x80000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $524288, %esi # imm = 0x80000
callq hipMalloc
movl $524288, %edi # imm = 0x80000
callq malloc
movq %rax, 184(%rsp) # 8-byte Spill
movl 12(%rsp), %eax
movsd .LCPI7_0(%rip), %xmm0 # xmm0 = mem[0],zero
testl %eax, %eax
jle .LBB7_5
# %bb.1: # %.lr.ph37.i
movq 32(%rsp), %rcx
cvtsi2sd %eax, %xmm1
divsd %xmm1, %xmm0
leaq (,%rax,8), %rdx
xorl %esi, %esi
movsd .LCPI7_1(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI7_2(%rip), %xmm2 # xmm2 = mem[0],zero
.p2align 4, 0x90
.LBB7_2: # %.lr.ph.i
# =>This Loop Header: Depth=1
# Child Loop BB7_3 Depth 2
xorps %xmm3, %xmm3
cvtsi2sd %esi, %xmm3
mulsd %xmm0, %xmm3
movapd %xmm1, %xmm4
cmpltsd %xmm3, %xmm4
cmpltsd %xmm1, %xmm3
movq %rcx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB7_3: # Parent Loop BB7_2 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm5, %xmm5
cvtsi2sd %r8d, %xmm5
mulsd %xmm0, %xmm5
movapd %xmm1, %xmm6
cmpltsd %xmm5, %xmm6
cmpltsd %xmm1, %xmm5
andpd %xmm2, %xmm5
andpd %xmm3, %xmm5
movapd %xmm4, %xmm7
andnpd %xmm5, %xmm7
movapd %xmm6, %xmm8
andnpd %xmm5, %xmm8
andpd %xmm2, %xmm6
orpd %xmm8, %xmm6
andpd %xmm4, %xmm6
orpd %xmm7, %xmm6
movlpd %xmm6, (%rdi)
incq %r8
addq %rdx, %rdi
cmpq %r8, %rax
jne .LBB7_3
# %bb.4: # %._crit_edge.i
# in Loop: Header=BB7_2 Depth=1
incq %rsi
addq $8, %rcx
cmpq %rax, %rsi
jne .LBB7_2
.LBB7_5: # %_Z10init_fieldPdii.exit
callq clock
movq %rax, 208(%rsp) # 8-byte Spill
movl 12(%rsp), %ecx
leal -1(%rcx), %eax
movq %rax, 56(%rsp) # 8-byte Spill
leaq (,%rcx,8), %rdi
movq %rcx, %r8
negq %r8
movsd .LCPI7_3(%rip), %xmm0 # xmm0 = mem[0],zero
xorl %edx, %edx
xorl %eax, %eax
jmp .LBB7_6
.p2align 4, 0x90
.LBB7_11: # %_Z14diffusion_hostPdS_id.exit
# in Loop: Header=BB7_6 Depth=1
movl 152(%rsp), %edx # 4-byte Reload
incl %edx
movl 156(%rsp), %eax # 4-byte Reload
movl 68(%rsp), %ebp # 4-byte Reload
cmpl $2000, %edx # imm = 0x7D0
je .LBB7_12
.LBB7_6: # =>This Loop Header: Depth=1
# Child Loop BB7_9 Depth 2
# Child Loop BB7_10 Depth 3
movl %edx, 152(%rsp) # 4-byte Spill
movl %eax, 68(%rsp) # 4-byte Spill
movl %ebp, 156(%rsp) # 4-byte Spill
movl %ebp, %eax
movq %rax, 192(%rsp) # 8-byte Spill
testl %ecx, %ecx
jle .LBB7_11
# %bb.7: # %.lr.ph.i47.preheader
# in Loop: Header=BB7_6 Depth=1
movl 68(%rsp), %eax # 4-byte Reload
movq 32(%rsp,%rax,8), %r15
movq 192(%rsp), %rax # 8-byte Reload
movq 32(%rsp,%rax,8), %r12
movsd 200(%rsp), %xmm1 # xmm1 = mem[0],zero
movq %r15, %r13
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB7_9: # %.lr.ph.i47
# Parent Loop BB7_6 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB7_10 Depth 3
movq %r10, %r14
incq %r10
movq 56(%rsp), %rax # 8-byte Reload
addl %r14d, %eax
cltd
idivl %ecx
cmpq %rcx, %r10
movl %r10d, %eax
cmovel %ebx, %eax
imulq %rcx, %r14
imull %ecx, %eax
imull %ecx, %edx
cltq
movslq %edx, %rdx
leaq (%r15,%r14,8), %rbp
leaq (%r15,%rdx,8), %r11
leaq (%r15,%rax,8), %r9
movl $1, %esi
.p2align 4, 0x90
.LBB7_10: # Parent Loop BB7_6 Depth=1
# Parent Loop BB7_9 Depth=2
# => This Inner Loop Header: Depth=3
leal (%rcx,%rsi), %eax
addl $-2, %eax
cltd
idivl %ecx
cmpq %rsi, %rcx
movsd -8(%r9,%rsi,8), %xmm2 # xmm2 = mem[0],zero
addsd -8(%r11,%rsi,8), %xmm2
movsd -8(%r13,%rsi,8), %xmm3 # xmm3 = mem[0],zero
movl %esi, %eax
cmovel %ebx, %eax
leal (%r14,%rax), %eax
addsd (%r15,%rax,8), %xmm2
movslq %edx, %rax
addsd (%rbp,%rax,8), %xmm2
movapd %xmm3, %xmm4
mulsd %xmm0, %xmm4
addsd %xmm2, %xmm4
mulsd %xmm1, %xmm4
addsd %xmm3, %xmm4
movsd %xmm4, -8(%r12,%rsi,8)
leaq (%r8,%rsi), %rax
incq %rax
incq %rsi
cmpq $1, %rax
jne .LBB7_10
# %bb.8: # %.loopexit.i
# in Loop: Header=BB7_9 Depth=2
addq %rdi, %r12
addq %rdi, %r13
cmpq %rcx, %r10
jne .LBB7_9
jmp .LBB7_11
.LBB7_12:
movq 192(%rsp), %rax # 8-byte Reload
movq 32(%rsp,%rax,8), %rsi
movl $524288, %edx # imm = 0x80000
movq 184(%rsp), %rdi # 8-byte Reload
callq memcpy@PLT
callq clock
subq 208(%rsp), %rax # 8-byte Folded Reload
xorl %ebp, %ebp
movl $.L.str.1, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl 12(%rsp), %eax
testl %eax, %eax
movsd .LCPI7_0(%rip), %xmm0 # xmm0 = mem[0],zero
jle .LBB7_17
# %bb.13: # %.lr.ph37.i52
movq 32(%rsp), %rcx
cvtsi2sd %eax, %xmm1
divsd %xmm1, %xmm0
leaq (,%rax,8), %rdx
xorl %esi, %esi
movsd .LCPI7_1(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI7_2(%rip), %xmm2 # xmm2 = mem[0],zero
.p2align 4, 0x90
.LBB7_14: # %.lr.ph.i54
# =>This Loop Header: Depth=1
# Child Loop BB7_15 Depth 2
xorps %xmm3, %xmm3
cvtsi2sd %esi, %xmm3
mulsd %xmm0, %xmm3
movapd %xmm1, %xmm4
cmpltsd %xmm3, %xmm4
cmpltsd %xmm1, %xmm3
movq %rcx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB7_15: # Parent Loop BB7_14 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm5, %xmm5
cvtsi2sd %r8d, %xmm5
mulsd %xmm0, %xmm5
movapd %xmm1, %xmm6
cmpltsd %xmm5, %xmm6
cmpltsd %xmm1, %xmm5
andpd %xmm2, %xmm5
andpd %xmm3, %xmm5
movapd %xmm4, %xmm7
andnpd %xmm5, %xmm7
movapd %xmm6, %xmm8
andnpd %xmm5, %xmm8
andpd %xmm2, %xmm6
orpd %xmm8, %xmm6
andpd %xmm4, %xmm6
orpd %xmm7, %xmm6
movlpd %xmm6, (%rdi)
incq %r8
addq %rdx, %rdi
cmpq %r8, %rax
jne .LBB7_15
# %bb.16: # %._crit_edge.i63
# in Loop: Header=BB7_14 Depth=1
incq %rsi
addq $8, %rcx
cmpq %rax, %rsi
jne .LBB7_14
.LBB7_17: # %_Z10init_fieldPdii.exit66
movabsq $137438953504, %r14 # imm = 0x2000000020
movabsq $4294967304, %r15 # imm = 0x100000008
callq clock
movq %rax, 56(%rsp) # 8-byte Spill
movq 16(%rsp), %rdi
movq 32(%rsp), %rsi
movl $1, %r13d
movl $524288, %edx # imm = 0x80000
movl $1, %ecx
callq hipMemcpy
movl $2000, %ebx # imm = 0x7D0
jmp .LBB7_18
.p2align 4, 0x90
.LBB7_20: # in Loop: Header=BB7_18 Depth=1
callq hipDeviceSynchronize
movl %r12d, %ebp
decl %ebx
je .LBB7_21
.LBB7_18: # =>This Inner Loop Header: Depth=1
movl %r13d, %r12d
movl %ebp, %r13d
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_20
# %bb.19: # in Loop: Header=BB7_18 Depth=1
movl %r13d, %eax
movq 16(%rsp,%rax,8), %rax
movl %r12d, %ecx
movq 16(%rsp,%rcx,8), %rcx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
leaq 144(%rsp), %rax
movq %rax, 160(%rsp)
leaq 136(%rsp), %rax
movq %rax, 168(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
movl $_Z16diffusion_globalPdS_, %edi
leaq 160(%rsp), %r9
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB7_20
.LBB7_21:
movq 80(%rsp), %rdi
movl %r12d, %eax
movq 16(%rsp,%rax,8), %rsi
movl $524288, %edx # imm = 0x80000
movl $2, %ecx
callq hipMemcpy
callq clock
subq 56(%rsp), %rax # 8-byte Folded Reload
xorl %ebp, %ebp
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl 12(%rsp), %eax
testl %eax, %eax
movsd .LCPI7_0(%rip), %xmm8 # xmm8 = mem[0],zero
jle .LBB7_26
# %bb.22: # %.lr.ph37.i67
movq 32(%rsp), %rcx
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm0, %xmm8
leaq (,%rax,8), %rdx
xorl %esi, %esi
movsd .LCPI7_1(%rip), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI7_2(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB7_23: # %.lr.ph.i69
# =>This Loop Header: Depth=1
# Child Loop BB7_24 Depth 2
xorps %xmm2, %xmm2
cvtsi2sd %esi, %xmm2
mulsd %xmm8, %xmm2
movapd %xmm0, %xmm3
cmpltsd %xmm2, %xmm3
cmpltsd %xmm0, %xmm2
movq %rcx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB7_24: # Parent Loop BB7_23 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm4, %xmm4
cvtsi2sd %r8d, %xmm4
mulsd %xmm8, %xmm4
movapd %xmm0, %xmm5
cmpltsd %xmm4, %xmm5
cmpltsd %xmm0, %xmm4
andpd %xmm1, %xmm4
andpd %xmm2, %xmm4
movapd %xmm3, %xmm6
andnpd %xmm4, %xmm6
movapd %xmm5, %xmm7
andnpd %xmm4, %xmm7
andpd %xmm1, %xmm5
orpd %xmm7, %xmm5
andpd %xmm3, %xmm5
orpd %xmm6, %xmm5
movlpd %xmm5, (%rdi)
incq %r8
addq %rdx, %rdi
cmpq %r8, %rax
jne .LBB7_24
# %bb.25: # %._crit_edge.i78
# in Loop: Header=BB7_23 Depth=1
incq %rsi
addq $8, %rcx
cmpq %rax, %rsi
jne .LBB7_23
.LBB7_26: # %_Z10init_fieldPdii.exit81
callq clock
movq %rax, 56(%rsp) # 8-byte Spill
movq 16(%rsp), %rdi
movq 32(%rsp), %rsi
movl $1, %r13d
movl $524288, %edx # imm = 0x80000
movl $1, %ecx
callq hipMemcpy
movl $2000, %ebx # imm = 0x7D0
jmp .LBB7_27
.p2align 4, 0x90
.LBB7_29: # in Loop: Header=BB7_27 Depth=1
callq hipDeviceSynchronize
movl %r12d, %ebp
decl %ebx
je .LBB7_30
.LBB7_27: # =>This Inner Loop Header: Depth=1
movl %r13d, %r12d
movl %ebp, %r13d
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_29
# %bb.28: # in Loop: Header=BB7_27 Depth=1
movl %r13d, %eax
movq 16(%rsp,%rax,8), %rax
movl %r12d, %ecx
movq 16(%rsp,%rcx,8), %rcx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
leaq 144(%rsp), %rax
movq %rax, 160(%rsp)
leaq 136(%rsp), %rax
movq %rax, 168(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
movl $_Z16diffusion_sharedPdS_, %edi
leaq 160(%rsp), %r9
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB7_29
.LBB7_30:
movq 72(%rsp), %rdi
movl %r12d, %eax
movq 16(%rsp,%rax,8), %rsi
movl $524288, %edx # imm = 0x80000
movl $2, %ecx
callq hipMemcpy
callq clock
subq 56(%rsp), %rax # 8-byte Folded Reload
movl $.L.str.3, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
movl 12(%rsp), %eax
xorpd %xmm0, %xmm0
testl %eax, %eax
movq 184(%rsp), %rbx # 8-byte Reload
je .LBB7_33
# %bb.31: # %.lr.ph.preheader.i
movq 80(%rsp), %rcx
imull %eax, %eax
cmpl $1, %eax
adcl $0, %eax
xorl %edx, %edx
.p2align 4, 0x90
.LBB7_32: # %.lr.ph.i89
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%rdx,8), %xmm1 # xmm1 = mem[0],zero
subsd (%rcx,%rdx,8), %xmm1
mulsd %xmm1, %xmm1
addsd %xmm1, %xmm0
incq %rdx
cmpq %rdx, %rax
jne .LBB7_32
.LBB7_33: # %_Z13check_residuePdS_i.exit
movl $.L.str.5, %edi
movb $1, %al
callq printf
movl 12(%rsp), %eax
testl %eax, %eax
xorpd %xmm0, %xmm0
je .LBB7_36
# %bb.34: # %.lr.ph.preheader.i95
movq 72(%rsp), %rcx
imull %eax, %eax
cmpl $1, %eax
adcl $0, %eax
xorl %edx, %edx
.p2align 4, 0x90
.LBB7_35: # %.lr.ph.i98
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%rdx,8), %xmm1 # xmm1 = mem[0],zero
subsd (%rcx,%rdx,8), %xmm1
mulsd %xmm1, %xmm1
addsd %xmm1, %xmm0
incq %rdx
cmpq %rdx, %rax
jne .LBB7_35
.LBB7_36: # %_Z13check_residuePdS_i.exit105
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
callq hipHostFree
movq 40(%rsp), %rdi
callq hipHostFree
movq 80(%rsp), %rdi
callq hipHostFree
movq 72(%rsp), %rdi
callq hipHostFree
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16diffusion_globalPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16diffusion_sharedPdS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $n, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $theta, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type n,@object # @n
.local n
.comm n,4,4
.type theta,@object # @theta
.local theta
.comm theta,8,8
.type _Z16diffusion_globalPdS_,@object # @_Z16diffusion_globalPdS_
.section .rodata,"a",@progbits
.globl _Z16diffusion_globalPdS_
.p2align 3, 0x0
_Z16diffusion_globalPdS_:
.quad _Z31__device_stub__diffusion_globalPdS_
.size _Z16diffusion_globalPdS_, 8
.type _Z16diffusion_sharedPdS_,@object # @_Z16diffusion_sharedPdS_
.globl _Z16diffusion_sharedPdS_
.p2align 3, 0x0
_Z16diffusion_sharedPdS_:
.quad _Z31__device_stub__diffusion_sharedPdS_
.size _Z16diffusion_sharedPdS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f %f %f\n"
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "host:%ld\n"
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "global:%ld\n"
.size .L.str.2, 12
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "shared:%ld\n"
.size .L.str.3, 12
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "global:%f\n"
.size .L.str.5, 11
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "shared:%f\n"
.size .L.str.6, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16diffusion_globalPdS_"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16diffusion_sharedPdS_"
.size .L__unnamed_2, 25
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "n"
.size .L__unnamed_3, 2
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "theta"
.size .L__unnamed_4, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "answers"
.size .Lstr, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__diffusion_globalPdS_
.addrsig_sym _Z31__device_stub__diffusion_sharedPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym n
.addrsig_sym theta
.addrsig_sym _Z16diffusion_globalPdS_
.addrsig_sym _Z16diffusion_sharedPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001891f2_00000000-6_diffusion_me.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10init_fieldPdii
.type _Z10init_fieldPdii, @function
_Z10init_fieldPdii:
.LFB2057:
.cfi_startproc
endbr64
pxor %xmm1, %xmm1
cvtsi2sdl %edx, %xmm1
pxor %xmm0, %xmm0
cvtsi2sdl %esi, %xmm0
movapd %xmm1, %xmm3
divsd %xmm0, %xmm3
mulsd .LC0(%rip), %xmm1
testl %esi, %esi
jle .L3
movl $0, %r8d
movl $0, %r9d
movsd .LC1(%rip), %xmm4
jmp .L13
.L18:
comisd %xmm2, %xmm1
jbe .L8
comisd %xmm0, %xmm1
ja .L7
.L8:
movslq %edx, %rcx
movq $0x000000000, (%rdi,%rcx,8)
.L11:
leal 1(%rax), %ecx
addl %esi, %edx
cmpl %ecx, %esi
je .L19
movl %ecx, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd %xmm3, %xmm0
comisd %xmm1, %xmm2
jbe .L18
comisd %xmm1, %xmm0
jbe .L8
.L7:
movslq %edx, %rcx
movsd %xmm4, (%rdi,%rcx,8)
jmp .L11
.L19:
leal 1(%r8), %edx
cmpl %eax, %r8d
je .L3
movl %edx, %r8d
.L13:
pxor %xmm2, %xmm2
cvtsi2sdl %r8d, %xmm2
mulsd %xmm3, %xmm2
movl %r8d, %edx
movl %r9d, %eax
jmp .L12
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z10init_fieldPdii, .-_Z10init_fieldPdii
.globl _Z7flip_ijPiS_
.type _Z7flip_ijPiS_, @function
_Z7flip_ijPiS_:
.LFB2058:
.cfi_startproc
endbr64
movl (%rdi), %eax
movl (%rsi), %edx
movl %edx, (%rdi)
movl %eax, (%rsi)
ret
.cfi_endproc
.LFE2058:
.size _Z7flip_ijPiS_, .-_Z7flip_ijPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "%f %f %f\n"
.text
.globl _Z11print_fieldP8_IO_FILEPdid
.type _Z11print_fieldP8_IO_FILEPdid, @function
_Z11print_fieldP8_IO_FILEPdid:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movl %edx, %eax
movapd %xmm0, %xmm1
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
divsd %xmm0, %xmm1
movsd %xmm1, 24(%rsp)
mulsd .LC3(%rip), %xmm1
movsd %xmm1, 16(%rsp)
cltq
leaq 0(,%rax,8), %r15
leaq 2048(%rsi), %rbp
movl $0, %r14d
leaq .LC4(%rip), %r13
.L23:
pxor %xmm0, %xmm0
cvtsi2sdl %r14d, %xmm0
mulsd 24(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
leaq -2048(%rbp), %rbx
.L22:
movsd (%rbx), %xmm2
movsd 16(%rsp), %xmm1
movsd 8(%rsp), %xmm0
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $3, %eax
call __fprintf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L22
addl $1, %r14d
addq %r15, %rbp
cmpl $256, %r14d
jne .L23
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z11print_fieldP8_IO_FILEPdid, .-_Z11print_fieldP8_IO_FILEPdid
.globl _Z14diffusion_hostPdS_id
.type _Z14diffusion_hostPdS_id, @function
_Z14diffusion_hostPdS_id:
.LFB2060:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L34
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, %r8
movl %edx, %edi
movslq %edx, %r14
leaq 0(,%r14,8), %r15
movq %r8, %r10
movq %rsi, %r9
movl $0, %r13d
movl $0, %r12d
leal -2(%rdx), %r11d
movsd .LC5(%rip), %xmm4
.L30:
addl $1, %r12d
movl %r13d, %esi
movl %r12d, %eax
cltd
idivl %edi
imull %edi, %edx
movslq %edx, %rdx
leaq (%r8,%rdx,8), %rbp
leal (%r12,%r11), %eax
cltd
idivl %edi
imull %edi, %edx
movslq %edx, %rdx
leaq (%r8,%rdx,8), %rbx
movl $1, %ecx
.L29:
movsd -8(%r10,%rcx,8), %xmm3
movl %ecx, %eax
cltd
idivl %edi
addl %esi, %edx
movslq %edx, %rdx
movsd -8(%rbp,%rcx,8), %xmm2
addsd -8(%rbx,%rcx,8), %xmm2
addsd (%r8,%rdx,8), %xmm2
leal (%r11,%rcx), %eax
cltd
idivl %edi
addl %esi, %edx
movslq %edx, %rdx
movapd %xmm2, %xmm1
addsd (%r8,%rdx,8), %xmm1
movapd %xmm3, %xmm2
mulsd %xmm4, %xmm2
subsd %xmm2, %xmm1
mulsd %xmm0, %xmm1
addsd %xmm3, %xmm1
movsd %xmm1, -8(%r9,%rcx,8)
movq %rcx, %rax
addq $1, %rcx
cmpq %r14, %rax
jne .L29
addl %edi, %r13d
addq %r15, %r10
addq %r15, %r9
cmpl %edi, %r12d
jne .L30
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2060:
.size _Z14diffusion_hostPdS_id, .-_Z14diffusion_hostPdS_id
.globl _Z13check_residuePdS_i
.type _Z13check_residuePdS_i, @function
_Z13check_residuePdS_i:
.LFB2061:
.cfi_startproc
endbr64
imull %edx, %edx
testl %edx, %edx
jle .L40
movslq %edx, %rdx
salq $3, %rdx
movl $0, %eax
pxor %xmm1, %xmm1
.L39:
movsd (%rdi,%rax), %xmm0
subsd (%rsi,%rax), %xmm0
mulsd %xmm0, %xmm0
addsd %xmm0, %xmm1
addq $8, %rax
cmpq %rdx, %rax
jne .L39
.L37:
movapd %xmm1, %xmm0
ret
.L40:
pxor %xmm1, %xmm1
jmp .L37
.cfi_endproc
.LFE2061:
.size _Z13check_residuePdS_i, .-_Z13check_residuePdS_i
.globl _Z38__device_stub__Z16diffusion_globalPdS_PdS_
.type _Z38__device_stub__Z16diffusion_globalPdS_PdS_, @function
_Z38__device_stub__Z16diffusion_globalPdS_PdS_:
.LFB2087:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L46
.L42:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L47
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16diffusion_globalPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L42
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z38__device_stub__Z16diffusion_globalPdS_PdS_, .-_Z38__device_stub__Z16diffusion_globalPdS_PdS_
.globl _Z16diffusion_globalPdS_
.type _Z16diffusion_globalPdS_, @function
_Z16diffusion_globalPdS_:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z16diffusion_globalPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z16diffusion_globalPdS_, .-_Z16diffusion_globalPdS_
.globl _Z38__device_stub__Z16diffusion_sharedPdS_PdS_
.type _Z38__device_stub__Z16diffusion_sharedPdS_PdS_, @function
_Z38__device_stub__Z16diffusion_sharedPdS_PdS_:
.LFB2089:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L54
.L50:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L55
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16diffusion_sharedPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L50
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z38__device_stub__Z16diffusion_sharedPdS_PdS_, .-_Z38__device_stub__Z16diffusion_sharedPdS_PdS_
.globl _Z16diffusion_sharedPdS_
.type _Z16diffusion_sharedPdS_, @function
_Z16diffusion_sharedPdS_:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z16diffusion_sharedPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z16diffusion_sharedPdS_, .-_Z16diffusion_sharedPdS_
.section .rodata.str1.1
.LC7:
.string "host:%ld\n"
.LC8:
.string "global:%ld\n"
.LC9:
.string "shared:%ld\n"
.LC10:
.string "answers\n"
.LC11:
.string "global:%f\n"
.LC12:
.string "shared:%f\n"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $112, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $1, 48(%rsp)
movl $256, 12(%rsp)
movq .LC6(%rip), %rax
movq %rax, 16(%rsp)
movl $32, 40(%rsp)
movl $32, 44(%rsp)
leaq 12(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL1n(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 16(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $8, %edx
leaq _ZL5theta(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 64(%rsp), %rdi
movl $2, %edx
movl $524288, %esi
call cudaHostAlloc@PLT
leaq 72(%rsp), %rdi
movl $2, %edx
movl $524288, %esi
call cudaHostAlloc@PLT
leaq 24(%rsp), %rdi
movl $2, %edx
movl $524288, %esi
call cudaHostAlloc@PLT
leaq 32(%rsp), %rdi
movl $2, %edx
movl $524288, %esi
call cudaHostAlloc@PLT
leaq 80(%rsp), %rdi
movl $524288, %esi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movl $524288, %esi
call cudaMalloc@PLT
movl $524288, %edi
call malloc@PLT
movq %rax, %r12
movl $10, %edx
movl 12(%rsp), %esi
movq 64(%rsp), %rdi
call _Z10init_fieldPdii
call clock@PLT
movq %rax, %r14
movl $2000, %ebp
movl $1, %ebx
movl $0, %r13d
jmp .L59
.L65:
movl %r13d, %eax
movl %ebx, %r13d
movl %eax, %ebx
.L59:
movslq %ebx, %rax
movq 64(%rsp,%rax,8), %rsi
movslq %r13d, %rax
movq 64(%rsp,%rax,8), %rdi
movsd 16(%rsp), %xmm0
movl 12(%rsp), %edx
call _Z14diffusion_hostPdS_id
subl $1, %ebp
jne .L65
movslq %ebx, %rbx
movq 64(%rsp,%rbx,8), %rsi
movl $524288, %edx
movq %r12, %rdi
call memcpy@PLT
call clock@PLT
subq %r14, %rax
movq %rax, %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, %edx
movl 12(%rsp), %esi
movq 64(%rsp), %rdi
call _Z10init_fieldPdii
call clock@PLT
movq %rax, %r14
movl $1, %ecx
movl $524288, %edx
movq 64(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $2000, %ebx
movl $1, %ebp
movl $0, %r13d
jmp .L61
.L60:
call cudaDeviceSynchronize@PLT
subl $1, %ebx
je .L69
movl %r13d, %eax
movl %ebp, %r13d
movl %eax, %ebp
.L61:
movl $8, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl 48(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L60
movslq %ebp, %rax
movq 80(%rsp,%rax,8), %rsi
movslq %r13d, %rax
movq 80(%rsp,%rax,8), %rdi
call _Z38__device_stub__Z16diffusion_globalPdS_PdS_
jmp .L60
.L69:
movslq %ebp, %rbp
movq 80(%rsp,%rbp,8), %rsi
movl $2, %ecx
movl $524288, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
subq %r14, %rax
movq %rax, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, %edx
movl 12(%rsp), %esi
movq 64(%rsp), %rdi
call _Z10init_fieldPdii
call clock@PLT
movq %rax, %r14
movl $1, %ecx
movl $524288, %edx
movq 64(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $2000, %ebx
movl $1, %ebp
movl $0, %r13d
jmp .L63
.L62:
call cudaDeviceSynchronize@PLT
subl $1, %ebx
je .L70
movl %r13d, %eax
movl %ebp, %r13d
movl %eax, %ebp
.L63:
movl $8, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl 48(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L62
movslq %ebp, %rax
movq 80(%rsp,%rax,8), %rsi
movslq %r13d, %rax
movq 80(%rsp,%rax,8), %rdi
call _Z38__device_stub__Z16diffusion_sharedPdS_PdS_
jmp .L62
.L70:
movslq %ebp, %rbp
movq 80(%rsp,%rbp,8), %rsi
movl $2, %ecx
movl $524288, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
subq %r14, %rax
movq %rax, %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call _Z13check_residuePdS_i
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 12(%rsp), %edx
movq 32(%rsp), %rsi
movq %r12, %rdi
call _Z13check_residuePdS_i
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 64(%rsp), %rdi
call cudaFreeHost@PLT
movq 72(%rsp), %rdi
call cudaFreeHost@PLT
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
movq 32(%rsp), %rdi
call cudaFreeHost@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L71
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L71:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z16diffusion_sharedPdS_"
.LC14:
.string "_Z16diffusion_globalPdS_"
.LC15:
.string "n"
.LC16:
.string "theta"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z16diffusion_sharedPdS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z16diffusion_globalPdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1n(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5theta(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL5theta
.comm _ZL5theta,8,8
.local _ZL1n
.comm _ZL1n,4,4
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1071644672
.align 8
.LC1:
.long 0
.long 1072693248
.align 8
.LC3:
.long 0
.long 1081081856
.align 8
.LC5:
.long 0
.long 1074790400
.align 8
.LC6:
.long -1717986918
.long 1069128089
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "diffusion_me.hip"
.globl _Z31__device_stub__diffusion_globalPdS_ # -- Begin function _Z31__device_stub__diffusion_globalPdS_
.p2align 4, 0x90
.type _Z31__device_stub__diffusion_globalPdS_,@function
_Z31__device_stub__diffusion_globalPdS_: # @_Z31__device_stub__diffusion_globalPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16diffusion_globalPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z31__device_stub__diffusion_globalPdS_, .Lfunc_end0-_Z31__device_stub__diffusion_globalPdS_
.cfi_endproc
# -- End function
.globl _Z31__device_stub__diffusion_sharedPdS_ # -- Begin function _Z31__device_stub__diffusion_sharedPdS_
.p2align 4, 0x90
.type _Z31__device_stub__diffusion_sharedPdS_,@function
_Z31__device_stub__diffusion_sharedPdS_: # @_Z31__device_stub__diffusion_sharedPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16diffusion_sharedPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z31__device_stub__diffusion_sharedPdS_, .Lfunc_end1-_Z31__device_stub__diffusion_sharedPdS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z10init_fieldPdii
.LCPI2_0:
.quad 0x3fe0000000000000 # double 0.5
.LCPI2_1:
.quad 0x3ff0000000000000 # double 1
.text
.globl _Z10init_fieldPdii
.p2align 4, 0x90
.type _Z10init_fieldPdii,@function
_Z10init_fieldPdii: # @_Z10init_fieldPdii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_5
# %bb.1: # %.lr.ph37
cvtsi2sd %edx, %xmm0
cvtsi2sd %esi, %xmm2
movapd %xmm0, %xmm1
divsd %xmm2, %xmm1
mulsd .LCPI2_0(%rip), %xmm0
movl %esi, %eax
leaq (,%rax,8), %rcx
xorl %edx, %edx
movsd .LCPI2_1(%rip), %xmm2 # xmm2 = mem[0],zero
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
xorps %xmm3, %xmm3
cvtsi2sd %edx, %xmm3
mulsd %xmm1, %xmm3
movapd %xmm0, %xmm4
cmpltsd %xmm3, %xmm4
cmpltsd %xmm0, %xmm3
movq %rdi, %rsi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm5, %xmm5
cvtsi2sd %r8d, %xmm5
mulsd %xmm1, %xmm5
movapd %xmm0, %xmm6
cmpltsd %xmm5, %xmm6
cmpltsd %xmm0, %xmm5
andpd %xmm2, %xmm5
andpd %xmm3, %xmm5
movapd %xmm4, %xmm7
andnpd %xmm5, %xmm7
movapd %xmm6, %xmm8
andnpd %xmm5, %xmm8
andpd %xmm2, %xmm6
orpd %xmm8, %xmm6
andpd %xmm4, %xmm6
orpd %xmm7, %xmm6
movlpd %xmm6, (%rsi)
incq %r8
addq %rcx, %rsi
cmpq %r8, %rax
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %rdx
addq $8, %rdi
cmpq %rax, %rdx
jne .LBB2_2
.LBB2_5: # %._crit_edge38
retq
.Lfunc_end2:
.size _Z10init_fieldPdii, .Lfunc_end2-_Z10init_fieldPdii
.cfi_endproc
# -- End function
.globl _Z7flip_ijPiS_ # -- Begin function _Z7flip_ijPiS_
.p2align 4, 0x90
.type _Z7flip_ijPiS_,@function
_Z7flip_ijPiS_: # @_Z7flip_ijPiS_
.cfi_startproc
# %bb.0:
movl (%rdi), %eax
movl (%rsi), %ecx
movl %ecx, (%rdi)
movl %eax, (%rsi)
retq
.Lfunc_end3:
.size _Z7flip_ijPiS_, .Lfunc_end3-_Z7flip_ijPiS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z11print_fieldP8_IO_FILEPdid
.LCPI4_0:
.quad 0x4070000000000000 # double 256
.text
.globl _Z11print_fieldP8_IO_FILEPdid
.p2align 4, 0x90
.type _Z11print_fieldP8_IO_FILEPdid,@function
_Z11print_fieldP8_IO_FILEPdid: # @_Z11print_fieldP8_IO_FILEPdid
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
cvtsi2sd %edx, %xmm1
divsd %xmm1, %xmm0
movslq %edx, %r15
movsd .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero
movsd %xmm0, 8(%rsp) # 8-byte Spill
mulsd %xmm0, %xmm1
shlq $3, %r15
xorl %r12d, %r12d
movsd %xmm1, 16(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB4_1: # =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
xorps %xmm0, %xmm0
cvtsi2sd %r12d, %xmm0
mulsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 24(%rsp) # 8-byte Spill
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rbx,%r13,8), %xmm2 # xmm2 = mem[0],zero
movl $.L.str, %esi
movq %r14, %rdi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movb $3, %al
callq fprintf
incq %r13
cmpq $256, %r13 # imm = 0x100
jne .LBB4_2
# %bb.3: # in Loop: Header=BB4_1 Depth=1
incq %r12
addq %r15, %rbx
cmpq $256, %r12 # imm = 0x100
jne .LBB4_1
# %bb.4:
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z11print_fieldP8_IO_FILEPdid, .Lfunc_end4-_Z11print_fieldP8_IO_FILEPdid
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z14diffusion_hostPdS_id
.LCPI5_0:
.quad 0xc010000000000000 # double -4
.text
.globl _Z14diffusion_hostPdS_id
.p2align 4, 0x90
.type _Z14diffusion_hostPdS_id,@function
_Z14diffusion_hostPdS_id: # @_Z14diffusion_hostPdS_id
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB5_6
# %bb.1: # %.lr.ph48
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ecx
movl %edx, %r8d
leal -1(%rcx), %eax
movq %rax, -8(%rsp) # 8-byte Spill
leaq (,%r8,8), %rax
movq %rax, -16(%rsp) # 8-byte Spill
movq %r8, %r11
negq %r11
xorl %ebx, %ebx
movsd .LCPI5_0(%rip), %xmm1 # xmm1 = mem[0],zero
movq %rdi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_3: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB5_4 Depth 2
movq %r15, %r12
incq %r15
movq -8(%rsp), %rax # 8-byte Reload
addl %r12d, %eax
cltd
idivl %ecx
cmpq %r8, %r15
movl %r15d, %eax
cmovel %ebx, %eax
imulq %r8, %r12
imull %ecx, %eax
imull %ecx, %edx
cltq
movslq %edx, %rdx
leaq (%rdi,%rax,8), %r13
leaq (%rdi,%rdx,8), %rbp
leaq (%rdi,%r12,8), %r9
movl $1, %r10d
.p2align 4, 0x90
.LBB5_4: # Parent Loop BB5_3 Depth=1
# => This Inner Loop Header: Depth=2
leal (%r8,%r10), %eax
addl $-2, %eax
cltd
idivl %r8d
cmpq %r10, %r8
movsd -8(%r13,%r10,8), %xmm2 # xmm2 = mem[0],zero
addsd -8(%rbp,%r10,8), %xmm2
movsd -8(%r14,%r10,8), %xmm3 # xmm3 = mem[0],zero
movl %r10d, %eax
cmovel %ebx, %eax
addl %r12d, %eax
addsd (%rdi,%rax,8), %xmm2
movslq %edx, %rax
addsd (%r9,%rax,8), %xmm2
movapd %xmm3, %xmm4
mulsd %xmm1, %xmm4
addsd %xmm2, %xmm4
mulsd %xmm0, %xmm4
addsd %xmm3, %xmm4
movsd %xmm4, -8(%rsi,%r10,8)
leaq (%r11,%r10), %rax
incq %rax
incq %r10
cmpq $1, %rax
jne .LBB5_4
# %bb.2: # %.loopexit
# in Loop: Header=BB5_3 Depth=1
movq -16(%rsp), %rax # 8-byte Reload
addq %rax, %rsi
addq %rax, %r14
cmpq %r8, %r15
jne .LBB5_3
# %bb.5:
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB5_6: # %._crit_edge
retq
.Lfunc_end5:
.size _Z14diffusion_hostPdS_id, .Lfunc_end5-_Z14diffusion_hostPdS_id
.cfi_endproc
# -- End function
.globl _Z13check_residuePdS_i # -- Begin function _Z13check_residuePdS_i
.p2align 4, 0x90
.type _Z13check_residuePdS_i,@function
_Z13check_residuePdS_i: # @_Z13check_residuePdS_i
.cfi_startproc
# %bb.0:
# kill: def $edx killed $edx def $rdx
testl %edx, %edx
je .LBB6_1
# %bb.2: # %.lr.ph.preheader
imull %edx, %edx
cmpl $1, %edx
adcl $0, %edx
xorpd %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB6_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%rdi,%rax,8), %xmm1 # xmm1 = mem[0],zero
subsd (%rsi,%rax,8), %xmm1
mulsd %xmm1, %xmm1
addsd %xmm1, %xmm0
incq %rax
cmpq %rax, %rdx
jne .LBB6_3
# %bb.4: # %._crit_edge
retq
.LBB6_1:
xorps %xmm0, %xmm0
retq
.Lfunc_end6:
.size _Z13check_residuePdS_i, .Lfunc_end6-_Z13check_residuePdS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI7_0:
.quad 0x4024000000000000 # double 10
.LCPI7_1:
.quad 0x4014000000000000 # double 5
.LCPI7_2:
.quad 0x3ff0000000000000 # double 1
.LCPI7_3:
.quad 0xc010000000000000 # double -4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $256, 12(%rsp) # imm = 0x100
movabsq $4591870180066957722, %rax # imm = 0x3FB999999999999A
movq %rax, 200(%rsp)
xorl %ebx, %ebx
leaq 12(%rsp), %rsi
movl $1, %ebp
movl $n, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 200(%rsp), %rsi
movl $theta, %edi
movl $8, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 32(%rsp), %rdi
movl $524288, %esi # imm = 0x80000
movl $2, %edx
callq hipHostAlloc
leaq 40(%rsp), %rdi
movl $524288, %esi # imm = 0x80000
movl $2, %edx
callq hipHostAlloc
leaq 80(%rsp), %rdi
movl $524288, %esi # imm = 0x80000
movl $2, %edx
callq hipHostAlloc
leaq 72(%rsp), %rdi
movl $524288, %esi # imm = 0x80000
movl $2, %edx
callq hipHostAlloc
leaq 16(%rsp), %rdi
movl $524288, %esi # imm = 0x80000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $524288, %esi # imm = 0x80000
callq hipMalloc
movl $524288, %edi # imm = 0x80000
callq malloc
movq %rax, 184(%rsp) # 8-byte Spill
movl 12(%rsp), %eax
movsd .LCPI7_0(%rip), %xmm0 # xmm0 = mem[0],zero
testl %eax, %eax
jle .LBB7_5
# %bb.1: # %.lr.ph37.i
movq 32(%rsp), %rcx
cvtsi2sd %eax, %xmm1
divsd %xmm1, %xmm0
leaq (,%rax,8), %rdx
xorl %esi, %esi
movsd .LCPI7_1(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI7_2(%rip), %xmm2 # xmm2 = mem[0],zero
.p2align 4, 0x90
.LBB7_2: # %.lr.ph.i
# =>This Loop Header: Depth=1
# Child Loop BB7_3 Depth 2
xorps %xmm3, %xmm3
cvtsi2sd %esi, %xmm3
mulsd %xmm0, %xmm3
movapd %xmm1, %xmm4
cmpltsd %xmm3, %xmm4
cmpltsd %xmm1, %xmm3
movq %rcx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB7_3: # Parent Loop BB7_2 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm5, %xmm5
cvtsi2sd %r8d, %xmm5
mulsd %xmm0, %xmm5
movapd %xmm1, %xmm6
cmpltsd %xmm5, %xmm6
cmpltsd %xmm1, %xmm5
andpd %xmm2, %xmm5
andpd %xmm3, %xmm5
movapd %xmm4, %xmm7
andnpd %xmm5, %xmm7
movapd %xmm6, %xmm8
andnpd %xmm5, %xmm8
andpd %xmm2, %xmm6
orpd %xmm8, %xmm6
andpd %xmm4, %xmm6
orpd %xmm7, %xmm6
movlpd %xmm6, (%rdi)
incq %r8
addq %rdx, %rdi
cmpq %r8, %rax
jne .LBB7_3
# %bb.4: # %._crit_edge.i
# in Loop: Header=BB7_2 Depth=1
incq %rsi
addq $8, %rcx
cmpq %rax, %rsi
jne .LBB7_2
.LBB7_5: # %_Z10init_fieldPdii.exit
callq clock
movq %rax, 208(%rsp) # 8-byte Spill
movl 12(%rsp), %ecx
leal -1(%rcx), %eax
movq %rax, 56(%rsp) # 8-byte Spill
leaq (,%rcx,8), %rdi
movq %rcx, %r8
negq %r8
movsd .LCPI7_3(%rip), %xmm0 # xmm0 = mem[0],zero
xorl %edx, %edx
xorl %eax, %eax
jmp .LBB7_6
.p2align 4, 0x90
.LBB7_11: # %_Z14diffusion_hostPdS_id.exit
# in Loop: Header=BB7_6 Depth=1
movl 152(%rsp), %edx # 4-byte Reload
incl %edx
movl 156(%rsp), %eax # 4-byte Reload
movl 68(%rsp), %ebp # 4-byte Reload
cmpl $2000, %edx # imm = 0x7D0
je .LBB7_12
.LBB7_6: # =>This Loop Header: Depth=1
# Child Loop BB7_9 Depth 2
# Child Loop BB7_10 Depth 3
movl %edx, 152(%rsp) # 4-byte Spill
movl %eax, 68(%rsp) # 4-byte Spill
movl %ebp, 156(%rsp) # 4-byte Spill
movl %ebp, %eax
movq %rax, 192(%rsp) # 8-byte Spill
testl %ecx, %ecx
jle .LBB7_11
# %bb.7: # %.lr.ph.i47.preheader
# in Loop: Header=BB7_6 Depth=1
movl 68(%rsp), %eax # 4-byte Reload
movq 32(%rsp,%rax,8), %r15
movq 192(%rsp), %rax # 8-byte Reload
movq 32(%rsp,%rax,8), %r12
movsd 200(%rsp), %xmm1 # xmm1 = mem[0],zero
movq %r15, %r13
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB7_9: # %.lr.ph.i47
# Parent Loop BB7_6 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB7_10 Depth 3
movq %r10, %r14
incq %r10
movq 56(%rsp), %rax # 8-byte Reload
addl %r14d, %eax
cltd
idivl %ecx
cmpq %rcx, %r10
movl %r10d, %eax
cmovel %ebx, %eax
imulq %rcx, %r14
imull %ecx, %eax
imull %ecx, %edx
cltq
movslq %edx, %rdx
leaq (%r15,%r14,8), %rbp
leaq (%r15,%rdx,8), %r11
leaq (%r15,%rax,8), %r9
movl $1, %esi
.p2align 4, 0x90
.LBB7_10: # Parent Loop BB7_6 Depth=1
# Parent Loop BB7_9 Depth=2
# => This Inner Loop Header: Depth=3
leal (%rcx,%rsi), %eax
addl $-2, %eax
cltd
idivl %ecx
cmpq %rsi, %rcx
movsd -8(%r9,%rsi,8), %xmm2 # xmm2 = mem[0],zero
addsd -8(%r11,%rsi,8), %xmm2
movsd -8(%r13,%rsi,8), %xmm3 # xmm3 = mem[0],zero
movl %esi, %eax
cmovel %ebx, %eax
leal (%r14,%rax), %eax
addsd (%r15,%rax,8), %xmm2
movslq %edx, %rax
addsd (%rbp,%rax,8), %xmm2
movapd %xmm3, %xmm4
mulsd %xmm0, %xmm4
addsd %xmm2, %xmm4
mulsd %xmm1, %xmm4
addsd %xmm3, %xmm4
movsd %xmm4, -8(%r12,%rsi,8)
leaq (%r8,%rsi), %rax
incq %rax
incq %rsi
cmpq $1, %rax
jne .LBB7_10
# %bb.8: # %.loopexit.i
# in Loop: Header=BB7_9 Depth=2
addq %rdi, %r12
addq %rdi, %r13
cmpq %rcx, %r10
jne .LBB7_9
jmp .LBB7_11
.LBB7_12:
movq 192(%rsp), %rax # 8-byte Reload
movq 32(%rsp,%rax,8), %rsi
movl $524288, %edx # imm = 0x80000
movq 184(%rsp), %rdi # 8-byte Reload
callq memcpy@PLT
callq clock
subq 208(%rsp), %rax # 8-byte Folded Reload
xorl %ebp, %ebp
movl $.L.str.1, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl 12(%rsp), %eax
testl %eax, %eax
movsd .LCPI7_0(%rip), %xmm0 # xmm0 = mem[0],zero
jle .LBB7_17
# %bb.13: # %.lr.ph37.i52
movq 32(%rsp), %rcx
cvtsi2sd %eax, %xmm1
divsd %xmm1, %xmm0
leaq (,%rax,8), %rdx
xorl %esi, %esi
movsd .LCPI7_1(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI7_2(%rip), %xmm2 # xmm2 = mem[0],zero
.p2align 4, 0x90
.LBB7_14: # %.lr.ph.i54
# =>This Loop Header: Depth=1
# Child Loop BB7_15 Depth 2
xorps %xmm3, %xmm3
cvtsi2sd %esi, %xmm3
mulsd %xmm0, %xmm3
movapd %xmm1, %xmm4
cmpltsd %xmm3, %xmm4
cmpltsd %xmm1, %xmm3
movq %rcx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB7_15: # Parent Loop BB7_14 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm5, %xmm5
cvtsi2sd %r8d, %xmm5
mulsd %xmm0, %xmm5
movapd %xmm1, %xmm6
cmpltsd %xmm5, %xmm6
cmpltsd %xmm1, %xmm5
andpd %xmm2, %xmm5
andpd %xmm3, %xmm5
movapd %xmm4, %xmm7
andnpd %xmm5, %xmm7
movapd %xmm6, %xmm8
andnpd %xmm5, %xmm8
andpd %xmm2, %xmm6
orpd %xmm8, %xmm6
andpd %xmm4, %xmm6
orpd %xmm7, %xmm6
movlpd %xmm6, (%rdi)
incq %r8
addq %rdx, %rdi
cmpq %r8, %rax
jne .LBB7_15
# %bb.16: # %._crit_edge.i63
# in Loop: Header=BB7_14 Depth=1
incq %rsi
addq $8, %rcx
cmpq %rax, %rsi
jne .LBB7_14
.LBB7_17: # %_Z10init_fieldPdii.exit66
movabsq $137438953504, %r14 # imm = 0x2000000020
movabsq $4294967304, %r15 # imm = 0x100000008
callq clock
movq %rax, 56(%rsp) # 8-byte Spill
movq 16(%rsp), %rdi
movq 32(%rsp), %rsi
movl $1, %r13d
movl $524288, %edx # imm = 0x80000
movl $1, %ecx
callq hipMemcpy
movl $2000, %ebx # imm = 0x7D0
jmp .LBB7_18
.p2align 4, 0x90
.LBB7_20: # in Loop: Header=BB7_18 Depth=1
callq hipDeviceSynchronize
movl %r12d, %ebp
decl %ebx
je .LBB7_21
.LBB7_18: # =>This Inner Loop Header: Depth=1
movl %r13d, %r12d
movl %ebp, %r13d
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_20
# %bb.19: # in Loop: Header=BB7_18 Depth=1
movl %r13d, %eax
movq 16(%rsp,%rax,8), %rax
movl %r12d, %ecx
movq 16(%rsp,%rcx,8), %rcx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
leaq 144(%rsp), %rax
movq %rax, 160(%rsp)
leaq 136(%rsp), %rax
movq %rax, 168(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
movl $_Z16diffusion_globalPdS_, %edi
leaq 160(%rsp), %r9
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB7_20
.LBB7_21:
movq 80(%rsp), %rdi
movl %r12d, %eax
movq 16(%rsp,%rax,8), %rsi
movl $524288, %edx # imm = 0x80000
movl $2, %ecx
callq hipMemcpy
callq clock
subq 56(%rsp), %rax # 8-byte Folded Reload
xorl %ebp, %ebp
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl 12(%rsp), %eax
testl %eax, %eax
movsd .LCPI7_0(%rip), %xmm8 # xmm8 = mem[0],zero
jle .LBB7_26
# %bb.22: # %.lr.ph37.i67
movq 32(%rsp), %rcx
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm0, %xmm8
leaq (,%rax,8), %rdx
xorl %esi, %esi
movsd .LCPI7_1(%rip), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI7_2(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB7_23: # %.lr.ph.i69
# =>This Loop Header: Depth=1
# Child Loop BB7_24 Depth 2
xorps %xmm2, %xmm2
cvtsi2sd %esi, %xmm2
mulsd %xmm8, %xmm2
movapd %xmm0, %xmm3
cmpltsd %xmm2, %xmm3
cmpltsd %xmm0, %xmm2
movq %rcx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB7_24: # Parent Loop BB7_23 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm4, %xmm4
cvtsi2sd %r8d, %xmm4
mulsd %xmm8, %xmm4
movapd %xmm0, %xmm5
cmpltsd %xmm4, %xmm5
cmpltsd %xmm0, %xmm4
andpd %xmm1, %xmm4
andpd %xmm2, %xmm4
movapd %xmm3, %xmm6
andnpd %xmm4, %xmm6
movapd %xmm5, %xmm7
andnpd %xmm4, %xmm7
andpd %xmm1, %xmm5
orpd %xmm7, %xmm5
andpd %xmm3, %xmm5
orpd %xmm6, %xmm5
movlpd %xmm5, (%rdi)
incq %r8
addq %rdx, %rdi
cmpq %r8, %rax
jne .LBB7_24
# %bb.25: # %._crit_edge.i78
# in Loop: Header=BB7_23 Depth=1
incq %rsi
addq $8, %rcx
cmpq %rax, %rsi
jne .LBB7_23
.LBB7_26: # %_Z10init_fieldPdii.exit81
callq clock
movq %rax, 56(%rsp) # 8-byte Spill
movq 16(%rsp), %rdi
movq 32(%rsp), %rsi
movl $1, %r13d
movl $524288, %edx # imm = 0x80000
movl $1, %ecx
callq hipMemcpy
movl $2000, %ebx # imm = 0x7D0
jmp .LBB7_27
.p2align 4, 0x90
.LBB7_29: # in Loop: Header=BB7_27 Depth=1
callq hipDeviceSynchronize
movl %r12d, %ebp
decl %ebx
je .LBB7_30
.LBB7_27: # =>This Inner Loop Header: Depth=1
movl %r13d, %r12d
movl %ebp, %r13d
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_29
# %bb.28: # in Loop: Header=BB7_27 Depth=1
movl %r13d, %eax
movq 16(%rsp,%rax,8), %rax
movl %r12d, %ecx
movq 16(%rsp,%rcx,8), %rcx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
leaq 144(%rsp), %rax
movq %rax, 160(%rsp)
leaq 136(%rsp), %rax
movq %rax, 168(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
movl $_Z16diffusion_sharedPdS_, %edi
leaq 160(%rsp), %r9
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB7_29
.LBB7_30:
movq 72(%rsp), %rdi
movl %r12d, %eax
movq 16(%rsp,%rax,8), %rsi
movl $524288, %edx # imm = 0x80000
movl $2, %ecx
callq hipMemcpy
callq clock
subq 56(%rsp), %rax # 8-byte Folded Reload
movl $.L.str.3, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
movl 12(%rsp), %eax
xorpd %xmm0, %xmm0
testl %eax, %eax
movq 184(%rsp), %rbx # 8-byte Reload
je .LBB7_33
# %bb.31: # %.lr.ph.preheader.i
movq 80(%rsp), %rcx
imull %eax, %eax
cmpl $1, %eax
adcl $0, %eax
xorl %edx, %edx
.p2align 4, 0x90
.LBB7_32: # %.lr.ph.i89
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%rdx,8), %xmm1 # xmm1 = mem[0],zero
subsd (%rcx,%rdx,8), %xmm1
mulsd %xmm1, %xmm1
addsd %xmm1, %xmm0
incq %rdx
cmpq %rdx, %rax
jne .LBB7_32
.LBB7_33: # %_Z13check_residuePdS_i.exit
movl $.L.str.5, %edi
movb $1, %al
callq printf
movl 12(%rsp), %eax
testl %eax, %eax
xorpd %xmm0, %xmm0
je .LBB7_36
# %bb.34: # %.lr.ph.preheader.i95
movq 72(%rsp), %rcx
imull %eax, %eax
cmpl $1, %eax
adcl $0, %eax
xorl %edx, %edx
.p2align 4, 0x90
.LBB7_35: # %.lr.ph.i98
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%rdx,8), %xmm1 # xmm1 = mem[0],zero
subsd (%rcx,%rdx,8), %xmm1
mulsd %xmm1, %xmm1
addsd %xmm1, %xmm0
incq %rdx
cmpq %rdx, %rax
jne .LBB7_35
.LBB7_36: # %_Z13check_residuePdS_i.exit105
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
callq hipHostFree
movq 40(%rsp), %rdi
callq hipHostFree
movq 80(%rsp), %rdi
callq hipHostFree
movq 72(%rsp), %rdi
callq hipHostFree
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16diffusion_globalPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16diffusion_sharedPdS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $n, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $theta, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type n,@object # @n
.local n
.comm n,4,4
.type theta,@object # @theta
.local theta
.comm theta,8,8
.type _Z16diffusion_globalPdS_,@object # @_Z16diffusion_globalPdS_
.section .rodata,"a",@progbits
.globl _Z16diffusion_globalPdS_
.p2align 3, 0x0
_Z16diffusion_globalPdS_:
.quad _Z31__device_stub__diffusion_globalPdS_
.size _Z16diffusion_globalPdS_, 8
.type _Z16diffusion_sharedPdS_,@object # @_Z16diffusion_sharedPdS_
.globl _Z16diffusion_sharedPdS_
.p2align 3, 0x0
_Z16diffusion_sharedPdS_:
.quad _Z31__device_stub__diffusion_sharedPdS_
.size _Z16diffusion_sharedPdS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f %f %f\n"
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "host:%ld\n"
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "global:%ld\n"
.size .L.str.2, 12
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "shared:%ld\n"
.size .L.str.3, 12
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "global:%f\n"
.size .L.str.5, 11
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "shared:%f\n"
.size .L.str.6, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16diffusion_globalPdS_"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16diffusion_sharedPdS_"
.size .L__unnamed_2, 25
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "n"
.size .L__unnamed_3, 2
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "theta"
.size .L__unnamed_4, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "answers"
.size .Lstr, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__diffusion_globalPdS_
.addrsig_sym _Z31__device_stub__diffusion_sharedPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym n
.addrsig_sym theta
.addrsig_sym _Z16diffusion_globalPdS_
.addrsig_sym _Z16diffusion_sharedPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime.h>
__global__ void print(int *test)
{
int id = threadIdx.x;
printf("%d: %d\n", id, test[id]);
__syncthreads();
}
int main()
{
int test_h[20], *test_d;
for(int i = 0; i < 20; i++){
test_h[i] = i;
}
size_t pitch = 0;
cudaError_t result = cudaMallocPitch((void**)&test_d, &pitch, 20*sizeof(int), 1);
result = cudaMemcpyAsync((void*)test_d, (const void*)test_h, 20*sizeof(int), cudaMemcpyHostToDevice);
print<<<1,20>>>(test_d);
cudaFree(test_d);
return 0;
} | code for sm_80
Function : _Z5printPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe40007ffe0ff */
/*0050*/ IMAD.WIDE R2, R10, R3, c[0x0][0x160] ; /* 0x000058000a027625 */
/* 0x001fca00078e0203 */
/*0060*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea2000c1e1900 */
/*0070*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0090*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*00b0*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0000660000000a00 */
/*00c0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00d0*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0041e80000100a00 */
/*00e0*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x002fc60000000000 */
/*00f0*/ MOV R11, 0x160 ; /* 0x00000160000b7802 */
/* 0x001fe40000000f00 */
/*0100*/ MOV R20, 0xe0 ; /* 0x000000e000147802 */
/* 0x000fc40000000f00 */
/*0110*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0120*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0130*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*0140*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0150*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0160*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0170*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
__global__ void print(int *test)
{
int id = threadIdx.x;
printf("%d: %d\n", id, test[id]);
__syncthreads();
}
int main()
{
int test_h[20], *test_d;
for(int i = 0; i < 20; i++){
test_h[i] = i;
}
size_t pitch = 0;
cudaError_t result = cudaMallocPitch((void**)&test_d, &pitch, 20*sizeof(int), 1);
result = cudaMemcpyAsync((void*)test_d, (const void*)test_h, 20*sizeof(int), cudaMemcpyHostToDevice);
print<<<1,20>>>(test_d);
cudaFree(test_d);
return 0;
} | .file "tmpxft_0019404e_00000000-6_memcpy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z5printPiPi
.type _Z24__device_stub__Z5printPiPi, @function
_Z24__device_stub__Z5printPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5printPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z5printPiPi, .-_Z24__device_stub__Z5printPiPi
.globl _Z5printPi
.type _Z5printPi, @function
_Z5printPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z5printPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5printPi, .-_Z5printPi
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
.L12:
movl %eax, 48(%rsp,%rax,4)
addq $1, %rax
cmpq $20, %rax
jne .L12
movq $0, 16(%rsp)
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdi
movl $1, %ecx
movl $80, %edx
call cudaMallocPitch@PLT
leaq 48(%rsp), %rsi
movl $0, %r8d
movl $1, %ecx
movl $80, %edx
movq 8(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl $20, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z24__device_stub__Z5printPiPi
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5printPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5printPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
__global__ void print(int *test)
{
int id = threadIdx.x;
printf("%d: %d\n", id, test[id]);
__syncthreads();
}
int main()
{
int test_h[20], *test_d;
for(int i = 0; i < 20; i++){
test_h[i] = i;
}
size_t pitch = 0;
cudaError_t result = cudaMallocPitch((void**)&test_d, &pitch, 20*sizeof(int), 1);
result = cudaMemcpyAsync((void*)test_d, (const void*)test_h, 20*sizeof(int), cudaMemcpyHostToDevice);
print<<<1,20>>>(test_d);
cudaFree(test_d);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void print(int *test)
{
int id = threadIdx.x;
printf("%d: %d\n", id, test[id]);
__syncthreads();
}
int main()
{
int test_h[20], *test_d;
for(int i = 0; i < 20; i++){
test_h[i] = i;
}
size_t pitch = 0;
hipError_t result = hipMallocPitch((void**)&test_d, &pitch, 20*sizeof(int), 1);
result = hipMemcpyAsync((void*)test_d, (const void*)test_h, 20*sizeof(int), hipMemcpyHostToDevice);
print<<<1,20>>>(test_d);
hipFree(test_d);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void print(int *test)
{
int id = threadIdx.x;
printf("%d: %d\n", id, test[id]);
__syncthreads();
}
int main()
{
int test_h[20], *test_d;
for(int i = 0; i < 20; i++){
test_h[i] = i;
}
size_t pitch = 0;
hipError_t result = hipMallocPitch((void**)&test_d, &pitch, 20*sizeof(int), 1);
result = hipMemcpyAsync((void*)test_d, (const void*)test_h, 20*sizeof(int), hipMemcpyHostToDevice);
print<<<1,20>>>(test_d);
hipFree(test_d);
return 0;
} | .text
.file "memcpy.hip"
.globl _Z20__device_stub__printPi # -- Begin function _Z20__device_stub__printPi
.p2align 4, 0x90
.type _Z20__device_stub__printPi,@function
_Z20__device_stub__printPi: # @_Z20__device_stub__printPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z5printPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z20__device_stub__printPi, .Lfunc_end0-_Z20__device_stub__printPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 96(%rsp,%rax,4)
incq %rax
cmpq $20, %rax
jne .LBB1_1
# %bb.2:
movq $0, 32(%rsp)
leaq 8(%rsp), %rdi
leaq 32(%rsp), %rsi
movl $80, %edx
movl $1, %ecx
callq hipMallocPitch
movq 8(%rsp), %rdi
leaq 96(%rsp), %rsi
movl $80, %edx
movl $1, %ecx
xorl %r8d, %r8d
callq hipMemcpyAsync
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 19(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 16(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z5printPi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5printPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5printPi,@object # @_Z5printPi
.section .rodata,"a",@progbits
.globl _Z5printPi
.p2align 3, 0x0
_Z5printPi:
.quad _Z20__device_stub__printPi
.size _Z5printPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5printPi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__printPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5printPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019404e_00000000-6_memcpy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z5printPiPi
.type _Z24__device_stub__Z5printPiPi, @function
_Z24__device_stub__Z5printPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5printPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z5printPiPi, .-_Z24__device_stub__Z5printPiPi
.globl _Z5printPi
.type _Z5printPi, @function
_Z5printPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z5printPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5printPi, .-_Z5printPi
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
.L12:
movl %eax, 48(%rsp,%rax,4)
addq $1, %rax
cmpq $20, %rax
jne .L12
movq $0, 16(%rsp)
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdi
movl $1, %ecx
movl $80, %edx
call cudaMallocPitch@PLT
leaq 48(%rsp), %rsi
movl $0, %r8d
movl $1, %ecx
movl $80, %edx
movq 8(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl $20, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z24__device_stub__Z5printPiPi
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5printPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5printPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "memcpy.hip"
.globl _Z20__device_stub__printPi # -- Begin function _Z20__device_stub__printPi
.p2align 4, 0x90
.type _Z20__device_stub__printPi,@function
_Z20__device_stub__printPi: # @_Z20__device_stub__printPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z5printPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z20__device_stub__printPi, .Lfunc_end0-_Z20__device_stub__printPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 96(%rsp,%rax,4)
incq %rax
cmpq $20, %rax
jne .LBB1_1
# %bb.2:
movq $0, 32(%rsp)
leaq 8(%rsp), %rdi
leaq 32(%rsp), %rsi
movl $80, %edx
movl $1, %ecx
callq hipMallocPitch
movq 8(%rsp), %rdi
leaq 96(%rsp), %rsi
movl $80, %edx
movl $1, %ecx
xorl %r8d, %r8d
callq hipMemcpyAsync
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 19(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 16(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z5printPi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5printPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5printPi,@object # @_Z5printPi
.section .rodata,"a",@progbits
.globl _Z5printPi
.p2align 3, 0x0
_Z5printPi:
.quad _Z20__device_stub__printPi
.size _Z5printPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5printPi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__printPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5printPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <math.h>
#define MAX 8192
#define LOG_MAX 13
#define BLOCK_SIZE 512
#define N 10
__host__ void fftHost(float x_r[], float x_i[])
{
float tmp_r, tmp_i ;
int i, j, i_lower ;
int stage, dft_pts, num_bf;
float pi;
pi = -2 * M_PI;
float arg, e, cos_result, sin_result;
for (stage = 1; stage <= LOG_MAX; stage++) {
dft_pts = 1 << stage;
num_bf = dft_pts / 2;
e = pi / dft_pts;
for (j = 0; j < num_bf; j++) {
arg = e * j;
cos_result = cos(arg);
sin_result = sin(arg);
for (i = j; i < MAX; i += dft_pts) {
i_lower = i + num_bf;
tmp_r = x_r[i_lower] * cos_result - x_i[i_lower] * sin_result;
tmp_i = x_i[i_lower] * cos_result + x_r[i_lower] * sin_result;
x_r[i_lower] = x_r[i] - tmp_r;
x_i[i_lower] = x_i[i] - tmp_i;
x_r[i] = x_r[i] + tmp_r;
x_i[i] = x_i[i] + tmp_i;
}
}
}
}
__global__ void fftKernel(float *dx_r, float *dx_i) {
int thread_id = blockDim.x * blockIdx.x + threadIdx.x;
float tmp_r, tmp_i;
int i, j, i_lower;
int dft_pts, num_bf;
float pi;
float arg, e, cos_result, sin_result;
pi = -2 * M_PI;
for (int stage = 1; stage <= 13; stage++) {
dft_pts = 1 << stage;
num_bf = dft_pts / 2;
e = pi / dft_pts;
if (thread_id < BLOCK_SIZE) {
int start = MAX/(2*BLOCK_SIZE) * thread_id;
for (int k = 0; k < MAX/(2*BLOCK_SIZE); k++) {
i = (start + k) + int(pow(2, stage - 1)) * ((start + k) / int(pow(2, stage - 1)));
j = i % num_bf;
arg = e * j;
cos_result = cos(arg);
sin_result = sin(arg);
i_lower = i + num_bf;
tmp_r = dx_r[i_lower] * cos_result - dx_i[i_lower] * sin_result;
tmp_i = dx_i[i_lower] * cos_result + dx_r[i_lower] * sin_result;
dx_r[i_lower] = dx_r[i] - tmp_r;
dx_i[i_lower] = dx_i[i] - tmp_i;
dx_r[i] = dx_r[i] + tmp_r;
dx_i[i] = dx_i[i] + tmp_i;
}
}
__syncthreads();
}
} | .file "tmpxft_00071cbe_00000000-6_fft_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7fftHostPfS_
.type _Z7fftHostPfS_, @function
_Z7fftHostPfS_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movq %rsi, %rbx
movl $1, 20(%rsp)
jmp .L7
.L4:
addl $1, 20(%rsp)
movl 20(%rsp), %eax
cmpl $14, %eax
je .L12
.L7:
movl $1, %r15d
movzbl 20(%rsp), %ecx
sall %cl, %r15d
movl %r15d, %eax
shrl $31, %eax
addl %r15d, %eax
sarl %eax
movl %eax, 16(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %r15d, %xmm0
movss .LC0(%rip), %xmm7
divss %xmm0, %xmm7
movss %xmm7, 4(%rsp)
cmpl $1, %r15d
jle .L4
movslq %eax, %r12
salq $2, %r12
leaq 0(%rbp,%r12), %r13
addq %rbx, %r12
movl $0, %r14d
leaq 28(%rsp), %rax
movq %rax, 8(%rsp)
.L6:
leaq 24(%rsp), %rsi
pxor %xmm0, %xmm0
cvtsi2ssl %r14d, %xmm0
mulss 4(%rsp), %xmm0
movq 8(%rsp), %rdi
call sincosf@PLT
movss 24(%rsp), %xmm4
movss 28(%rsp), %xmm3
movslq %r15d, %rdx
movq %r14, %rax
.L5:
movss 0(%r13,%rax,4), %xmm2
movss (%r12,%rax,4), %xmm0
movaps %xmm2, %xmm1
mulss %xmm4, %xmm1
movaps %xmm0, %xmm5
mulss %xmm3, %xmm5
subss %xmm5, %xmm1
mulss %xmm4, %xmm0
mulss %xmm3, %xmm2
addss %xmm2, %xmm0
movss 0(%rbp,%rax,4), %xmm2
subss %xmm1, %xmm2
movss %xmm2, 0(%r13,%rax,4)
movss (%rbx,%rax,4), %xmm2
subss %xmm0, %xmm2
movss %xmm2, (%r12,%rax,4)
addss 0(%rbp,%rax,4), %xmm1
movss %xmm1, 0(%rbp,%rax,4)
addss (%rbx,%rax,4), %xmm0
movss %xmm0, (%rbx,%rax,4)
addq %rdx, %rax
cmpl $8191, %eax
jle .L5
addq $1, %r14
cmpl %r14d, 16(%rsp)
jg .L6
jmp .L4
.L12:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z7fftHostPfS_, .-_Z7fftHostPfS_
.globl _Z30__device_stub__Z9fftKernelPfS_PfS_
.type _Z30__device_stub__Z9fftKernelPfS_PfS_, @function
_Z30__device_stub__Z9fftKernelPfS_PfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9fftKernelPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z9fftKernelPfS_PfS_, .-_Z30__device_stub__Z9fftKernelPfS_PfS_
.globl _Z9fftKernelPfS_
.type _Z9fftKernelPfS_, @function
_Z9fftKernelPfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9fftKernelPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9fftKernelPfS_, .-_Z9fftKernelPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z9fftKernelPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9fftKernelPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long -1060565029
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <math.h>
#define MAX 8192
#define LOG_MAX 13
#define BLOCK_SIZE 512
#define N 10
__host__ void fftHost(float x_r[], float x_i[])
{
float tmp_r, tmp_i ;
int i, j, i_lower ;
int stage, dft_pts, num_bf;
float pi;
pi = -2 * M_PI;
float arg, e, cos_result, sin_result;
for (stage = 1; stage <= LOG_MAX; stage++) {
dft_pts = 1 << stage;
num_bf = dft_pts / 2;
e = pi / dft_pts;
for (j = 0; j < num_bf; j++) {
arg = e * j;
cos_result = cos(arg);
sin_result = sin(arg);
for (i = j; i < MAX; i += dft_pts) {
i_lower = i + num_bf;
tmp_r = x_r[i_lower] * cos_result - x_i[i_lower] * sin_result;
tmp_i = x_i[i_lower] * cos_result + x_r[i_lower] * sin_result;
x_r[i_lower] = x_r[i] - tmp_r;
x_i[i_lower] = x_i[i] - tmp_i;
x_r[i] = x_r[i] + tmp_r;
x_i[i] = x_i[i] + tmp_i;
}
}
}
}
__global__ void fftKernel(float *dx_r, float *dx_i) {
int thread_id = blockDim.x * blockIdx.x + threadIdx.x;
float tmp_r, tmp_i;
int i, j, i_lower;
int dft_pts, num_bf;
float pi;
float arg, e, cos_result, sin_result;
pi = -2 * M_PI;
for (int stage = 1; stage <= 13; stage++) {
dft_pts = 1 << stage;
num_bf = dft_pts / 2;
e = pi / dft_pts;
if (thread_id < BLOCK_SIZE) {
int start = MAX/(2*BLOCK_SIZE) * thread_id;
for (int k = 0; k < MAX/(2*BLOCK_SIZE); k++) {
i = (start + k) + int(pow(2, stage - 1)) * ((start + k) / int(pow(2, stage - 1)));
j = i % num_bf;
arg = e * j;
cos_result = cos(arg);
sin_result = sin(arg);
i_lower = i + num_bf;
tmp_r = dx_r[i_lower] * cos_result - dx_i[i_lower] * sin_result;
tmp_i = dx_i[i_lower] * cos_result + dx_r[i_lower] * sin_result;
dx_r[i_lower] = dx_r[i] - tmp_r;
dx_i[i_lower] = dx_i[i] - tmp_i;
dx_r[i] = dx_r[i] + tmp_r;
dx_i[i] = dx_i[i] + tmp_i;
}
}
__syncthreads();
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#define MAX 8192
#define LOG_MAX 13
#define BLOCK_SIZE 512
#define N 10
__host__ void fftHost(float x_r[], float x_i[])
{
float tmp_r, tmp_i ;
int i, j, i_lower ;
int stage, dft_pts, num_bf;
float pi;
pi = -2 * M_PI;
float arg, e, cos_result, sin_result;
for (stage = 1; stage <= LOG_MAX; stage++) {
dft_pts = 1 << stage;
num_bf = dft_pts / 2;
e = pi / dft_pts;
for (j = 0; j < num_bf; j++) {
arg = e * j;
cos_result = cos(arg);
sin_result = sin(arg);
for (i = j; i < MAX; i += dft_pts) {
i_lower = i + num_bf;
tmp_r = x_r[i_lower] * cos_result - x_i[i_lower] * sin_result;
tmp_i = x_i[i_lower] * cos_result + x_r[i_lower] * sin_result;
x_r[i_lower] = x_r[i] - tmp_r;
x_i[i_lower] = x_i[i] - tmp_i;
x_r[i] = x_r[i] + tmp_r;
x_i[i] = x_i[i] + tmp_i;
}
}
}
}
__global__ void fftKernel(float *dx_r, float *dx_i) {
int thread_id = blockDim.x * blockIdx.x + threadIdx.x;
float tmp_r, tmp_i;
int i, j, i_lower;
int dft_pts, num_bf;
float pi;
float arg, e, cos_result, sin_result;
pi = -2 * M_PI;
for (int stage = 1; stage <= 13; stage++) {
dft_pts = 1 << stage;
num_bf = dft_pts / 2;
e = pi / dft_pts;
if (thread_id < BLOCK_SIZE) {
int start = MAX/(2*BLOCK_SIZE) * thread_id;
for (int k = 0; k < MAX/(2*BLOCK_SIZE); k++) {
i = (start + k) + int(pow(2, stage - 1)) * ((start + k) / int(pow(2, stage - 1)));
j = i % num_bf;
arg = e * j;
cos_result = cos(arg);
sin_result = sin(arg);
i_lower = i + num_bf;
tmp_r = dx_r[i_lower] * cos_result - dx_i[i_lower] * sin_result;
tmp_i = dx_i[i_lower] * cos_result + dx_r[i_lower] * sin_result;
dx_r[i_lower] = dx_r[i] - tmp_r;
dx_i[i_lower] = dx_i[i] - tmp_i;
dx_r[i] = dx_r[i] + tmp_r;
dx_i[i] = dx_i[i] + tmp_i;
}
}
__syncthreads();
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#define MAX 8192
#define LOG_MAX 13
#define BLOCK_SIZE 512
#define N 10
__host__ void fftHost(float x_r[], float x_i[])
{
float tmp_r, tmp_i ;
int i, j, i_lower ;
int stage, dft_pts, num_bf;
float pi;
pi = -2 * M_PI;
float arg, e, cos_result, sin_result;
for (stage = 1; stage <= LOG_MAX; stage++) {
dft_pts = 1 << stage;
num_bf = dft_pts / 2;
e = pi / dft_pts;
for (j = 0; j < num_bf; j++) {
arg = e * j;
cos_result = cos(arg);
sin_result = sin(arg);
for (i = j; i < MAX; i += dft_pts) {
i_lower = i + num_bf;
tmp_r = x_r[i_lower] * cos_result - x_i[i_lower] * sin_result;
tmp_i = x_i[i_lower] * cos_result + x_r[i_lower] * sin_result;
x_r[i_lower] = x_r[i] - tmp_r;
x_i[i_lower] = x_i[i] - tmp_i;
x_r[i] = x_r[i] + tmp_r;
x_i[i] = x_i[i] + tmp_i;
}
}
}
}
__global__ void fftKernel(float *dx_r, float *dx_i) {
int thread_id = blockDim.x * blockIdx.x + threadIdx.x;
float tmp_r, tmp_i;
int i, j, i_lower;
int dft_pts, num_bf;
float pi;
float arg, e, cos_result, sin_result;
pi = -2 * M_PI;
for (int stage = 1; stage <= 13; stage++) {
dft_pts = 1 << stage;
num_bf = dft_pts / 2;
e = pi / dft_pts;
if (thread_id < BLOCK_SIZE) {
int start = MAX/(2*BLOCK_SIZE) * thread_id;
for (int k = 0; k < MAX/(2*BLOCK_SIZE); k++) {
i = (start + k) + int(pow(2, stage - 1)) * ((start + k) / int(pow(2, stage - 1)));
j = i % num_bf;
arg = e * j;
cos_result = cos(arg);
sin_result = sin(arg);
i_lower = i + num_bf;
tmp_r = dx_r[i_lower] * cos_result - dx_i[i_lower] * sin_result;
tmp_i = dx_i[i_lower] * cos_result + dx_r[i_lower] * sin_result;
dx_r[i_lower] = dx_r[i] - tmp_r;
dx_i[i_lower] = dx_i[i] - tmp_i;
dx_r[i] = dx_r[i] + tmp_r;
dx_i[i] = dx_i[i] + tmp_i;
}
}
__syncthreads();
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9fftKernelPfS_
.globl _Z9fftKernelPfS_
.p2align 8
.type _Z9fftKernelPfS_,@function
_Z9fftKernelPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 3, v0
s_mov_b32 s33, 1
s_mov_b32 s9, 0x3fe55555
s_mov_b32 s8, 0x55555555
s_mov_b32 s11, 0x3fba6564
s_mov_b32 s10, 0x968915a9
s_mov_b32 s13, 0x3fbdee67
s_mov_b32 s12, 0x4222de17
s_mov_b32 s17, 0x3fbe25e4
s_mov_b32 s16, 0x3abe935a
s_mov_b32 s19, 0x3fc110ef
s_mov_b32 s18, 0x47e6c9c2
s_mov_b32 s21, 0x3fc3b13b
s_mov_b32 s20, 0xcfa74449
s_mov_b32 s23, 0x3fc745d1
s_mov_b32 s22, 0x71bf3c30
s_mov_b32 s25, 0x3fcc71c7
s_mov_b32 s24, 0x1c7792ce
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s2, 0xffff
s_mov_b32 s27, 0x3fd24924
s_mul_i32 s0, s15, s0
s_mov_b32 s26, 0x924920da
v_add_nc_u32_e32 v0, s0, v0
v_lshl_add_u32 v2, s0, 3, v1
s_mov_b32 s15, 0x3fd99999
s_mov_b32 s14, 0x9999999c
s_mov_b32 s29, 0x3fe62e42
v_cmp_gt_i32_e64 s0, 0x200, v0
s_mov_b32 s28, 0xfefa39ef
s_mov_b32 s31, 0x3c7abc9e
s_mov_b32 s30, 0x3b39803f
s_mov_b32 s3, 0xbfe55555
s_mov_b32 s35, 0x3c8543b0
s_mov_b32 s34, 0xd5df274d
s_mov_b32 s37, 0x3ff71547
s_mov_b32 s36, 0x652b82fe
s_mov_b32 s39, 0xbfe62e42
s_mov_b32 s41, 0xbc7abc9e
s_mov_b32 s43, 0x3e928af3
s_mov_b32 s42, 0xfca7ab0c
s_mov_b32 s45, 0x3e5ade15
s_mov_b32 s44, 0x6a5dcb37
s_mov_b32 s47, 0x3ec71dee
s_mov_b32 s46, 0x623fde64
s_mov_b32 s49, 0x3efa0199
s_mov_b32 s48, 0x7c89e6b0
s_mov_b32 s51, 0x3f2a01a0
s_mov_b32 s50, 0x14761f6e
s_mov_b32 s53, 0x3f56c16c
s_mov_b32 s52, 0x1852b7b0
s_mov_b32 s55, 0x3f811111
s_mov_b32 s54, 0x11122322
s_mov_b32 s57, 0x3fa55555
s_mov_b32 s56, 0x555502a1
s_mov_b32 s59, 0x3fc55555
s_mov_b32 s58, 0x55555511
s_mov_b32 s61, 0x3fe00000
s_mov_b32 s60, 11
s_mov_b32 s64, 0x7fffff
s_mov_b32 s65, 0xb94c1982
s_mov_b32 s66, 0x37d75334
s_branch .LBB0_2
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s67
s_add_i32 s33, s33, 1
s_waitcnt_vscnt null, 0x0
s_cmp_eq_u32 s33, 14
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_13
.LBB0_2:
s_and_saveexec_b32 s67, s0
s_cbranch_execz .LBB0_1
s_lshl_b32 s69, 1, s33
s_add_i32 s1, s33, -1
s_lshr_b32 s68, s69, 1
s_cmp_eq_u32 s1, 0
s_mov_b32 s62, 0
s_cselect_b32 s63, 0x3ff00000, 2.0
s_mov_b32 s2, s8
v_frexp_mant_f64_e32 v[0:1], s[62:63]
s_mov_b32 s38, s28
s_mov_b32 s40, s30
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, s[8:9], v[0:1]
v_cndmask_b32_e64 v3, 0, 1, vcc_lo
v_ldexp_f64 v[0:1], v[0:1], v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[3:4], v[0:1], 1.0
v_add_f64 v[9:10], v[0:1], -1.0
v_rcp_f64_e32 v[5:6], v[3:4]
v_add_f64 v[11:12], v[3:4], -1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], -v[11:12]
s_waitcnt_depctr 0xfff
v_fma_f64 v[7:8], -v[3:4], v[5:6], 1.0
v_fma_f64 v[5:6], v[7:8], v[5:6], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], -v[3:4], v[5:6], 1.0
v_fma_f64 v[5:6], v[7:8], v[5:6], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[7:8], v[9:10], v[5:6]
v_mul_f64 v[13:14], v[3:4], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[3:4], v[7:8], v[3:4], -v[13:14]
v_fma_f64 v[0:1], v[7:8], v[0:1], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[3:4], v[13:14], v[0:1]
v_add_f64 v[11:12], v[9:10], -v[3:4]
v_add_f64 v[13:14], v[3:4], -v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[9:10], v[9:10], -v[11:12]
v_add_f64 v[0:1], v[13:14], -v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[3:4], v[9:10], -v[3:4]
v_add_f64 v[0:1], v[0:1], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[11:12], v[0:1]
v_mul_f64 v[0:1], v[5:6], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[3:4], v[7:8], v[0:1]
v_add_f64 v[5:6], v[3:4], -v[7:8]
v_mul_f64 v[7:8], v[3:4], v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[0:1], v[0:1], -v[5:6]
v_fma_f64 v[5:6], v[3:4], v[3:4], -v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[9:10], v[0:1], v[0:1]
v_fma_f64 v[5:6], v[3:4], v[9:10], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[9:10], v[7:8], v[5:6]
v_fma_f64 v[11:12], v[9:10], s[12:13], s[10:11]
v_add_f64 v[7:8], v[9:10], -v[7:8]
v_mul_f64 v[17:18], v[3:4], v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[11:12], v[9:10], v[11:12], s[16:17]
v_add_f64 v[5:6], v[5:6], -v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], v[9:10], v[11:12], s[18:19]
v_fma_f64 v[11:12], v[9:10], v[11:12], s[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], v[9:10], v[11:12], s[22:23]
v_fma_f64 v[11:12], v[9:10], v[11:12], s[24:25]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], v[9:10], v[11:12], s[26:27]
v_fma_f64 v[11:12], v[9:10], v[11:12], s[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[13:14], v[9:10], v[11:12]
v_fma_f64 v[7:8], v[9:10], v[11:12], -v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[5:6], v[11:12], v[7:8]
v_add_f64 v[11:12], v[13:14], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[15:16], v[11:12], s[8:9]
v_add_f64 v[13:14], v[11:12], -v[13:14]
v_add_f64 v[19:20], v[15:16], s[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[7:8], v[7:8], -v[13:14]
v_fma_f64 v[13:14], v[9:10], v[3:4], -v[17:18]
v_add_f64 v[11:12], v[11:12], -v[19:20]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[7:8], v[7:8], s[34:35]
v_fma_f64 v[9:10], v[9:10], v[0:1], v[13:14]
v_ldexp_f64 v[0:1], v[0:1], 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[7:8], v[7:8], v[11:12]
v_fma_f64 v[5:6], v[5:6], v[3:4], v[9:10]
v_ldexp_f64 v[3:4], v[3:4], 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[9:10], v[15:16], v[7:8]
v_add_f64 v[11:12], v[17:18], v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[13:14], v[15:16], -v[9:10]
v_mul_f64 v[15:16], v[11:12], v[9:10]
v_add_f64 v[17:18], v[11:12], -v[17:18]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[7:8], v[7:8], v[13:14]
v_fma_f64 v[13:14], v[11:12], v[9:10], -v[15:16]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[5:6], -v[17:18]
v_fma_f64 v[7:8], v[11:12], v[7:8], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[5:6], v[5:6], v[9:10], v[7:8]
v_frexp_exp_i32_f64_e32 v9, s[62:63]
s_sub_i32 s63, 0, s68
v_add_f64 v[7:8], v[15:16], v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
v_cvt_f64_i32_e32 v[9:10], v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[11:12], v[3:4], v[7:8]
v_add_f64 v[13:14], v[7:8], -v[15:16]
v_mul_f64 v[15:16], v[9:10], s[28:29]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[3:4], v[11:12], -v[3:4]
v_add_f64 v[5:6], v[5:6], -v[13:14]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[13:14], v[9:10], s[28:29], -v[15:16]
v_add_f64 v[3:4], v[7:8], -v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[0:1], v[0:1], v[5:6]
v_fma_f64 v[5:6], v[9:10], s[30:31], v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[0:1], v[0:1], v[3:4]
v_add_f64 v[3:4], v[15:16], v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[7:8], v[11:12], v[0:1]
v_add_f64 v[15:16], v[3:4], -v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[9:10], v[3:4], v[7:8]
v_add_f64 v[11:12], v[7:8], -v[11:12]
v_add_f64 v[5:6], v[5:6], -v[15:16]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[13:14], v[9:10], -v[3:4]
v_add_f64 v[0:1], v[0:1], -v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[17:18], v[9:10], -v[13:14]
v_add_f64 v[7:8], v[7:8], -v[13:14]
v_add_f64 v[11:12], v[5:6], v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[3:4], v[3:4], -v[17:18]
v_add_f64 v[3:4], v[7:8], v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[7:8], v[11:12], -v[5:6]
v_add_f64 v[3:4], v[11:12], v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[11:12], v[11:12], -v[7:8]
v_add_f64 v[0:1], v[0:1], -v[7:8]
v_add_f64 v[13:14], v[9:10], v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[5:6], -v[11:12]
v_add_f64 v[7:8], v[13:14], -v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[0:1], v[0:1], v[5:6]
v_cvt_f64_i32_e32 v[5:6], s1
v_add_f64 v[3:4], v[3:4], -v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], v[3:4]
v_add_f64 v[3:4], v[13:14], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[7:8], v[3:4], -v[13:14]
v_mul_f64 v[9:10], v[3:4], v[5:6]
v_add_f64 v[0:1], v[0:1], -v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[3:4], v[5:6], v[3:4], -v[9:10]
v_cmp_class_f64_e64 vcc_lo, v[9:10], 0x204
v_fma_f64 v[0:1], v[5:6], v[0:1], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[3:4], v[9:10], v[0:1]
v_dual_cndmask_b32 v6, v4, v10 :: v_dual_cndmask_b32 v5, v3, v9
v_add_f64 v[3:4], v[3:4], -v[9:10]
s_delay_alu instid0(VALU_DEP_2)
v_mul_f64 v[7:8], v[5:6], s[36:37]
v_cmp_nlt_f64_e64 s1, 0x40900000, v[5:6]
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[5:6]|
v_cmp_ngt_f64_e64 s2, 0xc090cc00, v[5:6]
v_add_f64 v[0:1], v[0:1], -v[3:4]
v_rndne_f64_e32 v[7:8], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
s_and_b32 vcc_lo, s2, s1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[11:12], v[7:8], s[38:39], v[5:6]
v_cvt_i32_f64_e32 v15, v[7:8]
v_cvt_f32_i32_e32 v5, s69
v_fma_f64 v[11:12], v[7:8], s[40:41], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[11:12], s[44:45], s[42:43]
v_fma_f64 v[13:14], v[11:12], v[13:14], s[46:47]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[11:12], v[13:14], s[48:49]
v_fma_f64 v[13:14], v[11:12], v[13:14], s[50:51]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[11:12], v[13:14], s[52:53]
v_fma_f64 v[13:14], v[11:12], v[13:14], s[54:55]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[11:12], v[13:14], s[56:57]
v_fma_f64 v[13:14], v[11:12], v[13:14], s[58:59]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[11:12], v[13:14], s[60:61]
v_fma_f64 v[13:14], v[11:12], v[13:14], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[11:12], v[13:14], 1.0
v_ldexp_f64 v[7:8], v[7:8], v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, 0x7ff00000, v8, s1
v_cndmask_b32_e64 v4, 0, v3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, 0, v7, vcc_lo
v_fma_f64 v[0:1], v[3:4], v[0:1], v[3:4]
v_cmp_class_f64_e64 vcc_lo, v[3:4], 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v1, v1, v4 :: v_dual_cndmask_b32 v0, v0, v3
v_div_scale_f32 v3, null, v5, v5, 0xc0c90fdb
v_div_scale_f32 v6, vcc_lo, 0xc0c90fdb, v5, 0xc0c90fdb
v_cvt_i32_f64_e64 v0, |v[0:1]|
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v1, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v4, -v3, v1, 1.0
v_fmac_f32_e32 v1, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, v6, v1
v_fma_f32 v7, -v3, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v7, v1
v_fma_f32 v3, -v3, v4, v6
v_readfirstlane_b32 s1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fmas_f32 v0, v3, v1, v4
s_ashr_i32 s2, s1, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s1, s1, s2
v_div_fixup_f32 v3, v0, v5, 0xc0c90fdb
s_xor_b32 s38, s1, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s40, 0, s38
s_branch .LBB0_5
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mul_f32 v21, v9, v9 :: v_dual_and_b32 v22, 1, v10
v_dual_mul_f32 v19, v6, v6 :: v_dual_and_b32 v20, 1, v7
v_dual_fmaak_f32 v26, s66, v21, 0xbab64f3b :: v_dual_lshlrev_b32 v7, 30, v7
v_add_nc_u32_e32 v11, s68, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_dual_fmaak_f32 v23, s65, v19, 0x3c0881c4 :: v_dual_lshlrev_b32 v10, 30, v10
v_fmaak_f32 v26, v21, v26, 0x3d2aabf7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_xor_b32_e32 v5, v5, v4
v_and_b32_e32 v7, 0x80000000, v7
s_add_i32 s62, s62, 1
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_cmp_lg_u32 s62, 8
v_fmaak_f32 v26, v21, v26, 0xbf000004
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v13, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v14, vcc_lo, s7, v12, vcc_lo
v_add_co_u32 v11, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
global_load_b32 v8, v[13:14], off
v_add_co_u32 v15, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v16, vcc_lo, s5, v1, vcc_lo
s_clause 0x1
global_load_b32 v17, v[11:12], off
global_load_b32 v18, v[15:16], off
v_fmaak_f32 v23, v19, v23, 0xbe2aaa9d
v_cmp_eq_u32_e32 vcc_lo, 0, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v23, v19, v23 :: v_dual_and_b32 v10, 0x80000000, v10
v_dual_fmaak_f32 v25, s65, v21, 0x3c0881c4 :: v_dual_fmac_f32 v6, v6, v23
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v25, v21, v25, 0xbe2aaa9d
v_dual_fmaak_f32 v24, s66, v19, 0xbab64f3b :: v_dual_mul_f32 v25, v21, v25
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmaak_f32 v24, v19, v24, 0x3d2aabf7
v_fma_f32 v21, v21, v26, 1.0
v_dual_fmac_f32 v9, v9, v25 :: v_dual_fmaak_f32 v24, v19, v24, 0xbf000004
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v19, v19, v24, 1.0
v_cndmask_b32_e64 v6, -v6, v19, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v22
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_xor_b32_e32 v6, v7, v6
v_cndmask_b32_e32 v9, v21, v9, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v4, 0x1f8
v_xor3_b32 v5, v5, v10, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, 0x7fc00000, v6, vcc_lo
v_cndmask_b32_e32 v5, 0x7fc00000, v5, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_f32_e32 v6, v8, v5
s_waitcnt vmcnt(1)
v_mul_f32_e32 v5, v17, v5
v_fma_f32 v6, v4, v17, -v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v5, v4, v8
s_waitcnt vmcnt(0)
v_sub_f32_e32 v7, v18, v6
global_store_b32 v[11:12], v7, off
global_load_b32 v7, v[0:1], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v4, v7, v5
global_store_b32 v[13:14], v4, off
global_load_b32 v4, v[15:16], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v4, v6
global_store_b32 v[15:16], v4, off
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v4, v5
global_store_b32 v[0:1], v4, off
s_cbranch_scc0 .LBB0_1
.LBB0_5:
v_cvt_f32_u32_e32 v0, s38
v_add_nc_u32_e32 v4, s62, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v4, v5
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_xor_b32_e32 v6, v6, v5
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, s40, v0
v_mul_hi_u32 v1, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v1
v_mul_hi_u32 v0, v6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s38
v_sub_nc_u32_e32 v0, v6, v0
v_cvt_f32_u32_e32 v6, s68
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v1, s38, v0
v_cmp_le_u32_e32 vcc_lo, s38, v0
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v6
v_subrev_nc_u32_e32 v6, s38, v0
v_cmp_le_u32_e32 vcc_lo, s38, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_cndmask_b32_e32 v0, v0, v6, vcc_lo
v_xor_b32_e32 v0, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_nc_u32_e32 v0, v5, v0
v_mul_lo_u32 v5, s63, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v0, v4, v0, v4
v_mul_hi_u32 v5, v1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v0
v_add_nc_u32_e32 v6, v0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v1, v1, v5
v_xor_b32_e32 v5, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v5, v1
v_mul_lo_u32 v1, v1, s68
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v5, v1
v_subrev_nc_u32_e32 v5, s68, v1
v_cmp_le_u32_e32 vcc_lo, s68, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v5, vcc_lo
v_subrev_nc_u32_e32 v5, s68, v1
v_cmp_le_u32_e32 vcc_lo, s68, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v5, vcc_lo
v_xor_b32_e32 v1, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v1, v4
v_cvt_f32_i32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, v3, v1
v_and_b32_e32 v5, 0x7fffffff, v4
v_cmp_ngt_f32_e64 s69, 0x48000000, |v4|
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v8, 23, v5
v_and_or_b32 v1, v5, s64, 0x800000
s_and_saveexec_b32 s1, s69
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s70, exec_lo, s1
s_cbranch_execz .LBB0_7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[6:7], null, v1, 0xfe5163ab, 0
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v9, v7
v_add_nc_u32_e32 v7, 0xffffff88, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[11:12], null, v1, 0x3c439041, v[9:10]
v_cmp_lt_u32_e32 vcc_lo, 63, v7
v_cndmask_b32_e64 v16, 0, 0xffffffc0, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v9, v12
v_add_nc_u32_e32 v7, v16, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[12:13], null, v1, 0xdb629599, v[9:10]
v_cmp_lt_u32_e64 s1, 31, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v9, v13
v_cndmask_b32_e64 v17, 0, 0xffffffe0, s1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v6, v12, v6, vcc_lo
v_mad_u64_u32 v[13:14], null, v1, 0xf534ddc0, v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v7, v17, v7
v_cmp_lt_u32_e64 s2, 31, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v9, v14
v_mad_u64_u32 v[14:15], null, v1, 0xfc2757d1, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v9, v15
v_mad_u64_u32 v[15:16], null, v1, 0x4e441529, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v9, v16
v_mad_u64_u32 v[16:17], null, v1, 0xa2f9836e, v[9:10]
v_cndmask_b32_e64 v9, 0, 0xffffffe0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v10, v15, v13 :: v_dual_add_nc_u32 v7, v9, v7
v_dual_cndmask_b32 v16, v16, v14 :: v_dual_cndmask_b32 v15, v17, v15
v_dual_cndmask_b32 v14, v14, v12 :: v_dual_cndmask_b32 v9, v13, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v7
v_cndmask_b32_e64 v11, v16, v10, s1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v13, v15, v16, s1
v_cndmask_b32_e64 v10, v10, v14, s1
v_sub_nc_u32_e32 v15, 32, v7
v_cndmask_b32_e64 v14, v14, v9, s1
v_cndmask_b32_e64 v6, v9, v6, s1
v_cndmask_b32_e64 v13, v13, v11, s2
v_cndmask_b32_e64 v11, v11, v10, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v10, v10, v14, s2
v_cndmask_b32_e64 v6, v14, v6, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v16, v13, v11, v15
v_alignbit_b32 v12, v11, v10, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v14, v10, v6, v15
v_cndmask_b32_e32 v7, v16, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v9, v12, v11 :: v_dual_cndmask_b32 v10, v14, v10
v_bfe_u32 v11, v7, 29, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v12, v7, v9, 30
v_alignbit_b32 v9, v9, v10, 30
v_alignbit_b32 v6, v10, v6, 30
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v13, 0, v11
v_xor_b32_e32 v12, v12, v13
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v9, v9, v13
v_xor_b32_e32 v6, v6, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v14, v12
v_min_u32_e32 v14, 32, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v10, 31, v14
v_lshlrev_b32_e32 v16, 23, v14
v_alignbit_b32 v12, v12, v9, v10
v_alignbit_b32 v6, v9, v6, v10
v_lshrrev_b32_e32 v10, 29, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_alignbit_b32 v9, v12, v6, 9
v_lshlrev_b32_e32 v10, 31, v10
v_lshrrev_b32_e32 v12, 9, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_clz_i32_u32_e32 v13, v9
v_or_b32_e32 v15, 0.5, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min_u32_e32 v13, 32, v13
v_sub_nc_u32_e32 v15, v15, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v17, 31, v13
v_alignbit_b32 v6, v9, v6, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_or_b32_e32 v9, v12, v15
v_add_lshl_u32 v12, v13, v14, 23
v_lshrrev_b32_e32 v6, 9, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v13, 0x3fc90fda, v9
v_sub_nc_u32_e32 v6, v6, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v12, v9, 0x3fc90fda, -v13
v_add_nc_u32_e32 v6, 0x33000000, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v12, 0x33a22168, v9
v_or_b32_e32 v6, v6, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v12, 0x3fc90fda, v6
v_add_f32_e32 v6, v13, v12
v_lshrrev_b32_e32 v7, 30, v7
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v7, v11, v7
.LBB0_7:
s_or_saveexec_b32 s1, s70
v_mul_f32_e64 v11, 0x3f22f983, |v4|
s_xor_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v7, v11
v_fma_f32 v6, v7, 0xbfc90fda, |v4|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, 0xb3a22168, v7
v_fmac_f32_e32 v6, 0xa7c234c4, v7
v_cvt_i32_f32_e32 v7, v7
s_or_b32 exec_lo, exec_lo, s1
s_and_saveexec_b32 s1, s69
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s69, exec_lo, s1
s_cbranch_execz .LBB0_11
v_mad_u64_u32 v[9:10], null, v1, 0xfe5163ab, 0
v_mov_b32_e32 v11, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[12:13], null, v1, 0x3c439041, v[10:11]
v_mov_b32_e32 v10, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[13:14], null, v1, 0xdb629599, v[10:11]
v_add_nc_u32_e32 v8, 0xffffff88, v8
v_cmp_lt_u32_e32 vcc_lo, 63, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mov_b32_e32 v10, v14
v_cndmask_b32_e64 v17, 0, 0xffffffc0, vcc_lo
v_mad_u64_u32 v[14:15], null, v1, 0xf534ddc0, v[10:11]
v_cndmask_b32_e32 v9, v13, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v8, v17, v8
v_cmp_lt_u32_e64 s1, 31, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v18, 0, 0xffffffe0, s1
v_add_nc_u32_e32 v8, v18, v8
v_mov_b32_e32 v10, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s2, 31, v8
v_mad_u64_u32 v[15:16], null, v1, 0xfc2757d1, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v10, v16
v_mad_u64_u32 v[16:17], null, v1, 0x4e441529, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v10, v17
v_mad_u64_u32 v[17:18], null, v1, 0xa2f9836e, v[10:11]
v_cndmask_b32_e64 v1, 0, 0xffffffe0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v10, v16, v14 :: v_dual_add_nc_u32 v1, v1, v8
v_dual_cndmask_b32 v11, v17, v15 :: v_dual_cndmask_b32 v16, v18, v16
v_dual_cndmask_b32 v15, v15, v13 :: v_dual_cndmask_b32 v8, v14, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v14, 32, v1
v_cndmask_b32_e64 v12, v11, v10, s1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v11, v16, v11, s1
v_cndmask_b32_e64 v10, v10, v15, s1
v_cndmask_b32_e64 v15, v15, v8, s1
v_cmp_eq_u32_e32 vcc_lo, 0, v1
v_cndmask_b32_e64 v8, v8, v9, s1
v_cndmask_b32_e64 v11, v11, v12, s2
v_cndmask_b32_e64 v12, v12, v10, s2
v_cndmask_b32_e64 v10, v10, v15, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v8, v15, v8, s2
v_alignbit_b32 v16, v11, v12, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v13, v12, v10, v14
v_alignbit_b32 v14, v10, v8, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v1, v16, v11, vcc_lo
v_dual_cndmask_b32 v9, v13, v12 :: v_dual_cndmask_b32 v10, v14, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_bfe_u32 v11, v1, 29, 1
v_alignbit_b32 v12, v1, v9, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_alignbit_b32 v9, v9, v10, 30
v_alignbit_b32 v8, v10, v8, 30
v_sub_nc_u32_e32 v13, 0, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v12, v12, v13
v_xor_b32_e32 v9, v9, v13
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v8, v8, v13
v_clz_i32_u32_e32 v14, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v14, 32, v14
v_sub_nc_u32_e32 v10, 31, v14
v_lshlrev_b32_e32 v16, 23, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_alignbit_b32 v12, v12, v9, v10
v_alignbit_b32 v8, v9, v8, v10
v_lshrrev_b32_e32 v10, 29, v1
v_lshrrev_b32_e32 v1, 30, v1
v_alignbit_b32 v9, v12, v8, 9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v10, 31, v10
v_lshrrev_b32_e32 v12, 9, v12
v_clz_i32_u32_e32 v13, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v15, 0.5, v10
v_min_u32_e32 v13, 32, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v15, v15, v16
v_sub_nc_u32_e32 v17, 31, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v8, v9, v8, v17
v_or_b32_e32 v9, v12, v15
v_add_lshl_u32 v12, v13, v14, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v8, 9, v8
v_mul_f32_e32 v13, 0x3fc90fda, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v8, v8, v12
v_fma_f32 v12, v9, 0x3fc90fda, -v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v8, 0x33000000, v8
v_fmac_f32_e32 v12, 0x33a22168, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_or_b32_e32 v8, v8, v10
v_add_nc_u32_e32 v10, v11, v1
v_fmac_f32_e32 v12, 0x3fc90fda, v8
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v9, v13, v12
.LBB0_11:
s_and_not1_saveexec_b32 s1, s69
s_cbranch_execz .LBB0_4
v_rndne_f32_e32 v1, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v9, v1, 0xbfc90fda, |v4|
v_cvt_i32_f32_e32 v10, v1
v_fmac_f32_e32 v9, 0xb3a22168, v1
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v9, 0xa7c234c4, v1
s_branch .LBB0_4
.LBB0_13:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9fftKernelPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 27
.amdhsa_next_free_sgpr 71
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9fftKernelPfS_, .Lfunc_end0-_Z9fftKernelPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9fftKernelPfS_
.private_segment_fixed_size: 0
.sgpr_count: 73
.sgpr_spill_count: 0
.symbol: _Z9fftKernelPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 27
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#define MAX 8192
#define LOG_MAX 13
#define BLOCK_SIZE 512
#define N 10
__host__ void fftHost(float x_r[], float x_i[])
{
float tmp_r, tmp_i ;
int i, j, i_lower ;
int stage, dft_pts, num_bf;
float pi;
pi = -2 * M_PI;
float arg, e, cos_result, sin_result;
for (stage = 1; stage <= LOG_MAX; stage++) {
dft_pts = 1 << stage;
num_bf = dft_pts / 2;
e = pi / dft_pts;
for (j = 0; j < num_bf; j++) {
arg = e * j;
cos_result = cos(arg);
sin_result = sin(arg);
for (i = j; i < MAX; i += dft_pts) {
i_lower = i + num_bf;
tmp_r = x_r[i_lower] * cos_result - x_i[i_lower] * sin_result;
tmp_i = x_i[i_lower] * cos_result + x_r[i_lower] * sin_result;
x_r[i_lower] = x_r[i] - tmp_r;
x_i[i_lower] = x_i[i] - tmp_i;
x_r[i] = x_r[i] + tmp_r;
x_i[i] = x_i[i] + tmp_i;
}
}
}
}
__global__ void fftKernel(float *dx_r, float *dx_i) {
int thread_id = blockDim.x * blockIdx.x + threadIdx.x;
float tmp_r, tmp_i;
int i, j, i_lower;
int dft_pts, num_bf;
float pi;
float arg, e, cos_result, sin_result;
pi = -2 * M_PI;
for (int stage = 1; stage <= 13; stage++) {
dft_pts = 1 << stage;
num_bf = dft_pts / 2;
e = pi / dft_pts;
if (thread_id < BLOCK_SIZE) {
int start = MAX/(2*BLOCK_SIZE) * thread_id;
for (int k = 0; k < MAX/(2*BLOCK_SIZE); k++) {
i = (start + k) + int(pow(2, stage - 1)) * ((start + k) / int(pow(2, stage - 1)));
j = i % num_bf;
arg = e * j;
cos_result = cos(arg);
sin_result = sin(arg);
i_lower = i + num_bf;
tmp_r = dx_r[i_lower] * cos_result - dx_i[i_lower] * sin_result;
tmp_i = dx_i[i_lower] * cos_result + dx_r[i_lower] * sin_result;
dx_r[i_lower] = dx_r[i] - tmp_r;
dx_i[i_lower] = dx_i[i] - tmp_i;
dx_r[i] = dx_r[i] + tmp_r;
dx_i[i] = dx_i[i] + tmp_i;
}
}
__syncthreads();
}
} | .text
.file "fft_kernel.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z7fftHostPfS_
.LCPI0_0:
.long 0xc0c90fdb # float -6.28318548
.text
.globl _Z7fftHostPfS_
.p2align 4, 0x90
.type _Z7fftHostPfS_,@function
_Z7fftHostPfS_: # @_Z7fftHostPfS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq %rdi, %r14
movl $1, %ecx
jmp .LBB0_1
.p2align 4, 0x90
.LBB0_6: # in Loop: Header=BB0_1 Depth=1
movl (%rsp), %ecx # 4-byte Reload
incl %ecx
cmpl $14, %ecx
je .LBB0_7
.LBB0_1: # =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
# Child Loop BB0_4 Depth 3
movl $1, %r15d
movl %ecx, (%rsp) # 4-byte Spill
# kill: def $cl killed $cl killed $ecx
shll %cl, %r15d
movl %r15d, %eax
shrl %eax
xorps %xmm0, %xmm0
cvtsi2ss %r15d, %xmm0
movss .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movss %xmm1, 4(%rsp) # 4-byte Spill
cmpl $1, %eax
leaq (%rbx,%rax,4), %r12
leaq (%r14,%rax,4), %r13
# kill: def $eax killed $eax killed $rax def $rax
adcl $0, %eax
movq %rax, 16(%rsp) # 8-byte Spill
xorl %ebp, %ebp
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=2
incq %rbp
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB0_6
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_4 Depth 3
xorps %xmm0, %xmm0
cvtsi2ss %ebp, %xmm0
mulss 4(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, 12(%rsp) # 4-byte Spill
callq cosf
movss %xmm0, 8(%rsp) # 4-byte Spill
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq sinf
movss 8(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
cmpl $8191, %ebp # imm = 0x1FFF
ja .LBB0_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB0_2 Depth=2
movq %rbp, %rax
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# Parent Loop BB0_1 Depth=1
# Parent Loop BB0_2 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r13,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movaps %xmm5, %xmm2
mulss %xmm1, %xmm2
movss (%r12,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
movaps %xmm0, %xmm4
mulss %xmm3, %xmm4
subss %xmm4, %xmm2
mulss %xmm5, %xmm3
mulss %xmm0, %xmm1
addss %xmm3, %xmm1
movss (%r14,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
subss %xmm2, %xmm3
movss %xmm3, (%r13,%rax,4)
movss (%rbx,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
subss %xmm1, %xmm3
movss %xmm3, (%r12,%rax,4)
addss (%r14,%rax,4), %xmm2
movss %xmm2, (%r14,%rax,4)
addss (%rbx,%rax,4), %xmm1
movss %xmm1, (%rbx,%rax,4)
addq %r15, %rax
cmpq $8192, %rax # imm = 0x2000
jb .LBB0_4
jmp .LBB0_5
.LBB0_7:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z7fftHostPfS_, .Lfunc_end0-_Z7fftHostPfS_
.cfi_endproc
# -- End function
.globl _Z24__device_stub__fftKernelPfS_ # -- Begin function _Z24__device_stub__fftKernelPfS_
.p2align 4, 0x90
.type _Z24__device_stub__fftKernelPfS_,@function
_Z24__device_stub__fftKernelPfS_: # @_Z24__device_stub__fftKernelPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9fftKernelPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z24__device_stub__fftKernelPfS_, .Lfunc_end1-_Z24__device_stub__fftKernelPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9fftKernelPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9fftKernelPfS_,@object # @_Z9fftKernelPfS_
.section .rodata,"a",@progbits
.globl _Z9fftKernelPfS_
.p2align 3, 0x0
_Z9fftKernelPfS_:
.quad _Z24__device_stub__fftKernelPfS_
.size _Z9fftKernelPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9fftKernelPfS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__fftKernelPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9fftKernelPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00071cbe_00000000-6_fft_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7fftHostPfS_
.type _Z7fftHostPfS_, @function
_Z7fftHostPfS_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movq %rsi, %rbx
movl $1, 20(%rsp)
jmp .L7
.L4:
addl $1, 20(%rsp)
movl 20(%rsp), %eax
cmpl $14, %eax
je .L12
.L7:
movl $1, %r15d
movzbl 20(%rsp), %ecx
sall %cl, %r15d
movl %r15d, %eax
shrl $31, %eax
addl %r15d, %eax
sarl %eax
movl %eax, 16(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %r15d, %xmm0
movss .LC0(%rip), %xmm7
divss %xmm0, %xmm7
movss %xmm7, 4(%rsp)
cmpl $1, %r15d
jle .L4
movslq %eax, %r12
salq $2, %r12
leaq 0(%rbp,%r12), %r13
addq %rbx, %r12
movl $0, %r14d
leaq 28(%rsp), %rax
movq %rax, 8(%rsp)
.L6:
leaq 24(%rsp), %rsi
pxor %xmm0, %xmm0
cvtsi2ssl %r14d, %xmm0
mulss 4(%rsp), %xmm0
movq 8(%rsp), %rdi
call sincosf@PLT
movss 24(%rsp), %xmm4
movss 28(%rsp), %xmm3
movslq %r15d, %rdx
movq %r14, %rax
.L5:
movss 0(%r13,%rax,4), %xmm2
movss (%r12,%rax,4), %xmm0
movaps %xmm2, %xmm1
mulss %xmm4, %xmm1
movaps %xmm0, %xmm5
mulss %xmm3, %xmm5
subss %xmm5, %xmm1
mulss %xmm4, %xmm0
mulss %xmm3, %xmm2
addss %xmm2, %xmm0
movss 0(%rbp,%rax,4), %xmm2
subss %xmm1, %xmm2
movss %xmm2, 0(%r13,%rax,4)
movss (%rbx,%rax,4), %xmm2
subss %xmm0, %xmm2
movss %xmm2, (%r12,%rax,4)
addss 0(%rbp,%rax,4), %xmm1
movss %xmm1, 0(%rbp,%rax,4)
addss (%rbx,%rax,4), %xmm0
movss %xmm0, (%rbx,%rax,4)
addq %rdx, %rax
cmpl $8191, %eax
jle .L5
addq $1, %r14
cmpl %r14d, 16(%rsp)
jg .L6
jmp .L4
.L12:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z7fftHostPfS_, .-_Z7fftHostPfS_
.globl _Z30__device_stub__Z9fftKernelPfS_PfS_
.type _Z30__device_stub__Z9fftKernelPfS_PfS_, @function
_Z30__device_stub__Z9fftKernelPfS_PfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9fftKernelPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z9fftKernelPfS_PfS_, .-_Z30__device_stub__Z9fftKernelPfS_PfS_
.globl _Z9fftKernelPfS_
.type _Z9fftKernelPfS_, @function
_Z9fftKernelPfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9fftKernelPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9fftKernelPfS_, .-_Z9fftKernelPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z9fftKernelPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9fftKernelPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long -1060565029
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "fft_kernel.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z7fftHostPfS_
.LCPI0_0:
.long 0xc0c90fdb # float -6.28318548
.text
.globl _Z7fftHostPfS_
.p2align 4, 0x90
.type _Z7fftHostPfS_,@function
_Z7fftHostPfS_: # @_Z7fftHostPfS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq %rdi, %r14
movl $1, %ecx
jmp .LBB0_1
.p2align 4, 0x90
.LBB0_6: # in Loop: Header=BB0_1 Depth=1
movl (%rsp), %ecx # 4-byte Reload
incl %ecx
cmpl $14, %ecx
je .LBB0_7
.LBB0_1: # =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
# Child Loop BB0_4 Depth 3
movl $1, %r15d
movl %ecx, (%rsp) # 4-byte Spill
# kill: def $cl killed $cl killed $ecx
shll %cl, %r15d
movl %r15d, %eax
shrl %eax
xorps %xmm0, %xmm0
cvtsi2ss %r15d, %xmm0
movss .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movss %xmm1, 4(%rsp) # 4-byte Spill
cmpl $1, %eax
leaq (%rbx,%rax,4), %r12
leaq (%r14,%rax,4), %r13
# kill: def $eax killed $eax killed $rax def $rax
adcl $0, %eax
movq %rax, 16(%rsp) # 8-byte Spill
xorl %ebp, %ebp
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=2
incq %rbp
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB0_6
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_4 Depth 3
xorps %xmm0, %xmm0
cvtsi2ss %ebp, %xmm0
mulss 4(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, 12(%rsp) # 4-byte Spill
callq cosf
movss %xmm0, 8(%rsp) # 4-byte Spill
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq sinf
movss 8(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
cmpl $8191, %ebp # imm = 0x1FFF
ja .LBB0_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB0_2 Depth=2
movq %rbp, %rax
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# Parent Loop BB0_1 Depth=1
# Parent Loop BB0_2 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r13,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movaps %xmm5, %xmm2
mulss %xmm1, %xmm2
movss (%r12,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
movaps %xmm0, %xmm4
mulss %xmm3, %xmm4
subss %xmm4, %xmm2
mulss %xmm5, %xmm3
mulss %xmm0, %xmm1
addss %xmm3, %xmm1
movss (%r14,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
subss %xmm2, %xmm3
movss %xmm3, (%r13,%rax,4)
movss (%rbx,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
subss %xmm1, %xmm3
movss %xmm3, (%r12,%rax,4)
addss (%r14,%rax,4), %xmm2
movss %xmm2, (%r14,%rax,4)
addss (%rbx,%rax,4), %xmm1
movss %xmm1, (%rbx,%rax,4)
addq %r15, %rax
cmpq $8192, %rax # imm = 0x2000
jb .LBB0_4
jmp .LBB0_5
.LBB0_7:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z7fftHostPfS_, .Lfunc_end0-_Z7fftHostPfS_
.cfi_endproc
# -- End function
.globl _Z24__device_stub__fftKernelPfS_ # -- Begin function _Z24__device_stub__fftKernelPfS_
.p2align 4, 0x90
.type _Z24__device_stub__fftKernelPfS_,@function
_Z24__device_stub__fftKernelPfS_: # @_Z24__device_stub__fftKernelPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9fftKernelPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z24__device_stub__fftKernelPfS_, .Lfunc_end1-_Z24__device_stub__fftKernelPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9fftKernelPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9fftKernelPfS_,@object # @_Z9fftKernelPfS_
.section .rodata,"a",@progbits
.globl _Z9fftKernelPfS_
.p2align 3, 0x0
_Z9fftKernelPfS_:
.quad _Z24__device_stub__fftKernelPfS_
.size _Z9fftKernelPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9fftKernelPfS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__fftKernelPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9fftKernelPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
static void HandleError( cudaError_t err, const char *file, int line ) {
if (err != cudaSuccess) {
printf( "%s in %s at line %d\n", cudaGetErrorString( err ), file, line );
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
// Each block takes care of 1024 elements
__global__
void global_reduce(float* gpu_out, float* gpu_in){
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int tidx = threadIdx.x;
int s = blockDim.x/2;
while(s > 0 ){
if(tidx < s){
gpu_in[tid] += gpu_in[tid + s];
}
s >>= 1;
__syncthreads();
}
// only thread 0 writes result for this block back to global mem
if(tidx == 0){
gpu_out[blockIdx.x] = gpu_in[tid];
}
}
__global__
void shmem_reduce(float* gpu_out, const float* gpu_in){
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int tidx = threadIdx.x;
const int size = 1024;
__shared__
float smem[size];
if(tidx < size){
smem[tidx] = gpu_in[tid];
}
__syncthreads();
int s = size/2;
while(s > 0 ){
if(tidx < s){
smem[tidx] += smem[tidx + s];
}
s >>= 1;
__syncthreads();
}
// only thread 0 writes result for this block back to global mem
if(tidx == 0){
gpu_out[blockIdx.x] = smem[tidx];
}
}
void reduce(float *d_out, float *d_intermediate, float * d_in,
int size, bool usesSharedMemory){
const int maxThreadsPerBlock = 1024;
int threads = maxThreadsPerBlock;
int blocks = size / maxThreadsPerBlock;
if(usesSharedMemory){
shmem_reduce<<<blocks, threads>>>(d_intermediate, d_in);
}
else{
global_reduce<<<blocks, threads>>>(d_intermediate, d_in);
}
threads = maxThreadsPerBlock;
blocks = 1;
if(usesSharedMemory){
shmem_reduce<<<blocks, threads>>>(d_out, d_intermediate);
}
else{
global_reduce<<<blocks, threads>>>(d_out, d_intermediate);
}
}
int main(){
int dev = 0;
cudaSetDevice(dev);
const int ARRAY_SIZE = 1 << 20;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
// generate the input array on the host
float h_in[ARRAY_SIZE];
float sum = 0.0f;
for(int i = 0; i < ARRAY_SIZE; i++) {
// generate random float in [-1.0f, 1.0f]
h_in[i] = -1.0f + (float)random()/((float)RAND_MAX/2.0f);
sum += h_in[i];
}
printf("sum using serial reduce: %f\n", sum);
// declare GPU memory pointers
float * d_in, * d_intermediate, * d_out;
// allocate GPU memory
HANDLE_ERROR(cudaMalloc((void **) &d_in, ARRAY_BYTES));
HANDLE_ERROR(cudaMalloc((void **) &d_intermediate, ARRAY_BYTES)); // overallocated
HANDLE_ERROR(cudaMalloc((void **) &d_out, sizeof(float)));
// transfer the input array to the GPU
HANDLE_ERROR(cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice));
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
printf("Running global mamory reduce\n");
cudaEventRecord(start, 0);
const int itt = 100;
for (int i = 0; i < itt; i++){
HANDLE_ERROR(cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice));
reduce(d_out, d_intermediate, d_in, ARRAY_SIZE, false);
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
elapsedTime /= (float)itt; // 100 trials
// copy back the sum from GPU
float h_out;
HANDLE_ERROR(cudaMemcpy(&h_out, d_out, sizeof(float), cudaMemcpyDeviceToHost));
printf("sum using global memory kernel: %f\n", h_out);
printf("average time elapsed using global memory kernel: %f\n", elapsedTime);
printf("Running shared mamory reduce\n");
HANDLE_ERROR(cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice));
cudaEventRecord(start, 0);
for (int i = 0; i < itt; i++){
reduce(d_out, d_intermediate, d_in, ARRAY_SIZE, true);
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
elapsedTime /= (float)itt; // 100 trials
// copy back the sum from GPU
HANDLE_ERROR(cudaMemcpy(&h_out, d_out, sizeof(float), cudaMemcpyDeviceToHost));
printf("sum using shared memory kernel: %f\n", h_out);
printf("average time elapsed using shared memory kernel: %f\n", elapsedTime);
// free GPU memory allocation
cudaFree(d_in);
cudaFree(d_intermediate);
cudaFree(d_out);
return 0;
} | code for sm_80
Function : _Z12shmem_reducePfPKf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0xe0 ; /* 0x000000a000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0050*/ ISETP.GE.AND P1, PT, R3.reuse, 0x400, PT ; /* 0x000004000300780c */
/* 0x041fe40003f26270 */
/*0060*/ ISETP.GT.AND P0, PT, R3, 0x1ff, PT ; /* 0x000001ff0300780c */
/* 0x000fd60003f04270 */
/*0070*/ @P1 BRA 0xd0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x002fe200000001ff */
/*0090*/ IMAD R4, R0, c[0x0][0x0], R3 ; /* 0x0000000000047a24 */
/* 0x000fd200078e0203 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fcc00078e0205 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ STS [R3.X4], R4 ; /* 0x0000000403007388 */
/* 0x0041e40000004800 */
/*00d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*00f0*/ ISETP.GT.AND P1, PT, R3, 0xff, PT ; /* 0x000000ff0300780c */
/* 0x000fca0003f24270 */
/*0100*/ @!P0 LDS R2, [R3.X4] ; /* 0x0000000003028984 */
/* 0x000fe80000004800 */
/*0110*/ @!P0 LDS R5, [R3.X4+0x800] ; /* 0x0008000003058984 */
/* 0x000e640000004800 */
/*0120*/ @!P0 FADD R2, R2, R5 ; /* 0x0000000502028221 */
/* 0x002fca0000000000 */
/*0130*/ @!P0 STS [R3.X4], R2 ; /* 0x0000000203008388 */
/* 0x000fe80000004800 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0150*/ ISETP.GT.AND P0, PT, R3, 0x7f, PT ; /* 0x0000007f0300780c */
/* 0x000fca0003f04270 */
/*0160*/ @!P1 LDS R4, [R3.X4] ; /* 0x0000000003049984 */
/* 0x001fe80000004800 */
/*0170*/ @!P1 LDS R5, [R3.X4+0x400] ; /* 0x0004000003059984 */
/* 0x000e240000004800 */
/*0180*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*0190*/ @!P1 STS [R3.X4], R4 ; /* 0x0000000403009388 */
/* 0x000fe80000004800 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01b0*/ ISETP.GT.AND P1, PT, R3, 0x3f, PT ; /* 0x0000003f0300780c */
/* 0x000fca0003f24270 */
/*01c0*/ @!P0 LDS R5, [R3.X4] ; /* 0x0000000003058984 */
/* 0x000fe80000004800 */
/*01d0*/ @!P0 LDS R6, [R3.X4+0x200] ; /* 0x0002000003068984 */
/* 0x000e240000004800 */
/*01e0*/ @!P0 FADD R6, R5, R6 ; /* 0x0000000605068221 */
/* 0x001fca0000000000 */
/*01f0*/ @!P0 STS [R3.X4], R6 ; /* 0x0000000603008388 */
/* 0x000fe80000004800 */
/*0200*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0210*/ ISETP.GT.AND P0, PT, R3, 0x1f, PT ; /* 0x0000001f0300780c */
/* 0x000fca0003f04270 */
/*0220*/ @!P1 LDS R2, [R3.X4] ; /* 0x0000000003029984 */
/* 0x000fe80000004800 */
/*0230*/ @!P1 LDS R5, [R3.X4+0x100] ; /* 0x0001000003059984 */
/* 0x000e240000004800 */
/*0240*/ @!P1 FADD R2, R2, R5 ; /* 0x0000000502029221 */
/* 0x001fca0000000000 */
/*0250*/ @!P1 STS [R3.X4], R2 ; /* 0x0000000203009388 */
/* 0x000fe80000004800 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0270*/ ISETP.GT.AND P1, PT, R3, 0xf, PT ; /* 0x0000000f0300780c */
/* 0x000fca0003f24270 */
/*0280*/ @!P0 LDS R4, [R3.X4] ; /* 0x0000000003048984 */
/* 0x000fe80000004800 */
/*0290*/ @!P0 LDS R5, [R3.X4+0x80] ; /* 0x0000800003058984 */
/* 0x000e240000004800 */
/*02a0*/ @!P0 FADD R4, R4, R5 ; /* 0x0000000504048221 */
/* 0x001fca0000000000 */
/*02b0*/ @!P0 STS [R3.X4], R4 ; /* 0x0000000403008388 */
/* 0x000fe80000004800 */
/*02c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02d0*/ ISETP.GT.AND P0, PT, R3, 0x7, PT ; /* 0x000000070300780c */
/* 0x000fca0003f04270 */
/*02e0*/ @!P1 LDS R5, [R3.X4] ; /* 0x0000000003059984 */
/* 0x000fe80000004800 */
/*02f0*/ @!P1 LDS R6, [R3.X4+0x40] ; /* 0x0000400003069984 */
/* 0x000e240000004800 */
/*0300*/ @!P1 FADD R6, R5, R6 ; /* 0x0000000605069221 */
/* 0x001fca0000000000 */
/*0310*/ @!P1 STS [R3.X4], R6 ; /* 0x0000000603009388 */
/* 0x000fe80000004800 */
/*0320*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0330*/ ISETP.GT.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fca0003f24270 */
/*0340*/ @!P0 LDS R2, [R3.X4] ; /* 0x0000000003028984 */
/* 0x000fe80000004800 */
/*0350*/ @!P0 LDS R5, [R3.X4+0x20] ; /* 0x0000200003058984 */
/* 0x000e240000004800 */
/*0360*/ @!P0 FADD R2, R2, R5 ; /* 0x0000000502028221 */
/* 0x001fca0000000000 */
/*0370*/ @!P0 STS [R3.X4], R2 ; /* 0x0000000203008388 */
/* 0x000fe80000004800 */
/*0380*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0390*/ ISETP.GT.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fca0003f04270 */
/*03a0*/ @!P1 LDS R4, [R3.X4] ; /* 0x0000000003049984 */
/* 0x000fe80000004800 */
/*03b0*/ @!P1 LDS R5, [R3.X4+0x10] ; /* 0x0000100003059984 */
/* 0x000e240000004800 */
/*03c0*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*03d0*/ @!P1 STS [R3.X4], R4 ; /* 0x0000000403009388 */
/* 0x000fe80000004800 */
/*03e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03f0*/ ISETP.GT.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fca0003f24270 */
/*0400*/ @!P0 LDS R5, [R3.X4] ; /* 0x0000000003058984 */
/* 0x000fe80000004800 */
/*0410*/ @!P0 LDS R6, [R3.X4+0x8] ; /* 0x0000080003068984 */
/* 0x000e240000004800 */
/*0420*/ @!P0 FADD R6, R5, R6 ; /* 0x0000000605068221 */
/* 0x001fca0000000000 */
/*0430*/ @!P0 STS [R3.X4], R6 ; /* 0x0000000603008388 */
/* 0x000fe80000004800 */
/*0440*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0450*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fca0003f05270 */
/*0460*/ @!P1 LDS R2, [R3.X4] ; /* 0x0000000003029984 */
/* 0x000fe80000004800 */
/*0470*/ @!P1 LDS R5, [R3.X4+0x4] ; /* 0x0000040003059984 */
/* 0x000e240000004800 */
/*0480*/ @!P1 FADD R2, R2, R5 ; /* 0x0000000502029221 */
/* 0x001fca0000000000 */
/*0490*/ @!P1 STS [R3.X4], R2 ; /* 0x0000000203009388 */
/* 0x0001e80000004800 */
/*04a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*04c0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x001e220000000800 */
/*04d0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*04e0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0003 */
/*04f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ BRA 0x510; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13global_reducePfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0040*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0070*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*0080*/ IMAD R2, R6, c[0x0][0x0], R8 ; /* 0x0000000006027a24 */
/* 0x001fc800078e0208 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fd000078e0203 */
/*00a0*/ @!P0 BRA 0x190 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*00b0*/ MOV R7, UR4 ; /* 0x0000000400077c02 */
/* 0x000fc80008000f00 */
/*00c0*/ ISETP.GE.AND P0, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fe20003f06270 */
/*00d0*/ BSSY B0, 0x150 ; /* 0x0000007000007945 */
/* 0x000fd80003800000 */
/*00e0*/ @P0 BRA 0x140 ; /* 0x0000005000000947 */
/* 0x001fea0003800000 */
/*00f0*/ IMAD.WIDE R4, R7, 0x4, R2 ; /* 0x0000000407047825 */
/* 0x000fe200078e0202 */
/*0100*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000eaa000c1e1900 */
/*0110*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea4000c1e1900 */
/*0120*/ FADD R9, R0, R5 ; /* 0x0000000500097221 */
/* 0x004fca0000000000 */
/*0130*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e4000c101906 */
/*0140*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0150*/ SHF.R.U32.HI R7, RZ, 0x1, R7 ; /* 0x00000001ff077819 */
/* 0x000fe20000011607 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0170*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0180*/ @P0 BRA 0xc0 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*0190*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*01a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01b0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x001ea2000c1e1900 */
/*01c0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*01d0*/ IMAD.WIDE.U32 R4, R6, R5, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fca00078e0005 */
/*01e0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101906 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
static void HandleError( cudaError_t err, const char *file, int line ) {
if (err != cudaSuccess) {
printf( "%s in %s at line %d\n", cudaGetErrorString( err ), file, line );
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
// Each block takes care of 1024 elements
__global__
void global_reduce(float* gpu_out, float* gpu_in){
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int tidx = threadIdx.x;
int s = blockDim.x/2;
while(s > 0 ){
if(tidx < s){
gpu_in[tid] += gpu_in[tid + s];
}
s >>= 1;
__syncthreads();
}
// only thread 0 writes result for this block back to global mem
if(tidx == 0){
gpu_out[blockIdx.x] = gpu_in[tid];
}
}
__global__
void shmem_reduce(float* gpu_out, const float* gpu_in){
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int tidx = threadIdx.x;
const int size = 1024;
__shared__
float smem[size];
if(tidx < size){
smem[tidx] = gpu_in[tid];
}
__syncthreads();
int s = size/2;
while(s > 0 ){
if(tidx < s){
smem[tidx] += smem[tidx + s];
}
s >>= 1;
__syncthreads();
}
// only thread 0 writes result for this block back to global mem
if(tidx == 0){
gpu_out[blockIdx.x] = smem[tidx];
}
}
void reduce(float *d_out, float *d_intermediate, float * d_in,
int size, bool usesSharedMemory){
const int maxThreadsPerBlock = 1024;
int threads = maxThreadsPerBlock;
int blocks = size / maxThreadsPerBlock;
if(usesSharedMemory){
shmem_reduce<<<blocks, threads>>>(d_intermediate, d_in);
}
else{
global_reduce<<<blocks, threads>>>(d_intermediate, d_in);
}
threads = maxThreadsPerBlock;
blocks = 1;
if(usesSharedMemory){
shmem_reduce<<<blocks, threads>>>(d_out, d_intermediate);
}
else{
global_reduce<<<blocks, threads>>>(d_out, d_intermediate);
}
}
int main(){
int dev = 0;
cudaSetDevice(dev);
const int ARRAY_SIZE = 1 << 20;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
// generate the input array on the host
float h_in[ARRAY_SIZE];
float sum = 0.0f;
for(int i = 0; i < ARRAY_SIZE; i++) {
// generate random float in [-1.0f, 1.0f]
h_in[i] = -1.0f + (float)random()/((float)RAND_MAX/2.0f);
sum += h_in[i];
}
printf("sum using serial reduce: %f\n", sum);
// declare GPU memory pointers
float * d_in, * d_intermediate, * d_out;
// allocate GPU memory
HANDLE_ERROR(cudaMalloc((void **) &d_in, ARRAY_BYTES));
HANDLE_ERROR(cudaMalloc((void **) &d_intermediate, ARRAY_BYTES)); // overallocated
HANDLE_ERROR(cudaMalloc((void **) &d_out, sizeof(float)));
// transfer the input array to the GPU
HANDLE_ERROR(cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice));
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
printf("Running global mamory reduce\n");
cudaEventRecord(start, 0);
const int itt = 100;
for (int i = 0; i < itt; i++){
HANDLE_ERROR(cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice));
reduce(d_out, d_intermediate, d_in, ARRAY_SIZE, false);
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
elapsedTime /= (float)itt; // 100 trials
// copy back the sum from GPU
float h_out;
HANDLE_ERROR(cudaMemcpy(&h_out, d_out, sizeof(float), cudaMemcpyDeviceToHost));
printf("sum using global memory kernel: %f\n", h_out);
printf("average time elapsed using global memory kernel: %f\n", elapsedTime);
printf("Running shared mamory reduce\n");
HANDLE_ERROR(cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice));
cudaEventRecord(start, 0);
for (int i = 0; i < itt; i++){
reduce(d_out, d_intermediate, d_in, ARRAY_SIZE, true);
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
elapsedTime /= (float)itt; // 100 trials
// copy back the sum from GPU
HANDLE_ERROR(cudaMemcpy(&h_out, d_out, sizeof(float), cudaMemcpyDeviceToHost));
printf("sum using shared memory kernel: %f\n", h_out);
printf("average time elapsed using shared memory kernel: %f\n", elapsedTime);
// free GPU memory allocation
cudaFree(d_in);
cudaFree(d_intermediate);
cudaFree(d_out);
return 0;
} | .file "tmpxft_00107e13_00000000-6_reduce.cudafe1.cpp"
.text
#APP
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s in %s at line %d\n"
#NO_APP
.text
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB2057:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _ZL11HandleError9cudaErrorPKci, .-_ZL11HandleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z13global_reducePfS_PfS_
.type _Z35__device_stub__Z13global_reducePfS_PfS_, @function
_Z35__device_stub__Z13global_reducePfS_PfS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13global_reducePfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z13global_reducePfS_PfS_, .-_Z35__device_stub__Z13global_reducePfS_PfS_
.globl _Z13global_reducePfS_
.type _Z13global_reducePfS_, @function
_Z13global_reducePfS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13global_reducePfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13global_reducePfS_, .-_Z13global_reducePfS_
.globl _Z35__device_stub__Z12shmem_reducePfPKfPfPKf
.type _Z35__device_stub__Z12shmem_reducePfPKfPfPKf, @function
_Z35__device_stub__Z12shmem_reducePfPKfPfPKf:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12shmem_reducePfPKf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z35__device_stub__Z12shmem_reducePfPKfPfPKf, .-_Z35__device_stub__Z12shmem_reducePfPKfPfPKf
.globl _Z12shmem_reducePfPKf
.type _Z12shmem_reducePfPKf, @function
_Z12shmem_reducePfPKf:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12shmem_reducePfPKfPfPKf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z12shmem_reducePfPKf, .-_Z12shmem_reducePfPKf
.globl _Z6reducePfS_S_ib
.type _Z6reducePfS_S_ib, @function
_Z6reducePfS_S_ib:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %rbx
movq %rdx, %r12
leal 1023(%rcx), %eax
testl %ecx, %ecx
cmovns %ecx, %eax
sarl $10, %eax
testb %r8b, %r8b
je .L26
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L27:
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L25:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
movq %r12, %rsi
movq %rbx, %rdi
call _Z35__device_stub__Z12shmem_reducePfPKfPfPKf
jmp .L27
.L26:
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L30:
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L25
movq %rbx, %rsi
movq %rbp, %rdi
call _Z35__device_stub__Z13global_reducePfS_PfS_
jmp .L25
.L39:
movq %r12, %rsi
movq %rbx, %rdi
call _Z35__device_stub__Z13global_reducePfS_PfS_
jmp .L30
.L38:
movq %rbx, %rsi
movq %rbp, %rdi
call _Z35__device_stub__Z12shmem_reducePfPKfPfPKf
jmp .L25
.cfi_endproc
.LFE2058:
.size _Z6reducePfS_S_ib, .-_Z6reducePfS_S_ib
.section .rodata.str1.1
.LC4:
.string "sum using serial reduce: %f\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "/home/ubuntu/Datasets/stackv2/train-structured/amiremadz/cuda-codes/master/reduce/reduce.cu"
.section .rodata.str1.1
.LC6:
.string "Running global mamory reduce\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "sum using global memory kernel: %f\n"
.align 8
.LC9:
.string "average time elapsed using global memory kernel: %f\n"
.section .rodata.str1.1
.LC10:
.string "Running shared mamory reduce\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "sum using shared memory kernel: %f\n"
.align 8
.LC12:
.string "average time elapsed using shared memory kernel: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
leaq -4194304(%rsp), %r11
.cfi_def_cfa 11, 4194328
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $88, %rsp
.cfi_def_cfa_offset 4194416
movq %fs:40, %rax
movq %rax, 4194376(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
leaq 64(%rsp), %rbx
leaq 4194368(%rsp), %rbp
movl $0x00000000, 12(%rsp)
.L41:
call random@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
mulss .LC2(%rip), %xmm0
subss .LC3(%rip), %xmm0
movss %xmm0, (%rbx)
addss 12(%rsp), %xmm0
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L41
cvtss2sd %xmm0, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $114, %edx
leaq .LC5(%rip), %rbx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 32(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $115, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $116, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $4194304, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $119, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $100, %ebx
leaq .LC5(%rip), %rbp
.L42:
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $4194304, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $129, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %r8d
movl $1048576, %ecx
movq 24(%rsp), %rdx
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z6reducePfS_S_ib
subl $1, %ebx
jne .L42
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 16(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 16(%rsp), %xmm0
divss .LC7(%rip), %xmm0
movss %xmm0, 16(%rsp)
leaq 20(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 40(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
movl $141, %edx
leaq .LC5(%rip), %rbx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 16(%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $4194304, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $147, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $100, %ebx
.L43:
movl $1, %r8d
movl $1048576, %ecx
movq 24(%rsp), %rdx
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z6reducePfS_S_ib
subl $1, %ebx
jne .L43
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 16(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 16(%rsp), %xmm0
divss .LC7(%rip), %xmm0
movss %xmm0, 16(%rsp)
leaq 20(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 40(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
movl $160, %edx
leaq .LC5(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 16(%rsp), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 4194376(%rsp), %rax
subq %fs:40, %rax
jne .L49
movl $0, %eax
addq $4194392, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z12shmem_reducePfPKf"
.LC14:
.string "_Z13global_reducePfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z12shmem_reducePfPKf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z13global_reducePfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 813694976
.align 4
.LC3:
.long 1065353216
.align 4
.LC7:
.long 1120403456
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
static void HandleError( cudaError_t err, const char *file, int line ) {
if (err != cudaSuccess) {
printf( "%s in %s at line %d\n", cudaGetErrorString( err ), file, line );
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
// Each block takes care of 1024 elements
__global__
void global_reduce(float* gpu_out, float* gpu_in){
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int tidx = threadIdx.x;
int s = blockDim.x/2;
while(s > 0 ){
if(tidx < s){
gpu_in[tid] += gpu_in[tid + s];
}
s >>= 1;
__syncthreads();
}
// only thread 0 writes result for this block back to global mem
if(tidx == 0){
gpu_out[blockIdx.x] = gpu_in[tid];
}
}
__global__
void shmem_reduce(float* gpu_out, const float* gpu_in){
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int tidx = threadIdx.x;
const int size = 1024;
__shared__
float smem[size];
if(tidx < size){
smem[tidx] = gpu_in[tid];
}
__syncthreads();
int s = size/2;
while(s > 0 ){
if(tidx < s){
smem[tidx] += smem[tidx + s];
}
s >>= 1;
__syncthreads();
}
// only thread 0 writes result for this block back to global mem
if(tidx == 0){
gpu_out[blockIdx.x] = smem[tidx];
}
}
void reduce(float *d_out, float *d_intermediate, float * d_in,
int size, bool usesSharedMemory){
const int maxThreadsPerBlock = 1024;
int threads = maxThreadsPerBlock;
int blocks = size / maxThreadsPerBlock;
if(usesSharedMemory){
shmem_reduce<<<blocks, threads>>>(d_intermediate, d_in);
}
else{
global_reduce<<<blocks, threads>>>(d_intermediate, d_in);
}
threads = maxThreadsPerBlock;
blocks = 1;
if(usesSharedMemory){
shmem_reduce<<<blocks, threads>>>(d_out, d_intermediate);
}
else{
global_reduce<<<blocks, threads>>>(d_out, d_intermediate);
}
}
int main(){
int dev = 0;
cudaSetDevice(dev);
const int ARRAY_SIZE = 1 << 20;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
// generate the input array on the host
float h_in[ARRAY_SIZE];
float sum = 0.0f;
for(int i = 0; i < ARRAY_SIZE; i++) {
// generate random float in [-1.0f, 1.0f]
h_in[i] = -1.0f + (float)random()/((float)RAND_MAX/2.0f);
sum += h_in[i];
}
printf("sum using serial reduce: %f\n", sum);
// declare GPU memory pointers
float * d_in, * d_intermediate, * d_out;
// allocate GPU memory
HANDLE_ERROR(cudaMalloc((void **) &d_in, ARRAY_BYTES));
HANDLE_ERROR(cudaMalloc((void **) &d_intermediate, ARRAY_BYTES)); // overallocated
HANDLE_ERROR(cudaMalloc((void **) &d_out, sizeof(float)));
// transfer the input array to the GPU
HANDLE_ERROR(cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice));
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
printf("Running global mamory reduce\n");
cudaEventRecord(start, 0);
const int itt = 100;
for (int i = 0; i < itt; i++){
HANDLE_ERROR(cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice));
reduce(d_out, d_intermediate, d_in, ARRAY_SIZE, false);
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
elapsedTime /= (float)itt; // 100 trials
// copy back the sum from GPU
float h_out;
HANDLE_ERROR(cudaMemcpy(&h_out, d_out, sizeof(float), cudaMemcpyDeviceToHost));
printf("sum using global memory kernel: %f\n", h_out);
printf("average time elapsed using global memory kernel: %f\n", elapsedTime);
printf("Running shared mamory reduce\n");
HANDLE_ERROR(cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice));
cudaEventRecord(start, 0);
for (int i = 0; i < itt; i++){
reduce(d_out, d_intermediate, d_in, ARRAY_SIZE, true);
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
elapsedTime /= (float)itt; // 100 trials
// copy back the sum from GPU
HANDLE_ERROR(cudaMemcpy(&h_out, d_out, sizeof(float), cudaMemcpyDeviceToHost));
printf("sum using shared memory kernel: %f\n", h_out);
printf("average time elapsed using shared memory kernel: %f\n", elapsedTime);
// free GPU memory allocation
cudaFree(d_in);
cudaFree(d_intermediate);
cudaFree(d_out);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
static void HandleError( hipError_t err, const char *file, int line ) {
if (err != hipSuccess) {
printf( "%s in %s at line %d\n", hipGetErrorString( err ), file, line );
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
// Each block takes care of 1024 elements
__global__
void global_reduce(float* gpu_out, float* gpu_in){
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int tidx = threadIdx.x;
int s = blockDim.x/2;
while(s > 0 ){
if(tidx < s){
gpu_in[tid] += gpu_in[tid + s];
}
s >>= 1;
__syncthreads();
}
// only thread 0 writes result for this block back to global mem
if(tidx == 0){
gpu_out[blockIdx.x] = gpu_in[tid];
}
}
__global__
void shmem_reduce(float* gpu_out, const float* gpu_in){
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int tidx = threadIdx.x;
const int size = 1024;
__shared__
float smem[size];
if(tidx < size){
smem[tidx] = gpu_in[tid];
}
__syncthreads();
int s = size/2;
while(s > 0 ){
if(tidx < s){
smem[tidx] += smem[tidx + s];
}
s >>= 1;
__syncthreads();
}
// only thread 0 writes result for this block back to global mem
if(tidx == 0){
gpu_out[blockIdx.x] = smem[tidx];
}
}
void reduce(float *d_out, float *d_intermediate, float * d_in,
int size, bool usesSharedMemory){
const int maxThreadsPerBlock = 1024;
int threads = maxThreadsPerBlock;
int blocks = size / maxThreadsPerBlock;
if(usesSharedMemory){
shmem_reduce<<<blocks, threads>>>(d_intermediate, d_in);
}
else{
global_reduce<<<blocks, threads>>>(d_intermediate, d_in);
}
threads = maxThreadsPerBlock;
blocks = 1;
if(usesSharedMemory){
shmem_reduce<<<blocks, threads>>>(d_out, d_intermediate);
}
else{
global_reduce<<<blocks, threads>>>(d_out, d_intermediate);
}
}
int main(){
int dev = 0;
hipSetDevice(dev);
const int ARRAY_SIZE = 1 << 20;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
// generate the input array on the host
float h_in[ARRAY_SIZE];
float sum = 0.0f;
for(int i = 0; i < ARRAY_SIZE; i++) {
// generate random float in [-1.0f, 1.0f]
h_in[i] = -1.0f + (float)random()/((float)RAND_MAX/2.0f);
sum += h_in[i];
}
printf("sum using serial reduce: %f\n", sum);
// declare GPU memory pointers
float * d_in, * d_intermediate, * d_out;
// allocate GPU memory
HANDLE_ERROR(hipMalloc((void **) &d_in, ARRAY_BYTES));
HANDLE_ERROR(hipMalloc((void **) &d_intermediate, ARRAY_BYTES)); // overallocated
HANDLE_ERROR(hipMalloc((void **) &d_out, sizeof(float)));
// transfer the input array to the GPU
HANDLE_ERROR(hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice));
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
printf("Running global mamory reduce\n");
hipEventRecord(start, 0);
const int itt = 100;
for (int i = 0; i < itt; i++){
HANDLE_ERROR(hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice));
reduce(d_out, d_intermediate, d_in, ARRAY_SIZE, false);
}
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
elapsedTime /= (float)itt; // 100 trials
// copy back the sum from GPU
float h_out;
HANDLE_ERROR(hipMemcpy(&h_out, d_out, sizeof(float), hipMemcpyDeviceToHost));
printf("sum using global memory kernel: %f\n", h_out);
printf("average time elapsed using global memory kernel: %f\n", elapsedTime);
printf("Running shared mamory reduce\n");
HANDLE_ERROR(hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice));
hipEventRecord(start, 0);
for (int i = 0; i < itt; i++){
reduce(d_out, d_intermediate, d_in, ARRAY_SIZE, true);
}
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
elapsedTime /= (float)itt; // 100 trials
// copy back the sum from GPU
HANDLE_ERROR(hipMemcpy(&h_out, d_out, sizeof(float), hipMemcpyDeviceToHost));
printf("sum using shared memory kernel: %f\n", h_out);
printf("average time elapsed using shared memory kernel: %f\n", elapsedTime);
// free GPU memory allocation
hipFree(d_in);
hipFree(d_intermediate);
hipFree(d_out);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
static void HandleError( hipError_t err, const char *file, int line ) {
if (err != hipSuccess) {
printf( "%s in %s at line %d\n", hipGetErrorString( err ), file, line );
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
// Each block takes care of 1024 elements
__global__
void global_reduce(float* gpu_out, float* gpu_in){
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int tidx = threadIdx.x;
int s = blockDim.x/2;
while(s > 0 ){
if(tidx < s){
gpu_in[tid] += gpu_in[tid + s];
}
s >>= 1;
__syncthreads();
}
// only thread 0 writes result for this block back to global mem
if(tidx == 0){
gpu_out[blockIdx.x] = gpu_in[tid];
}
}
__global__
void shmem_reduce(float* gpu_out, const float* gpu_in){
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int tidx = threadIdx.x;
const int size = 1024;
__shared__
float smem[size];
if(tidx < size){
smem[tidx] = gpu_in[tid];
}
__syncthreads();
int s = size/2;
while(s > 0 ){
if(tidx < s){
smem[tidx] += smem[tidx + s];
}
s >>= 1;
__syncthreads();
}
// only thread 0 writes result for this block back to global mem
if(tidx == 0){
gpu_out[blockIdx.x] = smem[tidx];
}
}
void reduce(float *d_out, float *d_intermediate, float * d_in,
int size, bool usesSharedMemory){
const int maxThreadsPerBlock = 1024;
int threads = maxThreadsPerBlock;
int blocks = size / maxThreadsPerBlock;
if(usesSharedMemory){
shmem_reduce<<<blocks, threads>>>(d_intermediate, d_in);
}
else{
global_reduce<<<blocks, threads>>>(d_intermediate, d_in);
}
threads = maxThreadsPerBlock;
blocks = 1;
if(usesSharedMemory){
shmem_reduce<<<blocks, threads>>>(d_out, d_intermediate);
}
else{
global_reduce<<<blocks, threads>>>(d_out, d_intermediate);
}
}
int main(){
int dev = 0;
hipSetDevice(dev);
const int ARRAY_SIZE = 1 << 20;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
// generate the input array on the host
float h_in[ARRAY_SIZE];
float sum = 0.0f;
for(int i = 0; i < ARRAY_SIZE; i++) {
// generate random float in [-1.0f, 1.0f]
h_in[i] = -1.0f + (float)random()/((float)RAND_MAX/2.0f);
sum += h_in[i];
}
printf("sum using serial reduce: %f\n", sum);
// declare GPU memory pointers
float * d_in, * d_intermediate, * d_out;
// allocate GPU memory
HANDLE_ERROR(hipMalloc((void **) &d_in, ARRAY_BYTES));
HANDLE_ERROR(hipMalloc((void **) &d_intermediate, ARRAY_BYTES)); // overallocated
HANDLE_ERROR(hipMalloc((void **) &d_out, sizeof(float)));
// transfer the input array to the GPU
HANDLE_ERROR(hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice));
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
printf("Running global mamory reduce\n");
hipEventRecord(start, 0);
const int itt = 100;
for (int i = 0; i < itt; i++){
HANDLE_ERROR(hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice));
reduce(d_out, d_intermediate, d_in, ARRAY_SIZE, false);
}
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
elapsedTime /= (float)itt; // 100 trials
// copy back the sum from GPU
float h_out;
HANDLE_ERROR(hipMemcpy(&h_out, d_out, sizeof(float), hipMemcpyDeviceToHost));
printf("sum using global memory kernel: %f\n", h_out);
printf("average time elapsed using global memory kernel: %f\n", elapsedTime);
printf("Running shared mamory reduce\n");
HANDLE_ERROR(hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice));
hipEventRecord(start, 0);
for (int i = 0; i < itt; i++){
reduce(d_out, d_intermediate, d_in, ARRAY_SIZE, true);
}
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
elapsedTime /= (float)itt; // 100 trials
// copy back the sum from GPU
HANDLE_ERROR(hipMemcpy(&h_out, d_out, sizeof(float), hipMemcpyDeviceToHost));
printf("sum using shared memory kernel: %f\n", h_out);
printf("average time elapsed using shared memory kernel: %f\n", elapsedTime);
// free GPU memory allocation
hipFree(d_in);
hipFree(d_intermediate);
hipFree(d_out);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13global_reducePfS_
.globl _Z13global_reducePfS_
.p2align 8
.type _Z13global_reducePfS_,@function
_Z13global_reducePfS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x8
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_cmp_lt_u32 s3, 2
v_ashrrev_i32_e32 v2, 31, v1
s_cbranch_scc1 .LBB0_5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s7
s_cmp_gt_u32 s3, 3
s_mov_b32 s3, s6
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_5
.LBB0_3:
s_lshr_b32 s6, s3, 1
s_mov_b32 s7, exec_lo
v_cmpx_gt_u32_e64 s6, v0
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v5, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
s_clause 0x1
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[3:4], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v5, v6
global_store_b32 v[3:4], v5, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s3, 0
s_mov_b32 s6, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v0, v[0:1], off
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13global_reducePfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13global_reducePfS_, .Lfunc_end0-_Z13global_reducePfS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12shmem_reducePfPKf
.globl _Z12shmem_reducePfPKf
.p2align 8
.type _Z12shmem_reducePfPKf,@function
_Z12shmem_reducePfPKf:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x8
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_movk_i32 s3, 0x200
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB1_2
.p2align 6
.LBB1_1:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 1
s_cmp_gt_u32 s3, 1
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_4
.LBB1_2:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB1_1
v_add_lshl_u32 v2, s3, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB1_1
.LBB1_4:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_6
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB1_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12shmem_reducePfPKf
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12shmem_reducePfPKf, .Lfunc_end1-_Z12shmem_reducePfPKf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13global_reducePfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13global_reducePfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12shmem_reducePfPKf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12shmem_reducePfPKf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
static void HandleError( hipError_t err, const char *file, int line ) {
if (err != hipSuccess) {
printf( "%s in %s at line %d\n", hipGetErrorString( err ), file, line );
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
// Each block takes care of 1024 elements
__global__
void global_reduce(float* gpu_out, float* gpu_in){
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int tidx = threadIdx.x;
int s = blockDim.x/2;
while(s > 0 ){
if(tidx < s){
gpu_in[tid] += gpu_in[tid + s];
}
s >>= 1;
__syncthreads();
}
// only thread 0 writes result for this block back to global mem
if(tidx == 0){
gpu_out[blockIdx.x] = gpu_in[tid];
}
}
__global__
void shmem_reduce(float* gpu_out, const float* gpu_in){
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int tidx = threadIdx.x;
const int size = 1024;
__shared__
float smem[size];
if(tidx < size){
smem[tidx] = gpu_in[tid];
}
__syncthreads();
int s = size/2;
while(s > 0 ){
if(tidx < s){
smem[tidx] += smem[tidx + s];
}
s >>= 1;
__syncthreads();
}
// only thread 0 writes result for this block back to global mem
if(tidx == 0){
gpu_out[blockIdx.x] = smem[tidx];
}
}
void reduce(float *d_out, float *d_intermediate, float * d_in,
int size, bool usesSharedMemory){
const int maxThreadsPerBlock = 1024;
int threads = maxThreadsPerBlock;
int blocks = size / maxThreadsPerBlock;
if(usesSharedMemory){
shmem_reduce<<<blocks, threads>>>(d_intermediate, d_in);
}
else{
global_reduce<<<blocks, threads>>>(d_intermediate, d_in);
}
threads = maxThreadsPerBlock;
blocks = 1;
if(usesSharedMemory){
shmem_reduce<<<blocks, threads>>>(d_out, d_intermediate);
}
else{
global_reduce<<<blocks, threads>>>(d_out, d_intermediate);
}
}
int main(){
int dev = 0;
hipSetDevice(dev);
const int ARRAY_SIZE = 1 << 20;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
// generate the input array on the host
float h_in[ARRAY_SIZE];
float sum = 0.0f;
for(int i = 0; i < ARRAY_SIZE; i++) {
// generate random float in [-1.0f, 1.0f]
h_in[i] = -1.0f + (float)random()/((float)RAND_MAX/2.0f);
sum += h_in[i];
}
printf("sum using serial reduce: %f\n", sum);
// declare GPU memory pointers
float * d_in, * d_intermediate, * d_out;
// allocate GPU memory
HANDLE_ERROR(hipMalloc((void **) &d_in, ARRAY_BYTES));
HANDLE_ERROR(hipMalloc((void **) &d_intermediate, ARRAY_BYTES)); // overallocated
HANDLE_ERROR(hipMalloc((void **) &d_out, sizeof(float)));
// transfer the input array to the GPU
HANDLE_ERROR(hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice));
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
printf("Running global mamory reduce\n");
hipEventRecord(start, 0);
const int itt = 100;
for (int i = 0; i < itt; i++){
HANDLE_ERROR(hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice));
reduce(d_out, d_intermediate, d_in, ARRAY_SIZE, false);
}
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
elapsedTime /= (float)itt; // 100 trials
// copy back the sum from GPU
float h_out;
HANDLE_ERROR(hipMemcpy(&h_out, d_out, sizeof(float), hipMemcpyDeviceToHost));
printf("sum using global memory kernel: %f\n", h_out);
printf("average time elapsed using global memory kernel: %f\n", elapsedTime);
printf("Running shared mamory reduce\n");
HANDLE_ERROR(hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice));
hipEventRecord(start, 0);
for (int i = 0; i < itt; i++){
reduce(d_out, d_intermediate, d_in, ARRAY_SIZE, true);
}
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
elapsedTime /= (float)itt; // 100 trials
// copy back the sum from GPU
HANDLE_ERROR(hipMemcpy(&h_out, d_out, sizeof(float), hipMemcpyDeviceToHost));
printf("sum using shared memory kernel: %f\n", h_out);
printf("average time elapsed using shared memory kernel: %f\n", elapsedTime);
// free GPU memory allocation
hipFree(d_in);
hipFree(d_intermediate);
hipFree(d_out);
return 0;
} | .text
.file "reduce.hip"
.globl _Z28__device_stub__global_reducePfS_ # -- Begin function _Z28__device_stub__global_reducePfS_
.p2align 4, 0x90
.type _Z28__device_stub__global_reducePfS_,@function
_Z28__device_stub__global_reducePfS_: # @_Z28__device_stub__global_reducePfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13global_reducePfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__global_reducePfS_, .Lfunc_end0-_Z28__device_stub__global_reducePfS_
.cfi_endproc
# -- End function
.globl _Z27__device_stub__shmem_reducePfPKf # -- Begin function _Z27__device_stub__shmem_reducePfPKf
.p2align 4, 0x90
.type _Z27__device_stub__shmem_reducePfPKf,@function
_Z27__device_stub__shmem_reducePfPKf: # @_Z27__device_stub__shmem_reducePfPKf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12shmem_reducePfPKf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z27__device_stub__shmem_reducePfPKf, .Lfunc_end1-_Z27__device_stub__shmem_reducePfPKf
.cfi_endproc
# -- End function
.globl _Z6reducePfS_S_ib # -- Begin function _Z6reducePfS_S_ib
.p2align 4, 0x90
.type _Z6reducePfS_S_ib,@function
_Z6reducePfS_S_ib: # @_Z6reducePfS_S_ib
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %ebp
# kill: def $ecx killed $ecx def $rcx
movq %rdx, %r12
movq %rsi, %rbx
movq %rdi, %r14
movabsq $4294968320, %r15 # imm = 0x100000400
leal 1023(%rcx), %eax
testl %ecx, %ecx
cmovnsl %ecx, %eax
sarl $10, %eax
leaq (%rax,%r15), %rdi
addq $-1024, %rdi # imm = 0xFC00
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %ebp, %ebp
je .LBB2_3
# %bb.1:
testl %eax, %eax
jne .LBB2_6
# %bb.2:
movq %rbx, 56(%rsp)
movq %r12, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12shmem_reducePfPKf, %edi
jmp .LBB2_5
.LBB2_3:
testl %eax, %eax
jne .LBB2_6
# %bb.4:
movq %rbx, 56(%rsp)
movq %r12, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13global_reducePfS_, %edi
.LBB2_5:
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
leaq -1023(%r15), %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testb %bpl, %bpl
je .LBB2_9
# %bb.7:
testl %eax, %eax
jne .LBB2_12
# %bb.8:
movq %r14, 56(%rsp)
movq %rbx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12shmem_reducePfPKf, %edi
jmp .LBB2_11
.LBB2_9:
testl %eax, %eax
jne .LBB2_12
# %bb.10:
movq %r14, 56(%rsp)
movq %rbx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13global_reducePfS_, %edi
.LBB2_11:
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_12:
addq $80, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z6reducePfS_S_ib, .Lfunc_end2-_Z6reducePfS_S_ib
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x30800000 # float 9.31322574E-10
.LCPI3_1:
.long 0xbf800000 # float -1
.LCPI3_2:
.long 0x42c80000 # float 100
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $4194376, %rsp # imm = 0x400048
.cfi_def_cfa_offset 4194400
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
xorl %ebx, %ebx
xorl %edi, %edi
callq hipSetDevice
xorps %xmm0, %xmm0
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, 16(%rsp) # 4-byte Spill
callq random
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
mulss .LCPI3_0(%rip), %xmm0
addss .LCPI3_1(%rip), %xmm0
movss %xmm0, 64(%rsp,%rbx,4)
movss 16(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
addss %xmm0, %xmm1
movss %xmm1, 16(%rsp) # 4-byte Spill
movss 16(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
incq %rbx
cmpq $1048576, %rbx # imm = 0x100000
jne .LBB3_1
# %bb.2:
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
leaq 32(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB3_3
# %bb.5: # %_ZL11HandleError10hipError_tPKci.exit
leaq 56(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB3_6
# %bb.7: # %_ZL11HandleError10hipError_tPKci.exit15
leaq 40(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB3_8
# %bb.9: # %_ZL11HandleError10hipError_tPKci.exit17
movq 32(%rsp), %rdi
leaq 64(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_10
# %bb.16: # %_ZL11HandleError10hipError_tPKci.exit19
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movl $.Lstr, %edi
callq puts@PLT
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $100, %ebp
leaq 64(%rsp), %rbx
.p2align 4, 0x90
.LBB3_17: # =>This Inner Loop Header: Depth=1
movq 32(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_18
# %bb.11: # %_ZL11HandleError10hipError_tPKci.exit25
# in Loop: Header=BB3_17 Depth=1
movq 40(%rsp), %rdi
movq 56(%rsp), %rsi
movq 32(%rsp), %rdx
movl $1048576, %ecx # imm = 0x100000
xorl %r8d, %r8d
callq _Z6reducePfS_S_ib
decl %ebp
jne .LBB3_17
# %bb.12:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 48(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI3_2(%rip), %xmm0
movss %xmm0, 12(%rsp)
movq 40(%rsp), %rsi
leaq 20(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_13
# %bb.14: # %_ZL11HandleError10hipError_tPKci.exit21
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
movq 32(%rsp), %rdi
leaq 64(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_15
# %bb.22: # %_ZL11HandleError10hipError_tPKci.exit23
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $100, %ebx
.p2align 4, 0x90
.LBB3_23: # =>This Inner Loop Header: Depth=1
movq 40(%rsp), %rdi
movq 56(%rsp), %rsi
movq 32(%rsp), %rdx
movl $1048576, %ecx # imm = 0x100000
movl $1, %r8d
callq _Z6reducePfS_S_ib
decl %ebx
jne .LBB3_23
# %bb.19:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 48(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI3_2(%rip), %xmm0
movss %xmm0, 12(%rsp)
movq 40(%rsp), %rsi
leaq 20(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_20
# %bb.21: # %_ZL11HandleError10hipError_tPKci.exit27
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $4194376, %rsp # imm = 0x400048
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_18:
.cfi_def_cfa_offset 4194400
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $129, %ecx
.LBB3_4:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB3_3:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $114, %ecx
jmp .LBB3_4
.LBB3_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $115, %ecx
jmp .LBB3_4
.LBB3_8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $116, %ecx
jmp .LBB3_4
.LBB3_10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $119, %ecx
jmp .LBB3_4
.LBB3_13:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $141, %ecx
jmp .LBB3_4
.LBB3_15:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $147, %ecx
jmp .LBB3_4
.LBB3_20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $160, %ecx
jmp .LBB3_4
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13global_reducePfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12shmem_reducePfPKf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13global_reducePfS_,@object # @_Z13global_reducePfS_
.section .rodata,"a",@progbits
.globl _Z13global_reducePfS_
.p2align 3, 0x0
_Z13global_reducePfS_:
.quad _Z28__device_stub__global_reducePfS_
.size _Z13global_reducePfS_, 8
.type _Z12shmem_reducePfPKf,@object # @_Z12shmem_reducePfPKf
.globl _Z12shmem_reducePfPKf
.p2align 3, 0x0
_Z12shmem_reducePfPKf:
.quad _Z27__device_stub__shmem_reducePfPKf
.size _Z12shmem_reducePfPKf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "sum using serial reduce: %f\n"
.size .L.str, 29
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/amiremadz/cuda-codes/master/reduce/reduce.hip"
.size .L.str.1, 103
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "sum using global memory kernel: %f\n"
.size .L.str.3, 36
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "average time elapsed using global memory kernel: %f\n"
.size .L.str.4, 53
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "sum using shared memory kernel: %f\n"
.size .L.str.6, 36
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "average time elapsed using shared memory kernel: %f\n"
.size .L.str.7, 53
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%s in %s at line %d\n"
.size .L.str.8, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13global_reducePfS_"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12shmem_reducePfPKf"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Running global mamory reduce"
.size .Lstr, 29
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Running shared mamory reduce"
.size .Lstr.1, 29
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__global_reducePfS_
.addrsig_sym _Z27__device_stub__shmem_reducePfPKf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13global_reducePfS_
.addrsig_sym _Z12shmem_reducePfPKf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12shmem_reducePfPKf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0xe0 ; /* 0x000000a000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0050*/ ISETP.GE.AND P1, PT, R3.reuse, 0x400, PT ; /* 0x000004000300780c */
/* 0x041fe40003f26270 */
/*0060*/ ISETP.GT.AND P0, PT, R3, 0x1ff, PT ; /* 0x000001ff0300780c */
/* 0x000fd60003f04270 */
/*0070*/ @P1 BRA 0xd0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x002fe200000001ff */
/*0090*/ IMAD R4, R0, c[0x0][0x0], R3 ; /* 0x0000000000047a24 */
/* 0x000fd200078e0203 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fcc00078e0205 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ STS [R3.X4], R4 ; /* 0x0000000403007388 */
/* 0x0041e40000004800 */
/*00d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*00f0*/ ISETP.GT.AND P1, PT, R3, 0xff, PT ; /* 0x000000ff0300780c */
/* 0x000fca0003f24270 */
/*0100*/ @!P0 LDS R2, [R3.X4] ; /* 0x0000000003028984 */
/* 0x000fe80000004800 */
/*0110*/ @!P0 LDS R5, [R3.X4+0x800] ; /* 0x0008000003058984 */
/* 0x000e640000004800 */
/*0120*/ @!P0 FADD R2, R2, R5 ; /* 0x0000000502028221 */
/* 0x002fca0000000000 */
/*0130*/ @!P0 STS [R3.X4], R2 ; /* 0x0000000203008388 */
/* 0x000fe80000004800 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0150*/ ISETP.GT.AND P0, PT, R3, 0x7f, PT ; /* 0x0000007f0300780c */
/* 0x000fca0003f04270 */
/*0160*/ @!P1 LDS R4, [R3.X4] ; /* 0x0000000003049984 */
/* 0x001fe80000004800 */
/*0170*/ @!P1 LDS R5, [R3.X4+0x400] ; /* 0x0004000003059984 */
/* 0x000e240000004800 */
/*0180*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*0190*/ @!P1 STS [R3.X4], R4 ; /* 0x0000000403009388 */
/* 0x000fe80000004800 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01b0*/ ISETP.GT.AND P1, PT, R3, 0x3f, PT ; /* 0x0000003f0300780c */
/* 0x000fca0003f24270 */
/*01c0*/ @!P0 LDS R5, [R3.X4] ; /* 0x0000000003058984 */
/* 0x000fe80000004800 */
/*01d0*/ @!P0 LDS R6, [R3.X4+0x200] ; /* 0x0002000003068984 */
/* 0x000e240000004800 */
/*01e0*/ @!P0 FADD R6, R5, R6 ; /* 0x0000000605068221 */
/* 0x001fca0000000000 */
/*01f0*/ @!P0 STS [R3.X4], R6 ; /* 0x0000000603008388 */
/* 0x000fe80000004800 */
/*0200*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0210*/ ISETP.GT.AND P0, PT, R3, 0x1f, PT ; /* 0x0000001f0300780c */
/* 0x000fca0003f04270 */
/*0220*/ @!P1 LDS R2, [R3.X4] ; /* 0x0000000003029984 */
/* 0x000fe80000004800 */
/*0230*/ @!P1 LDS R5, [R3.X4+0x100] ; /* 0x0001000003059984 */
/* 0x000e240000004800 */
/*0240*/ @!P1 FADD R2, R2, R5 ; /* 0x0000000502029221 */
/* 0x001fca0000000000 */
/*0250*/ @!P1 STS [R3.X4], R2 ; /* 0x0000000203009388 */
/* 0x000fe80000004800 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0270*/ ISETP.GT.AND P1, PT, R3, 0xf, PT ; /* 0x0000000f0300780c */
/* 0x000fca0003f24270 */
/*0280*/ @!P0 LDS R4, [R3.X4] ; /* 0x0000000003048984 */
/* 0x000fe80000004800 */
/*0290*/ @!P0 LDS R5, [R3.X4+0x80] ; /* 0x0000800003058984 */
/* 0x000e240000004800 */
/*02a0*/ @!P0 FADD R4, R4, R5 ; /* 0x0000000504048221 */
/* 0x001fca0000000000 */
/*02b0*/ @!P0 STS [R3.X4], R4 ; /* 0x0000000403008388 */
/* 0x000fe80000004800 */
/*02c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02d0*/ ISETP.GT.AND P0, PT, R3, 0x7, PT ; /* 0x000000070300780c */
/* 0x000fca0003f04270 */
/*02e0*/ @!P1 LDS R5, [R3.X4] ; /* 0x0000000003059984 */
/* 0x000fe80000004800 */
/*02f0*/ @!P1 LDS R6, [R3.X4+0x40] ; /* 0x0000400003069984 */
/* 0x000e240000004800 */
/*0300*/ @!P1 FADD R6, R5, R6 ; /* 0x0000000605069221 */
/* 0x001fca0000000000 */
/*0310*/ @!P1 STS [R3.X4], R6 ; /* 0x0000000603009388 */
/* 0x000fe80000004800 */
/*0320*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0330*/ ISETP.GT.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fca0003f24270 */
/*0340*/ @!P0 LDS R2, [R3.X4] ; /* 0x0000000003028984 */
/* 0x000fe80000004800 */
/*0350*/ @!P0 LDS R5, [R3.X4+0x20] ; /* 0x0000200003058984 */
/* 0x000e240000004800 */
/*0360*/ @!P0 FADD R2, R2, R5 ; /* 0x0000000502028221 */
/* 0x001fca0000000000 */
/*0370*/ @!P0 STS [R3.X4], R2 ; /* 0x0000000203008388 */
/* 0x000fe80000004800 */
/*0380*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0390*/ ISETP.GT.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fca0003f04270 */
/*03a0*/ @!P1 LDS R4, [R3.X4] ; /* 0x0000000003049984 */
/* 0x000fe80000004800 */
/*03b0*/ @!P1 LDS R5, [R3.X4+0x10] ; /* 0x0000100003059984 */
/* 0x000e240000004800 */
/*03c0*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*03d0*/ @!P1 STS [R3.X4], R4 ; /* 0x0000000403009388 */
/* 0x000fe80000004800 */
/*03e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03f0*/ ISETP.GT.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fca0003f24270 */
/*0400*/ @!P0 LDS R5, [R3.X4] ; /* 0x0000000003058984 */
/* 0x000fe80000004800 */
/*0410*/ @!P0 LDS R6, [R3.X4+0x8] ; /* 0x0000080003068984 */
/* 0x000e240000004800 */
/*0420*/ @!P0 FADD R6, R5, R6 ; /* 0x0000000605068221 */
/* 0x001fca0000000000 */
/*0430*/ @!P0 STS [R3.X4], R6 ; /* 0x0000000603008388 */
/* 0x000fe80000004800 */
/*0440*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0450*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fca0003f05270 */
/*0460*/ @!P1 LDS R2, [R3.X4] ; /* 0x0000000003029984 */
/* 0x000fe80000004800 */
/*0470*/ @!P1 LDS R5, [R3.X4+0x4] ; /* 0x0000040003059984 */
/* 0x000e240000004800 */
/*0480*/ @!P1 FADD R2, R2, R5 ; /* 0x0000000502029221 */
/* 0x001fca0000000000 */
/*0490*/ @!P1 STS [R3.X4], R2 ; /* 0x0000000203009388 */
/* 0x0001e80000004800 */
/*04a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*04c0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x001e220000000800 */
/*04d0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*04e0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0003 */
/*04f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ BRA 0x510; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13global_reducePfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0040*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0070*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*0080*/ IMAD R2, R6, c[0x0][0x0], R8 ; /* 0x0000000006027a24 */
/* 0x001fc800078e0208 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fd000078e0203 */
/*00a0*/ @!P0 BRA 0x190 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*00b0*/ MOV R7, UR4 ; /* 0x0000000400077c02 */
/* 0x000fc80008000f00 */
/*00c0*/ ISETP.GE.AND P0, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fe20003f06270 */
/*00d0*/ BSSY B0, 0x150 ; /* 0x0000007000007945 */
/* 0x000fd80003800000 */
/*00e0*/ @P0 BRA 0x140 ; /* 0x0000005000000947 */
/* 0x001fea0003800000 */
/*00f0*/ IMAD.WIDE R4, R7, 0x4, R2 ; /* 0x0000000407047825 */
/* 0x000fe200078e0202 */
/*0100*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000eaa000c1e1900 */
/*0110*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea4000c1e1900 */
/*0120*/ FADD R9, R0, R5 ; /* 0x0000000500097221 */
/* 0x004fca0000000000 */
/*0130*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e4000c101906 */
/*0140*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0150*/ SHF.R.U32.HI R7, RZ, 0x1, R7 ; /* 0x00000001ff077819 */
/* 0x000fe20000011607 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0170*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0180*/ @P0 BRA 0xc0 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*0190*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*01a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01b0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x001ea2000c1e1900 */
/*01c0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*01d0*/ IMAD.WIDE.U32 R4, R6, R5, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fca00078e0005 */
/*01e0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101906 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13global_reducePfS_
.globl _Z13global_reducePfS_
.p2align 8
.type _Z13global_reducePfS_,@function
_Z13global_reducePfS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x8
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_cmp_lt_u32 s3, 2
v_ashrrev_i32_e32 v2, 31, v1
s_cbranch_scc1 .LBB0_5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s7
s_cmp_gt_u32 s3, 3
s_mov_b32 s3, s6
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_5
.LBB0_3:
s_lshr_b32 s6, s3, 1
s_mov_b32 s7, exec_lo
v_cmpx_gt_u32_e64 s6, v0
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v5, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
s_clause 0x1
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[3:4], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v5, v6
global_store_b32 v[3:4], v5, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s3, 0
s_mov_b32 s6, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v0, v[0:1], off
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13global_reducePfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13global_reducePfS_, .Lfunc_end0-_Z13global_reducePfS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12shmem_reducePfPKf
.globl _Z12shmem_reducePfPKf
.p2align 8
.type _Z12shmem_reducePfPKf,@function
_Z12shmem_reducePfPKf:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x8
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_movk_i32 s3, 0x200
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB1_2
.p2align 6
.LBB1_1:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 1
s_cmp_gt_u32 s3, 1
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_4
.LBB1_2:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB1_1
v_add_lshl_u32 v2, s3, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB1_1
.LBB1_4:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_6
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB1_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12shmem_reducePfPKf
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12shmem_reducePfPKf, .Lfunc_end1-_Z12shmem_reducePfPKf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13global_reducePfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13global_reducePfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12shmem_reducePfPKf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12shmem_reducePfPKf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00107e13_00000000-6_reduce.cudafe1.cpp"
.text
#APP
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s in %s at line %d\n"
#NO_APP
.text
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB2057:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _ZL11HandleError9cudaErrorPKci, .-_ZL11HandleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z13global_reducePfS_PfS_
.type _Z35__device_stub__Z13global_reducePfS_PfS_, @function
_Z35__device_stub__Z13global_reducePfS_PfS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13global_reducePfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z13global_reducePfS_PfS_, .-_Z35__device_stub__Z13global_reducePfS_PfS_
.globl _Z13global_reducePfS_
.type _Z13global_reducePfS_, @function
_Z13global_reducePfS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13global_reducePfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13global_reducePfS_, .-_Z13global_reducePfS_
.globl _Z35__device_stub__Z12shmem_reducePfPKfPfPKf
.type _Z35__device_stub__Z12shmem_reducePfPKfPfPKf, @function
_Z35__device_stub__Z12shmem_reducePfPKfPfPKf:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12shmem_reducePfPKf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z35__device_stub__Z12shmem_reducePfPKfPfPKf, .-_Z35__device_stub__Z12shmem_reducePfPKfPfPKf
.globl _Z12shmem_reducePfPKf
.type _Z12shmem_reducePfPKf, @function
_Z12shmem_reducePfPKf:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12shmem_reducePfPKfPfPKf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z12shmem_reducePfPKf, .-_Z12shmem_reducePfPKf
.globl _Z6reducePfS_S_ib
.type _Z6reducePfS_S_ib, @function
_Z6reducePfS_S_ib:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %rbx
movq %rdx, %r12
leal 1023(%rcx), %eax
testl %ecx, %ecx
cmovns %ecx, %eax
sarl $10, %eax
testb %r8b, %r8b
je .L26
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L27:
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L25:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
movq %r12, %rsi
movq %rbx, %rdi
call _Z35__device_stub__Z12shmem_reducePfPKfPfPKf
jmp .L27
.L26:
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L30:
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L25
movq %rbx, %rsi
movq %rbp, %rdi
call _Z35__device_stub__Z13global_reducePfS_PfS_
jmp .L25
.L39:
movq %r12, %rsi
movq %rbx, %rdi
call _Z35__device_stub__Z13global_reducePfS_PfS_
jmp .L30
.L38:
movq %rbx, %rsi
movq %rbp, %rdi
call _Z35__device_stub__Z12shmem_reducePfPKfPfPKf
jmp .L25
.cfi_endproc
.LFE2058:
.size _Z6reducePfS_S_ib, .-_Z6reducePfS_S_ib
.section .rodata.str1.1
.LC4:
.string "sum using serial reduce: %f\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "/home/ubuntu/Datasets/stackv2/train-structured/amiremadz/cuda-codes/master/reduce/reduce.cu"
.section .rodata.str1.1
.LC6:
.string "Running global mamory reduce\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "sum using global memory kernel: %f\n"
.align 8
.LC9:
.string "average time elapsed using global memory kernel: %f\n"
.section .rodata.str1.1
.LC10:
.string "Running shared mamory reduce\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "sum using shared memory kernel: %f\n"
.align 8
.LC12:
.string "average time elapsed using shared memory kernel: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
leaq -4194304(%rsp), %r11
.cfi_def_cfa 11, 4194328
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $88, %rsp
.cfi_def_cfa_offset 4194416
movq %fs:40, %rax
movq %rax, 4194376(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
leaq 64(%rsp), %rbx
leaq 4194368(%rsp), %rbp
movl $0x00000000, 12(%rsp)
.L41:
call random@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
mulss .LC2(%rip), %xmm0
subss .LC3(%rip), %xmm0
movss %xmm0, (%rbx)
addss 12(%rsp), %xmm0
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L41
cvtss2sd %xmm0, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $114, %edx
leaq .LC5(%rip), %rbx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 32(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $115, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $116, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $4194304, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $119, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $100, %ebx
leaq .LC5(%rip), %rbp
.L42:
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $4194304, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $129, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %r8d
movl $1048576, %ecx
movq 24(%rsp), %rdx
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z6reducePfS_S_ib
subl $1, %ebx
jne .L42
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 16(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 16(%rsp), %xmm0
divss .LC7(%rip), %xmm0
movss %xmm0, 16(%rsp)
leaq 20(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 40(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
movl $141, %edx
leaq .LC5(%rip), %rbx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 16(%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $4194304, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $147, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $100, %ebx
.L43:
movl $1, %r8d
movl $1048576, %ecx
movq 24(%rsp), %rdx
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z6reducePfS_S_ib
subl $1, %ebx
jne .L43
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 16(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 16(%rsp), %xmm0
divss .LC7(%rip), %xmm0
movss %xmm0, 16(%rsp)
leaq 20(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 40(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
movl $160, %edx
leaq .LC5(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 16(%rsp), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 4194376(%rsp), %rax
subq %fs:40, %rax
jne .L49
movl $0, %eax
addq $4194392, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z12shmem_reducePfPKf"
.LC14:
.string "_Z13global_reducePfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z12shmem_reducePfPKf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z13global_reducePfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 813694976
.align 4
.LC3:
.long 1065353216
.align 4
.LC7:
.long 1120403456
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reduce.hip"
.globl _Z28__device_stub__global_reducePfS_ # -- Begin function _Z28__device_stub__global_reducePfS_
.p2align 4, 0x90
.type _Z28__device_stub__global_reducePfS_,@function
_Z28__device_stub__global_reducePfS_: # @_Z28__device_stub__global_reducePfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13global_reducePfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__global_reducePfS_, .Lfunc_end0-_Z28__device_stub__global_reducePfS_
.cfi_endproc
# -- End function
.globl _Z27__device_stub__shmem_reducePfPKf # -- Begin function _Z27__device_stub__shmem_reducePfPKf
.p2align 4, 0x90
.type _Z27__device_stub__shmem_reducePfPKf,@function
_Z27__device_stub__shmem_reducePfPKf: # @_Z27__device_stub__shmem_reducePfPKf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12shmem_reducePfPKf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z27__device_stub__shmem_reducePfPKf, .Lfunc_end1-_Z27__device_stub__shmem_reducePfPKf
.cfi_endproc
# -- End function
.globl _Z6reducePfS_S_ib # -- Begin function _Z6reducePfS_S_ib
.p2align 4, 0x90
.type _Z6reducePfS_S_ib,@function
_Z6reducePfS_S_ib: # @_Z6reducePfS_S_ib
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %ebp
# kill: def $ecx killed $ecx def $rcx
movq %rdx, %r12
movq %rsi, %rbx
movq %rdi, %r14
movabsq $4294968320, %r15 # imm = 0x100000400
leal 1023(%rcx), %eax
testl %ecx, %ecx
cmovnsl %ecx, %eax
sarl $10, %eax
leaq (%rax,%r15), %rdi
addq $-1024, %rdi # imm = 0xFC00
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %ebp, %ebp
je .LBB2_3
# %bb.1:
testl %eax, %eax
jne .LBB2_6
# %bb.2:
movq %rbx, 56(%rsp)
movq %r12, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12shmem_reducePfPKf, %edi
jmp .LBB2_5
.LBB2_3:
testl %eax, %eax
jne .LBB2_6
# %bb.4:
movq %rbx, 56(%rsp)
movq %r12, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13global_reducePfS_, %edi
.LBB2_5:
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
leaq -1023(%r15), %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testb %bpl, %bpl
je .LBB2_9
# %bb.7:
testl %eax, %eax
jne .LBB2_12
# %bb.8:
movq %r14, 56(%rsp)
movq %rbx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12shmem_reducePfPKf, %edi
jmp .LBB2_11
.LBB2_9:
testl %eax, %eax
jne .LBB2_12
# %bb.10:
movq %r14, 56(%rsp)
movq %rbx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13global_reducePfS_, %edi
.LBB2_11:
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_12:
addq $80, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z6reducePfS_S_ib, .Lfunc_end2-_Z6reducePfS_S_ib
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x30800000 # float 9.31322574E-10
.LCPI3_1:
.long 0xbf800000 # float -1
.LCPI3_2:
.long 0x42c80000 # float 100
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $4194376, %rsp # imm = 0x400048
.cfi_def_cfa_offset 4194400
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
xorl %ebx, %ebx
xorl %edi, %edi
callq hipSetDevice
xorps %xmm0, %xmm0
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, 16(%rsp) # 4-byte Spill
callq random
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
mulss .LCPI3_0(%rip), %xmm0
addss .LCPI3_1(%rip), %xmm0
movss %xmm0, 64(%rsp,%rbx,4)
movss 16(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
addss %xmm0, %xmm1
movss %xmm1, 16(%rsp) # 4-byte Spill
movss 16(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
incq %rbx
cmpq $1048576, %rbx # imm = 0x100000
jne .LBB3_1
# %bb.2:
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
leaq 32(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB3_3
# %bb.5: # %_ZL11HandleError10hipError_tPKci.exit
leaq 56(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB3_6
# %bb.7: # %_ZL11HandleError10hipError_tPKci.exit15
leaq 40(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB3_8
# %bb.9: # %_ZL11HandleError10hipError_tPKci.exit17
movq 32(%rsp), %rdi
leaq 64(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_10
# %bb.16: # %_ZL11HandleError10hipError_tPKci.exit19
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movl $.Lstr, %edi
callq puts@PLT
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $100, %ebp
leaq 64(%rsp), %rbx
.p2align 4, 0x90
.LBB3_17: # =>This Inner Loop Header: Depth=1
movq 32(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_18
# %bb.11: # %_ZL11HandleError10hipError_tPKci.exit25
# in Loop: Header=BB3_17 Depth=1
movq 40(%rsp), %rdi
movq 56(%rsp), %rsi
movq 32(%rsp), %rdx
movl $1048576, %ecx # imm = 0x100000
xorl %r8d, %r8d
callq _Z6reducePfS_S_ib
decl %ebp
jne .LBB3_17
# %bb.12:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 48(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI3_2(%rip), %xmm0
movss %xmm0, 12(%rsp)
movq 40(%rsp), %rsi
leaq 20(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_13
# %bb.14: # %_ZL11HandleError10hipError_tPKci.exit21
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
movq 32(%rsp), %rdi
leaq 64(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_15
# %bb.22: # %_ZL11HandleError10hipError_tPKci.exit23
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $100, %ebx
.p2align 4, 0x90
.LBB3_23: # =>This Inner Loop Header: Depth=1
movq 40(%rsp), %rdi
movq 56(%rsp), %rsi
movq 32(%rsp), %rdx
movl $1048576, %ecx # imm = 0x100000
movl $1, %r8d
callq _Z6reducePfS_S_ib
decl %ebx
jne .LBB3_23
# %bb.19:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 48(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI3_2(%rip), %xmm0
movss %xmm0, 12(%rsp)
movq 40(%rsp), %rsi
leaq 20(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_20
# %bb.21: # %_ZL11HandleError10hipError_tPKci.exit27
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $4194376, %rsp # imm = 0x400048
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_18:
.cfi_def_cfa_offset 4194400
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $129, %ecx
.LBB3_4:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB3_3:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $114, %ecx
jmp .LBB3_4
.LBB3_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $115, %ecx
jmp .LBB3_4
.LBB3_8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $116, %ecx
jmp .LBB3_4
.LBB3_10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $119, %ecx
jmp .LBB3_4
.LBB3_13:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $141, %ecx
jmp .LBB3_4
.LBB3_15:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $147, %ecx
jmp .LBB3_4
.LBB3_20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $160, %ecx
jmp .LBB3_4
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13global_reducePfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12shmem_reducePfPKf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13global_reducePfS_,@object # @_Z13global_reducePfS_
.section .rodata,"a",@progbits
.globl _Z13global_reducePfS_
.p2align 3, 0x0
_Z13global_reducePfS_:
.quad _Z28__device_stub__global_reducePfS_
.size _Z13global_reducePfS_, 8
.type _Z12shmem_reducePfPKf,@object # @_Z12shmem_reducePfPKf
.globl _Z12shmem_reducePfPKf
.p2align 3, 0x0
_Z12shmem_reducePfPKf:
.quad _Z27__device_stub__shmem_reducePfPKf
.size _Z12shmem_reducePfPKf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "sum using serial reduce: %f\n"
.size .L.str, 29
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/amiremadz/cuda-codes/master/reduce/reduce.hip"
.size .L.str.1, 103
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "sum using global memory kernel: %f\n"
.size .L.str.3, 36
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "average time elapsed using global memory kernel: %f\n"
.size .L.str.4, 53
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "sum using shared memory kernel: %f\n"
.size .L.str.6, 36
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "average time elapsed using shared memory kernel: %f\n"
.size .L.str.7, 53
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%s in %s at line %d\n"
.size .L.str.8, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13global_reducePfS_"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12shmem_reducePfPKf"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Running global mamory reduce"
.size .Lstr, 29
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Running shared mamory reduce"
.size .Lstr.1, 29
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__global_reducePfS_
.addrsig_sym _Z27__device_stub__shmem_reducePfPKf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13global_reducePfS_
.addrsig_sym _Z12shmem_reducePfPKf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <functional>
#include <curand_kernel.h>
#define threadsPerBlock 256
typedef double(*test_func_t)(double*, int, double);
__device__ double rastrigin_cuda(double *input, int size, double val) {
if (size == 0 && input == NULL) {
return val * val - 10.0 * cos(2.0 * M_PI * val);
}
double first_term = 10 * static_cast<double>(size);
double second_term = 0.0;
for (int i = 0; i < size; ++i) {
second_term += (input[i] * input[i]);
second_term -= 10.0 * cos(2.0 * M_PI * input[i]);
}
return first_term + second_term;
}
__device__ double ackley_cuda(double *input, int size, double val) {
if (size == 0 && input == NULL) {
return -20.0 * exp(-0.2 * sqrt(0.5 * val * val))
-exp(0.5 * cos(2.0 * M_PI * val));
}
double square_term = 0.0;
double cosine_term = 0.0;
for (int i = 0; i < size; ++i) {
square_term += input[i] * input[i];
cosine_term += cos(2.0 * M_PI * input[i]);
}
double first_term = -20.0 * exp(-0.2 * sqrt(0.5 * square_term));
double second_term = -exp(cosine_term / double(size)) + exp(1.0) + 20.0;
return first_term + second_term;
}
__global__ void sa_kernel(double *dev_solution, int size, double lo, double hi,
double sigma, int choice) {
curandState state;
test_func_t func;
switch (choice) {
case(1):
func = rastrigin_cuda;
break;
case(2):
func = ackley_cuda;
break;
}
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx > size) return;
curand_init(idx, 0, 0, &state);
double iter = 0.0;
double temperature = 1.0;
double sol_idx = dev_solution[idx];
while(temperature >= 1e-6) {
double original_sol = sol_idx;
double diff = -func(NULL, 0, sol_idx);
sol_idx += curand_normal_double(&state) * sigma;
diff += func(NULL, 0, sol_idx);
if (diff > 0) {
double alpha = curand_uniform_double(&state);
double prob = exp(-diff / temperature);
if (alpha > prob) {
sol_idx = original_sol;
}
}
temperature = 1.0 / (1.0+2.5*iter);
iter += 1.0;
}
dev_solution[idx] = sol_idx;
}
void simulate_annealing_cuda(double *solution, int size, double lo,
double hi, double sigma, float *msec, int choice) {
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
int numBlock = size / threadsPerBlock + 1;
double *dev_solution;
cudaMalloc(&dev_solution, sizeof(double)*size);
cudaMemcpy(dev_solution, solution, sizeof(double)*size, cudaMemcpyHostToDevice);
cudaEventRecord(start);
sa_kernel<<<numBlock, threadsPerBlock>>>(dev_solution, size, lo, hi, sigma, choice);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(msec, start, stop);
cudaMemcpy(solution, dev_solution, sizeof(double)*size, cudaMemcpyDeviceToHost);
cudaFree(&dev_solution);
}
void printCudaInfo()
{
// for fun, just print out some stats on the machine
int deviceCount = 0;
cudaError_t err = cudaGetDeviceCount(&deviceCount);
printf("---------------------------------------------------------\n");
printf("Found %d CUDA devices\n", deviceCount);
for (int i=0; i<deviceCount; i++)
{
cudaDeviceProp deviceProps;
cudaGetDeviceProperties(&deviceProps, i);
printf("Device %d: %s\n", i, deviceProps.name);
printf(" SMs: %d\n", deviceProps.multiProcessorCount);
printf(" Global mem: %.0f MB\n",
static_cast<double>(deviceProps.totalGlobalMem) / (1024 * 1024));
printf(" CUDA Cap: %d.%d\n", deviceProps.major, deviceProps.minor);
}
printf("---------------------------------------------------------\n");
} | .file "tmpxft_001568bb_00000000-6_cuda_opt_SA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4038:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4038:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14rastrigin_cudaPdid
.type _Z14rastrigin_cudaPdid, @function
_Z14rastrigin_cudaPdid:
.LFB4032:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4032:
.size _Z14rastrigin_cudaPdid, .-_Z14rastrigin_cudaPdid
.globl _Z11ackley_cudaPdid
.type _Z11ackley_cudaPdid, @function
_Z11ackley_cudaPdid:
.LFB4033:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4033:
.size _Z11ackley_cudaPdid, .-_Z11ackley_cudaPdid
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "---------------------------------------------------------\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Found %d CUDA devices\n"
.LC2:
.string "Device %d: %s\n"
.LC3:
.string " SMs: %d\n"
.LC5:
.string " Global mem: %.0f MB\n"
.LC6:
.string " CUDA Cap: %d.%d\n"
.text
.globl _Z13printCudaInfov
.type _Z13printCudaInfov, @function
_Z13printCudaInfov:
.LFB4035:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $1056, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L8
movl $0, %ebx
leaq .LC2(%rip), %r13
leaq .LC3(%rip), %r12
leaq .LC5(%rip), %rbp
jmp .L11
.L9:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
.L10:
mulsd .LC4(%rip), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L8
.L11:
leaq 16(%rsp), %r14
movl %ebx, %esi
movq %r14, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %r14, %rcx
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rax
testq %rax, %rax
js .L9
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
jmp .L10
.L8:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4035:
.size _Z13printCudaInfov, .-_Z13printCudaInfov
.globl _Z33__device_stub__Z9sa_kernelPdidddiPdidddi
.type _Z33__device_stub__Z9sa_kernelPdidddiPdidddi, @function
_Z33__device_stub__Z9sa_kernelPdidddiPdidddi:
.LFB4060:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movsd %xmm0, 24(%rsp)
movsd %xmm1, 16(%rsp)
movsd %xmm2, 8(%rsp)
movl %edx, 32(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9sa_kernelPdidddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4060:
.size _Z33__device_stub__Z9sa_kernelPdidddiPdidddi, .-_Z33__device_stub__Z9sa_kernelPdidddiPdidddi
.globl _Z9sa_kernelPdidddi
.type _Z9sa_kernelPdidddi, @function
_Z9sa_kernelPdidddi:
.LFB4061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9sa_kernelPdidddiPdidddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4061:
.size _Z9sa_kernelPdidddi, .-_Z9sa_kernelPdidddi
.globl _Z23simulate_annealing_cudaPdidddPfi
.type _Z23simulate_annealing_cudaPdidddPfi, @function
_Z23simulate_annealing_cudaPdidddPfi:
.LFB4034:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $96, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %r12
movl %esi, %ebx
movsd %xmm0, 8(%rsp)
movsd %xmm1, 16(%rsp)
movsd %xmm2, 24(%rsp)
movq %rdx, %r13
movl %ecx, %r14d
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movslq %ebx, %rbp
salq $3, %rbp
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 76(%rsp)
movl $1, 80(%rsp)
leal 255(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $8, %eax
addl $1, %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L25:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaEventElapsedTime@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movl %r14d, %edx
movsd 24(%rsp), %xmm2
movsd 16(%rsp), %xmm1
movsd 8(%rsp), %xmm0
movl %ebx, %esi
movq 56(%rsp), %rdi
call _Z33__device_stub__Z9sa_kernelPdidddiPdidddi
jmp .L25
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4034:
.size _Z23simulate_annealing_cudaPdidddPfi, .-_Z23simulate_annealing_cudaPdidddPfi
.section .rodata.str1.1
.LC7:
.string "_Z9sa_kernelPdidddi"
.LC8:
.string "precalc_xorwow_matrix"
.LC9:
.string "precalc_xorwow_offset_matrix"
.LC10:
.string "mrg32k3aM1"
.LC11:
.string "mrg32k3aM2"
.LC12:
.string "mrg32k3aM1SubSeq"
.LC13:
.string "mrg32k3aM2SubSeq"
.LC14:
.string "mrg32k3aM1Seq"
.LC15:
.string "mrg32k3aM2Seq"
.LC16:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4063:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9sa_kernelPdidddi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4063:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1051721728
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <functional>
#include <curand_kernel.h>
#define threadsPerBlock 256
typedef double(*test_func_t)(double*, int, double);
__device__ double rastrigin_cuda(double *input, int size, double val) {
if (size == 0 && input == NULL) {
return val * val - 10.0 * cos(2.0 * M_PI * val);
}
double first_term = 10 * static_cast<double>(size);
double second_term = 0.0;
for (int i = 0; i < size; ++i) {
second_term += (input[i] * input[i]);
second_term -= 10.0 * cos(2.0 * M_PI * input[i]);
}
return first_term + second_term;
}
__device__ double ackley_cuda(double *input, int size, double val) {
if (size == 0 && input == NULL) {
return -20.0 * exp(-0.2 * sqrt(0.5 * val * val))
-exp(0.5 * cos(2.0 * M_PI * val));
}
double square_term = 0.0;
double cosine_term = 0.0;
for (int i = 0; i < size; ++i) {
square_term += input[i] * input[i];
cosine_term += cos(2.0 * M_PI * input[i]);
}
double first_term = -20.0 * exp(-0.2 * sqrt(0.5 * square_term));
double second_term = -exp(cosine_term / double(size)) + exp(1.0) + 20.0;
return first_term + second_term;
}
__global__ void sa_kernel(double *dev_solution, int size, double lo, double hi,
double sigma, int choice) {
curandState state;
test_func_t func;
switch (choice) {
case(1):
func = rastrigin_cuda;
break;
case(2):
func = ackley_cuda;
break;
}
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx > size) return;
curand_init(idx, 0, 0, &state);
double iter = 0.0;
double temperature = 1.0;
double sol_idx = dev_solution[idx];
while(temperature >= 1e-6) {
double original_sol = sol_idx;
double diff = -func(NULL, 0, sol_idx);
sol_idx += curand_normal_double(&state) * sigma;
diff += func(NULL, 0, sol_idx);
if (diff > 0) {
double alpha = curand_uniform_double(&state);
double prob = exp(-diff / temperature);
if (alpha > prob) {
sol_idx = original_sol;
}
}
temperature = 1.0 / (1.0+2.5*iter);
iter += 1.0;
}
dev_solution[idx] = sol_idx;
}
void simulate_annealing_cuda(double *solution, int size, double lo,
double hi, double sigma, float *msec, int choice) {
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
int numBlock = size / threadsPerBlock + 1;
double *dev_solution;
cudaMalloc(&dev_solution, sizeof(double)*size);
cudaMemcpy(dev_solution, solution, sizeof(double)*size, cudaMemcpyHostToDevice);
cudaEventRecord(start);
sa_kernel<<<numBlock, threadsPerBlock>>>(dev_solution, size, lo, hi, sigma, choice);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(msec, start, stop);
cudaMemcpy(solution, dev_solution, sizeof(double)*size, cudaMemcpyDeviceToHost);
cudaFree(&dev_solution);
}
void printCudaInfo()
{
// for fun, just print out some stats on the machine
int deviceCount = 0;
cudaError_t err = cudaGetDeviceCount(&deviceCount);
printf("---------------------------------------------------------\n");
printf("Found %d CUDA devices\n", deviceCount);
for (int i=0; i<deviceCount; i++)
{
cudaDeviceProp deviceProps;
cudaGetDeviceProperties(&deviceProps, i);
printf("Device %d: %s\n", i, deviceProps.name);
printf(" SMs: %d\n", deviceProps.multiProcessorCount);
printf(" Global mem: %.0f MB\n",
static_cast<double>(deviceProps.totalGlobalMem) / (1024 * 1024));
printf(" CUDA Cap: %d.%d\n", deviceProps.major, deviceProps.minor);
}
printf("---------------------------------------------------------\n");
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <functional>
#include <hiprand/hiprand_kernel.h>
#define threadsPerBlock 256
typedef double(*test_func_t)(double*, int, double);
__device__ double rastrigin_cuda(double *input, int size, double val) {
if (size == 0 && input == NULL) {
return val * val - 10.0 * cos(2.0 * M_PI * val);
}
double first_term = 10 * static_cast<double>(size);
double second_term = 0.0;
for (int i = 0; i < size; ++i) {
second_term += (input[i] * input[i]);
second_term -= 10.0 * cos(2.0 * M_PI * input[i]);
}
return first_term + second_term;
}
__device__ double ackley_cuda(double *input, int size, double val) {
if (size == 0 && input == NULL) {
return -20.0 * exp(-0.2 * sqrt(0.5 * val * val))
-exp(0.5 * cos(2.0 * M_PI * val));
}
double square_term = 0.0;
double cosine_term = 0.0;
for (int i = 0; i < size; ++i) {
square_term += input[i] * input[i];
cosine_term += cos(2.0 * M_PI * input[i]);
}
double first_term = -20.0 * exp(-0.2 * sqrt(0.5 * square_term));
double second_term = -exp(cosine_term / double(size)) + exp(1.0) + 20.0;
return first_term + second_term;
}
__global__ void sa_kernel(double *dev_solution, int size, double lo, double hi,
double sigma, int choice) {
hiprandState state;
test_func_t func;
switch (choice) {
case(1):
func = rastrigin_cuda;
break;
case(2):
func = ackley_cuda;
break;
}
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx > size) return;
hiprand_init(idx, 0, 0, &state);
double iter = 0.0;
double temperature = 1.0;
double sol_idx = dev_solution[idx];
while(temperature >= 1e-6) {
double original_sol = sol_idx;
double diff = -func(NULL, 0, sol_idx);
sol_idx += hiprand_normal_double(&state) * sigma;
diff += func(NULL, 0, sol_idx);
if (diff > 0) {
double alpha = hiprand_uniform_double(&state);
double prob = exp(-diff / temperature);
if (alpha > prob) {
sol_idx = original_sol;
}
}
temperature = 1.0 / (1.0+2.5*iter);
iter += 1.0;
}
dev_solution[idx] = sol_idx;
}
void simulate_annealing_cuda(double *solution, int size, double lo,
double hi, double sigma, float *msec, int choice) {
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
int numBlock = size / threadsPerBlock + 1;
double *dev_solution;
hipMalloc(&dev_solution, sizeof(double)*size);
hipMemcpy(dev_solution, solution, sizeof(double)*size, hipMemcpyHostToDevice);
hipEventRecord(start);
sa_kernel<<<numBlock, threadsPerBlock>>>(dev_solution, size, lo, hi, sigma, choice);
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(msec, start, stop);
hipMemcpy(solution, dev_solution, sizeof(double)*size, hipMemcpyDeviceToHost);
hipFree(&dev_solution);
}
void printCudaInfo()
{
// for fun, just print out some stats on the machine
int deviceCount = 0;
hipError_t err = hipGetDeviceCount(&deviceCount);
printf("---------------------------------------------------------\n");
printf("Found %d CUDA devices\n", deviceCount);
for (int i=0; i<deviceCount; i++)
{
hipDeviceProp_t deviceProps;
hipGetDeviceProperties(&deviceProps, i);
printf("Device %d: %s\n", i, deviceProps.name);
printf(" SMs: %d\n", deviceProps.multiProcessorCount);
printf(" Global mem: %.0f MB\n",
static_cast<double>(deviceProps.totalGlobalMem) / (1024 * 1024));
printf(" CUDA Cap: %d.%d\n", deviceProps.major, deviceProps.minor);
}
printf("---------------------------------------------------------\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <functional>
#include <hiprand/hiprand_kernel.h>
#define threadsPerBlock 256
typedef double(*test_func_t)(double*, int, double);
__device__ double rastrigin_cuda(double *input, int size, double val) {
if (size == 0 && input == NULL) {
return val * val - 10.0 * cos(2.0 * M_PI * val);
}
double first_term = 10 * static_cast<double>(size);
double second_term = 0.0;
for (int i = 0; i < size; ++i) {
second_term += (input[i] * input[i]);
second_term -= 10.0 * cos(2.0 * M_PI * input[i]);
}
return first_term + second_term;
}
__device__ double ackley_cuda(double *input, int size, double val) {
if (size == 0 && input == NULL) {
return -20.0 * exp(-0.2 * sqrt(0.5 * val * val))
-exp(0.5 * cos(2.0 * M_PI * val));
}
double square_term = 0.0;
double cosine_term = 0.0;
for (int i = 0; i < size; ++i) {
square_term += input[i] * input[i];
cosine_term += cos(2.0 * M_PI * input[i]);
}
double first_term = -20.0 * exp(-0.2 * sqrt(0.5 * square_term));
double second_term = -exp(cosine_term / double(size)) + exp(1.0) + 20.0;
return first_term + second_term;
}
__global__ void sa_kernel(double *dev_solution, int size, double lo, double hi,
double sigma, int choice) {
hiprandState state;
test_func_t func;
switch (choice) {
case(1):
func = rastrigin_cuda;
break;
case(2):
func = ackley_cuda;
break;
}
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx > size) return;
hiprand_init(idx, 0, 0, &state);
double iter = 0.0;
double temperature = 1.0;
double sol_idx = dev_solution[idx];
while(temperature >= 1e-6) {
double original_sol = sol_idx;
double diff = -func(NULL, 0, sol_idx);
sol_idx += hiprand_normal_double(&state) * sigma;
diff += func(NULL, 0, sol_idx);
if (diff > 0) {
double alpha = hiprand_uniform_double(&state);
double prob = exp(-diff / temperature);
if (alpha > prob) {
sol_idx = original_sol;
}
}
temperature = 1.0 / (1.0+2.5*iter);
iter += 1.0;
}
dev_solution[idx] = sol_idx;
}
void simulate_annealing_cuda(double *solution, int size, double lo,
double hi, double sigma, float *msec, int choice) {
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
int numBlock = size / threadsPerBlock + 1;
double *dev_solution;
hipMalloc(&dev_solution, sizeof(double)*size);
hipMemcpy(dev_solution, solution, sizeof(double)*size, hipMemcpyHostToDevice);
hipEventRecord(start);
sa_kernel<<<numBlock, threadsPerBlock>>>(dev_solution, size, lo, hi, sigma, choice);
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(msec, start, stop);
hipMemcpy(solution, dev_solution, sizeof(double)*size, hipMemcpyDeviceToHost);
hipFree(&dev_solution);
}
void printCudaInfo()
{
// for fun, just print out some stats on the machine
int deviceCount = 0;
hipError_t err = hipGetDeviceCount(&deviceCount);
printf("---------------------------------------------------------\n");
printf("Found %d CUDA devices\n", deviceCount);
for (int i=0; i<deviceCount; i++)
{
hipDeviceProp_t deviceProps;
hipGetDeviceProperties(&deviceProps, i);
printf("Device %d: %s\n", i, deviceProps.name);
printf(" SMs: %d\n", deviceProps.multiProcessorCount);
printf(" Global mem: %.0f MB\n",
static_cast<double>(deviceProps.totalGlobalMem) / (1024 * 1024));
printf(" CUDA Cap: %d.%d\n", deviceProps.major, deviceProps.minor);
}
printf("---------------------------------------------------------\n");
} | .text
.file "cuda_opt_SA.hip"
.globl _Z24__device_stub__sa_kernelPdidddi # -- Begin function _Z24__device_stub__sa_kernelPdidddi
.p2align 4, 0x90
.type _Z24__device_stub__sa_kernelPdidddi,@function
_Z24__device_stub__sa_kernelPdidddi: # @_Z24__device_stub__sa_kernelPdidddi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 12(%rsp)
movsd %xmm0, 80(%rsp)
movsd %xmm1, 72(%rsp)
movsd %xmm2, 64(%rsp)
movl %edx, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9sa_kernelPdidddi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z24__device_stub__sa_kernelPdidddi, .Lfunc_end0-_Z24__device_stub__sa_kernelPdidddi
.cfi_endproc
# -- End function
.globl _Z23simulate_annealing_cudaPdidddPfi # -- Begin function _Z23simulate_annealing_cudaPdidddPfi
.p2align 4, 0x90
.type _Z23simulate_annealing_cudaPdidddPfi,@function
_Z23simulate_annealing_cudaPdidddPfi: # @_Z23simulate_annealing_cudaPdidddPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %r14
movsd %xmm2, 56(%rsp) # 8-byte Spill
movsd %xmm1, 48(%rsp) # 8-byte Spill
movsd %xmm0, 40(%rsp) # 8-byte Spill
movl %esi, %r12d
movq %rdi, %rbx
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
leal 255(%r12), %r13d
testl %r12d, %r12d
cmovnsl %r12d, %r13d
sarl $8, %r13d
incl %r13d
movslq %r12d, %r15
shlq $3, %r15
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %r13
orq $256, %rdx # imm = 0x100
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 136(%rsp)
movl %r12d, 28(%rsp)
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 128(%rsp)
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 120(%rsp)
movsd 56(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 112(%rsp)
movl %ebp, 24(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 28(%rsp), %rax
movq %rax, 152(%rsp)
leaq 128(%rsp), %rax
movq %rax, 160(%rsp)
leaq 120(%rsp), %rax
movq %rax, 168(%rsp)
leaq 112(%rsp), %rax
movq %rax, 176(%rsp)
leaq 24(%rsp), %rax
movq %rax, 184(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z9sa_kernelPdidddi, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
movq %r14, %rdi
callq hipEventElapsedTime
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
callq hipFree
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z23simulate_annealing_cudaPdidddPfi, .Lfunc_end1-_Z23simulate_annealing_cudaPdidddPfi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z13printCudaInfov
.LCPI2_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI2_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_2:
.quad 0x3eb0000000000000 # double 9.5367431640625E-7
.text
.globl _Z13printCudaInfov
.p2align 4, 0x90
.type _Z13printCudaInfov,@function
_Z13printCudaInfov: # @_Z13printCudaInfov
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl $.Lstr.1, %edi
callq puts@PLT
movl 4(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpl $0, 4(%rsp)
jle .LBB2_3
# %bb.1: # %.lr.ph
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.2, %edi
movl %ebp, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
movl 396(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movsd 296(%rsp), %xmm1 # xmm1 = mem[0],zero
unpcklps .LCPI2_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI2_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
mulsd .LCPI2_2(%rip), %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movl 368(%rsp), %esi
movl 372(%rsp), %edx
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB2_2
.LBB2_3: # %._crit_edge
movl $.Lstr.1, %edi
callq puts@PLT
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z13printCudaInfov, .Lfunc_end2-_Z13printCudaInfov
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9sa_kernelPdidddi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9sa_kernelPdidddi,@object # @_Z9sa_kernelPdidddi
.section .rodata,"a",@progbits
.globl _Z9sa_kernelPdidddi
.p2align 3, 0x0
_Z9sa_kernelPdidddi:
.quad _Z24__device_stub__sa_kernelPdidddi
.size _Z9sa_kernelPdidddi, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Found %d CUDA devices\n"
.size .L.str.1, 23
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device %d: %s\n"
.size .L.str.2, 15
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " SMs: %d\n"
.size .L.str.3, 19
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " Global mem: %.0f MB\n"
.size .L.str.4, 24
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " CUDA Cap: %d.%d\n"
.size .L.str.5, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9sa_kernelPdidddi"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "---------------------------------------------------------"
.size .Lstr.1, 58
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__sa_kernelPdidddi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9sa_kernelPdidddi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001568bb_00000000-6_cuda_opt_SA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4038:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4038:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14rastrigin_cudaPdid
.type _Z14rastrigin_cudaPdid, @function
_Z14rastrigin_cudaPdid:
.LFB4032:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4032:
.size _Z14rastrigin_cudaPdid, .-_Z14rastrigin_cudaPdid
.globl _Z11ackley_cudaPdid
.type _Z11ackley_cudaPdid, @function
_Z11ackley_cudaPdid:
.LFB4033:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4033:
.size _Z11ackley_cudaPdid, .-_Z11ackley_cudaPdid
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "---------------------------------------------------------\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Found %d CUDA devices\n"
.LC2:
.string "Device %d: %s\n"
.LC3:
.string " SMs: %d\n"
.LC5:
.string " Global mem: %.0f MB\n"
.LC6:
.string " CUDA Cap: %d.%d\n"
.text
.globl _Z13printCudaInfov
.type _Z13printCudaInfov, @function
_Z13printCudaInfov:
.LFB4035:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $1056, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L8
movl $0, %ebx
leaq .LC2(%rip), %r13
leaq .LC3(%rip), %r12
leaq .LC5(%rip), %rbp
jmp .L11
.L9:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
.L10:
mulsd .LC4(%rip), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L8
.L11:
leaq 16(%rsp), %r14
movl %ebx, %esi
movq %r14, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %r14, %rcx
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rax
testq %rax, %rax
js .L9
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
jmp .L10
.L8:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4035:
.size _Z13printCudaInfov, .-_Z13printCudaInfov
.globl _Z33__device_stub__Z9sa_kernelPdidddiPdidddi
.type _Z33__device_stub__Z9sa_kernelPdidddiPdidddi, @function
_Z33__device_stub__Z9sa_kernelPdidddiPdidddi:
.LFB4060:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movsd %xmm0, 24(%rsp)
movsd %xmm1, 16(%rsp)
movsd %xmm2, 8(%rsp)
movl %edx, 32(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9sa_kernelPdidddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4060:
.size _Z33__device_stub__Z9sa_kernelPdidddiPdidddi, .-_Z33__device_stub__Z9sa_kernelPdidddiPdidddi
.globl _Z9sa_kernelPdidddi
.type _Z9sa_kernelPdidddi, @function
_Z9sa_kernelPdidddi:
.LFB4061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9sa_kernelPdidddiPdidddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4061:
.size _Z9sa_kernelPdidddi, .-_Z9sa_kernelPdidddi
.globl _Z23simulate_annealing_cudaPdidddPfi
.type _Z23simulate_annealing_cudaPdidddPfi, @function
_Z23simulate_annealing_cudaPdidddPfi:
.LFB4034:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $96, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %r12
movl %esi, %ebx
movsd %xmm0, 8(%rsp)
movsd %xmm1, 16(%rsp)
movsd %xmm2, 24(%rsp)
movq %rdx, %r13
movl %ecx, %r14d
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movslq %ebx, %rbp
salq $3, %rbp
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 76(%rsp)
movl $1, 80(%rsp)
leal 255(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $8, %eax
addl $1, %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L25:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaEventElapsedTime@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movl %r14d, %edx
movsd 24(%rsp), %xmm2
movsd 16(%rsp), %xmm1
movsd 8(%rsp), %xmm0
movl %ebx, %esi
movq 56(%rsp), %rdi
call _Z33__device_stub__Z9sa_kernelPdidddiPdidddi
jmp .L25
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4034:
.size _Z23simulate_annealing_cudaPdidddPfi, .-_Z23simulate_annealing_cudaPdidddPfi
.section .rodata.str1.1
.LC7:
.string "_Z9sa_kernelPdidddi"
.LC8:
.string "precalc_xorwow_matrix"
.LC9:
.string "precalc_xorwow_offset_matrix"
.LC10:
.string "mrg32k3aM1"
.LC11:
.string "mrg32k3aM2"
.LC12:
.string "mrg32k3aM1SubSeq"
.LC13:
.string "mrg32k3aM2SubSeq"
.LC14:
.string "mrg32k3aM1Seq"
.LC15:
.string "mrg32k3aM2Seq"
.LC16:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4063:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9sa_kernelPdidddi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4063:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1051721728
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_opt_SA.hip"
.globl _Z24__device_stub__sa_kernelPdidddi # -- Begin function _Z24__device_stub__sa_kernelPdidddi
.p2align 4, 0x90
.type _Z24__device_stub__sa_kernelPdidddi,@function
_Z24__device_stub__sa_kernelPdidddi: # @_Z24__device_stub__sa_kernelPdidddi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 12(%rsp)
movsd %xmm0, 80(%rsp)
movsd %xmm1, 72(%rsp)
movsd %xmm2, 64(%rsp)
movl %edx, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9sa_kernelPdidddi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z24__device_stub__sa_kernelPdidddi, .Lfunc_end0-_Z24__device_stub__sa_kernelPdidddi
.cfi_endproc
# -- End function
.globl _Z23simulate_annealing_cudaPdidddPfi # -- Begin function _Z23simulate_annealing_cudaPdidddPfi
.p2align 4, 0x90
.type _Z23simulate_annealing_cudaPdidddPfi,@function
_Z23simulate_annealing_cudaPdidddPfi: # @_Z23simulate_annealing_cudaPdidddPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %r14
movsd %xmm2, 56(%rsp) # 8-byte Spill
movsd %xmm1, 48(%rsp) # 8-byte Spill
movsd %xmm0, 40(%rsp) # 8-byte Spill
movl %esi, %r12d
movq %rdi, %rbx
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
leal 255(%r12), %r13d
testl %r12d, %r12d
cmovnsl %r12d, %r13d
sarl $8, %r13d
incl %r13d
movslq %r12d, %r15
shlq $3, %r15
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %r13
orq $256, %rdx # imm = 0x100
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 136(%rsp)
movl %r12d, 28(%rsp)
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 128(%rsp)
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 120(%rsp)
movsd 56(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 112(%rsp)
movl %ebp, 24(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 28(%rsp), %rax
movq %rax, 152(%rsp)
leaq 128(%rsp), %rax
movq %rax, 160(%rsp)
leaq 120(%rsp), %rax
movq %rax, 168(%rsp)
leaq 112(%rsp), %rax
movq %rax, 176(%rsp)
leaq 24(%rsp), %rax
movq %rax, 184(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z9sa_kernelPdidddi, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
movq %r14, %rdi
callq hipEventElapsedTime
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
callq hipFree
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z23simulate_annealing_cudaPdidddPfi, .Lfunc_end1-_Z23simulate_annealing_cudaPdidddPfi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z13printCudaInfov
.LCPI2_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI2_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_2:
.quad 0x3eb0000000000000 # double 9.5367431640625E-7
.text
.globl _Z13printCudaInfov
.p2align 4, 0x90
.type _Z13printCudaInfov,@function
_Z13printCudaInfov: # @_Z13printCudaInfov
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl $.Lstr.1, %edi
callq puts@PLT
movl 4(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpl $0, 4(%rsp)
jle .LBB2_3
# %bb.1: # %.lr.ph
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.2, %edi
movl %ebp, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
movl 396(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movsd 296(%rsp), %xmm1 # xmm1 = mem[0],zero
unpcklps .LCPI2_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI2_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
mulsd .LCPI2_2(%rip), %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movl 368(%rsp), %esi
movl 372(%rsp), %edx
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB2_2
.LBB2_3: # %._crit_edge
movl $.Lstr.1, %edi
callq puts@PLT
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z13printCudaInfov, .Lfunc_end2-_Z13printCudaInfov
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9sa_kernelPdidddi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9sa_kernelPdidddi,@object # @_Z9sa_kernelPdidddi
.section .rodata,"a",@progbits
.globl _Z9sa_kernelPdidddi
.p2align 3, 0x0
_Z9sa_kernelPdidddi:
.quad _Z24__device_stub__sa_kernelPdidddi
.size _Z9sa_kernelPdidddi, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Found %d CUDA devices\n"
.size .L.str.1, 23
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device %d: %s\n"
.size .L.str.2, 15
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " SMs: %d\n"
.size .L.str.3, 19
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " Global mem: %.0f MB\n"
.size .L.str.4, 24
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " CUDA Cap: %d.%d\n"
.size .L.str.5, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9sa_kernelPdidddi"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "---------------------------------------------------------"
.size .Lstr.1, 58
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__sa_kernelPdidddi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9sa_kernelPdidddi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define THETA_N 4
#define SQRT_2 1.4142135623730951f
#define PI 3.141592653589793f
extern "C" {
/**
* Clears out the Gabor Energies Tensor, setting all of its values to zero.
* The Gabor Energies Tensor is the data structure whose [y, x, theta] value contains the average magnitude response to
* the different complex 'Gabor' filters for an specific 'theta' orientation at 'image' location (y, x).
* This is the first step towards its calculation. Note that the number of rows and columns in the Gabor Energies Tensor
* is (image_rows - (kernel_size >> 1)) X (image_cols - (kernel_size >> 1)) due to the padding lost at convolution.
* @param gabor_energies The Gabor Energies Tensor.
* @param rows The number of rows in the 'image' whose Energies Tensor will be calculated.
* @param cols The number of columns in the 'image' whose Energies Tensor will be calculated.
* @param kernel_size Both the number of rows and columns in the Gabor kernels to apply. Should be an odd number.
*/
__global__ void resetGaborEnergiesTensor(float* gabor_energies, int rows, int cols, int kernel_size)
{
int image_y = blockDim.y * blockIdx.y + threadIdx.y;
int image_x = blockDim.x * blockIdx.x + threadIdx.x;
int image_padding = (kernel_size >> 1);
if (image_y < image_padding || image_y + image_padding >= rows ||
image_x < image_padding || image_x + image_padding >= cols)
return; // Part of the padding lost due to lack of border information.
int tensor_offset = ((image_y - image_padding) * (cols - (image_padding << 1)) + (image_x - image_padding)) * THETA_N;
for (int i = 0; i < THETA_N; i++)
gabor_energies[tensor_offset + i] = 0.0f;
}
/**
* Applies a 2D Complex Convolution on a real image given a square kernel and adds its magnitude response to the
* corresponding [y, x, theta] location in the Gabor Energies Tensor.
* This kernel is the second step towards its calculation and should be called once for every frequency to apply.
* @param gabor_energies The Gabor Energies Tensor.
* @param theta_idx The orientation index for the Gabor Energies Tensor specifying the orientation for which to add
* this convolution.
* @param image The image on which to apply the convolution operation.
* @param rows The number of rows in 'image'.
* @param cols The number of columns in 'image'.
* @param real_kernel The real part of the square convolution kernel to apply on 'image'.
* @param imag_kernel The imaginary part of the square convolution kernel to apply on 'image'.
* @param kernel_size Both the number of rows and columns in 'kernel'. Should be an odd number.
*/
__global__ void addGaborFilterMagnitudeResponse(float* gabor_energies, int theta_idx,
unsigned char* image, int rows, int cols,
float* real_kernel, float* imag_kernel, int kernel_size)
{
int image_y = blockDim.y * blockIdx.y + threadIdx.y;
int image_x = blockDim.x * blockIdx.x + threadIdx.x;
int image_padding = (kernel_size >> 1);
if (image_y < image_padding || image_y + image_padding >= rows ||
image_x < image_padding || image_x + image_padding >= cols)
return; // Part of the padding lost due to lack of border information.
int image_idx = (image_y - image_padding) * cols + (image_x - image_padding), kernel_idx = 0;
float real_response = 0.0f, imag_response = 0.0f;
for (int i = 0; i < kernel_size; i++)
{
for (int j = 0; j < kernel_size; j++)
{
real_response += image[image_idx] * real_kernel[kernel_idx];
imag_response += image[image_idx] * imag_kernel[kernel_idx];
image_idx++;
kernel_idx++;
}
image_idx += cols - kernel_size;
}
int tensor_offset = ((image_y - image_padding) * (cols - (image_padding << 1)) + (image_x - image_padding)) * THETA_N;
gabor_energies[tensor_offset + theta_idx] = sqrtf(real_response * real_response + imag_response * imag_response);
}
/**
* Divides all of the Gabor Energies Tensor elements by a constant.
* This is the third and last step to calculate the Tensor. This step is used to average out the magnitude responses of
* the different applied Gabor kernels: for a given [y, x, theta], one is applied per frequency.
* @param gabor_energies The Gabor Energies Tensor.
* @param rows The number of rows in the 'image' whose Energies Tensor will be calculated.
* @param cols The number of columns in the 'image' whose Energies Tensor will be calculated.
* @param kernel_size Both the number of rows and columns in the applied Gabor kernels. Should be an odd number.
* @param constant The number by which to divide all of the Gabor Energies Tensor elements. Should be equal to the
* number of applied frequencies.
*/
__global__ void divideGaborEnergiesTensor(float* gabor_energies, int rows, int cols, int kernel_size, int constant)
{
int image_y = blockDim.y * blockIdx.y + threadIdx.y;
int image_x = blockDim.x * blockIdx.x + threadIdx.x;
int image_padding = (kernel_size >> 1);
if (image_y < image_padding || image_y + image_padding >= rows ||
image_x < image_padding || image_x + image_padding >= cols)
return; // Part of the padding lost due to lack of border information.
int tensor_offset = ((image_y - image_padding) * (cols - (image_padding << 1)) + (image_x - image_padding)) * THETA_N;
for (int i = 0; i < THETA_N; i++)
gabor_energies[tensor_offset + i] /= constant;
}
/**
* Combines the Gabor Energies Tensor into a Matrix by joining the magnitude response of the different thetas into a
* single one with a corresponding combined energy and combined phase (angle). This takes into consideration the two
* strongest orientations (thetas) and linearly joining their equivalent plane components. The two weakest components
* are subtracted from the strongest ones since random textures tend to equally respond to different Gabor kernels.
* @param gabor_energies The Gabor Energies Tensor.
* @param rows The number of rows in 'gabor_energies'.
* @param cols The number of columns in 'gabor_energies'.
* @param combined_energies The resulting magnitude response from combining the Gabor energies at different thetas.
* @param combined_phases The resulting phase response from combining the Gabor energies at different thetas.
*/
__global__ void combineGaborEnergies(float* gabor_energies, int rows, int cols,
float* combined_energies, float* combined_phases)
{
int image_y = blockDim.y * blockIdx.y + threadIdx.y;
int image_x = blockDim.x * blockIdx.x + threadIdx.x;
int offset = image_y * cols + image_x;
if (image_y >= rows || image_x >= cols)
return; // Out of image.
int descending_energies_arg[THETA_N];
float temp_energies[THETA_N];
for (int i = 0; i < THETA_N; i++)
temp_energies[i] = gabor_energies[THETA_N * offset + i];
for (int i = 0; i < THETA_N; i++)
{
int max_idx = 0;
float max_energy = temp_energies[0];
for (int j = 1; j < THETA_N; j++)
if (temp_energies[j] > max_energy)
{
max_idx = j;
max_energy = temp_energies[j];
}
descending_energies_arg[i] = max_idx;
temp_energies[max_idx] = -1.0f;
}
float s1 = (gabor_energies[THETA_N * offset + descending_energies_arg[0]] -
gabor_energies[THETA_N * offset + descending_energies_arg[3]]);
float s2 = (gabor_energies[THETA_N * offset + descending_energies_arg[1]] -
gabor_energies[THETA_N * offset + descending_energies_arg[2]]);
int theta_idx1 = descending_energies_arg[0];
int theta_idx2 = descending_energies_arg[1];
float combined_y = 0.0f, combined_x = 0.0f;
switch(theta_idx1)
{
case 0:
if (theta_idx2 == 1)
{
combined_y = s1 + s2 / SQRT_2;
combined_x = s2 / SQRT_2;
}
else if (theta_idx2 == 3)
{
combined_y = s1 + s2 / SQRT_2;
combined_x = -s2 / SQRT_2;
}
break;
case 1:
if (theta_idx2 == 0)
{
combined_y = s1 / SQRT_2 + s2;
combined_x = s1 / SQRT_2;
}
else if (theta_idx2 == 2)
{
combined_y = s1 / SQRT_2;
combined_x = s1 / SQRT_2 + s2;
}
break;
case 2:
if (theta_idx2 == 1)
{
combined_y = s2 / SQRT_2;
combined_x = s1 + s2 / SQRT_2;
}
else if (theta_idx2 == 3)
{
combined_y = s2 / SQRT_2;
combined_x = -s1 - s2 / SQRT_2;
}
break;
case 3:
if (theta_idx2 == 0)
{
combined_y = s1 / SQRT_2 + s2;
combined_x = -s1 / SQRT_2;
}
else if (theta_idx2 == 2)
{
combined_y = s1 / SQRT_2;
combined_x = -s1 / SQRT_2 - s2;
}
break;
}
combined_energies[offset] = sqrtf(combined_y * combined_y + combined_x * combined_x);
combined_phases[offset] = atan2f(combined_y, combined_x);
}
/**
* Generates votes for all of the Vanishing Point candidates by allowing all of the voting region to assign a voting
* weight for their preferred candidates. The candidate region is assumed to be directly above the voting region
* (combined components) such that concatenated are part of a continuous region of the original image.
* @param combined_energies The resulting magnitude response from combining the Gabor energies at different thetas.
* @param combined_phases The resulting phase response from combining the Gabor energies at different thetas.
* @param candidates The Vanishing Point candidates, being a region directly above the voting region which should also
* correspond to a stripe around the horizon line.
* @param voters_rows The number of rows in both 'combined_energies' and 'combined_phases'.
* @param candidates_rows The number of rows in 'candidates'.
* @param cols The number of columns in all three: 'combined_energies', 'combined_phases', and 'candidates'.
*/
__global__ void voteForVanishingPointCandidates(float* combined_energies, float* combined_phases, float* candidates,
int voters_rows, int candidates_rows, int cols)
{
int image_y = blockDim.y * blockIdx.y + threadIdx.y;
int image_x = blockDim.x * blockIdx.x + threadIdx.x;
if (image_y >= voters_rows || image_x >= cols)
return; // Out of image.
int energies_offset = image_y * cols + image_x;
int candidates_y_offset = candidates_rows * cols;
float energy = combined_energies[energies_offset];
float phase = combined_phases[energies_offset];
float cot = 1.0f / tanf(phase);
for (int candidates_y = candidates_rows - 1; candidates_y >= 0; candidates_y--)
{
candidates_y_offset -= cols;
int y_delta = image_y + candidates_rows - candidates_y;
int candidates_x = image_x + cot * y_delta;
if (candidates_x >= 0 && candidates_x < cols)
atomicAdd(&candidates[candidates_y_offset + candidates_x], energy);
}
}
} | .file "tmpxft_0007cb39_00000000-6_vanishing_point_detector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z24resetGaborEnergiesTensorPfiiiPfiii
.type _Z47__device_stub__Z24resetGaborEnergiesTensorPfiiiPfiii, @function
_Z47__device_stub__Z24resetGaborEnergiesTensorPfiiiPfiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq resetGaborEnergiesTensor(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z24resetGaborEnergiesTensorPfiiiPfiii, .-_Z47__device_stub__Z24resetGaborEnergiesTensorPfiiiPfiii
.globl resetGaborEnergiesTensor
.type resetGaborEnergiesTensor, @function
resetGaborEnergiesTensor:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z24resetGaborEnergiesTensorPfiiiPfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size resetGaborEnergiesTensor, .-resetGaborEnergiesTensor
.globl _Z61__device_stub__Z31addGaborFilterMagnitudeResponsePfiPhiiS_S_iPfiPhiiS_S_i
.type _Z61__device_stub__Z31addGaborFilterMagnitudeResponsePfiPhiiS_S_iPfiPhiiS_S_i, @function
_Z61__device_stub__Z31addGaborFilterMagnitudeResponsePfiPhiiS_S_iPfiPhiiS_S_i:
.LFB2053:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 32(%rsp)
movl %r8d, 20(%rsp)
movq %r9, 8(%rsp)
movq 208(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq addGaborFilterMagnitudeResponse(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z61__device_stub__Z31addGaborFilterMagnitudeResponsePfiPhiiS_S_iPfiPhiiS_S_i, .-_Z61__device_stub__Z31addGaborFilterMagnitudeResponsePfiPhiiS_S_iPfiPhiiS_S_i
.globl addGaborFilterMagnitudeResponse
.type addGaborFilterMagnitudeResponse, @function
addGaborFilterMagnitudeResponse:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z61__device_stub__Z31addGaborFilterMagnitudeResponsePfiPhiiS_S_iPfiPhiiS_S_i
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size addGaborFilterMagnitudeResponse, .-addGaborFilterMagnitudeResponse
.globl _Z49__device_stub__Z25divideGaborEnergiesTensorPfiiiiPfiiii
.type _Z49__device_stub__Z25divideGaborEnergiesTensorPfiiiiPfiiii, @function
_Z49__device_stub__Z25divideGaborEnergiesTensorPfiiiiPfiiii:
.LFB2055:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq divideGaborEnergiesTensor(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z49__device_stub__Z25divideGaborEnergiesTensorPfiiiiPfiiii, .-_Z49__device_stub__Z25divideGaborEnergiesTensorPfiiiiPfiiii
.globl divideGaborEnergiesTensor
.type divideGaborEnergiesTensor, @function
divideGaborEnergiesTensor:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z25divideGaborEnergiesTensorPfiiiiPfiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size divideGaborEnergiesTensor, .-divideGaborEnergiesTensor
.globl _Z46__device_stub__Z20combineGaborEnergiesPfiiS_S_PfiiS_S_
.type _Z46__device_stub__Z20combineGaborEnergiesPfiiS_S_PfiiS_S_, @function
_Z46__device_stub__Z20combineGaborEnergiesPfiiS_S_PfiiS_S_:
.LFB2057:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq combineGaborEnergies(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z46__device_stub__Z20combineGaborEnergiesPfiiS_S_PfiiS_S_, .-_Z46__device_stub__Z20combineGaborEnergiesPfiiS_S_PfiiS_S_
.globl combineGaborEnergies
.type combineGaborEnergies, @function
combineGaborEnergies:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z20combineGaborEnergiesPfiiS_S_PfiiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size combineGaborEnergies, .-combineGaborEnergies
.globl _Z58__device_stub__Z31voteForVanishingPointCandidatesPfS_S_iiiPfS_S_iii
.type _Z58__device_stub__Z31voteForVanishingPointCandidatesPfS_S_iiiPfS_S_iii, @function
_Z58__device_stub__Z31voteForVanishingPointCandidatesPfS_S_iiiPfS_S_iii:
.LFB2059:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq voteForVanishingPointCandidates(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z58__device_stub__Z31voteForVanishingPointCandidatesPfS_S_iiiPfS_S_iii, .-_Z58__device_stub__Z31voteForVanishingPointCandidatesPfS_S_iiiPfS_S_iii
.globl voteForVanishingPointCandidates
.type voteForVanishingPointCandidates, @function
voteForVanishingPointCandidates:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z58__device_stub__Z31voteForVanishingPointCandidatesPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size voteForVanishingPointCandidates, .-voteForVanishingPointCandidates
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "voteForVanishingPointCandidates"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "combineGaborEnergies"
.LC2:
.string "divideGaborEnergiesTensor"
.section .rodata.str1.8
.align 8
.LC3:
.string "addGaborFilterMagnitudeResponse"
.section .rodata.str1.1
.LC4:
.string "resetGaborEnergiesTensor"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2062:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq voteForVanishingPointCandidates(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq combineGaborEnergies(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq divideGaborEnergiesTensor(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq addGaborFilterMagnitudeResponse(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq resetGaborEnergiesTensor(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define THETA_N 4
#define SQRT_2 1.4142135623730951f
#define PI 3.141592653589793f
extern "C" {
/**
* Clears out the Gabor Energies Tensor, setting all of its values to zero.
* The Gabor Energies Tensor is the data structure whose [y, x, theta] value contains the average magnitude response to
* the different complex 'Gabor' filters for an specific 'theta' orientation at 'image' location (y, x).
* This is the first step towards its calculation. Note that the number of rows and columns in the Gabor Energies Tensor
* is (image_rows - (kernel_size >> 1)) X (image_cols - (kernel_size >> 1)) due to the padding lost at convolution.
* @param gabor_energies The Gabor Energies Tensor.
* @param rows The number of rows in the 'image' whose Energies Tensor will be calculated.
* @param cols The number of columns in the 'image' whose Energies Tensor will be calculated.
* @param kernel_size Both the number of rows and columns in the Gabor kernels to apply. Should be an odd number.
*/
__global__ void resetGaborEnergiesTensor(float* gabor_energies, int rows, int cols, int kernel_size)
{
int image_y = blockDim.y * blockIdx.y + threadIdx.y;
int image_x = blockDim.x * blockIdx.x + threadIdx.x;
int image_padding = (kernel_size >> 1);
if (image_y < image_padding || image_y + image_padding >= rows ||
image_x < image_padding || image_x + image_padding >= cols)
return; // Part of the padding lost due to lack of border information.
int tensor_offset = ((image_y - image_padding) * (cols - (image_padding << 1)) + (image_x - image_padding)) * THETA_N;
for (int i = 0; i < THETA_N; i++)
gabor_energies[tensor_offset + i] = 0.0f;
}
/**
* Applies a 2D Complex Convolution on a real image given a square kernel and adds its magnitude response to the
* corresponding [y, x, theta] location in the Gabor Energies Tensor.
* This kernel is the second step towards its calculation and should be called once for every frequency to apply.
* @param gabor_energies The Gabor Energies Tensor.
* @param theta_idx The orientation index for the Gabor Energies Tensor specifying the orientation for which to add
* this convolution.
* @param image The image on which to apply the convolution operation.
* @param rows The number of rows in 'image'.
* @param cols The number of columns in 'image'.
* @param real_kernel The real part of the square convolution kernel to apply on 'image'.
* @param imag_kernel The imaginary part of the square convolution kernel to apply on 'image'.
* @param kernel_size Both the number of rows and columns in 'kernel'. Should be an odd number.
*/
__global__ void addGaborFilterMagnitudeResponse(float* gabor_energies, int theta_idx,
unsigned char* image, int rows, int cols,
float* real_kernel, float* imag_kernel, int kernel_size)
{
int image_y = blockDim.y * blockIdx.y + threadIdx.y;
int image_x = blockDim.x * blockIdx.x + threadIdx.x;
int image_padding = (kernel_size >> 1);
if (image_y < image_padding || image_y + image_padding >= rows ||
image_x < image_padding || image_x + image_padding >= cols)
return; // Part of the padding lost due to lack of border information.
int image_idx = (image_y - image_padding) * cols + (image_x - image_padding), kernel_idx = 0;
float real_response = 0.0f, imag_response = 0.0f;
for (int i = 0; i < kernel_size; i++)
{
for (int j = 0; j < kernel_size; j++)
{
real_response += image[image_idx] * real_kernel[kernel_idx];
imag_response += image[image_idx] * imag_kernel[kernel_idx];
image_idx++;
kernel_idx++;
}
image_idx += cols - kernel_size;
}
int tensor_offset = ((image_y - image_padding) * (cols - (image_padding << 1)) + (image_x - image_padding)) * THETA_N;
gabor_energies[tensor_offset + theta_idx] = sqrtf(real_response * real_response + imag_response * imag_response);
}
/**
* Divides all of the Gabor Energies Tensor elements by a constant.
* This is the third and last step to calculate the Tensor. This step is used to average out the magnitude responses of
* the different applied Gabor kernels: for a given [y, x, theta], one is applied per frequency.
* @param gabor_energies The Gabor Energies Tensor.
* @param rows The number of rows in the 'image' whose Energies Tensor will be calculated.
* @param cols The number of columns in the 'image' whose Energies Tensor will be calculated.
* @param kernel_size Both the number of rows and columns in the applied Gabor kernels. Should be an odd number.
* @param constant The number by which to divide all of the Gabor Energies Tensor elements. Should be equal to the
* number of applied frequencies.
*/
__global__ void divideGaborEnergiesTensor(float* gabor_energies, int rows, int cols, int kernel_size, int constant)
{
int image_y = blockDim.y * blockIdx.y + threadIdx.y;
int image_x = blockDim.x * blockIdx.x + threadIdx.x;
int image_padding = (kernel_size >> 1);
if (image_y < image_padding || image_y + image_padding >= rows ||
image_x < image_padding || image_x + image_padding >= cols)
return; // Part of the padding lost due to lack of border information.
int tensor_offset = ((image_y - image_padding) * (cols - (image_padding << 1)) + (image_x - image_padding)) * THETA_N;
for (int i = 0; i < THETA_N; i++)
gabor_energies[tensor_offset + i] /= constant;
}
/**
* Combines the Gabor Energies Tensor into a Matrix by joining the magnitude response of the different thetas into a
* single one with a corresponding combined energy and combined phase (angle). This takes into consideration the two
* strongest orientations (thetas) and linearly joining their equivalent plane components. The two weakest components
* are subtracted from the strongest ones since random textures tend to equally respond to different Gabor kernels.
* @param gabor_energies The Gabor Energies Tensor.
* @param rows The number of rows in 'gabor_energies'.
* @param cols The number of columns in 'gabor_energies'.
* @param combined_energies The resulting magnitude response from combining the Gabor energies at different thetas.
* @param combined_phases The resulting phase response from combining the Gabor energies at different thetas.
*/
__global__ void combineGaborEnergies(float* gabor_energies, int rows, int cols,
float* combined_energies, float* combined_phases)
{
int image_y = blockDim.y * blockIdx.y + threadIdx.y;
int image_x = blockDim.x * blockIdx.x + threadIdx.x;
int offset = image_y * cols + image_x;
if (image_y >= rows || image_x >= cols)
return; // Out of image.
int descending_energies_arg[THETA_N];
float temp_energies[THETA_N];
for (int i = 0; i < THETA_N; i++)
temp_energies[i] = gabor_energies[THETA_N * offset + i];
for (int i = 0; i < THETA_N; i++)
{
int max_idx = 0;
float max_energy = temp_energies[0];
for (int j = 1; j < THETA_N; j++)
if (temp_energies[j] > max_energy)
{
max_idx = j;
max_energy = temp_energies[j];
}
descending_energies_arg[i] = max_idx;
temp_energies[max_idx] = -1.0f;
}
float s1 = (gabor_energies[THETA_N * offset + descending_energies_arg[0]] -
gabor_energies[THETA_N * offset + descending_energies_arg[3]]);
float s2 = (gabor_energies[THETA_N * offset + descending_energies_arg[1]] -
gabor_energies[THETA_N * offset + descending_energies_arg[2]]);
int theta_idx1 = descending_energies_arg[0];
int theta_idx2 = descending_energies_arg[1];
float combined_y = 0.0f, combined_x = 0.0f;
switch(theta_idx1)
{
case 0:
if (theta_idx2 == 1)
{
combined_y = s1 + s2 / SQRT_2;
combined_x = s2 / SQRT_2;
}
else if (theta_idx2 == 3)
{
combined_y = s1 + s2 / SQRT_2;
combined_x = -s2 / SQRT_2;
}
break;
case 1:
if (theta_idx2 == 0)
{
combined_y = s1 / SQRT_2 + s2;
combined_x = s1 / SQRT_2;
}
else if (theta_idx2 == 2)
{
combined_y = s1 / SQRT_2;
combined_x = s1 / SQRT_2 + s2;
}
break;
case 2:
if (theta_idx2 == 1)
{
combined_y = s2 / SQRT_2;
combined_x = s1 + s2 / SQRT_2;
}
else if (theta_idx2 == 3)
{
combined_y = s2 / SQRT_2;
combined_x = -s1 - s2 / SQRT_2;
}
break;
case 3:
if (theta_idx2 == 0)
{
combined_y = s1 / SQRT_2 + s2;
combined_x = -s1 / SQRT_2;
}
else if (theta_idx2 == 2)
{
combined_y = s1 / SQRT_2;
combined_x = -s1 / SQRT_2 - s2;
}
break;
}
combined_energies[offset] = sqrtf(combined_y * combined_y + combined_x * combined_x);
combined_phases[offset] = atan2f(combined_y, combined_x);
}
/**
* Generates votes for all of the Vanishing Point candidates by allowing all of the voting region to assign a voting
* weight for their preferred candidates. The candidate region is assumed to be directly above the voting region
* (combined components) such that concatenated are part of a continuous region of the original image.
* @param combined_energies The resulting magnitude response from combining the Gabor energies at different thetas.
* @param combined_phases The resulting phase response from combining the Gabor energies at different thetas.
* @param candidates The Vanishing Point candidates, being a region directly above the voting region which should also
* correspond to a stripe around the horizon line.
* @param voters_rows The number of rows in both 'combined_energies' and 'combined_phases'.
* @param candidates_rows The number of rows in 'candidates'.
* @param cols The number of columns in all three: 'combined_energies', 'combined_phases', and 'candidates'.
*/
__global__ void voteForVanishingPointCandidates(float* combined_energies, float* combined_phases, float* candidates,
int voters_rows, int candidates_rows, int cols)
{
int image_y = blockDim.y * blockIdx.y + threadIdx.y;
int image_x = blockDim.x * blockIdx.x + threadIdx.x;
if (image_y >= voters_rows || image_x >= cols)
return; // Out of image.
int energies_offset = image_y * cols + image_x;
int candidates_y_offset = candidates_rows * cols;
float energy = combined_energies[energies_offset];
float phase = combined_phases[energies_offset];
float cot = 1.0f / tanf(phase);
for (int candidates_y = candidates_rows - 1; candidates_y >= 0; candidates_y--)
{
candidates_y_offset -= cols;
int y_delta = image_y + candidates_rows - candidates_y;
int candidates_x = image_x + cot * y_delta;
if (candidates_x >= 0 && candidates_x < cols)
atomicAdd(&candidates[candidates_y_offset + candidates_x], energy);
}
}
} | #include <hip/hip_runtime.h>
#define THETA_N 4
#define SQRT_2 1.4142135623730951f
#define PI 3.141592653589793f
extern "C" {
/**
* Clears out the Gabor Energies Tensor, setting all of its values to zero.
* The Gabor Energies Tensor is the data structure whose [y, x, theta] value contains the average magnitude response to
* the different complex 'Gabor' filters for an specific 'theta' orientation at 'image' location (y, x).
* This is the first step towards its calculation. Note that the number of rows and columns in the Gabor Energies Tensor
* is (image_rows - (kernel_size >> 1)) X (image_cols - (kernel_size >> 1)) due to the padding lost at convolution.
* @param gabor_energies The Gabor Energies Tensor.
* @param rows The number of rows in the 'image' whose Energies Tensor will be calculated.
* @param cols The number of columns in the 'image' whose Energies Tensor will be calculated.
* @param kernel_size Both the number of rows and columns in the Gabor kernels to apply. Should be an odd number.
*/
__global__ void resetGaborEnergiesTensor(float* gabor_energies, int rows, int cols, int kernel_size)
{
int image_y = blockDim.y * blockIdx.y + threadIdx.y;
int image_x = blockDim.x * blockIdx.x + threadIdx.x;
int image_padding = (kernel_size >> 1);
if (image_y < image_padding || image_y + image_padding >= rows ||
image_x < image_padding || image_x + image_padding >= cols)
return; // Part of the padding lost due to lack of border information.
int tensor_offset = ((image_y - image_padding) * (cols - (image_padding << 1)) + (image_x - image_padding)) * THETA_N;
for (int i = 0; i < THETA_N; i++)
gabor_energies[tensor_offset + i] = 0.0f;
}
/**
* Applies a 2D Complex Convolution on a real image given a square kernel and adds its magnitude response to the
* corresponding [y, x, theta] location in the Gabor Energies Tensor.
* This kernel is the second step towards its calculation and should be called once for every frequency to apply.
* @param gabor_energies The Gabor Energies Tensor.
* @param theta_idx The orientation index for the Gabor Energies Tensor specifying the orientation for which to add
* this convolution.
* @param image The image on which to apply the convolution operation.
* @param rows The number of rows in 'image'.
* @param cols The number of columns in 'image'.
* @param real_kernel The real part of the square convolution kernel to apply on 'image'.
* @param imag_kernel The imaginary part of the square convolution kernel to apply on 'image'.
* @param kernel_size Both the number of rows and columns in 'kernel'. Should be an odd number.
*/
__global__ void addGaborFilterMagnitudeResponse(float* gabor_energies, int theta_idx,
unsigned char* image, int rows, int cols,
float* real_kernel, float* imag_kernel, int kernel_size)
{
int image_y = blockDim.y * blockIdx.y + threadIdx.y;
int image_x = blockDim.x * blockIdx.x + threadIdx.x;
int image_padding = (kernel_size >> 1);
if (image_y < image_padding || image_y + image_padding >= rows ||
image_x < image_padding || image_x + image_padding >= cols)
return; // Part of the padding lost due to lack of border information.
int image_idx = (image_y - image_padding) * cols + (image_x - image_padding), kernel_idx = 0;
float real_response = 0.0f, imag_response = 0.0f;
for (int i = 0; i < kernel_size; i++)
{
for (int j = 0; j < kernel_size; j++)
{
real_response += image[image_idx] * real_kernel[kernel_idx];
imag_response += image[image_idx] * imag_kernel[kernel_idx];
image_idx++;
kernel_idx++;
}
image_idx += cols - kernel_size;
}
int tensor_offset = ((image_y - image_padding) * (cols - (image_padding << 1)) + (image_x - image_padding)) * THETA_N;
gabor_energies[tensor_offset + theta_idx] = sqrtf(real_response * real_response + imag_response * imag_response);
}
/**
* Divides all of the Gabor Energies Tensor elements by a constant.
* This is the third and last step to calculate the Tensor. This step is used to average out the magnitude responses of
* the different applied Gabor kernels: for a given [y, x, theta], one is applied per frequency.
* @param gabor_energies The Gabor Energies Tensor.
* @param rows The number of rows in the 'image' whose Energies Tensor will be calculated.
* @param cols The number of columns in the 'image' whose Energies Tensor will be calculated.
* @param kernel_size Both the number of rows and columns in the applied Gabor kernels. Should be an odd number.
* @param constant The number by which to divide all of the Gabor Energies Tensor elements. Should be equal to the
* number of applied frequencies.
*/
__global__ void divideGaborEnergiesTensor(float* gabor_energies, int rows, int cols, int kernel_size, int constant)
{
int image_y = blockDim.y * blockIdx.y + threadIdx.y;
int image_x = blockDim.x * blockIdx.x + threadIdx.x;
int image_padding = (kernel_size >> 1);
if (image_y < image_padding || image_y + image_padding >= rows ||
image_x < image_padding || image_x + image_padding >= cols)
return; // Part of the padding lost due to lack of border information.
int tensor_offset = ((image_y - image_padding) * (cols - (image_padding << 1)) + (image_x - image_padding)) * THETA_N;
for (int i = 0; i < THETA_N; i++)
gabor_energies[tensor_offset + i] /= constant;
}
/**
* Combines the Gabor Energies Tensor into a Matrix by joining the magnitude response of the different thetas into a
* single one with a corresponding combined energy and combined phase (angle). This takes into consideration the two
* strongest orientations (thetas) and linearly joining their equivalent plane components. The two weakest components
* are subtracted from the strongest ones since random textures tend to equally respond to different Gabor kernels.
* @param gabor_energies The Gabor Energies Tensor.
* @param rows The number of rows in 'gabor_energies'.
* @param cols The number of columns in 'gabor_energies'.
* @param combined_energies The resulting magnitude response from combining the Gabor energies at different thetas.
* @param combined_phases The resulting phase response from combining the Gabor energies at different thetas.
*/
__global__ void combineGaborEnergies(float* gabor_energies, int rows, int cols,
float* combined_energies, float* combined_phases)
{
int image_y = blockDim.y * blockIdx.y + threadIdx.y;
int image_x = blockDim.x * blockIdx.x + threadIdx.x;
int offset = image_y * cols + image_x;
if (image_y >= rows || image_x >= cols)
return; // Out of image.
int descending_energies_arg[THETA_N];
float temp_energies[THETA_N];
for (int i = 0; i < THETA_N; i++)
temp_energies[i] = gabor_energies[THETA_N * offset + i];
for (int i = 0; i < THETA_N; i++)
{
int max_idx = 0;
float max_energy = temp_energies[0];
for (int j = 1; j < THETA_N; j++)
if (temp_energies[j] > max_energy)
{
max_idx = j;
max_energy = temp_energies[j];
}
descending_energies_arg[i] = max_idx;
temp_energies[max_idx] = -1.0f;
}
float s1 = (gabor_energies[THETA_N * offset + descending_energies_arg[0]] -
gabor_energies[THETA_N * offset + descending_energies_arg[3]]);
float s2 = (gabor_energies[THETA_N * offset + descending_energies_arg[1]] -
gabor_energies[THETA_N * offset + descending_energies_arg[2]]);
int theta_idx1 = descending_energies_arg[0];
int theta_idx2 = descending_energies_arg[1];
float combined_y = 0.0f, combined_x = 0.0f;
switch(theta_idx1)
{
case 0:
if (theta_idx2 == 1)
{
combined_y = s1 + s2 / SQRT_2;
combined_x = s2 / SQRT_2;
}
else if (theta_idx2 == 3)
{
combined_y = s1 + s2 / SQRT_2;
combined_x = -s2 / SQRT_2;
}
break;
case 1:
if (theta_idx2 == 0)
{
combined_y = s1 / SQRT_2 + s2;
combined_x = s1 / SQRT_2;
}
else if (theta_idx2 == 2)
{
combined_y = s1 / SQRT_2;
combined_x = s1 / SQRT_2 + s2;
}
break;
case 2:
if (theta_idx2 == 1)
{
combined_y = s2 / SQRT_2;
combined_x = s1 + s2 / SQRT_2;
}
else if (theta_idx2 == 3)
{
combined_y = s2 / SQRT_2;
combined_x = -s1 - s2 / SQRT_2;
}
break;
case 3:
if (theta_idx2 == 0)
{
combined_y = s1 / SQRT_2 + s2;
combined_x = -s1 / SQRT_2;
}
else if (theta_idx2 == 2)
{
combined_y = s1 / SQRT_2;
combined_x = -s1 / SQRT_2 - s2;
}
break;
}
combined_energies[offset] = sqrtf(combined_y * combined_y + combined_x * combined_x);
combined_phases[offset] = atan2f(combined_y, combined_x);
}
/**
* Generates votes for all of the Vanishing Point candidates by allowing all of the voting region to assign a voting
* weight for their preferred candidates. The candidate region is assumed to be directly above the voting region
* (combined components) such that concatenated are part of a continuous region of the original image.
* @param combined_energies The resulting magnitude response from combining the Gabor energies at different thetas.
* @param combined_phases The resulting phase response from combining the Gabor energies at different thetas.
* @param candidates The Vanishing Point candidates, being a region directly above the voting region which should also
* correspond to a stripe around the horizon line.
* @param voters_rows The number of rows in both 'combined_energies' and 'combined_phases'.
* @param candidates_rows The number of rows in 'candidates'.
* @param cols The number of columns in all three: 'combined_energies', 'combined_phases', and 'candidates'.
*/
__global__ void voteForVanishingPointCandidates(float* combined_energies, float* combined_phases, float* candidates,
int voters_rows, int candidates_rows, int cols)
{
int image_y = blockDim.y * blockIdx.y + threadIdx.y;
int image_x = blockDim.x * blockIdx.x + threadIdx.x;
if (image_y >= voters_rows || image_x >= cols)
return; // Out of image.
int energies_offset = image_y * cols + image_x;
int candidates_y_offset = candidates_rows * cols;
float energy = combined_energies[energies_offset];
float phase = combined_phases[energies_offset];
float cot = 1.0f / tanf(phase);
for (int candidates_y = candidates_rows - 1; candidates_y >= 0; candidates_y--)
{
candidates_y_offset -= cols;
int y_delta = image_y + candidates_rows - candidates_y;
int candidates_x = image_x + cot * y_delta;
if (candidates_x >= 0 && candidates_x < cols)
atomicAdd(&candidates[candidates_y_offset + candidates_x], energy);
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define THETA_N 4
#define SQRT_2 1.4142135623730951f
#define PI 3.141592653589793f
extern "C" {
/**
* Clears out the Gabor Energies Tensor, setting all of its values to zero.
* The Gabor Energies Tensor is the data structure whose [y, x, theta] value contains the average magnitude response to
* the different complex 'Gabor' filters for an specific 'theta' orientation at 'image' location (y, x).
* This is the first step towards its calculation. Note that the number of rows and columns in the Gabor Energies Tensor
* is (image_rows - (kernel_size >> 1)) X (image_cols - (kernel_size >> 1)) due to the padding lost at convolution.
* @param gabor_energies The Gabor Energies Tensor.
* @param rows The number of rows in the 'image' whose Energies Tensor will be calculated.
* @param cols The number of columns in the 'image' whose Energies Tensor will be calculated.
* @param kernel_size Both the number of rows and columns in the Gabor kernels to apply. Should be an odd number.
*/
__global__ void resetGaborEnergiesTensor(float* gabor_energies, int rows, int cols, int kernel_size)
{
int image_y = blockDim.y * blockIdx.y + threadIdx.y;
int image_x = blockDim.x * blockIdx.x + threadIdx.x;
int image_padding = (kernel_size >> 1);
if (image_y < image_padding || image_y + image_padding >= rows ||
image_x < image_padding || image_x + image_padding >= cols)
return; // Part of the padding lost due to lack of border information.
int tensor_offset = ((image_y - image_padding) * (cols - (image_padding << 1)) + (image_x - image_padding)) * THETA_N;
for (int i = 0; i < THETA_N; i++)
gabor_energies[tensor_offset + i] = 0.0f;
}
/**
* Applies a 2D Complex Convolution on a real image given a square kernel and adds its magnitude response to the
* corresponding [y, x, theta] location in the Gabor Energies Tensor.
* This kernel is the second step towards its calculation and should be called once for every frequency to apply.
* @param gabor_energies The Gabor Energies Tensor.
* @param theta_idx The orientation index for the Gabor Energies Tensor specifying the orientation for which to add
* this convolution.
* @param image The image on which to apply the convolution operation.
* @param rows The number of rows in 'image'.
* @param cols The number of columns in 'image'.
* @param real_kernel The real part of the square convolution kernel to apply on 'image'.
* @param imag_kernel The imaginary part of the square convolution kernel to apply on 'image'.
* @param kernel_size Both the number of rows and columns in 'kernel'. Should be an odd number.
*/
__global__ void addGaborFilterMagnitudeResponse(float* gabor_energies, int theta_idx,
unsigned char* image, int rows, int cols,
float* real_kernel, float* imag_kernel, int kernel_size)
{
int image_y = blockDim.y * blockIdx.y + threadIdx.y;
int image_x = blockDim.x * blockIdx.x + threadIdx.x;
int image_padding = (kernel_size >> 1);
if (image_y < image_padding || image_y + image_padding >= rows ||
image_x < image_padding || image_x + image_padding >= cols)
return; // Part of the padding lost due to lack of border information.
int image_idx = (image_y - image_padding) * cols + (image_x - image_padding), kernel_idx = 0;
float real_response = 0.0f, imag_response = 0.0f;
for (int i = 0; i < kernel_size; i++)
{
for (int j = 0; j < kernel_size; j++)
{
real_response += image[image_idx] * real_kernel[kernel_idx];
imag_response += image[image_idx] * imag_kernel[kernel_idx];
image_idx++;
kernel_idx++;
}
image_idx += cols - kernel_size;
}
int tensor_offset = ((image_y - image_padding) * (cols - (image_padding << 1)) + (image_x - image_padding)) * THETA_N;
gabor_energies[tensor_offset + theta_idx] = sqrtf(real_response * real_response + imag_response * imag_response);
}
/**
* Divides all of the Gabor Energies Tensor elements by a constant.
* This is the third and last step to calculate the Tensor. This step is used to average out the magnitude responses of
* the different applied Gabor kernels: for a given [y, x, theta], one is applied per frequency.
* @param gabor_energies The Gabor Energies Tensor.
* @param rows The number of rows in the 'image' whose Energies Tensor will be calculated.
* @param cols The number of columns in the 'image' whose Energies Tensor will be calculated.
* @param kernel_size Both the number of rows and columns in the applied Gabor kernels. Should be an odd number.
* @param constant The number by which to divide all of the Gabor Energies Tensor elements. Should be equal to the
* number of applied frequencies.
*/
__global__ void divideGaborEnergiesTensor(float* gabor_energies, int rows, int cols, int kernel_size, int constant)
{
int image_y = blockDim.y * blockIdx.y + threadIdx.y;
int image_x = blockDim.x * blockIdx.x + threadIdx.x;
int image_padding = (kernel_size >> 1);
if (image_y < image_padding || image_y + image_padding >= rows ||
image_x < image_padding || image_x + image_padding >= cols)
return; // Part of the padding lost due to lack of border information.
int tensor_offset = ((image_y - image_padding) * (cols - (image_padding << 1)) + (image_x - image_padding)) * THETA_N;
for (int i = 0; i < THETA_N; i++)
gabor_energies[tensor_offset + i] /= constant;
}
/**
* Combines the Gabor Energies Tensor into a Matrix by joining the magnitude response of the different thetas into a
* single one with a corresponding combined energy and combined phase (angle). This takes into consideration the two
* strongest orientations (thetas) and linearly joining their equivalent plane components. The two weakest components
* are subtracted from the strongest ones since random textures tend to equally respond to different Gabor kernels.
* @param gabor_energies The Gabor Energies Tensor.
* @param rows The number of rows in 'gabor_energies'.
* @param cols The number of columns in 'gabor_energies'.
* @param combined_energies The resulting magnitude response from combining the Gabor energies at different thetas.
* @param combined_phases The resulting phase response from combining the Gabor energies at different thetas.
*/
__global__ void combineGaborEnergies(float* gabor_energies, int rows, int cols,
float* combined_energies, float* combined_phases)
{
int image_y = blockDim.y * blockIdx.y + threadIdx.y;
int image_x = blockDim.x * blockIdx.x + threadIdx.x;
int offset = image_y * cols + image_x;
if (image_y >= rows || image_x >= cols)
return; // Out of image.
int descending_energies_arg[THETA_N];
float temp_energies[THETA_N];
for (int i = 0; i < THETA_N; i++)
temp_energies[i] = gabor_energies[THETA_N * offset + i];
for (int i = 0; i < THETA_N; i++)
{
int max_idx = 0;
float max_energy = temp_energies[0];
for (int j = 1; j < THETA_N; j++)
if (temp_energies[j] > max_energy)
{
max_idx = j;
max_energy = temp_energies[j];
}
descending_energies_arg[i] = max_idx;
temp_energies[max_idx] = -1.0f;
}
float s1 = (gabor_energies[THETA_N * offset + descending_energies_arg[0]] -
gabor_energies[THETA_N * offset + descending_energies_arg[3]]);
float s2 = (gabor_energies[THETA_N * offset + descending_energies_arg[1]] -
gabor_energies[THETA_N * offset + descending_energies_arg[2]]);
int theta_idx1 = descending_energies_arg[0];
int theta_idx2 = descending_energies_arg[1];
float combined_y = 0.0f, combined_x = 0.0f;
switch(theta_idx1)
{
case 0:
if (theta_idx2 == 1)
{
combined_y = s1 + s2 / SQRT_2;
combined_x = s2 / SQRT_2;
}
else if (theta_idx2 == 3)
{
combined_y = s1 + s2 / SQRT_2;
combined_x = -s2 / SQRT_2;
}
break;
case 1:
if (theta_idx2 == 0)
{
combined_y = s1 / SQRT_2 + s2;
combined_x = s1 / SQRT_2;
}
else if (theta_idx2 == 2)
{
combined_y = s1 / SQRT_2;
combined_x = s1 / SQRT_2 + s2;
}
break;
case 2:
if (theta_idx2 == 1)
{
combined_y = s2 / SQRT_2;
combined_x = s1 + s2 / SQRT_2;
}
else if (theta_idx2 == 3)
{
combined_y = s2 / SQRT_2;
combined_x = -s1 - s2 / SQRT_2;
}
break;
case 3:
if (theta_idx2 == 0)
{
combined_y = s1 / SQRT_2 + s2;
combined_x = -s1 / SQRT_2;
}
else if (theta_idx2 == 2)
{
combined_y = s1 / SQRT_2;
combined_x = -s1 / SQRT_2 - s2;
}
break;
}
combined_energies[offset] = sqrtf(combined_y * combined_y + combined_x * combined_x);
combined_phases[offset] = atan2f(combined_y, combined_x);
}
/**
* Generates votes for all of the Vanishing Point candidates by allowing all of the voting region to assign a voting
* weight for their preferred candidates. The candidate region is assumed to be directly above the voting region
* (combined components) such that concatenated are part of a continuous region of the original image.
* @param combined_energies The resulting magnitude response from combining the Gabor energies at different thetas.
* @param combined_phases The resulting phase response from combining the Gabor energies at different thetas.
* @param candidates The Vanishing Point candidates, being a region directly above the voting region which should also
* correspond to a stripe around the horizon line.
* @param voters_rows The number of rows in both 'combined_energies' and 'combined_phases'.
* @param candidates_rows The number of rows in 'candidates'.
* @param cols The number of columns in all three: 'combined_energies', 'combined_phases', and 'candidates'.
*/
__global__ void voteForVanishingPointCandidates(float* combined_energies, float* combined_phases, float* candidates,
int voters_rows, int candidates_rows, int cols)
{
int image_y = blockDim.y * blockIdx.y + threadIdx.y;
int image_x = blockDim.x * blockIdx.x + threadIdx.x;
if (image_y >= voters_rows || image_x >= cols)
return; // Out of image.
int energies_offset = image_y * cols + image_x;
int candidates_y_offset = candidates_rows * cols;
float energy = combined_energies[energies_offset];
float phase = combined_phases[energies_offset];
float cot = 1.0f / tanf(phase);
for (int candidates_y = candidates_rows - 1; candidates_y >= 0; candidates_y--)
{
candidates_y_offset -= cols;
int y_delta = image_y + candidates_rows - candidates_y;
int candidates_x = image_x + cot * y_delta;
if (candidates_x >= 0 && candidates_x < cols)
atomicAdd(&candidates[candidates_y_offset + candidates_x], energy);
}
}
} | .text
.file "vanishing_point_detector.hip"
.globl __device_stub__resetGaborEnergiesTensor # -- Begin function __device_stub__resetGaborEnergiesTensor
.p2align 4, 0x90
.type __device_stub__resetGaborEnergiesTensor,@function
__device_stub__resetGaborEnergiesTensor: # @__device_stub__resetGaborEnergiesTensor
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $resetGaborEnergiesTensor, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__resetGaborEnergiesTensor, .Lfunc_end0-__device_stub__resetGaborEnergiesTensor
.cfi_endproc
# -- End function
.globl __device_stub__addGaborFilterMagnitudeResponse # -- Begin function __device_stub__addGaborFilterMagnitudeResponse
.p2align 4, 0x90
.type __device_stub__addGaborFilterMagnitudeResponse,@function
__device_stub__addGaborFilterMagnitudeResponse: # @__device_stub__addGaborFilterMagnitudeResponse
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 80(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $addGaborFilterMagnitudeResponse, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size __device_stub__addGaborFilterMagnitudeResponse, .Lfunc_end1-__device_stub__addGaborFilterMagnitudeResponse
.cfi_endproc
# -- End function
.globl __device_stub__divideGaborEnergiesTensor # -- Begin function __device_stub__divideGaborEnergiesTensor
.p2align 4, 0x90
.type __device_stub__divideGaborEnergiesTensor,@function
__device_stub__divideGaborEnergiesTensor: # @__device_stub__divideGaborEnergiesTensor
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $divideGaborEnergiesTensor, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size __device_stub__divideGaborEnergiesTensor, .Lfunc_end2-__device_stub__divideGaborEnergiesTensor
.cfi_endproc
# -- End function
.globl __device_stub__combineGaborEnergies # -- Begin function __device_stub__combineGaborEnergies
.p2align 4, 0x90
.type __device_stub__combineGaborEnergies,@function
__device_stub__combineGaborEnergies: # @__device_stub__combineGaborEnergies
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $combineGaborEnergies, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size __device_stub__combineGaborEnergies, .Lfunc_end3-__device_stub__combineGaborEnergies
.cfi_endproc
# -- End function
.globl __device_stub__voteForVanishingPointCandidates # -- Begin function __device_stub__voteForVanishingPointCandidates
.p2align 4, 0x90
.type __device_stub__voteForVanishingPointCandidates,@function
__device_stub__voteForVanishingPointCandidates: # @__device_stub__voteForVanishingPointCandidates
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $voteForVanishingPointCandidates, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end4:
.size __device_stub__voteForVanishingPointCandidates, .Lfunc_end4-__device_stub__voteForVanishingPointCandidates
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $resetGaborEnergiesTensor, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $addGaborFilterMagnitudeResponse, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $divideGaborEnergiesTensor, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $combineGaborEnergies, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $voteForVanishingPointCandidates, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type resetGaborEnergiesTensor,@object # @resetGaborEnergiesTensor
.section .rodata,"a",@progbits
.globl resetGaborEnergiesTensor
.p2align 3, 0x0
resetGaborEnergiesTensor:
.quad __device_stub__resetGaborEnergiesTensor
.size resetGaborEnergiesTensor, 8
.type addGaborFilterMagnitudeResponse,@object # @addGaborFilterMagnitudeResponse
.globl addGaborFilterMagnitudeResponse
.p2align 3, 0x0
addGaborFilterMagnitudeResponse:
.quad __device_stub__addGaborFilterMagnitudeResponse
.size addGaborFilterMagnitudeResponse, 8
.type divideGaborEnergiesTensor,@object # @divideGaborEnergiesTensor
.globl divideGaborEnergiesTensor
.p2align 3, 0x0
divideGaborEnergiesTensor:
.quad __device_stub__divideGaborEnergiesTensor
.size divideGaborEnergiesTensor, 8
.type combineGaborEnergies,@object # @combineGaborEnergies
.globl combineGaborEnergies
.p2align 3, 0x0
combineGaborEnergies:
.quad __device_stub__combineGaborEnergies
.size combineGaborEnergies, 8
.type voteForVanishingPointCandidates,@object # @voteForVanishingPointCandidates
.globl voteForVanishingPointCandidates
.p2align 3, 0x0
voteForVanishingPointCandidates:
.quad __device_stub__voteForVanishingPointCandidates
.size voteForVanishingPointCandidates, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "resetGaborEnergiesTensor"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "addGaborFilterMagnitudeResponse"
.size .L__unnamed_2, 32
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "divideGaborEnergiesTensor"
.size .L__unnamed_3, 26
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "combineGaborEnergies"
.size .L__unnamed_4, 21
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "voteForVanishingPointCandidates"
.size .L__unnamed_5, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__resetGaborEnergiesTensor
.addrsig_sym __device_stub__addGaborFilterMagnitudeResponse
.addrsig_sym __device_stub__divideGaborEnergiesTensor
.addrsig_sym __device_stub__combineGaborEnergies
.addrsig_sym __device_stub__voteForVanishingPointCandidates
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym resetGaborEnergiesTensor
.addrsig_sym addGaborFilterMagnitudeResponse
.addrsig_sym divideGaborEnergiesTensor
.addrsig_sym combineGaborEnergies
.addrsig_sym voteForVanishingPointCandidates
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007cb39_00000000-6_vanishing_point_detector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z24resetGaborEnergiesTensorPfiiiPfiii
.type _Z47__device_stub__Z24resetGaborEnergiesTensorPfiiiPfiii, @function
_Z47__device_stub__Z24resetGaborEnergiesTensorPfiiiPfiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq resetGaborEnergiesTensor(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z24resetGaborEnergiesTensorPfiiiPfiii, .-_Z47__device_stub__Z24resetGaborEnergiesTensorPfiiiPfiii
.globl resetGaborEnergiesTensor
.type resetGaborEnergiesTensor, @function
resetGaborEnergiesTensor:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z24resetGaborEnergiesTensorPfiiiPfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size resetGaborEnergiesTensor, .-resetGaborEnergiesTensor
.globl _Z61__device_stub__Z31addGaborFilterMagnitudeResponsePfiPhiiS_S_iPfiPhiiS_S_i
.type _Z61__device_stub__Z31addGaborFilterMagnitudeResponsePfiPhiiS_S_iPfiPhiiS_S_i, @function
_Z61__device_stub__Z31addGaborFilterMagnitudeResponsePfiPhiiS_S_iPfiPhiiS_S_i:
.LFB2053:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 32(%rsp)
movl %r8d, 20(%rsp)
movq %r9, 8(%rsp)
movq 208(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq addGaborFilterMagnitudeResponse(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z61__device_stub__Z31addGaborFilterMagnitudeResponsePfiPhiiS_S_iPfiPhiiS_S_i, .-_Z61__device_stub__Z31addGaborFilterMagnitudeResponsePfiPhiiS_S_iPfiPhiiS_S_i
.globl addGaborFilterMagnitudeResponse
.type addGaborFilterMagnitudeResponse, @function
addGaborFilterMagnitudeResponse:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z61__device_stub__Z31addGaborFilterMagnitudeResponsePfiPhiiS_S_iPfiPhiiS_S_i
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size addGaborFilterMagnitudeResponse, .-addGaborFilterMagnitudeResponse
.globl _Z49__device_stub__Z25divideGaborEnergiesTensorPfiiiiPfiiii
.type _Z49__device_stub__Z25divideGaborEnergiesTensorPfiiiiPfiiii, @function
_Z49__device_stub__Z25divideGaborEnergiesTensorPfiiiiPfiiii:
.LFB2055:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq divideGaborEnergiesTensor(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z49__device_stub__Z25divideGaborEnergiesTensorPfiiiiPfiiii, .-_Z49__device_stub__Z25divideGaborEnergiesTensorPfiiiiPfiiii
.globl divideGaborEnergiesTensor
.type divideGaborEnergiesTensor, @function
divideGaborEnergiesTensor:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z25divideGaborEnergiesTensorPfiiiiPfiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size divideGaborEnergiesTensor, .-divideGaborEnergiesTensor
.globl _Z46__device_stub__Z20combineGaborEnergiesPfiiS_S_PfiiS_S_
.type _Z46__device_stub__Z20combineGaborEnergiesPfiiS_S_PfiiS_S_, @function
_Z46__device_stub__Z20combineGaborEnergiesPfiiS_S_PfiiS_S_:
.LFB2057:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq combineGaborEnergies(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z46__device_stub__Z20combineGaborEnergiesPfiiS_S_PfiiS_S_, .-_Z46__device_stub__Z20combineGaborEnergiesPfiiS_S_PfiiS_S_
.globl combineGaborEnergies
.type combineGaborEnergies, @function
combineGaborEnergies:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z20combineGaborEnergiesPfiiS_S_PfiiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size combineGaborEnergies, .-combineGaborEnergies
.globl _Z58__device_stub__Z31voteForVanishingPointCandidatesPfS_S_iiiPfS_S_iii
.type _Z58__device_stub__Z31voteForVanishingPointCandidatesPfS_S_iiiPfS_S_iii, @function
_Z58__device_stub__Z31voteForVanishingPointCandidatesPfS_S_iiiPfS_S_iii:
.LFB2059:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq voteForVanishingPointCandidates(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z58__device_stub__Z31voteForVanishingPointCandidatesPfS_S_iiiPfS_S_iii, .-_Z58__device_stub__Z31voteForVanishingPointCandidatesPfS_S_iiiPfS_S_iii
.globl voteForVanishingPointCandidates
.type voteForVanishingPointCandidates, @function
voteForVanishingPointCandidates:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z58__device_stub__Z31voteForVanishingPointCandidatesPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size voteForVanishingPointCandidates, .-voteForVanishingPointCandidates
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "voteForVanishingPointCandidates"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "combineGaborEnergies"
.LC2:
.string "divideGaborEnergiesTensor"
.section .rodata.str1.8
.align 8
.LC3:
.string "addGaborFilterMagnitudeResponse"
.section .rodata.str1.1
.LC4:
.string "resetGaborEnergiesTensor"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2062:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq voteForVanishingPointCandidates(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq combineGaborEnergies(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq divideGaborEnergiesTensor(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq addGaborFilterMagnitudeResponse(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq resetGaborEnergiesTensor(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vanishing_point_detector.hip"
.globl __device_stub__resetGaborEnergiesTensor # -- Begin function __device_stub__resetGaborEnergiesTensor
.p2align 4, 0x90
.type __device_stub__resetGaborEnergiesTensor,@function
__device_stub__resetGaborEnergiesTensor: # @__device_stub__resetGaborEnergiesTensor
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $resetGaborEnergiesTensor, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__resetGaborEnergiesTensor, .Lfunc_end0-__device_stub__resetGaborEnergiesTensor
.cfi_endproc
# -- End function
.globl __device_stub__addGaborFilterMagnitudeResponse # -- Begin function __device_stub__addGaborFilterMagnitudeResponse
.p2align 4, 0x90
.type __device_stub__addGaborFilterMagnitudeResponse,@function
__device_stub__addGaborFilterMagnitudeResponse: # @__device_stub__addGaborFilterMagnitudeResponse
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 80(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $addGaborFilterMagnitudeResponse, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size __device_stub__addGaborFilterMagnitudeResponse, .Lfunc_end1-__device_stub__addGaborFilterMagnitudeResponse
.cfi_endproc
# -- End function
.globl __device_stub__divideGaborEnergiesTensor # -- Begin function __device_stub__divideGaborEnergiesTensor
.p2align 4, 0x90
.type __device_stub__divideGaborEnergiesTensor,@function
__device_stub__divideGaborEnergiesTensor: # @__device_stub__divideGaborEnergiesTensor
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $divideGaborEnergiesTensor, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size __device_stub__divideGaborEnergiesTensor, .Lfunc_end2-__device_stub__divideGaborEnergiesTensor
.cfi_endproc
# -- End function
.globl __device_stub__combineGaborEnergies # -- Begin function __device_stub__combineGaborEnergies
.p2align 4, 0x90
.type __device_stub__combineGaborEnergies,@function
__device_stub__combineGaborEnergies: # @__device_stub__combineGaborEnergies
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $combineGaborEnergies, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size __device_stub__combineGaborEnergies, .Lfunc_end3-__device_stub__combineGaborEnergies
.cfi_endproc
# -- End function
.globl __device_stub__voteForVanishingPointCandidates # -- Begin function __device_stub__voteForVanishingPointCandidates
.p2align 4, 0x90
.type __device_stub__voteForVanishingPointCandidates,@function
__device_stub__voteForVanishingPointCandidates: # @__device_stub__voteForVanishingPointCandidates
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $voteForVanishingPointCandidates, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end4:
.size __device_stub__voteForVanishingPointCandidates, .Lfunc_end4-__device_stub__voteForVanishingPointCandidates
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $resetGaborEnergiesTensor, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $addGaborFilterMagnitudeResponse, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $divideGaborEnergiesTensor, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $combineGaborEnergies, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $voteForVanishingPointCandidates, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type resetGaborEnergiesTensor,@object # @resetGaborEnergiesTensor
.section .rodata,"a",@progbits
.globl resetGaborEnergiesTensor
.p2align 3, 0x0
resetGaborEnergiesTensor:
.quad __device_stub__resetGaborEnergiesTensor
.size resetGaborEnergiesTensor, 8
.type addGaborFilterMagnitudeResponse,@object # @addGaborFilterMagnitudeResponse
.globl addGaborFilterMagnitudeResponse
.p2align 3, 0x0
addGaborFilterMagnitudeResponse:
.quad __device_stub__addGaborFilterMagnitudeResponse
.size addGaborFilterMagnitudeResponse, 8
.type divideGaborEnergiesTensor,@object # @divideGaborEnergiesTensor
.globl divideGaborEnergiesTensor
.p2align 3, 0x0
divideGaborEnergiesTensor:
.quad __device_stub__divideGaborEnergiesTensor
.size divideGaborEnergiesTensor, 8
.type combineGaborEnergies,@object # @combineGaborEnergies
.globl combineGaborEnergies
.p2align 3, 0x0
combineGaborEnergies:
.quad __device_stub__combineGaborEnergies
.size combineGaborEnergies, 8
.type voteForVanishingPointCandidates,@object # @voteForVanishingPointCandidates
.globl voteForVanishingPointCandidates
.p2align 3, 0x0
voteForVanishingPointCandidates:
.quad __device_stub__voteForVanishingPointCandidates
.size voteForVanishingPointCandidates, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "resetGaborEnergiesTensor"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "addGaborFilterMagnitudeResponse"
.size .L__unnamed_2, 32
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "divideGaborEnergiesTensor"
.size .L__unnamed_3, 26
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "combineGaborEnergies"
.size .L__unnamed_4, 21
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "voteForVanishingPointCandidates"
.size .L__unnamed_5, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__resetGaborEnergiesTensor
.addrsig_sym __device_stub__addGaborFilterMagnitudeResponse
.addrsig_sym __device_stub__divideGaborEnergiesTensor
.addrsig_sym __device_stub__combineGaborEnergies
.addrsig_sym __device_stub__voteForVanishingPointCandidates
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym resetGaborEnergiesTensor
.addrsig_sym addGaborFilterMagnitudeResponse
.addrsig_sym divideGaborEnergiesTensor
.addrsig_sym combineGaborEnergies
.addrsig_sym voteForVanishingPointCandidates
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#define N 1024
__global__ void arraySum (float *d_a, float *d_b, float *d_c){
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < N){
d_c[tid] = d_a[tid] + d_b[tid];
}
}
int main(){
float *h_a, *h_b, *h_c;
float *d_a, *d_b, *d_c;
int memSize = sizeof(float) * N;
//Reserve host memory
h_a = (float*) malloc(memSize);
h_b = (float*) malloc(memSize);
h_c = (float*) malloc(memSize);
//Reserves device memory
cudaError_t error;
error = cudaMalloc((void**)&d_a, memSize);
if (error != cudaSuccess) {
fprintf(stderr, "Error al reservar memoria en la GPU\n");
return -1;
}
error = cudaMalloc((void**)&d_b, memSize);
if (error != cudaSuccess) {
fprintf(stderr, "Error al reservar memoria en la GPU\n");
return -1;
}
error = cudaMalloc((void**)&d_c, memSize);
if (error != cudaSuccess) {
fprintf(stderr, "Error al reservar memoria en la GPU\n");
return -1;
}
//Fills the arrays
for (int i = 0; i < N; ++i) {
h_a[i] = h_b[i] = 1.0f;
}
//Copies host memory to device
error = cudaMemcpy(d_a, h_a, memSize, cudaMemcpyHostToDevice);
if (error != cudaSuccess) {
fprintf(stderr, "Error al transferir información\n");
return -1;
}
error = cudaMemcpy(d_b, h_b, memSize, cudaMemcpyHostToDevice);
if (error != cudaSuccess) {
fprintf(stderr, "Error al transferir información\n");
return -1;
}
//Grid Definition
dim3 block (N/256);
dim3 thread (256);
arraySum<<< block, thread >>>(d_a, d_b, d_c);
error = cudaMemcpy(h_c, d_c, memSize, cudaMemcpyDeviceToHost);
if (error != cudaSuccess) {
fprintf(stderr, "Error al transferir información\n");
return -1;
}
for (int i = 0; i < N; ++i) {
printf("%f, ", h_c[i]);
}
printf("\n");
return 0;
} | code for sm_80
Function : _Z8arraySumPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0x3ff, PT ; /* 0x000003ff0600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#define N 1024
__global__ void arraySum (float *d_a, float *d_b, float *d_c){
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < N){
d_c[tid] = d_a[tid] + d_b[tid];
}
}
int main(){
float *h_a, *h_b, *h_c;
float *d_a, *d_b, *d_c;
int memSize = sizeof(float) * N;
//Reserve host memory
h_a = (float*) malloc(memSize);
h_b = (float*) malloc(memSize);
h_c = (float*) malloc(memSize);
//Reserves device memory
cudaError_t error;
error = cudaMalloc((void**)&d_a, memSize);
if (error != cudaSuccess) {
fprintf(stderr, "Error al reservar memoria en la GPU\n");
return -1;
}
error = cudaMalloc((void**)&d_b, memSize);
if (error != cudaSuccess) {
fprintf(stderr, "Error al reservar memoria en la GPU\n");
return -1;
}
error = cudaMalloc((void**)&d_c, memSize);
if (error != cudaSuccess) {
fprintf(stderr, "Error al reservar memoria en la GPU\n");
return -1;
}
//Fills the arrays
for (int i = 0; i < N; ++i) {
h_a[i] = h_b[i] = 1.0f;
}
//Copies host memory to device
error = cudaMemcpy(d_a, h_a, memSize, cudaMemcpyHostToDevice);
if (error != cudaSuccess) {
fprintf(stderr, "Error al transferir información\n");
return -1;
}
error = cudaMemcpy(d_b, h_b, memSize, cudaMemcpyHostToDevice);
if (error != cudaSuccess) {
fprintf(stderr, "Error al transferir información\n");
return -1;
}
//Grid Definition
dim3 block (N/256);
dim3 thread (256);
arraySum<<< block, thread >>>(d_a, d_b, d_c);
error = cudaMemcpy(h_c, d_c, memSize, cudaMemcpyDeviceToHost);
if (error != cudaSuccess) {
fprintf(stderr, "Error al transferir información\n");
return -1;
}
for (int i = 0; i < N; ++i) {
printf("%f, ", h_c[i]);
}
printf("\n");
return 0;
} | .file "tmpxft_00057502_00000000-6_sumaVector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8arraySumPfS_S_PfS_S_
.type _Z31__device_stub__Z8arraySumPfS_S_PfS_S_, @function
_Z31__device_stub__Z8arraySumPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8arraySumPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z8arraySumPfS_S_PfS_S_, .-_Z31__device_stub__Z8arraySumPfS_S_PfS_S_
.globl _Z8arraySumPfS_S_
.type _Z8arraySumPfS_S_, @function
_Z8arraySumPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8arraySumPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8arraySumPfS_S_, .-_Z8arraySumPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Error al reservar memoria en la GPU\n"
.align 8
.LC2:
.string "Error al transferir informaci\303\263n\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "%f, "
.LC4:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4096, %edi
call malloc@PLT
movq %rax, %rbx
movl $4096, %edi
call malloc@PLT
movq %rax, %rbp
movl $4096, %edi
call malloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L26
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L27
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L28
movl $0, %eax
movss .LC1(%rip), %xmm0
.L15:
movss %xmm0, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq $4096, %rax
jne .L15
movl $1, %ecx
movl $4096, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L29
movl $1, %ecx
movl $4096, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L30
movl $4, 32(%rsp)
movl $1, 36(%rsp)
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L18:
movl $2, %ecx
movl $4096, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L32
movq %r12, %rbx
leaq 4096(%r12), %rbp
leaq .LC3(%rip), %r12
.L20:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L20
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L11:
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L33
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %eax
jmp .L11
.L27:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %eax
jmp .L11
.L28:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %eax
jmp .L11
.L29:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %eax
jmp .L11
.L30:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %eax
jmp .L11
.L31:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z31__device_stub__Z8arraySumPfS_S_PfS_S_
jmp .L18
.L32:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %eax
jmp .L11
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z8arraySumPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z8arraySumPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#define N 1024
__global__ void arraySum (float *d_a, float *d_b, float *d_c){
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < N){
d_c[tid] = d_a[tid] + d_b[tid];
}
}
int main(){
float *h_a, *h_b, *h_c;
float *d_a, *d_b, *d_c;
int memSize = sizeof(float) * N;
//Reserve host memory
h_a = (float*) malloc(memSize);
h_b = (float*) malloc(memSize);
h_c = (float*) malloc(memSize);
//Reserves device memory
cudaError_t error;
error = cudaMalloc((void**)&d_a, memSize);
if (error != cudaSuccess) {
fprintf(stderr, "Error al reservar memoria en la GPU\n");
return -1;
}
error = cudaMalloc((void**)&d_b, memSize);
if (error != cudaSuccess) {
fprintf(stderr, "Error al reservar memoria en la GPU\n");
return -1;
}
error = cudaMalloc((void**)&d_c, memSize);
if (error != cudaSuccess) {
fprintf(stderr, "Error al reservar memoria en la GPU\n");
return -1;
}
//Fills the arrays
for (int i = 0; i < N; ++i) {
h_a[i] = h_b[i] = 1.0f;
}
//Copies host memory to device
error = cudaMemcpy(d_a, h_a, memSize, cudaMemcpyHostToDevice);
if (error != cudaSuccess) {
fprintf(stderr, "Error al transferir información\n");
return -1;
}
error = cudaMemcpy(d_b, h_b, memSize, cudaMemcpyHostToDevice);
if (error != cudaSuccess) {
fprintf(stderr, "Error al transferir información\n");
return -1;
}
//Grid Definition
dim3 block (N/256);
dim3 thread (256);
arraySum<<< block, thread >>>(d_a, d_b, d_c);
error = cudaMemcpy(h_c, d_c, memSize, cudaMemcpyDeviceToHost);
if (error != cudaSuccess) {
fprintf(stderr, "Error al transferir información\n");
return -1;
}
for (int i = 0; i < N; ++i) {
printf("%f, ", h_c[i]);
}
printf("\n");
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define N 1024
__global__ void arraySum (float *d_a, float *d_b, float *d_c){
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < N){
d_c[tid] = d_a[tid] + d_b[tid];
}
}
int main(){
float *h_a, *h_b, *h_c;
float *d_a, *d_b, *d_c;
int memSize = sizeof(float) * N;
//Reserve host memory
h_a = (float*) malloc(memSize);
h_b = (float*) malloc(memSize);
h_c = (float*) malloc(memSize);
//Reserves device memory
hipError_t error;
error = hipMalloc((void**)&d_a, memSize);
if (error != hipSuccess) {
fprintf(stderr, "Error al reservar memoria en la GPU\n");
return -1;
}
error = hipMalloc((void**)&d_b, memSize);
if (error != hipSuccess) {
fprintf(stderr, "Error al reservar memoria en la GPU\n");
return -1;
}
error = hipMalloc((void**)&d_c, memSize);
if (error != hipSuccess) {
fprintf(stderr, "Error al reservar memoria en la GPU\n");
return -1;
}
//Fills the arrays
for (int i = 0; i < N; ++i) {
h_a[i] = h_b[i] = 1.0f;
}
//Copies host memory to device
error = hipMemcpy(d_a, h_a, memSize, hipMemcpyHostToDevice);
if (error != hipSuccess) {
fprintf(stderr, "Error al transferir información\n");
return -1;
}
error = hipMemcpy(d_b, h_b, memSize, hipMemcpyHostToDevice);
if (error != hipSuccess) {
fprintf(stderr, "Error al transferir información\n");
return -1;
}
//Grid Definition
dim3 block (N/256);
dim3 thread (256);
arraySum<<< block, thread >>>(d_a, d_b, d_c);
error = hipMemcpy(h_c, d_c, memSize, hipMemcpyDeviceToHost);
if (error != hipSuccess) {
fprintf(stderr, "Error al transferir información\n");
return -1;
}
for (int i = 0; i < N; ++i) {
printf("%f, ", h_c[i]);
}
printf("\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define N 1024
__global__ void arraySum (float *d_a, float *d_b, float *d_c){
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < N){
d_c[tid] = d_a[tid] + d_b[tid];
}
}
int main(){
float *h_a, *h_b, *h_c;
float *d_a, *d_b, *d_c;
int memSize = sizeof(float) * N;
//Reserve host memory
h_a = (float*) malloc(memSize);
h_b = (float*) malloc(memSize);
h_c = (float*) malloc(memSize);
//Reserves device memory
hipError_t error;
error = hipMalloc((void**)&d_a, memSize);
if (error != hipSuccess) {
fprintf(stderr, "Error al reservar memoria en la GPU\n");
return -1;
}
error = hipMalloc((void**)&d_b, memSize);
if (error != hipSuccess) {
fprintf(stderr, "Error al reservar memoria en la GPU\n");
return -1;
}
error = hipMalloc((void**)&d_c, memSize);
if (error != hipSuccess) {
fprintf(stderr, "Error al reservar memoria en la GPU\n");
return -1;
}
//Fills the arrays
for (int i = 0; i < N; ++i) {
h_a[i] = h_b[i] = 1.0f;
}
//Copies host memory to device
error = hipMemcpy(d_a, h_a, memSize, hipMemcpyHostToDevice);
if (error != hipSuccess) {
fprintf(stderr, "Error al transferir información\n");
return -1;
}
error = hipMemcpy(d_b, h_b, memSize, hipMemcpyHostToDevice);
if (error != hipSuccess) {
fprintf(stderr, "Error al transferir información\n");
return -1;
}
//Grid Definition
dim3 block (N/256);
dim3 thread (256);
arraySum<<< block, thread >>>(d_a, d_b, d_c);
error = hipMemcpy(h_c, d_c, memSize, hipMemcpyDeviceToHost);
if (error != hipSuccess) {
fprintf(stderr, "Error al transferir información\n");
return -1;
}
for (int i = 0; i < N; ++i) {
printf("%f, ", h_c[i]);
}
printf("\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8arraySumPfS_S_
.globl _Z8arraySumPfS_S_
.p2align 8
.type _Z8arraySumPfS_S_,@function
_Z8arraySumPfS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x400, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8arraySumPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8arraySumPfS_S_, .Lfunc_end0-_Z8arraySumPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8arraySumPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8arraySumPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define N 1024
__global__ void arraySum (float *d_a, float *d_b, float *d_c){
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < N){
d_c[tid] = d_a[tid] + d_b[tid];
}
}
int main(){
float *h_a, *h_b, *h_c;
float *d_a, *d_b, *d_c;
int memSize = sizeof(float) * N;
//Reserve host memory
h_a = (float*) malloc(memSize);
h_b = (float*) malloc(memSize);
h_c = (float*) malloc(memSize);
//Reserves device memory
hipError_t error;
error = hipMalloc((void**)&d_a, memSize);
if (error != hipSuccess) {
fprintf(stderr, "Error al reservar memoria en la GPU\n");
return -1;
}
error = hipMalloc((void**)&d_b, memSize);
if (error != hipSuccess) {
fprintf(stderr, "Error al reservar memoria en la GPU\n");
return -1;
}
error = hipMalloc((void**)&d_c, memSize);
if (error != hipSuccess) {
fprintf(stderr, "Error al reservar memoria en la GPU\n");
return -1;
}
//Fills the arrays
for (int i = 0; i < N; ++i) {
h_a[i] = h_b[i] = 1.0f;
}
//Copies host memory to device
error = hipMemcpy(d_a, h_a, memSize, hipMemcpyHostToDevice);
if (error != hipSuccess) {
fprintf(stderr, "Error al transferir información\n");
return -1;
}
error = hipMemcpy(d_b, h_b, memSize, hipMemcpyHostToDevice);
if (error != hipSuccess) {
fprintf(stderr, "Error al transferir información\n");
return -1;
}
//Grid Definition
dim3 block (N/256);
dim3 thread (256);
arraySum<<< block, thread >>>(d_a, d_b, d_c);
error = hipMemcpy(h_c, d_c, memSize, hipMemcpyDeviceToHost);
if (error != hipSuccess) {
fprintf(stderr, "Error al transferir información\n");
return -1;
}
for (int i = 0; i < N; ++i) {
printf("%f, ", h_c[i]);
}
printf("\n");
return 0;
} | .text
.file "sumaVector.hip"
.globl _Z23__device_stub__arraySumPfS_S_ # -- Begin function _Z23__device_stub__arraySumPfS_S_
.p2align 4, 0x90
.type _Z23__device_stub__arraySumPfS_S_,@function
_Z23__device_stub__arraySumPfS_S_: # @_Z23__device_stub__arraySumPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8arraySumPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__arraySumPfS_S_, .Lfunc_end0-_Z23__device_stub__arraySumPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r15
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3:
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.4:
movq %rsp, %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.5: # %.preheader44.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_6: # %.preheader44
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%r14,%rax,4) # imm = 0x3F800000
movl $1065353216, (%r15,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB1_6
# %bb.7:
movq 16(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_8
# %bb.9:
movq 8(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_8
# %bb.10:
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 252(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_12
# %bb.11:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8arraySumPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_12:
movq (%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_8
# %bb.13: # %.preheader.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_14: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r14
cmpq $1024, %r14 # imm = 0x400
jne .LBB1_14
# %bb.15:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
jmp .LBB1_16
.LBB1_1:
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $36, %esi
jmp .LBB1_2
.LBB1_8:
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $33, %esi
.LBB1_2:
movl $1, %edx
callq fwrite@PLT
movl $-1, %eax
.LBB1_16:
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8arraySumPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8arraySumPfS_S_,@object # @_Z8arraySumPfS_S_
.section .rodata,"a",@progbits
.globl _Z8arraySumPfS_S_
.p2align 3, 0x0
_Z8arraySumPfS_S_:
.quad _Z23__device_stub__arraySumPfS_S_
.size _Z8arraySumPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error al reservar memoria en la GPU\n"
.size .L.str, 37
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error al transferir informaci\303\263n\n"
.size .L.str.1, 34
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%f, "
.size .L.str.2, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8arraySumPfS_S_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__arraySumPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8arraySumPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8arraySumPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0x3ff, PT ; /* 0x000003ff0600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8arraySumPfS_S_
.globl _Z8arraySumPfS_S_
.p2align 8
.type _Z8arraySumPfS_S_,@function
_Z8arraySumPfS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x400, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8arraySumPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8arraySumPfS_S_, .Lfunc_end0-_Z8arraySumPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8arraySumPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8arraySumPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00057502_00000000-6_sumaVector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8arraySumPfS_S_PfS_S_
.type _Z31__device_stub__Z8arraySumPfS_S_PfS_S_, @function
_Z31__device_stub__Z8arraySumPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8arraySumPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z8arraySumPfS_S_PfS_S_, .-_Z31__device_stub__Z8arraySumPfS_S_PfS_S_
.globl _Z8arraySumPfS_S_
.type _Z8arraySumPfS_S_, @function
_Z8arraySumPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8arraySumPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8arraySumPfS_S_, .-_Z8arraySumPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Error al reservar memoria en la GPU\n"
.align 8
.LC2:
.string "Error al transferir informaci\303\263n\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "%f, "
.LC4:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4096, %edi
call malloc@PLT
movq %rax, %rbx
movl $4096, %edi
call malloc@PLT
movq %rax, %rbp
movl $4096, %edi
call malloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L26
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L27
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L28
movl $0, %eax
movss .LC1(%rip), %xmm0
.L15:
movss %xmm0, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq $4096, %rax
jne .L15
movl $1, %ecx
movl $4096, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L29
movl $1, %ecx
movl $4096, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L30
movl $4, 32(%rsp)
movl $1, 36(%rsp)
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L18:
movl $2, %ecx
movl $4096, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L32
movq %r12, %rbx
leaq 4096(%r12), %rbp
leaq .LC3(%rip), %r12
.L20:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L20
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L11:
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L33
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %eax
jmp .L11
.L27:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %eax
jmp .L11
.L28:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %eax
jmp .L11
.L29:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %eax
jmp .L11
.L30:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %eax
jmp .L11
.L31:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z31__device_stub__Z8arraySumPfS_S_PfS_S_
jmp .L18
.L32:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %eax
jmp .L11
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z8arraySumPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z8arraySumPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sumaVector.hip"
.globl _Z23__device_stub__arraySumPfS_S_ # -- Begin function _Z23__device_stub__arraySumPfS_S_
.p2align 4, 0x90
.type _Z23__device_stub__arraySumPfS_S_,@function
_Z23__device_stub__arraySumPfS_S_: # @_Z23__device_stub__arraySumPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8arraySumPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__arraySumPfS_S_, .Lfunc_end0-_Z23__device_stub__arraySumPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r15
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3:
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.4:
movq %rsp, %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.5: # %.preheader44.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_6: # %.preheader44
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%r14,%rax,4) # imm = 0x3F800000
movl $1065353216, (%r15,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB1_6
# %bb.7:
movq 16(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_8
# %bb.9:
movq 8(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_8
# %bb.10:
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 252(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_12
# %bb.11:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8arraySumPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_12:
movq (%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_8
# %bb.13: # %.preheader.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_14: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r14
cmpq $1024, %r14 # imm = 0x400
jne .LBB1_14
# %bb.15:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
jmp .LBB1_16
.LBB1_1:
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $36, %esi
jmp .LBB1_2
.LBB1_8:
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $33, %esi
.LBB1_2:
movl $1, %edx
callq fwrite@PLT
movl $-1, %eax
.LBB1_16:
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8arraySumPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8arraySumPfS_S_,@object # @_Z8arraySumPfS_S_
.section .rodata,"a",@progbits
.globl _Z8arraySumPfS_S_
.p2align 3, 0x0
_Z8arraySumPfS_S_:
.quad _Z23__device_stub__arraySumPfS_S_
.size _Z8arraySumPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error al reservar memoria en la GPU\n"
.size .L.str, 37
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error al transferir informaci\303\263n\n"
.size .L.str.1, 34
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%f, "
.size .L.str.2, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8arraySumPfS_S_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__arraySumPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8arraySumPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //tÌÆÅÌÌ^®vZÊðâÔµCÅIIÈÊðvZ
//HACK::¡ÍPÉü`âÔ
//HACK::§û̵©Å«È¢ÌÉÓ
#ifndef _GPU_ICE_INTERPOLATION_H_
#define _GPU_ICE_INTERPOLATION_H_
#include <iostream>
#include <cuda_runtime.h>
using namespace std;
void LaunchInterPolationGPU(int prtNum, float* sldPrtPos, float* sldPrtVel, float* sphPrtPos, float* sphPrtVel);
__global__ void LinerInterPolation(float* sldPrtPos, float* sldPrtVel, float* sphPrtPos, float* sphPrtVel, int side);
void LaunchInterPolationGPU(int prtNum, float* sldPrtPos, float* sldPrtVel, float* sphPrtPos, float* sphPrtVel)
{ //cout << __FUNCTION__ << endl;
int side = pow(prtNum, 1.0/3.0) + 0.5; //§ûÌÌPÓ̸_
dim3 grid(side, side);
dim3 block(side, 1, 1);
//ü`âÔ
LinerInterPolation<<<grid ,block>>>(sldPrtPos, sldPrtVel, sphPrtPos, sphPrtVel, side);
cudaThreadSynchronize();
}
__global__
void LinerInterPolation(float* sldPrtPos, float* sldPrtVel, float* sphPrtPos, float* sphPrtVel, int side)
{
//vZ·é±qÌ»è
int pIndx = blockIdx.x * side * side + blockIdx.y * side + threadIdx.x;
int sphIndx = pIndx * 4;
int sldIndx = pIndx * 3;
//ü`âÔ
sphPrtPos[sphIndx+0] = sldPrtPos[sldIndx+0];
sphPrtPos[sphIndx+1] = sldPrtPos[sldIndx+1];
sphPrtPos[sphIndx+2] = sldPrtPos[sldIndx+2];
sphPrtVel[sphIndx+0] = sldPrtVel[sldIndx+0];
sphPrtVel[sphIndx+1] = sldPrtVel[sldIndx+1];
sphPrtVel[sphIndx+2] = sldPrtVel[sldIndx+2];
}
#endif | code for sm_80
Function : _Z18LinerInterPolationPfS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0x180], R3 ; /* 0x0000600000007a24 */
/* 0x001fc800078e0203 */
/*0070*/ IMAD R0, R0, c[0x0][0x180], R5 ; /* 0x0000600000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ LEA R6, R0, R0, 0x1 ; /* 0x0000000000067211 */
/* 0x000fca00078e08ff */
/*0090*/ IMAD.WIDE R2, R6, R9, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fca00078e0209 */
/*00a0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ SHF.L.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007819 */
/* 0x000fca00000006ff */
/*00c0*/ IMAD.WIDE R4, R0, R9, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fca00078e0209 */
/*00d0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0041e8000c101904 */
/*00e0*/ LDG.E R13, [R2.64+0x4] ; /* 0x00000404020d7981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc600078e0209 */
/*0100*/ STG.E [R4.64+0x4], R13 ; /* 0x0000040d04007986 */
/* 0x004fe8000c101904 */
/*0110*/ LDG.E R15, [R2.64+0x8] ; /* 0x00000804020f7981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.WIDE R8, R0, R9, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fc600078e0209 */
/*0130*/ STG.E [R4.64+0x8], R15 ; /* 0x0000080f04007986 */
/* 0x004fe8000c101904 */
/*0140*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */
/* 0x000ea8000c1e1900 */
/*0150*/ STG.E [R8.64], R17 ; /* 0x0000001108007986 */
/* 0x004fe8000c101904 */
/*0160*/ LDG.E R19, [R6.64+0x4] ; /* 0x0000040406137981 */
/* 0x000ea8000c1e1900 */
/*0170*/ STG.E [R8.64+0x4], R19 ; /* 0x0000041308007986 */
/* 0x004fe8000c101904 */
/*0180*/ LDG.E R11, [R6.64+0x8] ; /* 0x00000804060b7981 */
/* 0x001ea8000c1e1900 */
/*0190*/ STG.E [R8.64+0x8], R11 ; /* 0x0000080b08007986 */
/* 0x004fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //tÌÆÅÌÌ^®vZÊðâÔµCÅIIÈÊðvZ
//HACK::¡ÍPÉü`âÔ
//HACK::§û̵©Å«È¢ÌÉÓ
#ifndef _GPU_ICE_INTERPOLATION_H_
#define _GPU_ICE_INTERPOLATION_H_
#include <iostream>
#include <cuda_runtime.h>
using namespace std;
void LaunchInterPolationGPU(int prtNum, float* sldPrtPos, float* sldPrtVel, float* sphPrtPos, float* sphPrtVel);
__global__ void LinerInterPolation(float* sldPrtPos, float* sldPrtVel, float* sphPrtPos, float* sphPrtVel, int side);
void LaunchInterPolationGPU(int prtNum, float* sldPrtPos, float* sldPrtVel, float* sphPrtPos, float* sphPrtVel)
{ //cout << __FUNCTION__ << endl;
int side = pow(prtNum, 1.0/3.0) + 0.5; //§ûÌÌPÓ̸_
dim3 grid(side, side);
dim3 block(side, 1, 1);
//ü`âÔ
LinerInterPolation<<<grid ,block>>>(sldPrtPos, sldPrtVel, sphPrtPos, sphPrtVel, side);
cudaThreadSynchronize();
}
__global__
void LinerInterPolation(float* sldPrtPos, float* sldPrtVel, float* sphPrtPos, float* sphPrtVel, int side)
{
//vZ·é±qÌ»è
int pIndx = blockIdx.x * side * side + blockIdx.y * side + threadIdx.x;
int sphIndx = pIndx * 4;
int sldIndx = pIndx * 3;
//ü`âÔ
sphPrtPos[sphIndx+0] = sldPrtPos[sldIndx+0];
sphPrtPos[sphIndx+1] = sldPrtPos[sldIndx+1];
sphPrtPos[sphIndx+2] = sldPrtPos[sldIndx+2];
sphPrtVel[sphIndx+0] = sldPrtVel[sldIndx+0];
sphPrtVel[sphIndx+1] = sldPrtVel[sldIndx+1];
sphPrtVel[sphIndx+2] = sldPrtVel[sldIndx+2];
}
#endif | .file "tmpxft_001170a5_00000000-6_IceInterPolation.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z18LinerInterPolationPfS_S_S_iPfS_S_S_i
.type _Z45__device_stub__Z18LinerInterPolationPfS_S_S_iPfS_S_S_i, @function
_Z45__device_stub__Z18LinerInterPolationPfS_S_S_iPfS_S_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18LinerInterPolationPfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z45__device_stub__Z18LinerInterPolationPfS_S_S_iPfS_S_S_i, .-_Z45__device_stub__Z18LinerInterPolationPfS_S_S_iPfS_S_S_i
.globl _Z18LinerInterPolationPfS_S_S_i
.type _Z18LinerInterPolationPfS_S_S_i, @function
_Z18LinerInterPolationPfS_S_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z18LinerInterPolationPfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z18LinerInterPolationPfS_S_S_i, .-_Z18LinerInterPolationPfS_S_S_i
.globl _Z22LaunchInterPolationGPUiPfS_S_S_
.type _Z22LaunchInterPolationGPUiPfS_S_S_, @function
_Z22LaunchInterPolationGPUiPfS_S_S_:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbp
movq %rdx, %r12
movq %rcx, %r13
movq %r8, %r14
pxor %xmm0, %xmm0
cvtsi2sdl %edi, %xmm0
movsd .LC0(%rip), %xmm1
call pow@PLT
addsd .LC1(%rip), %xmm0
cvttsd2sil %xmm0, %ebx
movl %ebx, 8(%rsp)
movl %ebx, 12(%rsp)
movl %ebx, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaThreadSynchronize@PLT
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %ebx, %r8d
movq %r14, %rcx
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z45__device_stub__Z18LinerInterPolationPfS_S_S_iPfS_S_S_i
jmp .L12
.cfi_endproc
.LFE3669:
.size _Z22LaunchInterPolationGPUiPfS_S_S_, .-_Z22LaunchInterPolationGPUiPfS_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z18LinerInterPolationPfS_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z18LinerInterPolationPfS_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 1431655765
.long 1070945621
.align 8
.LC1:
.long 0
.long 1071644672
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //tÌÆÅÌÌ^®vZÊðâÔµCÅIIÈÊðvZ
//HACK::¡ÍPÉü`âÔ
//HACK::§û̵©Å«È¢ÌÉÓ
#ifndef _GPU_ICE_INTERPOLATION_H_
#define _GPU_ICE_INTERPOLATION_H_
#include <iostream>
#include <cuda_runtime.h>
using namespace std;
void LaunchInterPolationGPU(int prtNum, float* sldPrtPos, float* sldPrtVel, float* sphPrtPos, float* sphPrtVel);
__global__ void LinerInterPolation(float* sldPrtPos, float* sldPrtVel, float* sphPrtPos, float* sphPrtVel, int side);
void LaunchInterPolationGPU(int prtNum, float* sldPrtPos, float* sldPrtVel, float* sphPrtPos, float* sphPrtVel)
{ //cout << __FUNCTION__ << endl;
int side = pow(prtNum, 1.0/3.0) + 0.5; //§ûÌÌPÓ̸_
dim3 grid(side, side);
dim3 block(side, 1, 1);
//ü`âÔ
LinerInterPolation<<<grid ,block>>>(sldPrtPos, sldPrtVel, sphPrtPos, sphPrtVel, side);
cudaThreadSynchronize();
}
__global__
void LinerInterPolation(float* sldPrtPos, float* sldPrtVel, float* sphPrtPos, float* sphPrtVel, int side)
{
//vZ·é±qÌ»è
int pIndx = blockIdx.x * side * side + blockIdx.y * side + threadIdx.x;
int sphIndx = pIndx * 4;
int sldIndx = pIndx * 3;
//ü`âÔ
sphPrtPos[sphIndx+0] = sldPrtPos[sldIndx+0];
sphPrtPos[sphIndx+1] = sldPrtPos[sldIndx+1];
sphPrtPos[sphIndx+2] = sldPrtPos[sldIndx+2];
sphPrtVel[sphIndx+0] = sldPrtVel[sldIndx+0];
sphPrtVel[sphIndx+1] = sldPrtVel[sldIndx+1];
sphPrtVel[sphIndx+2] = sldPrtVel[sldIndx+2];
}
#endif | //tÌÆÅÌÌ^®vZÊðâÔµCÅIIÈÊðvZ
//HACK::¡ÍPÉü`âÔ
//HACK::§û̵©Å«È¢ÌÉÓ
#ifndef _GPU_ICE_INTERPOLATION_H_
#define _GPU_ICE_INTERPOLATION_H_
#include <iostream>
#include <hip/hip_runtime.h>
using namespace std;
void LaunchInterPolationGPU(int prtNum, float* sldPrtPos, float* sldPrtVel, float* sphPrtPos, float* sphPrtVel);
__global__ void LinerInterPolation(float* sldPrtPos, float* sldPrtVel, float* sphPrtPos, float* sphPrtVel, int side);
void LaunchInterPolationGPU(int prtNum, float* sldPrtPos, float* sldPrtVel, float* sphPrtPos, float* sphPrtVel)
{ //cout << __FUNCTION__ << endl;
int side = pow(prtNum, 1.0/3.0) + 0.5; //§ûÌÌPÓ̸_
dim3 grid(side, side);
dim3 block(side, 1, 1);
//ü`âÔ
LinerInterPolation<<<grid ,block>>>(sldPrtPos, sldPrtVel, sphPrtPos, sphPrtVel, side);
hipDeviceSynchronize();
}
__global__
void LinerInterPolation(float* sldPrtPos, float* sldPrtVel, float* sphPrtPos, float* sphPrtVel, int side)
{
//vZ·é±qÌ»è
int pIndx = blockIdx.x * side * side + blockIdx.y * side + threadIdx.x;
int sphIndx = pIndx * 4;
int sldIndx = pIndx * 3;
//ü`âÔ
sphPrtPos[sphIndx+0] = sldPrtPos[sldIndx+0];
sphPrtPos[sphIndx+1] = sldPrtPos[sldIndx+1];
sphPrtPos[sphIndx+2] = sldPrtPos[sldIndx+2];
sphPrtVel[sphIndx+0] = sldPrtVel[sldIndx+0];
sphPrtVel[sphIndx+1] = sldPrtVel[sldIndx+1];
sphPrtVel[sphIndx+2] = sldPrtVel[sldIndx+2];
}
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //tÌÆÅÌÌ^®vZÊðâÔµCÅIIÈÊðvZ
//HACK::¡ÍPÉü`âÔ
//HACK::§û̵©Å«È¢ÌÉÓ
#ifndef _GPU_ICE_INTERPOLATION_H_
#define _GPU_ICE_INTERPOLATION_H_
#include <iostream>
#include <hip/hip_runtime.h>
using namespace std;
void LaunchInterPolationGPU(int prtNum, float* sldPrtPos, float* sldPrtVel, float* sphPrtPos, float* sphPrtVel);
__global__ void LinerInterPolation(float* sldPrtPos, float* sldPrtVel, float* sphPrtPos, float* sphPrtVel, int side);
void LaunchInterPolationGPU(int prtNum, float* sldPrtPos, float* sldPrtVel, float* sphPrtPos, float* sphPrtVel)
{ //cout << __FUNCTION__ << endl;
int side = pow(prtNum, 1.0/3.0) + 0.5; //§ûÌÌPÓ̸_
dim3 grid(side, side);
dim3 block(side, 1, 1);
//ü`âÔ
LinerInterPolation<<<grid ,block>>>(sldPrtPos, sldPrtVel, sphPrtPos, sphPrtVel, side);
hipDeviceSynchronize();
}
__global__
void LinerInterPolation(float* sldPrtPos, float* sldPrtVel, float* sphPrtPos, float* sphPrtVel, int side)
{
//vZ·é±qÌ»è
int pIndx = blockIdx.x * side * side + blockIdx.y * side + threadIdx.x;
int sphIndx = pIndx * 4;
int sldIndx = pIndx * 3;
//ü`âÔ
sphPrtPos[sphIndx+0] = sldPrtPos[sldIndx+0];
sphPrtPos[sphIndx+1] = sldPrtPos[sldIndx+1];
sphPrtPos[sphIndx+2] = sldPrtPos[sldIndx+2];
sphPrtVel[sphIndx+0] = sldPrtVel[sldIndx+0];
sphPrtVel[sphIndx+1] = sldPrtVel[sldIndx+1];
sphPrtVel[sphIndx+2] = sldPrtVel[sldIndx+2];
}
#endif | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18LinerInterPolationPfS_S_S_i
.globl _Z18LinerInterPolationPfS_S_S_i
.p2align 8
.type _Z18LinerInterPolationPfS_S_S_i,@function
_Z18LinerInterPolationPfS_S_S_i:
s_load_b32 s2, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s14, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s15
v_mad_u64_u32 v[1:2], null, s3, s2, v[0:1]
s_load_b256 s[0:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshl_add_u32 v2, v1, 1, v1
v_lshlrev_b32_e32 v0, 2, v1
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v12, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v3, vcc_lo
global_load_b32 v10, v[4:5], off
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v8, vcc_lo, s0, v12
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v13, vcc_lo
v_add_co_u32 v14, vcc_lo, v2, 8
v_add_co_ci_u32_e32 v15, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[6:7], v10, off
global_load_b32 v1, v[8:9], off
v_or_b32_e32 v6, 1, v0
v_or_b32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v7, vcc_lo
v_add_co_u32 v10, vcc_lo, s0, v14
v_add_co_ci_u32_e32 v11, vcc_lo, s1, v15, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[8:9], v1, off
global_load_b32 v10, v[10:11], off
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v8, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[8:9], v10, off
global_load_b32 v8, v[2:3], off
v_add_co_u32 v2, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v12
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v13, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v8, off
global_load_b32 v8, v[4:5], off
v_add_co_u32 v2, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v7, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v14
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v15, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v8, off
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18LinerInterPolationPfS_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18LinerInterPolationPfS_S_S_i, .Lfunc_end0-_Z18LinerInterPolationPfS_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18LinerInterPolationPfS_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18LinerInterPolationPfS_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //tÌÆÅÌÌ^®vZÊðâÔµCÅIIÈÊðvZ
//HACK::¡ÍPÉü`âÔ
//HACK::§û̵©Å«È¢ÌÉÓ
#ifndef _GPU_ICE_INTERPOLATION_H_
#define _GPU_ICE_INTERPOLATION_H_
#include <iostream>
#include <hip/hip_runtime.h>
using namespace std;
void LaunchInterPolationGPU(int prtNum, float* sldPrtPos, float* sldPrtVel, float* sphPrtPos, float* sphPrtVel);
__global__ void LinerInterPolation(float* sldPrtPos, float* sldPrtVel, float* sphPrtPos, float* sphPrtVel, int side);
void LaunchInterPolationGPU(int prtNum, float* sldPrtPos, float* sldPrtVel, float* sphPrtPos, float* sphPrtVel)
{ //cout << __FUNCTION__ << endl;
int side = pow(prtNum, 1.0/3.0) + 0.5; //§ûÌÌPÓ̸_
dim3 grid(side, side);
dim3 block(side, 1, 1);
//ü`âÔ
LinerInterPolation<<<grid ,block>>>(sldPrtPos, sldPrtVel, sphPrtPos, sphPrtVel, side);
hipDeviceSynchronize();
}
__global__
void LinerInterPolation(float* sldPrtPos, float* sldPrtVel, float* sphPrtPos, float* sphPrtVel, int side)
{
//vZ·é±qÌ»è
int pIndx = blockIdx.x * side * side + blockIdx.y * side + threadIdx.x;
int sphIndx = pIndx * 4;
int sldIndx = pIndx * 3;
//ü`âÔ
sphPrtPos[sphIndx+0] = sldPrtPos[sldIndx+0];
sphPrtPos[sphIndx+1] = sldPrtPos[sldIndx+1];
sphPrtPos[sphIndx+2] = sldPrtPos[sldIndx+2];
sphPrtVel[sphIndx+0] = sldPrtVel[sldIndx+0];
sphPrtVel[sphIndx+1] = sldPrtVel[sldIndx+1];
sphPrtVel[sphIndx+2] = sldPrtVel[sldIndx+2];
}
#endif | .text
.file "IceInterPolation.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z22LaunchInterPolationGPUiPfS_S_S_
.LCPI0_0:
.quad 0x3fd5555555555555 # double 0.33333333333333331
.LCPI0_1:
.quad 0x3fe0000000000000 # double 0.5
.text
.globl _Z22LaunchInterPolationGPUiPfS_S_S_
.p2align 4, 0x90
.type _Z22LaunchInterPolationGPUiPfS_S_S_,@function
_Z22LaunchInterPolationGPUiPfS_S_S_: # @_Z22LaunchInterPolationGPUiPfS_S_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %r8, %rbx
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r12
cvtsi2sd %edi, %xmm0
movsd .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero
callq pow
addsd .LCPI0_1(%rip), %xmm0
cvttsd2si %xmm0, %r13d
movabsq $4294967296, %rdx # imm = 0x100000000
leaq 1(%rdx), %rdi
imulq %r13, %rdi
orq %r13, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq %r12, 88(%rsp)
movq %r15, 80(%rsp)
movq %r14, 72(%rsp)
movq %rbx, 64(%rsp)
movl %r13d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18LinerInterPolationPfS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
callq hipDeviceSynchronize
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z22LaunchInterPolationGPUiPfS_S_S_, .Lfunc_end0-_Z22LaunchInterPolationGPUiPfS_S_S_
.cfi_endproc
# -- End function
.globl _Z33__device_stub__LinerInterPolationPfS_S_S_i # -- Begin function _Z33__device_stub__LinerInterPolationPfS_S_S_i
.p2align 4, 0x90
.type _Z33__device_stub__LinerInterPolationPfS_S_S_i,@function
_Z33__device_stub__LinerInterPolationPfS_S_S_i: # @_Z33__device_stub__LinerInterPolationPfS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18LinerInterPolationPfS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z33__device_stub__LinerInterPolationPfS_S_S_i, .Lfunc_end1-_Z33__device_stub__LinerInterPolationPfS_S_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18LinerInterPolationPfS_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18LinerInterPolationPfS_S_S_i,@object # @_Z18LinerInterPolationPfS_S_S_i
.section .rodata,"a",@progbits
.globl _Z18LinerInterPolationPfS_S_S_i
.p2align 3, 0x0
_Z18LinerInterPolationPfS_S_S_i:
.quad _Z33__device_stub__LinerInterPolationPfS_S_S_i
.size _Z18LinerInterPolationPfS_S_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18LinerInterPolationPfS_S_S_i"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__LinerInterPolationPfS_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18LinerInterPolationPfS_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18LinerInterPolationPfS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0x180], R3 ; /* 0x0000600000007a24 */
/* 0x001fc800078e0203 */
/*0070*/ IMAD R0, R0, c[0x0][0x180], R5 ; /* 0x0000600000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ LEA R6, R0, R0, 0x1 ; /* 0x0000000000067211 */
/* 0x000fca00078e08ff */
/*0090*/ IMAD.WIDE R2, R6, R9, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fca00078e0209 */
/*00a0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ SHF.L.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007819 */
/* 0x000fca00000006ff */
/*00c0*/ IMAD.WIDE R4, R0, R9, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fca00078e0209 */
/*00d0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0041e8000c101904 */
/*00e0*/ LDG.E R13, [R2.64+0x4] ; /* 0x00000404020d7981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc600078e0209 */
/*0100*/ STG.E [R4.64+0x4], R13 ; /* 0x0000040d04007986 */
/* 0x004fe8000c101904 */
/*0110*/ LDG.E R15, [R2.64+0x8] ; /* 0x00000804020f7981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.WIDE R8, R0, R9, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fc600078e0209 */
/*0130*/ STG.E [R4.64+0x8], R15 ; /* 0x0000080f04007986 */
/* 0x004fe8000c101904 */
/*0140*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */
/* 0x000ea8000c1e1900 */
/*0150*/ STG.E [R8.64], R17 ; /* 0x0000001108007986 */
/* 0x004fe8000c101904 */
/*0160*/ LDG.E R19, [R6.64+0x4] ; /* 0x0000040406137981 */
/* 0x000ea8000c1e1900 */
/*0170*/ STG.E [R8.64+0x4], R19 ; /* 0x0000041308007986 */
/* 0x004fe8000c101904 */
/*0180*/ LDG.E R11, [R6.64+0x8] ; /* 0x00000804060b7981 */
/* 0x001ea8000c1e1900 */
/*0190*/ STG.E [R8.64+0x8], R11 ; /* 0x0000080b08007986 */
/* 0x004fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18LinerInterPolationPfS_S_S_i
.globl _Z18LinerInterPolationPfS_S_S_i
.p2align 8
.type _Z18LinerInterPolationPfS_S_S_i,@function
_Z18LinerInterPolationPfS_S_S_i:
s_load_b32 s2, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s14, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s15
v_mad_u64_u32 v[1:2], null, s3, s2, v[0:1]
s_load_b256 s[0:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshl_add_u32 v2, v1, 1, v1
v_lshlrev_b32_e32 v0, 2, v1
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v12, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v3, vcc_lo
global_load_b32 v10, v[4:5], off
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v8, vcc_lo, s0, v12
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v13, vcc_lo
v_add_co_u32 v14, vcc_lo, v2, 8
v_add_co_ci_u32_e32 v15, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[6:7], v10, off
global_load_b32 v1, v[8:9], off
v_or_b32_e32 v6, 1, v0
v_or_b32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v7, vcc_lo
v_add_co_u32 v10, vcc_lo, s0, v14
v_add_co_ci_u32_e32 v11, vcc_lo, s1, v15, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[8:9], v1, off
global_load_b32 v10, v[10:11], off
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v8, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[8:9], v10, off
global_load_b32 v8, v[2:3], off
v_add_co_u32 v2, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v12
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v13, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v8, off
global_load_b32 v8, v[4:5], off
v_add_co_u32 v2, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v7, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v14
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v15, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v8, off
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18LinerInterPolationPfS_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18LinerInterPolationPfS_S_S_i, .Lfunc_end0-_Z18LinerInterPolationPfS_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18LinerInterPolationPfS_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18LinerInterPolationPfS_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001170a5_00000000-6_IceInterPolation.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z18LinerInterPolationPfS_S_S_iPfS_S_S_i
.type _Z45__device_stub__Z18LinerInterPolationPfS_S_S_iPfS_S_S_i, @function
_Z45__device_stub__Z18LinerInterPolationPfS_S_S_iPfS_S_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18LinerInterPolationPfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z45__device_stub__Z18LinerInterPolationPfS_S_S_iPfS_S_S_i, .-_Z45__device_stub__Z18LinerInterPolationPfS_S_S_iPfS_S_S_i
.globl _Z18LinerInterPolationPfS_S_S_i
.type _Z18LinerInterPolationPfS_S_S_i, @function
_Z18LinerInterPolationPfS_S_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z18LinerInterPolationPfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z18LinerInterPolationPfS_S_S_i, .-_Z18LinerInterPolationPfS_S_S_i
.globl _Z22LaunchInterPolationGPUiPfS_S_S_
.type _Z22LaunchInterPolationGPUiPfS_S_S_, @function
_Z22LaunchInterPolationGPUiPfS_S_S_:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbp
movq %rdx, %r12
movq %rcx, %r13
movq %r8, %r14
pxor %xmm0, %xmm0
cvtsi2sdl %edi, %xmm0
movsd .LC0(%rip), %xmm1
call pow@PLT
addsd .LC1(%rip), %xmm0
cvttsd2sil %xmm0, %ebx
movl %ebx, 8(%rsp)
movl %ebx, 12(%rsp)
movl %ebx, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaThreadSynchronize@PLT
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %ebx, %r8d
movq %r14, %rcx
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z45__device_stub__Z18LinerInterPolationPfS_S_S_iPfS_S_S_i
jmp .L12
.cfi_endproc
.LFE3669:
.size _Z22LaunchInterPolationGPUiPfS_S_S_, .-_Z22LaunchInterPolationGPUiPfS_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z18LinerInterPolationPfS_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z18LinerInterPolationPfS_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 1431655765
.long 1070945621
.align 8
.LC1:
.long 0
.long 1071644672
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "IceInterPolation.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z22LaunchInterPolationGPUiPfS_S_S_
.LCPI0_0:
.quad 0x3fd5555555555555 # double 0.33333333333333331
.LCPI0_1:
.quad 0x3fe0000000000000 # double 0.5
.text
.globl _Z22LaunchInterPolationGPUiPfS_S_S_
.p2align 4, 0x90
.type _Z22LaunchInterPolationGPUiPfS_S_S_,@function
_Z22LaunchInterPolationGPUiPfS_S_S_: # @_Z22LaunchInterPolationGPUiPfS_S_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %r8, %rbx
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r12
cvtsi2sd %edi, %xmm0
movsd .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero
callq pow
addsd .LCPI0_1(%rip), %xmm0
cvttsd2si %xmm0, %r13d
movabsq $4294967296, %rdx # imm = 0x100000000
leaq 1(%rdx), %rdi
imulq %r13, %rdi
orq %r13, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq %r12, 88(%rsp)
movq %r15, 80(%rsp)
movq %r14, 72(%rsp)
movq %rbx, 64(%rsp)
movl %r13d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18LinerInterPolationPfS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
callq hipDeviceSynchronize
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z22LaunchInterPolationGPUiPfS_S_S_, .Lfunc_end0-_Z22LaunchInterPolationGPUiPfS_S_S_
.cfi_endproc
# -- End function
.globl _Z33__device_stub__LinerInterPolationPfS_S_S_i # -- Begin function _Z33__device_stub__LinerInterPolationPfS_S_S_i
.p2align 4, 0x90
.type _Z33__device_stub__LinerInterPolationPfS_S_S_i,@function
_Z33__device_stub__LinerInterPolationPfS_S_S_i: # @_Z33__device_stub__LinerInterPolationPfS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18LinerInterPolationPfS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z33__device_stub__LinerInterPolationPfS_S_S_i, .Lfunc_end1-_Z33__device_stub__LinerInterPolationPfS_S_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18LinerInterPolationPfS_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18LinerInterPolationPfS_S_S_i,@object # @_Z18LinerInterPolationPfS_S_S_i
.section .rodata,"a",@progbits
.globl _Z18LinerInterPolationPfS_S_S_i
.p2align 3, 0x0
_Z18LinerInterPolationPfS_S_S_i:
.quad _Z33__device_stub__LinerInterPolationPfS_S_S_i
.size _Z18LinerInterPolationPfS_S_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18LinerInterPolationPfS_S_S_i"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__LinerInterPolationPfS_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18LinerInterPolationPfS_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // RUN: %run_test hipify "%s" "%t" %hipify_args %clang_args
// CHECK: #include <hip/hip_runtime.h>
#include <iostream>
// CHECK: #include <hiprand.h>
#include <curand.h>
// CHECK: #include <hipcub/hipcub.hpp>
#include <cub/cub.cuh>
// using namespace hipcub;
using namespace cub;
// Simple CUDA kernel for computing tiled partial sums
template <int BLOCK_THREADS, int ITEMS_PER_THREAD,
BlockLoadAlgorithm LOAD_ALGO,
BlockScanAlgorithm SCAN_ALGO>
__global__ void ScanTilesKernel(int *d_in, int *d_out) {
// Specialize collective types for problem context
// TODO: typedef cub::BlockLoad<int*, BLOCK_THREADS, ITEMS_PER_THREAD, LOAD_ALGO> BlockLoadT;
typedef BlockLoad<int*, BLOCK_THREADS, ITEMS_PER_THREAD, LOAD_ALGO> BlockLoadT;
typedef BlockScan<int, BLOCK_THREADS, SCAN_ALGO> BlockScanT;
// Allocate on-chip temporary storage
__shared__ union {
typename BlockLoadT::TempStorage load;
typename BlockScanT::TempStorage reduce;
} temp_storage;
// Load data per thread
int thread_data[ITEMS_PER_THREAD];
int offset = blockIdx.x * (BLOCK_THREADS * ITEMS_PER_THREAD);
BlockLoadT(temp_storage.load).Load(d_in + offset, offset);
__syncthreads();
// Compute the block-wide prefix sum
BlockScanT(temp_storage).Sum(thread_data);
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // RUN: %run_test hipify "%s" "%t" %hipify_args %clang_args
// CHECK: #include <hip/hip_runtime.h>
#include <iostream>
// CHECK: #include <hiprand.h>
#include <curand.h>
// CHECK: #include <hipcub/hipcub.hpp>
#include <cub/cub.cuh>
// using namespace hipcub;
using namespace cub;
// Simple CUDA kernel for computing tiled partial sums
template <int BLOCK_THREADS, int ITEMS_PER_THREAD,
BlockLoadAlgorithm LOAD_ALGO,
BlockScanAlgorithm SCAN_ALGO>
__global__ void ScanTilesKernel(int *d_in, int *d_out) {
// Specialize collective types for problem context
// TODO: typedef cub::BlockLoad<int*, BLOCK_THREADS, ITEMS_PER_THREAD, LOAD_ALGO> BlockLoadT;
typedef BlockLoad<int*, BLOCK_THREADS, ITEMS_PER_THREAD, LOAD_ALGO> BlockLoadT;
typedef BlockScan<int, BLOCK_THREADS, SCAN_ALGO> BlockScanT;
// Allocate on-chip temporary storage
__shared__ union {
typename BlockLoadT::TempStorage load;
typename BlockScanT::TempStorage reduce;
} temp_storage;
// Load data per thread
int thread_data[ITEMS_PER_THREAD];
int offset = blockIdx.x * (BLOCK_THREADS * ITEMS_PER_THREAD);
BlockLoadT(temp_storage.load).Load(d_in + offset, offset);
__syncthreads();
// Compute the block-wide prefix sum
BlockScanT(temp_storage).Sum(thread_data);
} | // RUN: %run_test hipify "%s" "%t" %hipify_args %clang_args
// CHECK: #include <hip/hip_runtime.h>
#include <hip/hip_runtime.h>
#include <iostream>
// CHECK: #include <hiprand.h>
#include <hiprand/hiprand.h>
// CHECK: #include <hipcub/hipcub.hpp>
#include <hipcub/hipcub.hpp>
// using namespace hipcub;
using namespace hipcub;
// Simple CUDA kernel for computing tiled partial sums
template <int BLOCK_THREADS, int ITEMS_PER_THREAD,
BlockLoadAlgorithm LOAD_ALGO,
BlockScanAlgorithm SCAN_ALGO>
__global__ void ScanTilesKernel(int *d_in, int *d_out) {
// Specialize collective types for problem context
// TODO: typedef cub::BlockLoad<int*, BLOCK_THREADS, ITEMS_PER_THREAD, LOAD_ALGO> BlockLoadT;
typedef BlockLoad<int*, BLOCK_THREADS, ITEMS_PER_THREAD, LOAD_ALGO> BlockLoadT;
typedef BlockScan<int, BLOCK_THREADS, SCAN_ALGO> BlockScanT;
// Allocate on-chip temporary storage
__shared__ union {
typename BlockLoadT::TempStorage load;
typename BlockScanT::TempStorage reduce;
} temp_storage;
// Load data per thread
int thread_data[ITEMS_PER_THREAD];
int offset = blockIdx.x * (BLOCK_THREADS * ITEMS_PER_THREAD);
BlockLoadT(temp_storage.load).Load(d_in + offset, offset);
__syncthreads();
// Compute the block-wide prefix sum
BlockScanT(temp_storage).Sum(thread_data);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // RUN: %run_test hipify "%s" "%t" %hipify_args %clang_args
// CHECK: #include <hip/hip_runtime.h>
#include <hip/hip_runtime.h>
#include <iostream>
// CHECK: #include <hiprand.h>
#include <hiprand/hiprand.h>
// CHECK: #include <hipcub/hipcub.hpp>
#include <hipcub/hipcub.hpp>
// using namespace hipcub;
using namespace hipcub;
// Simple CUDA kernel for computing tiled partial sums
template <int BLOCK_THREADS, int ITEMS_PER_THREAD,
BlockLoadAlgorithm LOAD_ALGO,
BlockScanAlgorithm SCAN_ALGO>
__global__ void ScanTilesKernel(int *d_in, int *d_out) {
// Specialize collective types for problem context
// TODO: typedef cub::BlockLoad<int*, BLOCK_THREADS, ITEMS_PER_THREAD, LOAD_ALGO> BlockLoadT;
typedef BlockLoad<int*, BLOCK_THREADS, ITEMS_PER_THREAD, LOAD_ALGO> BlockLoadT;
typedef BlockScan<int, BLOCK_THREADS, SCAN_ALGO> BlockScanT;
// Allocate on-chip temporary storage
__shared__ union {
typename BlockLoadT::TempStorage load;
typename BlockScanT::TempStorage reduce;
} temp_storage;
// Load data per thread
int thread_data[ITEMS_PER_THREAD];
int offset = blockIdx.x * (BLOCK_THREADS * ITEMS_PER_THREAD);
BlockLoadT(temp_storage.load).Load(d_in + offset, offset);
__syncthreads();
// Compute the block-wide prefix sum
BlockScanT(temp_storage).Sum(thread_data);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // RUN: %run_test hipify "%s" "%t" %hipify_args %clang_args
// CHECK: #include <hip/hip_runtime.h>
#include <hip/hip_runtime.h>
#include <iostream>
// CHECK: #include <hiprand.h>
#include <hiprand/hiprand.h>
// CHECK: #include <hipcub/hipcub.hpp>
#include <hipcub/hipcub.hpp>
// using namespace hipcub;
using namespace hipcub;
// Simple CUDA kernel for computing tiled partial sums
template <int BLOCK_THREADS, int ITEMS_PER_THREAD,
BlockLoadAlgorithm LOAD_ALGO,
BlockScanAlgorithm SCAN_ALGO>
__global__ void ScanTilesKernel(int *d_in, int *d_out) {
// Specialize collective types for problem context
// TODO: typedef cub::BlockLoad<int*, BLOCK_THREADS, ITEMS_PER_THREAD, LOAD_ALGO> BlockLoadT;
typedef BlockLoad<int*, BLOCK_THREADS, ITEMS_PER_THREAD, LOAD_ALGO> BlockLoadT;
typedef BlockScan<int, BLOCK_THREADS, SCAN_ALGO> BlockScanT;
// Allocate on-chip temporary storage
__shared__ union {
typename BlockLoadT::TempStorage load;
typename BlockScanT::TempStorage reduce;
} temp_storage;
// Load data per thread
int thread_data[ITEMS_PER_THREAD];
int offset = blockIdx.x * (BLOCK_THREADS * ITEMS_PER_THREAD);
BlockLoadT(temp_storage.load).Load(d_in + offset, offset);
__syncthreads();
// Compute the block-wide prefix sum
BlockScanT(temp_storage).Sum(thread_data);
} | .text
.file "cub_03.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C"
__global__ void find_reduce_point(char *nodes, int node_count, int count, int threads, int blocks, int *out)
{
char TERMINAL = 0;
char NETERMINAL = 1;
char NONE = 0xf;
int TYPE_INDEX = 0;
int MODEL_INDEX = 1;
int CHILD_INDEX = 2;
int VALUE_INDEX = 3;
int NODE_SIZE = 11;
int node_offset = count * NODE_SIZE;
int tid = blockIdx.x * threads + threadIdx.x;
while (tid < count) {
int start_pos = tid * NODE_SIZE;
int child = 0;
int actual = start_pos;
if (nodes[start_pos + TYPE_INDEX] == TERMINAL) {
out[tid] = 0;
}
for (int i = start_pos + node_offset; i < (node_offset * node_count); i += node_offset) {
if (nodes[i + TYPE_INDEX] == TERMINAL)
child++;
else if (nodes[i + TYPE_INDEX] == NETERMINAL) {
child = 0;
actual = i;
} else {
continue;
}
if (child == nodes[actual + CHILD_INDEX]) {
out[tid] = (actual / NODE_SIZE / count);
break;
}
}
tid += threads * blocks;
}
__syncthreads();
} | code for sm_80
Function : find_reduce_point
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ BSSY B0, 0x570 ; /* 0x0000054000007945 */
/* 0x000fe60003800000 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R4, R4, c[0x0][0x170], R3 ; /* 0x00005c0004047a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x16c], PT ; /* 0x00005b0004007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 BRA 0x560 ; /* 0x000004f000000947 */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff007624 */
/* 0x000fc800078e00ff */
/*0080*/ IMAD R0, R0, 0xb, RZ ; /* 0x0000000b00007824 */
/* 0x000fc800078e02ff */
/*0090*/ IMAD R5, R0, c[0x0][0x168], RZ ; /* 0x00005a0000057a24 */
/* 0x000fe400078e02ff */
/*00a0*/ IMAD R9, R4, 0xb, RZ ; /* 0x0000000b04097824 */
/* 0x000fe200078e02ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00c0*/ IADD3 R6, P0, R9, c[0x0][0x160], RZ ; /* 0x0000580009067a10 */
/* 0x000fc80007f1e0ff */
/*00d0*/ LEA.HI.X.SX32 R7, R9, c[0x0][0x164], 0x1, P0 ; /* 0x0000590009077a11 */
/* 0x002fca00000f0eff */
/*00e0*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1100 */
/*00f0*/ IMAD.IADD R8, R0, 0x1, R9 ; /* 0x0000000100087824 */
/* 0x000fe200078e0209 */
/*0100*/ BSSY B1, 0x550 ; /* 0x0000044000017945 */
/* 0x000fe20003800000 */
/*0110*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x001fe400078e00ff */
/*0120*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0b7624 */
/* 0x000fe200078e00ff */
/*0130*/ ISETP.GE.AND P1, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fe20003f26270 */
/*0140*/ IMAD.WIDE R2, R4, R3, c[0x0][0x178] ; /* 0x00005e0004027625 */
/* 0x000fc800078e0203 */
/*0150*/ IMAD R4, R11, c[0x0][0x170], R4 ; /* 0x00005c000b047a24 */
/* 0x000fe200078e0204 */
/*0160*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f05270 */
/*0170*/ @!P0 STG.E [R2.64], RZ ; /* 0x000000ff02008986 */
/* 0x0001e2000c101904 */
/*0180*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x16c], PT ; /* 0x00005b0004007a0c */
/* 0x000fe20003f06270 */
/*0190*/ @P1 BRA 0x540 ; /* 0x000003a000001947 */
/* 0x000fee0003800000 */
/*01a0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fca00078e00ff */
/*01b0*/ IADD3 R6, P1, R8, c[0x0][0x160], RZ ; /* 0x0000580008067a10 */
/* 0x000fe20007f3e0ff */
/*01c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*01d0*/ LEA.HI.X.SX32 R7, R8, c[0x0][0x164], 0x1, P1 ; /* 0x0000590008077a11 */
/* 0x000fca00008f0eff */
/*01e0*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1100 */
/*01f0*/ BSSY B2, 0x340 ; /* 0x0000014000027945 */
/* 0x000fe20003800000 */
/*0200*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f25270 */
/*0210*/ @!P1 BRA 0x270 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*0220*/ ISETP.NE.AND P1, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f25270 */
/*0230*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e00ff */
/*0240*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fd400078e0008 */
/*0250*/ @!P1 BRA 0x290 ; /* 0x0000003000009947 */
/* 0x000fea0003800000 */
/*0260*/ BRA 0x330 ; /* 0x000000c000007947 */
/* 0x000fea0003800000 */
/*0270*/ IADD3 R11, R10, 0x1, RZ ; /* 0x000000010a0b7810 */
/* 0x000fe20007ffe0ff */
/*0280*/ IMAD.MOV.U32 R12, RZ, RZ, R9 ; /* 0x000000ffff0c7224 */
/* 0x000fca00078e0009 */
/*0290*/ IADD3 R7, R12, 0x2, RZ ; /* 0x000000020c077810 */
/* 0x000fe20007ffe0ff */
/*02a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*02b0*/ IADD3 R6, P1, R7, c[0x0][0x160], RZ ; /* 0x0000580007067a10 */
/* 0x000fc80007f3e0ff */
/*02c0*/ LEA.HI.X.SX32 R7, R7, c[0x0][0x164], 0x1, P1 ; /* 0x0000590007077a11 */
/* 0x000fca00008f0eff */
/*02d0*/ LDG.E.S8 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1300 */
/*02e0*/ ISETP.NE.AND P1, PT, R11, R6, PT ; /* 0x000000060b00720c */
/* 0x004fda0003f25270 */
/*02f0*/ @!P1 BREAK B2 ; /* 0x0000000000029942 */
/* 0x000fe20003800000 */
/*0300*/ @!P1 BRA 0x380 ; /* 0x0000007000009947 */
/* 0x000fea0003800000 */
/*0310*/ IMAD.MOV.U32 R10, RZ, RZ, R11 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e000b */
/*0320*/ IMAD.MOV.U32 R9, RZ, RZ, R12 ; /* 0x000000ffff097224 */
/* 0x000fe400078e000c */
/*0330*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0340*/ IMAD.IADD R8, R0, 0x1, R8 ; /* 0x0000000100087824 */
/* 0x000fca00078e0208 */
/*0350*/ ISETP.GE.AND P1, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f26270 */
/*0360*/ @!P1 BRA 0x1b0 ; /* 0xfffffe4000009947 */
/* 0x000fea000383ffff */
/*0370*/ BRA 0x540 ; /* 0x000001c000007947 */
/* 0x000fea0003800000 */
/*0380*/ IABS R11, c[0x0][0x16c] ; /* 0x00005b00000b7a13 */
/* 0x000fe20000000000 */
/*0390*/ IMAD.HI R12, R12, 0x2e8ba2e9, RZ ; /* 0x2e8ba2e90c0c7827 */
/* 0x000fe200078e02ff */
/*03a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*03b0*/ I2F.RP R8, R11 ; /* 0x0000000b00087306 */
/* 0x000e640000209400 */
/*03c0*/ SHF.R.S32.HI R9, RZ, 0x1, R12 ; /* 0x00000001ff097819 */
/* 0x000fc8000001140c */
/*03d0*/ LEA.HI R9, R12, R9, RZ, 0x1 ; /* 0x000000090c097211 */
/* 0x000fe400078f08ff */
/*03e0*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x002e640000001000 */
/*03f0*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x002fe40007ffe0ff */
/*0400*/ IABS R8, R9 ; /* 0x0000000900087213 */
/* 0x000fc80000000000 */
/*0410*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x0002a2000021f000 */
/*0420*/ LOP3.LUT R9, R9, c[0x0][0x16c], RZ, 0x3c, !PT ; /* 0x00005b0009097a12 */
/* 0x000fc800078e3cff */
/*0430*/ ISETP.GE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f46270 */
/*0440*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x002fe400078e00ff */
/*0450*/ IMAD.MOV R10, RZ, RZ, -R7 ; /* 0x000000ffff0a7224 */
/* 0x004fc800078e0a07 */
/*0460*/ IMAD R13, R10, R11, RZ ; /* 0x0000000b0a0d7224 */
/* 0x000fc800078e02ff */
/*0470*/ IMAD.HI.U32 R7, R7, R13, R6 ; /* 0x0000000d07077227 */
/* 0x000fcc00078e0006 */
/*0480*/ IMAD.HI.U32 R7, R7, R8, RZ ; /* 0x0000000807077227 */
/* 0x000fc800078e00ff */
/*0490*/ IMAD.MOV R6, RZ, RZ, -R7 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a07 */
/*04a0*/ IMAD R6, R11, R6, R8 ; /* 0x000000060b067224 */
/* 0x000fca00078e0208 */
/*04b0*/ ISETP.GT.U32.AND P3, PT, R11, R6, PT ; /* 0x000000060b00720c */
/* 0x000fda0003f64070 */
/*04c0*/ @!P3 IMAD.IADD R6, R6, 0x1, -R11 ; /* 0x000000010606b824 */
/* 0x000fe200078e0a0b */
/*04d0*/ @!P3 IADD3 R7, R7, 0x1, RZ ; /* 0x000000010707b810 */
/* 0x000fe40007ffe0ff */
/*04e0*/ ISETP.NE.AND P3, PT, RZ, c[0x0][0x16c], PT ; /* 0x00005b00ff007a0c */
/* 0x000fe40003f65270 */
/*04f0*/ ISETP.GE.U32.AND P1, PT, R6, R11, PT ; /* 0x0000000b0600720c */
/* 0x000fda0003f26070 */
/*0500*/ @P1 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107071810 */
/* 0x000fca0007ffe0ff */
/*0510*/ @!P2 IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff07a224 */
/* 0x000fe200078e0a07 */
/*0520*/ @!P3 LOP3.LUT R7, RZ, c[0x0][0x16c], RZ, 0x33, !PT ; /* 0x00005b00ff07ba12 */
/* 0x000fca00078e33ff */
/*0530*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0003e4000c101904 */
/*0540*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0550*/ @!P0 BRA 0xa0 ; /* 0xfffffb4000008947 */
/* 0x000fea000383ffff */
/*0560*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0570*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0580*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0590*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05a0*/ BRA 0x5a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
__global__ void find_reduce_point(char *nodes, int node_count, int count, int threads, int blocks, int *out)
{
char TERMINAL = 0;
char NETERMINAL = 1;
char NONE = 0xf;
int TYPE_INDEX = 0;
int MODEL_INDEX = 1;
int CHILD_INDEX = 2;
int VALUE_INDEX = 3;
int NODE_SIZE = 11;
int node_offset = count * NODE_SIZE;
int tid = blockIdx.x * threads + threadIdx.x;
while (tid < count) {
int start_pos = tid * NODE_SIZE;
int child = 0;
int actual = start_pos;
if (nodes[start_pos + TYPE_INDEX] == TERMINAL) {
out[tid] = 0;
}
for (int i = start_pos + node_offset; i < (node_offset * node_count); i += node_offset) {
if (nodes[i + TYPE_INDEX] == TERMINAL)
child++;
else if (nodes[i + TYPE_INDEX] == NETERMINAL) {
child = 0;
actual = i;
} else {
continue;
}
if (child == nodes[actual + CHILD_INDEX]) {
out[tid] = (actual / NODE_SIZE / count);
break;
}
}
tid += threads * blocks;
}
__syncthreads();
} | .file "tmpxft_0005a926_00000000-6_evaluate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z17find_reduce_pointPciiiiPiPciiiiPi
.type _Z43__device_stub__Z17find_reduce_pointPciiiiPiPciiiiPi, @function
_Z43__device_stub__Z17find_reduce_pointPciiiiPiPciiiiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq find_reduce_point(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z17find_reduce_pointPciiiiPiPciiiiPi, .-_Z43__device_stub__Z17find_reduce_pointPciiiiPiPciiiiPi
.globl find_reduce_point
.type find_reduce_point, @function
find_reduce_point:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z17find_reduce_pointPciiiiPiPciiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size find_reduce_point, .-find_reduce_point
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "find_reduce_point"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq find_reduce_point(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
__global__ void find_reduce_point(char *nodes, int node_count, int count, int threads, int blocks, int *out)
{
char TERMINAL = 0;
char NETERMINAL = 1;
char NONE = 0xf;
int TYPE_INDEX = 0;
int MODEL_INDEX = 1;
int CHILD_INDEX = 2;
int VALUE_INDEX = 3;
int NODE_SIZE = 11;
int node_offset = count * NODE_SIZE;
int tid = blockIdx.x * threads + threadIdx.x;
while (tid < count) {
int start_pos = tid * NODE_SIZE;
int child = 0;
int actual = start_pos;
if (nodes[start_pos + TYPE_INDEX] == TERMINAL) {
out[tid] = 0;
}
for (int i = start_pos + node_offset; i < (node_offset * node_count); i += node_offset) {
if (nodes[i + TYPE_INDEX] == TERMINAL)
child++;
else if (nodes[i + TYPE_INDEX] == NETERMINAL) {
child = 0;
actual = i;
} else {
continue;
}
if (child == nodes[actual + CHILD_INDEX]) {
out[tid] = (actual / NODE_SIZE / count);
break;
}
}
tid += threads * blocks;
}
__syncthreads();
} | #include <hip/hip_runtime.h>
extern "C"
__global__ void find_reduce_point(char *nodes, int node_count, int count, int threads, int blocks, int *out)
{
char TERMINAL = 0;
char NETERMINAL = 1;
char NONE = 0xf;
int TYPE_INDEX = 0;
int MODEL_INDEX = 1;
int CHILD_INDEX = 2;
int VALUE_INDEX = 3;
int NODE_SIZE = 11;
int node_offset = count * NODE_SIZE;
int tid = blockIdx.x * threads + threadIdx.x;
while (tid < count) {
int start_pos = tid * NODE_SIZE;
int child = 0;
int actual = start_pos;
if (nodes[start_pos + TYPE_INDEX] == TERMINAL) {
out[tid] = 0;
}
for (int i = start_pos + node_offset; i < (node_offset * node_count); i += node_offset) {
if (nodes[i + TYPE_INDEX] == TERMINAL)
child++;
else if (nodes[i + TYPE_INDEX] == NETERMINAL) {
child = 0;
actual = i;
} else {
continue;
}
if (child == nodes[actual + CHILD_INDEX]) {
out[tid] = (actual / NODE_SIZE / count);
break;
}
}
tid += threads * blocks;
}
__syncthreads();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void find_reduce_point(char *nodes, int node_count, int count, int threads, int blocks, int *out)
{
char TERMINAL = 0;
char NETERMINAL = 1;
char NONE = 0xf;
int TYPE_INDEX = 0;
int MODEL_INDEX = 1;
int CHILD_INDEX = 2;
int VALUE_INDEX = 3;
int NODE_SIZE = 11;
int node_offset = count * NODE_SIZE;
int tid = blockIdx.x * threads + threadIdx.x;
while (tid < count) {
int start_pos = tid * NODE_SIZE;
int child = 0;
int actual = start_pos;
if (nodes[start_pos + TYPE_INDEX] == TERMINAL) {
out[tid] = 0;
}
for (int i = start_pos + node_offset; i < (node_offset * node_count); i += node_offset) {
if (nodes[i + TYPE_INDEX] == TERMINAL)
child++;
else if (nodes[i + TYPE_INDEX] == NETERMINAL) {
child = 0;
actual = i;
} else {
continue;
}
if (child == nodes[actual + CHILD_INDEX]) {
out[tid] = (actual / NODE_SIZE / count);
break;
}
}
tid += threads * blocks;
}
__syncthreads();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected find_reduce_point
.globl find_reduce_point
.p2align 8
.type find_reduce_point,@function
find_reduce_point:
s_load_b64 s[2:3], s[0:1], 0xc
s_mov_b32 s9, exec_lo
s_waitcnt lgkmcnt(0)
s_mul_i32 s15, s15, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s15, v0
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_20
s_clause 0x3
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s13, s[0:1], 0x8
s_load_b32 s14, s[0:1], 0x14
s_load_b64 s[6:7], s[0:1], 0x18
v_add3_u32 v0, s15, s2, v0
s_mul_i32 s8, s2, 11
s_mov_b32 s16, 0
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v0, v0, 11
s_waitcnt lgkmcnt(0)
s_add_u32 s1, s4, 2
s_addc_u32 s10, s5, 0
s_ashr_i32 s11, s2, 31
s_mul_i32 s3, s14, s3
s_add_i32 s0, s2, s11
s_mul_i32 s13, s8, s13
s_xor_b32 s12, s0, s11
s_mul_i32 s14, s3, 11
v_cvt_f32_u32_e32 v2, s12
s_sub_i32 s0, 0, s12
s_ashr_i32 s15, s8, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s0, v2
v_mul_hi_u32 v5, v2, v3
v_mad_u64_u32 v[3:4], null, v1, 11, s[8:9]
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v7, v2, v5
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s17
v_add_nc_u32_e32 v1, s3, v1
v_add_nc_u32_e32 v0, s14, v0
v_add_nc_u32_e32 v3, s14, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s2, v1
s_or_b32 s16, vcc_lo, s16
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execz .LBB0_20
.LBB0_3:
v_mul_lo_u32 v8, v1, 11
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v8
v_add_co_u32 v4, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v2, vcc_lo
global_load_u8 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u16_e32 0, v2
s_cbranch_execz .LBB0_5
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_store_b32 v[4:5], v6, off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v2, s8, v8
v_ashrrev_i32_e32 v4, 31, v3
s_mov_b32 s17, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_i32_e64 s13, v2
s_cbranch_execz .LBB0_2
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v5, v4
v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v4, v3
v_mov_b32_e32 v2, v0
s_mov_b32 s18, 0
s_branch .LBB0_8
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s22
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, exec_lo, s21
s_or_b32 s18, s0, s18
s_and_not1_b32 s0, s19, exec_lo
s_and_b32 s19, s20, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s19, s0, s19
s_and_not1_b32 exec_lo, exec_lo, s18
s_cbranch_execz .LBB0_18
.LBB0_8:
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v5, vcc_lo
s_mov_b32 s21, 0
s_mov_b32 s0, 0
s_mov_b32 s22, exec_lo
global_load_u8 v10, v[10:11], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i16_e32 0, v10
s_xor_b32 s22, exec_lo, s22
s_cbranch_execz .LBB0_12
s_mov_b32 s0, -1
s_mov_b32 s24, exec_lo
v_cmpx_eq_u16_e32 1, v10
v_mov_b32_e32 v8, v4
s_mov_b32 s21, exec_lo
s_mov_b32 s23, 0
s_xor_b32 s0, exec_lo, -1
s_or_b32 exec_lo, exec_lo, s24
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s0, s0, exec_lo
s_and_b32 s21, s21, exec_lo
.LBB0_12:
s_or_saveexec_b32 s22, s22
v_mov_b32_e32 v10, s23
s_xor_b32 exec_lo, exec_lo, s22
v_add_nc_u32_e32 v10, 1, v9
s_or_b32 s21, s21, exec_lo
s_or_b32 exec_lo, exec_lo, s22
s_and_saveexec_b32 s22, s21
s_cbranch_execz .LBB0_16
v_ashrrev_i32_e32 v9, 31, v8
v_add_co_u32 v11, vcc_lo, s1, v8
s_and_not1_b32 s0, s0, exec_lo
s_mov_b32 s23, -1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v12, vcc_lo, s10, v9, vcc_lo
global_load_i8 v9, v[11:12], off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, v10, v9
v_mov_b32_e32 v9, v10
s_and_b32 s21, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s0, s0, s21
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s22
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 s20, s20, exec_lo
s_and_b32 s22, s23, exec_lo
s_mov_b32 s21, -1
s_or_b32 s20, s20, s22
s_and_saveexec_b32 s22, s0
s_cbranch_execz .LBB0_7
v_add_nc_u32_e32 v2, s8, v2
v_add_co_u32 v4, s0, v4, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v5, s0, s15, v5, s0
v_cmp_le_i32_e32 vcc_lo, s13, v2
s_and_not1_b32 s20, s20, exec_lo
s_or_not1_b32 s21, vcc_lo, exec_lo
s_branch .LBB0_7
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s18
s_and_saveexec_b32 s0, s19
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_2
v_mul_hi_i32 v2, v8, 0x2e8ba2e9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v4, 31, v2
v_ashrrev_i32_e32 v2, 1, v2
v_add_nc_u32_e32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v2
v_add_nc_u32_e32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v4
v_mul_hi_u32 v5, v2, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v8, v5, s12
v_sub_nc_u32_e32 v2, v2, v8
v_add_nc_u32_e32 v8, 1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v9, s12, v2
v_cmp_le_u32_e32 vcc_lo, s12, v2
v_dual_cndmask_b32 v5, v5, v8 :: v_dual_cndmask_b32 v2, v2, v9
v_xor_b32_e32 v9, s11, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v8, 1, v5
v_cmp_le_u32_e32 vcc_lo, s12, v2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v5, v8, vcc_lo
v_xor_b32_e32 v8, v4, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_sub_nc_u32_e32 v2, v8, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_store_b32 v[4:5], v2, off
s_branch .LBB0_2
.LBB0_20:
s_or_b32 exec_lo, exec_lo, s9
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel find_reduce_point
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 25
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size find_reduce_point, .Lfunc_end0-find_reduce_point
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: find_reduce_point
.private_segment_fixed_size: 0
.sgpr_count: 27
.sgpr_spill_count: 0
.symbol: find_reduce_point.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void find_reduce_point(char *nodes, int node_count, int count, int threads, int blocks, int *out)
{
char TERMINAL = 0;
char NETERMINAL = 1;
char NONE = 0xf;
int TYPE_INDEX = 0;
int MODEL_INDEX = 1;
int CHILD_INDEX = 2;
int VALUE_INDEX = 3;
int NODE_SIZE = 11;
int node_offset = count * NODE_SIZE;
int tid = blockIdx.x * threads + threadIdx.x;
while (tid < count) {
int start_pos = tid * NODE_SIZE;
int child = 0;
int actual = start_pos;
if (nodes[start_pos + TYPE_INDEX] == TERMINAL) {
out[tid] = 0;
}
for (int i = start_pos + node_offset; i < (node_offset * node_count); i += node_offset) {
if (nodes[i + TYPE_INDEX] == TERMINAL)
child++;
else if (nodes[i + TYPE_INDEX] == NETERMINAL) {
child = 0;
actual = i;
} else {
continue;
}
if (child == nodes[actual + CHILD_INDEX]) {
out[tid] = (actual / NODE_SIZE / count);
break;
}
}
tid += threads * blocks;
}
__syncthreads();
} | .text
.file "evaluate.hip"
.globl __device_stub__find_reduce_point # -- Begin function __device_stub__find_reduce_point
.p2align 4, 0x90
.type __device_stub__find_reduce_point,@function
__device_stub__find_reduce_point: # @__device_stub__find_reduce_point
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %r9, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $find_reduce_point, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size __device_stub__find_reduce_point, .Lfunc_end0-__device_stub__find_reduce_point
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $find_reduce_point, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type find_reduce_point,@object # @find_reduce_point
.section .rodata,"a",@progbits
.globl find_reduce_point
.p2align 3, 0x0
find_reduce_point:
.quad __device_stub__find_reduce_point
.size find_reduce_point, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "find_reduce_point"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__find_reduce_point
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym find_reduce_point
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : find_reduce_point
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ BSSY B0, 0x570 ; /* 0x0000054000007945 */
/* 0x000fe60003800000 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R4, R4, c[0x0][0x170], R3 ; /* 0x00005c0004047a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x16c], PT ; /* 0x00005b0004007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 BRA 0x560 ; /* 0x000004f000000947 */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff007624 */
/* 0x000fc800078e00ff */
/*0080*/ IMAD R0, R0, 0xb, RZ ; /* 0x0000000b00007824 */
/* 0x000fc800078e02ff */
/*0090*/ IMAD R5, R0, c[0x0][0x168], RZ ; /* 0x00005a0000057a24 */
/* 0x000fe400078e02ff */
/*00a0*/ IMAD R9, R4, 0xb, RZ ; /* 0x0000000b04097824 */
/* 0x000fe200078e02ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00c0*/ IADD3 R6, P0, R9, c[0x0][0x160], RZ ; /* 0x0000580009067a10 */
/* 0x000fc80007f1e0ff */
/*00d0*/ LEA.HI.X.SX32 R7, R9, c[0x0][0x164], 0x1, P0 ; /* 0x0000590009077a11 */
/* 0x002fca00000f0eff */
/*00e0*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1100 */
/*00f0*/ IMAD.IADD R8, R0, 0x1, R9 ; /* 0x0000000100087824 */
/* 0x000fe200078e0209 */
/*0100*/ BSSY B1, 0x550 ; /* 0x0000044000017945 */
/* 0x000fe20003800000 */
/*0110*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x001fe400078e00ff */
/*0120*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0b7624 */
/* 0x000fe200078e00ff */
/*0130*/ ISETP.GE.AND P1, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fe20003f26270 */
/*0140*/ IMAD.WIDE R2, R4, R3, c[0x0][0x178] ; /* 0x00005e0004027625 */
/* 0x000fc800078e0203 */
/*0150*/ IMAD R4, R11, c[0x0][0x170], R4 ; /* 0x00005c000b047a24 */
/* 0x000fe200078e0204 */
/*0160*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f05270 */
/*0170*/ @!P0 STG.E [R2.64], RZ ; /* 0x000000ff02008986 */
/* 0x0001e2000c101904 */
/*0180*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x16c], PT ; /* 0x00005b0004007a0c */
/* 0x000fe20003f06270 */
/*0190*/ @P1 BRA 0x540 ; /* 0x000003a000001947 */
/* 0x000fee0003800000 */
/*01a0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fca00078e00ff */
/*01b0*/ IADD3 R6, P1, R8, c[0x0][0x160], RZ ; /* 0x0000580008067a10 */
/* 0x000fe20007f3e0ff */
/*01c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*01d0*/ LEA.HI.X.SX32 R7, R8, c[0x0][0x164], 0x1, P1 ; /* 0x0000590008077a11 */
/* 0x000fca00008f0eff */
/*01e0*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1100 */
/*01f0*/ BSSY B2, 0x340 ; /* 0x0000014000027945 */
/* 0x000fe20003800000 */
/*0200*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f25270 */
/*0210*/ @!P1 BRA 0x270 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*0220*/ ISETP.NE.AND P1, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f25270 */
/*0230*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e00ff */
/*0240*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fd400078e0008 */
/*0250*/ @!P1 BRA 0x290 ; /* 0x0000003000009947 */
/* 0x000fea0003800000 */
/*0260*/ BRA 0x330 ; /* 0x000000c000007947 */
/* 0x000fea0003800000 */
/*0270*/ IADD3 R11, R10, 0x1, RZ ; /* 0x000000010a0b7810 */
/* 0x000fe20007ffe0ff */
/*0280*/ IMAD.MOV.U32 R12, RZ, RZ, R9 ; /* 0x000000ffff0c7224 */
/* 0x000fca00078e0009 */
/*0290*/ IADD3 R7, R12, 0x2, RZ ; /* 0x000000020c077810 */
/* 0x000fe20007ffe0ff */
/*02a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*02b0*/ IADD3 R6, P1, R7, c[0x0][0x160], RZ ; /* 0x0000580007067a10 */
/* 0x000fc80007f3e0ff */
/*02c0*/ LEA.HI.X.SX32 R7, R7, c[0x0][0x164], 0x1, P1 ; /* 0x0000590007077a11 */
/* 0x000fca00008f0eff */
/*02d0*/ LDG.E.S8 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1300 */
/*02e0*/ ISETP.NE.AND P1, PT, R11, R6, PT ; /* 0x000000060b00720c */
/* 0x004fda0003f25270 */
/*02f0*/ @!P1 BREAK B2 ; /* 0x0000000000029942 */
/* 0x000fe20003800000 */
/*0300*/ @!P1 BRA 0x380 ; /* 0x0000007000009947 */
/* 0x000fea0003800000 */
/*0310*/ IMAD.MOV.U32 R10, RZ, RZ, R11 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e000b */
/*0320*/ IMAD.MOV.U32 R9, RZ, RZ, R12 ; /* 0x000000ffff097224 */
/* 0x000fe400078e000c */
/*0330*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0340*/ IMAD.IADD R8, R0, 0x1, R8 ; /* 0x0000000100087824 */
/* 0x000fca00078e0208 */
/*0350*/ ISETP.GE.AND P1, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f26270 */
/*0360*/ @!P1 BRA 0x1b0 ; /* 0xfffffe4000009947 */
/* 0x000fea000383ffff */
/*0370*/ BRA 0x540 ; /* 0x000001c000007947 */
/* 0x000fea0003800000 */
/*0380*/ IABS R11, c[0x0][0x16c] ; /* 0x00005b00000b7a13 */
/* 0x000fe20000000000 */
/*0390*/ IMAD.HI R12, R12, 0x2e8ba2e9, RZ ; /* 0x2e8ba2e90c0c7827 */
/* 0x000fe200078e02ff */
/*03a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*03b0*/ I2F.RP R8, R11 ; /* 0x0000000b00087306 */
/* 0x000e640000209400 */
/*03c0*/ SHF.R.S32.HI R9, RZ, 0x1, R12 ; /* 0x00000001ff097819 */
/* 0x000fc8000001140c */
/*03d0*/ LEA.HI R9, R12, R9, RZ, 0x1 ; /* 0x000000090c097211 */
/* 0x000fe400078f08ff */
/*03e0*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x002e640000001000 */
/*03f0*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x002fe40007ffe0ff */
/*0400*/ IABS R8, R9 ; /* 0x0000000900087213 */
/* 0x000fc80000000000 */
/*0410*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x0002a2000021f000 */
/*0420*/ LOP3.LUT R9, R9, c[0x0][0x16c], RZ, 0x3c, !PT ; /* 0x00005b0009097a12 */
/* 0x000fc800078e3cff */
/*0430*/ ISETP.GE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f46270 */
/*0440*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x002fe400078e00ff */
/*0450*/ IMAD.MOV R10, RZ, RZ, -R7 ; /* 0x000000ffff0a7224 */
/* 0x004fc800078e0a07 */
/*0460*/ IMAD R13, R10, R11, RZ ; /* 0x0000000b0a0d7224 */
/* 0x000fc800078e02ff */
/*0470*/ IMAD.HI.U32 R7, R7, R13, R6 ; /* 0x0000000d07077227 */
/* 0x000fcc00078e0006 */
/*0480*/ IMAD.HI.U32 R7, R7, R8, RZ ; /* 0x0000000807077227 */
/* 0x000fc800078e00ff */
/*0490*/ IMAD.MOV R6, RZ, RZ, -R7 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a07 */
/*04a0*/ IMAD R6, R11, R6, R8 ; /* 0x000000060b067224 */
/* 0x000fca00078e0208 */
/*04b0*/ ISETP.GT.U32.AND P3, PT, R11, R6, PT ; /* 0x000000060b00720c */
/* 0x000fda0003f64070 */
/*04c0*/ @!P3 IMAD.IADD R6, R6, 0x1, -R11 ; /* 0x000000010606b824 */
/* 0x000fe200078e0a0b */
/*04d0*/ @!P3 IADD3 R7, R7, 0x1, RZ ; /* 0x000000010707b810 */
/* 0x000fe40007ffe0ff */
/*04e0*/ ISETP.NE.AND P3, PT, RZ, c[0x0][0x16c], PT ; /* 0x00005b00ff007a0c */
/* 0x000fe40003f65270 */
/*04f0*/ ISETP.GE.U32.AND P1, PT, R6, R11, PT ; /* 0x0000000b0600720c */
/* 0x000fda0003f26070 */
/*0500*/ @P1 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107071810 */
/* 0x000fca0007ffe0ff */
/*0510*/ @!P2 IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff07a224 */
/* 0x000fe200078e0a07 */
/*0520*/ @!P3 LOP3.LUT R7, RZ, c[0x0][0x16c], RZ, 0x33, !PT ; /* 0x00005b00ff07ba12 */
/* 0x000fca00078e33ff */
/*0530*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0003e4000c101904 */
/*0540*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0550*/ @!P0 BRA 0xa0 ; /* 0xfffffb4000008947 */
/* 0x000fea000383ffff */
/*0560*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0570*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0580*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0590*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05a0*/ BRA 0x5a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected find_reduce_point
.globl find_reduce_point
.p2align 8
.type find_reduce_point,@function
find_reduce_point:
s_load_b64 s[2:3], s[0:1], 0xc
s_mov_b32 s9, exec_lo
s_waitcnt lgkmcnt(0)
s_mul_i32 s15, s15, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s15, v0
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_20
s_clause 0x3
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s13, s[0:1], 0x8
s_load_b32 s14, s[0:1], 0x14
s_load_b64 s[6:7], s[0:1], 0x18
v_add3_u32 v0, s15, s2, v0
s_mul_i32 s8, s2, 11
s_mov_b32 s16, 0
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v0, v0, 11
s_waitcnt lgkmcnt(0)
s_add_u32 s1, s4, 2
s_addc_u32 s10, s5, 0
s_ashr_i32 s11, s2, 31
s_mul_i32 s3, s14, s3
s_add_i32 s0, s2, s11
s_mul_i32 s13, s8, s13
s_xor_b32 s12, s0, s11
s_mul_i32 s14, s3, 11
v_cvt_f32_u32_e32 v2, s12
s_sub_i32 s0, 0, s12
s_ashr_i32 s15, s8, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s0, v2
v_mul_hi_u32 v5, v2, v3
v_mad_u64_u32 v[3:4], null, v1, 11, s[8:9]
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v7, v2, v5
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s17
v_add_nc_u32_e32 v1, s3, v1
v_add_nc_u32_e32 v0, s14, v0
v_add_nc_u32_e32 v3, s14, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s2, v1
s_or_b32 s16, vcc_lo, s16
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execz .LBB0_20
.LBB0_3:
v_mul_lo_u32 v8, v1, 11
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v8
v_add_co_u32 v4, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v2, vcc_lo
global_load_u8 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u16_e32 0, v2
s_cbranch_execz .LBB0_5
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_store_b32 v[4:5], v6, off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v2, s8, v8
v_ashrrev_i32_e32 v4, 31, v3
s_mov_b32 s17, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_i32_e64 s13, v2
s_cbranch_execz .LBB0_2
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v5, v4
v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v4, v3
v_mov_b32_e32 v2, v0
s_mov_b32 s18, 0
s_branch .LBB0_8
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s22
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, exec_lo, s21
s_or_b32 s18, s0, s18
s_and_not1_b32 s0, s19, exec_lo
s_and_b32 s19, s20, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s19, s0, s19
s_and_not1_b32 exec_lo, exec_lo, s18
s_cbranch_execz .LBB0_18
.LBB0_8:
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v5, vcc_lo
s_mov_b32 s21, 0
s_mov_b32 s0, 0
s_mov_b32 s22, exec_lo
global_load_u8 v10, v[10:11], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i16_e32 0, v10
s_xor_b32 s22, exec_lo, s22
s_cbranch_execz .LBB0_12
s_mov_b32 s0, -1
s_mov_b32 s24, exec_lo
v_cmpx_eq_u16_e32 1, v10
v_mov_b32_e32 v8, v4
s_mov_b32 s21, exec_lo
s_mov_b32 s23, 0
s_xor_b32 s0, exec_lo, -1
s_or_b32 exec_lo, exec_lo, s24
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s0, s0, exec_lo
s_and_b32 s21, s21, exec_lo
.LBB0_12:
s_or_saveexec_b32 s22, s22
v_mov_b32_e32 v10, s23
s_xor_b32 exec_lo, exec_lo, s22
v_add_nc_u32_e32 v10, 1, v9
s_or_b32 s21, s21, exec_lo
s_or_b32 exec_lo, exec_lo, s22
s_and_saveexec_b32 s22, s21
s_cbranch_execz .LBB0_16
v_ashrrev_i32_e32 v9, 31, v8
v_add_co_u32 v11, vcc_lo, s1, v8
s_and_not1_b32 s0, s0, exec_lo
s_mov_b32 s23, -1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v12, vcc_lo, s10, v9, vcc_lo
global_load_i8 v9, v[11:12], off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, v10, v9
v_mov_b32_e32 v9, v10
s_and_b32 s21, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s0, s0, s21
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s22
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 s20, s20, exec_lo
s_and_b32 s22, s23, exec_lo
s_mov_b32 s21, -1
s_or_b32 s20, s20, s22
s_and_saveexec_b32 s22, s0
s_cbranch_execz .LBB0_7
v_add_nc_u32_e32 v2, s8, v2
v_add_co_u32 v4, s0, v4, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v5, s0, s15, v5, s0
v_cmp_le_i32_e32 vcc_lo, s13, v2
s_and_not1_b32 s20, s20, exec_lo
s_or_not1_b32 s21, vcc_lo, exec_lo
s_branch .LBB0_7
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s18
s_and_saveexec_b32 s0, s19
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_2
v_mul_hi_i32 v2, v8, 0x2e8ba2e9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v4, 31, v2
v_ashrrev_i32_e32 v2, 1, v2
v_add_nc_u32_e32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v2
v_add_nc_u32_e32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v4
v_mul_hi_u32 v5, v2, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v8, v5, s12
v_sub_nc_u32_e32 v2, v2, v8
v_add_nc_u32_e32 v8, 1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v9, s12, v2
v_cmp_le_u32_e32 vcc_lo, s12, v2
v_dual_cndmask_b32 v5, v5, v8 :: v_dual_cndmask_b32 v2, v2, v9
v_xor_b32_e32 v9, s11, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v8, 1, v5
v_cmp_le_u32_e32 vcc_lo, s12, v2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v5, v8, vcc_lo
v_xor_b32_e32 v8, v4, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_sub_nc_u32_e32 v2, v8, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_store_b32 v[4:5], v2, off
s_branch .LBB0_2
.LBB0_20:
s_or_b32 exec_lo, exec_lo, s9
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel find_reduce_point
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 25
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size find_reduce_point, .Lfunc_end0-find_reduce_point
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: find_reduce_point
.private_segment_fixed_size: 0
.sgpr_count: 27
.sgpr_spill_count: 0
.symbol: find_reduce_point.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005a926_00000000-6_evaluate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z17find_reduce_pointPciiiiPiPciiiiPi
.type _Z43__device_stub__Z17find_reduce_pointPciiiiPiPciiiiPi, @function
_Z43__device_stub__Z17find_reduce_pointPciiiiPiPciiiiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq find_reduce_point(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z17find_reduce_pointPciiiiPiPciiiiPi, .-_Z43__device_stub__Z17find_reduce_pointPciiiiPiPciiiiPi
.globl find_reduce_point
.type find_reduce_point, @function
find_reduce_point:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z17find_reduce_pointPciiiiPiPciiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size find_reduce_point, .-find_reduce_point
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "find_reduce_point"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq find_reduce_point(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "evaluate.hip"
.globl __device_stub__find_reduce_point # -- Begin function __device_stub__find_reduce_point
.p2align 4, 0x90
.type __device_stub__find_reduce_point,@function
__device_stub__find_reduce_point: # @__device_stub__find_reduce_point
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %r9, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $find_reduce_point, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size __device_stub__find_reduce_point, .Lfunc_end0-__device_stub__find_reduce_point
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $find_reduce_point, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type find_reduce_point,@object # @find_reduce_point
.section .rodata,"a",@progbits
.globl find_reduce_point
.p2align 3, 0x0
find_reduce_point:
.quad __device_stub__find_reduce_point
.size find_reduce_point, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "find_reduce_point"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__find_reduce_point
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym find_reduce_point
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <time.h>
#include <iostream>
#include <math.h>
#include <vector>
#include <stdio.h>
#include <stdlib.h>
#include <chrono>
using namespace std;
using namespace std::chrono;
#define W (8192)
#define N (8192)
#define THREADS_PER_BLOCK (1)
#define NUMBER_BLOCKS (N/THREADS_PER_BLOCK)
typedef float myFloat;
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true){
if (code != cudaSuccess){
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void DistanceForBMUCalcBlocks(myFloat *input, myFloat *v, myFloat *x){
myFloat d = 0;
for(long long int i = 0; i < W; i++){
d += (v[i+W*blockIdx.x] - input[i]) * (v[blockIdx.x*W+i] - input[i]);
}
x[blockIdx.x] = sqrt(d);
}
__global__ void DistanceForBMUCalcBlocksAndThreads(myFloat *input, myFloat *v, myFloat *x){
myFloat d = 0;
int index = threadIdx.x + blockIdx.x * blockDim.x;
for(long long int i = 0; i < W; i++){
d += (v[i+W*index] - input[i]) * (v[index*W+i] - input[i]);
}
x[index] = sqrt(d);
}
int main(int argc, char* argv[]){
steady_clock::time_point t_i = steady_clock::now();
srand(0);
myFloat *v;
myFloat *d_v;
long long int size = N*W * sizeof(myFloat);
long long int d_vSize = N*W * sizeof(myFloat);
gpuErrchk(cudaMalloc((void **)&d_v, d_vSize));
v = (myFloat *)malloc(size);
for(int i = 0; i < N*W; i++){
v[i] = rand();
}
myFloat *distances;
myFloat *d_distances;
long long int distanceArraySize = N * sizeof(myFloat);
gpuErrchk(cudaMalloc((void **)&d_distances, distanceArraySize));
distances = (myFloat *)malloc(distanceArraySize);
myFloat *training;
myFloat *d_training;
long long int trainingSize = W * sizeof(myFloat);
gpuErrchk(cudaMalloc((void **)&d_training, trainingSize));
training = (myFloat *)malloc(trainingSize);
int index = 0;
for(int i = 0; i < W; i++){
training[i] = rand();
}
steady_clock::time_point workI = steady_clock::now();
for(int i = 0; i < 1; i++){
//steady_clock::time_point t_CPUToGPUI = steady_clock::now();
gpuErrchk(cudaMemcpy(d_v, v, size, cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(d_training, training, trainingSize, cudaMemcpyHostToDevice));
//int t_CPUToGPUF = time(NULL);
//cout<<"Finished copying to device "<<t_CPUToGPUF - t_CPUToGPUI<<endl;
//DistanceForBMUCalcBlocks<<<NUMBER_BLOCKS, THREADS_PER_BLOCK>>>(d_training, d_v, d_distances);
DistanceForBMUCalcBlocksAndThreads<<<NUMBER_BLOCKS, THREADS_PER_BLOCK>>>(d_training, d_v, d_distances);
cudaThreadSynchronize();
//cout<<"Finished distance calc"<<endl;
//int t_GPUToCPUI = time(NULL);
gpuErrchk(cudaMemcpy(distances, d_distances, distanceArraySize, cudaMemcpyDeviceToHost));
//int t_GPUToCPUF = time(NULL);
//cout<<"Finished Device to CPU copy "<<t_GPUToCPUF - t_GPUToCPUI<<endl;
myFloat dmin = distances[0];
for(int j = 0; j < N; j++){
if(distances[j] < dmin){
dmin = distances[j];
index = j;
}
}
}
steady_clock::time_point workF = steady_clock::now();
cout<<"Total work execution time "<<duration_cast<milliseconds>(workF - workI).count()<<endl;
cout<<"BMU is "<<index<<endl;
steady_clock::time_point t_f = steady_clock::now();
cout<<"Total Execution Time: "<<duration_cast<milliseconds>(t_f - t_i).count()<<endl;
} | code for sm_80
Function : _Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ UMOV UR5, 0x2000 ; /* 0x0000200000057882 */
/* 0x000fe40000000000 */
/*0070*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0090*/ SHF.L.U32 R2, R0, 0xd, RZ ; /* 0x0000000d00027819 */
/* 0x000fca00000006ff */
/*00a0*/ IMAD.WIDE R2, R2, R7, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0207 */
/*00b0*/ IADD3 R4, P0, R2, 0x20, RZ ; /* 0x0000002002047810 */
/* 0x000fe40007f1e0ff */
/*00c0*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe40000000f00 */
/*00d0*/ IADD3.X R5, RZ, R3, RZ, P0, !PT ; /* 0x00000003ff057210 */
/* 0x000fe400007fe4ff */
/*00e0*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*00f0*/ LDG.E R12, [R2.64] ; /* 0x00000006020c7981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R13, [R4.64+-0x20] ; /* 0xffffe006040d7981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R24, [R2.64+0x4] ; /* 0x0000040602187981 */
/* 0x000ee8000c1e1900 */
/*0120*/ LDG.E R25, [R4.64+-0x1c] ; /* 0xffffe40604197981 */
/* 0x000ee8000c1e1900 */
/*0130*/ LDG.E R17, [R2.64+0x8] ; /* 0x0000080602117981 */
/* 0x000f28000c1e1900 */
/*0140*/ LDG.E R14, [R4.64+-0x18] ; /* 0xffffe806040e7981 */
/* 0x000f28000c1e1900 */
/*0150*/ LDG.E R16, [R2.64+0xc] ; /* 0x00000c0602107981 */
/* 0x000f68000c1e1900 */
/*0160*/ LDG.E R19, [R4.64+-0x14] ; /* 0xffffec0604137981 */
/* 0x000f68000c1e1900 */
/*0170*/ LDG.E R23, [R2.64+0x10] ; /* 0x0000100602177981 */
/* 0x000f68000c1e1900 */
/*0180*/ LDG.E R20, [R4.64+-0x10] ; /* 0xfffff00604147981 */
/* 0x000f68000c1e1900 */
/*0190*/ LDG.E R18, [R2.64+0x14] ; /* 0x0000140602127981 */
/* 0x000f68000c1e1900 */
/*01a0*/ LDG.E R21, [R4.64+-0xc] ; /* 0xfffff40604157981 */
/* 0x000f68000c1e1900 */
/*01b0*/ LDG.E R11, [R2.64+0x18] ; /* 0x00001806020b7981 */
/* 0x000f68000c1e1900 */
/*01c0*/ LDG.E R8, [R4.64+-0x8] ; /* 0xfffff80604087981 */
/* 0x000f68000c1e1900 */
/*01d0*/ LDG.E R6, [R2.64+0x1c] ; /* 0x00001c0602067981 */
/* 0x000f68000c1e1900 */
/*01e0*/ LDG.E R9, [R4.64+-0x4] ; /* 0xfffffc0604097981 */
/* 0x000f68000c1e1900 */
/*01f0*/ LDG.E R15, [R2.64+0x20] ; /* 0x00002006020f7981 */
/* 0x000162000c1e1900 */
/*0200*/ FADD R13, -R12, R13 ; /* 0x0000000d0c0d7221 */
/* 0x004fc60000000100 */
/*0210*/ LDG.E R12, [R4.64] ; /* 0x00000006040c7981 */
/* 0x0002a2000c1e1900 */
/*0220*/ FFMA R22, R13, R13, R10 ; /* 0x0000000d0d167223 */
/* 0x000fc6000000000a */
/*0230*/ LDG.E R13, [R2.64+0x24] ; /* 0x00002406020d7981 */
/* 0x0000a2000c1e1900 */
/*0240*/ FADD R25, -R24, R25 ; /* 0x0000001918197221 */
/* 0x008fc60000000100 */
/*0250*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000406040a7981 */
/* 0x0002e2000c1e1900 */
/*0260*/ FFMA R22, R25, R25, R22 ; /* 0x0000001919167223 */
/* 0x000fe40000000016 */
/*0270*/ FADD R25, -R17, R14 ; /* 0x0000000e11197221 */
/* 0x010fe40000000100 */
/*0280*/ LDG.E R17, [R2.64+0x28] ; /* 0x0000280602117981 */
/* 0x000124000c1e1900 */
/*0290*/ FFMA R22, R25, R25, R22 ; /* 0x0000001919167223 */
/* 0x000fe40000000016 */
/*02a0*/ LDG.E R14, [R4.64+0x8] ; /* 0x00000806040e7981 */
/* 0x000322000c1e1900 */
/*02b0*/ FADD R25, -R16, R19 ; /* 0x0000001310197221 */
/* 0x020fc60000000100 */
/*02c0*/ LDG.E R19, [R2.64+0x2c] ; /* 0x00002c0602137981 */
/* 0x000162000c1e1900 */
/*02d0*/ FFMA R22, R25, R25, R22 ; /* 0x0000001919167223 */
/* 0x000fc60000000016 */
/*02e0*/ LDG.E R16, [R4.64+0xc] ; /* 0x00000c0604107981 */
/* 0x000362000c1e1900 */
/*02f0*/ FADD R25, -R23, R20 ; /* 0x0000001417197221 */
/* 0x000fc60000000100 */
/*0300*/ LDG.E R20, [R2.64+0x30] ; /* 0x0000300602147981 */
/* 0x000162000c1e1900 */
/*0310*/ FFMA R22, R25, R25, R22 ; /* 0x0000001919167223 */
/* 0x000fc60000000016 */
/*0320*/ LDG.E R23, [R4.64+0x10] ; /* 0x0000100604177981 */
/* 0x000362000c1e1900 */
/*0330*/ FADD R25, -R18, R21 ; /* 0x0000001512197221 */
/* 0x000fc60000000100 */
/*0340*/ LDG.E R21, [R2.64+0x34] ; /* 0x0000340602157981 */
/* 0x000168000c1e1900 */
/*0350*/ LDG.E R18, [R4.64+0x14] ; /* 0x0000140604127981 */
/* 0x000362000c1e1900 */
/*0360*/ FFMA R24, R25, R25, R22 ; /* 0x0000001919187223 */
/* 0x000fc60000000016 */
/*0370*/ LDG.E R25, [R2.64+0x38] ; /* 0x0000380602197981 */
/* 0x000162000c1e1900 */
/*0380*/ FADD R27, -R11, R8 ; /* 0x000000080b1b7221 */
/* 0x000fc60000000100 */
/*0390*/ LDG.E R22, [R4.64+0x18] ; /* 0x0000180604167981 */
/* 0x000368000c1e1900 */
/*03a0*/ LDG.E R8, [R2.64+0x3c] ; /* 0x00003c0602087981 */
/* 0x000168000c1e1900 */
/*03b0*/ LDG.E R11, [R4.64+0x1c] ; /* 0x00001c06040b7981 */
/* 0x000362000c1e1900 */
/*03c0*/ FFMA R24, R27, R27, R24 ; /* 0x0000001b1b187223 */
/* 0x000fe40000000018 */
/*03d0*/ FADD R9, -R6, R9 ; /* 0x0000000906097221 */
/* 0x000fc80000000100 */
/*03e0*/ FFMA R24, R9, R9, R24 ; /* 0x0000000909187223 */
/* 0x000fe20000000018 */
/*03f0*/ UIADD3 UR5, UP0, UR5, -0x10, URZ ; /* 0xfffffff005057890 */
/* 0x000fc8000ff1e03f */
/*0400*/ UIADD3.X UR4, UR4, -0x1, URZ, UP0, !UPT ; /* 0xffffffff04047890 */
/* 0x000fe400087fe43f */
/*0410*/ ISETP.NE.U32.AND P0, PT, RZ, UR5, PT ; /* 0x00000005ff007c0c */
/* 0x000fc8000bf05070 */
/*0420*/ ISETP.NE.AND.EX P0, PT, RZ, UR4, PT, P0 ; /* 0x00000004ff007c0c */
/* 0x000fe4000bf05300 */
/*0430*/ IADD3 R4, P1, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x002fe40007f3e0ff */
/*0440*/ IADD3 R2, P2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x001fe40007f5e0ff */
/*0450*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe40000ffe4ff */
/*0460*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x000fe200017fe4ff */
/*0470*/ FADD R15, -R15, R12 ; /* 0x0000000c0f0f7221 */
/* 0x004fc80000000100 */
/*0480*/ FFMA R24, R15, R15, R24 ; /* 0x0000000f0f187223 */
/* 0x000fe40000000018 */
/*0490*/ FADD R13, -R13, R10 ; /* 0x0000000a0d0d7221 */
/* 0x008fc80000000100 */
/*04a0*/ FFMA R24, R13, R13, R24 ; /* 0x0000000d0d187223 */
/* 0x000fe40000000018 */
/*04b0*/ FADD R17, -R17, R14 ; /* 0x0000000e11117221 */
/* 0x010fc80000000100 */
/*04c0*/ FFMA R24, R17, R17, R24 ; /* 0x0000001111187223 */
/* 0x000fe40000000018 */
/*04d0*/ FADD R19, -R19, R16 ; /* 0x0000001013137221 */
/* 0x020fc80000000100 */
/*04e0*/ FFMA R24, R19, R19, R24 ; /* 0x0000001313187223 */
/* 0x000fe40000000018 */
/*04f0*/ FADD R23, -R20, R23 ; /* 0x0000001714177221 */
/* 0x000fc80000000100 */
/*0500*/ FFMA R24, R23, R23, R24 ; /* 0x0000001717187223 */
/* 0x000fe40000000018 */
/*0510*/ FADD R21, -R21, R18 ; /* 0x0000001215157221 */
/* 0x000fc80000000100 */
/*0520*/ FFMA R24, R21, R21, R24 ; /* 0x0000001515187223 */
/* 0x000fe40000000018 */
/*0530*/ FADD R25, -R25, R22 ; /* 0x0000001619197221 */
/* 0x000fc80000000100 */
/*0540*/ FFMA R24, R25, R25, R24 ; /* 0x0000001919187223 */
/* 0x000fe40000000018 */
/*0550*/ FADD R11, -R8, R11 ; /* 0x0000000b080b7221 */
/* 0x000fc80000000100 */
/*0560*/ FFMA R10, R11, R11, R24 ; /* 0x0000000b0b0a7223 */
/* 0x000fe20000000018 */
/*0570*/ @P0 BRA 0xf0 ; /* 0xfffffb7000000947 */
/* 0x000fea000383ffff */
/*0580*/ IADD3 R2, R10, -0xd000000, RZ ; /* 0xf30000000a027810 */
/* 0x000fe20007ffe0ff */
/*0590*/ MUFU.RSQ R9, R10 ; /* 0x0000000a00097308 */
/* 0x0000620000001400 */
/*05a0*/ BSSY B0, 0x670 ; /* 0x000000c000007945 */
/* 0x000fe40003800000 */
/*05b0*/ ISETP.GT.U32.AND P0, PT, R2, 0x727fffff, PT ; /* 0x727fffff0200780c */
/* 0x000fe20003f04070 */
/*05c0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fd800078e0207 */
/*05d0*/ @!P0 BRA 0x620 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*05e0*/ MOV R8, 0x600 ; /* 0x0000060000087802 */
/* 0x003fe40000000f00 */
/*05f0*/ CALL.REL.NOINC 0x690 ; /* 0x0000009000007944 */
/* 0x000fea0003c00000 */
/*0600*/ MOV R5, R0 ; /* 0x0000000000057202 */
/* 0x000fe20000000f00 */
/*0610*/ BRA 0x660 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0620*/ FMUL.FTZ R5, R10, R9 ; /* 0x000000090a057220 */
/* 0x003fe40000410000 */
/*0630*/ FMUL.FTZ R0, R9, 0.5 ; /* 0x3f00000009007820 */
/* 0x000fe40000410000 */
/*0640*/ FFMA R10, -R5, R5, R10 ; /* 0x00000005050a7223 */
/* 0x000fc8000000010a */
/*0650*/ FFMA R5, R10, R0, R5 ; /* 0x000000000a057223 */
/* 0x000fe40000000005 */
/*0660*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0670*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*0680*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0690*/ LOP3.LUT P0, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fda000780c0ff */
/*06a0*/ @!P0 MOV R0, R10 ; /* 0x0000000a00008202 */
/* 0x000fe20000000f00 */
/*06b0*/ @!P0 BRA 0x7c0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*06c0*/ FSETP.GEU.FTZ.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720b */
/* 0x000fda0003f1e000 */
/*06d0*/ @!P0 MOV R0, 0x7fffffff ; /* 0x7fffffff00008802 */
/* 0x000fe20000000f00 */
/*06e0*/ @!P0 BRA 0x7c0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*06f0*/ FSETP.GTU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fda0003f1c200 */
/*0700*/ @P0 FADD.FTZ R0, R10, 1 ; /* 0x3f8000000a000421 */
/* 0x000fe20000010000 */
/*0710*/ @P0 BRA 0x7c0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0720*/ FSETP.NEU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fda0003f1d200 */
/*0730*/ @P0 FFMA R4, R10, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000a040823 */
/* 0x000fc800000000ff */
/*0740*/ @P0 MUFU.RSQ R5, R4 ; /* 0x0000000400050308 */
/* 0x000e240000001400 */
/*0750*/ @P0 FMUL.FTZ R7, R4, R5 ; /* 0x0000000504070220 */
/* 0x001fe40000410000 */
/*0760*/ @P0 FMUL.FTZ R5, R5, 0.5 ; /* 0x3f00000005050820 */
/* 0x000fe40000410000 */
/*0770*/ @P0 FADD.FTZ R0, -R7, -RZ ; /* 0x800000ff07000221 */
/* 0x000fc80000010100 */
/*0780*/ @P0 FFMA R6, R7, R0, R4 ; /* 0x0000000007060223 */
/* 0x000fe20000000004 */
/*0790*/ @!P0 MOV R0, R10 ; /* 0x0000000a00008202 */
/* 0x000fc60000000f00 */
/*07a0*/ @P0 FFMA R5, R6, R5, R7 ; /* 0x0000000506050223 */
/* 0x000fc80000000007 */
/*07b0*/ @P0 FMUL.FTZ R0, R5, 2.3283064365386962891e-10 ; /* 0x2f80000005000820 */
/* 0x000fe40000410000 */
/*07c0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*07d0*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x000fca0000000f00 */
/*07e0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff81004007950 */
/* 0x000fea0003c3ffff */
/*07f0*/ BRA 0x7f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z24DistanceForBMUCalcBlocksPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe200000001ff */
/*0050*/ UMOV UR5, 0x2000 ; /* 0x0000200000057882 */
/* 0x000fe40000000000 */
/*0060*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0070*/ SHF.L.U32 R2, R0, 0xd, RZ ; /* 0x0000000d00027819 */
/* 0x001fca00000006ff */
/*0080*/ IMAD.WIDE.U32 R2, R2, R7, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0007 */
/*0090*/ IADD3 R4, P0, R2, 0x20, RZ ; /* 0x0000002002047810 */
/* 0x000fe40007f1e0ff */
/*00a0*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe40000000f00 */
/*00b0*/ IADD3.X R5, RZ, R3, RZ, P0, !PT ; /* 0x00000003ff057210 */
/* 0x000fe400007fe4ff */
/*00c0*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*00d0*/ LDG.E R12, [R2.64] ; /* 0x00000006020c7981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ LDG.E R13, [R4.64+-0x20] ; /* 0xffffe006040d7981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R24, [R2.64+0x4] ; /* 0x0000040602187981 */
/* 0x000ee8000c1e1900 */
/*0100*/ LDG.E R25, [R4.64+-0x1c] ; /* 0xffffe40604197981 */
/* 0x000ee8000c1e1900 */
/*0110*/ LDG.E R17, [R2.64+0x8] ; /* 0x0000080602117981 */
/* 0x000f28000c1e1900 */
/*0120*/ LDG.E R14, [R4.64+-0x18] ; /* 0xffffe806040e7981 */
/* 0x000f28000c1e1900 */
/*0130*/ LDG.E R16, [R2.64+0xc] ; /* 0x00000c0602107981 */
/* 0x000f68000c1e1900 */
/*0140*/ LDG.E R19, [R4.64+-0x14] ; /* 0xffffec0604137981 */
/* 0x000f68000c1e1900 */
/*0150*/ LDG.E R23, [R2.64+0x10] ; /* 0x0000100602177981 */
/* 0x000f68000c1e1900 */
/*0160*/ LDG.E R20, [R4.64+-0x10] ; /* 0xfffff00604147981 */
/* 0x000f68000c1e1900 */
/*0170*/ LDG.E R18, [R2.64+0x14] ; /* 0x0000140602127981 */
/* 0x000f68000c1e1900 */
/*0180*/ LDG.E R21, [R4.64+-0xc] ; /* 0xfffff40604157981 */
/* 0x000f68000c1e1900 */
/*0190*/ LDG.E R11, [R2.64+0x18] ; /* 0x00001806020b7981 */
/* 0x000f68000c1e1900 */
/*01a0*/ LDG.E R8, [R4.64+-0x8] ; /* 0xfffff80604087981 */
/* 0x000f68000c1e1900 */
/*01b0*/ LDG.E R6, [R2.64+0x1c] ; /* 0x00001c0602067981 */
/* 0x000f68000c1e1900 */
/*01c0*/ LDG.E R9, [R4.64+-0x4] ; /* 0xfffffc0604097981 */
/* 0x000f68000c1e1900 */
/*01d0*/ LDG.E R15, [R2.64+0x20] ; /* 0x00002006020f7981 */
/* 0x000162000c1e1900 */
/*01e0*/ FADD R13, -R12, R13 ; /* 0x0000000d0c0d7221 */
/* 0x004fc60000000100 */
/*01f0*/ LDG.E R12, [R4.64] ; /* 0x00000006040c7981 */
/* 0x0002a2000c1e1900 */
/*0200*/ FFMA R22, R13, R13, R10 ; /* 0x0000000d0d167223 */
/* 0x000fc6000000000a */
/*0210*/ LDG.E R13, [R2.64+0x24] ; /* 0x00002406020d7981 */
/* 0x0000a2000c1e1900 */
/*0220*/ FADD R25, -R24, R25 ; /* 0x0000001918197221 */
/* 0x008fc60000000100 */
/*0230*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000406040a7981 */
/* 0x0002e2000c1e1900 */
/*0240*/ FFMA R22, R25, R25, R22 ; /* 0x0000001919167223 */
/* 0x000fe40000000016 */
/*0250*/ FADD R25, -R17, R14 ; /* 0x0000000e11197221 */
/* 0x010fe40000000100 */
/*0260*/ LDG.E R17, [R2.64+0x28] ; /* 0x0000280602117981 */
/* 0x000124000c1e1900 */
/*0270*/ FFMA R22, R25, R25, R22 ; /* 0x0000001919167223 */
/* 0x000fe40000000016 */
/*0280*/ LDG.E R14, [R4.64+0x8] ; /* 0x00000806040e7981 */
/* 0x000322000c1e1900 */
/*0290*/ FADD R25, -R16, R19 ; /* 0x0000001310197221 */
/* 0x020fc60000000100 */
/*02a0*/ LDG.E R19, [R2.64+0x2c] ; /* 0x00002c0602137981 */
/* 0x000162000c1e1900 */
/*02b0*/ FFMA R22, R25, R25, R22 ; /* 0x0000001919167223 */
/* 0x000fc60000000016 */
/*02c0*/ LDG.E R16, [R4.64+0xc] ; /* 0x00000c0604107981 */
/* 0x000362000c1e1900 */
/*02d0*/ FADD R25, -R23, R20 ; /* 0x0000001417197221 */
/* 0x000fc60000000100 */
/*02e0*/ LDG.E R20, [R2.64+0x30] ; /* 0x0000300602147981 */
/* 0x000162000c1e1900 */
/*02f0*/ FFMA R22, R25, R25, R22 ; /* 0x0000001919167223 */
/* 0x000fc60000000016 */
/*0300*/ LDG.E R23, [R4.64+0x10] ; /* 0x0000100604177981 */
/* 0x000362000c1e1900 */
/*0310*/ FADD R25, -R18, R21 ; /* 0x0000001512197221 */
/* 0x000fc60000000100 */
/*0320*/ LDG.E R21, [R2.64+0x34] ; /* 0x0000340602157981 */
/* 0x000168000c1e1900 */
/*0330*/ LDG.E R18, [R4.64+0x14] ; /* 0x0000140604127981 */
/* 0x000362000c1e1900 */
/*0340*/ FFMA R24, R25, R25, R22 ; /* 0x0000001919187223 */
/* 0x000fc60000000016 */
/*0350*/ LDG.E R25, [R2.64+0x38] ; /* 0x0000380602197981 */
/* 0x000162000c1e1900 */
/*0360*/ FADD R27, -R11, R8 ; /* 0x000000080b1b7221 */
/* 0x000fc60000000100 */
/*0370*/ LDG.E R22, [R4.64+0x18] ; /* 0x0000180604167981 */
/* 0x000368000c1e1900 */
/*0380*/ LDG.E R8, [R2.64+0x3c] ; /* 0x00003c0602087981 */
/* 0x000168000c1e1900 */
/*0390*/ LDG.E R11, [R4.64+0x1c] ; /* 0x00001c06040b7981 */
/* 0x000362000c1e1900 */
/*03a0*/ FFMA R24, R27, R27, R24 ; /* 0x0000001b1b187223 */
/* 0x000fe40000000018 */
/*03b0*/ FADD R9, -R6, R9 ; /* 0x0000000906097221 */
/* 0x000fc80000000100 */
/*03c0*/ FFMA R24, R9, R9, R24 ; /* 0x0000000909187223 */
/* 0x000fe20000000018 */
/*03d0*/ UIADD3 UR5, UP0, UR5, -0x10, URZ ; /* 0xfffffff005057890 */
/* 0x000fc8000ff1e03f */
/*03e0*/ UIADD3.X UR4, UR4, -0x1, URZ, UP0, !UPT ; /* 0xffffffff04047890 */
/* 0x000fe400087fe43f */
/*03f0*/ ISETP.NE.U32.AND P0, PT, RZ, UR5, PT ; /* 0x00000005ff007c0c */
/* 0x000fc8000bf05070 */
/*0400*/ ISETP.NE.AND.EX P0, PT, RZ, UR4, PT, P0 ; /* 0x00000004ff007c0c */
/* 0x000fe4000bf05300 */
/*0410*/ IADD3 R4, P1, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x002fe40007f3e0ff */
/*0420*/ IADD3 R2, P2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x001fe40007f5e0ff */
/*0430*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe40000ffe4ff */
/*0440*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x000fe200017fe4ff */
/*0450*/ FADD R15, -R15, R12 ; /* 0x0000000c0f0f7221 */
/* 0x004fc80000000100 */
/*0460*/ FFMA R24, R15, R15, R24 ; /* 0x0000000f0f187223 */
/* 0x000fe40000000018 */
/*0470*/ FADD R13, -R13, R10 ; /* 0x0000000a0d0d7221 */
/* 0x008fc80000000100 */
/*0480*/ FFMA R24, R13, R13, R24 ; /* 0x0000000d0d187223 */
/* 0x000fe40000000018 */
/*0490*/ FADD R17, -R17, R14 ; /* 0x0000000e11117221 */
/* 0x010fc80000000100 */
/*04a0*/ FFMA R24, R17, R17, R24 ; /* 0x0000001111187223 */
/* 0x000fe40000000018 */
/*04b0*/ FADD R19, -R19, R16 ; /* 0x0000001013137221 */
/* 0x020fc80000000100 */
/*04c0*/ FFMA R24, R19, R19, R24 ; /* 0x0000001313187223 */
/* 0x000fe40000000018 */
/*04d0*/ FADD R23, -R20, R23 ; /* 0x0000001714177221 */
/* 0x000fc80000000100 */
/*04e0*/ FFMA R24, R23, R23, R24 ; /* 0x0000001717187223 */
/* 0x000fe40000000018 */
/*04f0*/ FADD R21, -R21, R18 ; /* 0x0000001215157221 */
/* 0x000fc80000000100 */
/*0500*/ FFMA R24, R21, R21, R24 ; /* 0x0000001515187223 */
/* 0x000fe40000000018 */
/*0510*/ FADD R25, -R25, R22 ; /* 0x0000001619197221 */
/* 0x000fc80000000100 */
/*0520*/ FFMA R24, R25, R25, R24 ; /* 0x0000001919187223 */
/* 0x000fe40000000018 */
/*0530*/ FADD R11, -R8, R11 ; /* 0x0000000b080b7221 */
/* 0x000fc80000000100 */
/*0540*/ FFMA R10, R11, R11, R24 ; /* 0x0000000b0b0a7223 */
/* 0x000fe20000000018 */
/*0550*/ @P0 BRA 0xd0 ; /* 0xfffffb7000000947 */
/* 0x000fea000383ffff */
/*0560*/ IADD3 R2, R10, -0xd000000, RZ ; /* 0xf30000000a027810 */
/* 0x000fe20007ffe0ff */
/*0570*/ MUFU.RSQ R9, R10 ; /* 0x0000000a00097308 */
/* 0x0000660000001400 */
/*0580*/ ISETP.GT.U32.AND P0, PT, R2, 0x727fffff, PT ; /* 0x727fffff0200780c */
/* 0x000fe20003f04070 */
/*0590*/ IMAD.WIDE.U32 R2, R0, R7, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fd800078e0007 */
/*05a0*/ @!P0 BRA 0x5f0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*05b0*/ MOV R4, 0x5d0 ; /* 0x000005d000047802 */
/* 0x003fe40000000f00 */
/*05c0*/ CALL.REL.NOINC 0x650 ; /* 0x0000008000007944 */
/* 0x000fea0003c00000 */
/*05d0*/ MOV R5, R0 ; /* 0x0000000000057202 */
/* 0x000fe20000000f00 */
/*05e0*/ BRA 0x630 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*05f0*/ FMUL.FTZ R5, R10, R9 ; /* 0x000000090a057220 */
/* 0x003fe40000410000 */
/*0600*/ FMUL.FTZ R0, R9, 0.5 ; /* 0x3f00000009007820 */
/* 0x000fe40000410000 */
/*0610*/ FFMA R10, -R5, R5, R10 ; /* 0x00000005050a7223 */
/* 0x000fc8000000010a */
/*0620*/ FFMA R5, R10, R0, R5 ; /* 0x000000000a057223 */
/* 0x000fca0000000005 */
/*0630*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*0640*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0650*/ LOP3.LUT P0, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fda000780c0ff */
/*0660*/ @!P0 MOV R0, R10 ; /* 0x0000000a00008202 */
/* 0x000fe20000000f00 */
/*0670*/ @!P0 BRA 0x790 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0680*/ FSETP.GEU.FTZ.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720b */
/* 0x000fda0003f1e000 */
/*0690*/ @!P0 MOV R0, 0x7fffffff ; /* 0x7fffffff00008802 */
/* 0x000fe20000000f00 */
/*06a0*/ @!P0 BRA 0x790 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*06b0*/ FSETP.GTU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fda0003f1c200 */
/*06c0*/ @P0 FADD.FTZ R0, R10, 1 ; /* 0x3f8000000a000421 */
/* 0x000fe20000010000 */
/*06d0*/ @P0 BRA 0x790 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*06e0*/ FSETP.NEU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fda0003f1d200 */
/*06f0*/ @!P0 MOV R0, R10 ; /* 0x0000000a00008202 */
/* 0x000fe20000000f00 */
/*0700*/ @!P0 BRA 0x790 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0710*/ FFMA R10, R10, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000a0a7823 */
/* 0x000fc800000000ff */
/*0720*/ MUFU.RSQ R5, R10 ; /* 0x0000000a00057308 */
/* 0x000e240000001400 */
/*0730*/ FMUL.FTZ R7, R10, R5 ; /* 0x000000050a077220 */
/* 0x001fe40000410000 */
/*0740*/ FMUL.FTZ R5, R5, 0.5 ; /* 0x3f00000005057820 */
/* 0x000fe40000410000 */
/*0750*/ FADD.FTZ R0, -R7, -RZ ; /* 0x800000ff07007221 */
/* 0x000fc80000010100 */
/*0760*/ FFMA R0, R7, R0, R10 ; /* 0x0000000007007223 */
/* 0x000fc8000000000a */
/*0770*/ FFMA R0, R0, R5, R7 ; /* 0x0000000500007223 */
/* 0x000fc80000000007 */
/*0780*/ FMUL.FTZ R0, R0, 2.3283064365386962891e-10 ; /* 0x2f80000000007820 */
/* 0x000fe40000410000 */
/*0790*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fcc00000001ff */
/*07a0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff85004007950 */
/* 0x000fea0003c3ffff */
/*07b0*/ BRA 0x7b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <time.h>
#include <iostream>
#include <math.h>
#include <vector>
#include <stdio.h>
#include <stdlib.h>
#include <chrono>
using namespace std;
using namespace std::chrono;
#define W (8192)
#define N (8192)
#define THREADS_PER_BLOCK (1)
#define NUMBER_BLOCKS (N/THREADS_PER_BLOCK)
typedef float myFloat;
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true){
if (code != cudaSuccess){
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void DistanceForBMUCalcBlocks(myFloat *input, myFloat *v, myFloat *x){
myFloat d = 0;
for(long long int i = 0; i < W; i++){
d += (v[i+W*blockIdx.x] - input[i]) * (v[blockIdx.x*W+i] - input[i]);
}
x[blockIdx.x] = sqrt(d);
}
__global__ void DistanceForBMUCalcBlocksAndThreads(myFloat *input, myFloat *v, myFloat *x){
myFloat d = 0;
int index = threadIdx.x + blockIdx.x * blockDim.x;
for(long long int i = 0; i < W; i++){
d += (v[i+W*index] - input[i]) * (v[index*W+i] - input[i]);
}
x[index] = sqrt(d);
}
int main(int argc, char* argv[]){
steady_clock::time_point t_i = steady_clock::now();
srand(0);
myFloat *v;
myFloat *d_v;
long long int size = N*W * sizeof(myFloat);
long long int d_vSize = N*W * sizeof(myFloat);
gpuErrchk(cudaMalloc((void **)&d_v, d_vSize));
v = (myFloat *)malloc(size);
for(int i = 0; i < N*W; i++){
v[i] = rand();
}
myFloat *distances;
myFloat *d_distances;
long long int distanceArraySize = N * sizeof(myFloat);
gpuErrchk(cudaMalloc((void **)&d_distances, distanceArraySize));
distances = (myFloat *)malloc(distanceArraySize);
myFloat *training;
myFloat *d_training;
long long int trainingSize = W * sizeof(myFloat);
gpuErrchk(cudaMalloc((void **)&d_training, trainingSize));
training = (myFloat *)malloc(trainingSize);
int index = 0;
for(int i = 0; i < W; i++){
training[i] = rand();
}
steady_clock::time_point workI = steady_clock::now();
for(int i = 0; i < 1; i++){
//steady_clock::time_point t_CPUToGPUI = steady_clock::now();
gpuErrchk(cudaMemcpy(d_v, v, size, cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(d_training, training, trainingSize, cudaMemcpyHostToDevice));
//int t_CPUToGPUF = time(NULL);
//cout<<"Finished copying to device "<<t_CPUToGPUF - t_CPUToGPUI<<endl;
//DistanceForBMUCalcBlocks<<<NUMBER_BLOCKS, THREADS_PER_BLOCK>>>(d_training, d_v, d_distances);
DistanceForBMUCalcBlocksAndThreads<<<NUMBER_BLOCKS, THREADS_PER_BLOCK>>>(d_training, d_v, d_distances);
cudaThreadSynchronize();
//cout<<"Finished distance calc"<<endl;
//int t_GPUToCPUI = time(NULL);
gpuErrchk(cudaMemcpy(distances, d_distances, distanceArraySize, cudaMemcpyDeviceToHost));
//int t_GPUToCPUF = time(NULL);
//cout<<"Finished Device to CPU copy "<<t_GPUToCPUF - t_GPUToCPUI<<endl;
myFloat dmin = distances[0];
for(int j = 0; j < N; j++){
if(distances[j] < dmin){
dmin = distances[j];
index = j;
}
}
}
steady_clock::time_point workF = steady_clock::now();
cout<<"Total work execution time "<<duration_cast<milliseconds>(workF - workI).count()<<endl;
cout<<"BMU is "<<index<<endl;
steady_clock::time_point t_f = steady_clock::now();
cout<<"Total Execution Time: "<<duration_cast<milliseconds>(t_f - t_i).count()<<endl;
} | .file "tmpxft_0011f97e_00000000-6_bmuGPUOuterTest.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4137:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4137:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB4131:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE4131:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z48__device_stub__Z24DistanceForBMUCalcBlocksPfS_S_PfS_S_
.type _Z48__device_stub__Z24DistanceForBMUCalcBlocksPfS_S_PfS_S_, @function
_Z48__device_stub__Z24DistanceForBMUCalcBlocksPfS_S_PfS_S_:
.LFB4159:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24DistanceForBMUCalcBlocksPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4159:
.size _Z48__device_stub__Z24DistanceForBMUCalcBlocksPfS_S_PfS_S_, .-_Z48__device_stub__Z24DistanceForBMUCalcBlocksPfS_S_PfS_S_
.globl _Z24DistanceForBMUCalcBlocksPfS_S_
.type _Z24DistanceForBMUCalcBlocksPfS_S_, @function
_Z24DistanceForBMUCalcBlocksPfS_S_:
.LFB4160:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z24DistanceForBMUCalcBlocksPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4160:
.size _Z24DistanceForBMUCalcBlocksPfS_S_, .-_Z24DistanceForBMUCalcBlocksPfS_S_
.globl _Z58__device_stub__Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_PfS_S_
.type _Z58__device_stub__Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_PfS_S_, @function
_Z58__device_stub__Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_PfS_S_:
.LFB4161:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4161:
.size _Z58__device_stub__Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_PfS_S_, .-_Z58__device_stub__Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_PfS_S_
.globl _Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_
.type _Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_, @function
_Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_:
.LFB4162:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z58__device_stub__Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4162:
.size _Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_, .-_Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/CarlyWilson/CUDA-Testing/master/benchMarking/gpuTestOuterLoop/bmuGPUOuterTest.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Total work execution time "
.LC3:
.string "BMU is "
.LC4:
.string "Total Execution Time: "
.text
.globl main
.type main, @function
main:
.LFB4132:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
movq %rax, %rbp
movl $0, %edi
call srand@PLT
leaq 8(%rsp), %rdi
movl $268435456, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $54, %edx
leaq .LC1(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $268435456, %edi
call malloc@PLT
movq %rax, %r13
movq %rax, %rbx
leaq 268435456(%rax), %r12
.L28:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L28
leaq 16(%rsp), %rdi
movl $32768, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $64, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $32768, %edi
call malloc@PLT
movq %rax, %r12
leaq 24(%rsp), %rdi
movl $32768, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $70, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $32768, %edi
call malloc@PLT
movq %rax, %r15
movq %rax, %rbx
leaq 32768(%rax), %r14
.L29:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %r14, %rbx
jne .L29
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
movq %rax, %r14
movl $1, %ecx
movl $268435456, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $82, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movl $32768, %edx
movq %r15, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $84, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $8192, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L30:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $32768, %edx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $97, %edx
leaq .LC1(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movss (%r12), %xmm0
movl $0, %eax
movl $0, %ebx
.L33:
movss (%r12,%rax,4), %xmm1
comiss %xmm1, %xmm0
cmova %eax, %ebx
minss %xmm0, %xmm1
movaps %xmm1, %xmm0
addq $1, %rax
cmpq $8192, %rax
jne .L33
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
movq %rax, %r12
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r12, %rcx
subq %r14, %rcx
movabsq $4835703278458516699, %r12
movq %rcx, %rax
imulq %r12
sarq $18, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC3(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
movq %rax, %rbx
leaq .LC4(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %rcx
subq %rbp, %rcx
movq %rcx, %rax
imulq %r12
sarq $18, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z58__device_stub__Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_PfS_S_
jmp .L30
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4132:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC5:
.string "_Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_"
.align 8
.LC6:
.string "_Z24DistanceForBMUCalcBlocksPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4164:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z24DistanceForBMUCalcBlocksPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4164:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <time.h>
#include <iostream>
#include <math.h>
#include <vector>
#include <stdio.h>
#include <stdlib.h>
#include <chrono>
using namespace std;
using namespace std::chrono;
#define W (8192)
#define N (8192)
#define THREADS_PER_BLOCK (1)
#define NUMBER_BLOCKS (N/THREADS_PER_BLOCK)
typedef float myFloat;
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true){
if (code != cudaSuccess){
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void DistanceForBMUCalcBlocks(myFloat *input, myFloat *v, myFloat *x){
myFloat d = 0;
for(long long int i = 0; i < W; i++){
d += (v[i+W*blockIdx.x] - input[i]) * (v[blockIdx.x*W+i] - input[i]);
}
x[blockIdx.x] = sqrt(d);
}
__global__ void DistanceForBMUCalcBlocksAndThreads(myFloat *input, myFloat *v, myFloat *x){
myFloat d = 0;
int index = threadIdx.x + blockIdx.x * blockDim.x;
for(long long int i = 0; i < W; i++){
d += (v[i+W*index] - input[i]) * (v[index*W+i] - input[i]);
}
x[index] = sqrt(d);
}
int main(int argc, char* argv[]){
steady_clock::time_point t_i = steady_clock::now();
srand(0);
myFloat *v;
myFloat *d_v;
long long int size = N*W * sizeof(myFloat);
long long int d_vSize = N*W * sizeof(myFloat);
gpuErrchk(cudaMalloc((void **)&d_v, d_vSize));
v = (myFloat *)malloc(size);
for(int i = 0; i < N*W; i++){
v[i] = rand();
}
myFloat *distances;
myFloat *d_distances;
long long int distanceArraySize = N * sizeof(myFloat);
gpuErrchk(cudaMalloc((void **)&d_distances, distanceArraySize));
distances = (myFloat *)malloc(distanceArraySize);
myFloat *training;
myFloat *d_training;
long long int trainingSize = W * sizeof(myFloat);
gpuErrchk(cudaMalloc((void **)&d_training, trainingSize));
training = (myFloat *)malloc(trainingSize);
int index = 0;
for(int i = 0; i < W; i++){
training[i] = rand();
}
steady_clock::time_point workI = steady_clock::now();
for(int i = 0; i < 1; i++){
//steady_clock::time_point t_CPUToGPUI = steady_clock::now();
gpuErrchk(cudaMemcpy(d_v, v, size, cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(d_training, training, trainingSize, cudaMemcpyHostToDevice));
//int t_CPUToGPUF = time(NULL);
//cout<<"Finished copying to device "<<t_CPUToGPUF - t_CPUToGPUI<<endl;
//DistanceForBMUCalcBlocks<<<NUMBER_BLOCKS, THREADS_PER_BLOCK>>>(d_training, d_v, d_distances);
DistanceForBMUCalcBlocksAndThreads<<<NUMBER_BLOCKS, THREADS_PER_BLOCK>>>(d_training, d_v, d_distances);
cudaThreadSynchronize();
//cout<<"Finished distance calc"<<endl;
//int t_GPUToCPUI = time(NULL);
gpuErrchk(cudaMemcpy(distances, d_distances, distanceArraySize, cudaMemcpyDeviceToHost));
//int t_GPUToCPUF = time(NULL);
//cout<<"Finished Device to CPU copy "<<t_GPUToCPUF - t_GPUToCPUI<<endl;
myFloat dmin = distances[0];
for(int j = 0; j < N; j++){
if(distances[j] < dmin){
dmin = distances[j];
index = j;
}
}
}
steady_clock::time_point workF = steady_clock::now();
cout<<"Total work execution time "<<duration_cast<milliseconds>(workF - workI).count()<<endl;
cout<<"BMU is "<<index<<endl;
steady_clock::time_point t_f = steady_clock::now();
cout<<"Total Execution Time: "<<duration_cast<milliseconds>(t_f - t_i).count()<<endl;
} | #include <hip/hip_runtime.h>
#include <time.h>
#include <iostream>
#include <math.h>
#include <vector>
#include <stdio.h>
#include <stdlib.h>
#include <chrono>
using namespace std;
using namespace std::chrono;
#define W (8192)
#define N (8192)
#define THREADS_PER_BLOCK (1)
#define NUMBER_BLOCKS (N/THREADS_PER_BLOCK)
typedef float myFloat;
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true){
if (code != hipSuccess){
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void DistanceForBMUCalcBlocks(myFloat *input, myFloat *v, myFloat *x){
myFloat d = 0;
for(long long int i = 0; i < W; i++){
d += (v[i+W*blockIdx.x] - input[i]) * (v[blockIdx.x*W+i] - input[i]);
}
x[blockIdx.x] = sqrt(d);
}
__global__ void DistanceForBMUCalcBlocksAndThreads(myFloat *input, myFloat *v, myFloat *x){
myFloat d = 0;
int index = threadIdx.x + blockIdx.x * blockDim.x;
for(long long int i = 0; i < W; i++){
d += (v[i+W*index] - input[i]) * (v[index*W+i] - input[i]);
}
x[index] = sqrt(d);
}
int main(int argc, char* argv[]){
steady_clock::time_point t_i = steady_clock::now();
srand(0);
myFloat *v;
myFloat *d_v;
long long int size = N*W * sizeof(myFloat);
long long int d_vSize = N*W * sizeof(myFloat);
gpuErrchk(hipMalloc((void **)&d_v, d_vSize));
v = (myFloat *)malloc(size);
for(int i = 0; i < N*W; i++){
v[i] = rand();
}
myFloat *distances;
myFloat *d_distances;
long long int distanceArraySize = N * sizeof(myFloat);
gpuErrchk(hipMalloc((void **)&d_distances, distanceArraySize));
distances = (myFloat *)malloc(distanceArraySize);
myFloat *training;
myFloat *d_training;
long long int trainingSize = W * sizeof(myFloat);
gpuErrchk(hipMalloc((void **)&d_training, trainingSize));
training = (myFloat *)malloc(trainingSize);
int index = 0;
for(int i = 0; i < W; i++){
training[i] = rand();
}
steady_clock::time_point workI = steady_clock::now();
for(int i = 0; i < 1; i++){
//steady_clock::time_point t_CPUToGPUI = steady_clock::now();
gpuErrchk(hipMemcpy(d_v, v, size, hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(d_training, training, trainingSize, hipMemcpyHostToDevice));
//int t_CPUToGPUF = time(NULL);
//cout<<"Finished copying to device "<<t_CPUToGPUF - t_CPUToGPUI<<endl;
//DistanceForBMUCalcBlocks<<<NUMBER_BLOCKS, THREADS_PER_BLOCK>>>(d_training, d_v, d_distances);
DistanceForBMUCalcBlocksAndThreads<<<NUMBER_BLOCKS, THREADS_PER_BLOCK>>>(d_training, d_v, d_distances);
hipDeviceSynchronize();
//cout<<"Finished distance calc"<<endl;
//int t_GPUToCPUI = time(NULL);
gpuErrchk(hipMemcpy(distances, d_distances, distanceArraySize, hipMemcpyDeviceToHost));
//int t_GPUToCPUF = time(NULL);
//cout<<"Finished Device to CPU copy "<<t_GPUToCPUF - t_GPUToCPUI<<endl;
myFloat dmin = distances[0];
for(int j = 0; j < N; j++){
if(distances[j] < dmin){
dmin = distances[j];
index = j;
}
}
}
steady_clock::time_point workF = steady_clock::now();
cout<<"Total work execution time "<<duration_cast<milliseconds>(workF - workI).count()<<endl;
cout<<"BMU is "<<index<<endl;
steady_clock::time_point t_f = steady_clock::now();
cout<<"Total Execution Time: "<<duration_cast<milliseconds>(t_f - t_i).count()<<endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <time.h>
#include <iostream>
#include <math.h>
#include <vector>
#include <stdio.h>
#include <stdlib.h>
#include <chrono>
using namespace std;
using namespace std::chrono;
#define W (8192)
#define N (8192)
#define THREADS_PER_BLOCK (1)
#define NUMBER_BLOCKS (N/THREADS_PER_BLOCK)
typedef float myFloat;
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true){
if (code != hipSuccess){
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void DistanceForBMUCalcBlocks(myFloat *input, myFloat *v, myFloat *x){
myFloat d = 0;
for(long long int i = 0; i < W; i++){
d += (v[i+W*blockIdx.x] - input[i]) * (v[blockIdx.x*W+i] - input[i]);
}
x[blockIdx.x] = sqrt(d);
}
__global__ void DistanceForBMUCalcBlocksAndThreads(myFloat *input, myFloat *v, myFloat *x){
myFloat d = 0;
int index = threadIdx.x + blockIdx.x * blockDim.x;
for(long long int i = 0; i < W; i++){
d += (v[i+W*index] - input[i]) * (v[index*W+i] - input[i]);
}
x[index] = sqrt(d);
}
int main(int argc, char* argv[]){
steady_clock::time_point t_i = steady_clock::now();
srand(0);
myFloat *v;
myFloat *d_v;
long long int size = N*W * sizeof(myFloat);
long long int d_vSize = N*W * sizeof(myFloat);
gpuErrchk(hipMalloc((void **)&d_v, d_vSize));
v = (myFloat *)malloc(size);
for(int i = 0; i < N*W; i++){
v[i] = rand();
}
myFloat *distances;
myFloat *d_distances;
long long int distanceArraySize = N * sizeof(myFloat);
gpuErrchk(hipMalloc((void **)&d_distances, distanceArraySize));
distances = (myFloat *)malloc(distanceArraySize);
myFloat *training;
myFloat *d_training;
long long int trainingSize = W * sizeof(myFloat);
gpuErrchk(hipMalloc((void **)&d_training, trainingSize));
training = (myFloat *)malloc(trainingSize);
int index = 0;
for(int i = 0; i < W; i++){
training[i] = rand();
}
steady_clock::time_point workI = steady_clock::now();
for(int i = 0; i < 1; i++){
//steady_clock::time_point t_CPUToGPUI = steady_clock::now();
gpuErrchk(hipMemcpy(d_v, v, size, hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(d_training, training, trainingSize, hipMemcpyHostToDevice));
//int t_CPUToGPUF = time(NULL);
//cout<<"Finished copying to device "<<t_CPUToGPUF - t_CPUToGPUI<<endl;
//DistanceForBMUCalcBlocks<<<NUMBER_BLOCKS, THREADS_PER_BLOCK>>>(d_training, d_v, d_distances);
DistanceForBMUCalcBlocksAndThreads<<<NUMBER_BLOCKS, THREADS_PER_BLOCK>>>(d_training, d_v, d_distances);
hipDeviceSynchronize();
//cout<<"Finished distance calc"<<endl;
//int t_GPUToCPUI = time(NULL);
gpuErrchk(hipMemcpy(distances, d_distances, distanceArraySize, hipMemcpyDeviceToHost));
//int t_GPUToCPUF = time(NULL);
//cout<<"Finished Device to CPU copy "<<t_GPUToCPUF - t_GPUToCPUI<<endl;
myFloat dmin = distances[0];
for(int j = 0; j < N; j++){
if(distances[j] < dmin){
dmin = distances[j];
index = j;
}
}
}
steady_clock::time_point workF = steady_clock::now();
cout<<"Total work execution time "<<duration_cast<milliseconds>(workF - workI).count()<<endl;
cout<<"BMU is "<<index<<endl;
steady_clock::time_point t_f = steady_clock::now();
cout<<"Total Execution Time: "<<duration_cast<milliseconds>(t_f - t_i).count()<<endl;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24DistanceForBMUCalcBlocksPfS_S_
.globl _Z24DistanceForBMUCalcBlocksPfS_S_
.p2align 8
.type _Z24DistanceForBMUCalcBlocksPfS_S_,@function
_Z24DistanceForBMUCalcBlocksPfS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s3, 0
s_lshl_b32 s2, s15, 13
v_mov_b32_e32 v0, 0
s_lshl_b64 s[2:3], s[2:3], 2
s_mov_b32 s8, s15
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_mov_b64 s[2:3], 0
.LBB0_1:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s10, s6, s2
s_addc_u32 s11, s7, s3
s_add_u32 s12, s4, s2
s_addc_u32 s13, s5, s3
s_load_b32 s9, s[10:11], 0x0
s_load_b32 s10, s[12:13], 0x0
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_eq_u64 s[2:3], 0x8000
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v1, s9, s10
v_fmac_f32_e32 v0, v1, v1
s_cbranch_scc0 .LBB0_1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_f32_e32 v1, 0x4f800000, v0
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
s_mov_b32 s9, 0
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v1, v0
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v2, -1, v1
v_add_nc_u32_e32 v3, 1, v1
v_fma_f32 v4, -v2, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, -v3, v1, v0
v_cmp_ge_f32_e64 s2, 0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v1, v1, v2, s2
s_load_b64 s[2:3], s[0:1], 0x10
v_cmp_lt_f32_e64 s0, 0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v1, v1, v3, s0
s_lshl_b64 s[0:1], s[8:9], 2
v_mul_f32_e32 v2, 0x37800000, v1
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v2, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v0, 0x260
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
v_dual_cndmask_b32 v0, v1, v0 :: v_dual_mov_b32 v1, 0
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24DistanceForBMUCalcBlocksPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24DistanceForBMUCalcBlocksPfS_S_, .Lfunc_end0-_Z24DistanceForBMUCalcBlocksPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_
.globl _Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_
.p2align 8
.type _Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_,@function
_Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v0, 0
s_mov_b64 s[2:3], 0
v_lshlrev_b32_e32 v2, 13, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
.LBB1_1:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, v2, s2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
s_add_u32 s6, s4, s2
s_addc_u32 s7, s5, s3
s_add_u32 s2, s2, 4
global_load_b32 v4, v[4:5], off
s_load_b32 s6, s[6:7], 0x0
s_addc_u32 s3, s3, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_eq_u64 s[2:3], 0x8000
s_waitcnt vmcnt(0) lgkmcnt(0)
v_subrev_f32_e32 v4, s6, v4
v_fmac_f32_e32 v0, v4, v4
s_cbranch_scc0 .LBB1_1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v2, 0x4f800000, v0
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
v_cndmask_b32_e32 v3, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v0, v3
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v2, -1, v0
v_add_nc_u32_e32 v4, 1, v0
v_fma_f32 v5, -v2, v0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v4, v0, v3
v_cmp_ge_f32_e64 s2, 0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v0, v0, v2, s2
s_load_b64 s[2:3], s[0:1], 0x10
v_cmp_lt_f32_e64 s0, 0, v6
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v0, v0, v4, s0
v_mul_f32_e32 v4, 0x37800000, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v4, v0, v4, vcc_lo
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_cmp_class_f32_e64 vcc_lo, v3, 0x260
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, v4, v3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_, .Lfunc_end1-_Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24DistanceForBMUCalcBlocksPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24DistanceForBMUCalcBlocksPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <time.h>
#include <iostream>
#include <math.h>
#include <vector>
#include <stdio.h>
#include <stdlib.h>
#include <chrono>
using namespace std;
using namespace std::chrono;
#define W (8192)
#define N (8192)
#define THREADS_PER_BLOCK (1)
#define NUMBER_BLOCKS (N/THREADS_PER_BLOCK)
typedef float myFloat;
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true){
if (code != hipSuccess){
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void DistanceForBMUCalcBlocks(myFloat *input, myFloat *v, myFloat *x){
myFloat d = 0;
for(long long int i = 0; i < W; i++){
d += (v[i+W*blockIdx.x] - input[i]) * (v[blockIdx.x*W+i] - input[i]);
}
x[blockIdx.x] = sqrt(d);
}
__global__ void DistanceForBMUCalcBlocksAndThreads(myFloat *input, myFloat *v, myFloat *x){
myFloat d = 0;
int index = threadIdx.x + blockIdx.x * blockDim.x;
for(long long int i = 0; i < W; i++){
d += (v[i+W*index] - input[i]) * (v[index*W+i] - input[i]);
}
x[index] = sqrt(d);
}
int main(int argc, char* argv[]){
steady_clock::time_point t_i = steady_clock::now();
srand(0);
myFloat *v;
myFloat *d_v;
long long int size = N*W * sizeof(myFloat);
long long int d_vSize = N*W * sizeof(myFloat);
gpuErrchk(hipMalloc((void **)&d_v, d_vSize));
v = (myFloat *)malloc(size);
for(int i = 0; i < N*W; i++){
v[i] = rand();
}
myFloat *distances;
myFloat *d_distances;
long long int distanceArraySize = N * sizeof(myFloat);
gpuErrchk(hipMalloc((void **)&d_distances, distanceArraySize));
distances = (myFloat *)malloc(distanceArraySize);
myFloat *training;
myFloat *d_training;
long long int trainingSize = W * sizeof(myFloat);
gpuErrchk(hipMalloc((void **)&d_training, trainingSize));
training = (myFloat *)malloc(trainingSize);
int index = 0;
for(int i = 0; i < W; i++){
training[i] = rand();
}
steady_clock::time_point workI = steady_clock::now();
for(int i = 0; i < 1; i++){
//steady_clock::time_point t_CPUToGPUI = steady_clock::now();
gpuErrchk(hipMemcpy(d_v, v, size, hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(d_training, training, trainingSize, hipMemcpyHostToDevice));
//int t_CPUToGPUF = time(NULL);
//cout<<"Finished copying to device "<<t_CPUToGPUF - t_CPUToGPUI<<endl;
//DistanceForBMUCalcBlocks<<<NUMBER_BLOCKS, THREADS_PER_BLOCK>>>(d_training, d_v, d_distances);
DistanceForBMUCalcBlocksAndThreads<<<NUMBER_BLOCKS, THREADS_PER_BLOCK>>>(d_training, d_v, d_distances);
hipDeviceSynchronize();
//cout<<"Finished distance calc"<<endl;
//int t_GPUToCPUI = time(NULL);
gpuErrchk(hipMemcpy(distances, d_distances, distanceArraySize, hipMemcpyDeviceToHost));
//int t_GPUToCPUF = time(NULL);
//cout<<"Finished Device to CPU copy "<<t_GPUToCPUF - t_GPUToCPUI<<endl;
myFloat dmin = distances[0];
for(int j = 0; j < N; j++){
if(distances[j] < dmin){
dmin = distances[j];
index = j;
}
}
}
steady_clock::time_point workF = steady_clock::now();
cout<<"Total work execution time "<<duration_cast<milliseconds>(workF - workI).count()<<endl;
cout<<"BMU is "<<index<<endl;
steady_clock::time_point t_f = steady_clock::now();
cout<<"Total Execution Time: "<<duration_cast<milliseconds>(t_f - t_i).count()<<endl;
} | .text
.file "bmuGPUOuterTest.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z39__device_stub__DistanceForBMUCalcBlocksPfS_S_ # -- Begin function _Z39__device_stub__DistanceForBMUCalcBlocksPfS_S_
.p2align 4, 0x90
.type _Z39__device_stub__DistanceForBMUCalcBlocksPfS_S_,@function
_Z39__device_stub__DistanceForBMUCalcBlocksPfS_S_: # @_Z39__device_stub__DistanceForBMUCalcBlocksPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24DistanceForBMUCalcBlocksPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z39__device_stub__DistanceForBMUCalcBlocksPfS_S_, .Lfunc_end0-_Z39__device_stub__DistanceForBMUCalcBlocksPfS_S_
.cfi_endproc
# -- End function
.globl _Z49__device_stub__DistanceForBMUCalcBlocksAndThreadsPfS_S_ # -- Begin function _Z49__device_stub__DistanceForBMUCalcBlocksAndThreadsPfS_S_
.p2align 4, 0x90
.type _Z49__device_stub__DistanceForBMUCalcBlocksAndThreadsPfS_S_,@function
_Z49__device_stub__DistanceForBMUCalcBlocksAndThreadsPfS_S_: # @_Z49__device_stub__DistanceForBMUCalcBlocksAndThreadsPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z49__device_stub__DistanceForBMUCalcBlocksAndThreadsPfS_S_, .Lfunc_end1-_Z49__device_stub__DistanceForBMUCalcBlocksAndThreadsPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
callq _ZNSt6chrono3_V212steady_clock3nowEv
movq %rax, %rbx
xorl %edi, %edi
callq srand
leaq 16(%rsp), %rdi
movl $268435456, %esi # imm = 0x10000000
callq hipMalloc
testl %eax, %eax
jne .LBB2_1
# %bb.7: # %_Z9gpuAssert10hipError_tPKcib.exit
movl $268435456, %edi # imm = 0x10000000
callq malloc
movq %rax, %r12
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_8: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r12,%r14,4)
incq %r14
cmpq $67108864, %r14 # imm = 0x4000000
jne .LBB2_8
# %bb.3:
leaq 8(%rsp), %rdi
movl $32768, %esi # imm = 0x8000
callq hipMalloc
testl %eax, %eax
jne .LBB2_4
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit42
movl $32768, %edi # imm = 0x8000
callq malloc
movq %rax, %r14
movq %rsp, %rdi
movl $32768, %esi # imm = 0x8000
callq hipMalloc
testl %eax, %eax
jne .LBB2_6
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit44
movl $32768, %edi # imm = 0x8000
callq malloc
movq %rax, %r13
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_10: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r13,%r15,4)
incq %r15
cmpq $8192, %r15 # imm = 0x2000
jne .LBB2_10
# %bb.11:
callq _ZNSt6chrono3_V212steady_clock3nowEv
movq %rax, %r15
movq 16(%rsp), %rdi
movl $268435456, %edx # imm = 0x10000000
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_12
# %bb.26: # %_Z9gpuAssert10hipError_tPKcib.exit48
movq (%rsp), %rdi
movl $32768, %edx # imm = 0x8000
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_27
# %bb.28: # %_Z9gpuAssert10hipError_tPKcib.exit50
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 8191(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_30
# %bb.29:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_30:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $32768, %edx # imm = 0x8000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_31
# %bb.32: # %_Z9gpuAssert10hipError_tPKcib.exit52
movss (%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %eax, %eax
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_33: # =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
cmoval %eax, %ebp
minss %xmm0, %xmm1
incq %rax
movaps %xmm1, %xmm0
cmpq $8192, %rax # imm = 0x2000
jne .LBB2_33
# %bb.13: # %.loopexit
callq _ZNSt6chrono3_V212steady_clock3nowEv
movq %rax, %r14
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r15, %r14
movabsq $4835703278458516699, %r15 # imm = 0x431BDE82D7B634DB
movq %r14, %rax
imulq %r15
movq %rdx, %rsi
shrq $63, %rsi
sarq $18, %rdx
addq %rdx, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_34
# %bb.14: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB2_16
# %bb.15:
movzbl 67(%r14), %ecx
jmp .LBB2_17
.LBB2_16:
movq %r14, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB2_17: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_34
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i54
cmpb $0, 56(%r14)
je .LBB2_20
# %bb.19:
movzbl 67(%r14), %ecx
jmp .LBB2_21
.LBB2_20:
movq %r14, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB2_21: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit57
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq _ZNSt6chrono3_V212steady_clock3nowEv
movq %rax, %r14
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %rbx, %r14
movq %r14, %rax
imulq %r15
movq %rdx, %rsi
shrq $63, %rsi
sarq $18, %rdx
addq %rdx, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_34
# %bb.22: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i59
cmpb $0, 56(%rbx)
je .LBB2_24
# %bb.23:
movzbl 67(%rbx), %ecx
jmp .LBB2_25
.LBB2_24:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_25: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit62
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_34:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.LBB2_1:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $56, %r8d
jmp .LBB2_2
.LBB2_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $66, %r8d
jmp .LBB2_2
.LBB2_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $72, %r8d
jmp .LBB2_2
.LBB2_12:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $84, %r8d
jmp .LBB2_2
.LBB2_27:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $86, %r8d
jmp .LBB2_2
.LBB2_31:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $99, %r8d
.LBB2_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24DistanceForBMUCalcBlocksPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24DistanceForBMUCalcBlocksPfS_S_,@object # @_Z24DistanceForBMUCalcBlocksPfS_S_
.section .rodata,"a",@progbits
.globl _Z24DistanceForBMUCalcBlocksPfS_S_
.p2align 3, 0x0
_Z24DistanceForBMUCalcBlocksPfS_S_:
.quad _Z39__device_stub__DistanceForBMUCalcBlocksPfS_S_
.size _Z24DistanceForBMUCalcBlocksPfS_S_, 8
.type _Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_,@object # @_Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_
.globl _Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_
.p2align 3, 0x0
_Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_:
.quad _Z49__device_stub__DistanceForBMUCalcBlocksAndThreadsPfS_S_
.size _Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/CarlyWilson/CUDA-Testing/master/benchMarking/gpuTestOuterLoop/bmuGPUOuterTest.hip"
.size .L.str, 139
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Total work execution time "
.size .L.str.1, 27
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "BMU is "
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Total Execution Time: "
.size .L.str.3, 23
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.4, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z24DistanceForBMUCalcBlocksPfS_S_"
.size .L__unnamed_1, 35
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_"
.size .L__unnamed_2, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__DistanceForBMUCalcBlocksPfS_S_
.addrsig_sym _Z49__device_stub__DistanceForBMUCalcBlocksAndThreadsPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24DistanceForBMUCalcBlocksPfS_S_
.addrsig_sym _Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011f97e_00000000-6_bmuGPUOuterTest.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4137:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4137:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB4131:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE4131:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z48__device_stub__Z24DistanceForBMUCalcBlocksPfS_S_PfS_S_
.type _Z48__device_stub__Z24DistanceForBMUCalcBlocksPfS_S_PfS_S_, @function
_Z48__device_stub__Z24DistanceForBMUCalcBlocksPfS_S_PfS_S_:
.LFB4159:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24DistanceForBMUCalcBlocksPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4159:
.size _Z48__device_stub__Z24DistanceForBMUCalcBlocksPfS_S_PfS_S_, .-_Z48__device_stub__Z24DistanceForBMUCalcBlocksPfS_S_PfS_S_
.globl _Z24DistanceForBMUCalcBlocksPfS_S_
.type _Z24DistanceForBMUCalcBlocksPfS_S_, @function
_Z24DistanceForBMUCalcBlocksPfS_S_:
.LFB4160:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z24DistanceForBMUCalcBlocksPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4160:
.size _Z24DistanceForBMUCalcBlocksPfS_S_, .-_Z24DistanceForBMUCalcBlocksPfS_S_
.globl _Z58__device_stub__Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_PfS_S_
.type _Z58__device_stub__Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_PfS_S_, @function
_Z58__device_stub__Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_PfS_S_:
.LFB4161:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4161:
.size _Z58__device_stub__Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_PfS_S_, .-_Z58__device_stub__Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_PfS_S_
.globl _Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_
.type _Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_, @function
_Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_:
.LFB4162:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z58__device_stub__Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4162:
.size _Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_, .-_Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/CarlyWilson/CUDA-Testing/master/benchMarking/gpuTestOuterLoop/bmuGPUOuterTest.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Total work execution time "
.LC3:
.string "BMU is "
.LC4:
.string "Total Execution Time: "
.text
.globl main
.type main, @function
main:
.LFB4132:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
movq %rax, %rbp
movl $0, %edi
call srand@PLT
leaq 8(%rsp), %rdi
movl $268435456, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $54, %edx
leaq .LC1(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $268435456, %edi
call malloc@PLT
movq %rax, %r13
movq %rax, %rbx
leaq 268435456(%rax), %r12
.L28:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L28
leaq 16(%rsp), %rdi
movl $32768, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $64, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $32768, %edi
call malloc@PLT
movq %rax, %r12
leaq 24(%rsp), %rdi
movl $32768, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $70, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $32768, %edi
call malloc@PLT
movq %rax, %r15
movq %rax, %rbx
leaq 32768(%rax), %r14
.L29:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %r14, %rbx
jne .L29
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
movq %rax, %r14
movl $1, %ecx
movl $268435456, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $82, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movl $32768, %edx
movq %r15, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $84, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $8192, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L30:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $32768, %edx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $97, %edx
leaq .LC1(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movss (%r12), %xmm0
movl $0, %eax
movl $0, %ebx
.L33:
movss (%r12,%rax,4), %xmm1
comiss %xmm1, %xmm0
cmova %eax, %ebx
minss %xmm0, %xmm1
movaps %xmm1, %xmm0
addq $1, %rax
cmpq $8192, %rax
jne .L33
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
movq %rax, %r12
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r12, %rcx
subq %r14, %rcx
movabsq $4835703278458516699, %r12
movq %rcx, %rax
imulq %r12
sarq $18, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC3(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
movq %rax, %rbx
leaq .LC4(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %rcx
subq %rbp, %rcx
movq %rcx, %rax
imulq %r12
sarq $18, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z58__device_stub__Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_PfS_S_
jmp .L30
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4132:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC5:
.string "_Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_"
.align 8
.LC6:
.string "_Z24DistanceForBMUCalcBlocksPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4164:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z24DistanceForBMUCalcBlocksPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4164:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "bmuGPUOuterTest.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z39__device_stub__DistanceForBMUCalcBlocksPfS_S_ # -- Begin function _Z39__device_stub__DistanceForBMUCalcBlocksPfS_S_
.p2align 4, 0x90
.type _Z39__device_stub__DistanceForBMUCalcBlocksPfS_S_,@function
_Z39__device_stub__DistanceForBMUCalcBlocksPfS_S_: # @_Z39__device_stub__DistanceForBMUCalcBlocksPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24DistanceForBMUCalcBlocksPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z39__device_stub__DistanceForBMUCalcBlocksPfS_S_, .Lfunc_end0-_Z39__device_stub__DistanceForBMUCalcBlocksPfS_S_
.cfi_endproc
# -- End function
.globl _Z49__device_stub__DistanceForBMUCalcBlocksAndThreadsPfS_S_ # -- Begin function _Z49__device_stub__DistanceForBMUCalcBlocksAndThreadsPfS_S_
.p2align 4, 0x90
.type _Z49__device_stub__DistanceForBMUCalcBlocksAndThreadsPfS_S_,@function
_Z49__device_stub__DistanceForBMUCalcBlocksAndThreadsPfS_S_: # @_Z49__device_stub__DistanceForBMUCalcBlocksAndThreadsPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z49__device_stub__DistanceForBMUCalcBlocksAndThreadsPfS_S_, .Lfunc_end1-_Z49__device_stub__DistanceForBMUCalcBlocksAndThreadsPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
callq _ZNSt6chrono3_V212steady_clock3nowEv
movq %rax, %rbx
xorl %edi, %edi
callq srand
leaq 16(%rsp), %rdi
movl $268435456, %esi # imm = 0x10000000
callq hipMalloc
testl %eax, %eax
jne .LBB2_1
# %bb.7: # %_Z9gpuAssert10hipError_tPKcib.exit
movl $268435456, %edi # imm = 0x10000000
callq malloc
movq %rax, %r12
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_8: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r12,%r14,4)
incq %r14
cmpq $67108864, %r14 # imm = 0x4000000
jne .LBB2_8
# %bb.3:
leaq 8(%rsp), %rdi
movl $32768, %esi # imm = 0x8000
callq hipMalloc
testl %eax, %eax
jne .LBB2_4
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit42
movl $32768, %edi # imm = 0x8000
callq malloc
movq %rax, %r14
movq %rsp, %rdi
movl $32768, %esi # imm = 0x8000
callq hipMalloc
testl %eax, %eax
jne .LBB2_6
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit44
movl $32768, %edi # imm = 0x8000
callq malloc
movq %rax, %r13
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_10: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r13,%r15,4)
incq %r15
cmpq $8192, %r15 # imm = 0x2000
jne .LBB2_10
# %bb.11:
callq _ZNSt6chrono3_V212steady_clock3nowEv
movq %rax, %r15
movq 16(%rsp), %rdi
movl $268435456, %edx # imm = 0x10000000
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_12
# %bb.26: # %_Z9gpuAssert10hipError_tPKcib.exit48
movq (%rsp), %rdi
movl $32768, %edx # imm = 0x8000
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_27
# %bb.28: # %_Z9gpuAssert10hipError_tPKcib.exit50
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 8191(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_30
# %bb.29:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_30:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $32768, %edx # imm = 0x8000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_31
# %bb.32: # %_Z9gpuAssert10hipError_tPKcib.exit52
movss (%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %eax, %eax
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_33: # =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
cmoval %eax, %ebp
minss %xmm0, %xmm1
incq %rax
movaps %xmm1, %xmm0
cmpq $8192, %rax # imm = 0x2000
jne .LBB2_33
# %bb.13: # %.loopexit
callq _ZNSt6chrono3_V212steady_clock3nowEv
movq %rax, %r14
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r15, %r14
movabsq $4835703278458516699, %r15 # imm = 0x431BDE82D7B634DB
movq %r14, %rax
imulq %r15
movq %rdx, %rsi
shrq $63, %rsi
sarq $18, %rdx
addq %rdx, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_34
# %bb.14: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB2_16
# %bb.15:
movzbl 67(%r14), %ecx
jmp .LBB2_17
.LBB2_16:
movq %r14, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB2_17: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_34
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i54
cmpb $0, 56(%r14)
je .LBB2_20
# %bb.19:
movzbl 67(%r14), %ecx
jmp .LBB2_21
.LBB2_20:
movq %r14, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB2_21: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit57
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq _ZNSt6chrono3_V212steady_clock3nowEv
movq %rax, %r14
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %rbx, %r14
movq %r14, %rax
imulq %r15
movq %rdx, %rsi
shrq $63, %rsi
sarq $18, %rdx
addq %rdx, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_34
# %bb.22: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i59
cmpb $0, 56(%rbx)
je .LBB2_24
# %bb.23:
movzbl 67(%rbx), %ecx
jmp .LBB2_25
.LBB2_24:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_25: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit62
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_34:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.LBB2_1:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $56, %r8d
jmp .LBB2_2
.LBB2_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $66, %r8d
jmp .LBB2_2
.LBB2_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $72, %r8d
jmp .LBB2_2
.LBB2_12:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $84, %r8d
jmp .LBB2_2
.LBB2_27:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $86, %r8d
jmp .LBB2_2
.LBB2_31:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $99, %r8d
.LBB2_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24DistanceForBMUCalcBlocksPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24DistanceForBMUCalcBlocksPfS_S_,@object # @_Z24DistanceForBMUCalcBlocksPfS_S_
.section .rodata,"a",@progbits
.globl _Z24DistanceForBMUCalcBlocksPfS_S_
.p2align 3, 0x0
_Z24DistanceForBMUCalcBlocksPfS_S_:
.quad _Z39__device_stub__DistanceForBMUCalcBlocksPfS_S_
.size _Z24DistanceForBMUCalcBlocksPfS_S_, 8
.type _Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_,@object # @_Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_
.globl _Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_
.p2align 3, 0x0
_Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_:
.quad _Z49__device_stub__DistanceForBMUCalcBlocksAndThreadsPfS_S_
.size _Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/CarlyWilson/CUDA-Testing/master/benchMarking/gpuTestOuterLoop/bmuGPUOuterTest.hip"
.size .L.str, 139
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Total work execution time "
.size .L.str.1, 27
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "BMU is "
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Total Execution Time: "
.size .L.str.3, 23
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.4, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z24DistanceForBMUCalcBlocksPfS_S_"
.size .L__unnamed_1, 35
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_"
.size .L__unnamed_2, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__DistanceForBMUCalcBlocksPfS_S_
.addrsig_sym _Z49__device_stub__DistanceForBMUCalcBlocksAndThreadsPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24DistanceForBMUCalcBlocksPfS_S_
.addrsig_sym _Z34DistanceForBMUCalcBlocksAndThreadsPfS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
using namespace std;
//host
extern float *Hy, coe_Hy, dt, dz;
extern int size_space, size_Hy;
const float PI = 3.141592653589793f;
const float mu = (4 * PI)*1e-7f;
//device
extern float *dev_Hy, *dev_Ex;
void Hy_init_malloc(int );
void Hy_init_assignValue(int );
void Hy_checkout();
void Hy_transfer_host_device();
void Hy_transfer_device_host();
void Hy_init(int space_size)
{
size_Hy = space_size;
Hy_init_malloc(size_Hy);
Hy_init_assignValue(size_Hy);
}
void Hy_init_malloc(int size)
{
//host
Hy = (float *)malloc(size * sizeof(float));
//device
cudaMalloc(&dev_Hy, size * sizeof(float));
}
void Hy_init_assignValue(int size)
{
int i;
for ( i = 0; i < size; i++){
Hy[i] = 0.f;
}
coe_Hy = dt / (mu * dz);
}
void Hy_checkout(int size)
{
cout << "Hy: size = " << size << endl;
cout << "coe_Hy = " << coe_Hy;
cout << "Hy: ";
for (int i = 0; i < size; i++)
{
cout << Hy[i] << "\t";
}
cout << endl;
}
void Hy_transfer_host_device(int size_Hy)
{
cudaMemcpy(dev_Hy, Hy, size_Hy * sizeof(float), cudaMemcpyHostToDevice);
}
void Hy_transfer_device_host(int size_Hy)
{
cudaMemcpy(Hy, dev_Hy, size_Hy * sizeof(float), cudaMemcpyDeviceToHost);
}
__global__ void Hy_cmp_kernel(float* dev_Hy, float * dev_Ex, float coe_Hy, int size_space)
{
int i;
for (i = 0; i < size_space; i++){
dev_Hy[i] = dev_Hy[i] - (coe_Hy)*(dev_Ex[i + 1] - dev_Ex[i]);
//test
//dev_Hy[i] = i*10.0;
}
} | code for sm_80
Function : _Z13Hy_cmp_kernelPfS_fi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R0, c[0x0][0x174] ; /* 0x00005d0000007a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0050*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0060*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0070*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fe20000000a00 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0090*/ @!P0 BRA 0xe40 ; /* 0x00000da000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R6, -R0, c[0x0][0x174], RZ ; /* 0x00005d0000067a10 */
/* 0x000fe20007ffe1ff */
/*00b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00c0*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe40000000f00 */
/*00d0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*00e0*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fce0000000f00 */
/*0110*/ @!P0 BRA 0xc00 ; /* 0x00000ae000008947 */
/* 0x000fea0003800000 */
/*0120*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0130*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0140*/ @!P1 BRA 0x820 ; /* 0x000006d000009947 */
/* 0x000fea0003800000 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0160*/ LDG.E R7, [R2.64] ; /* 0x0000000c02077981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040c02087981 */
/* 0x000ea8000c1e1900 */
/*0180*/ LDG.E R10, [R4.64] ; /* 0x0000000c040a7981 */
/* 0x000ee8000c1e1900 */
/*0190*/ LDG.E R11, [R4.64+0x4] ; /* 0x0000040c040b7981 */
/* 0x000f28000c1e1900 */
/*01a0*/ LDG.E R13, [R4.64+0x8] ; /* 0x0000080c040d7981 */
/* 0x000f62000c1e1900 */
/*01b0*/ FADD R7, -R7, R8 ; /* 0x0000000807077221 */
/* 0x004fc80000000100 */
/*01c0*/ FFMA R7, -R7, c[0x0][0x170], R10 ; /* 0x00005c0007077a23 */
/* 0x008fe4000000010a */
/*01d0*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c0c040a7981 */
/* 0x000ea8000c1e1900 */
/*01e0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe8000c10190c */
/*01f0*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040c02087981 */
/* 0x000ee8000c1e1900 */
/*0200*/ LDG.E R9, [R2.64+0x8] ; /* 0x0000080c02097981 */
/* 0x000ee4000c1e1900 */
/*0210*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*0220*/ FFMA R11, -R8, c[0x0][0x170], R11 ; /* 0x00005c00080b7a23 */
/* 0x010fca000000010b */
/*0230*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0001e8000c10190c */
/*0240*/ LDG.E R8, [R2.64+0x8] ; /* 0x0000080c02087981 */
/* 0x000ee8000c1e1900 */
/*0250*/ LDG.E R9, [R2.64+0xc] ; /* 0x00000c0c02097981 */
/* 0x000ee8000c1e1900 */
/*0260*/ LDG.E R11, [R4.64+0x10] ; /* 0x0000100c040b7981 */
/* 0x001f22000c1e1900 */
/*0270*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*0280*/ FFMA R13, -R8, c[0x0][0x170], R13 ; /* 0x00005c00080d7a23 */
/* 0x020fca000000010d */
/*0290*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x0001e8000c10190c */
/*02a0*/ LDG.E R7, [R2.64+0xc] ; /* 0x00000c0c02077981 */
/* 0x000ee8000c1e1900 */
/*02b0*/ LDG.E R8, [R2.64+0x10] ; /* 0x0000100c02087981 */
/* 0x000ee8000c1e1900 */
/*02c0*/ LDG.E R13, [R4.64+0x14] ; /* 0x0000140c040d7981 */
/* 0x001f62000c1e1900 */
/*02d0*/ FADD R7, -R7, R8 ; /* 0x0000000807077221 */
/* 0x008fc80000000100 */
/*02e0*/ FFMA R7, -R7, c[0x0][0x170], R10 ; /* 0x00005c0007077a23 */
/* 0x004fe4000000010a */
/*02f0*/ LDG.E R10, [R4.64+0x18] ; /* 0x0000180c040a7981 */
/* 0x000ea8000c1e1900 */
/*0300*/ STG.E [R4.64+0xc], R7 ; /* 0x00000c0704007986 */
/* 0x000fe8000c10190c */
/*0310*/ LDG.E R8, [R2.64+0x10] ; /* 0x0000100c02087981 */
/* 0x000ee8000c1e1900 */
/*0320*/ LDG.E R9, [R2.64+0x14] ; /* 0x0000140c02097981 */
/* 0x000ee4000c1e1900 */
/*0330*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*0340*/ FFMA R11, -R8, c[0x0][0x170], R11 ; /* 0x00005c00080b7a23 */
/* 0x010fca000000010b */
/*0350*/ STG.E [R4.64+0x10], R11 ; /* 0x0000100b04007986 */
/* 0x0001e8000c10190c */
/*0360*/ LDG.E R8, [R2.64+0x14] ; /* 0x0000140c02087981 */
/* 0x000ee8000c1e1900 */
/*0370*/ LDG.E R9, [R2.64+0x18] ; /* 0x0000180c02097981 */
/* 0x000ee8000c1e1900 */
/*0380*/ LDG.E R11, [R4.64+0x1c] ; /* 0x00001c0c040b7981 */
/* 0x001f22000c1e1900 */
/*0390*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*03a0*/ FFMA R13, -R8, c[0x0][0x170], R13 ; /* 0x00005c00080d7a23 */
/* 0x020fca000000010d */
/*03b0*/ STG.E [R4.64+0x14], R13 ; /* 0x0000140d04007986 */
/* 0x0001e8000c10190c */
/*03c0*/ LDG.E R7, [R2.64+0x18] ; /* 0x0000180c02077981 */
/* 0x000ee8000c1e1900 */
/*03d0*/ LDG.E R8, [R2.64+0x1c] ; /* 0x00001c0c02087981 */
/* 0x000ee8000c1e1900 */
/*03e0*/ LDG.E R13, [R4.64+0x20] ; /* 0x0000200c040d7981 */
/* 0x001f62000c1e1900 */
/*03f0*/ FADD R7, -R7, R8 ; /* 0x0000000807077221 */
/* 0x008fc80000000100 */
/*0400*/ FFMA R7, -R7, c[0x0][0x170], R10 ; /* 0x00005c0007077a23 */
/* 0x004fe4000000010a */
/*0410*/ LDG.E R10, [R4.64+0x24] ; /* 0x0000240c040a7981 */
/* 0x000ea8000c1e1900 */
/*0420*/ STG.E [R4.64+0x18], R7 ; /* 0x0000180704007986 */
/* 0x000fe8000c10190c */
/*0430*/ LDG.E R8, [R2.64+0x1c] ; /* 0x00001c0c02087981 */
/* 0x000ee8000c1e1900 */
/*0440*/ LDG.E R9, [R2.64+0x20] ; /* 0x0000200c02097981 */
/* 0x000ee4000c1e1900 */
/*0450*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*0460*/ FFMA R11, -R8, c[0x0][0x170], R11 ; /* 0x00005c00080b7a23 */
/* 0x010fca000000010b */
/*0470*/ STG.E [R4.64+0x1c], R11 ; /* 0x00001c0b04007986 */
/* 0x0001e8000c10190c */
/*0480*/ LDG.E R8, [R2.64+0x20] ; /* 0x0000200c02087981 */
/* 0x000ee8000c1e1900 */
/*0490*/ LDG.E R9, [R2.64+0x24] ; /* 0x0000240c02097981 */
/* 0x000ee8000c1e1900 */
/*04a0*/ LDG.E R11, [R4.64+0x28] ; /* 0x0000280c040b7981 */
/* 0x001f22000c1e1900 */
/*04b0*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*04c0*/ FFMA R13, -R8, c[0x0][0x170], R13 ; /* 0x00005c00080d7a23 */
/* 0x020fca000000010d */
/*04d0*/ STG.E [R4.64+0x20], R13 ; /* 0x0000200d04007986 */
/* 0x0001e8000c10190c */
/*04e0*/ LDG.E R7, [R2.64+0x24] ; /* 0x0000240c02077981 */
/* 0x000ee8000c1e1900 */
/*04f0*/ LDG.E R8, [R2.64+0x28] ; /* 0x0000280c02087981 */
/* 0x000ee8000c1e1900 */
/*0500*/ LDG.E R13, [R4.64+0x2c] ; /* 0x00002c0c040d7981 */
/* 0x001f62000c1e1900 */
/*0510*/ FADD R7, -R7, R8 ; /* 0x0000000807077221 */
/* 0x008fc80000000100 */
/*0520*/ FFMA R7, -R7, c[0x0][0x170], R10 ; /* 0x00005c0007077a23 */
/* 0x004fe4000000010a */
/*0530*/ LDG.E R10, [R4.64+0x30] ; /* 0x0000300c040a7981 */
/* 0x000ea8000c1e1900 */
/*0540*/ STG.E [R4.64+0x24], R7 ; /* 0x0000240704007986 */
/* 0x000fe8000c10190c */
/*0550*/ LDG.E R8, [R2.64+0x28] ; /* 0x0000280c02087981 */
/* 0x000ee8000c1e1900 */
/*0560*/ LDG.E R9, [R2.64+0x2c] ; /* 0x00002c0c02097981 */
/* 0x000ee4000c1e1900 */
/*0570*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*0580*/ FFMA R11, -R8, c[0x0][0x170], R11 ; /* 0x00005c00080b7a23 */
/* 0x010fca000000010b */
/*0590*/ STG.E [R4.64+0x28], R11 ; /* 0x0000280b04007986 */
/* 0x0001e8000c10190c */
/*05a0*/ LDG.E R8, [R2.64+0x2c] ; /* 0x00002c0c02087981 */
/* 0x000ee8000c1e1900 */
/*05b0*/ LDG.E R9, [R2.64+0x30] ; /* 0x0000300c02097981 */
/* 0x000ee8000c1e1900 */
/*05c0*/ LDG.E R11, [R4.64+0x34] ; /* 0x0000340c040b7981 */
/* 0x001f22000c1e1900 */
/*05d0*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*05e0*/ FFMA R13, -R8, c[0x0][0x170], R13 ; /* 0x00005c00080d7a23 */
/* 0x020fca000000010d */
/*05f0*/ STG.E [R4.64+0x2c], R13 ; /* 0x00002c0d04007986 */
/* 0x0001e8000c10190c */
/*0600*/ LDG.E R7, [R2.64+0x30] ; /* 0x0000300c02077981 */
/* 0x000ee8000c1e1900 */
/*0610*/ LDG.E R8, [R2.64+0x34] ; /* 0x0000340c02087981 */
/* 0x000ee8000c1e1900 */
/*0620*/ LDG.E R13, [R4.64+0x38] ; /* 0x0000380c040d7981 */
/* 0x001f62000c1e1900 */
/*0630*/ FADD R7, -R7, R8 ; /* 0x0000000807077221 */
/* 0x008fc80000000100 */
/*0640*/ FFMA R7, -R7, c[0x0][0x170], R10 ; /* 0x00005c0007077a23 */
/* 0x004fe4000000010a */
/*0650*/ LDG.E R10, [R4.64+0x3c] ; /* 0x00003c0c040a7981 */
/* 0x000ea8000c1e1900 */
/*0660*/ STG.E [R4.64+0x30], R7 ; /* 0x0000300704007986 */
/* 0x0001e8000c10190c */
/*0670*/ LDG.E R8, [R2.64+0x34] ; /* 0x0000340c02087981 */
/* 0x000ee8000c1e1900 */
/*0680*/ LDG.E R9, [R2.64+0x38] ; /* 0x0000380c02097981 */
/* 0x000ee4000c1e1900 */
/*0690*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*06a0*/ FFMA R11, -R8, c[0x0][0x170], R11 ; /* 0x00005c00080b7a23 */
/* 0x010fca000000010b */
/*06b0*/ STG.E [R4.64+0x34], R11 ; /* 0x0000340b04007986 */
/* 0x0003e8000c10190c */
/*06c0*/ LDG.E R8, [R2.64+0x38] ; /* 0x0000380c02087981 */
/* 0x000ee8000c1e1900 */
/*06d0*/ LDG.E R9, [R2.64+0x3c] ; /* 0x00003c0c02097981 */
/* 0x000ee4000c1e1900 */
/*06e0*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*06f0*/ FFMA R13, -R8, c[0x0][0x170], R13 ; /* 0x00005c00080d7a23 */
/* 0x020fca000000010d */
/*0700*/ STG.E [R4.64+0x38], R13 ; /* 0x0000380d04007986 */
/* 0x000fe8000c10190c */
/*0710*/ LDG.E R8, [R2.64+0x40] ; /* 0x0000400c02087981 */
/* 0x000ee8000c1e1900 */
/*0720*/ LDG.E R7, [R2.64+0x3c] ; /* 0x00003c0c02077981 */
/* 0x001ee2000c1e1900 */
/*0730*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*0740*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*0750*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*0760*/ FADD R7, -R7, R8 ; /* 0x0000000807077221 */
/* 0x008fe20000000100 */
/*0770*/ IADD3 R8, P3, R4, 0x40, RZ ; /* 0x0000004004087810 */
/* 0x000fc60007f7e0ff */
/*0780*/ FFMA R7, -R7, c[0x0][0x170], R10 ; /* 0x00005c0007077a23 */
/* 0x004fe2000000010a */
/*0790*/ IADD3 R10, P2, R2, 0x40, RZ ; /* 0x00000040020a7810 */
/* 0x000fe40007f5e0ff */
/*07a0*/ IADD3.X R9, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff097210 */
/* 0x000fe40001ffe4ff */
/*07b0*/ IADD3.X R11, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff0b7210 */
/* 0x002fe200017fe4ff */
/*07c0*/ STG.E [R4.64+0x3c], R7 ; /* 0x00003c0704007986 */
/* 0x0001e2000c10190c */
/*07d0*/ MOV R2, R10 ; /* 0x0000000a00027202 */
/* 0x000fe40000000f00 */
/*07e0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fe40000000f00 */
/*07f0*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x001fe20000000f00 */
/*0800*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*0810*/ @P1 BRA 0x160 ; /* 0xfffff94000001947 */
/* 0x000fea000383ffff */
/*0820*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0830*/ @!P1 BRA 0xbe0 ; /* 0x000003a000009947 */
/* 0x000fea0003800000 */
/*0840*/ LDG.E R7, [R2.64] ; /* 0x0000000c02077981 */
/* 0x000ea8000c1e1900 */
/*0850*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040c02087981 */
/* 0x000ea8000c1e1900 */
/*0860*/ LDG.E R10, [R4.64] ; /* 0x0000000c040a7981 */
/* 0x000ee8000c1e1900 */
/*0870*/ LDG.E R11, [R4.64+0x4] ; /* 0x0000040c040b7981 */
/* 0x000f28000c1e1900 */
/*0880*/ LDG.E R13, [R4.64+0x8] ; /* 0x0000080c040d7981 */
/* 0x000f62000c1e1900 */
/*0890*/ FADD R7, -R7, R8 ; /* 0x0000000807077221 */
/* 0x004fc80000000100 */
/*08a0*/ FFMA R7, -R7, c[0x0][0x170], R10 ; /* 0x00005c0007077a23 */
/* 0x008fe4000000010a */
/*08b0*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c0c040a7981 */
/* 0x000ea8000c1e1900 */
/*08c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe8000c10190c */
/*08d0*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040c02087981 */
/* 0x000ee8000c1e1900 */
/*08e0*/ LDG.E R9, [R2.64+0x8] ; /* 0x0000080c02097981 */
/* 0x000ee4000c1e1900 */
/*08f0*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*0900*/ FFMA R11, -R8, c[0x0][0x170], R11 ; /* 0x00005c00080b7a23 */
/* 0x010fca000000010b */
/*0910*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0001e8000c10190c */
/*0920*/ LDG.E R8, [R2.64+0x8] ; /* 0x0000080c02087981 */
/* 0x000ee8000c1e1900 */
/*0930*/ LDG.E R9, [R2.64+0xc] ; /* 0x00000c0c02097981 */
/* 0x000ee8000c1e1900 */
/*0940*/ LDG.E R11, [R4.64+0x10] ; /* 0x0000100c040b7981 */
/* 0x001f22000c1e1900 */
/*0950*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*0960*/ FFMA R13, -R8, c[0x0][0x170], R13 ; /* 0x00005c00080d7a23 */
/* 0x020fca000000010d */
/*0970*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x0001e8000c10190c */
/*0980*/ LDG.E R7, [R2.64+0xc] ; /* 0x00000c0c02077981 */
/* 0x000ee8000c1e1900 */
/*0990*/ LDG.E R8, [R2.64+0x10] ; /* 0x0000100c02087981 */
/* 0x000ee8000c1e1900 */
/*09a0*/ LDG.E R13, [R4.64+0x14] ; /* 0x0000140c040d7981 */
/* 0x001f62000c1e1900 */
/*09b0*/ FADD R7, -R7, R8 ; /* 0x0000000807077221 */
/* 0x008fc80000000100 */
/*09c0*/ FFMA R7, -R7, c[0x0][0x170], R10 ; /* 0x00005c0007077a23 */
/* 0x004fe4000000010a */
/*09d0*/ LDG.E R10, [R4.64+0x18] ; /* 0x0000180c040a7981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ STG.E [R4.64+0xc], R7 ; /* 0x00000c0704007986 */
/* 0x000fe8000c10190c */
/*09f0*/ LDG.E R8, [R2.64+0x10] ; /* 0x0000100c02087981 */
/* 0x000ee8000c1e1900 */
/*0a00*/ LDG.E R9, [R2.64+0x14] ; /* 0x0000140c02097981 */
/* 0x000ee4000c1e1900 */
/*0a10*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*0a20*/ FFMA R11, -R8, c[0x0][0x170], R11 ; /* 0x00005c00080b7a23 */
/* 0x010fca000000010b */
/*0a30*/ STG.E [R4.64+0x10], R11 ; /* 0x0000100b04007986 */
/* 0x0001e8000c10190c */
/*0a40*/ LDG.E R8, [R2.64+0x14] ; /* 0x0000140c02087981 */
/* 0x000ee8000c1e1900 */
/*0a50*/ LDG.E R9, [R2.64+0x18] ; /* 0x0000180c02097981 */
/* 0x000ee8000c1e1900 */
/*0a60*/ LDG.E R11, [R4.64+0x1c] ; /* 0x00001c0c040b7981 */
/* 0x001f22000c1e1900 */
/*0a70*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*0a80*/ FFMA R13, -R8, c[0x0][0x170], R13 ; /* 0x00005c00080d7a23 */
/* 0x020fca000000010d */
/*0a90*/ STG.E [R4.64+0x14], R13 ; /* 0x0000140d04007986 */
/* 0x000fe8000c10190c */
/*0aa0*/ LDG.E R7, [R2.64+0x18] ; /* 0x0000180c02077981 */
/* 0x000ee8000c1e1900 */
/*0ab0*/ LDG.E R8, [R2.64+0x1c] ; /* 0x00001c0c02087981 */
/* 0x000ee4000c1e1900 */
/*0ac0*/ FADD R7, -R7, R8 ; /* 0x0000000807077221 */
/* 0x008fc80000000100 */
/*0ad0*/ FFMA R7, -R7, c[0x0][0x170], R10 ; /* 0x00005c0007077a23 */
/* 0x004fca000000010a */
/*0ae0*/ STG.E [R4.64+0x18], R7 ; /* 0x0000180704007986 */
/* 0x000fe8000c10190c */
/*0af0*/ LDG.E R9, [R2.64+0x20] ; /* 0x0000200c02097981 */
/* 0x0000a8000c1e1900 */
/*0b00*/ LDG.E R8, [R2.64+0x1c] ; /* 0x00001c0c02087981 */
/* 0x0000a2000c1e1900 */
/*0b10*/ IADD3 R10, P1, R2, 0x20, RZ ; /* 0x00000020020a7810 */
/* 0x000fe40007f3e0ff */
/*0b20*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0b30*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0b40*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0b50*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x001fe40000ffe4ff */
/*0b60*/ MOV R2, R10 ; /* 0x0000000a00027202 */
/* 0x000fe20000000f00 */
/*0b70*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x004fc80000000100 */
/*0b80*/ FFMA R11, -R8, c[0x0][0x170], R11 ; /* 0x00005c00080b7a23 */
/* 0x010fe2000000010b */
/*0b90*/ IADD3 R8, P2, R4, 0x20, RZ ; /* 0x0000002004087810 */
/* 0x000fc80007f5e0ff */
/*0ba0*/ IADD3.X R9, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff097210 */
/* 0x000fe200017fe4ff */
/*0bb0*/ STG.E [R4.64+0x1c], R11 ; /* 0x00001c0b04007986 */
/* 0x0001e4000c10190c */
/*0bc0*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x001fe40000000f00 */
/*0bd0*/ MOV R5, R9 ; /* 0x0000000900057202 */
/* 0x000fe40000000f00 */
/*0be0*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0bf0*/ @!P0 BRA 0xe40 ; /* 0x0000024000008947 */
/* 0x000fea0003800000 */
/*0c00*/ LDG.E R7, [R2.64] ; /* 0x0000000c02077981 */
/* 0x000ea8000c1e1900 */
/*0c10*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040c02087981 */
/* 0x000ea8000c1e1900 */
/*0c20*/ LDG.E R10, [R4.64] ; /* 0x0000000c040a7981 */
/* 0x000ee8000c1e1900 */
/*0c30*/ LDG.E R11, [R4.64+0x4] ; /* 0x0000040c040b7981 */
/* 0x000f28000c1e1900 */
/*0c40*/ LDG.E R13, [R4.64+0x8] ; /* 0x0000080c040d7981 */
/* 0x000f62000c1e1900 */
/*0c50*/ FADD R7, -R7, R8 ; /* 0x0000000807077221 */
/* 0x004fc80000000100 */
/*0c60*/ FFMA R7, -R7, c[0x0][0x170], R10 ; /* 0x00005c0007077a23 */
/* 0x008fe4000000010a */
/*0c70*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c0c040a7981 */
/* 0x000ea8000c1e1900 */
/*0c80*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c10190c */
/*0c90*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040c02087981 */
/* 0x000ee8000c1e1900 */
/*0ca0*/ LDG.E R9, [R2.64+0x8] ; /* 0x0000080c02097981 */
/* 0x000ee4000c1e1900 */
/*0cb0*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*0cc0*/ FFMA R11, -R8, c[0x0][0x170], R11 ; /* 0x00005c00080b7a23 */
/* 0x010fca000000010b */
/*0cd0*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0003e8000c10190c */
/*0ce0*/ LDG.E R8, [R2.64+0x8] ; /* 0x0000080c02087981 */
/* 0x000ee8000c1e1900 */
/*0cf0*/ LDG.E R9, [R2.64+0xc] ; /* 0x00000c0c02097981 */
/* 0x000ee4000c1e1900 */
/*0d00*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*0d10*/ FFMA R13, -R8, c[0x0][0x170], R13 ; /* 0x00005c00080d7a23 */
/* 0x020fca000000010d */
/*0d20*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x000fe8000c10190c */
/*0d30*/ LDG.E R8, [R2.64+0x10] ; /* 0x0000100c02087981 */
/* 0x000ee8000c1e1900 */
/*0d40*/ LDG.E R7, [R2.64+0xc] ; /* 0x00000c0c02077981 */
/* 0x001ee2000c1e1900 */
/*0d50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0d60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0d70*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0d80*/ FADD R7, -R7, R8 ; /* 0x0000000807077221 */
/* 0x008fe20000000100 */
/*0d90*/ IADD3 R8, P2, R4, 0x10, RZ ; /* 0x0000001004087810 */
/* 0x000fc60007f5e0ff */
/*0da0*/ FFMA R7, -R7, c[0x0][0x170], R10 ; /* 0x00005c0007077a23 */
/* 0x004fe2000000010a */
/*0db0*/ IADD3 R10, P1, R2, 0x10, RZ ; /* 0x00000010020a7810 */
/* 0x000fe40007f3e0ff */
/*0dc0*/ IADD3.X R9, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff097210 */
/* 0x000fe400017fe4ff */
/*0dd0*/ IADD3.X R11, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff0b7210 */
/* 0x002fe20000ffe4ff */
/*0de0*/ STG.E [R4.64+0xc], R7 ; /* 0x00000c0704007986 */
/* 0x0001e2000c10190c */
/*0df0*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000a */
/*0e00*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fe40000000f00 */
/*0e10*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x001fc40000000f00 */
/*0e20*/ MOV R5, R9 ; /* 0x0000000900057202 */
/* 0x000fe20000000f00 */
/*0e30*/ @P0 BRA 0xc00 ; /* 0xfffffdc000000947 */
/* 0x000fea000383ffff */
/*0e40*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0e50*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0e60*/ UIADD3 UR5, UR4, 0x1, URZ ; /* 0x0000000104057890 */
/* 0x000fe4000fffe03f */
/*0e70*/ UMOV UR10, 0x4 ; /* 0x00000004000a7882 */
/* 0x000fe40000000000 */
/*0e80*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe40000000a00 */
/*0e90*/ ULDC.64 UR8, c[0x0][0x160] ; /* 0x0000580000087ab9 */
/* 0x000fe40000000a00 */
/*0ea0*/ UIMAD.WIDE UR6, UR5, UR10, UR6 ; /* 0x0000000a050672a5 */
/* 0x000fe4000f8e0206 */
/*0eb0*/ UIMAD.WIDE UR4, UR4, UR10, UR8 ; /* 0x0000000a040472a5 */
/* 0x000fc8000f8e0208 */
/*0ec0*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fe40008000f00 */
/*0ed0*/ MOV R6, UR4 ; /* 0x0000000400067c02 */
/* 0x000fe20008000f00 */
/*0ee0*/ IMAD.U32 R7, RZ, RZ, UR5 ; /* 0x00000005ff077e24 */
/* 0x000fe2000f8e00ff */
/*0ef0*/ MOV R3, UR7 ; /* 0x0000000700037c02 */
/* 0x000fe40008000f00 */
/*0f00*/ MOV R8, UR4 ; /* 0x0000000400087c02 */
/* 0x000fe40008000f00 */
/*0f10*/ MOV R2, UR6 ; /* 0x0000000600027c02 */
/* 0x000fe40008000f00 */
/*0f20*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fc40008000f00 */
/*0f30*/ MOV R9, UR5 ; /* 0x0000000500097c02 */
/* 0x000fe40008000f00 */
/*0f40*/ MOV R3, R5 ; /* 0x0000000500037202 */
/* 0x000fe40000000f00 */
/*0f50*/ MOV R8, R6 ; /* 0x0000000600087202 */
/* 0x000fc80000000f00 */
/*0f60*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x000fe20000000f00 */
/*0f70*/ LDG.E R6, [R2.64+-0x4] ; /* 0xfffffc0c02067981 */
/* 0x0000a2000c1e1900 */
/*0f80*/ MOV R5, R9 ; /* 0x0000000900057202 */
/* 0x000fc60000000f00 */
/*0f90*/ LDG.E R7, [R2.64] ; /* 0x0000000c02077981 */
/* 0x0000a8000c1e1900 */
/*0fa0*/ LDG.E R9, [R4.64] ; /* 0x0000000c04097981 */
/* 0x000ee2000c1e1900 */
/*0fb0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*0fc0*/ IADD3 R8, P2, R4, 0x4, RZ ; /* 0x0000000404087810 */
/* 0x000fe40007f5e0ff */
/*0fd0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0fe0*/ IADD3 R2, P1, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fc80007f3e0ff */
/*0ff0*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x000fe20000ffe4ff */
/*1000*/ FADD R6, -R6, R7 ; /* 0x0000000706067221 */
/* 0x004fc80000000100 */
/*1010*/ FFMA R9, -R6, c[0x0][0x170], R9 ; /* 0x00005c0006097a23 */
/* 0x008fca0000000109 */
/*1020*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c10190c */
/*1030*/ IADD3.X R9, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff097210 */
/* 0x001fe200017fe4ff */
/*1040*/ @P0 BRA 0xf60 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*1050*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1060*/ BRA 0x1060; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
using namespace std;
//host
extern float *Hy, coe_Hy, dt, dz;
extern int size_space, size_Hy;
const float PI = 3.141592653589793f;
const float mu = (4 * PI)*1e-7f;
//device
extern float *dev_Hy, *dev_Ex;
void Hy_init_malloc(int );
void Hy_init_assignValue(int );
void Hy_checkout();
void Hy_transfer_host_device();
void Hy_transfer_device_host();
void Hy_init(int space_size)
{
size_Hy = space_size;
Hy_init_malloc(size_Hy);
Hy_init_assignValue(size_Hy);
}
void Hy_init_malloc(int size)
{
//host
Hy = (float *)malloc(size * sizeof(float));
//device
cudaMalloc(&dev_Hy, size * sizeof(float));
}
void Hy_init_assignValue(int size)
{
int i;
for ( i = 0; i < size; i++){
Hy[i] = 0.f;
}
coe_Hy = dt / (mu * dz);
}
void Hy_checkout(int size)
{
cout << "Hy: size = " << size << endl;
cout << "coe_Hy = " << coe_Hy;
cout << "Hy: ";
for (int i = 0; i < size; i++)
{
cout << Hy[i] << "\t";
}
cout << endl;
}
void Hy_transfer_host_device(int size_Hy)
{
cudaMemcpy(dev_Hy, Hy, size_Hy * sizeof(float), cudaMemcpyHostToDevice);
}
void Hy_transfer_device_host(int size_Hy)
{
cudaMemcpy(Hy, dev_Hy, size_Hy * sizeof(float), cudaMemcpyDeviceToHost);
}
__global__ void Hy_cmp_kernel(float* dev_Hy, float * dev_Ex, float coe_Hy, int size_space)
{
int i;
for (i = 0; i < size_space; i++){
dev_Hy[i] = dev_Hy[i] - (coe_Hy)*(dev_Ex[i + 1] - dev_Ex[i]);
//test
//dev_Hy[i] = i*10.0;
}
} | .file "tmpxft_000554e0_00000000-6_Hy.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3677:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3677:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14Hy_init_malloci
.type _Z14Hy_init_malloci, @function
_Z14Hy_init_malloci:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movslq %edi, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, Hy(%rip)
movq %rbx, %rsi
leaq dev_Hy(%rip), %rdi
call cudaMalloc@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z14Hy_init_malloci, .-_Z14Hy_init_malloci
.globl _Z19Hy_init_assignValuei
.type _Z19Hy_init_assignValuei, @function
_Z19Hy_init_assignValuei:
.LFB3671:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L6
movslq %edi, %rdi
leaq 0(,%rdi,4), %rcx
movl $0, %eax
.L7:
movq Hy(%rip), %rdx
movl $0x00000000, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L7
.L6:
movss .LC1(%rip), %xmm1
mulss dz(%rip), %xmm1
movss dt(%rip), %xmm0
divss %xmm1, %xmm0
movss %xmm0, coe_Hy(%rip)
ret
.cfi_endproc
.LFE3671:
.size _Z19Hy_init_assignValuei, .-_Z19Hy_init_assignValuei
.globl _Z7Hy_initi
.type _Z7Hy_initi, @function
_Z7Hy_initi:
.LFB3669:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl %edi, size_Hy(%rip)
call _Z14Hy_init_malloci
movl size_Hy(%rip), %edi
call _Z19Hy_init_assignValuei
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z7Hy_initi, .-_Z7Hy_initi
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Hy: size = "
.LC3:
.string "coe_Hy = "
.LC4:
.string "Hy: "
.LC5:
.string "\t"
.text
.globl _Z11Hy_checkouti
.type _Z11Hy_checkouti, @function
_Z11Hy_checkouti:
.LFB3672:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebp
movl $11, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L22
cmpb $0, 56(%r12)
je .L13
movzbl 67(%r12), %esi
.L14:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $9, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd coe_Hy(%rip), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movl $4, %edx
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
testl %ebp, %ebp
jle .L15
movslq %ebp, %rbp
salq $2, %rbp
movl $0, %ebx
leaq _ZSt4cout(%rip), %r13
leaq .LC5(%rip), %r12
.L16:
movq Hy(%rip), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, %rbp
jne .L16
.L15:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L23
cmpb $0, 56(%rbx)
je .L18
movzbl 67(%rbx), %esi
.L19:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L13:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L14
.L23:
call _ZSt16__throw_bad_castv@PLT
.L18:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L19
.cfi_endproc
.LFE3672:
.size _Z11Hy_checkouti, .-_Z11Hy_checkouti
.globl _Z23Hy_transfer_host_devicei
.type _Z23Hy_transfer_host_devicei, @function
_Z23Hy_transfer_host_devicei:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movslq %edi, %rdx
salq $2, %rdx
movl $1, %ecx
movq Hy(%rip), %rsi
movq dev_Hy(%rip), %rdi
call cudaMemcpy@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _Z23Hy_transfer_host_devicei, .-_Z23Hy_transfer_host_devicei
.globl _Z23Hy_transfer_device_hosti
.type _Z23Hy_transfer_device_hosti, @function
_Z23Hy_transfer_device_hosti:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movslq %edi, %rdx
salq $2, %rdx
movl $2, %ecx
movq dev_Hy(%rip), %rsi
movq Hy(%rip), %rdi
call cudaMemcpy@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _Z23Hy_transfer_device_hosti, .-_Z23Hy_transfer_device_hosti
.globl _Z37__device_stub__Z13Hy_cmp_kernelPfS_fiPfS_fi
.type _Z37__device_stub__Z13Hy_cmp_kernelPfS_fiPfS_fi, @function
_Z37__device_stub__Z13Hy_cmp_kernelPfS_fiPfS_fi:
.LFB3699:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13Hy_cmp_kernelPfS_fi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z37__device_stub__Z13Hy_cmp_kernelPfS_fiPfS_fi, .-_Z37__device_stub__Z13Hy_cmp_kernelPfS_fiPfS_fi
.globl _Z13Hy_cmp_kernelPfS_fi
.type _Z13Hy_cmp_kernelPfS_fi, @function
_Z13Hy_cmp_kernelPfS_fi:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13Hy_cmp_kernelPfS_fiPfS_fi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z13Hy_cmp_kernelPfS_fi, .-_Z13Hy_cmp_kernelPfS_fi
.section .rodata.str1.1
.LC6:
.string "_Z13Hy_cmp_kernelPfS_fi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z13Hy_cmp_kernelPfS_fi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 900245945
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
using namespace std;
//host
extern float *Hy, coe_Hy, dt, dz;
extern int size_space, size_Hy;
const float PI = 3.141592653589793f;
const float mu = (4 * PI)*1e-7f;
//device
extern float *dev_Hy, *dev_Ex;
void Hy_init_malloc(int );
void Hy_init_assignValue(int );
void Hy_checkout();
void Hy_transfer_host_device();
void Hy_transfer_device_host();
void Hy_init(int space_size)
{
size_Hy = space_size;
Hy_init_malloc(size_Hy);
Hy_init_assignValue(size_Hy);
}
void Hy_init_malloc(int size)
{
//host
Hy = (float *)malloc(size * sizeof(float));
//device
cudaMalloc(&dev_Hy, size * sizeof(float));
}
void Hy_init_assignValue(int size)
{
int i;
for ( i = 0; i < size; i++){
Hy[i] = 0.f;
}
coe_Hy = dt / (mu * dz);
}
void Hy_checkout(int size)
{
cout << "Hy: size = " << size << endl;
cout << "coe_Hy = " << coe_Hy;
cout << "Hy: ";
for (int i = 0; i < size; i++)
{
cout << Hy[i] << "\t";
}
cout << endl;
}
void Hy_transfer_host_device(int size_Hy)
{
cudaMemcpy(dev_Hy, Hy, size_Hy * sizeof(float), cudaMemcpyHostToDevice);
}
void Hy_transfer_device_host(int size_Hy)
{
cudaMemcpy(Hy, dev_Hy, size_Hy * sizeof(float), cudaMemcpyDeviceToHost);
}
__global__ void Hy_cmp_kernel(float* dev_Hy, float * dev_Ex, float coe_Hy, int size_space)
{
int i;
for (i = 0; i < size_space; i++){
dev_Hy[i] = dev_Hy[i] - (coe_Hy)*(dev_Ex[i + 1] - dev_Ex[i]);
//test
//dev_Hy[i] = i*10.0;
}
} | #pragma once
#include <hip/hip_runtime.h>
#ifndef HY_CUH
#define HY_CUH
void Hy_init(int size_space);
void Hy_checkout(int size_Hy);
void Hy_transfer_host_device(int size_Hy);
void Hy_transfer_device_host(int size_Hy);
__global__ void Hy_cmp_kernel(float* dev_Hy, float * dev_Ex, float coe_Hy, int size_space);
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #pragma once
#include <hip/hip_runtime.h>
#ifndef HY_CUH
#define HY_CUH
void Hy_init(int size_space);
void Hy_checkout(int size_Hy);
void Hy_transfer_host_device(int size_Hy);
void Hy_transfer_device_host(int size_Hy);
__global__ void Hy_cmp_kernel(float* dev_Hy, float * dev_Ex, float coe_Hy, int size_space);
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #pragma once
#include <hip/hip_runtime.h>
#ifndef HY_CUH
#define HY_CUH
void Hy_init(int size_space);
void Hy_checkout(int size_Hy);
void Hy_transfer_host_device(int size_Hy);
void Hy_transfer_device_host(int size_Hy);
__global__ void Hy_cmp_kernel(float* dev_Hy, float * dev_Ex, float coe_Hy, int size_space);
#endif | .text
.file "Hy.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13Hy_cmp_kernelPfS_fi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R0, c[0x0][0x174] ; /* 0x00005d0000007a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0050*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0060*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0070*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fe20000000a00 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0090*/ @!P0 BRA 0xe40 ; /* 0x00000da000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R6, -R0, c[0x0][0x174], RZ ; /* 0x00005d0000067a10 */
/* 0x000fe20007ffe1ff */
/*00b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00c0*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe40000000f00 */
/*00d0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*00e0*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fce0000000f00 */
/*0110*/ @!P0 BRA 0xc00 ; /* 0x00000ae000008947 */
/* 0x000fea0003800000 */
/*0120*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0130*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0140*/ @!P1 BRA 0x820 ; /* 0x000006d000009947 */
/* 0x000fea0003800000 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0160*/ LDG.E R7, [R2.64] ; /* 0x0000000c02077981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040c02087981 */
/* 0x000ea8000c1e1900 */
/*0180*/ LDG.E R10, [R4.64] ; /* 0x0000000c040a7981 */
/* 0x000ee8000c1e1900 */
/*0190*/ LDG.E R11, [R4.64+0x4] ; /* 0x0000040c040b7981 */
/* 0x000f28000c1e1900 */
/*01a0*/ LDG.E R13, [R4.64+0x8] ; /* 0x0000080c040d7981 */
/* 0x000f62000c1e1900 */
/*01b0*/ FADD R7, -R7, R8 ; /* 0x0000000807077221 */
/* 0x004fc80000000100 */
/*01c0*/ FFMA R7, -R7, c[0x0][0x170], R10 ; /* 0x00005c0007077a23 */
/* 0x008fe4000000010a */
/*01d0*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c0c040a7981 */
/* 0x000ea8000c1e1900 */
/*01e0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe8000c10190c */
/*01f0*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040c02087981 */
/* 0x000ee8000c1e1900 */
/*0200*/ LDG.E R9, [R2.64+0x8] ; /* 0x0000080c02097981 */
/* 0x000ee4000c1e1900 */
/*0210*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*0220*/ FFMA R11, -R8, c[0x0][0x170], R11 ; /* 0x00005c00080b7a23 */
/* 0x010fca000000010b */
/*0230*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0001e8000c10190c */
/*0240*/ LDG.E R8, [R2.64+0x8] ; /* 0x0000080c02087981 */
/* 0x000ee8000c1e1900 */
/*0250*/ LDG.E R9, [R2.64+0xc] ; /* 0x00000c0c02097981 */
/* 0x000ee8000c1e1900 */
/*0260*/ LDG.E R11, [R4.64+0x10] ; /* 0x0000100c040b7981 */
/* 0x001f22000c1e1900 */
/*0270*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*0280*/ FFMA R13, -R8, c[0x0][0x170], R13 ; /* 0x00005c00080d7a23 */
/* 0x020fca000000010d */
/*0290*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x0001e8000c10190c */
/*02a0*/ LDG.E R7, [R2.64+0xc] ; /* 0x00000c0c02077981 */
/* 0x000ee8000c1e1900 */
/*02b0*/ LDG.E R8, [R2.64+0x10] ; /* 0x0000100c02087981 */
/* 0x000ee8000c1e1900 */
/*02c0*/ LDG.E R13, [R4.64+0x14] ; /* 0x0000140c040d7981 */
/* 0x001f62000c1e1900 */
/*02d0*/ FADD R7, -R7, R8 ; /* 0x0000000807077221 */
/* 0x008fc80000000100 */
/*02e0*/ FFMA R7, -R7, c[0x0][0x170], R10 ; /* 0x00005c0007077a23 */
/* 0x004fe4000000010a */
/*02f0*/ LDG.E R10, [R4.64+0x18] ; /* 0x0000180c040a7981 */
/* 0x000ea8000c1e1900 */
/*0300*/ STG.E [R4.64+0xc], R7 ; /* 0x00000c0704007986 */
/* 0x000fe8000c10190c */
/*0310*/ LDG.E R8, [R2.64+0x10] ; /* 0x0000100c02087981 */
/* 0x000ee8000c1e1900 */
/*0320*/ LDG.E R9, [R2.64+0x14] ; /* 0x0000140c02097981 */
/* 0x000ee4000c1e1900 */
/*0330*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*0340*/ FFMA R11, -R8, c[0x0][0x170], R11 ; /* 0x00005c00080b7a23 */
/* 0x010fca000000010b */
/*0350*/ STG.E [R4.64+0x10], R11 ; /* 0x0000100b04007986 */
/* 0x0001e8000c10190c */
/*0360*/ LDG.E R8, [R2.64+0x14] ; /* 0x0000140c02087981 */
/* 0x000ee8000c1e1900 */
/*0370*/ LDG.E R9, [R2.64+0x18] ; /* 0x0000180c02097981 */
/* 0x000ee8000c1e1900 */
/*0380*/ LDG.E R11, [R4.64+0x1c] ; /* 0x00001c0c040b7981 */
/* 0x001f22000c1e1900 */
/*0390*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*03a0*/ FFMA R13, -R8, c[0x0][0x170], R13 ; /* 0x00005c00080d7a23 */
/* 0x020fca000000010d */
/*03b0*/ STG.E [R4.64+0x14], R13 ; /* 0x0000140d04007986 */
/* 0x0001e8000c10190c */
/*03c0*/ LDG.E R7, [R2.64+0x18] ; /* 0x0000180c02077981 */
/* 0x000ee8000c1e1900 */
/*03d0*/ LDG.E R8, [R2.64+0x1c] ; /* 0x00001c0c02087981 */
/* 0x000ee8000c1e1900 */
/*03e0*/ LDG.E R13, [R4.64+0x20] ; /* 0x0000200c040d7981 */
/* 0x001f62000c1e1900 */
/*03f0*/ FADD R7, -R7, R8 ; /* 0x0000000807077221 */
/* 0x008fc80000000100 */
/*0400*/ FFMA R7, -R7, c[0x0][0x170], R10 ; /* 0x00005c0007077a23 */
/* 0x004fe4000000010a */
/*0410*/ LDG.E R10, [R4.64+0x24] ; /* 0x0000240c040a7981 */
/* 0x000ea8000c1e1900 */
/*0420*/ STG.E [R4.64+0x18], R7 ; /* 0x0000180704007986 */
/* 0x000fe8000c10190c */
/*0430*/ LDG.E R8, [R2.64+0x1c] ; /* 0x00001c0c02087981 */
/* 0x000ee8000c1e1900 */
/*0440*/ LDG.E R9, [R2.64+0x20] ; /* 0x0000200c02097981 */
/* 0x000ee4000c1e1900 */
/*0450*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*0460*/ FFMA R11, -R8, c[0x0][0x170], R11 ; /* 0x00005c00080b7a23 */
/* 0x010fca000000010b */
/*0470*/ STG.E [R4.64+0x1c], R11 ; /* 0x00001c0b04007986 */
/* 0x0001e8000c10190c */
/*0480*/ LDG.E R8, [R2.64+0x20] ; /* 0x0000200c02087981 */
/* 0x000ee8000c1e1900 */
/*0490*/ LDG.E R9, [R2.64+0x24] ; /* 0x0000240c02097981 */
/* 0x000ee8000c1e1900 */
/*04a0*/ LDG.E R11, [R4.64+0x28] ; /* 0x0000280c040b7981 */
/* 0x001f22000c1e1900 */
/*04b0*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*04c0*/ FFMA R13, -R8, c[0x0][0x170], R13 ; /* 0x00005c00080d7a23 */
/* 0x020fca000000010d */
/*04d0*/ STG.E [R4.64+0x20], R13 ; /* 0x0000200d04007986 */
/* 0x0001e8000c10190c */
/*04e0*/ LDG.E R7, [R2.64+0x24] ; /* 0x0000240c02077981 */
/* 0x000ee8000c1e1900 */
/*04f0*/ LDG.E R8, [R2.64+0x28] ; /* 0x0000280c02087981 */
/* 0x000ee8000c1e1900 */
/*0500*/ LDG.E R13, [R4.64+0x2c] ; /* 0x00002c0c040d7981 */
/* 0x001f62000c1e1900 */
/*0510*/ FADD R7, -R7, R8 ; /* 0x0000000807077221 */
/* 0x008fc80000000100 */
/*0520*/ FFMA R7, -R7, c[0x0][0x170], R10 ; /* 0x00005c0007077a23 */
/* 0x004fe4000000010a */
/*0530*/ LDG.E R10, [R4.64+0x30] ; /* 0x0000300c040a7981 */
/* 0x000ea8000c1e1900 */
/*0540*/ STG.E [R4.64+0x24], R7 ; /* 0x0000240704007986 */
/* 0x000fe8000c10190c */
/*0550*/ LDG.E R8, [R2.64+0x28] ; /* 0x0000280c02087981 */
/* 0x000ee8000c1e1900 */
/*0560*/ LDG.E R9, [R2.64+0x2c] ; /* 0x00002c0c02097981 */
/* 0x000ee4000c1e1900 */
/*0570*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*0580*/ FFMA R11, -R8, c[0x0][0x170], R11 ; /* 0x00005c00080b7a23 */
/* 0x010fca000000010b */
/*0590*/ STG.E [R4.64+0x28], R11 ; /* 0x0000280b04007986 */
/* 0x0001e8000c10190c */
/*05a0*/ LDG.E R8, [R2.64+0x2c] ; /* 0x00002c0c02087981 */
/* 0x000ee8000c1e1900 */
/*05b0*/ LDG.E R9, [R2.64+0x30] ; /* 0x0000300c02097981 */
/* 0x000ee8000c1e1900 */
/*05c0*/ LDG.E R11, [R4.64+0x34] ; /* 0x0000340c040b7981 */
/* 0x001f22000c1e1900 */
/*05d0*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*05e0*/ FFMA R13, -R8, c[0x0][0x170], R13 ; /* 0x00005c00080d7a23 */
/* 0x020fca000000010d */
/*05f0*/ STG.E [R4.64+0x2c], R13 ; /* 0x00002c0d04007986 */
/* 0x0001e8000c10190c */
/*0600*/ LDG.E R7, [R2.64+0x30] ; /* 0x0000300c02077981 */
/* 0x000ee8000c1e1900 */
/*0610*/ LDG.E R8, [R2.64+0x34] ; /* 0x0000340c02087981 */
/* 0x000ee8000c1e1900 */
/*0620*/ LDG.E R13, [R4.64+0x38] ; /* 0x0000380c040d7981 */
/* 0x001f62000c1e1900 */
/*0630*/ FADD R7, -R7, R8 ; /* 0x0000000807077221 */
/* 0x008fc80000000100 */
/*0640*/ FFMA R7, -R7, c[0x0][0x170], R10 ; /* 0x00005c0007077a23 */
/* 0x004fe4000000010a */
/*0650*/ LDG.E R10, [R4.64+0x3c] ; /* 0x00003c0c040a7981 */
/* 0x000ea8000c1e1900 */
/*0660*/ STG.E [R4.64+0x30], R7 ; /* 0x0000300704007986 */
/* 0x0001e8000c10190c */
/*0670*/ LDG.E R8, [R2.64+0x34] ; /* 0x0000340c02087981 */
/* 0x000ee8000c1e1900 */
/*0680*/ LDG.E R9, [R2.64+0x38] ; /* 0x0000380c02097981 */
/* 0x000ee4000c1e1900 */
/*0690*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*06a0*/ FFMA R11, -R8, c[0x0][0x170], R11 ; /* 0x00005c00080b7a23 */
/* 0x010fca000000010b */
/*06b0*/ STG.E [R4.64+0x34], R11 ; /* 0x0000340b04007986 */
/* 0x0003e8000c10190c */
/*06c0*/ LDG.E R8, [R2.64+0x38] ; /* 0x0000380c02087981 */
/* 0x000ee8000c1e1900 */
/*06d0*/ LDG.E R9, [R2.64+0x3c] ; /* 0x00003c0c02097981 */
/* 0x000ee4000c1e1900 */
/*06e0*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*06f0*/ FFMA R13, -R8, c[0x0][0x170], R13 ; /* 0x00005c00080d7a23 */
/* 0x020fca000000010d */
/*0700*/ STG.E [R4.64+0x38], R13 ; /* 0x0000380d04007986 */
/* 0x000fe8000c10190c */
/*0710*/ LDG.E R8, [R2.64+0x40] ; /* 0x0000400c02087981 */
/* 0x000ee8000c1e1900 */
/*0720*/ LDG.E R7, [R2.64+0x3c] ; /* 0x00003c0c02077981 */
/* 0x001ee2000c1e1900 */
/*0730*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*0740*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*0750*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*0760*/ FADD R7, -R7, R8 ; /* 0x0000000807077221 */
/* 0x008fe20000000100 */
/*0770*/ IADD3 R8, P3, R4, 0x40, RZ ; /* 0x0000004004087810 */
/* 0x000fc60007f7e0ff */
/*0780*/ FFMA R7, -R7, c[0x0][0x170], R10 ; /* 0x00005c0007077a23 */
/* 0x004fe2000000010a */
/*0790*/ IADD3 R10, P2, R2, 0x40, RZ ; /* 0x00000040020a7810 */
/* 0x000fe40007f5e0ff */
/*07a0*/ IADD3.X R9, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff097210 */
/* 0x000fe40001ffe4ff */
/*07b0*/ IADD3.X R11, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff0b7210 */
/* 0x002fe200017fe4ff */
/*07c0*/ STG.E [R4.64+0x3c], R7 ; /* 0x00003c0704007986 */
/* 0x0001e2000c10190c */
/*07d0*/ MOV R2, R10 ; /* 0x0000000a00027202 */
/* 0x000fe40000000f00 */
/*07e0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fe40000000f00 */
/*07f0*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x001fe20000000f00 */
/*0800*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*0810*/ @P1 BRA 0x160 ; /* 0xfffff94000001947 */
/* 0x000fea000383ffff */
/*0820*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0830*/ @!P1 BRA 0xbe0 ; /* 0x000003a000009947 */
/* 0x000fea0003800000 */
/*0840*/ LDG.E R7, [R2.64] ; /* 0x0000000c02077981 */
/* 0x000ea8000c1e1900 */
/*0850*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040c02087981 */
/* 0x000ea8000c1e1900 */
/*0860*/ LDG.E R10, [R4.64] ; /* 0x0000000c040a7981 */
/* 0x000ee8000c1e1900 */
/*0870*/ LDG.E R11, [R4.64+0x4] ; /* 0x0000040c040b7981 */
/* 0x000f28000c1e1900 */
/*0880*/ LDG.E R13, [R4.64+0x8] ; /* 0x0000080c040d7981 */
/* 0x000f62000c1e1900 */
/*0890*/ FADD R7, -R7, R8 ; /* 0x0000000807077221 */
/* 0x004fc80000000100 */
/*08a0*/ FFMA R7, -R7, c[0x0][0x170], R10 ; /* 0x00005c0007077a23 */
/* 0x008fe4000000010a */
/*08b0*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c0c040a7981 */
/* 0x000ea8000c1e1900 */
/*08c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe8000c10190c */
/*08d0*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040c02087981 */
/* 0x000ee8000c1e1900 */
/*08e0*/ LDG.E R9, [R2.64+0x8] ; /* 0x0000080c02097981 */
/* 0x000ee4000c1e1900 */
/*08f0*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*0900*/ FFMA R11, -R8, c[0x0][0x170], R11 ; /* 0x00005c00080b7a23 */
/* 0x010fca000000010b */
/*0910*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0001e8000c10190c */
/*0920*/ LDG.E R8, [R2.64+0x8] ; /* 0x0000080c02087981 */
/* 0x000ee8000c1e1900 */
/*0930*/ LDG.E R9, [R2.64+0xc] ; /* 0x00000c0c02097981 */
/* 0x000ee8000c1e1900 */
/*0940*/ LDG.E R11, [R4.64+0x10] ; /* 0x0000100c040b7981 */
/* 0x001f22000c1e1900 */
/*0950*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*0960*/ FFMA R13, -R8, c[0x0][0x170], R13 ; /* 0x00005c00080d7a23 */
/* 0x020fca000000010d */
/*0970*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x0001e8000c10190c */
/*0980*/ LDG.E R7, [R2.64+0xc] ; /* 0x00000c0c02077981 */
/* 0x000ee8000c1e1900 */
/*0990*/ LDG.E R8, [R2.64+0x10] ; /* 0x0000100c02087981 */
/* 0x000ee8000c1e1900 */
/*09a0*/ LDG.E R13, [R4.64+0x14] ; /* 0x0000140c040d7981 */
/* 0x001f62000c1e1900 */
/*09b0*/ FADD R7, -R7, R8 ; /* 0x0000000807077221 */
/* 0x008fc80000000100 */
/*09c0*/ FFMA R7, -R7, c[0x0][0x170], R10 ; /* 0x00005c0007077a23 */
/* 0x004fe4000000010a */
/*09d0*/ LDG.E R10, [R4.64+0x18] ; /* 0x0000180c040a7981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ STG.E [R4.64+0xc], R7 ; /* 0x00000c0704007986 */
/* 0x000fe8000c10190c */
/*09f0*/ LDG.E R8, [R2.64+0x10] ; /* 0x0000100c02087981 */
/* 0x000ee8000c1e1900 */
/*0a00*/ LDG.E R9, [R2.64+0x14] ; /* 0x0000140c02097981 */
/* 0x000ee4000c1e1900 */
/*0a10*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*0a20*/ FFMA R11, -R8, c[0x0][0x170], R11 ; /* 0x00005c00080b7a23 */
/* 0x010fca000000010b */
/*0a30*/ STG.E [R4.64+0x10], R11 ; /* 0x0000100b04007986 */
/* 0x0001e8000c10190c */
/*0a40*/ LDG.E R8, [R2.64+0x14] ; /* 0x0000140c02087981 */
/* 0x000ee8000c1e1900 */
/*0a50*/ LDG.E R9, [R2.64+0x18] ; /* 0x0000180c02097981 */
/* 0x000ee8000c1e1900 */
/*0a60*/ LDG.E R11, [R4.64+0x1c] ; /* 0x00001c0c040b7981 */
/* 0x001f22000c1e1900 */
/*0a70*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*0a80*/ FFMA R13, -R8, c[0x0][0x170], R13 ; /* 0x00005c00080d7a23 */
/* 0x020fca000000010d */
/*0a90*/ STG.E [R4.64+0x14], R13 ; /* 0x0000140d04007986 */
/* 0x000fe8000c10190c */
/*0aa0*/ LDG.E R7, [R2.64+0x18] ; /* 0x0000180c02077981 */
/* 0x000ee8000c1e1900 */
/*0ab0*/ LDG.E R8, [R2.64+0x1c] ; /* 0x00001c0c02087981 */
/* 0x000ee4000c1e1900 */
/*0ac0*/ FADD R7, -R7, R8 ; /* 0x0000000807077221 */
/* 0x008fc80000000100 */
/*0ad0*/ FFMA R7, -R7, c[0x0][0x170], R10 ; /* 0x00005c0007077a23 */
/* 0x004fca000000010a */
/*0ae0*/ STG.E [R4.64+0x18], R7 ; /* 0x0000180704007986 */
/* 0x000fe8000c10190c */
/*0af0*/ LDG.E R9, [R2.64+0x20] ; /* 0x0000200c02097981 */
/* 0x0000a8000c1e1900 */
/*0b00*/ LDG.E R8, [R2.64+0x1c] ; /* 0x00001c0c02087981 */
/* 0x0000a2000c1e1900 */
/*0b10*/ IADD3 R10, P1, R2, 0x20, RZ ; /* 0x00000020020a7810 */
/* 0x000fe40007f3e0ff */
/*0b20*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0b30*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0b40*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0b50*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x001fe40000ffe4ff */
/*0b60*/ MOV R2, R10 ; /* 0x0000000a00027202 */
/* 0x000fe20000000f00 */
/*0b70*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x004fc80000000100 */
/*0b80*/ FFMA R11, -R8, c[0x0][0x170], R11 ; /* 0x00005c00080b7a23 */
/* 0x010fe2000000010b */
/*0b90*/ IADD3 R8, P2, R4, 0x20, RZ ; /* 0x0000002004087810 */
/* 0x000fc80007f5e0ff */
/*0ba0*/ IADD3.X R9, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff097210 */
/* 0x000fe200017fe4ff */
/*0bb0*/ STG.E [R4.64+0x1c], R11 ; /* 0x00001c0b04007986 */
/* 0x0001e4000c10190c */
/*0bc0*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x001fe40000000f00 */
/*0bd0*/ MOV R5, R9 ; /* 0x0000000900057202 */
/* 0x000fe40000000f00 */
/*0be0*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0bf0*/ @!P0 BRA 0xe40 ; /* 0x0000024000008947 */
/* 0x000fea0003800000 */
/*0c00*/ LDG.E R7, [R2.64] ; /* 0x0000000c02077981 */
/* 0x000ea8000c1e1900 */
/*0c10*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040c02087981 */
/* 0x000ea8000c1e1900 */
/*0c20*/ LDG.E R10, [R4.64] ; /* 0x0000000c040a7981 */
/* 0x000ee8000c1e1900 */
/*0c30*/ LDG.E R11, [R4.64+0x4] ; /* 0x0000040c040b7981 */
/* 0x000f28000c1e1900 */
/*0c40*/ LDG.E R13, [R4.64+0x8] ; /* 0x0000080c040d7981 */
/* 0x000f62000c1e1900 */
/*0c50*/ FADD R7, -R7, R8 ; /* 0x0000000807077221 */
/* 0x004fc80000000100 */
/*0c60*/ FFMA R7, -R7, c[0x0][0x170], R10 ; /* 0x00005c0007077a23 */
/* 0x008fe4000000010a */
/*0c70*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c0c040a7981 */
/* 0x000ea8000c1e1900 */
/*0c80*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c10190c */
/*0c90*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040c02087981 */
/* 0x000ee8000c1e1900 */
/*0ca0*/ LDG.E R9, [R2.64+0x8] ; /* 0x0000080c02097981 */
/* 0x000ee4000c1e1900 */
/*0cb0*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*0cc0*/ FFMA R11, -R8, c[0x0][0x170], R11 ; /* 0x00005c00080b7a23 */
/* 0x010fca000000010b */
/*0cd0*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0003e8000c10190c */
/*0ce0*/ LDG.E R8, [R2.64+0x8] ; /* 0x0000080c02087981 */
/* 0x000ee8000c1e1900 */
/*0cf0*/ LDG.E R9, [R2.64+0xc] ; /* 0x00000c0c02097981 */
/* 0x000ee4000c1e1900 */
/*0d00*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x008fc80000000100 */
/*0d10*/ FFMA R13, -R8, c[0x0][0x170], R13 ; /* 0x00005c00080d7a23 */
/* 0x020fca000000010d */
/*0d20*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x000fe8000c10190c */
/*0d30*/ LDG.E R8, [R2.64+0x10] ; /* 0x0000100c02087981 */
/* 0x000ee8000c1e1900 */
/*0d40*/ LDG.E R7, [R2.64+0xc] ; /* 0x00000c0c02077981 */
/* 0x001ee2000c1e1900 */
/*0d50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0d60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0d70*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0d80*/ FADD R7, -R7, R8 ; /* 0x0000000807077221 */
/* 0x008fe20000000100 */
/*0d90*/ IADD3 R8, P2, R4, 0x10, RZ ; /* 0x0000001004087810 */
/* 0x000fc60007f5e0ff */
/*0da0*/ FFMA R7, -R7, c[0x0][0x170], R10 ; /* 0x00005c0007077a23 */
/* 0x004fe2000000010a */
/*0db0*/ IADD3 R10, P1, R2, 0x10, RZ ; /* 0x00000010020a7810 */
/* 0x000fe40007f3e0ff */
/*0dc0*/ IADD3.X R9, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff097210 */
/* 0x000fe400017fe4ff */
/*0dd0*/ IADD3.X R11, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff0b7210 */
/* 0x002fe20000ffe4ff */
/*0de0*/ STG.E [R4.64+0xc], R7 ; /* 0x00000c0704007986 */
/* 0x0001e2000c10190c */
/*0df0*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000a */
/*0e00*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fe40000000f00 */
/*0e10*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x001fc40000000f00 */
/*0e20*/ MOV R5, R9 ; /* 0x0000000900057202 */
/* 0x000fe20000000f00 */
/*0e30*/ @P0 BRA 0xc00 ; /* 0xfffffdc000000947 */
/* 0x000fea000383ffff */
/*0e40*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0e50*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0e60*/ UIADD3 UR5, UR4, 0x1, URZ ; /* 0x0000000104057890 */
/* 0x000fe4000fffe03f */
/*0e70*/ UMOV UR10, 0x4 ; /* 0x00000004000a7882 */
/* 0x000fe40000000000 */
/*0e80*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe40000000a00 */
/*0e90*/ ULDC.64 UR8, c[0x0][0x160] ; /* 0x0000580000087ab9 */
/* 0x000fe40000000a00 */
/*0ea0*/ UIMAD.WIDE UR6, UR5, UR10, UR6 ; /* 0x0000000a050672a5 */
/* 0x000fe4000f8e0206 */
/*0eb0*/ UIMAD.WIDE UR4, UR4, UR10, UR8 ; /* 0x0000000a040472a5 */
/* 0x000fc8000f8e0208 */
/*0ec0*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fe40008000f00 */
/*0ed0*/ MOV R6, UR4 ; /* 0x0000000400067c02 */
/* 0x000fe20008000f00 */
/*0ee0*/ IMAD.U32 R7, RZ, RZ, UR5 ; /* 0x00000005ff077e24 */
/* 0x000fe2000f8e00ff */
/*0ef0*/ MOV R3, UR7 ; /* 0x0000000700037c02 */
/* 0x000fe40008000f00 */
/*0f00*/ MOV R8, UR4 ; /* 0x0000000400087c02 */
/* 0x000fe40008000f00 */
/*0f10*/ MOV R2, UR6 ; /* 0x0000000600027c02 */
/* 0x000fe40008000f00 */
/*0f20*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fc40008000f00 */
/*0f30*/ MOV R9, UR5 ; /* 0x0000000500097c02 */
/* 0x000fe40008000f00 */
/*0f40*/ MOV R3, R5 ; /* 0x0000000500037202 */
/* 0x000fe40000000f00 */
/*0f50*/ MOV R8, R6 ; /* 0x0000000600087202 */
/* 0x000fc80000000f00 */
/*0f60*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x000fe20000000f00 */
/*0f70*/ LDG.E R6, [R2.64+-0x4] ; /* 0xfffffc0c02067981 */
/* 0x0000a2000c1e1900 */
/*0f80*/ MOV R5, R9 ; /* 0x0000000900057202 */
/* 0x000fc60000000f00 */
/*0f90*/ LDG.E R7, [R2.64] ; /* 0x0000000c02077981 */
/* 0x0000a8000c1e1900 */
/*0fa0*/ LDG.E R9, [R4.64] ; /* 0x0000000c04097981 */
/* 0x000ee2000c1e1900 */
/*0fb0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*0fc0*/ IADD3 R8, P2, R4, 0x4, RZ ; /* 0x0000000404087810 */
/* 0x000fe40007f5e0ff */
/*0fd0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0fe0*/ IADD3 R2, P1, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fc80007f3e0ff */
/*0ff0*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x000fe20000ffe4ff */
/*1000*/ FADD R6, -R6, R7 ; /* 0x0000000706067221 */
/* 0x004fc80000000100 */
/*1010*/ FFMA R9, -R6, c[0x0][0x170], R9 ; /* 0x00005c0006097a23 */
/* 0x008fca0000000109 */
/*1020*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c10190c */
/*1030*/ IADD3.X R9, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff097210 */
/* 0x001fe200017fe4ff */
/*1040*/ @P0 BRA 0xf60 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*1050*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1060*/ BRA 0x1060; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000554e0_00000000-6_Hy.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3677:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3677:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14Hy_init_malloci
.type _Z14Hy_init_malloci, @function
_Z14Hy_init_malloci:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movslq %edi, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, Hy(%rip)
movq %rbx, %rsi
leaq dev_Hy(%rip), %rdi
call cudaMalloc@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z14Hy_init_malloci, .-_Z14Hy_init_malloci
.globl _Z19Hy_init_assignValuei
.type _Z19Hy_init_assignValuei, @function
_Z19Hy_init_assignValuei:
.LFB3671:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L6
movslq %edi, %rdi
leaq 0(,%rdi,4), %rcx
movl $0, %eax
.L7:
movq Hy(%rip), %rdx
movl $0x00000000, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L7
.L6:
movss .LC1(%rip), %xmm1
mulss dz(%rip), %xmm1
movss dt(%rip), %xmm0
divss %xmm1, %xmm0
movss %xmm0, coe_Hy(%rip)
ret
.cfi_endproc
.LFE3671:
.size _Z19Hy_init_assignValuei, .-_Z19Hy_init_assignValuei
.globl _Z7Hy_initi
.type _Z7Hy_initi, @function
_Z7Hy_initi:
.LFB3669:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl %edi, size_Hy(%rip)
call _Z14Hy_init_malloci
movl size_Hy(%rip), %edi
call _Z19Hy_init_assignValuei
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z7Hy_initi, .-_Z7Hy_initi
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Hy: size = "
.LC3:
.string "coe_Hy = "
.LC4:
.string "Hy: "
.LC5:
.string "\t"
.text
.globl _Z11Hy_checkouti
.type _Z11Hy_checkouti, @function
_Z11Hy_checkouti:
.LFB3672:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebp
movl $11, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L22
cmpb $0, 56(%r12)
je .L13
movzbl 67(%r12), %esi
.L14:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $9, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd coe_Hy(%rip), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movl $4, %edx
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
testl %ebp, %ebp
jle .L15
movslq %ebp, %rbp
salq $2, %rbp
movl $0, %ebx
leaq _ZSt4cout(%rip), %r13
leaq .LC5(%rip), %r12
.L16:
movq Hy(%rip), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, %rbp
jne .L16
.L15:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L23
cmpb $0, 56(%rbx)
je .L18
movzbl 67(%rbx), %esi
.L19:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L13:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L14
.L23:
call _ZSt16__throw_bad_castv@PLT
.L18:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L19
.cfi_endproc
.LFE3672:
.size _Z11Hy_checkouti, .-_Z11Hy_checkouti
.globl _Z23Hy_transfer_host_devicei
.type _Z23Hy_transfer_host_devicei, @function
_Z23Hy_transfer_host_devicei:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movslq %edi, %rdx
salq $2, %rdx
movl $1, %ecx
movq Hy(%rip), %rsi
movq dev_Hy(%rip), %rdi
call cudaMemcpy@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _Z23Hy_transfer_host_devicei, .-_Z23Hy_transfer_host_devicei
.globl _Z23Hy_transfer_device_hosti
.type _Z23Hy_transfer_device_hosti, @function
_Z23Hy_transfer_device_hosti:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movslq %edi, %rdx
salq $2, %rdx
movl $2, %ecx
movq dev_Hy(%rip), %rsi
movq Hy(%rip), %rdi
call cudaMemcpy@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _Z23Hy_transfer_device_hosti, .-_Z23Hy_transfer_device_hosti
.globl _Z37__device_stub__Z13Hy_cmp_kernelPfS_fiPfS_fi
.type _Z37__device_stub__Z13Hy_cmp_kernelPfS_fiPfS_fi, @function
_Z37__device_stub__Z13Hy_cmp_kernelPfS_fiPfS_fi:
.LFB3699:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13Hy_cmp_kernelPfS_fi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z37__device_stub__Z13Hy_cmp_kernelPfS_fiPfS_fi, .-_Z37__device_stub__Z13Hy_cmp_kernelPfS_fiPfS_fi
.globl _Z13Hy_cmp_kernelPfS_fi
.type _Z13Hy_cmp_kernelPfS_fi, @function
_Z13Hy_cmp_kernelPfS_fi:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13Hy_cmp_kernelPfS_fiPfS_fi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z13Hy_cmp_kernelPfS_fi, .-_Z13Hy_cmp_kernelPfS_fi
.section .rodata.str1.1
.LC6:
.string "_Z13Hy_cmp_kernelPfS_fi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z13Hy_cmp_kernelPfS_fi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 900245945
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Hy.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
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