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stringclasses 7
values | input
stringlengths 10
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You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z6vecAddPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPdS_S_i
.globl _Z6vecAddPdS_S_i
.p2align 8
.type _Z6vecAddPdS_S_i,@function
_Z6vecAddPdS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPdS_S_i, .Lfunc_end0-_Z6vecAddPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecAddPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0010506f_00000000-6_1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6vecAddPdS_S_iPdS_S_i
.type _Z30__device_stub__Z6vecAddPdS_S_iPdS_S_i, @function
_Z30__device_stub__Z6vecAddPdS_S_iPdS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z6vecAddPdS_S_iPdS_S_i, .-_Z30__device_stub__Z6vecAddPdS_S_iPdS_S_i
.globl _Z6vecAddPdS_S_i
.type _Z6vecAddPdS_S_i, @function
_Z6vecAddPdS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6vecAddPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6vecAddPdS_S_i, .-_Z6vecAddPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " %f + %f =%f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $800, %edi
call malloc@PLT
movq %rax, %r12
movl $800, %edi
call malloc@PLT
movq %rax, %rbp
movl $800, %edi
call malloc@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $800, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $800, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $800, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, 0(%rbp,%rax,8)
movsd %xmm0, (%r12,%rax,8)
addq $1, %rax
cmpq $100, %rax
jne .L12
movl $1, %ecx
movl $800, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $800, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $10, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $800, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %r14
.L14:
movsd (%r12,%rbx), %xmm0
movsd 0(%r13,%rbx), %xmm2
movsd 0(%rbp,%rbx), %xmm1
movq %r14, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq $800, %rbx
jne .L14
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $100, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z6vecAddPdS_S_iPdS_S_i
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6vecAddPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "1.hip"
.globl _Z21__device_stub__vecAddPdS_S_i # -- Begin function _Z21__device_stub__vecAddPdS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPdS_S_i,@function
_Z21__device_stub__vecAddPdS_S_i: # @_Z21__device_stub__vecAddPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__vecAddPdS_S_i, .Lfunc_end0-_Z21__device_stub__vecAddPdS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $800, %edi # imm = 0x320
callq malloc
movq %rax, %rbx
movl $800, %edi # imm = 0x320
callq malloc
movq %rax, %r14
movl $800, %edi # imm = 0x320
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
leaq 16(%rsp), %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
leaq 8(%rsp), %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%r14,%rax,8)
movsd %xmm0, (%rbx,%rax,8)
incq %rax
cmpq $100, %rax
jne .LBB1_1
# %bb.2:
movq 24(%rsp), %rdi
movl $800, %edx # imm = 0x320
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $800, %edx # imm = 0x320
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967306, %rdi # imm = 0x10000000A
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $100, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6vecAddPdS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $800, %edx # imm = 0x320
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movsd (%rbx,%r12,8), %xmm0 # xmm0 = mem[0],zero
movsd (%r14,%r12,8), %xmm1 # xmm1 = mem[0],zero
movsd (%r15,%r12,8), %xmm2 # xmm2 = mem[0],zero
movl $.L.str, %edi
movb $3, %al
callq printf
incq %r12
cmpq $100, %r12
jne .LBB1_5
# %bb.6:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecAddPdS_S_i,@object # @_Z6vecAddPdS_S_i
.section .rodata,"a",@progbits
.globl _Z6vecAddPdS_S_i
.p2align 3, 0x0
_Z6vecAddPdS_S_i:
.quad _Z21__device_stub__vecAddPdS_S_i
.size _Z6vecAddPdS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " %f + %f =%f\n"
.size .L.str, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecAddPdS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include<iostream>
#include<cuda.h>
/*
Using CUDA warp level primitives
all threads in a warp are executed in SIMT fashioni
compute bound workloads
criteria
------------
performance
numerical accuracy and
thread-safety
3 topics
------------
floating point operations
intrinsic and standard functions
atomic operations
*/
__global__
void float_precision(float* f, double* d){
int tid = blockDim.x * blockIdx.x + threadIdx.x;
*f = 12.1;
*d = 12.1;
}
void precision(){
std::cout << "Testing single and double precision differences in CUDA. \n";
// Accuracy
double d = 12.1;
float f = 12.1;
printf("Host single precision representation of 12. 1 : %.32f\n", f);
printf("Host double precision representation of 12. 1 : %.32f\n", d);
double* device_d;
float* device_f;
double host_device_d;
float host_device_f;
cudaMalloc((void **) &device_f, sizeof(float));
cudaMalloc((void **) &device_d, sizeof(double));
float_precision<<<1,32>>>(device_f, device_d);
cudaMemcpy(&host_device_f, device_f, sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(&host_device_d, device_d, sizeof(double), cudaMemcpyDeviceToHost);
printf("Device single precision representation of 12. 1 : %.32f\n", host_device_f);
printf("Device double precision representation of 12. 1 : %.32f\n", host_device_d);
if (host_device_d == d) printf("Double representation is same for host and device.\n");
if (host_device_f == f) printf("Float representation is same for host and device.\n");
printf("Difference between single and double precision : %.32f\n", d-f);
// Performance
// Correctness
}
void intrinsic(){
}
int main(int argc, char** argv){
//precision();
intrinsic();
return 0;
}
|
code for sm_80
Function : _Z15float_precisionPfPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ HFMA2.MMA R6, -RZ, RZ, 0.2249755859375, 0.2249755859375 ; /* 0x33333333ff067435 */
/* 0x000fe200000001ff */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4141999a ; /* 0x4141999aff097424 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0050*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R7, 0x40283333 ; /* 0x4028333300077802 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*00a0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x000fe2000c101b04 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include<iostream>
#include<cuda.h>
/*
Using CUDA warp level primitives
all threads in a warp are executed in SIMT fashioni
compute bound workloads
criteria
------------
performance
numerical accuracy and
thread-safety
3 topics
------------
floating point operations
intrinsic and standard functions
atomic operations
*/
__global__
void float_precision(float* f, double* d){
int tid = blockDim.x * blockIdx.x + threadIdx.x;
*f = 12.1;
*d = 12.1;
}
void precision(){
std::cout << "Testing single and double precision differences in CUDA. \n";
// Accuracy
double d = 12.1;
float f = 12.1;
printf("Host single precision representation of 12. 1 : %.32f\n", f);
printf("Host double precision representation of 12. 1 : %.32f\n", d);
double* device_d;
float* device_f;
double host_device_d;
float host_device_f;
cudaMalloc((void **) &device_f, sizeof(float));
cudaMalloc((void **) &device_d, sizeof(double));
float_precision<<<1,32>>>(device_f, device_d);
cudaMemcpy(&host_device_f, device_f, sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(&host_device_d, device_d, sizeof(double), cudaMemcpyDeviceToHost);
printf("Device single precision representation of 12. 1 : %.32f\n", host_device_f);
printf("Device double precision representation of 12. 1 : %.32f\n", host_device_d);
if (host_device_d == d) printf("Double representation is same for host and device.\n");
if (host_device_f == f) printf("Float representation is same for host and device.\n");
printf("Difference between single and double precision : %.32f\n", d-f);
// Performance
// Correctness
}
void intrinsic(){
}
int main(int argc, char** argv){
//precision();
intrinsic();
return 0;
}
|
.file "tmpxft_00036eba_00000000-6_cuPrimitives.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9intrinsicv
.type _Z9intrinsicv, @function
_Z9intrinsicv:
.LFB3670:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE3670:
.size _Z9intrinsicv, .-_Z9intrinsicv
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE3671:
.size main, .-main
.globl _Z37__device_stub__Z15float_precisionPfPdPfPd
.type _Z37__device_stub__Z15float_precisionPfPdPfPd, @function
_Z37__device_stub__Z15float_precisionPfPdPfPd:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15float_precisionPfPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z37__device_stub__Z15float_precisionPfPdPfPd, .-_Z37__device_stub__Z15float_precisionPfPdPfPd
.globl _Z15float_precisionPfPd
.type _Z15float_precisionPfPd, @function
_Z15float_precisionPfPd:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z15float_precisionPfPdPfPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z15float_precisionPfPd, .-_Z15float_precisionPfPd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Testing single and double precision differences in CUDA. \n"
.align 8
.LC2:
.string "Host single precision representation of 12. 1 : %.32f\n"
.align 8
.LC4:
.string "Host double precision representation of 12. 1 : %.32f\n"
.align 8
.LC5:
.string "Device single precision representation of 12. 1 : %.32f\n"
.align 8
.LC6:
.string "Device double precision representation of 12. 1 : %.32f\n"
.align 8
.LC7:
.string "Double representation is same for host and device.\n"
.align 8
.LC9:
.string "Float representation is same for host and device.\n"
.align 8
.LC11:
.string "Difference between single and double precision : %.32f\n"
.text
.globl _Z9precisionv
.type _Z9precisionv, @function
_Z9precisionv:
.LFB3669:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $58, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd .LC1(%rip), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd .LC3(%rip), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl $32, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L14:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq 40(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 40(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd .LC3(%rip), %xmm0
ucomisd 40(%rsp), %xmm0
jp .L15
je .L24
.L15:
movss 28(%rsp), %xmm0
ucomiss .LC8(%rip), %xmm0
jp .L17
je .L25
.L17:
movsd .LC10(%rip), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z37__device_stub__Z15float_precisionPfPdPfPd
jmp .L14
.L24:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L15
.L25:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L17
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z9precisionv, .-_Z9precisionv
.section .rodata.str1.1,"aMS",@progbits,1
.LC12:
.string "_Z15float_precisionPfPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z15float_precisionPfPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 1073741824
.long 1076376371
.align 8
.LC3:
.long 858993459
.long 1076376371
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC8:
.long 1094818202
.section .rodata.cst8
.align 8
.LC10:
.long -1711276032
.long -1097229927
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include<iostream>
#include<cuda.h>
/*
Using CUDA warp level primitives
all threads in a warp are executed in SIMT fashioni
compute bound workloads
criteria
------------
performance
numerical accuracy and
thread-safety
3 topics
------------
floating point operations
intrinsic and standard functions
atomic operations
*/
__global__
void float_precision(float* f, double* d){
int tid = blockDim.x * blockIdx.x + threadIdx.x;
*f = 12.1;
*d = 12.1;
}
void precision(){
std::cout << "Testing single and double precision differences in CUDA. \n";
// Accuracy
double d = 12.1;
float f = 12.1;
printf("Host single precision representation of 12. 1 : %.32f\n", f);
printf("Host double precision representation of 12. 1 : %.32f\n", d);
double* device_d;
float* device_f;
double host_device_d;
float host_device_f;
cudaMalloc((void **) &device_f, sizeof(float));
cudaMalloc((void **) &device_d, sizeof(double));
float_precision<<<1,32>>>(device_f, device_d);
cudaMemcpy(&host_device_f, device_f, sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(&host_device_d, device_d, sizeof(double), cudaMemcpyDeviceToHost);
printf("Device single precision representation of 12. 1 : %.32f\n", host_device_f);
printf("Device double precision representation of 12. 1 : %.32f\n", host_device_d);
if (host_device_d == d) printf("Double representation is same for host and device.\n");
if (host_device_f == f) printf("Float representation is same for host and device.\n");
printf("Difference between single and double precision : %.32f\n", d-f);
// Performance
// Correctness
}
void intrinsic(){
}
int main(int argc, char** argv){
//precision();
intrinsic();
return 0;
}
|
#include<iostream>
#include<hip/hip_runtime.h>
/*
Using CUDA warp level primitives
all threads in a warp are executed in SIMT fashioni
compute bound workloads
criteria
------------
performance
numerical accuracy and
thread-safety
3 topics
------------
floating point operations
intrinsic and standard functions
atomic operations
*/
__global__
void float_precision(float* f, double* d){
int tid = blockDim.x * blockIdx.x + threadIdx.x;
*f = 12.1;
*d = 12.1;
}
void precision(){
std::cout << "Testing single and double precision differences in CUDA. \n";
// Accuracy
double d = 12.1;
float f = 12.1;
printf("Host single precision representation of 12. 1 : %.32f\n", f);
printf("Host double precision representation of 12. 1 : %.32f\n", d);
double* device_d;
float* device_f;
double host_device_d;
float host_device_f;
hipMalloc((void **) &device_f, sizeof(float));
hipMalloc((void **) &device_d, sizeof(double));
float_precision<<<1,32>>>(device_f, device_d);
hipMemcpy(&host_device_f, device_f, sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(&host_device_d, device_d, sizeof(double), hipMemcpyDeviceToHost);
printf("Device single precision representation of 12. 1 : %.32f\n", host_device_f);
printf("Device double precision representation of 12. 1 : %.32f\n", host_device_d);
if (host_device_d == d) printf("Double representation is same for host and device.\n");
if (host_device_f == f) printf("Float representation is same for host and device.\n");
printf("Difference between single and double precision : %.32f\n", d-f);
// Performance
// Correctness
}
void intrinsic(){
}
int main(int argc, char** argv){
//precision();
intrinsic();
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include<iostream>
#include<hip/hip_runtime.h>
/*
Using CUDA warp level primitives
all threads in a warp are executed in SIMT fashioni
compute bound workloads
criteria
------------
performance
numerical accuracy and
thread-safety
3 topics
------------
floating point operations
intrinsic and standard functions
atomic operations
*/
__global__
void float_precision(float* f, double* d){
int tid = blockDim.x * blockIdx.x + threadIdx.x;
*f = 12.1;
*d = 12.1;
}
void precision(){
std::cout << "Testing single and double precision differences in CUDA. \n";
// Accuracy
double d = 12.1;
float f = 12.1;
printf("Host single precision representation of 12. 1 : %.32f\n", f);
printf("Host double precision representation of 12. 1 : %.32f\n", d);
double* device_d;
float* device_f;
double host_device_d;
float host_device_f;
hipMalloc((void **) &device_f, sizeof(float));
hipMalloc((void **) &device_d, sizeof(double));
float_precision<<<1,32>>>(device_f, device_d);
hipMemcpy(&host_device_f, device_f, sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(&host_device_d, device_d, sizeof(double), hipMemcpyDeviceToHost);
printf("Device single precision representation of 12. 1 : %.32f\n", host_device_f);
printf("Device double precision representation of 12. 1 : %.32f\n", host_device_d);
if (host_device_d == d) printf("Double representation is same for host and device.\n");
if (host_device_f == f) printf("Float representation is same for host and device.\n");
printf("Difference between single and double precision : %.32f\n", d-f);
// Performance
// Correctness
}
void intrinsic(){
}
int main(int argc, char** argv){
//precision();
intrinsic();
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15float_precisionPfPd
.globl _Z15float_precisionPfPd
.p2align 8
.type _Z15float_precisionPfPd,@function
_Z15float_precisionPfPd:
s_load_b128 s[0:3], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0x4141999a
v_mov_b32_e32 v0, 0x33333333
v_mov_b32_e32 v1, 0x40283333
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_store_b32 v2, v3, s[0:1]
global_store_b64 v2, v[0:1], s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15float_precisionPfPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15float_precisionPfPd, .Lfunc_end0-_Z15float_precisionPfPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15float_precisionPfPd
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z15float_precisionPfPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include<iostream>
#include<hip/hip_runtime.h>
/*
Using CUDA warp level primitives
all threads in a warp are executed in SIMT fashioni
compute bound workloads
criteria
------------
performance
numerical accuracy and
thread-safety
3 topics
------------
floating point operations
intrinsic and standard functions
atomic operations
*/
__global__
void float_precision(float* f, double* d){
int tid = blockDim.x * blockIdx.x + threadIdx.x;
*f = 12.1;
*d = 12.1;
}
void precision(){
std::cout << "Testing single and double precision differences in CUDA. \n";
// Accuracy
double d = 12.1;
float f = 12.1;
printf("Host single precision representation of 12. 1 : %.32f\n", f);
printf("Host double precision representation of 12. 1 : %.32f\n", d);
double* device_d;
float* device_f;
double host_device_d;
float host_device_f;
hipMalloc((void **) &device_f, sizeof(float));
hipMalloc((void **) &device_d, sizeof(double));
float_precision<<<1,32>>>(device_f, device_d);
hipMemcpy(&host_device_f, device_f, sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(&host_device_d, device_d, sizeof(double), hipMemcpyDeviceToHost);
printf("Device single precision representation of 12. 1 : %.32f\n", host_device_f);
printf("Device double precision representation of 12. 1 : %.32f\n", host_device_d);
if (host_device_d == d) printf("Double representation is same for host and device.\n");
if (host_device_f == f) printf("Float representation is same for host and device.\n");
printf("Difference between single and double precision : %.32f\n", d-f);
// Performance
// Correctness
}
void intrinsic(){
}
int main(int argc, char** argv){
//precision();
intrinsic();
return 0;
}
|
.text
.file "cuPrimitives.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__float_precisionPfPd # -- Begin function _Z30__device_stub__float_precisionPfPd
.p2align 4, 0x90
.type _Z30__device_stub__float_precisionPfPd,@function
_Z30__device_stub__float_precisionPfPd: # @_Z30__device_stub__float_precisionPfPd
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15float_precisionPfPd, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z30__device_stub__float_precisionPfPd, .Lfunc_end0-_Z30__device_stub__float_precisionPfPd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9precisionv
.LCPI1_0:
.quad 0x4028333340000000 # double 12.100000381469727
.LCPI1_1:
.quad 0x4028333333333333 # double 12.1
.LCPI1_3:
.quad 0xbe9999999a000000 # double -3.8146972691777137E-7
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI1_2:
.long 0x4141999a # float 12.1000004
.text
.globl _Z9precisionv
.p2align 4, 0x90
.type _Z9precisionv,@function
_Z9precisionv: # @_Z9precisionv
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $58, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
movb $1, %al
callq printf
movsd .LCPI1_1(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %edi
movb $1, %al
callq printf
leaq 40(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 48(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 40(%rsp), %rax
movq 48(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
leaq 96(%rsp), %rax
movq %rax, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 24(%rsp)
movq %rsp, %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z15float_precisionPfPd, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 40(%rsp), %rsi
movq %rsp, %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq 48(%rsp), %rsi
leaq 16(%rsp), %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
movss (%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movsd 16(%rsp), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.4, %edi
movb $1, %al
callq printf
movsd 16(%rsp), %xmm0 # xmm0 = mem[0],zero
ucomisd .LCPI1_1(%rip), %xmm0
jne .LBB1_4
jp .LBB1_4
# %bb.3:
movl $.Lstr, %edi
callq puts@PLT
.LBB1_4:
movss (%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss .LCPI1_2(%rip), %xmm0
jne .LBB1_6
jp .LBB1_6
# %bb.5:
movl $.Lstr.1, %edi
callq puts@PLT
.LBB1_6:
movsd .LCPI1_3(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.7, %edi
movb $1, %al
callq printf
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9precisionv, .Lfunc_end1-_Z9precisionv
.cfi_endproc
# -- End function
.globl _Z9intrinsicv # -- Begin function _Z9intrinsicv
.p2align 4, 0x90
.type _Z9intrinsicv,@function
_Z9intrinsicv: # @_Z9intrinsicv
.cfi_startproc
# %bb.0:
retq
.Lfunc_end2:
.size _Z9intrinsicv, .Lfunc_end2-_Z9intrinsicv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15float_precisionPfPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15float_precisionPfPd,@object # @_Z15float_precisionPfPd
.section .rodata,"a",@progbits
.globl _Z15float_precisionPfPd
.p2align 3, 0x0
_Z15float_precisionPfPd:
.quad _Z30__device_stub__float_precisionPfPd
.size _Z15float_precisionPfPd, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Testing single and double precision differences in CUDA. \n"
.size .L.str, 59
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Host single precision representation of 12. 1 : %.32f\n"
.size .L.str.1, 55
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Host double precision representation of 12. 1 : %.32f\n"
.size .L.str.2, 55
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Device single precision representation of 12. 1 : %.32f\n"
.size .L.str.3, 57
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Device double precision representation of 12. 1 : %.32f\n"
.size .L.str.4, 57
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Difference between single and double precision : %.32f\n"
.size .L.str.7, 56
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15float_precisionPfPd"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Double representation is same for host and device."
.size .Lstr, 51
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Float representation is same for host and device."
.size .Lstr.1, 50
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__float_precisionPfPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15float_precisionPfPd
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z15float_precisionPfPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ HFMA2.MMA R6, -RZ, RZ, 0.2249755859375, 0.2249755859375 ; /* 0x33333333ff067435 */
/* 0x000fe200000001ff */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4141999a ; /* 0x4141999aff097424 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0050*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R7, 0x40283333 ; /* 0x4028333300077802 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*00a0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x000fe2000c101b04 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15float_precisionPfPd
.globl _Z15float_precisionPfPd
.p2align 8
.type _Z15float_precisionPfPd,@function
_Z15float_precisionPfPd:
s_load_b128 s[0:3], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0x4141999a
v_mov_b32_e32 v0, 0x33333333
v_mov_b32_e32 v1, 0x40283333
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_store_b32 v2, v3, s[0:1]
global_store_b64 v2, v[0:1], s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15float_precisionPfPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15float_precisionPfPd, .Lfunc_end0-_Z15float_precisionPfPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15float_precisionPfPd
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z15float_precisionPfPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00036eba_00000000-6_cuPrimitives.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9intrinsicv
.type _Z9intrinsicv, @function
_Z9intrinsicv:
.LFB3670:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE3670:
.size _Z9intrinsicv, .-_Z9intrinsicv
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE3671:
.size main, .-main
.globl _Z37__device_stub__Z15float_precisionPfPdPfPd
.type _Z37__device_stub__Z15float_precisionPfPdPfPd, @function
_Z37__device_stub__Z15float_precisionPfPdPfPd:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15float_precisionPfPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z37__device_stub__Z15float_precisionPfPdPfPd, .-_Z37__device_stub__Z15float_precisionPfPdPfPd
.globl _Z15float_precisionPfPd
.type _Z15float_precisionPfPd, @function
_Z15float_precisionPfPd:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z15float_precisionPfPdPfPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z15float_precisionPfPd, .-_Z15float_precisionPfPd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Testing single and double precision differences in CUDA. \n"
.align 8
.LC2:
.string "Host single precision representation of 12. 1 : %.32f\n"
.align 8
.LC4:
.string "Host double precision representation of 12. 1 : %.32f\n"
.align 8
.LC5:
.string "Device single precision representation of 12. 1 : %.32f\n"
.align 8
.LC6:
.string "Device double precision representation of 12. 1 : %.32f\n"
.align 8
.LC7:
.string "Double representation is same for host and device.\n"
.align 8
.LC9:
.string "Float representation is same for host and device.\n"
.align 8
.LC11:
.string "Difference between single and double precision : %.32f\n"
.text
.globl _Z9precisionv
.type _Z9precisionv, @function
_Z9precisionv:
.LFB3669:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $58, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd .LC1(%rip), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd .LC3(%rip), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl $32, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L14:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq 40(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 40(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd .LC3(%rip), %xmm0
ucomisd 40(%rsp), %xmm0
jp .L15
je .L24
.L15:
movss 28(%rsp), %xmm0
ucomiss .LC8(%rip), %xmm0
jp .L17
je .L25
.L17:
movsd .LC10(%rip), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z37__device_stub__Z15float_precisionPfPdPfPd
jmp .L14
.L24:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L15
.L25:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L17
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z9precisionv, .-_Z9precisionv
.section .rodata.str1.1,"aMS",@progbits,1
.LC12:
.string "_Z15float_precisionPfPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z15float_precisionPfPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 1073741824
.long 1076376371
.align 8
.LC3:
.long 858993459
.long 1076376371
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC8:
.long 1094818202
.section .rodata.cst8
.align 8
.LC10:
.long -1711276032
.long -1097229927
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "cuPrimitives.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__float_precisionPfPd # -- Begin function _Z30__device_stub__float_precisionPfPd
.p2align 4, 0x90
.type _Z30__device_stub__float_precisionPfPd,@function
_Z30__device_stub__float_precisionPfPd: # @_Z30__device_stub__float_precisionPfPd
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15float_precisionPfPd, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z30__device_stub__float_precisionPfPd, .Lfunc_end0-_Z30__device_stub__float_precisionPfPd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9precisionv
.LCPI1_0:
.quad 0x4028333340000000 # double 12.100000381469727
.LCPI1_1:
.quad 0x4028333333333333 # double 12.1
.LCPI1_3:
.quad 0xbe9999999a000000 # double -3.8146972691777137E-7
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI1_2:
.long 0x4141999a # float 12.1000004
.text
.globl _Z9precisionv
.p2align 4, 0x90
.type _Z9precisionv,@function
_Z9precisionv: # @_Z9precisionv
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $58, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
movb $1, %al
callq printf
movsd .LCPI1_1(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %edi
movb $1, %al
callq printf
leaq 40(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 48(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 40(%rsp), %rax
movq 48(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
leaq 96(%rsp), %rax
movq %rax, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 24(%rsp)
movq %rsp, %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z15float_precisionPfPd, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 40(%rsp), %rsi
movq %rsp, %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq 48(%rsp), %rsi
leaq 16(%rsp), %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
movss (%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movsd 16(%rsp), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.4, %edi
movb $1, %al
callq printf
movsd 16(%rsp), %xmm0 # xmm0 = mem[0],zero
ucomisd .LCPI1_1(%rip), %xmm0
jne .LBB1_4
jp .LBB1_4
# %bb.3:
movl $.Lstr, %edi
callq puts@PLT
.LBB1_4:
movss (%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss .LCPI1_2(%rip), %xmm0
jne .LBB1_6
jp .LBB1_6
# %bb.5:
movl $.Lstr.1, %edi
callq puts@PLT
.LBB1_6:
movsd .LCPI1_3(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.7, %edi
movb $1, %al
callq printf
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9precisionv, .Lfunc_end1-_Z9precisionv
.cfi_endproc
# -- End function
.globl _Z9intrinsicv # -- Begin function _Z9intrinsicv
.p2align 4, 0x90
.type _Z9intrinsicv,@function
_Z9intrinsicv: # @_Z9intrinsicv
.cfi_startproc
# %bb.0:
retq
.Lfunc_end2:
.size _Z9intrinsicv, .Lfunc_end2-_Z9intrinsicv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15float_precisionPfPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15float_precisionPfPd,@object # @_Z15float_precisionPfPd
.section .rodata,"a",@progbits
.globl _Z15float_precisionPfPd
.p2align 3, 0x0
_Z15float_precisionPfPd:
.quad _Z30__device_stub__float_precisionPfPd
.size _Z15float_precisionPfPd, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Testing single and double precision differences in CUDA. \n"
.size .L.str, 59
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Host single precision representation of 12. 1 : %.32f\n"
.size .L.str.1, 55
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Host double precision representation of 12. 1 : %.32f\n"
.size .L.str.2, 55
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Device single precision representation of 12. 1 : %.32f\n"
.size .L.str.3, 57
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Device double precision representation of 12. 1 : %.32f\n"
.size .L.str.4, 57
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Difference between single and double precision : %.32f\n"
.size .L.str.7, 56
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15float_precisionPfPd"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Double representation is same for host and device."
.size .Lstr, 51
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Float representation is same for host and device."
.size .Lstr.1, 50
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__float_precisionPfPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15float_precisionPfPd
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
//pass
//--blockDim=2048 --gridDim=64
struct s {
float x, y, z;
};
__global__ void foo(s *q) {
s p = { 0.0f, 0.0f, 0.0f };
q[threadIdx.x + blockIdx.x * blockDim.x] = p;
}
|
code for sm_80
Function : _Z3fooP1s
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 7.152557373046875e-07 ; /* 0x0000000cff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0005 */
/*0070*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101904 */
/*0080*/ STG.E [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe8000c101904 */
/*0090*/ STG.E [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
//pass
//--blockDim=2048 --gridDim=64
struct s {
float x, y, z;
};
__global__ void foo(s *q) {
s p = { 0.0f, 0.0f, 0.0f };
q[threadIdx.x + blockIdx.x * blockDim.x] = p;
}
|
.file "tmpxft_0017d448_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z3fooP1sP1s
.type _Z23__device_stub__Z3fooP1sP1s, @function
_Z23__device_stub__Z3fooP1sP1s:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3fooP1s(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z23__device_stub__Z3fooP1sP1s, .-_Z23__device_stub__Z3fooP1sP1s
.globl _Z3fooP1s
.type _Z3fooP1s, @function
_Z3fooP1s:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z3fooP1sP1s
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3fooP1s, .-_Z3fooP1s
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3fooP1s"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3fooP1s(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
//pass
//--blockDim=2048 --gridDim=64
struct s {
float x, y, z;
};
__global__ void foo(s *q) {
s p = { 0.0f, 0.0f, 0.0f };
q[threadIdx.x + blockIdx.x * blockDim.x] = p;
}
|
#include <hip/hip_runtime.h>
//pass
//--blockDim=2048 --gridDim=64
struct s {
float x, y, z;
};
__global__ void foo(s *q) {
s p = { 0.0f, 0.0f, 0.0f };
q[threadIdx.x + blockIdx.x * blockDim.x] = p;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
//pass
//--blockDim=2048 --gridDim=64
struct s {
float x, y, z;
};
__global__ void foo(s *q) {
s p = { 0.0f, 0.0f, 0.0f };
q[threadIdx.x + blockIdx.x * blockDim.x] = p;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3fooP1s
.globl _Z3fooP1s
.p2align 8
.type _Z3fooP1s,@function
_Z3fooP1s:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v2, v0
s_delay_alu instid0(VALU_DEP_3)
v_mad_u64_u32 v[3:4], null, v1, 12, s[0:1]
v_mov_b32_e32 v1, v0
global_store_b96 v[3:4], v[0:2], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3fooP1s
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3fooP1s, .Lfunc_end0-_Z3fooP1s
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3fooP1s
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3fooP1s.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
//pass
//--blockDim=2048 --gridDim=64
struct s {
float x, y, z;
};
__global__ void foo(s *q) {
s p = { 0.0f, 0.0f, 0.0f };
q[threadIdx.x + blockIdx.x * blockDim.x] = p;
}
|
.text
.file "kernel.hip"
.globl _Z18__device_stub__fooP1s # -- Begin function _Z18__device_stub__fooP1s
.p2align 4, 0x90
.type _Z18__device_stub__fooP1s,@function
_Z18__device_stub__fooP1s: # @_Z18__device_stub__fooP1s
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3fooP1s, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z18__device_stub__fooP1s, .Lfunc_end0-_Z18__device_stub__fooP1s
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3fooP1s, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3fooP1s,@object # @_Z3fooP1s
.section .rodata,"a",@progbits
.globl _Z3fooP1s
.p2align 3, 0x0
_Z3fooP1s:
.quad _Z18__device_stub__fooP1s
.size _Z3fooP1s, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3fooP1s"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__fooP1s
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3fooP1s
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z3fooP1s
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 7.152557373046875e-07 ; /* 0x0000000cff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0005 */
/*0070*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101904 */
/*0080*/ STG.E [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe8000c101904 */
/*0090*/ STG.E [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3fooP1s
.globl _Z3fooP1s
.p2align 8
.type _Z3fooP1s,@function
_Z3fooP1s:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v2, v0
s_delay_alu instid0(VALU_DEP_3)
v_mad_u64_u32 v[3:4], null, v1, 12, s[0:1]
v_mov_b32_e32 v1, v0
global_store_b96 v[3:4], v[0:2], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3fooP1s
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3fooP1s, .Lfunc_end0-_Z3fooP1s
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3fooP1s
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3fooP1s.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0017d448_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z3fooP1sP1s
.type _Z23__device_stub__Z3fooP1sP1s, @function
_Z23__device_stub__Z3fooP1sP1s:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3fooP1s(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z23__device_stub__Z3fooP1sP1s, .-_Z23__device_stub__Z3fooP1sP1s
.globl _Z3fooP1s
.type _Z3fooP1s, @function
_Z3fooP1s:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z3fooP1sP1s
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3fooP1s, .-_Z3fooP1s
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3fooP1s"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3fooP1s(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "kernel.hip"
.globl _Z18__device_stub__fooP1s # -- Begin function _Z18__device_stub__fooP1s
.p2align 4, 0x90
.type _Z18__device_stub__fooP1s,@function
_Z18__device_stub__fooP1s: # @_Z18__device_stub__fooP1s
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3fooP1s, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z18__device_stub__fooP1s, .Lfunc_end0-_Z18__device_stub__fooP1s
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3fooP1s, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3fooP1s,@object # @_Z3fooP1s
.section .rodata,"a",@progbits
.globl _Z3fooP1s
.p2align 3, 0x0
_Z3fooP1s:
.quad _Z18__device_stub__fooP1s
.size _Z3fooP1s, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3fooP1s"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__fooP1s
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3fooP1s
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <iostream>
#include <stdio.h>
#include <cuda.h>
#include <cstdlib>
#include <curand_kernel.h>
#include <bits/stdc++.h>
using namespace std;
const int numberNodes = 439;
struct Agent{
int size;
float fitness;
int genome[numberNodes];
};
/* Arrange the N elements of ARRAY in random order.
Only effective if N is much smaller than RAND_MAX;
if this may not be the case, use a better random
number generator. */
void shuffle(int *array, size_t n)
{
if (n > 1)
{
size_t i;
for (i = 0; i < n - 1; i++)
{
size_t j = i + rand() / (RAND_MAX / (n - i) + 1);
int t = array[j];
array[j] = array[i];
array[i] = t;
}
}
}
Agent RandomAgent(int size){
int g[size];
for (int i = 0; i < size ; i++){
g[i] = i;
}
shuffle(g,size);
struct Agent RAgent{};
RAgent.size = size;
RAgent.fitness = 0.0;
for (int i = 0; i < size ; i++){
RAgent.genome[i] = g[i];
}
return RAgent;
}
__device__ Agent NewAgent (const int genome[]){
struct Agent nw{};
nw.size = numberNodes;
nw.fitness = 0.0;
for (int i = 0; i < numberNodes ; i++){
nw.genome[i] = genome[i];
}
return nw;
}
__device__ void Mutate(struct Agent *agent, curandState state) {
unsigned int p1 = curand(&state) % numberNodes;
while (true) {
unsigned int p2 = curand(&state) % numberNodes;
if (p1 != p2) {
int temp = agent->genome[p1];
agent->genome[p1] = agent->genome[p2];
agent->genome[p2] = temp;
break;
}
}
}
__device__ void CrossPermutation(int a[], int b[], curandState state){
unsigned int crossPoint = curand(&state)%(numberNodes-2)+1;
unsigned int tempSize = crossPoint+1;
int tempA[numberNodes];
int tempB[numberNodes];
for(int i = 0;i<numberNodes;i++){
tempA[i]=0;
tempB[i]=0;
}
for(int i = tempSize;i<numberNodes;i++){
tempA[a[i]]=1;
tempB[b[i]]=1;
}
unsigned int idenA = tempSize;
unsigned int idenB = tempSize;
for (int i = 0;i < numberNodes ; i++) {
if ( tempA[b[i]] ==1 ) {
a[idenA] = b[i];
idenA++;
}
}
for (int i = 0;i < numberNodes ; i++) {
if ( tempB[a[i]] ==1 ) {
b[idenB] = a[i];
idenB++;
}
}
};
__device__ void FitnessFunction(struct Agent *agent, const float *distance){
float fitness = 0;
for (int i = 0; i < numberNodes ; i++){
if (i < numberNodes - 1 ){
fitness += distance[agent->genome[i]+agent->genome[i+1]*numberNodes];
}else{
fitness += distance[agent->genome[i]+agent->genome[0]*numberNodes];
}
}
agent->fitness = fitness;
}
__device__ Agent GetBest(struct Agent a1,struct Agent a2,struct Agent a3){
if(a1.fitness < a2.fitness && a1.fitness < a3.fitness){
return a1;
}else if (a2.fitness < a3.fitness){
return a2;
}else{
return a3;
}
}
void PrintAgent(struct Agent agent){
cout<<agent.fitness<< " ";
for (int i : agent.genome){
cout<< i << " ";
}
cout << endl;
}
__global__ void EvaluateGen(float *DDistance, struct Agent *DIPopulation, struct Agent *DFPopulation, int popSize, float rate) {
unsigned int tId = threadIdx.x + (blockIdx.x * blockDim.x);
curandState state;
curand_init((unsigned long long)clock() , tId, 0, &state);
if(tId < popSize){
FitnessFunction(&DIPopulation[tId], DDistance);
if(curand_uniform(&state) < rate){
unsigned int pair = curand(&state)%popSize;
int n1[numberNodes];
int n2[numberNodes];
memcpy(n1,DIPopulation[pair].genome,sizeof(int)*numberNodes);
memcpy(n2,DIPopulation[tId].genome,sizeof(int)*numberNodes);
CrossPermutation(n1,n2,state);
struct Agent a1 = NewAgent(n1);
struct Agent a2 = NewAgent(n2);
Mutate(&a1, state);
Mutate(&a2, state);
FitnessFunction(&a1,DDistance);
FitnessFunction(&a2,DDistance);
DFPopulation[tId] = GetBest(a1,a2,DIPopulation[tId]);
}else{
DFPopulation[tId] = DIPopulation[tId];
}
}
}
void CondensedResult(float current[], float *results, float mean, int popSize, int generation){
float median = 0, best = 0, worst = 0, stDeviation = 0;
sort(current,current +popSize);
best = current[0];
worst = current[popSize-1];
if (popSize % 2 == 0){
median = (current[int(popSize/2)]+current[int((popSize/2)+1)])/2;
} else{
median = current[int((popSize/2)+1)];
}
for(int i = 0;i<popSize;i++){
stDeviation += pow(current[i]-mean,2);
}
stDeviation /= popSize;
stDeviation = sqrt(stDeviation);
results[generation*5] = best;
results[generation*5+1] = worst;
results[generation*5+2] = mean;
results[generation*5+3] = median;
results[generation*5+4] = stDeviation;
}
extern "C" {
void evaluateGen(float *distance, float *results, int popSize, int generations, float rate) {
srand(time(nullptr));
struct Agent population[popSize];
for (int i = 0; i< popSize;i++){
population[i] = RandomAgent(numberNodes);
}
unsigned long DDistanceSize = (numberNodes*numberNodes)*sizeof(float);
float* DDistance;
cudaMalloc((void**)&DDistance,DDistanceSize);
cudaMemcpy(DDistance,distance,DDistanceSize,cudaMemcpyHostToDevice);
unsigned long DPopulationSize = (sizeof(int)+sizeof(float)+(sizeof(int)*numberNodes))*popSize;
struct Agent* DIPopulation;
cudaMalloc((void**)&DIPopulation,DPopulationSize);
struct Agent* DFPopulation;
cudaMalloc((void**)&DFPopulation,DPopulationSize);
cudaMemcpy(DIPopulation,population,DPopulationSize,cudaMemcpyHostToDevice);
for (int i = 0; i < generations;i++){
float popResults[popSize];
float mean = 0.0;
if(i%2==0){
EvaluateGen<<<128,int(popSize/128)+1>>>(DDistance, DIPopulation, DFPopulation, popSize, rate);
cudaMemcpy(population,DFPopulation,DPopulationSize,cudaMemcpyDeviceToHost);
}else{
EvaluateGen<<<128,int(popSize/128)+1>>>(DDistance, DFPopulation, DIPopulation, popSize, rate);
cudaMemcpy(population,DIPopulation,DPopulationSize,cudaMemcpyDeviceToHost);
}
for (int j = 0; j< popSize;j++){
mean += population[j].fitness;
popResults[j] = population[j].fitness;
// PrintAgent(population[j]);
}
mean /= popSize;
CondensedResult(popResults,results,mean, popSize,i);
}
cudaFree(DDistance);
cudaFree(DIPopulation);
cudaFree(DFPopulation);
}
}
|
.file "tmpxft_0005c897_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB11085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE11085:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7shufflePim
.type _Z7shufflePim, @function
_Z7shufflePim:
.LFB11073:
.cfi_startproc
endbr64
cmpq $1, %rsi
jbe .L8
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %rbp
movq %rsi, %r13
leaq -1(%rsi), %r14
movl $0, %ebx
movl $2147483647, %r12d
.L5:
call rand@PLT
movslq %eax, %rcx
movq %r13, %rsi
subq %rbx, %rsi
movq %r12, %rax
movl $0, %edx
divq %rsi
leaq 1(%rax), %rsi
movq %rcx, %rax
movl $0, %edx
divq %rsi
addq %rbx, %rax
leaq 0(%rbp,%rax,4), %rax
movl (%rax), %edx
movl 0(%rbp,%rbx,4), %ecx
movl %ecx, (%rax)
movl %edx, 0(%rbp,%rbx,4)
addq $1, %rbx
cmpq %r14, %rbx
jne .L5
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
ret
.cfi_endproc
.LFE11073:
.size _Z7shufflePim, .-_Z7shufflePim
.globl _Z11RandomAgenti
.type _Z11RandomAgenti, @function
_Z11RandomAgenti:
.LFB11074:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $16, %rsp
.cfi_offset 14, -24
.cfi_offset 13, -32
.cfi_offset 12, -40
.cfi_offset 3, -48
movq %rdi, %r13
movl %esi, %r14d
movq %fs:40, %rax
movq %rax, -40(%rbp)
xorl %eax, %eax
movslq %esi, %rax
leaq 0(,%rax,4), %r12
leaq 15(%r12), %rdx
movq %rdx, %rsi
andq $-16, %rsi
andq $-4096, %rdx
movq %rsp, %rcx
subq %rdx, %rcx
.L12:
cmpq %rcx, %rsp
je .L13
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L12
.L13:
movq %rsi, %rdx
andl $4095, %edx
subq %rdx, %rsp
testq %rdx, %rdx
je .L14
orq $0, -8(%rsp,%rdx)
.L14:
movq %rsp, %rbx
testl %r14d, %r14d
jle .L15
movl $0, %esi
.L16:
movl %esi, (%rbx,%rsi,4)
addq $1, %rsi
cmpq %rsi, %rax
jne .L16
movq %rbx, %rdi
call _Z7shufflePim
movq $0, 0(%r13)
movq $0, 1756(%r13)
leaq 8(%r13), %rdi
andq $-8, %rdi
movq %r13, %rcx
subq %rdi, %rcx
addl $1764, %ecx
shrl $3, %ecx
movl %ecx, %ecx
movl $0, %eax
rep stosq
movl %r14d, 0(%r13)
leaq 8(%r13), %rcx
.L17:
movl (%rbx,%rax), %edx
movl %edx, (%rcx,%rax)
addq $4, %rax
cmpq %rax, %r12
jne .L17
.L11:
movq -40(%rbp), %rax
subq %fs:40, %rax
jne .L23
movq %r13, %rax
leaq -32(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L15:
.cfi_restore_state
movq %rax, %rsi
movq %rbx, %rdi
call _Z7shufflePim
movq $0, 0(%r13)
movq $0, 1756(%r13)
leaq 8(%r13), %rdi
andq $-8, %rdi
movq %r13, %rcx
subq %rdi, %rcx
addl $1764, %ecx
shrl $3, %ecx
movl %ecx, %ecx
movl $0, %eax
rep stosq
movl %r14d, 0(%r13)
jmp .L11
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE11074:
.size _Z11RandomAgenti, .-_Z11RandomAgenti
.globl _Z8NewAgentPKi
.type _Z8NewAgentPKi, @function
_Z8NewAgentPKi:
.LFB11075:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE11075:
.size _Z8NewAgentPKi, .-_Z8NewAgentPKi
.globl _Z6MutateP5Agent17curandStateXORWOW
.type _Z6MutateP5Agent17curandStateXORWOW, @function
_Z6MutateP5Agent17curandStateXORWOW:
.LFB11076:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE11076:
.size _Z6MutateP5Agent17curandStateXORWOW, .-_Z6MutateP5Agent17curandStateXORWOW
.globl _Z16CrossPermutationPiS_17curandStateXORWOW
.type _Z16CrossPermutationPiS_17curandStateXORWOW, @function
_Z16CrossPermutationPiS_17curandStateXORWOW:
.LFB11077:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE11077:
.size _Z16CrossPermutationPiS_17curandStateXORWOW, .-_Z16CrossPermutationPiS_17curandStateXORWOW
.globl _Z15FitnessFunctionP5AgentPKf
.type _Z15FitnessFunctionP5AgentPKf, @function
_Z15FitnessFunctionP5AgentPKf:
.LFB11078:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE11078:
.size _Z15FitnessFunctionP5AgentPKf, .-_Z15FitnessFunctionP5AgentPKf
.globl _Z7GetBest5AgentS_S_
.type _Z7GetBest5AgentS_S_, @function
_Z7GetBest5AgentS_S_:
.LFB11079:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE11079:
.size _Z7GetBest5AgentS_S_, .-_Z7GetBest5AgentS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl _Z10PrintAgent5Agent
.type _Z10PrintAgent5Agent, @function
_Z10PrintAgent5Agent:
.LFB11080:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC0(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
leaq 56(%rsp), %rbx
leaq 1812(%rsp), %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC0(%rip), %rbp
.L35:
movl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %rbp, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L35
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L41
cmpb $0, 56(%rbx)
je .L37
movzbl 67(%rbx), %eax
.L38:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L37:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L38
.cfi_endproc
.LFE11080:
.size _Z10PrintAgent5Agent, .-_Z10PrintAgent5Agent
.globl _Z43__device_stub__Z11EvaluateGenPfP5AgentS1_ifPfP5AgentS1_if
.type _Z43__device_stub__Z11EvaluateGenPfP5AgentS1_ifPfP5AgentS1_if, @function
_Z43__device_stub__Z11EvaluateGenPfP5AgentS1_ifPfP5AgentS1_if:
.LFB11107:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movss %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L46
.L42:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L47
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11EvaluateGenPfP5AgentS1_if(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L42
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE11107:
.size _Z43__device_stub__Z11EvaluateGenPfP5AgentS1_ifPfP5AgentS1_if, .-_Z43__device_stub__Z11EvaluateGenPfP5AgentS1_ifPfP5AgentS1_if
.globl _Z11EvaluateGenPfP5AgentS1_if
.type _Z11EvaluateGenPfP5AgentS1_if, @function
_Z11EvaluateGenPfP5AgentS1_if:
.LFB11108:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z11EvaluateGenPfP5AgentS1_ifPfP5AgentS1_if
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE11108:
.size _Z11EvaluateGenPfP5AgentS1_if, .-_Z11EvaluateGenPfP5AgentS1_if
.section .rodata.str1.1
.LC1:
.string "_Z11EvaluateGenPfP5AgentS1_if"
.LC2:
.string "precalc_xorwow_matrix"
.LC3:
.string "precalc_xorwow_offset_matrix"
.LC4:
.string "mrg32k3aM1"
.LC5:
.string "mrg32k3aM2"
.LC6:
.string "mrg32k3aM1SubSeq"
.LC7:
.string "mrg32k3aM2SubSeq"
.LC8:
.string "mrg32k3aM1Seq"
.LC9:
.string "mrg32k3aM2Seq"
.LC10:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB11110:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11EvaluateGenPfP5AgentS1_if(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE11110:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZSt25__unguarded_linear_insertIPfN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_,"axG",@progbits,_ZSt25__unguarded_linear_insertIPfN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_,comdat
.weak _ZSt25__unguarded_linear_insertIPfN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_
.type _ZSt25__unguarded_linear_insertIPfN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_, @function
_ZSt25__unguarded_linear_insertIPfN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_:
.LFB12658:
.cfi_startproc
endbr64
movss (%rdi), %xmm1
leaq -4(%rdi), %rax
movss -4(%rdi), %xmm0
comiss %xmm1, %xmm0
jbe .L53
.L55:
movss %xmm0, 4(%rax)
movq %rax, %rdi
subq $4, %rax
movss (%rax), %xmm0
comiss %xmm1, %xmm0
ja .L55
.L53:
movss %xmm1, (%rdi)
ret
.cfi_endproc
.LFE12658:
.size _ZSt25__unguarded_linear_insertIPfN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_, .-_ZSt25__unguarded_linear_insertIPfN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_
.section .text._ZSt16__insertion_sortIPfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_,"axG",@progbits,_ZSt16__insertion_sortIPfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_,comdat
.weak _ZSt16__insertion_sortIPfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_
.type _ZSt16__insertion_sortIPfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_, @function
_ZSt16__insertion_sortIPfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_:
.LFB12552:
.cfi_startproc
endbr64
cmpq %rsi, %rdi
je .L70
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %rbp
movq %rsi, %r13
leaq 4(%rdi), %rbx
cmpq %rbx, %rsi
je .L58
movl $4, %r14d
jmp .L65
.L62:
je .L73
.L63:
movl %r12d, 0(%rbp)
.L64:
addq $4, %rbx
cmpq %rbx, %r13
je .L58
.L65:
movl (%rbx), %r12d
movss 0(%rbp), %xmm0
movd %r12d, %xmm1
comiss %xmm1, %xmm0
jbe .L68
movq %rbx, %rdx
subq %rbp, %rdx
cmpq $4, %rdx
jle .L62
movq %r14, %rdi
subq %rdx, %rdi
addq %rbx, %rdi
movq %rbp, %rsi
call memmove@PLT
jmp .L63
.L73:
movss %xmm0, (%rbx)
jmp .L63
.L68:
movq %rbx, %rdi
call _ZSt25__unguarded_linear_insertIPfN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_
jmp .L64
.L58:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L70:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
ret
.cfi_endproc
.LFE12552:
.size _ZSt16__insertion_sortIPfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_, .-_ZSt16__insertion_sortIPfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_
.section .text._ZSt13__adjust_heapIPflfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_T0_S5_T1_T2_,"axG",@progbits,_ZSt13__adjust_heapIPflfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_T0_S5_T1_T2_,comdat
.weak _ZSt13__adjust_heapIPflfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_T0_S5_T1_T2_
.type _ZSt13__adjust_heapIPflfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_T0_S5_T1_T2_, @function
_ZSt13__adjust_heapIPflfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_T0_S5_T1_T2_:
.LFB12787:
.cfi_startproc
endbr64
movq %rdi, %rcx
movq %rsi, %r8
leaq -1(%rdx), %rax
movq %rax, %r9
shrq $63, %r9
addq %rax, %r9
sarq %r9
cmpq %r9, %rsi
jge .L75
movq %rsi, %rdi
jmp .L78
.L76:
movss (%rcx,%rax,4), %xmm1
movss %xmm1, (%rcx,%rdi,4)
cmpq %r9, %rax
jge .L90
movq %rax, %rdi
.L78:
leaq 1(%rdi), %rsi
leaq (%rsi,%rsi), %rax
movss -4(%rcx,%rsi,8), %xmm1
comiss (%rcx,%rsi,8), %xmm1
jbe .L76
subq $1, %rax
jmp .L76
.L90:
testb $1, %dl
jne .L79
.L83:
subq $2, %rdx
movq %rdx, %rsi
shrq $63, %rsi
addq %rsi, %rdx
sarq %rdx
cmpq %rax, %rdx
je .L91
.L79:
leaq -1(%rax), %rdx
movq %rdx, %rsi
shrq $63, %rsi
addq %rdx, %rsi
sarq %rsi
cmpq %r8, %rax
jg .L82
jmp .L80
.L91:
leaq 2(%rax,%rax), %rdx
movss -4(%rcx,%rdx,4), %xmm1
movss %xmm1, (%rcx,%rax,4)
leaq -1(%rdx), %rax
jmp .L79
.L85:
movq %rdx, %rsi
.L82:
movss (%rcx,%rsi,4), %xmm1
comiss %xmm1, %xmm0
jbe .L80
movss %xmm1, (%rcx,%rax,4)
leaq -1(%rsi), %rdx
movq %rdx, %rax
shrq $63, %rax
addq %rdx, %rax
sarq %rax
movq %rax, %rdx
movq %rsi, %rax
cmpq %rsi, %r8
jl .L85
.L80:
movss %xmm0, (%rcx,%rax,4)
ret
.L75:
movq %rsi, %rax
testb $1, %dl
jne .L80
movq %r8, %rax
jmp .L83
.cfi_endproc
.LFE12787:
.size _ZSt13__adjust_heapIPflfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_T0_S5_T1_T2_, .-_ZSt13__adjust_heapIPflfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_T0_S5_T1_T2_
.section .text._ZSt16__introsort_loopIPflN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_,"axG",@progbits,_ZSt16__introsort_loopIPflN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_,comdat
.weak _ZSt16__introsort_loopIPflN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_
.type _ZSt16__introsort_loopIPflN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_, @function
_ZSt16__introsort_loopIPflN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_:
.LFB12411:
.cfi_startproc
endbr64
movq %rsi, %rax
subq %rdi, %rax
cmpq $64, %rax
jle .L141
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movq %rdx, %r12
testq %rdx, %rdx
jne .L95
movq %rsi, %rbx
.L119:
sarq $2, %rax
movq %rax, %r12
leaq -2(%rax), %rax
movq %rax, %r13
shrq $63, %r13
addq %rax, %r13
sarq %r13
jmp .L96
.L141:
.cfi_def_cfa_offset 8
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.L142:
.cfi_def_cfa_offset 48
.cfi_offset 3, -40
.cfi_offset 6, -32
.cfi_offset 12, -24
.cfi_offset 13, -16
subq $1, %r13
.L96:
movss 0(%rbp,%r13,4), %xmm0
movq %r12, %rdx
movq %r13, %rsi
movq %rbp, %rdi
call _ZSt13__adjust_heapIPflfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_T0_S5_T1_T2_
testq %r13, %r13
jne .L142
movq %rbx, %rax
subq %rbp, %rax
cmpq $4, %rax
jle .L92
.L97:
subq $4, %rbx
movss (%rbx), %xmm0
movss 0(%rbp), %xmm1
movss %xmm1, (%rbx)
movq %rbx, %r12
subq %rbp, %r12
movq %r12, %rdx
sarq $2, %rdx
movl $0, %esi
movq %rbp, %rdi
call _ZSt13__adjust_heapIPflfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_T0_S5_T1_T2_
cmpq $4, %r12
jg .L97
.L92:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L134:
.cfi_restore_state
comiss %xmm1, %xmm2
jbe .L135
movss 0(%rbp), %xmm0
movss %xmm2, 0(%rbp)
movss %xmm0, -4(%rsi)
jmp .L106
.L135:
movss 0(%rbp), %xmm0
movss %xmm1, 0(%rbp)
movss %xmm0, 4(%rbp)
jmp .L106
.L133:
movss -4(%rsi), %xmm2
comiss %xmm1, %xmm2
jbe .L136
movss 0(%rbp), %xmm0
movss %xmm1, 0(%rbp)
movss %xmm0, 4(%rbp)
jmp .L106
.L136:
comiss %xmm0, %xmm2
jbe .L137
movss 0(%rbp), %xmm0
movss %xmm2, 0(%rbp)
movss %xmm0, -4(%rsi)
jmp .L106
.L137:
movss 0(%rbp), %xmm1
movss %xmm0, 0(%rbp)
movss %xmm1, (%rax)
jmp .L106
.L143:
movq %r12, %rdx
movq %rbx, %rdi
call _ZSt16__introsort_loopIPflN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_
movq %rbx, %rax
subq %rbp, %rax
cmpq $64, %rax
jle .L92
testq %r12, %r12
je .L119
movq %rbx, %rsi
.L95:
subq $1, %r12
movq %rax, %rdx
sarq $2, %rdx
shrq $63, %rax
addq %rdx, %rax
sarq %rax
leaq 0(%rbp,%rax,4), %rax
leaq 4(%rbp), %rbx
movss 4(%rbp), %xmm1
movss (%rax), %xmm0
comiss %xmm1, %xmm0
jbe .L133
movss -4(%rsi), %xmm2
comiss %xmm0, %xmm2
jbe .L134
movss 0(%rbp), %xmm1
movss %xmm0, 0(%rbp)
movss %xmm1, (%rax)
.L106:
movq %rsi, %rdx
.L103:
movss (%rbx), %xmm1
movss 0(%rbp), %xmm0
comiss %xmm1, %xmm0
jbe .L111
.L113:
addq $4, %rbx
movss (%rbx), %xmm1
comiss %xmm1, %xmm0
ja .L113
.L111:
leaq -4(%rdx), %rax
movss -4(%rdx), %xmm2
comiss %xmm0, %xmm2
jbe .L114
.L116:
subq $4, %rax
movss (%rax), %xmm2
comiss %xmm0, %xmm2
ja .L116
.L114:
cmpq %rax, %rbx
jnb .L143
movss %xmm2, (%rbx)
movss %xmm1, (%rax)
addq $4, %rbx
movq %rax, %rdx
jmp .L103
.cfi_endproc
.LFE12411:
.size _ZSt16__introsort_loopIPflN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_, .-_ZSt16__introsort_loopIPflN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_
.text
.globl _Z15CondensedResultPfS_fii
.type _Z15CondensedResultPfS_fii, @function
_Z15CondensedResultPfS_fii:
.LFB11081:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
movq %rsi, %r13
movss %xmm0, 4(%rsp)
movl %edx, %r12d
movl %ecx, 12(%rsp)
movslq %edx, %r14
salq $2, %r14
leaq (%rdi,%r14), %r15
cmpq %rdi, %r15
je .L145
movq %r14, %rdx
sarq $2, %rdx
movl $64, %eax
je .L146
bsrq %rdx, %rax
xorl $63, %eax
.L146:
movl $63, %edx
subl %eax, %edx
movslq %edx, %rdx
addq %rdx, %rdx
movq %r15, %rsi
movq %rbx, %rdi
call _ZSt16__introsort_loopIPflN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_
cmpq $64, %r14
jle .L147
leaq 64(%rbx), %rbp
movq %rbp, %rsi
movq %rbx, %rdi
call _ZSt16__insertion_sortIPfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_
cmpq %rbp, %r15
je .L145
.L148:
movq %rbp, %rdi
call _ZSt25__unguarded_linear_insertIPfN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_
addq $4, %rbp
cmpq %rbp, %r15
jne .L148
jmp .L145
.L147:
movq %r15, %rsi
movq %rbx, %rdi
call _ZSt16__insertion_sortIPfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_
.L145:
movl (%rbx), %r15d
movl -4(%rbx,%r14), %ebp
testb $1, %r12b
jne .L149
movl %r12d, %eax
shrl $31, %eax
addl %r12d, %eax
sarl %eax
cltq
movss 4(%rbx,%rax,4), %xmm0
addss (%rbx,%rax,4), %xmm0
mulss .LC12(%rip), %xmm0
movss %xmm0, 8(%rsp)
.L150:
testl %r12d, %r12d
jle .L151
movq %rbx, %rax
addq %r14, %rbx
pxor %xmm0, %xmm0
.L152:
movss (%rax), %xmm1
subss 4(%rsp), %xmm1
cvtss2sd %xmm1, %xmm1
mulsd %xmm1, %xmm1
cvtss2sd %xmm0, %xmm0
addsd %xmm0, %xmm1
pxor %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
addq $4, %rax
cmpq %rbx, %rax
jne .L152
pxor %xmm1, %xmm1
cvtsi2ssl %r12d, %xmm1
divss %xmm1, %xmm0
pxor %xmm1, %xmm1
ucomiss %xmm0, %xmm1
ja .L160
.L156:
sqrtss %xmm0, %xmm0
.L155:
movl 12(%rsp), %eax
leal (%rax,%rax,4), %eax
cltq
movl %r15d, 0(%r13,%rax,4)
addq $1, %rax
leaq 0(,%rax,4), %rdx
movl %ebp, 0(%r13,%rax,4)
movss 4(%rsp), %xmm3
movss %xmm3, 4(%r13,%rdx)
movss 8(%rsp), %xmm4
movss %xmm4, 8(%r13,%rdx)
movss %xmm0, 12(%r13,%rdx)
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L149:
.cfi_restore_state
movl %r12d, %eax
shrl $31, %eax
addl %r12d, %eax
sarl %eax
addl $1, %eax
cltq
movss (%rbx,%rax,4), %xmm5
movss %xmm5, 8(%rsp)
jmp .L150
.L160:
call sqrtf@PLT
jmp .L155
.L151:
pxor %xmm1, %xmm1
cvtsi2ssl %r12d, %xmm1
pxor %xmm0, %xmm0
divss %xmm1, %xmm0
jmp .L156
.cfi_endproc
.LFE11081:
.size _Z15CondensedResultPfS_fii, .-_Z15CondensedResultPfS_fii
.globl evaluateGen
.type evaluateGen, @function
evaluateGen:
.LFB11082:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $1912, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rdi, %rbx
movq %rsi, -1912(%rbp)
movl %edx, %r12d
movl %ecx, -1900(%rbp)
movss %xmm0, -1904(%rbp)
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movslq %r12d, %rax
movq %rax, -1920(%rbp)
imulq $1764, %rax, %rax
movq %rax, -1896(%rbp)
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L164:
cmpq %rdx, %rsp
je .L165
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L164
.L165:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L166
orq $0, -8(%rsp,%rax)
.L166:
movq %rsp, %r15
testl %r12d, %r12d
jle .L167
movl $0, %r13d
leaq -1888(%rbp), %r14
movq %rbx, -1928(%rbp)
.L168:
movslq %r13d, %rbx
imulq $1764, %rbx, %rbx
addq %r15, %rbx
movl $439, %esi
movq %r14, %rdi
call _Z11RandomAgenti
movq (%r14), %rax
movq %rax, (%rbx)
movq -132(%rbp), %rax
movq %rax, 1756(%rbx)
leaq 8(%rbx), %rdi
andq $-8, %rdi
subq %rdi, %rbx
movq %r14, %rsi
subq %rbx, %rsi
addl $1764, %ebx
shrl $3, %ebx
movl %ebx, %ecx
rep movsq
addl $1, %r13d
cmpl %r13d, %r12d
jne .L168
movq -1928(%rbp), %rbx
.L167:
leaq -104(%rbp), %rdi
movl $770884, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $770884, %edx
movq %rbx, %rsi
movq -104(%rbp), %rdi
call cudaMemcpy@PLT
leaq -96(%rbp), %rdi
movq -1896(%rbp), %rbx
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -88(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq -96(%rbp), %rdi
call cudaMemcpy@PLT
cmpl $0, -1900(%rbp)
jle .L169
movq -1920(%rbp), %rsi
salq $2, %rsi
leal 127(%r12), %eax
testl %r12d, %r12d
cmovns %r12d, %eax
sarl $7, %eax
addl $1, %eax
movl %eax, -1920(%rbp)
movl $0, %ebx
leaq 15(%rsi), %rax
movq %rax, %rdi
andq $-16, %rdi
movq %rdi, -1944(%rbp)
andq $-4096, %rax
movq %rax, -1928(%rbp)
movq %rsi, -1936(%rbp)
jmp .L180
.L171:
movq -1944(%rbp), %rdi
movq %rdi, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L172
movq %rdi, %rax
andl $4095, %eax
orq $0, -8(%rsp,%rax)
.L172:
movq %rsp, %r13
testb $1, %bl
jne .L173
movl -1920(%rbp), %eax
movl %eax, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $128, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L186
.L174:
movl $2, %ecx
movq -1896(%rbp), %rdx
movq -88(%rbp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
.L178:
pxor %xmm1, %xmm1
testl %r12d, %r12d
jle .L176
leaq 4(%r15), %rdx
movq %r13, %rax
movq -1936(%rbp), %rdi
leaq 0(%r13,%rdi), %rcx
pxor %xmm1, %xmm1
.L179:
movss (%rdx), %xmm0
addss %xmm0, %xmm1
movss %xmm0, (%rax)
addq $1764, %rdx
addq $4, %rax
cmpq %rcx, %rax
jne .L179
.L176:
pxor %xmm0, %xmm0
cvtsi2ssl %r12d, %xmm0
divss %xmm0, %xmm1
movl %ebx, %ecx
movl %r12d, %edx
movaps %xmm1, %xmm0
movq -1912(%rbp), %rsi
movq %r13, %rdi
call _Z15CondensedResultPfS_fii
movq %r14, %rsp
addl $1, %ebx
cmpl %ebx, -1900(%rbp)
je .L169
.L180:
movq %rsp, %r14
movq %rsp, %rax
movq -1928(%rbp), %rsi
subq %rsi, %rax
.L170:
cmpq %rax, %rsp
je .L171
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L170
.L186:
movss -1904(%rbp), %xmm0
movl %r12d, %ecx
movq -88(%rbp), %rdx
movq -96(%rbp), %rsi
movq -104(%rbp), %rdi
call _Z43__device_stub__Z11EvaluateGenPfP5AgentS1_ifPfP5AgentS1_if
jmp .L174
.L173:
movl -1920(%rbp), %eax
movl %eax, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $128, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L187
.L177:
movl $2, %ecx
movq -1896(%rbp), %rdx
movq -96(%rbp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
jmp .L178
.L187:
movss -1904(%rbp), %xmm0
movl %r12d, %ecx
movq -96(%rbp), %rdx
movq -88(%rbp), %rsi
movq -104(%rbp), %rdi
call _Z43__device_stub__Z11EvaluateGenPfP5AgentS1_ifPfP5AgentS1_if
jmp .L177
.L169:
movq -104(%rbp), %rdi
call cudaFree@PLT
movq -96(%rbp), %rdi
call cudaFree@PLT
movq -88(%rbp), %rdi
call cudaFree@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L188
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L188:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE11082:
.size evaluateGen, .-evaluateGen
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC12:
.long 1056964608
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <iostream>
#include <stdio.h>
#include <cuda.h>
#include <cstdlib>
#include <curand_kernel.h>
#include <bits/stdc++.h>
using namespace std;
const int numberNodes = 439;
struct Agent{
int size;
float fitness;
int genome[numberNodes];
};
/* Arrange the N elements of ARRAY in random order.
Only effective if N is much smaller than RAND_MAX;
if this may not be the case, use a better random
number generator. */
void shuffle(int *array, size_t n)
{
if (n > 1)
{
size_t i;
for (i = 0; i < n - 1; i++)
{
size_t j = i + rand() / (RAND_MAX / (n - i) + 1);
int t = array[j];
array[j] = array[i];
array[i] = t;
}
}
}
Agent RandomAgent(int size){
int g[size];
for (int i = 0; i < size ; i++){
g[i] = i;
}
shuffle(g,size);
struct Agent RAgent{};
RAgent.size = size;
RAgent.fitness = 0.0;
for (int i = 0; i < size ; i++){
RAgent.genome[i] = g[i];
}
return RAgent;
}
__device__ Agent NewAgent (const int genome[]){
struct Agent nw{};
nw.size = numberNodes;
nw.fitness = 0.0;
for (int i = 0; i < numberNodes ; i++){
nw.genome[i] = genome[i];
}
return nw;
}
__device__ void Mutate(struct Agent *agent, curandState state) {
unsigned int p1 = curand(&state) % numberNodes;
while (true) {
unsigned int p2 = curand(&state) % numberNodes;
if (p1 != p2) {
int temp = agent->genome[p1];
agent->genome[p1] = agent->genome[p2];
agent->genome[p2] = temp;
break;
}
}
}
__device__ void CrossPermutation(int a[], int b[], curandState state){
unsigned int crossPoint = curand(&state)%(numberNodes-2)+1;
unsigned int tempSize = crossPoint+1;
int tempA[numberNodes];
int tempB[numberNodes];
for(int i = 0;i<numberNodes;i++){
tempA[i]=0;
tempB[i]=0;
}
for(int i = tempSize;i<numberNodes;i++){
tempA[a[i]]=1;
tempB[b[i]]=1;
}
unsigned int idenA = tempSize;
unsigned int idenB = tempSize;
for (int i = 0;i < numberNodes ; i++) {
if ( tempA[b[i]] ==1 ) {
a[idenA] = b[i];
idenA++;
}
}
for (int i = 0;i < numberNodes ; i++) {
if ( tempB[a[i]] ==1 ) {
b[idenB] = a[i];
idenB++;
}
}
};
__device__ void FitnessFunction(struct Agent *agent, const float *distance){
float fitness = 0;
for (int i = 0; i < numberNodes ; i++){
if (i < numberNodes - 1 ){
fitness += distance[agent->genome[i]+agent->genome[i+1]*numberNodes];
}else{
fitness += distance[agent->genome[i]+agent->genome[0]*numberNodes];
}
}
agent->fitness = fitness;
}
__device__ Agent GetBest(struct Agent a1,struct Agent a2,struct Agent a3){
if(a1.fitness < a2.fitness && a1.fitness < a3.fitness){
return a1;
}else if (a2.fitness < a3.fitness){
return a2;
}else{
return a3;
}
}
void PrintAgent(struct Agent agent){
cout<<agent.fitness<< " ";
for (int i : agent.genome){
cout<< i << " ";
}
cout << endl;
}
__global__ void EvaluateGen(float *DDistance, struct Agent *DIPopulation, struct Agent *DFPopulation, int popSize, float rate) {
unsigned int tId = threadIdx.x + (blockIdx.x * blockDim.x);
curandState state;
curand_init((unsigned long long)clock() , tId, 0, &state);
if(tId < popSize){
FitnessFunction(&DIPopulation[tId], DDistance);
if(curand_uniform(&state) < rate){
unsigned int pair = curand(&state)%popSize;
int n1[numberNodes];
int n2[numberNodes];
memcpy(n1,DIPopulation[pair].genome,sizeof(int)*numberNodes);
memcpy(n2,DIPopulation[tId].genome,sizeof(int)*numberNodes);
CrossPermutation(n1,n2,state);
struct Agent a1 = NewAgent(n1);
struct Agent a2 = NewAgent(n2);
Mutate(&a1, state);
Mutate(&a2, state);
FitnessFunction(&a1,DDistance);
FitnessFunction(&a2,DDistance);
DFPopulation[tId] = GetBest(a1,a2,DIPopulation[tId]);
}else{
DFPopulation[tId] = DIPopulation[tId];
}
}
}
void CondensedResult(float current[], float *results, float mean, int popSize, int generation){
float median = 0, best = 0, worst = 0, stDeviation = 0;
sort(current,current +popSize);
best = current[0];
worst = current[popSize-1];
if (popSize % 2 == 0){
median = (current[int(popSize/2)]+current[int((popSize/2)+1)])/2;
} else{
median = current[int((popSize/2)+1)];
}
for(int i = 0;i<popSize;i++){
stDeviation += pow(current[i]-mean,2);
}
stDeviation /= popSize;
stDeviation = sqrt(stDeviation);
results[generation*5] = best;
results[generation*5+1] = worst;
results[generation*5+2] = mean;
results[generation*5+3] = median;
results[generation*5+4] = stDeviation;
}
extern "C" {
void evaluateGen(float *distance, float *results, int popSize, int generations, float rate) {
srand(time(nullptr));
struct Agent population[popSize];
for (int i = 0; i< popSize;i++){
population[i] = RandomAgent(numberNodes);
}
unsigned long DDistanceSize = (numberNodes*numberNodes)*sizeof(float);
float* DDistance;
cudaMalloc((void**)&DDistance,DDistanceSize);
cudaMemcpy(DDistance,distance,DDistanceSize,cudaMemcpyHostToDevice);
unsigned long DPopulationSize = (sizeof(int)+sizeof(float)+(sizeof(int)*numberNodes))*popSize;
struct Agent* DIPopulation;
cudaMalloc((void**)&DIPopulation,DPopulationSize);
struct Agent* DFPopulation;
cudaMalloc((void**)&DFPopulation,DPopulationSize);
cudaMemcpy(DIPopulation,population,DPopulationSize,cudaMemcpyHostToDevice);
for (int i = 0; i < generations;i++){
float popResults[popSize];
float mean = 0.0;
if(i%2==0){
EvaluateGen<<<128,int(popSize/128)+1>>>(DDistance, DIPopulation, DFPopulation, popSize, rate);
cudaMemcpy(population,DFPopulation,DPopulationSize,cudaMemcpyDeviceToHost);
}else{
EvaluateGen<<<128,int(popSize/128)+1>>>(DDistance, DFPopulation, DIPopulation, popSize, rate);
cudaMemcpy(population,DIPopulation,DPopulationSize,cudaMemcpyDeviceToHost);
}
for (int j = 0; j< popSize;j++){
mean += population[j].fitness;
popResults[j] = population[j].fitness;
// PrintAgent(population[j]);
}
mean /= popSize;
CondensedResult(popResults,results,mean, popSize,i);
}
cudaFree(DDistance);
cudaFree(DIPopulation);
cudaFree(DFPopulation);
}
}
|
#include <iostream>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <cstdlib>
#include <hiprand/hiprand_kernel.h>
#include <bits/stdc++.h>
using namespace std;
const int numberNodes = 439;
struct Agent{
int size;
float fitness;
int genome[numberNodes];
};
/* Arrange the N elements of ARRAY in random order.
Only effective if N is much smaller than RAND_MAX;
if this may not be the case, use a better random
number generator. */
void shuffle(int *array, size_t n)
{
if (n > 1)
{
size_t i;
for (i = 0; i < n - 1; i++)
{
size_t j = i + rand() / (RAND_MAX / (n - i) + 1);
int t = array[j];
array[j] = array[i];
array[i] = t;
}
}
}
Agent RandomAgent(int size){
int g[size];
for (int i = 0; i < size ; i++){
g[i] = i;
}
shuffle(g,size);
struct Agent RAgent{};
RAgent.size = size;
RAgent.fitness = 0.0;
for (int i = 0; i < size ; i++){
RAgent.genome[i] = g[i];
}
return RAgent;
}
__device__ Agent NewAgent (const int genome[]){
struct Agent nw{};
nw.size = numberNodes;
nw.fitness = 0.0;
for (int i = 0; i < numberNodes ; i++){
nw.genome[i] = genome[i];
}
return nw;
}
__device__ void Mutate(struct Agent *agent, hiprandState state) {
unsigned int p1 = hiprand(&state) % numberNodes;
while (true) {
unsigned int p2 = hiprand(&state) % numberNodes;
if (p1 != p2) {
int temp = agent->genome[p1];
agent->genome[p1] = agent->genome[p2];
agent->genome[p2] = temp;
break;
}
}
}
__device__ void CrossPermutation(int a[], int b[], hiprandState state){
unsigned int crossPoint = hiprand(&state)%(numberNodes-2)+1;
unsigned int tempSize = crossPoint+1;
int tempA[numberNodes];
int tempB[numberNodes];
for(int i = 0;i<numberNodes;i++){
tempA[i]=0;
tempB[i]=0;
}
for(int i = tempSize;i<numberNodes;i++){
tempA[a[i]]=1;
tempB[b[i]]=1;
}
unsigned int idenA = tempSize;
unsigned int idenB = tempSize;
for (int i = 0;i < numberNodes ; i++) {
if ( tempA[b[i]] ==1 ) {
a[idenA] = b[i];
idenA++;
}
}
for (int i = 0;i < numberNodes ; i++) {
if ( tempB[a[i]] ==1 ) {
b[idenB] = a[i];
idenB++;
}
}
};
__device__ void FitnessFunction(struct Agent *agent, const float *distance){
float fitness = 0;
for (int i = 0; i < numberNodes ; i++){
if (i < numberNodes - 1 ){
fitness += distance[agent->genome[i]+agent->genome[i+1]*numberNodes];
}else{
fitness += distance[agent->genome[i]+agent->genome[0]*numberNodes];
}
}
agent->fitness = fitness;
}
__device__ Agent GetBest(struct Agent a1,struct Agent a2,struct Agent a3){
if(a1.fitness < a2.fitness && a1.fitness < a3.fitness){
return a1;
}else if (a2.fitness < a3.fitness){
return a2;
}else{
return a3;
}
}
void PrintAgent(struct Agent agent){
cout<<agent.fitness<< " ";
for (int i : agent.genome){
cout<< i << " ";
}
cout << endl;
}
__global__ void EvaluateGen(float *DDistance, struct Agent *DIPopulation, struct Agent *DFPopulation, int popSize, float rate) {
unsigned int tId = threadIdx.x + (blockIdx.x * blockDim.x);
hiprandState state;
hiprand_init((unsigned long long)clock() , tId, 0, &state);
if(tId < popSize){
FitnessFunction(&DIPopulation[tId], DDistance);
if(hiprand_uniform(&state) < rate){
unsigned int pair = hiprand(&state)%popSize;
int n1[numberNodes];
int n2[numberNodes];
memcpy(n1,DIPopulation[pair].genome,sizeof(int)*numberNodes);
memcpy(n2,DIPopulation[tId].genome,sizeof(int)*numberNodes);
CrossPermutation(n1,n2,state);
struct Agent a1 = NewAgent(n1);
struct Agent a2 = NewAgent(n2);
Mutate(&a1, state);
Mutate(&a2, state);
FitnessFunction(&a1,DDistance);
FitnessFunction(&a2,DDistance);
DFPopulation[tId] = GetBest(a1,a2,DIPopulation[tId]);
}else{
DFPopulation[tId] = DIPopulation[tId];
}
}
}
void CondensedResult(float current[], float *results, float mean, int popSize, int generation){
float median = 0, best = 0, worst = 0, stDeviation = 0;
sort(current,current +popSize);
best = current[0];
worst = current[popSize-1];
if (popSize % 2 == 0){
median = (current[int(popSize/2)]+current[int((popSize/2)+1)])/2;
} else{
median = current[int((popSize/2)+1)];
}
for(int i = 0;i<popSize;i++){
stDeviation += pow(current[i]-mean,2);
}
stDeviation /= popSize;
stDeviation = sqrt(stDeviation);
results[generation*5] = best;
results[generation*5+1] = worst;
results[generation*5+2] = mean;
results[generation*5+3] = median;
results[generation*5+4] = stDeviation;
}
extern "C" {
void evaluateGen(float *distance, float *results, int popSize, int generations, float rate) {
srand(time(nullptr));
struct Agent population[popSize];
for (int i = 0; i< popSize;i++){
population[i] = RandomAgent(numberNodes);
}
unsigned long DDistanceSize = (numberNodes*numberNodes)*sizeof(float);
float* DDistance;
hipMalloc((void**)&DDistance,DDistanceSize);
hipMemcpy(DDistance,distance,DDistanceSize,hipMemcpyHostToDevice);
unsigned long DPopulationSize = (sizeof(int)+sizeof(float)+(sizeof(int)*numberNodes))*popSize;
struct Agent* DIPopulation;
hipMalloc((void**)&DIPopulation,DPopulationSize);
struct Agent* DFPopulation;
hipMalloc((void**)&DFPopulation,DPopulationSize);
hipMemcpy(DIPopulation,population,DPopulationSize,hipMemcpyHostToDevice);
for (int i = 0; i < generations;i++){
float popResults[popSize];
float mean = 0.0;
if(i%2==0){
EvaluateGen<<<128,int(popSize/128)+1>>>(DDistance, DIPopulation, DFPopulation, popSize, rate);
hipMemcpy(population,DFPopulation,DPopulationSize,hipMemcpyDeviceToHost);
}else{
EvaluateGen<<<128,int(popSize/128)+1>>>(DDistance, DFPopulation, DIPopulation, popSize, rate);
hipMemcpy(population,DIPopulation,DPopulationSize,hipMemcpyDeviceToHost);
}
for (int j = 0; j< popSize;j++){
mean += population[j].fitness;
popResults[j] = population[j].fitness;
// PrintAgent(population[j]);
}
mean /= popSize;
CondensedResult(popResults,results,mean, popSize,i);
}
hipFree(DDistance);
hipFree(DIPopulation);
hipFree(DFPopulation);
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <iostream>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <cstdlib>
#include <hiprand/hiprand_kernel.h>
#include <bits/stdc++.h>
using namespace std;
const int numberNodes = 439;
struct Agent{
int size;
float fitness;
int genome[numberNodes];
};
/* Arrange the N elements of ARRAY in random order.
Only effective if N is much smaller than RAND_MAX;
if this may not be the case, use a better random
number generator. */
void shuffle(int *array, size_t n)
{
if (n > 1)
{
size_t i;
for (i = 0; i < n - 1; i++)
{
size_t j = i + rand() / (RAND_MAX / (n - i) + 1);
int t = array[j];
array[j] = array[i];
array[i] = t;
}
}
}
Agent RandomAgent(int size){
int g[size];
for (int i = 0; i < size ; i++){
g[i] = i;
}
shuffle(g,size);
struct Agent RAgent{};
RAgent.size = size;
RAgent.fitness = 0.0;
for (int i = 0; i < size ; i++){
RAgent.genome[i] = g[i];
}
return RAgent;
}
__device__ Agent NewAgent (const int genome[]){
struct Agent nw{};
nw.size = numberNodes;
nw.fitness = 0.0;
for (int i = 0; i < numberNodes ; i++){
nw.genome[i] = genome[i];
}
return nw;
}
__device__ void Mutate(struct Agent *agent, hiprandState state) {
unsigned int p1 = hiprand(&state) % numberNodes;
while (true) {
unsigned int p2 = hiprand(&state) % numberNodes;
if (p1 != p2) {
int temp = agent->genome[p1];
agent->genome[p1] = agent->genome[p2];
agent->genome[p2] = temp;
break;
}
}
}
__device__ void CrossPermutation(int a[], int b[], hiprandState state){
unsigned int crossPoint = hiprand(&state)%(numberNodes-2)+1;
unsigned int tempSize = crossPoint+1;
int tempA[numberNodes];
int tempB[numberNodes];
for(int i = 0;i<numberNodes;i++){
tempA[i]=0;
tempB[i]=0;
}
for(int i = tempSize;i<numberNodes;i++){
tempA[a[i]]=1;
tempB[b[i]]=1;
}
unsigned int idenA = tempSize;
unsigned int idenB = tempSize;
for (int i = 0;i < numberNodes ; i++) {
if ( tempA[b[i]] ==1 ) {
a[idenA] = b[i];
idenA++;
}
}
for (int i = 0;i < numberNodes ; i++) {
if ( tempB[a[i]] ==1 ) {
b[idenB] = a[i];
idenB++;
}
}
};
__device__ void FitnessFunction(struct Agent *agent, const float *distance){
float fitness = 0;
for (int i = 0; i < numberNodes ; i++){
if (i < numberNodes - 1 ){
fitness += distance[agent->genome[i]+agent->genome[i+1]*numberNodes];
}else{
fitness += distance[agent->genome[i]+agent->genome[0]*numberNodes];
}
}
agent->fitness = fitness;
}
__device__ Agent GetBest(struct Agent a1,struct Agent a2,struct Agent a3){
if(a1.fitness < a2.fitness && a1.fitness < a3.fitness){
return a1;
}else if (a2.fitness < a3.fitness){
return a2;
}else{
return a3;
}
}
void PrintAgent(struct Agent agent){
cout<<agent.fitness<< " ";
for (int i : agent.genome){
cout<< i << " ";
}
cout << endl;
}
__global__ void EvaluateGen(float *DDistance, struct Agent *DIPopulation, struct Agent *DFPopulation, int popSize, float rate) {
unsigned int tId = threadIdx.x + (blockIdx.x * blockDim.x);
hiprandState state;
hiprand_init((unsigned long long)clock() , tId, 0, &state);
if(tId < popSize){
FitnessFunction(&DIPopulation[tId], DDistance);
if(hiprand_uniform(&state) < rate){
unsigned int pair = hiprand(&state)%popSize;
int n1[numberNodes];
int n2[numberNodes];
memcpy(n1,DIPopulation[pair].genome,sizeof(int)*numberNodes);
memcpy(n2,DIPopulation[tId].genome,sizeof(int)*numberNodes);
CrossPermutation(n1,n2,state);
struct Agent a1 = NewAgent(n1);
struct Agent a2 = NewAgent(n2);
Mutate(&a1, state);
Mutate(&a2, state);
FitnessFunction(&a1,DDistance);
FitnessFunction(&a2,DDistance);
DFPopulation[tId] = GetBest(a1,a2,DIPopulation[tId]);
}else{
DFPopulation[tId] = DIPopulation[tId];
}
}
}
void CondensedResult(float current[], float *results, float mean, int popSize, int generation){
float median = 0, best = 0, worst = 0, stDeviation = 0;
sort(current,current +popSize);
best = current[0];
worst = current[popSize-1];
if (popSize % 2 == 0){
median = (current[int(popSize/2)]+current[int((popSize/2)+1)])/2;
} else{
median = current[int((popSize/2)+1)];
}
for(int i = 0;i<popSize;i++){
stDeviation += pow(current[i]-mean,2);
}
stDeviation /= popSize;
stDeviation = sqrt(stDeviation);
results[generation*5] = best;
results[generation*5+1] = worst;
results[generation*5+2] = mean;
results[generation*5+3] = median;
results[generation*5+4] = stDeviation;
}
extern "C" {
void evaluateGen(float *distance, float *results, int popSize, int generations, float rate) {
srand(time(nullptr));
struct Agent population[popSize];
for (int i = 0; i< popSize;i++){
population[i] = RandomAgent(numberNodes);
}
unsigned long DDistanceSize = (numberNodes*numberNodes)*sizeof(float);
float* DDistance;
hipMalloc((void**)&DDistance,DDistanceSize);
hipMemcpy(DDistance,distance,DDistanceSize,hipMemcpyHostToDevice);
unsigned long DPopulationSize = (sizeof(int)+sizeof(float)+(sizeof(int)*numberNodes))*popSize;
struct Agent* DIPopulation;
hipMalloc((void**)&DIPopulation,DPopulationSize);
struct Agent* DFPopulation;
hipMalloc((void**)&DFPopulation,DPopulationSize);
hipMemcpy(DIPopulation,population,DPopulationSize,hipMemcpyHostToDevice);
for (int i = 0; i < generations;i++){
float popResults[popSize];
float mean = 0.0;
if(i%2==0){
EvaluateGen<<<128,int(popSize/128)+1>>>(DDistance, DIPopulation, DFPopulation, popSize, rate);
hipMemcpy(population,DFPopulation,DPopulationSize,hipMemcpyDeviceToHost);
}else{
EvaluateGen<<<128,int(popSize/128)+1>>>(DDistance, DFPopulation, DIPopulation, popSize, rate);
hipMemcpy(population,DIPopulation,DPopulationSize,hipMemcpyDeviceToHost);
}
for (int j = 0; j< popSize;j++){
mean += population[j].fitness;
popResults[j] = population[j].fitness;
// PrintAgent(population[j]);
}
mean /= popSize;
CondensedResult(popResults,results,mean, popSize,i);
}
hipFree(DDistance);
hipFree(DIPopulation);
hipFree(DFPopulation);
}
}
|
.text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z7shufflePim # -- Begin function _Z7shufflePim
.p2align 4, 0x90
.type _Z7shufflePim,@function
_Z7shufflePim: # @_Z7shufflePim
.cfi_startproc
# %bb.0:
cmpq $2, %rsi
jb .LBB0_5
# %bb.1: # %.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
cmpq $1, %rsi
je .LBB0_4
# %bb.2: # %.lr.ph.preheader
movq %rdi, %r14
xorl %r15d, %r15d
movq %rdi, %r12
.p2align 4, 0x90
.LBB0_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movslq %eax, %rcx
movl $2147483647, %eax # imm = 0x7FFFFFFF
xorl %edx, %edx
divq %rbx
movq %rax, %rsi
incq %rsi
movq %rcx, %rax
xorl %edx, %edx
divq %rsi
leaq (%r14,%r15,4), %rcx
movl (%rcx,%rax,4), %edx
movl (%r12), %esi
movl %esi, (%rcx,%rax,4)
movl %edx, (%r12)
incq %r15
decq %rbx
addq $4, %r12
cmpq $1, %rbx
jne .LBB0_3
.LBB0_4:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB0_5: # %.loopexit
retq
.Lfunc_end0:
.size _Z7shufflePim, .Lfunc_end0-_Z7shufflePim
.cfi_endproc
# -- End function
.globl _Z11RandomAgenti # -- Begin function _Z11RandomAgenti
.p2align 4, 0x90
.type _Z11RandomAgenti,@function
_Z11RandomAgenti: # @_Z11RandomAgenti
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $24, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movq %rdi, -56(%rbp) # 8-byte Spill
movl %esi, %r14d
movq %rsp, %r12
leaq 15(,%r14,4), %rax
andq $-16, %rax
subq %rax, %r12
movq %r12, %rsp
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %eax, (%r12,%rax,4)
incq %rax
cmpq %rax, %r14
jne .LBB1_2
.LBB1_3: # %._crit_edge
movl %esi, -44(%rbp) # 4-byte Spill
cmpl $2, %esi
jb .LBB1_7
# %bb.4: # %.preheader.i
movslq -44(%rbp), %r13 # 4-byte Folded Reload
cmpq $1, %r13
je .LBB1_7
# %bb.5: # %.lr.ph.i.preheader
xorl %ebx, %ebx
movq %r12, %r15
.p2align 4, 0x90
.LBB1_6: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movslq %eax, %rcx
movl $2147483647, %eax # imm = 0x7FFFFFFF
xorl %edx, %edx
divq %r13
movq %rax, %rsi
incq %rsi
movq %rcx, %rax
xorl %edx, %edx
divq %rsi
leaq (%r12,%rbx,4), %rcx
movl (%rcx,%rax,4), %edx
movl (%r15), %esi
movl %esi, (%rcx,%rax,4)
movl %edx, (%r15)
incq %rbx
decq %r13
addq $4, %r15
cmpq $1, %r13
jne .LBB1_6
.LBB1_7: # %_Z7shufflePim.exit
movl $1764, %edx # imm = 0x6E4
movq -56(%rbp), %rbx # 8-byte Reload
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movl -44(%rbp), %eax # 4-byte Reload
movl %eax, (%rbx)
movl $0, 4(%rbx)
testl %eax, %eax
jle .LBB1_9
# %bb.8: # %.lr.ph17.preheader
movq %rbx, %rdi
addq $8, %rdi
shlq $2, %r14
movq %r12, %rsi
movq %r14, %rdx
callq memcpy@PLT
.LBB1_9: # %._crit_edge18
movq %rbx, %rax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end1:
.size _Z11RandomAgenti, .Lfunc_end1-_Z11RandomAgenti
.cfi_endproc
# -- End function
.globl _Z10PrintAgent5Agent # -- Begin function _Z10PrintAgent5Agent
.p2align 4, 0x90
.type _Z10PrintAgent5Agent,@function
_Z10PrintAgent5Agent: # @_Z10PrintAgent5Agent
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 32(%rsp), %rbx
movss 36(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $8, %r14d
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
addq $4, %r14
cmpq $1764, %r14 # imm = 0x6E4
jne .LBB2_1
# %bb.2:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_7
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_5
# %bb.4:
movzbl 67(%rbx), %eax
jmp .LBB2_6
.LBB2_5:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB2_7:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size _Z10PrintAgent5Agent, .Lfunc_end2-_Z10PrintAgent5Agent
.cfi_endproc
# -- End function
.globl _Z26__device_stub__EvaluateGenPfP5AgentS1_if # -- Begin function _Z26__device_stub__EvaluateGenPfP5AgentS1_if
.p2align 4, 0x90
.type _Z26__device_stub__EvaluateGenPfP5AgentS1_if,@function
_Z26__device_stub__EvaluateGenPfP5AgentS1_if: # @_Z26__device_stub__EvaluateGenPfP5AgentS1_if
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movss %xmm0, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11EvaluateGenPfP5AgentS1_if, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z26__device_stub__EvaluateGenPfP5AgentS1_if, .Lfunc_end3-_Z26__device_stub__EvaluateGenPfP5AgentS1_if
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z15CondensedResultPfS_fii
.LCPI4_0:
.long 0x3f000000 # float 0.5
.text
.globl _Z15CondensedResultPfS_fii
.p2align 4, 0x90
.type _Z15CondensedResultPfS_fii,@function
_Z15CondensedResultPfS_fii: # @_Z15CondensedResultPfS_fii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r14d
movl %edx, %ebp
movaps %xmm0, %xmm3
movq %rsi, %rbx
movq %rdi, %r12
movslq %edx, %rax
leaq (%rdi,%rax,4), %r15
testl %eax, %eax
movss %xmm0, (%rsp) # 4-byte Spill
je .LBB4_2
# %bb.1:
bsrq %rax, %rax
xorl $63, %eax
addl %eax, %eax
movl $126, %edx
subq %rax, %rdx
movq %r12, %rdi
movq %r15, %rsi
callq _ZSt16__introsort_loopIPflN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_
movq %r12, %rdi
movq %r15, %rsi
callq _ZSt22__final_insertion_sortIPfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_
movss (%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
.LBB4_2: # %_ZSt4sortIPfEvT_S1_.exit
movl %ebp, %eax
testb $1, %bpl
jne .LBB4_4
# %bb.3:
sarl %eax
cltq
movss (%r12,%rax,4), %xmm4 # xmm4 = mem[0],zero,zero,zero
addss 4(%r12,%rax,4), %xmm4
mulss .LCPI4_0(%rip), %xmm4
jmp .LBB4_5
.LBB4_4:
shrl $31, %eax
addl %ebp, %eax
sarl %eax
cltq
movss 4(%r12,%rax,4), %xmm4 # xmm4 = mem[0],zero,zero,zero
.LBB4_5:
xorps %xmm1, %xmm1
xorps %xmm0, %xmm0
testl %ebp, %ebp
jle .LBB4_8
# %bb.6: # %.lr.ph.preheader
movl %ebp, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_7: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%r12,%rcx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss %xmm3, %xmm2
cvtss2sd %xmm2, %xmm2
mulsd %xmm2, %xmm2
cvtss2sd %xmm0, %xmm0
addsd %xmm2, %xmm0
cvtsd2ss %xmm0, %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB4_7
.LBB4_8: # %._crit_edge
movss (%r12), %xmm5 # xmm5 = mem[0],zero,zero,zero
xorps %xmm2, %xmm2
cvtsi2ss %ebp, %xmm2
movss -4(%r15), %xmm6 # xmm6 = mem[0],zero,zero,zero
divss %xmm2, %xmm0
ucomiss %xmm1, %xmm0
jb .LBB4_10
# %bb.9:
sqrtss %xmm0, %xmm0
jmp .LBB4_11
.LBB4_10: # %call.sqrt
movss %xmm4, 12(%rsp) # 4-byte Spill
movss %xmm5, 8(%rsp) # 4-byte Spill
movss %xmm6, 4(%rsp) # 4-byte Spill
callq sqrtf
movss 4(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 8(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 12(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss (%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
.LBB4_11: # %._crit_edge.split
leal (%r14,%r14,4), %eax
cltq
movss %xmm5, (%rbx,%rax,4)
movss %xmm6, 4(%rbx,%rax,4)
movss %xmm3, 8(%rbx,%rax,4)
movss %xmm4, 12(%rbx,%rax,4)
movss %xmm0, 16(%rbx,%rax,4)
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z15CondensedResultPfS_fii, .Lfunc_end4-_Z15CondensedResultPfS_fii
.cfi_endproc
# -- End function
.globl evaluateGen # -- Begin function evaluateGen
.p2align 4, 0x90
.type evaluateGen,@function
evaluateGen: # @evaluateGen
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $3688, %rsp # imm = 0xE68
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movss %xmm0, -76(%rbp) # 4-byte Spill
movl %ecx, -80(%rbp) # 4-byte Spill
movl %edx, %r14d
movq %rsi, -200(%rbp) # 8-byte Spill
movq %rdi, -88(%rbp) # 8-byte Spill
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl %r14d, %ebx
movq %rsp, %rcx
imulq $1764, %rbx, %rax # imm = 0x6E4
addq $15, %rax
andq $-16, %rax
subq %rax, %rcx
movq %rcx, -96(%rbp) # 8-byte Spill
movq %rcx, %rsp
movq %r14, -56(%rbp) # 8-byte Spill
testl %r14d, %r14d
jle .LBB5_7
# %bb.1: # %.lr.ph.preheader
xorl %r14d, %r14d
leaq -1968(%rbp), %r13
.p2align 4, 0x90
.LBB5_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB5_3 Depth 2
# Child Loop BB5_5 Depth 2
movq %rsp, -112(%rbp) # 8-byte Spill
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_3: # %.lr.ph.i
# Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %eax, -1968(%rbp,%rax,4)
incq %rax
cmpq $439, %rax # imm = 0x1B7
jne .LBB5_3
# %bb.4: # %.lr.ph.i.i.preheader
# in Loop: Header=BB5_2 Depth=1
movl $439, %r15d # imm = 0x1B7
movq %r13, %r12
.p2align 4, 0x90
.LBB5_5: # %.lr.ph.i.i
# Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movslq %eax, %rcx
movl $2147483647, %eax # imm = 0x7FFFFFFF
xorl %edx, %edx
divq %r15
movq %rax, %rsi
incq %rsi
movq %rcx, %rax
xorl %edx, %edx
divq %rsi
movl (%r13,%rax,4), %ecx
movl (%r13), %edx
movl %edx, (%r13,%rax,4)
movl %ecx, (%r13)
decq %r15
addq $4, %r13
cmpq $1, %r15
jne .LBB5_5
# %bb.6: # %_Z11RandomAgenti.exit
# in Loop: Header=BB5_2 Depth=1
movl $1756, %edx # imm = 0x6DC
leaq -3728(%rbp), %r15
movq %r15, %rdi
movq %r12, %r13
movq %r12, %rsi
callq memcpy@PLT
movq -112(%rbp), %rsp # 8-byte Reload
imulq $1764, %r14, %rax # imm = 0x6E4
movq -96(%rbp), %rcx # 8-byte Reload
movq $439, (%rcx,%rax) # imm = 0x1B7
leaq (%rcx,%rax), %rdi
addq $8, %rdi
movl $1756, %edx # imm = 0x6DC
movq %r15, %rsi
callq memcpy@PLT
incq %r14
cmpq %rbx, %r14
jne .LBB5_2
.LBB5_7: # %._crit_edge
leaq -104(%rbp), %rdi
movl $770884, %esi # imm = 0xBC344
callq hipMalloc
movq -104(%rbp), %rdi
movl $770884, %edx # imm = 0xBC344
movq -88(%rbp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movslq -56(%rbp), %rax # 4-byte Folded Reload
imulq $1764, %rax, %r14 # imm = 0x6E4
leaq -64(%rbp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq -72(%rbp), %rdi
movq %r14, %rsi
callq hipMalloc
movq -64(%rbp), %rdi
movq -96(%rbp), %rsi # 8-byte Reload
movq %r14, -112(%rbp) # 8-byte Spill
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
cmpl $0, -80(%rbp) # 4-byte Folded Reload
jle .LBB5_17
# %bb.8: # %.lr.ph74
movabsq $4294967296, %r12 # imm = 0x100000000
movq -56(%rbp), %rax # 8-byte Reload
leal 127(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $7, %ecx
incl %ecx
cvtsi2ss %eax, %xmm0
movss %xmm0, -172(%rbp) # 4-byte Spill
orq %r12, %rcx
movq %rcx, -88(%rbp) # 8-byte Spill
movq -96(%rbp), %rax # 8-byte Reload
addq $4, %rax
movq %rax, -184(%rbp) # 8-byte Spill
xorl %r13d, %r13d
leaq 15(,%rbx,4), %rax
andq $-16, %rax
movq %rax, -192(%rbp) # 8-byte Spill
subq $-128, %r12
jmp .LBB5_9
.p2align 4, 0x90
.LBB5_15: # in Loop: Header=BB5_9 Depth=1
xorps %xmm0, %xmm0
.LBB5_16: # %._crit_edge71
# in Loop: Header=BB5_9 Depth=1
divss -172(%rbp), %xmm0 # 4-byte Folded Reload
movq %r15, %rdi
movq -200(%rbp), %rsi # 8-byte Reload
movq -56(%rbp), %rdx # 8-byte Reload
# kill: def $edx killed $edx killed $rdx
movl %r13d, %ecx
callq _Z15CondensedResultPfS_fii
movq %r14, %rsp
incl %r13d
cmpl -80(%rbp), %r13d # 4-byte Folded Reload
je .LBB5_17
.LBB5_9: # =>This Loop Header: Depth=1
# Child Loop BB5_19 Depth 2
movq %rsp, %r14
movq %rsp, %r15
subq -192(%rbp), %r15 # 8-byte Folded Reload
movq %r15, %rsp
movq %r12, %rdi
movl $1, %esi
testb $1, %r13b
jne .LBB5_12
# %bb.10: # in Loop: Header=BB5_9 Depth=1
movq -88(%rbp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
leaq -72(%rbp), %rcx
testl %eax, %eax
jne .LBB5_14
# %bb.11: # in Loop: Header=BB5_9 Depth=1
movq -104(%rbp), %rax
movq -64(%rbp), %rcx
movq -72(%rbp), %rdx
movq %rax, -168(%rbp)
movq %rcx, -160(%rbp)
movq %rdx, -152(%rbp)
movq -56(%rbp), %rax # 8-byte Reload
movl %eax, -48(%rbp)
movss -76(%rbp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, -44(%rbp)
leaq -168(%rbp), %rax
movq %rax, -1968(%rbp)
leaq -160(%rbp), %rax
movq %rax, -1960(%rbp)
leaq -152(%rbp), %rax
movq %rax, -1952(%rbp)
leaq -48(%rbp), %rax
movq %rax, -1944(%rbp)
leaq -44(%rbp), %rax
movq %rax, -1936(%rbp)
leaq -3728(%rbp), %rdi
leaq -144(%rbp), %rsi
leaq -128(%rbp), %rdx
leaq -120(%rbp), %rcx
callq __hipPopCallConfiguration
movq -3728(%rbp), %rsi
movl -3720(%rbp), %edx
movq -144(%rbp), %rcx
movl -136(%rbp), %r8d
movl $_Z11EvaluateGenPfP5AgentS1_if, %edi
leaq -1968(%rbp), %r9
pushq -120(%rbp)
pushq -128(%rbp)
callq hipLaunchKernel
addq $16, %rsp
leaq -72(%rbp), %rcx
jmp .LBB5_14
.p2align 4, 0x90
.LBB5_12: # in Loop: Header=BB5_9 Depth=1
movq -88(%rbp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
leaq -64(%rbp), %rcx
testl %eax, %eax
jne .LBB5_14
# %bb.13: # in Loop: Header=BB5_9 Depth=1
movq -104(%rbp), %rax
movq -72(%rbp), %rcx
movq -64(%rbp), %rdx
movq %rax, -168(%rbp)
movq %rcx, -160(%rbp)
movq %rdx, -152(%rbp)
movq -56(%rbp), %rax # 8-byte Reload
movl %eax, -48(%rbp)
movss -76(%rbp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, -44(%rbp)
leaq -168(%rbp), %rax
movq %rax, -1968(%rbp)
leaq -160(%rbp), %rax
movq %rax, -1960(%rbp)
leaq -152(%rbp), %rax
movq %rax, -1952(%rbp)
leaq -48(%rbp), %rax
movq %rax, -1944(%rbp)
leaq -44(%rbp), %rax
movq %rax, -1936(%rbp)
leaq -3728(%rbp), %rdi
leaq -144(%rbp), %rsi
leaq -128(%rbp), %rdx
leaq -120(%rbp), %rcx
callq __hipPopCallConfiguration
movq -3728(%rbp), %rsi
movl -3720(%rbp), %edx
movq -144(%rbp), %rcx
movl -136(%rbp), %r8d
movl $_Z11EvaluateGenPfP5AgentS1_if, %edi
leaq -1968(%rbp), %r9
pushq -120(%rbp)
pushq -128(%rbp)
callq hipLaunchKernel
addq $16, %rsp
leaq -64(%rbp), %rcx
.p2align 4, 0x90
.LBB5_14: # in Loop: Header=BB5_9 Depth=1
movq (%rcx), %rsi
movq -96(%rbp), %rdi # 8-byte Reload
movq -112(%rbp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
cmpl $0, -56(%rbp) # 4-byte Folded Reload
jle .LBB5_15
# %bb.18: # %.lr.ph70.preheader
# in Loop: Header=BB5_9 Depth=1
xorps %xmm0, %xmm0
movq -184(%rbp), %rax # 8-byte Reload
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_19: # %.lr.ph70
# Parent Loop BB5_9 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rax), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm1, %xmm0
movss %xmm1, (%r15,%rcx,4)
incq %rcx
addq $1764, %rax # imm = 0x6E4
cmpq %rcx, %rbx
jne .LBB5_19
jmp .LBB5_16
.LBB5_17: # %._crit_edge75
movq -104(%rbp), %rdi
callq hipFree
movq -64(%rbp), %rdi
callq hipFree
movq -72(%rbp), %rdi
callq hipFree
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end5:
.size evaluateGen, .Lfunc_end5-evaluateGen
.cfi_endproc
# -- End function
.section .text._ZSt16__introsort_loopIPflN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_,"axG",@progbits,_ZSt16__introsort_loopIPflN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_,comdat
.weak _ZSt16__introsort_loopIPflN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_ # -- Begin function _ZSt16__introsort_loopIPflN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_
.p2align 4, 0x90
.type _ZSt16__introsort_loopIPflN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_,@function
_ZSt16__introsort_loopIPflN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_: # @_ZSt16__introsort_loopIPflN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r12
subq %rdi, %r12
cmpq $65, %r12
jl .LBB6_54
# %bb.1: # %.lr.ph
movq %rdx, %r14
movq %rdi, %rbx
leaq 4(%rdi), %r13
movq $-4, %rbp
subq %rdi, %rbp
jmp .LBB6_3
.p2align 4, 0x90
.LBB6_2: # %_ZSt27__unguarded_partition_pivotIPfN9__gnu_cxx5__ops15_Iter_less_iterEET_S4_S4_T0_.exit
# in Loop: Header=BB6_3 Depth=1
movq %r15, %rdi
movq %r14, %rdx
callq _ZSt16__introsort_loopIPflN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_
movq %r15, %rsi
cmpq $64, %r12
jle .LBB6_54
.LBB6_3: # =>This Loop Header: Depth=1
# Child Loop BB6_16 Depth 2
# Child Loop BB6_17 Depth 3
# Child Loop BB6_19 Depth 3
subq $1, %r14
jb .LBB6_22
# %bb.4: # in Loop: Header=BB6_3 Depth=1
shrq $3, %r12
movss 4(%rbx), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss (%rbx,%r12,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm2
movss -4(%rsi), %xmm0 # xmm0 = mem[0],zero,zero,zero
jbe .LBB6_7
# %bb.5: # in Loop: Header=BB6_3 Depth=1
ucomiss %xmm2, %xmm0
jbe .LBB6_9
# %bb.6: # in Loop: Header=BB6_3 Depth=1
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm2, (%rbx)
movss %xmm0, (%rbx,%r12,4)
jmp .LBB6_15
.p2align 4, 0x90
.LBB6_7: # in Loop: Header=BB6_3 Depth=1
ucomiss %xmm1, %xmm0
jbe .LBB6_11
# %bb.8: # in Loop: Header=BB6_3 Depth=1
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm1, (%rbx)
movss %xmm0, 4(%rbx)
jmp .LBB6_15
.p2align 4, 0x90
.LBB6_9: # in Loop: Header=BB6_3 Depth=1
ucomiss %xmm1, %xmm0
movss (%rbx), %xmm2 # xmm2 = mem[0],zero,zero,zero
jbe .LBB6_13
# %bb.10: # in Loop: Header=BB6_3 Depth=1
movss %xmm0, (%rbx)
movss %xmm2, -4(%rsi)
jmp .LBB6_15
.p2align 4, 0x90
.LBB6_11: # in Loop: Header=BB6_3 Depth=1
ucomiss %xmm2, %xmm0
movss (%rbx), %xmm1 # xmm1 = mem[0],zero,zero,zero
jbe .LBB6_14
# %bb.12: # in Loop: Header=BB6_3 Depth=1
movss %xmm0, (%rbx)
movss %xmm1, -4(%rsi)
jmp .LBB6_15
.LBB6_13: # in Loop: Header=BB6_3 Depth=1
movss %xmm1, (%rbx)
movss %xmm2, 4(%rbx)
jmp .LBB6_15
.LBB6_14: # in Loop: Header=BB6_3 Depth=1
movss %xmm2, (%rbx)
movss %xmm1, (%rbx,%r12,4)
.p2align 4, 0x90
.LBB6_15: # %_ZSt22__move_median_to_firstIPfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_S4_S4_T0_.exit.i.preheader
# in Loop: Header=BB6_3 Depth=1
movq %rsi, %rax
movq %r13, %rcx
.p2align 4, 0x90
.LBB6_16: # %_ZSt22__move_median_to_firstIPfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_S4_S4_T0_.exit.i
# Parent Loop BB6_3 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_17 Depth 3
# Child Loop BB6_19 Depth 3
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
leaq (%rcx,%rbp), %r12
.p2align 4, 0x90
.LBB6_17: # Parent Loop BB6_3 Depth=1
# Parent Loop BB6_16 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rcx), %xmm1 # xmm1 = mem[0],zero,zero,zero
addq $4, %rcx
addq $4, %r12
ucomiss %xmm1, %xmm0
ja .LBB6_17
# %bb.18: # %.preheader.i.i.preheader
# in Loop: Header=BB6_16 Depth=2
leaq -4(%rcx), %r15
.p2align 4, 0x90
.LBB6_19: # %.preheader.i.i
# Parent Loop BB6_3 Depth=1
# Parent Loop BB6_16 Depth=2
# => This Inner Loop Header: Depth=3
movss -4(%rax), %xmm2 # xmm2 = mem[0],zero,zero,zero
addq $-4, %rax
ucomiss %xmm0, %xmm2
ja .LBB6_19
# %bb.20: # in Loop: Header=BB6_16 Depth=2
cmpq %rax, %r15
jae .LBB6_2
# %bb.21: # in Loop: Header=BB6_16 Depth=2
movss %xmm2, (%r15)
movss %xmm1, (%rax)
jmp .LBB6_16
.LBB6_22:
movq %r12, %rdx
shrq $2, %rdx
leaq -2(%rdx), %rax
movq %rax, %rcx
shrq %rcx
leaq -1(%rdx), %rdi
shrq $63, %rdi
addq %rdi, %rdx
decq %rdx
sarq %rdx
sarq %rax
xorl %edi, %edi
jmp .LBB6_25
.p2align 4, 0x90
.LBB6_23: # in Loop: Header=BB6_25 Depth=1
movq %r8, %r9
.LBB6_24: # %_ZSt13__adjust_heapIPflfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_T0_S5_T1_T2_.exit.i.i
# in Loop: Header=BB6_25 Depth=1
movss %xmm0, (%rbx,%r9,4)
movq %rcx, %r8
subq $1, %r8
cmovbq %rdi, %r8
testq %rcx, %rcx
movq %r8, %rcx
je .LBB6_40
.LBB6_25: # =>This Loop Header: Depth=1
# Child Loop BB6_29 Depth 2
# Child Loop BB6_35 Depth 2
movss (%rbx,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rcx, %r8
cmpq %rcx, %rdx
jle .LBB6_31
# %bb.26: # %.lr.ph.i.i.i.preheader
# in Loop: Header=BB6_25 Depth=1
movq %rcx, %r9
jmp .LBB6_29
.p2align 4, 0x90
.LBB6_27: # %.lr.ph.i.i.i
# in Loop: Header=BB6_29 Depth=2
leaq 2(,%r9,2), %r8
.LBB6_28: # %.lr.ph.i.i.i
# in Loop: Header=BB6_29 Depth=2
movss (%rbx,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss %xmm1, (%rbx,%r9,4)
movq %r8, %r9
cmpq %rdx, %r8
jge .LBB6_31
.LBB6_29: # %.lr.ph.i.i.i
# Parent Loop BB6_25 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%r9,%r9), %r8
movss 4(%rbx,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss 8(%rbx,%r8,4), %xmm1
jbe .LBB6_27
# %bb.30: # in Loop: Header=BB6_29 Depth=2
leaq 1(,%r9,2), %r8
jmp .LBB6_28
.p2align 4, 0x90
.LBB6_31: # %._crit_edge.i.i.i
# in Loop: Header=BB6_25 Depth=1
testb $4, %r12b
jne .LBB6_34
# %bb.32: # %._crit_edge.i.i.i
# in Loop: Header=BB6_25 Depth=1
cmpq %rax, %r8
jne .LBB6_34
# %bb.33: # in Loop: Header=BB6_25 Depth=1
leaq (%r8,%r8), %r9
movss 4(%rbx,%r9,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss %xmm1, (%rbx,%r8,4)
leaq 1(,%r8,2), %r8
.LBB6_34: # in Loop: Header=BB6_25 Depth=1
cmpq %rcx, %r8
jle .LBB6_23
.p2align 4, 0x90
.LBB6_35: # %.lr.ph.i.i.i.i14
# Parent Loop BB6_25 Depth=1
# => This Inner Loop Header: Depth=2
leaq -1(%r8), %r9
shrq $63, %r9
addq %r8, %r9
decq %r9
sarq %r9
movss (%rbx,%r9,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jbe .LBB6_23
# %bb.36: # in Loop: Header=BB6_35 Depth=2
movss %xmm1, (%rbx,%r8,4)
movq %r9, %r8
cmpq %rcx, %r9
jg .LBB6_35
jmp .LBB6_24
.p2align 4, 0x90
.LBB6_38: # in Loop: Header=BB6_40 Depth=1
movq %rcx, %rdx
.LBB6_39: # %_ZSt10__pop_heapIPfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_S4_RT0_.exit.i.i
# in Loop: Header=BB6_40 Depth=1
movss %xmm0, (%rbx,%rdx,4)
cmpq $4, %rax
jle .LBB6_54
.LBB6_40: # %.lr.ph.i.i
# =>This Loop Header: Depth=1
# Child Loop BB6_44 Depth 2
# Child Loop BB6_51 Depth 2
movss -4(%rsi), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%rbx), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss %xmm1, -4(%rsi)
addq $-4, %rsi
movq %rsi, %rax
subq %rbx, %rax
movq %rax, %rdx
sarq $2, %rdx
cmpq $3, %rdx
jl .LBB6_46
# %bb.41: # %.lr.ph.i.i.i.i.preheader
# in Loop: Header=BB6_40 Depth=1
leaq -1(%rdx), %rcx
shrq $63, %rcx
leaq (%rdx,%rcx), %rdi
decq %rdi
sarq %rdi
xorl %r8d, %r8d
jmp .LBB6_44
.p2align 4, 0x90
.LBB6_42: # %.lr.ph.i.i.i.i
# in Loop: Header=BB6_44 Depth=2
leaq 2(,%r8,2), %rcx
.LBB6_43: # %.lr.ph.i.i.i.i
# in Loop: Header=BB6_44 Depth=2
movss (%rbx,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss %xmm1, (%rbx,%r8,4)
movq %rcx, %r8
cmpq %rdi, %rcx
jge .LBB6_47
.LBB6_44: # %.lr.ph.i.i.i.i
# Parent Loop BB6_40 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%r8,%r8), %rcx
movss 4(%rbx,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss 8(%rbx,%rcx,4), %xmm1
jbe .LBB6_42
# %bb.45: # in Loop: Header=BB6_44 Depth=2
leaq 1(,%r8,2), %rcx
jmp .LBB6_43
.p2align 4, 0x90
.LBB6_46: # in Loop: Header=BB6_40 Depth=1
xorl %ecx, %ecx
.LBB6_47: # %._crit_edge.i.i.i.i
# in Loop: Header=BB6_40 Depth=1
testb $4, %al
jne .LBB6_50
# %bb.48: # in Loop: Header=BB6_40 Depth=1
addq $-2, %rdx
sarq %rdx
cmpq %rdx, %rcx
jne .LBB6_50
# %bb.49: # in Loop: Header=BB6_40 Depth=1
leaq (%rcx,%rcx), %rdx
movss 4(%rbx,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss %xmm1, (%rbx,%rcx,4)
leaq 1(,%rcx,2), %rcx
.LBB6_50: # in Loop: Header=BB6_40 Depth=1
testq %rcx, %rcx
jle .LBB6_38
.p2align 4, 0x90
.LBB6_51: # %.lr.ph.i.i.i.i.i
# Parent Loop BB6_40 Depth=1
# => This Inner Loop Header: Depth=2
leaq -1(%rcx), %rdx
shrq $63, %rdx
addq %rcx, %rdx
decq %rdx
sarq %rdx
movss (%rbx,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jbe .LBB6_38
# %bb.52: # in Loop: Header=BB6_51 Depth=2
movss %xmm1, (%rbx,%rcx,4)
cmpq $2, %rcx
movq %rdx, %rcx
jg .LBB6_51
jmp .LBB6_39
.LBB6_54: # %_ZSt14__partial_sortIPfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_S4_T0_.exit
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _ZSt16__introsort_loopIPflN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_, .Lfunc_end6-_ZSt16__introsort_loopIPflN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_
.cfi_endproc
# -- End function
.section .text._ZSt22__final_insertion_sortIPfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_,"axG",@progbits,_ZSt22__final_insertion_sortIPfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_,comdat
.weak _ZSt22__final_insertion_sortIPfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_ # -- Begin function _ZSt22__final_insertion_sortIPfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_
.p2align 4, 0x90
.type _ZSt22__final_insertion_sortIPfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_,@function
_ZSt22__final_insertion_sortIPfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_: # @_ZSt22__final_insertion_sortIPfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq %rdi, %r14
movq %rsi, %rax
subq %rdi, %rax
cmpq $65, %rax
jl .LBB7_12
# %bb.1:
leaq 4(%r14), %r15
movl $4, %r12d
movq %r15, %r13
movq %r14, %rbp
jmp .LBB7_6
.p2align 4, 0x90
.LBB7_2: # in Loop: Header=BB7_6 Depth=1
cmpq $5, %r12
jb .LBB7_10
# %bb.3: # in Loop: Header=BB7_6 Depth=1
movq %r15, %rdi
movq %r14, %rsi
movq %r12, %rdx
movss %xmm1, 4(%rsp) # 4-byte Spill
callq memmove@PLT
movss 4(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
.LBB7_4: # %_ZSt13move_backwardIPfS0_ET0_T_S2_S1_.exit.i
# in Loop: Header=BB7_6 Depth=1
movq %r14, %rax
.LBB7_5: # %_ZSt13move_backwardIPfS0_ET0_T_S2_S1_.exit.i
# in Loop: Header=BB7_6 Depth=1
movss %xmm1, (%rax)
addq $4, %r12
addq $4, %r13
cmpq $64, %r12
je .LBB7_25
.LBB7_6: # =>This Loop Header: Depth=1
# Child Loop BB7_9 Depth 2
movq %rbp, %rcx
leaq (%r14,%r12), %rbp
movss (%r14,%r12), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss (%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
ja .LBB7_2
# %bb.7: # in Loop: Header=BB7_6 Depth=1
movss (%rcx), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
movq %rbp, %rax
jbe .LBB7_5
# %bb.8: # %.lr.ph.i.i.preheader
# in Loop: Header=BB7_6 Depth=1
movq %r13, %rax
.p2align 4, 0x90
.LBB7_9: # %.lr.ph.i.i
# Parent Loop BB7_6 Depth=1
# => This Inner Loop Header: Depth=2
movss %xmm0, (%rax)
movss -8(%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
addq $-4, %rax
ucomiss %xmm1, %xmm0
ja .LBB7_9
jmp .LBB7_5
.LBB7_10: # in Loop: Header=BB7_6 Depth=1
movq %r14, %rax
cmpq $4, %r12
jne .LBB7_5
# %bb.11: # in Loop: Header=BB7_6 Depth=1
movss %xmm0, 4(%rcx)
jmp .LBB7_4
.LBB7_12:
cmpq %rbx, %r14
je .LBB7_31
# %bb.13:
leaq 4(%r14), %rax
cmpq %rbx, %rax
je .LBB7_31
# %bb.14: # %.lr.ph.i16.preheader
movq %r14, %r15
jmp .LBB7_19
.p2align 4, 0x90
.LBB7_15: # in Loop: Header=BB7_19 Depth=1
movq %r15, %rdx
subq %r14, %rdx
movq %rdx, %rax
sarq $2, %rax
cmpq $2, %rax
jl .LBB7_23
# %bb.16: # in Loop: Header=BB7_19 Depth=1
shlq $2, %rax
subq %rax, %rdi
addq $8, %rdi
movq %r14, %rsi
movss %xmm1, 4(%rsp) # 4-byte Spill
callq memmove@PLT
movss 4(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
.LBB7_17: # %_ZSt13move_backwardIPfS0_ET0_T_S2_S1_.exit.i27
# in Loop: Header=BB7_19 Depth=1
movq %r14, %rax
.LBB7_18: # %_ZSt13move_backwardIPfS0_ET0_T_S2_S1_.exit.i27
# in Loop: Header=BB7_19 Depth=1
movss %xmm1, (%rax)
leaq 4(%r15), %rax
cmpq %rbx, %rax
je .LBB7_31
.LBB7_19: # %.lr.ph.i16
# =>This Loop Header: Depth=1
# Child Loop BB7_22 Depth 2
movq %r15, %rdi
movq %rax, %r15
movss 4(%rdi), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss (%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
ja .LBB7_15
# %bb.20: # in Loop: Header=BB7_19 Depth=1
movss (%rdi), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
movq %r15, %rax
jbe .LBB7_18
# %bb.21: # %.lr.ph.i.i23.preheader
# in Loop: Header=BB7_19 Depth=1
movq %r15, %rax
.p2align 4, 0x90
.LBB7_22: # %.lr.ph.i.i23
# Parent Loop BB7_19 Depth=1
# => This Inner Loop Header: Depth=2
movss %xmm0, (%rax)
movss -8(%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
addq $-4, %rax
ucomiss %xmm1, %xmm0
ja .LBB7_22
jmp .LBB7_18
.LBB7_23: # in Loop: Header=BB7_19 Depth=1
movq %r14, %rax
cmpq $4, %rdx
jne .LBB7_18
# %bb.24: # in Loop: Header=BB7_19 Depth=1
movss %xmm0, 4(%rdi)
jmp .LBB7_17
.LBB7_25: # %_ZSt16__insertion_sortIPfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_.exit
addq $64, %r14
jmp .LBB7_27
.p2align 4, 0x90
.LBB7_26: # %_ZSt25__unguarded_linear_insertIPfN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_.exit.i8
# in Loop: Header=BB7_27 Depth=1
movss %xmm0, (%rax)
addq $4, %r14
.LBB7_27: # %_ZSt16__insertion_sortIPfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_.exit
# =>This Loop Header: Depth=1
# Child Loop BB7_30 Depth 2
cmpq %rbx, %r14
je .LBB7_31
# %bb.28: # %.lr.ph.i
# in Loop: Header=BB7_27 Depth=1
movss -4(%r14), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss (%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
movq %r14, %rax
jbe .LBB7_26
# %bb.29: # %.lr.ph.i.i11.preheader
# in Loop: Header=BB7_27 Depth=1
movq %r14, %rax
.p2align 4, 0x90
.LBB7_30: # %.lr.ph.i.i11
# Parent Loop BB7_27 Depth=1
# => This Inner Loop Header: Depth=2
movss %xmm1, (%rax)
movss -8(%rax), %xmm1 # xmm1 = mem[0],zero,zero,zero
addq $-4, %rax
ucomiss %xmm0, %xmm1
ja .LBB7_30
jmp .LBB7_26
.LBB7_31: # %_ZSt26__unguarded_insertion_sortIPfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_.exit
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _ZSt22__final_insertion_sortIPfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_, .Lfunc_end7-_ZSt22__final_insertion_sortIPfN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11EvaluateGenPfP5AgentS1_if, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type _Z11EvaluateGenPfP5AgentS1_if,@object # @_Z11EvaluateGenPfP5AgentS1_if
.section .rodata,"a",@progbits
.globl _Z11EvaluateGenPfP5AgentS1_if
.p2align 3, 0x0
_Z11EvaluateGenPfP5AgentS1_if:
.quad _Z26__device_stub__EvaluateGenPfP5AgentS1_if
.size _Z11EvaluateGenPfP5AgentS1_if, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11EvaluateGenPfP5AgentS1_if"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__EvaluateGenPfP5AgentS1_if
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z11EvaluateGenPfP5AgentS1_if
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
/*
Cource - "Разработка приложений на CUDA "
Task 1:
Выделить на GPU массив arr из 10^9 элементов типа
float и инициализировать его с помощью ядра следующим образом:
arr[i] = sin((i%360)*Pi/180). Скопировать массив в память центрального
процессора и посчитать ошибку err = sum_i(abs(sin((i%360)*Pi/180)
- arr[i]))/10^9. Провести исследование зависимости результата от использования
функций: sin, sinf, __sin. Объяснить результат. Проверить результат
при использовании массива типа double.
Written by Pavel Santaev
*/
#include <stdio.h>
#include <unistd.h>
#include <math.h>
typedef double arrType;
__global__ void calcSin(arrType * a, size_t len){
unsigned int index = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int i = index;
size_t threadsCount = blockDim.x * gridDim.x;
while (i < len){
double value = ((arrType)(i % 360)) * M_PI / 180;
a[i] = __sinf(value);
i = i + threadsCount;
}
}
double calcErr(arrType * arr, size_t len){
double sum = 0;
for (int i = 0; i < len; i++){
sum += abs(sin((i % 360) * M_PI / 180) - arr[i]);
}
return sum / len;
}
int main(){
size_t N = 1000 * 1000 * 100;
size_t size = sizeof(arrType) * N;
arrType * ptr;
cudaError_t error;
int deviceCount = 0;
error = cudaGetDeviceCount(&deviceCount);
if (cudaSuccess != error){
printf("Error in cudaGetDeviceCount: %s\n", cudaGetErrorString(error));
return 0;
}
printf("cudaGetDeviceCount = %x\n", deviceCount);
int deviceID = 1;
cudaDeviceProp devProp;
error = cudaGetDeviceProperties(&devProp, deviceID);
if (cudaSuccess != error){
printf("Error in cudaGetDeviceProperties: %d\n", cudaGetErrorString(error));
return 0;
}
printf ( "Device %d\n", 0 );
printf ( "Compute capability : %d.%d\n", devProp.major, devProp.minor );
printf ( "Name : %s\n", devProp.name );
printf ( "Total Global Memory : %d\n", devProp.totalGlobalMem );
printf ( "Shared memory per block: %d\n", devProp.sharedMemPerBlock );
printf ( "Registers per block : %d\n", devProp.regsPerBlock );
printf ( "Warp size : %d\n", devProp.warpSize );
printf ( "Max threads per block : %d\n", devProp.maxThreadsPerBlock );
printf ( "Total constant memory : %d\n", devProp.totalConstMem );
printf ( "Max Grid Size : %d %d %d\n", devProp.maxGridSize[0], devProp.maxGridSize[1], devProp.maxGridSize[2]);
printf ( "Max Threads Dim : %d %d %d\n", devProp.maxThreadsDim[0], devProp.maxThreadsDim[1], devProp.maxThreadsDim[2]);
cudaSetDevice(deviceID);
printf("sizeof size_t %d \n", sizeof(size_t));
printf("sizeof type %d \n", sizeof(arrType));
printf("allocating %u memory\n", size);
cudaMalloc(&ptr, size);
dim3 threads = dim3(devProp.maxThreadsPerBlock, 1);
dim3 blocks = dim3(128, 1);
calcSin<<<blocks, threads>>>(ptr, N);
int i = 0;
arrType * hostPtr;
hostPtr = (arrType *)malloc(size);
cudaMemcpy(hostPtr, ptr, size, cudaMemcpyDeviceToHost);
for (i = 0; i < 10; i++){
printf("%f ", hostPtr[i]);
}
printf("\nerror = %0.10f ", calcErr(hostPtr, N));
cudaFree(ptr);
free(hostPtr);
printf("\nfinished\n");
}
|
code for sm_80
Function : _Z7calcSinPdm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fc80003f06070 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x16c], PT, P0 ; /* 0x00005b00ff007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, R2 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0002 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ MUFU.RCP64H R7, 180 ; /* 0x4066800000077908 */
/* 0x001e220000001800 */
/*00b0*/ SHF.R.U32.HI R4, RZ, 0x3, R2 ; /* 0x00000003ff047819 */
/* 0x000fe20000011602 */
/*00c0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe200078e00ff */
/*00d0*/ BSSY B0, 0x240 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*00e0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x40668000 ; /* 0x40668000ff0b7424 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD.WIDE.U32 R4, R4, 0x16c16c17, RZ ; /* 0x16c16c1704047825 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe200078e00ff */
/*0110*/ SHF.R.U32.HI R9, RZ, 0x2, R5 ; /* 0x00000002ff097819 */
/* 0x000fca0000011605 */
/*0120*/ DFMA R4, R6, -R10, 1 ; /* 0x3ff000000604742b */
/* 0x001e22000000080a */
/*0130*/ IMAD R14, R9, -0x168, R2 ; /* 0xfffffe98090e7824 */
/* 0x000fca00078e0202 */
/*0140*/ DFMA R8, R4, R4, R4 ; /* 0x000000040408722b */
/* 0x0010480000000004 */
/*0150*/ I2F.F64.U32 R4, R14 ; /* 0x0000000e00047312 */
/* 0x001e240000201800 */
/*0160*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x002e4c0000000006 */
/*0170*/ DFMA R6, R8, -R10, 1 ; /* 0x3ff000000806742b */
/* 0x002e4c000000080a */
/*0180*/ DFMA R6, R8, R6, R8 ; /* 0x000000060806722b */
/* 0x002fc80000000008 */
/*0190*/ DMUL R12, R4, c[0x2][0x0] ; /* 0x00800000040c7a28 */
/* 0x001e0c0000000000 */
/*01a0*/ DMUL R4, R12, R6 ; /* 0x000000060c047228 */
/* 0x001e080000000000 */
/*01b0*/ FSETP.GEU.AND P1, PT, |R13|, 6.5827683646048100446e-37, PT ; /* 0x036000000d00780b */
/* 0x000fe40003f2e200 */
/*01c0*/ DFMA R8, R4, -180, R12 ; /* 0xc06680000408782b */
/* 0x001e0c000000000c */
/*01d0*/ DFMA R4, R6, R8, R4 ; /* 0x000000080604722b */
/* 0x001e140000000004 */
/*01e0*/ FFMA R6, RZ, 3.6015625, R5 ; /* 0x40668000ff067823 */
/* 0x001fca0000000005 */
/*01f0*/ FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; /* 0x001000000600780b */
/* 0x000fda0003f04200 */
/*0200*/ @P0 BRA P1, 0x230 ; /* 0x0000002000000947 */
/* 0x000fea0000800000 */
/*0210*/ MOV R10, 0x230 ; /* 0x00000230000a7802 */
/* 0x000fe40000000f00 */
/*0220*/ CALL.REL.NOINC 0x330 ; /* 0x0000010000007944 */
/* 0x000fea0003c00000 */
/*0230*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0240*/ F2F.F32.F64 R4, R4 ; /* 0x0000000400047310 */
/* 0x000e220000301000 */
/*0250*/ LEA R8, P0, R3, c[0x0][0x160], 0x3 ; /* 0x0000580003087a11 */
/* 0x000fc800078018ff */
/*0260*/ LEA.HI.X R9, R3, c[0x0][0x164], R0, 0x3, P0 ; /* 0x0000590003097a11 */
/* 0x000fe200000f1c00 */
/*0270*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x000fe400078e00ff */
/*0280*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*0290*/ IMAD R3, R3, c[0x0][0xc], R2 ; /* 0x0000030003037a24 */
/* 0x000fc800078e0202 */
/*02a0*/ IMAD.MOV.U32 R2, RZ, RZ, R3 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0003 */
/*02b0*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fe20003f06070 */
/*02c0*/ FMUL.RZ R10, R4, 0.15915493667125701904 ; /* 0x3e22f983040a7820 */
/* 0x001fc6000040c000 */
/*02d0*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x16c], PT, P0 ; /* 0x00005b00ff007a0c */
/* 0x000fe20003f06100 */
/*02e0*/ MUFU.SIN R6, R10 ; /* 0x0000000a00067308 */
/* 0x000e300000000400 */
/*02f0*/ F2F.F64.F32 R6, R6 ; /* 0x0000000600067310 */
/* 0x001e240000201800 */
/*0300*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x0011e4000c101b04 */
/*0310*/ @!P0 BRA 0xa0 ; /* 0xfffffd8000008947 */
/* 0x000fea000383ffff */
/*0320*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0330*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3ff68000 ; /* 0x3ff68000ff057424 */
/* 0x000fe200078e00ff */
/*0340*/ BSSY B1, 0x810 ; /* 0x000004c000017945 */
/* 0x000fe20003800000 */
/*0350*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fc400078e000d */
/*0360*/ MUFU.RCP64H R9, R5 ; /* 0x0000000500097308 */
/* 0x000e220000001800 */
/*0370*/ IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff047424 */
/* 0x000fe400078e00ff */
/*0380*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*0390*/ FSETP.GEU.AND P1, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f2e200 */
/*03a0*/ IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000c */
/*03b0*/ LOP3.LUT R11, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000070b7812 */
/* 0x000fe200078ec0ff */
/*03c0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff107424 */
/* 0x000fe400078e00ff */
/*03d0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x40600000 ; /* 0x40600000ff157424 */
/* 0x000fe200078e00ff */
/*03e0*/ ISETP.GE.U32.AND P0, PT, R11, 0x40600000, PT ; /* 0x406000000b00780c */
/* 0x000fe20003f06070 */
/*03f0*/ IMAD.MOV.U32 R20, RZ, RZ, R11 ; /* 0x000000ffff147224 */
/* 0x000fc600078e000b */
/*0400*/ IADD3 R22, R21, -0x1, RZ ; /* 0xffffffff15167810 */
/* 0x000fe20007ffe0ff */
/*0410*/ DFMA R12, R8, -R4, 1 ; /* 0x3ff00000080c742b */
/* 0x001e0c0000000804 */
/*0420*/ DFMA R14, R12, R12, R12 ; /* 0x0000000c0c0e722b */
/* 0x001064000000000c */
/*0430*/ SEL R13, R16, 0x63400000, !P0 ; /* 0x63400000100d7807 */
/* 0x001fc80004000000 */
/*0440*/ @!P1 LOP3.LUT R12, R13.reuse, 0x80000000, R7.reuse, 0xf8, !PT ; /* 0x800000000d0c9812 */
/* 0x140fe200078ef807 */
/*0450*/ DFMA R16, R8, R14, R8 ; /* 0x0000000e0810722b */
/* 0x0020640000000008 */
/*0460*/ LOP3.LUT R9, R13, 0x800fffff, R7, 0xf8, !PT ; /* 0x800fffff0d097812 */
/* 0x001fe200078ef807 */
/*0470*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0006 */
/*0480*/ @!P1 LOP3.LUT R15, R12, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000c0f9812 */
/* 0x000fe200078efcff */
/*0490*/ @!P1 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e9224 */
/* 0x000fe200078e00ff */
/*04a0*/ DFMA R18, R16, -R4, 1 ; /* 0x3ff000001012742b */
/* 0x002e0a0000000804 */
/*04b0*/ @!P1 DFMA R8, R8, 2, -R14 ; /* 0x400000000808982b */
/* 0x000e48000000080e */
/*04c0*/ DFMA R14, R16, R18, R16 ; /* 0x00000012100e722b */
/* 0x001e0c0000000010 */
/*04d0*/ @!P1 LOP3.LUT R20, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009149812 */
/* 0x002fe200078ec0ff */
/*04e0*/ DMUL R16, R14, R8 ; /* 0x000000080e107228 */
/* 0x001e060000000000 */
/*04f0*/ IADD3 R12, R20, -0x1, RZ ; /* 0xffffffff140c7810 */
/* 0x000fc60007ffe0ff */
/*0500*/ DFMA R18, R16, -R4, R8 ; /* 0x800000041012722b */
/* 0x001e220000000008 */
/*0510*/ ISETP.GT.U32.AND P0, PT, R12, 0x7feffffe, PT ; /* 0x7feffffe0c00780c */
/* 0x000fc80003f04070 */
/*0520*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fe20000704470 */
/*0530*/ DFMA R14, R14, R18, R16 ; /* 0x000000120e0e722b */
/* 0x0010580000000010 */
/*0540*/ @P0 BRA 0x6f0 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*0550*/ IADD3 R11, R11, -0x40600000, RZ ; /* 0xbfa000000b0b7810 */
/* 0x003fc80007ffe0ff */
/*0560*/ IMNMX R11, R11, -0x46a00000, !PT ; /* 0xb96000000b0b7817 */
/* 0x000fc80007800200 */
/*0570*/ IMNMX R6, R11, 0x46a00000, PT ; /* 0x46a000000b067817 */
/* 0x000fca0003800200 */
/*0580*/ IMAD.IADD R11, R6, 0x1, -R13 ; /* 0x00000001060b7824 */
/* 0x000fe400078e0a0d */
/*0590*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*05a0*/ IADD3 R7, R11, 0x7fe00000, RZ ; /* 0x7fe000000b077810 */
/* 0x000fcc0007ffe0ff */
/*05b0*/ DMUL R12, R14, R6 ; /* 0x000000060e0c7228 */
/* 0x000e140000000000 */
/*05c0*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x001fda0003f0c200 */
/*05d0*/ @P0 BRA 0x800 ; /* 0x0000022000000947 */
/* 0x000fea0003800000 */
/*05e0*/ DFMA R4, R14, -R4, R8 ; /* 0x800000040e04722b */
/* 0x000e220000000008 */
/*05f0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fd200078e00ff */
/*0600*/ FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720b */
/* 0x041fe40003f0d000 */
/*0610*/ LOP3.LUT R4, R5, 0x40668000, RZ, 0x3c, !PT ; /* 0x4066800005047812 */
/* 0x000fc800078e3cff */
/*0620*/ LOP3.LUT R9, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004097812 */
/* 0x000fc800078ec0ff */
/*0630*/ LOP3.LUT R7, R9, R7, RZ, 0xfc, !PT ; /* 0x0000000709077212 */
/* 0x000fc600078efcff */
/*0640*/ @!P0 BRA 0x800 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0650*/ IMAD.MOV R5, RZ, RZ, -R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a0b */
/*0660*/ DMUL.RP R6, R14, R6 ; /* 0x000000060e067228 */
/* 0x000e220000008000 */
/*0670*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fcc00078e00ff */
/*0680*/ DFMA R4, R12, -R4, R14 ; /* 0x800000040c04722b */
/* 0x000e46000000000e */
/*0690*/ LOP3.LUT R9, R7, R9, RZ, 0x3c, !PT ; /* 0x0000000907097212 */
/* 0x001fc600078e3cff */
/*06a0*/ IADD3 R4, -R11, -0x43300000, RZ ; /* 0xbcd000000b047810 */
/* 0x002fc80007ffe1ff */
/*06b0*/ FSETP.NEU.AND P0, PT, |R5|, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f0d200 */
/*06c0*/ FSEL R12, R6, R12, !P0 ; /* 0x0000000c060c7208 */
/* 0x000fe40004000000 */
/*06d0*/ FSEL R13, R9, R13, !P0 ; /* 0x0000000d090d7208 */
/* 0x000fe20004000000 */
/*06e0*/ BRA 0x800 ; /* 0x0000011000007947 */
/* 0x000fea0003800000 */
/*06f0*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x003e1c0003f08000 */
/*0700*/ @P0 BRA 0x7e0 ; /* 0x000000d000000947 */
/* 0x001fea0003800000 */
/*0710*/ ISETP.NE.AND P0, PT, R20, R21, PT ; /* 0x000000151400720c */
/* 0x000fe20003f05270 */
/*0720*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*0730*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*0740*/ @!P0 BRA 0x800 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0750*/ ISETP.NE.AND P0, PT, R20, 0x7ff00000, PT ; /* 0x7ff000001400780c */
/* 0x000fe40003f05270 */
/*0760*/ LOP3.LUT R6, R7, 0x40668000, RZ, 0x3c, !PT ; /* 0x4066800007067812 */
/* 0x000fe400078e3cff */
/*0770*/ ISETP.EQ.OR P0, PT, R21, RZ, !P0 ; /* 0x000000ff1500720c */
/* 0x000fe40004702670 */
/*0780*/ LOP3.LUT R13, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x80000000060d7812 */
/* 0x000fd600078ec0ff */
/*0790*/ @P0 LOP3.LUT R4, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d040812 */
/* 0x000fe200078efcff */
/*07a0*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*07b0*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*07c0*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R4 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0004 */
/*07d0*/ BRA 0x800 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*07e0*/ LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070d7812 */
/* 0x000fe200078efcff */
/*07f0*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0006 */
/*0800*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0810*/ IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; /* 0x00000000ff0b7424 */
/* 0x000fe400078e00ff */
/*0820*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000c */
/*0830*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000d */
/*0840*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff7b00a007950 */
/* 0x000fec0003c3ffff */
/*0850*/ BRA 0x850; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
/*
Cource - "Разработка приложений на CUDA "
Task 1:
Выделить на GPU массив arr из 10^9 элементов типа
float и инициализировать его с помощью ядра следующим образом:
arr[i] = sin((i%360)*Pi/180). Скопировать массив в память центрального
процессора и посчитать ошибку err = sum_i(abs(sin((i%360)*Pi/180)
- arr[i]))/10^9. Провести исследование зависимости результата от использования
функций: sin, sinf, __sin. Объяснить результат. Проверить результат
при использовании массива типа double.
Written by Pavel Santaev
*/
#include <stdio.h>
#include <unistd.h>
#include <math.h>
typedef double arrType;
__global__ void calcSin(arrType * a, size_t len){
unsigned int index = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int i = index;
size_t threadsCount = blockDim.x * gridDim.x;
while (i < len){
double value = ((arrType)(i % 360)) * M_PI / 180;
a[i] = __sinf(value);
i = i + threadsCount;
}
}
double calcErr(arrType * arr, size_t len){
double sum = 0;
for (int i = 0; i < len; i++){
sum += abs(sin((i % 360) * M_PI / 180) - arr[i]);
}
return sum / len;
}
int main(){
size_t N = 1000 * 1000 * 100;
size_t size = sizeof(arrType) * N;
arrType * ptr;
cudaError_t error;
int deviceCount = 0;
error = cudaGetDeviceCount(&deviceCount);
if (cudaSuccess != error){
printf("Error in cudaGetDeviceCount: %s\n", cudaGetErrorString(error));
return 0;
}
printf("cudaGetDeviceCount = %x\n", deviceCount);
int deviceID = 1;
cudaDeviceProp devProp;
error = cudaGetDeviceProperties(&devProp, deviceID);
if (cudaSuccess != error){
printf("Error in cudaGetDeviceProperties: %d\n", cudaGetErrorString(error));
return 0;
}
printf ( "Device %d\n", 0 );
printf ( "Compute capability : %d.%d\n", devProp.major, devProp.minor );
printf ( "Name : %s\n", devProp.name );
printf ( "Total Global Memory : %d\n", devProp.totalGlobalMem );
printf ( "Shared memory per block: %d\n", devProp.sharedMemPerBlock );
printf ( "Registers per block : %d\n", devProp.regsPerBlock );
printf ( "Warp size : %d\n", devProp.warpSize );
printf ( "Max threads per block : %d\n", devProp.maxThreadsPerBlock );
printf ( "Total constant memory : %d\n", devProp.totalConstMem );
printf ( "Max Grid Size : %d %d %d\n", devProp.maxGridSize[0], devProp.maxGridSize[1], devProp.maxGridSize[2]);
printf ( "Max Threads Dim : %d %d %d\n", devProp.maxThreadsDim[0], devProp.maxThreadsDim[1], devProp.maxThreadsDim[2]);
cudaSetDevice(deviceID);
printf("sizeof size_t %d \n", sizeof(size_t));
printf("sizeof type %d \n", sizeof(arrType));
printf("allocating %u memory\n", size);
cudaMalloc(&ptr, size);
dim3 threads = dim3(devProp.maxThreadsPerBlock, 1);
dim3 blocks = dim3(128, 1);
calcSin<<<blocks, threads>>>(ptr, N);
int i = 0;
arrType * hostPtr;
hostPtr = (arrType *)malloc(size);
cudaMemcpy(hostPtr, ptr, size, cudaMemcpyDeviceToHost);
for (i = 0; i < 10; i++){
printf("%f ", hostPtr[i]);
}
printf("\nerror = %0.10f ", calcErr(hostPtr, N));
cudaFree(ptr);
free(hostPtr);
printf("\nfinished\n");
}
|
.file "tmpxft_00089b81_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7calcErrPdm
.type _Z7calcErrPdm, @function
_Z7calcErrPdm:
.LFB2070:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %rbp
testq %rsi, %rsi
je .L8
movq %rdi, %r12
movq $0x000000000, 8(%rsp)
movl $0, %ebx
.L5:
movslq %ebx, %rax
imulq $-1240768329, %rax, %rax
shrq $32, %rax
addl %ebx, %eax
sarl $8, %eax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
imull $360, %eax, %eax
movl %ebx, %edx
subl %eax, %edx
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
mulsd .LC1(%rip), %xmm0
divsd .LC2(%rip), %xmm0
call sin@PLT
subsd (%r12,%rbx,8), %xmm0
andpd .LC3(%rip), %xmm0
addsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
addq $1, %rbx
cmpq %rbp, %rbx
jne .L5
.L4:
testq %rbp, %rbp
js .L6
pxor %xmm1, %xmm1
cvtsi2sdq %rbp, %xmm1
.L7:
movsd 8(%rsp), %xmm0
divsd %xmm1, %xmm0
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
movq $0x000000000, 8(%rsp)
jmp .L4
.L6:
movq %rbp, %rax
shrq %rax
andl $1, %ebp
orq %rbp, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm1
jmp .L7
.cfi_endproc
.LFE2070:
.size _Z7calcErrPdm, .-_Z7calcErrPdm
.globl _Z27__device_stub__Z7calcSinPdmPdm
.type _Z27__device_stub__Z7calcSinPdmPdm, @function
_Z27__device_stub__Z7calcSinPdmPdm:
.LFB2096:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7calcSinPdm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z27__device_stub__Z7calcSinPdmPdm, .-_Z27__device_stub__Z7calcSinPdmPdm
.globl _Z7calcSinPdm
.type _Z7calcSinPdm, @function
_Z7calcSinPdm:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7calcSinPdmPdm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z7calcSinPdm, .-_Z7calcSinPdm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Error in cudaGetDeviceCount: %s\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "cudaGetDeviceCount = %x\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "Error in cudaGetDeviceProperties: %d\n"
.section .rodata.str1.1
.LC7:
.string "Device %d\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "Compute capability : %d.%d\n"
.section .rodata.str1.1
.LC9:
.string "Name : %s\n"
.LC10:
.string "Total Global Memory : %d\n"
.LC11:
.string "Shared memory per block: %d\n"
.LC12:
.string "Registers per block : %d\n"
.LC13:
.string "Warp size : %d\n"
.LC14:
.string "Max threads per block : %d\n"
.LC15:
.string "Total constant memory : %d\n"
.LC16:
.string "Max Grid Size : %d %d %d\n"
.LC17:
.string "Max Threads Dim : %d %d %d\n"
.LC18:
.string "sizeof size_t %d \n"
.LC19:
.string "sizeof type %d \n"
.LC20:
.string "allocating %u memory\n"
.LC21:
.string "%f "
.LC22:
.string "\nerror = %0.10f "
.LC23:
.string "\nfinished\n"
.text
.globl main
.type main, @function
main:
.LFB2071:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1096, %rsp
.cfi_def_cfa_offset 1136
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L28
movl 12(%rsp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rdi
movl $1, %esi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L29
movl $0, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 412(%rsp), %ecx
movl 408(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 336(%rsp), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 344(%rsp), %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 352(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 356(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 368(%rsp), %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 400(%rsp), %rdx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 392(%rsp), %r8d
movl 388(%rsp), %ecx
movl 384(%rsp), %edx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %r8d
movl 376(%rsp), %ecx
movl 372(%rsp), %edx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call cudaSetDevice@PLT
movl $8, %edx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $8, %edx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $800000000, %edx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rdi
movl $800000000, %esi
call cudaMalloc@PLT
movl 368(%rsp), %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl $128, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L23:
movl $800000000, %edi
call malloc@PLT
movq %rax, %r13
movl $2, %ecx
movl $800000000, %edx
movq 16(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movq %r13, %rbx
leaq 80(%r13), %r12
leaq .LC21(%rip), %rbp
.L24:
movsd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %r12, %rbx
jne .L24
movl $100000000, %esi
movq %r13, %rdi
call _Z7calcErrPdm
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L21:
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $1096, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L21
.L29:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L21
.L30:
movl $100000000, %esi
movq 16(%rsp), %rdi
call _Z27__device_stub__Z7calcSinPdmPdm
jmp .L23
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size main, .-main
.section .rodata.str1.1
.LC24:
.string "_Z7calcSinPdm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC24(%rip), %rdx
movq %rdx, %rcx
leaq _Z7calcSinPdm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 1413754136
.long 1074340347
.align 8
.LC2:
.long 0
.long 1080459264
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC3:
.long -1
.long 2147483647
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/*
Cource - "Разработка приложений на CUDA "
Task 1:
Выделить на GPU массив arr из 10^9 элементов типа
float и инициализировать его с помощью ядра следующим образом:
arr[i] = sin((i%360)*Pi/180). Скопировать массив в память центрального
процессора и посчитать ошибку err = sum_i(abs(sin((i%360)*Pi/180)
- arr[i]))/10^9. Провести исследование зависимости результата от использования
функций: sin, sinf, __sin. Объяснить результат. Проверить результат
при использовании массива типа double.
Written by Pavel Santaev
*/
#include <stdio.h>
#include <unistd.h>
#include <math.h>
typedef double arrType;
__global__ void calcSin(arrType * a, size_t len){
unsigned int index = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int i = index;
size_t threadsCount = blockDim.x * gridDim.x;
while (i < len){
double value = ((arrType)(i % 360)) * M_PI / 180;
a[i] = __sinf(value);
i = i + threadsCount;
}
}
double calcErr(arrType * arr, size_t len){
double sum = 0;
for (int i = 0; i < len; i++){
sum += abs(sin((i % 360) * M_PI / 180) - arr[i]);
}
return sum / len;
}
int main(){
size_t N = 1000 * 1000 * 100;
size_t size = sizeof(arrType) * N;
arrType * ptr;
cudaError_t error;
int deviceCount = 0;
error = cudaGetDeviceCount(&deviceCount);
if (cudaSuccess != error){
printf("Error in cudaGetDeviceCount: %s\n", cudaGetErrorString(error));
return 0;
}
printf("cudaGetDeviceCount = %x\n", deviceCount);
int deviceID = 1;
cudaDeviceProp devProp;
error = cudaGetDeviceProperties(&devProp, deviceID);
if (cudaSuccess != error){
printf("Error in cudaGetDeviceProperties: %d\n", cudaGetErrorString(error));
return 0;
}
printf ( "Device %d\n", 0 );
printf ( "Compute capability : %d.%d\n", devProp.major, devProp.minor );
printf ( "Name : %s\n", devProp.name );
printf ( "Total Global Memory : %d\n", devProp.totalGlobalMem );
printf ( "Shared memory per block: %d\n", devProp.sharedMemPerBlock );
printf ( "Registers per block : %d\n", devProp.regsPerBlock );
printf ( "Warp size : %d\n", devProp.warpSize );
printf ( "Max threads per block : %d\n", devProp.maxThreadsPerBlock );
printf ( "Total constant memory : %d\n", devProp.totalConstMem );
printf ( "Max Grid Size : %d %d %d\n", devProp.maxGridSize[0], devProp.maxGridSize[1], devProp.maxGridSize[2]);
printf ( "Max Threads Dim : %d %d %d\n", devProp.maxThreadsDim[0], devProp.maxThreadsDim[1], devProp.maxThreadsDim[2]);
cudaSetDevice(deviceID);
printf("sizeof size_t %d \n", sizeof(size_t));
printf("sizeof type %d \n", sizeof(arrType));
printf("allocating %u memory\n", size);
cudaMalloc(&ptr, size);
dim3 threads = dim3(devProp.maxThreadsPerBlock, 1);
dim3 blocks = dim3(128, 1);
calcSin<<<blocks, threads>>>(ptr, N);
int i = 0;
arrType * hostPtr;
hostPtr = (arrType *)malloc(size);
cudaMemcpy(hostPtr, ptr, size, cudaMemcpyDeviceToHost);
for (i = 0; i < 10; i++){
printf("%f ", hostPtr[i]);
}
printf("\nerror = %0.10f ", calcErr(hostPtr, N));
cudaFree(ptr);
free(hostPtr);
printf("\nfinished\n");
}
|
/*
Cource - "Разработка приложений на CUDA "
Task 1:
Выделить на GPU массив arr из 10^9 элементов типа
float и инициализировать его с помощью ядра следующим образом:
arr[i] = sin((i%360)*Pi/180). Скопировать массив в память центрального
процессора и посчитать ошибку err = sum_i(abs(sin((i%360)*Pi/180)
- arr[i]))/10^9. Провести исследование зависимости результата от использования
функций: sin, sinf, __sin. Объяснить результат. Проверить результат
при использовании массива типа double.
Written by Pavel Santaev
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <unistd.h>
#include <math.h>
typedef double arrType;
__global__ void calcSin(arrType * a, size_t len){
unsigned int index = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int i = index;
size_t threadsCount = blockDim.x * gridDim.x;
while (i < len){
double value = ((arrType)(i % 360)) * M_PI / 180;
a[i] = __sinf(value);
i = i + threadsCount;
}
}
double calcErr(arrType * arr, size_t len){
double sum = 0;
for (int i = 0; i < len; i++){
sum += abs(sin((i % 360) * M_PI / 180) - arr[i]);
}
return sum / len;
}
int main(){
size_t N = 1000 * 1000 * 100;
size_t size = sizeof(arrType) * N;
arrType * ptr;
hipError_t error;
int deviceCount = 0;
error = hipGetDeviceCount(&deviceCount);
if (hipSuccess != error){
printf("Error in cudaGetDeviceCount: %s\n", hipGetErrorString(error));
return 0;
}
printf("hipGetDeviceCount = %x\n", deviceCount);
int deviceID = 1;
hipDeviceProp_t devProp;
error = hipGetDeviceProperties(&devProp, deviceID);
if (hipSuccess != error){
printf("Error in cudaGetDeviceProperties: %d\n", hipGetErrorString(error));
return 0;
}
printf ( "Device %d\n", 0 );
printf ( "Compute capability : %d.%d\n", devProp.major, devProp.minor );
printf ( "Name : %s\n", devProp.name );
printf ( "Total Global Memory : %d\n", devProp.totalGlobalMem );
printf ( "Shared memory per block: %d\n", devProp.sharedMemPerBlock );
printf ( "Registers per block : %d\n", devProp.regsPerBlock );
printf ( "Warp size : %d\n", devProp.warpSize );
printf ( "Max threads per block : %d\n", devProp.maxThreadsPerBlock );
printf ( "Total constant memory : %d\n", devProp.totalConstMem );
printf ( "Max Grid Size : %d %d %d\n", devProp.maxGridSize[0], devProp.maxGridSize[1], devProp.maxGridSize[2]);
printf ( "Max Threads Dim : %d %d %d\n", devProp.maxThreadsDim[0], devProp.maxThreadsDim[1], devProp.maxThreadsDim[2]);
hipSetDevice(deviceID);
printf("sizeof size_t %d \n", sizeof(size_t));
printf("sizeof type %d \n", sizeof(arrType));
printf("allocating %u memory\n", size);
hipMalloc(&ptr, size);
dim3 threads = dim3(devProp.maxThreadsPerBlock, 1);
dim3 blocks = dim3(128, 1);
calcSin<<<blocks, threads>>>(ptr, N);
int i = 0;
arrType * hostPtr;
hostPtr = (arrType *)malloc(size);
hipMemcpy(hostPtr, ptr, size, hipMemcpyDeviceToHost);
for (i = 0; i < 10; i++){
printf("%f ", hostPtr[i]);
}
printf("\nerror = %0.10f ", calcErr(hostPtr, N));
hipFree(ptr);
free(hostPtr);
printf("\nfinished\n");
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
/*
Cource - "Разработка приложений на CUDA "
Task 1:
Выделить на GPU массив arr из 10^9 элементов типа
float и инициализировать его с помощью ядра следующим образом:
arr[i] = sin((i%360)*Pi/180). Скопировать массив в память центрального
процессора и посчитать ошибку err = sum_i(abs(sin((i%360)*Pi/180)
- arr[i]))/10^9. Провести исследование зависимости результата от использования
функций: sin, sinf, __sin. Объяснить результат. Проверить результат
при использовании массива типа double.
Written by Pavel Santaev
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <unistd.h>
#include <math.h>
typedef double arrType;
__global__ void calcSin(arrType * a, size_t len){
unsigned int index = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int i = index;
size_t threadsCount = blockDim.x * gridDim.x;
while (i < len){
double value = ((arrType)(i % 360)) * M_PI / 180;
a[i] = __sinf(value);
i = i + threadsCount;
}
}
double calcErr(arrType * arr, size_t len){
double sum = 0;
for (int i = 0; i < len; i++){
sum += abs(sin((i % 360) * M_PI / 180) - arr[i]);
}
return sum / len;
}
int main(){
size_t N = 1000 * 1000 * 100;
size_t size = sizeof(arrType) * N;
arrType * ptr;
hipError_t error;
int deviceCount = 0;
error = hipGetDeviceCount(&deviceCount);
if (hipSuccess != error){
printf("Error in cudaGetDeviceCount: %s\n", hipGetErrorString(error));
return 0;
}
printf("hipGetDeviceCount = %x\n", deviceCount);
int deviceID = 1;
hipDeviceProp_t devProp;
error = hipGetDeviceProperties(&devProp, deviceID);
if (hipSuccess != error){
printf("Error in cudaGetDeviceProperties: %d\n", hipGetErrorString(error));
return 0;
}
printf ( "Device %d\n", 0 );
printf ( "Compute capability : %d.%d\n", devProp.major, devProp.minor );
printf ( "Name : %s\n", devProp.name );
printf ( "Total Global Memory : %d\n", devProp.totalGlobalMem );
printf ( "Shared memory per block: %d\n", devProp.sharedMemPerBlock );
printf ( "Registers per block : %d\n", devProp.regsPerBlock );
printf ( "Warp size : %d\n", devProp.warpSize );
printf ( "Max threads per block : %d\n", devProp.maxThreadsPerBlock );
printf ( "Total constant memory : %d\n", devProp.totalConstMem );
printf ( "Max Grid Size : %d %d %d\n", devProp.maxGridSize[0], devProp.maxGridSize[1], devProp.maxGridSize[2]);
printf ( "Max Threads Dim : %d %d %d\n", devProp.maxThreadsDim[0], devProp.maxThreadsDim[1], devProp.maxThreadsDim[2]);
hipSetDevice(deviceID);
printf("sizeof size_t %d \n", sizeof(size_t));
printf("sizeof type %d \n", sizeof(arrType));
printf("allocating %u memory\n", size);
hipMalloc(&ptr, size);
dim3 threads = dim3(devProp.maxThreadsPerBlock, 1);
dim3 blocks = dim3(128, 1);
calcSin<<<blocks, threads>>>(ptr, N);
int i = 0;
arrType * hostPtr;
hostPtr = (arrType *)malloc(size);
hipMemcpy(hostPtr, ptr, size, hipMemcpyDeviceToHost);
for (i = 0; i < 10; i++){
printf("%f ", hostPtr[i]);
}
printf("\nerror = %0.10f ", calcErr(hostPtr, N));
hipFree(ptr);
free(hostPtr);
printf("\nfinished\n");
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7calcSinPdm
.globl _Z7calcSinPdm
.p2align 8
.type _Z7calcSinPdm,@function
_Z7calcSinPdm:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_add_u32 s4, s0, 16
s_addc_u32 s5, s1, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[2:3]
s_cbranch_execz .LBB0_3
s_load_b32 s7, s[4:5], 0x0
s_load_b64 s[4:5], s[0:1], 0x0
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_mov_b32 s8, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s15, s15, s7
s_mul_i32 s1, s7, s6
v_mad_u64_u32 v[6:7], null, s15, s6, v[0:1]
s_mov_b32 s7, 0x400921fb
s_mov_b32 s6, 0x54442d18
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v6
.LBB0_2:
v_lshrrev_b32_e32 v0, 3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v0, 0x16c16c17
v_lshrrev_b32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v0, 0x168, v0
v_sub_nc_u32_e32 v0, v1, v0
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_u32_e32 v[6:7], v0
v_mul_f64 v[6:7], v[6:7], s[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[8:9], null, 0x40668000, 0x40668000, v[6:7]
v_div_scale_f64 v[14:15], vcc_lo, v[6:7], 0x40668000, v[6:7]
v_rcp_f64_e32 v[10:11], v[8:9]
s_waitcnt_depctr 0xfff
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
v_mul_f64 v[12:13], v[14:15], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[8:9], v[12:13], v[14:15]
v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[12:13]
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[2:3]
s_or_b32 s8, vcc_lo, s8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[6:7], v[8:9], 0x40668000, v[6:7]
v_lshlrev_b64 v[8:9], 3, v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
v_add_nc_u32_e32 v2, s1, v2
v_add_co_u32 v8, s0, s4, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s0, s5, v9, s0
v_cvt_f32_f64_e32 v0, v[6:7]
v_mul_f32_e32 v0, 0.15915494, v0
s_delay_alu instid0(VALU_DEP_1)
v_sin_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_cvt_f64_f32_e32 v[6:7], v0
global_store_b64 v[8:9], v[6:7], off
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7calcSinPdm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7calcSinPdm, .Lfunc_end0-_Z7calcSinPdm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7calcSinPdm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7calcSinPdm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
/*
Cource - "Разработка приложений на CUDA "
Task 1:
Выделить на GPU массив arr из 10^9 элементов типа
float и инициализировать его с помощью ядра следующим образом:
arr[i] = sin((i%360)*Pi/180). Скопировать массив в память центрального
процессора и посчитать ошибку err = sum_i(abs(sin((i%360)*Pi/180)
- arr[i]))/10^9. Провести исследование зависимости результата от использования
функций: sin, sinf, __sin. Объяснить результат. Проверить результат
при использовании массива типа double.
Written by Pavel Santaev
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <unistd.h>
#include <math.h>
typedef double arrType;
__global__ void calcSin(arrType * a, size_t len){
unsigned int index = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int i = index;
size_t threadsCount = blockDim.x * gridDim.x;
while (i < len){
double value = ((arrType)(i % 360)) * M_PI / 180;
a[i] = __sinf(value);
i = i + threadsCount;
}
}
double calcErr(arrType * arr, size_t len){
double sum = 0;
for (int i = 0; i < len; i++){
sum += abs(sin((i % 360) * M_PI / 180) - arr[i]);
}
return sum / len;
}
int main(){
size_t N = 1000 * 1000 * 100;
size_t size = sizeof(arrType) * N;
arrType * ptr;
hipError_t error;
int deviceCount = 0;
error = hipGetDeviceCount(&deviceCount);
if (hipSuccess != error){
printf("Error in cudaGetDeviceCount: %s\n", hipGetErrorString(error));
return 0;
}
printf("hipGetDeviceCount = %x\n", deviceCount);
int deviceID = 1;
hipDeviceProp_t devProp;
error = hipGetDeviceProperties(&devProp, deviceID);
if (hipSuccess != error){
printf("Error in cudaGetDeviceProperties: %d\n", hipGetErrorString(error));
return 0;
}
printf ( "Device %d\n", 0 );
printf ( "Compute capability : %d.%d\n", devProp.major, devProp.minor );
printf ( "Name : %s\n", devProp.name );
printf ( "Total Global Memory : %d\n", devProp.totalGlobalMem );
printf ( "Shared memory per block: %d\n", devProp.sharedMemPerBlock );
printf ( "Registers per block : %d\n", devProp.regsPerBlock );
printf ( "Warp size : %d\n", devProp.warpSize );
printf ( "Max threads per block : %d\n", devProp.maxThreadsPerBlock );
printf ( "Total constant memory : %d\n", devProp.totalConstMem );
printf ( "Max Grid Size : %d %d %d\n", devProp.maxGridSize[0], devProp.maxGridSize[1], devProp.maxGridSize[2]);
printf ( "Max Threads Dim : %d %d %d\n", devProp.maxThreadsDim[0], devProp.maxThreadsDim[1], devProp.maxThreadsDim[2]);
hipSetDevice(deviceID);
printf("sizeof size_t %d \n", sizeof(size_t));
printf("sizeof type %d \n", sizeof(arrType));
printf("allocating %u memory\n", size);
hipMalloc(&ptr, size);
dim3 threads = dim3(devProp.maxThreadsPerBlock, 1);
dim3 blocks = dim3(128, 1);
calcSin<<<blocks, threads>>>(ptr, N);
int i = 0;
arrType * hostPtr;
hostPtr = (arrType *)malloc(size);
hipMemcpy(hostPtr, ptr, size, hipMemcpyDeviceToHost);
for (i = 0; i < 10; i++){
printf("%f ", hostPtr[i]);
}
printf("\nerror = %0.10f ", calcErr(hostPtr, N));
hipFree(ptr);
free(hostPtr);
printf("\nfinished\n");
}
|
.text
.file "main.hip"
.globl _Z22__device_stub__calcSinPdm # -- Begin function _Z22__device_stub__calcSinPdm
.p2align 4, 0x90
.type _Z22__device_stub__calcSinPdm,@function
_Z22__device_stub__calcSinPdm: # @_Z22__device_stub__calcSinPdm
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7calcSinPdm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__calcSinPdm, .Lfunc_end0-_Z22__device_stub__calcSinPdm
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7calcErrPdm
.LCPI1_0:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.LCPI1_1:
.quad 0x4066800000000000 # double 180
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_2:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.LCPI1_3:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI1_4:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.text
.globl _Z7calcErrPdm
.p2align 4, 0x90
.type _Z7calcErrPdm,@function
_Z7calcErrPdm: # @_Z7calcErrPdm
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
testq %rsi, %rsi
je .LBB1_1
# %bb.3: # %.lr.ph.preheader
movq %rdi, %r14
xorpd %xmm2, %xmm2
xorl %ebp, %ebp
movq %rbx, %r15
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd %xmm2, (%rsp) # 8-byte Spill
movl %ebp, %eax
shrl $3, %eax
imulq $381774871, %rax, %rax # imm = 0x16C16C17
shrq $34, %rax
imull $360, %eax, %eax # imm = 0x168
movl %ebp, %ecx
subl %eax, %ecx
xorps %xmm0, %xmm0
cvtsi2sd %ecx, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
divsd .LCPI1_1(%rip), %xmm0
callq sin
movsd (%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
subsd (%r14), %xmm0
andpd .LCPI1_2(%rip), %xmm0
addsd %xmm0, %xmm2
addq $8, %r14
incl %ebp
decq %r15
jne .LBB1_4
jmp .LBB1_2
.LBB1_1:
xorpd %xmm2, %xmm2
.LBB1_2: # %._crit_edge
movq %rbx, %xmm0
punpckldq .LCPI1_3(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd .LCPI1_4(%rip), %xmm0
movapd %xmm0, %xmm1
unpckhpd %xmm0, %xmm1 # xmm1 = xmm1[1],xmm0[1]
addsd %xmm0, %xmm1
divsd %xmm1, %xmm2
movapd %xmm2, %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z7calcErrPdm, .Lfunc_end1-_Z7calcErrPdm
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.LCPI2_1:
.quad 0x4066800000000000 # double 180
.LCPI2_3:
.quad 0x4197d78400000000 # double 1.0E+8
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI2_2:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1584, %rsp # imm = 0x630
.cfi_def_cfa_offset 1616
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
je .LBB2_3
# %bb.1:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
jmp .LBB2_2
.LBB2_3:
movl 12(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
leaq 112(%rsp), %rdi
movl $1, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
je .LBB2_5
# %bb.4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
.LBB2_2:
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_12:
xorl %eax, %eax
addq $1584, %rsp # imm = 0x630
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_5:
.cfi_def_cfa_offset 1616
movl $.L.str.3, %edi
xorl %esi, %esi
xorl %eax, %eax
callq printf
movl 472(%rsp), %esi
movl 476(%rsp), %edx
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
leaq 112(%rsp), %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movq 400(%rsp), %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq 408(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 416(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl 420(%rsp), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 432(%rsp), %esi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movq 464(%rsp), %rsi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl 448(%rsp), %esi
movl 452(%rsp), %edx
movl 456(%rsp), %ecx
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl 436(%rsp), %esi
movl 440(%rsp), %edx
movl 444(%rsp), %ecx
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movl $1, %edi
callq hipSetDevice
movl $.L.str.14, %edi
movl $8, %esi
xorl %eax, %eax
callq printf
movl $.L.str.15, %edi
movl $8, %esi
xorl %eax, %eax
callq printf
movl $.L.str.16, %edi
movl $800000000, %esi # imm = 0x2FAF0800
xorl %eax, %eax
callq printf
leaq 24(%rsp), %rdi
movl $800000000, %esi # imm = 0x2FAF0800
callq hipMalloc
movl 432(%rsp), %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $128, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 24(%rsp), %rax
movq %rax, 88(%rsp)
movq $100000000, 80(%rsp) # imm = 0x5F5E100
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7calcSinPdm, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7:
movl $800000000, %edi # imm = 0x2FAF0800
callq malloc
movq %rax, %rbx
movq 24(%rsp), %rsi
movl $800000000, %edx # imm = 0x2FAF0800
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_8: # =>This Inner Loop Header: Depth=1
movsd (%rbx,%r14,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.17, %edi
movb $1, %al
callq printf
incq %r14
cmpq $10, %r14
jne .LBB2_8
# %bb.9: # %.lr.ph.i.preheader
xorpd %xmm0, %xmm0
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_10: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movsd %xmm0, 16(%rsp) # 8-byte Spill
movl %r14d, %eax
shrl $3, %eax
imulq $381774871, %rax, %rax # imm = 0x16C16C17
shrq $34, %rax
imull $360, %eax, %eax # imm = 0x168
movl %r14d, %ecx
subl %eax, %ecx
xorps %xmm0, %xmm0
cvtsi2sd %ecx, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
divsd .LCPI2_1(%rip), %xmm0
callq sin
subsd (%rbx,%r15), %xmm0
andpd .LCPI2_2(%rip), %xmm0
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp) # 8-byte Spill
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addq $8, %r15
incl %r14d
cmpq $800000000, %r15 # imm = 0x2FAF0800
jne .LBB2_10
# %bb.11: # %_Z7calcErrPdm.exit
divsd .LCPI2_3(%rip), %xmm0
movl $.L.str.18, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movl $.Lstr, %edi
callq puts@PLT
jmp .LBB2_12
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7calcSinPdm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7calcSinPdm,@object # @_Z7calcSinPdm
.section .rodata,"a",@progbits
.globl _Z7calcSinPdm
.p2align 3, 0x0
_Z7calcSinPdm:
.quad _Z22__device_stub__calcSinPdm
.size _Z7calcSinPdm, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error in cudaGetDeviceCount: %s\n"
.size .L.str, 33
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipGetDeviceCount = %x\n"
.size .L.str.1, 24
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error in cudaGetDeviceProperties: %d\n"
.size .L.str.2, 38
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Device %d\n"
.size .L.str.3, 11
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Compute capability : %d.%d\n"
.size .L.str.4, 32
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Name : %s\n"
.size .L.str.5, 29
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Total Global Memory : %d\n"
.size .L.str.6, 29
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Shared memory per block: %d\n"
.size .L.str.7, 29
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Registers per block : %d\n"
.size .L.str.8, 29
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Warp size : %d\n"
.size .L.str.9, 29
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Max threads per block : %d\n"
.size .L.str.10, 29
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Total constant memory : %d\n"
.size .L.str.11, 29
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Max Grid Size : %d %d %d\n"
.size .L.str.12, 27
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Max Threads Dim : %d %d %d\n"
.size .L.str.13, 29
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "sizeof size_t %d \n"
.size .L.str.14, 19
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "sizeof type %d \n"
.size .L.str.15, 17
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "allocating %u memory\n"
.size .L.str.16, 22
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "%f "
.size .L.str.17, 4
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "\nerror = %0.10f "
.size .L.str.18, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7calcSinPdm"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nfinished"
.size .Lstr, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__calcSinPdm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7calcSinPdm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z7calcSinPdm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fc80003f06070 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x16c], PT, P0 ; /* 0x00005b00ff007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, R2 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0002 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ MUFU.RCP64H R7, 180 ; /* 0x4066800000077908 */
/* 0x001e220000001800 */
/*00b0*/ SHF.R.U32.HI R4, RZ, 0x3, R2 ; /* 0x00000003ff047819 */
/* 0x000fe20000011602 */
/*00c0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe200078e00ff */
/*00d0*/ BSSY B0, 0x240 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*00e0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x40668000 ; /* 0x40668000ff0b7424 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD.WIDE.U32 R4, R4, 0x16c16c17, RZ ; /* 0x16c16c1704047825 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe200078e00ff */
/*0110*/ SHF.R.U32.HI R9, RZ, 0x2, R5 ; /* 0x00000002ff097819 */
/* 0x000fca0000011605 */
/*0120*/ DFMA R4, R6, -R10, 1 ; /* 0x3ff000000604742b */
/* 0x001e22000000080a */
/*0130*/ IMAD R14, R9, -0x168, R2 ; /* 0xfffffe98090e7824 */
/* 0x000fca00078e0202 */
/*0140*/ DFMA R8, R4, R4, R4 ; /* 0x000000040408722b */
/* 0x0010480000000004 */
/*0150*/ I2F.F64.U32 R4, R14 ; /* 0x0000000e00047312 */
/* 0x001e240000201800 */
/*0160*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x002e4c0000000006 */
/*0170*/ DFMA R6, R8, -R10, 1 ; /* 0x3ff000000806742b */
/* 0x002e4c000000080a */
/*0180*/ DFMA R6, R8, R6, R8 ; /* 0x000000060806722b */
/* 0x002fc80000000008 */
/*0190*/ DMUL R12, R4, c[0x2][0x0] ; /* 0x00800000040c7a28 */
/* 0x001e0c0000000000 */
/*01a0*/ DMUL R4, R12, R6 ; /* 0x000000060c047228 */
/* 0x001e080000000000 */
/*01b0*/ FSETP.GEU.AND P1, PT, |R13|, 6.5827683646048100446e-37, PT ; /* 0x036000000d00780b */
/* 0x000fe40003f2e200 */
/*01c0*/ DFMA R8, R4, -180, R12 ; /* 0xc06680000408782b */
/* 0x001e0c000000000c */
/*01d0*/ DFMA R4, R6, R8, R4 ; /* 0x000000080604722b */
/* 0x001e140000000004 */
/*01e0*/ FFMA R6, RZ, 3.6015625, R5 ; /* 0x40668000ff067823 */
/* 0x001fca0000000005 */
/*01f0*/ FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; /* 0x001000000600780b */
/* 0x000fda0003f04200 */
/*0200*/ @P0 BRA P1, 0x230 ; /* 0x0000002000000947 */
/* 0x000fea0000800000 */
/*0210*/ MOV R10, 0x230 ; /* 0x00000230000a7802 */
/* 0x000fe40000000f00 */
/*0220*/ CALL.REL.NOINC 0x330 ; /* 0x0000010000007944 */
/* 0x000fea0003c00000 */
/*0230*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0240*/ F2F.F32.F64 R4, R4 ; /* 0x0000000400047310 */
/* 0x000e220000301000 */
/*0250*/ LEA R8, P0, R3, c[0x0][0x160], 0x3 ; /* 0x0000580003087a11 */
/* 0x000fc800078018ff */
/*0260*/ LEA.HI.X R9, R3, c[0x0][0x164], R0, 0x3, P0 ; /* 0x0000590003097a11 */
/* 0x000fe200000f1c00 */
/*0270*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x000fe400078e00ff */
/*0280*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*0290*/ IMAD R3, R3, c[0x0][0xc], R2 ; /* 0x0000030003037a24 */
/* 0x000fc800078e0202 */
/*02a0*/ IMAD.MOV.U32 R2, RZ, RZ, R3 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0003 */
/*02b0*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fe20003f06070 */
/*02c0*/ FMUL.RZ R10, R4, 0.15915493667125701904 ; /* 0x3e22f983040a7820 */
/* 0x001fc6000040c000 */
/*02d0*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x16c], PT, P0 ; /* 0x00005b00ff007a0c */
/* 0x000fe20003f06100 */
/*02e0*/ MUFU.SIN R6, R10 ; /* 0x0000000a00067308 */
/* 0x000e300000000400 */
/*02f0*/ F2F.F64.F32 R6, R6 ; /* 0x0000000600067310 */
/* 0x001e240000201800 */
/*0300*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x0011e4000c101b04 */
/*0310*/ @!P0 BRA 0xa0 ; /* 0xfffffd8000008947 */
/* 0x000fea000383ffff */
/*0320*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0330*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3ff68000 ; /* 0x3ff68000ff057424 */
/* 0x000fe200078e00ff */
/*0340*/ BSSY B1, 0x810 ; /* 0x000004c000017945 */
/* 0x000fe20003800000 */
/*0350*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fc400078e000d */
/*0360*/ MUFU.RCP64H R9, R5 ; /* 0x0000000500097308 */
/* 0x000e220000001800 */
/*0370*/ IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff047424 */
/* 0x000fe400078e00ff */
/*0380*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*0390*/ FSETP.GEU.AND P1, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f2e200 */
/*03a0*/ IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000c */
/*03b0*/ LOP3.LUT R11, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000070b7812 */
/* 0x000fe200078ec0ff */
/*03c0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff107424 */
/* 0x000fe400078e00ff */
/*03d0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x40600000 ; /* 0x40600000ff157424 */
/* 0x000fe200078e00ff */
/*03e0*/ ISETP.GE.U32.AND P0, PT, R11, 0x40600000, PT ; /* 0x406000000b00780c */
/* 0x000fe20003f06070 */
/*03f0*/ IMAD.MOV.U32 R20, RZ, RZ, R11 ; /* 0x000000ffff147224 */
/* 0x000fc600078e000b */
/*0400*/ IADD3 R22, R21, -0x1, RZ ; /* 0xffffffff15167810 */
/* 0x000fe20007ffe0ff */
/*0410*/ DFMA R12, R8, -R4, 1 ; /* 0x3ff00000080c742b */
/* 0x001e0c0000000804 */
/*0420*/ DFMA R14, R12, R12, R12 ; /* 0x0000000c0c0e722b */
/* 0x001064000000000c */
/*0430*/ SEL R13, R16, 0x63400000, !P0 ; /* 0x63400000100d7807 */
/* 0x001fc80004000000 */
/*0440*/ @!P1 LOP3.LUT R12, R13.reuse, 0x80000000, R7.reuse, 0xf8, !PT ; /* 0x800000000d0c9812 */
/* 0x140fe200078ef807 */
/*0450*/ DFMA R16, R8, R14, R8 ; /* 0x0000000e0810722b */
/* 0x0020640000000008 */
/*0460*/ LOP3.LUT R9, R13, 0x800fffff, R7, 0xf8, !PT ; /* 0x800fffff0d097812 */
/* 0x001fe200078ef807 */
/*0470*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0006 */
/*0480*/ @!P1 LOP3.LUT R15, R12, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000c0f9812 */
/* 0x000fe200078efcff */
/*0490*/ @!P1 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e9224 */
/* 0x000fe200078e00ff */
/*04a0*/ DFMA R18, R16, -R4, 1 ; /* 0x3ff000001012742b */
/* 0x002e0a0000000804 */
/*04b0*/ @!P1 DFMA R8, R8, 2, -R14 ; /* 0x400000000808982b */
/* 0x000e48000000080e */
/*04c0*/ DFMA R14, R16, R18, R16 ; /* 0x00000012100e722b */
/* 0x001e0c0000000010 */
/*04d0*/ @!P1 LOP3.LUT R20, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009149812 */
/* 0x002fe200078ec0ff */
/*04e0*/ DMUL R16, R14, R8 ; /* 0x000000080e107228 */
/* 0x001e060000000000 */
/*04f0*/ IADD3 R12, R20, -0x1, RZ ; /* 0xffffffff140c7810 */
/* 0x000fc60007ffe0ff */
/*0500*/ DFMA R18, R16, -R4, R8 ; /* 0x800000041012722b */
/* 0x001e220000000008 */
/*0510*/ ISETP.GT.U32.AND P0, PT, R12, 0x7feffffe, PT ; /* 0x7feffffe0c00780c */
/* 0x000fc80003f04070 */
/*0520*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fe20000704470 */
/*0530*/ DFMA R14, R14, R18, R16 ; /* 0x000000120e0e722b */
/* 0x0010580000000010 */
/*0540*/ @P0 BRA 0x6f0 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*0550*/ IADD3 R11, R11, -0x40600000, RZ ; /* 0xbfa000000b0b7810 */
/* 0x003fc80007ffe0ff */
/*0560*/ IMNMX R11, R11, -0x46a00000, !PT ; /* 0xb96000000b0b7817 */
/* 0x000fc80007800200 */
/*0570*/ IMNMX R6, R11, 0x46a00000, PT ; /* 0x46a000000b067817 */
/* 0x000fca0003800200 */
/*0580*/ IMAD.IADD R11, R6, 0x1, -R13 ; /* 0x00000001060b7824 */
/* 0x000fe400078e0a0d */
/*0590*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*05a0*/ IADD3 R7, R11, 0x7fe00000, RZ ; /* 0x7fe000000b077810 */
/* 0x000fcc0007ffe0ff */
/*05b0*/ DMUL R12, R14, R6 ; /* 0x000000060e0c7228 */
/* 0x000e140000000000 */
/*05c0*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x001fda0003f0c200 */
/*05d0*/ @P0 BRA 0x800 ; /* 0x0000022000000947 */
/* 0x000fea0003800000 */
/*05e0*/ DFMA R4, R14, -R4, R8 ; /* 0x800000040e04722b */
/* 0x000e220000000008 */
/*05f0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fd200078e00ff */
/*0600*/ FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720b */
/* 0x041fe40003f0d000 */
/*0610*/ LOP3.LUT R4, R5, 0x40668000, RZ, 0x3c, !PT ; /* 0x4066800005047812 */
/* 0x000fc800078e3cff */
/*0620*/ LOP3.LUT R9, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004097812 */
/* 0x000fc800078ec0ff */
/*0630*/ LOP3.LUT R7, R9, R7, RZ, 0xfc, !PT ; /* 0x0000000709077212 */
/* 0x000fc600078efcff */
/*0640*/ @!P0 BRA 0x800 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0650*/ IMAD.MOV R5, RZ, RZ, -R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a0b */
/*0660*/ DMUL.RP R6, R14, R6 ; /* 0x000000060e067228 */
/* 0x000e220000008000 */
/*0670*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fcc00078e00ff */
/*0680*/ DFMA R4, R12, -R4, R14 ; /* 0x800000040c04722b */
/* 0x000e46000000000e */
/*0690*/ LOP3.LUT R9, R7, R9, RZ, 0x3c, !PT ; /* 0x0000000907097212 */
/* 0x001fc600078e3cff */
/*06a0*/ IADD3 R4, -R11, -0x43300000, RZ ; /* 0xbcd000000b047810 */
/* 0x002fc80007ffe1ff */
/*06b0*/ FSETP.NEU.AND P0, PT, |R5|, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f0d200 */
/*06c0*/ FSEL R12, R6, R12, !P0 ; /* 0x0000000c060c7208 */
/* 0x000fe40004000000 */
/*06d0*/ FSEL R13, R9, R13, !P0 ; /* 0x0000000d090d7208 */
/* 0x000fe20004000000 */
/*06e0*/ BRA 0x800 ; /* 0x0000011000007947 */
/* 0x000fea0003800000 */
/*06f0*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x003e1c0003f08000 */
/*0700*/ @P0 BRA 0x7e0 ; /* 0x000000d000000947 */
/* 0x001fea0003800000 */
/*0710*/ ISETP.NE.AND P0, PT, R20, R21, PT ; /* 0x000000151400720c */
/* 0x000fe20003f05270 */
/*0720*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*0730*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*0740*/ @!P0 BRA 0x800 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0750*/ ISETP.NE.AND P0, PT, R20, 0x7ff00000, PT ; /* 0x7ff000001400780c */
/* 0x000fe40003f05270 */
/*0760*/ LOP3.LUT R6, R7, 0x40668000, RZ, 0x3c, !PT ; /* 0x4066800007067812 */
/* 0x000fe400078e3cff */
/*0770*/ ISETP.EQ.OR P0, PT, R21, RZ, !P0 ; /* 0x000000ff1500720c */
/* 0x000fe40004702670 */
/*0780*/ LOP3.LUT R13, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x80000000060d7812 */
/* 0x000fd600078ec0ff */
/*0790*/ @P0 LOP3.LUT R4, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d040812 */
/* 0x000fe200078efcff */
/*07a0*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*07b0*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*07c0*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R4 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0004 */
/*07d0*/ BRA 0x800 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*07e0*/ LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070d7812 */
/* 0x000fe200078efcff */
/*07f0*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0006 */
/*0800*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0810*/ IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; /* 0x00000000ff0b7424 */
/* 0x000fe400078e00ff */
/*0820*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000c */
/*0830*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000d */
/*0840*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff7b00a007950 */
/* 0x000fec0003c3ffff */
/*0850*/ BRA 0x850; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7calcSinPdm
.globl _Z7calcSinPdm
.p2align 8
.type _Z7calcSinPdm,@function
_Z7calcSinPdm:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_add_u32 s4, s0, 16
s_addc_u32 s5, s1, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[2:3]
s_cbranch_execz .LBB0_3
s_load_b32 s7, s[4:5], 0x0
s_load_b64 s[4:5], s[0:1], 0x0
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_mov_b32 s8, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s15, s15, s7
s_mul_i32 s1, s7, s6
v_mad_u64_u32 v[6:7], null, s15, s6, v[0:1]
s_mov_b32 s7, 0x400921fb
s_mov_b32 s6, 0x54442d18
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v6
.LBB0_2:
v_lshrrev_b32_e32 v0, 3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v0, 0x16c16c17
v_lshrrev_b32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v0, 0x168, v0
v_sub_nc_u32_e32 v0, v1, v0
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_u32_e32 v[6:7], v0
v_mul_f64 v[6:7], v[6:7], s[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[8:9], null, 0x40668000, 0x40668000, v[6:7]
v_div_scale_f64 v[14:15], vcc_lo, v[6:7], 0x40668000, v[6:7]
v_rcp_f64_e32 v[10:11], v[8:9]
s_waitcnt_depctr 0xfff
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
v_mul_f64 v[12:13], v[14:15], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[8:9], v[12:13], v[14:15]
v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[12:13]
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[2:3]
s_or_b32 s8, vcc_lo, s8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[6:7], v[8:9], 0x40668000, v[6:7]
v_lshlrev_b64 v[8:9], 3, v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
v_add_nc_u32_e32 v2, s1, v2
v_add_co_u32 v8, s0, s4, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s0, s5, v9, s0
v_cvt_f32_f64_e32 v0, v[6:7]
v_mul_f32_e32 v0, 0.15915494, v0
s_delay_alu instid0(VALU_DEP_1)
v_sin_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_cvt_f64_f32_e32 v[6:7], v0
global_store_b64 v[8:9], v[6:7], off
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7calcSinPdm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7calcSinPdm, .Lfunc_end0-_Z7calcSinPdm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7calcSinPdm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7calcSinPdm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00089b81_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7calcErrPdm
.type _Z7calcErrPdm, @function
_Z7calcErrPdm:
.LFB2070:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %rbp
testq %rsi, %rsi
je .L8
movq %rdi, %r12
movq $0x000000000, 8(%rsp)
movl $0, %ebx
.L5:
movslq %ebx, %rax
imulq $-1240768329, %rax, %rax
shrq $32, %rax
addl %ebx, %eax
sarl $8, %eax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
imull $360, %eax, %eax
movl %ebx, %edx
subl %eax, %edx
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
mulsd .LC1(%rip), %xmm0
divsd .LC2(%rip), %xmm0
call sin@PLT
subsd (%r12,%rbx,8), %xmm0
andpd .LC3(%rip), %xmm0
addsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
addq $1, %rbx
cmpq %rbp, %rbx
jne .L5
.L4:
testq %rbp, %rbp
js .L6
pxor %xmm1, %xmm1
cvtsi2sdq %rbp, %xmm1
.L7:
movsd 8(%rsp), %xmm0
divsd %xmm1, %xmm0
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
movq $0x000000000, 8(%rsp)
jmp .L4
.L6:
movq %rbp, %rax
shrq %rax
andl $1, %ebp
orq %rbp, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm1
jmp .L7
.cfi_endproc
.LFE2070:
.size _Z7calcErrPdm, .-_Z7calcErrPdm
.globl _Z27__device_stub__Z7calcSinPdmPdm
.type _Z27__device_stub__Z7calcSinPdmPdm, @function
_Z27__device_stub__Z7calcSinPdmPdm:
.LFB2096:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7calcSinPdm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z27__device_stub__Z7calcSinPdmPdm, .-_Z27__device_stub__Z7calcSinPdmPdm
.globl _Z7calcSinPdm
.type _Z7calcSinPdm, @function
_Z7calcSinPdm:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7calcSinPdmPdm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z7calcSinPdm, .-_Z7calcSinPdm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Error in cudaGetDeviceCount: %s\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "cudaGetDeviceCount = %x\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "Error in cudaGetDeviceProperties: %d\n"
.section .rodata.str1.1
.LC7:
.string "Device %d\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "Compute capability : %d.%d\n"
.section .rodata.str1.1
.LC9:
.string "Name : %s\n"
.LC10:
.string "Total Global Memory : %d\n"
.LC11:
.string "Shared memory per block: %d\n"
.LC12:
.string "Registers per block : %d\n"
.LC13:
.string "Warp size : %d\n"
.LC14:
.string "Max threads per block : %d\n"
.LC15:
.string "Total constant memory : %d\n"
.LC16:
.string "Max Grid Size : %d %d %d\n"
.LC17:
.string "Max Threads Dim : %d %d %d\n"
.LC18:
.string "sizeof size_t %d \n"
.LC19:
.string "sizeof type %d \n"
.LC20:
.string "allocating %u memory\n"
.LC21:
.string "%f "
.LC22:
.string "\nerror = %0.10f "
.LC23:
.string "\nfinished\n"
.text
.globl main
.type main, @function
main:
.LFB2071:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1096, %rsp
.cfi_def_cfa_offset 1136
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L28
movl 12(%rsp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rdi
movl $1, %esi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L29
movl $0, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 412(%rsp), %ecx
movl 408(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 336(%rsp), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 344(%rsp), %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 352(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 356(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 368(%rsp), %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 400(%rsp), %rdx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 392(%rsp), %r8d
movl 388(%rsp), %ecx
movl 384(%rsp), %edx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %r8d
movl 376(%rsp), %ecx
movl 372(%rsp), %edx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call cudaSetDevice@PLT
movl $8, %edx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $8, %edx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $800000000, %edx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rdi
movl $800000000, %esi
call cudaMalloc@PLT
movl 368(%rsp), %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl $128, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L23:
movl $800000000, %edi
call malloc@PLT
movq %rax, %r13
movl $2, %ecx
movl $800000000, %edx
movq 16(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movq %r13, %rbx
leaq 80(%r13), %r12
leaq .LC21(%rip), %rbp
.L24:
movsd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %r12, %rbx
jne .L24
movl $100000000, %esi
movq %r13, %rdi
call _Z7calcErrPdm
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L21:
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $1096, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L21
.L29:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L21
.L30:
movl $100000000, %esi
movq 16(%rsp), %rdi
call _Z27__device_stub__Z7calcSinPdmPdm
jmp .L23
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size main, .-main
.section .rodata.str1.1
.LC24:
.string "_Z7calcSinPdm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC24(%rip), %rdx
movq %rdx, %rcx
leaq _Z7calcSinPdm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 1413754136
.long 1074340347
.align 8
.LC2:
.long 0
.long 1080459264
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC3:
.long -1
.long 2147483647
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "main.hip"
.globl _Z22__device_stub__calcSinPdm # -- Begin function _Z22__device_stub__calcSinPdm
.p2align 4, 0x90
.type _Z22__device_stub__calcSinPdm,@function
_Z22__device_stub__calcSinPdm: # @_Z22__device_stub__calcSinPdm
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7calcSinPdm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__calcSinPdm, .Lfunc_end0-_Z22__device_stub__calcSinPdm
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7calcErrPdm
.LCPI1_0:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.LCPI1_1:
.quad 0x4066800000000000 # double 180
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_2:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.LCPI1_3:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI1_4:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.text
.globl _Z7calcErrPdm
.p2align 4, 0x90
.type _Z7calcErrPdm,@function
_Z7calcErrPdm: # @_Z7calcErrPdm
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
testq %rsi, %rsi
je .LBB1_1
# %bb.3: # %.lr.ph.preheader
movq %rdi, %r14
xorpd %xmm2, %xmm2
xorl %ebp, %ebp
movq %rbx, %r15
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd %xmm2, (%rsp) # 8-byte Spill
movl %ebp, %eax
shrl $3, %eax
imulq $381774871, %rax, %rax # imm = 0x16C16C17
shrq $34, %rax
imull $360, %eax, %eax # imm = 0x168
movl %ebp, %ecx
subl %eax, %ecx
xorps %xmm0, %xmm0
cvtsi2sd %ecx, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
divsd .LCPI1_1(%rip), %xmm0
callq sin
movsd (%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
subsd (%r14), %xmm0
andpd .LCPI1_2(%rip), %xmm0
addsd %xmm0, %xmm2
addq $8, %r14
incl %ebp
decq %r15
jne .LBB1_4
jmp .LBB1_2
.LBB1_1:
xorpd %xmm2, %xmm2
.LBB1_2: # %._crit_edge
movq %rbx, %xmm0
punpckldq .LCPI1_3(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd .LCPI1_4(%rip), %xmm0
movapd %xmm0, %xmm1
unpckhpd %xmm0, %xmm1 # xmm1 = xmm1[1],xmm0[1]
addsd %xmm0, %xmm1
divsd %xmm1, %xmm2
movapd %xmm2, %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z7calcErrPdm, .Lfunc_end1-_Z7calcErrPdm
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.LCPI2_1:
.quad 0x4066800000000000 # double 180
.LCPI2_3:
.quad 0x4197d78400000000 # double 1.0E+8
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI2_2:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1584, %rsp # imm = 0x630
.cfi_def_cfa_offset 1616
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
je .LBB2_3
# %bb.1:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
jmp .LBB2_2
.LBB2_3:
movl 12(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
leaq 112(%rsp), %rdi
movl $1, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
je .LBB2_5
# %bb.4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
.LBB2_2:
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_12:
xorl %eax, %eax
addq $1584, %rsp # imm = 0x630
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_5:
.cfi_def_cfa_offset 1616
movl $.L.str.3, %edi
xorl %esi, %esi
xorl %eax, %eax
callq printf
movl 472(%rsp), %esi
movl 476(%rsp), %edx
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
leaq 112(%rsp), %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movq 400(%rsp), %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq 408(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 416(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl 420(%rsp), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 432(%rsp), %esi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movq 464(%rsp), %rsi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl 448(%rsp), %esi
movl 452(%rsp), %edx
movl 456(%rsp), %ecx
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl 436(%rsp), %esi
movl 440(%rsp), %edx
movl 444(%rsp), %ecx
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movl $1, %edi
callq hipSetDevice
movl $.L.str.14, %edi
movl $8, %esi
xorl %eax, %eax
callq printf
movl $.L.str.15, %edi
movl $8, %esi
xorl %eax, %eax
callq printf
movl $.L.str.16, %edi
movl $800000000, %esi # imm = 0x2FAF0800
xorl %eax, %eax
callq printf
leaq 24(%rsp), %rdi
movl $800000000, %esi # imm = 0x2FAF0800
callq hipMalloc
movl 432(%rsp), %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $128, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 24(%rsp), %rax
movq %rax, 88(%rsp)
movq $100000000, 80(%rsp) # imm = 0x5F5E100
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7calcSinPdm, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7:
movl $800000000, %edi # imm = 0x2FAF0800
callq malloc
movq %rax, %rbx
movq 24(%rsp), %rsi
movl $800000000, %edx # imm = 0x2FAF0800
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_8: # =>This Inner Loop Header: Depth=1
movsd (%rbx,%r14,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.17, %edi
movb $1, %al
callq printf
incq %r14
cmpq $10, %r14
jne .LBB2_8
# %bb.9: # %.lr.ph.i.preheader
xorpd %xmm0, %xmm0
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_10: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movsd %xmm0, 16(%rsp) # 8-byte Spill
movl %r14d, %eax
shrl $3, %eax
imulq $381774871, %rax, %rax # imm = 0x16C16C17
shrq $34, %rax
imull $360, %eax, %eax # imm = 0x168
movl %r14d, %ecx
subl %eax, %ecx
xorps %xmm0, %xmm0
cvtsi2sd %ecx, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
divsd .LCPI2_1(%rip), %xmm0
callq sin
subsd (%rbx,%r15), %xmm0
andpd .LCPI2_2(%rip), %xmm0
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp) # 8-byte Spill
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addq $8, %r15
incl %r14d
cmpq $800000000, %r15 # imm = 0x2FAF0800
jne .LBB2_10
# %bb.11: # %_Z7calcErrPdm.exit
divsd .LCPI2_3(%rip), %xmm0
movl $.L.str.18, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movl $.Lstr, %edi
callq puts@PLT
jmp .LBB2_12
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7calcSinPdm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7calcSinPdm,@object # @_Z7calcSinPdm
.section .rodata,"a",@progbits
.globl _Z7calcSinPdm
.p2align 3, 0x0
_Z7calcSinPdm:
.quad _Z22__device_stub__calcSinPdm
.size _Z7calcSinPdm, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error in cudaGetDeviceCount: %s\n"
.size .L.str, 33
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipGetDeviceCount = %x\n"
.size .L.str.1, 24
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error in cudaGetDeviceProperties: %d\n"
.size .L.str.2, 38
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Device %d\n"
.size .L.str.3, 11
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Compute capability : %d.%d\n"
.size .L.str.4, 32
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Name : %s\n"
.size .L.str.5, 29
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Total Global Memory : %d\n"
.size .L.str.6, 29
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Shared memory per block: %d\n"
.size .L.str.7, 29
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Registers per block : %d\n"
.size .L.str.8, 29
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Warp size : %d\n"
.size .L.str.9, 29
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Max threads per block : %d\n"
.size .L.str.10, 29
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Total constant memory : %d\n"
.size .L.str.11, 29
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Max Grid Size : %d %d %d\n"
.size .L.str.12, 27
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Max Threads Dim : %d %d %d\n"
.size .L.str.13, 29
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "sizeof size_t %d \n"
.size .L.str.14, 19
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "sizeof type %d \n"
.size .L.str.15, 17
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "allocating %u memory\n"
.size .L.str.16, 22
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "%f "
.size .L.str.17, 4
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "\nerror = %0.10f "
.size .L.str.18, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7calcSinPdm"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nfinished"
.size .Lstr, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__calcSinPdm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7calcSinPdm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
void CPUFunction() {
printf("Hello world from the CPU.\n");
}
__global__ void GPUFunction(int myid) {
printf("Hello world from GPU %d.\n", myid);
}
int main() {
// function to run on the cpu
CPUFunction();
int deviceCount;
cudaGetDeviceCount(&deviceCount);
int device;
for (device=0; device < deviceCount; ++device) {
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, device);
printf("Device %d has compute capability %d.%d.\n",
device, deviceProp.major, deviceProp.minor);
}
// run on gpu 0
int device_id = 0;
cudaSetDevice(device_id);
GPUFunction<<<1, 1>>>(device_id);
// run on gpu 1
device_id = 1;
cudaSetDevice(device_id);
GPUFunction<<<1, 1>>>(device_id);
// kernel execution is asynchronous so sync on its completion
cudaDeviceSynchronize();
}
|
code for sm_80
Function : _Z11GPUFunctioni
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fca00078e00ff */
/*0010*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0020*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0050*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0070*/ STL [R1], R8 ; /* 0x0000000801007387 */
/* 0x0001e20000100800 */
/*0080*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0000640000000a00 */
/*0090*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fcc00000e06ff */
/*00a0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x001fe40000000000 */
/*00b0*/ MOV R11, 0x120 ; /* 0x00000120000b7802 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R20, 0xa0 ; /* 0x000000a000147802 */
/* 0x000fc40000000f00 */
/*00d0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*00f0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0100*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0110*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
void CPUFunction() {
printf("Hello world from the CPU.\n");
}
__global__ void GPUFunction(int myid) {
printf("Hello world from GPU %d.\n", myid);
}
int main() {
// function to run on the cpu
CPUFunction();
int deviceCount;
cudaGetDeviceCount(&deviceCount);
int device;
for (device=0; device < deviceCount; ++device) {
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, device);
printf("Device %d has compute capability %d.%d.\n",
device, deviceProp.major, deviceProp.minor);
}
// run on gpu 0
int device_id = 0;
cudaSetDevice(device_id);
GPUFunction<<<1, 1>>>(device_id);
// run on gpu 1
device_id = 1;
cudaSetDevice(device_id);
GPUFunction<<<1, 1>>>(device_id);
// kernel execution is asynchronous so sync on its completion
cudaDeviceSynchronize();
}
|
.file "tmpxft_00103255_00000000-6_multi_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello world from the CPU.\n"
.text
.globl _Z11CPUFunctionv
.type _Z11CPUFunctionv, @function
_Z11CPUFunctionv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11CPUFunctionv, .-_Z11CPUFunctionv
.globl _Z30__device_stub__Z11GPUFunctionii
.type _Z30__device_stub__Z11GPUFunctionii, @function
_Z30__device_stub__Z11GPUFunctionii:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11GPUFunctioni(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z30__device_stub__Z11GPUFunctionii, .-_Z30__device_stub__Z11GPUFunctionii
.globl _Z11GPUFunctioni
.type _Z11GPUFunctioni, @function
_Z11GPUFunctioni:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z11GPUFunctionii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z11GPUFunctioni, .-_Z11GPUFunctioni
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Device %d has compute capability %d.%d.\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1080, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1064(%rsp)
xorl %eax, %eax
call _Z11CPUFunctionv
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 4(%rsp)
jle .L14
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L15:
leaq 32(%rsp), %rdi
movl %ebx, %esi
call cudaGetDeviceProperties_v2@PLT
movl 396(%rsp), %r8d
movl 392(%rsp), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 4(%rsp)
jg .L15
.L14:
movl $0, %edi
call cudaSetDevice@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L16:
movl $1, %edi
call cudaSetDevice@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L17:
call cudaDeviceSynchronize@PLT
movq 1064(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $1080, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $0, %edi
call _Z30__device_stub__Z11GPUFunctionii
jmp .L16
.L22:
movl $1, %edi
call _Z30__device_stub__Z11GPUFunctionii
jmp .L17
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z11GPUFunctioni"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z11GPUFunctioni(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
void CPUFunction() {
printf("Hello world from the CPU.\n");
}
__global__ void GPUFunction(int myid) {
printf("Hello world from GPU %d.\n", myid);
}
int main() {
// function to run on the cpu
CPUFunction();
int deviceCount;
cudaGetDeviceCount(&deviceCount);
int device;
for (device=0; device < deviceCount; ++device) {
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, device);
printf("Device %d has compute capability %d.%d.\n",
device, deviceProp.major, deviceProp.minor);
}
// run on gpu 0
int device_id = 0;
cudaSetDevice(device_id);
GPUFunction<<<1, 1>>>(device_id);
// run on gpu 1
device_id = 1;
cudaSetDevice(device_id);
GPUFunction<<<1, 1>>>(device_id);
// kernel execution is asynchronous so sync on its completion
cudaDeviceSynchronize();
}
|
#include <hip/hip_runtime.h>
#include <stdio.h>
void CPUFunction() {
printf("Hello world from the CPU.\n");
}
__global__ void GPUFunction(int myid) {
printf("Hello world from GPU %d.\n", myid);
}
int main() {
// function to run on the cpu
CPUFunction();
int deviceCount;
hipGetDeviceCount(&deviceCount);
int device;
for (device=0; device < deviceCount; ++device) {
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, device);
printf("Device %d has compute capability %d.%d.\n",
device, deviceProp.major, deviceProp.minor);
}
// run on gpu 0
int device_id = 0;
hipSetDevice(device_id);
GPUFunction<<<1, 1>>>(device_id);
// run on gpu 1
device_id = 1;
hipSetDevice(device_id);
GPUFunction<<<1, 1>>>(device_id);
// kernel execution is asynchronous so sync on its completion
hipDeviceSynchronize();
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
void CPUFunction() {
printf("Hello world from the CPU.\n");
}
__global__ void GPUFunction(int myid) {
printf("Hello world from GPU %d.\n", myid);
}
int main() {
// function to run on the cpu
CPUFunction();
int deviceCount;
hipGetDeviceCount(&deviceCount);
int device;
for (device=0; device < deviceCount; ++device) {
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, device);
printf("Device %d has compute capability %d.%d.\n",
device, deviceProp.major, deviceProp.minor);
}
// run on gpu 0
int device_id = 0;
hipSetDevice(device_id);
GPUFunction<<<1, 1>>>(device_id);
// run on gpu 1
device_id = 1;
hipSetDevice(device_id);
GPUFunction<<<1, 1>>>(device_id);
// kernel execution is asynchronous so sync on its completion
hipDeviceSynchronize();
}
|
.text
.file "multi_gpu.hip"
.globl _Z11CPUFunctionv # -- Begin function _Z11CPUFunctionv
.p2align 4, 0x90
.type _Z11CPUFunctionv,@function
_Z11CPUFunctionv: # @_Z11CPUFunctionv
.cfi_startproc
# %bb.0:
movl $.Lstr, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end0:
.size _Z11CPUFunctionv, .Lfunc_end0-_Z11CPUFunctionv
.cfi_endproc
# -- End function
.globl _Z26__device_stub__GPUFunctioni # -- Begin function _Z26__device_stub__GPUFunctioni
.p2align 4, 0x90
.type _Z26__device_stub__GPUFunctioni,@function
_Z26__device_stub__GPUFunctioni: # @_Z26__device_stub__GPUFunctioni
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z11GPUFunctioni, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z26__device_stub__GPUFunctioni, .Lfunc_end1-_Z26__device_stub__GPUFunctioni
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1528, %rsp # imm = 0x5F8
.cfi_def_cfa_offset 1552
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl $.Lstr, %edi
callq puts@PLT
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 12(%rsp)
jle .LBB2_3
# %bb.1: # %.lr.ph
leaq 56(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl 416(%rsp), %edx
movl 420(%rsp), %ecx
movl $.L.str.1, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 12(%rsp), %ebp
jl .LBB2_2
.LBB2_3: # %._crit_edge
movabsq $4294967297, %rbx # imm = 0x100000001
xorl %edi, %edi
callq hipSetDevice
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movl $0, 8(%rsp)
leaq 8(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z11GPUFunctioni, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
movl $1, %edi
callq hipSetDevice
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movl $1, 8(%rsp)
leaq 8(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z11GPUFunctioni, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $1528, %rsp # imm = 0x5F8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11GPUFunctioni, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11GPUFunctioni,@object # @_Z11GPUFunctioni
.section .rodata,"a",@progbits
.globl _Z11GPUFunctioni
.p2align 3, 0x0
_Z11GPUFunctioni:
.quad _Z26__device_stub__GPUFunctioni
.size _Z11GPUFunctioni, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Device %d has compute capability %d.%d.\n"
.size .L.str.1, 41
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11GPUFunctioni"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello world from the CPU."
.size .Lstr, 26
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__GPUFunctioni
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11GPUFunctioni
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00103255_00000000-6_multi_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello world from the CPU.\n"
.text
.globl _Z11CPUFunctionv
.type _Z11CPUFunctionv, @function
_Z11CPUFunctionv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11CPUFunctionv, .-_Z11CPUFunctionv
.globl _Z30__device_stub__Z11GPUFunctionii
.type _Z30__device_stub__Z11GPUFunctionii, @function
_Z30__device_stub__Z11GPUFunctionii:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11GPUFunctioni(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z30__device_stub__Z11GPUFunctionii, .-_Z30__device_stub__Z11GPUFunctionii
.globl _Z11GPUFunctioni
.type _Z11GPUFunctioni, @function
_Z11GPUFunctioni:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z11GPUFunctionii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z11GPUFunctioni, .-_Z11GPUFunctioni
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Device %d has compute capability %d.%d.\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1080, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1064(%rsp)
xorl %eax, %eax
call _Z11CPUFunctionv
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 4(%rsp)
jle .L14
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L15:
leaq 32(%rsp), %rdi
movl %ebx, %esi
call cudaGetDeviceProperties_v2@PLT
movl 396(%rsp), %r8d
movl 392(%rsp), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 4(%rsp)
jg .L15
.L14:
movl $0, %edi
call cudaSetDevice@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L16:
movl $1, %edi
call cudaSetDevice@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L17:
call cudaDeviceSynchronize@PLT
movq 1064(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $1080, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $0, %edi
call _Z30__device_stub__Z11GPUFunctionii
jmp .L16
.L22:
movl $1, %edi
call _Z30__device_stub__Z11GPUFunctionii
jmp .L17
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z11GPUFunctioni"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z11GPUFunctioni(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "multi_gpu.hip"
.globl _Z11CPUFunctionv # -- Begin function _Z11CPUFunctionv
.p2align 4, 0x90
.type _Z11CPUFunctionv,@function
_Z11CPUFunctionv: # @_Z11CPUFunctionv
.cfi_startproc
# %bb.0:
movl $.Lstr, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end0:
.size _Z11CPUFunctionv, .Lfunc_end0-_Z11CPUFunctionv
.cfi_endproc
# -- End function
.globl _Z26__device_stub__GPUFunctioni # -- Begin function _Z26__device_stub__GPUFunctioni
.p2align 4, 0x90
.type _Z26__device_stub__GPUFunctioni,@function
_Z26__device_stub__GPUFunctioni: # @_Z26__device_stub__GPUFunctioni
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z11GPUFunctioni, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z26__device_stub__GPUFunctioni, .Lfunc_end1-_Z26__device_stub__GPUFunctioni
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1528, %rsp # imm = 0x5F8
.cfi_def_cfa_offset 1552
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl $.Lstr, %edi
callq puts@PLT
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 12(%rsp)
jle .LBB2_3
# %bb.1: # %.lr.ph
leaq 56(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl 416(%rsp), %edx
movl 420(%rsp), %ecx
movl $.L.str.1, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 12(%rsp), %ebp
jl .LBB2_2
.LBB2_3: # %._crit_edge
movabsq $4294967297, %rbx # imm = 0x100000001
xorl %edi, %edi
callq hipSetDevice
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movl $0, 8(%rsp)
leaq 8(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z11GPUFunctioni, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
movl $1, %edi
callq hipSetDevice
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movl $1, 8(%rsp)
leaq 8(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z11GPUFunctioni, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $1528, %rsp # imm = 0x5F8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11GPUFunctioni, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11GPUFunctioni,@object # @_Z11GPUFunctioni
.section .rodata,"a",@progbits
.globl _Z11GPUFunctioni
.p2align 3, 0x0
_Z11GPUFunctioni:
.quad _Z26__device_stub__GPUFunctioni
.size _Z11GPUFunctioni, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Device %d has compute capability %d.%d.\n"
.size .L.str.1, 41
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11GPUFunctioni"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello world from the CPU."
.size .Lstr, 26
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__GPUFunctioni
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11GPUFunctioni
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
//xfail:BOOGIE_ERROR
//--warp-sync=32 --blockDim=32 --gridDim=1 --equality-abstraction --no-inline
//kernel.cu:10
#include <cuda.h>
#include <cuda_runtime_api.h>
#include <stdio.h>
#include <assert.h>
#define N 2//32
__global__ void foo(int * A) {
A[0] = 1;
A[1] = 1;
A[threadIdx.x] = 0;
//__assert(A[0] == 1 | A[1] == 1 | A[2] == 1);
}
int main(){
int *b;
int *dev_b;
b = (int*)malloc(N*sizeof(int));
for (int i = 0; i < N; ++i){
b[i] = 2;
}
cudaMalloc((void**)&dev_b, N*sizeof(int));
cudaMemcpy(dev_b, b, N*sizeof(int), cudaMemcpyHostToDevice);
foo<<<1,N>>>(dev_b);
//ESBMC_verify_kernel(foo, 1, N, dev_b);
cudaMemcpy(b, dev_b, N*sizeof(int), cudaMemcpyDeviceToHost);
for (int i = 0; i < N; ++i){
assert(b[i] == 0 || b[i] == 1);
}
free(b);
cudaFree(dev_b);
}
|
code for sm_80
Function : _Z3fooPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0070*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*0080*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x000fe2000c101904 */
/*0090*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x001fca00078e0005 */
/*00a0*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
//xfail:BOOGIE_ERROR
//--warp-sync=32 --blockDim=32 --gridDim=1 --equality-abstraction --no-inline
//kernel.cu:10
#include <cuda.h>
#include <cuda_runtime_api.h>
#include <stdio.h>
#include <assert.h>
#define N 2//32
__global__ void foo(int * A) {
A[0] = 1;
A[1] = 1;
A[threadIdx.x] = 0;
//__assert(A[0] == 1 | A[1] == 1 | A[2] == 1);
}
int main(){
int *b;
int *dev_b;
b = (int*)malloc(N*sizeof(int));
for (int i = 0; i < N; ++i){
b[i] = 2;
}
cudaMalloc((void**)&dev_b, N*sizeof(int));
cudaMemcpy(dev_b, b, N*sizeof(int), cudaMemcpyHostToDevice);
foo<<<1,N>>>(dev_b);
//ESBMC_verify_kernel(foo, 1, N, dev_b);
cudaMemcpy(b, dev_b, N*sizeof(int), cudaMemcpyDeviceToHost);
for (int i = 0; i < N; ++i){
assert(b[i] == 0 || b[i] == 1);
}
free(b);
cudaFree(dev_b);
}
|
.file "tmpxft_001ba16b_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z3fooPiPi
.type _Z22__device_stub__Z3fooPiPi, @function
_Z22__device_stub__Z3fooPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3fooPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z22__device_stub__Z3fooPiPi, .-_Z22__device_stub__Z3fooPiPi
.globl _Z3fooPi
.type _Z3fooPi, @function
_Z3fooPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3fooPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3fooPi, .-_Z3fooPi
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $8, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, (%rax)
movl $2, 4(%rax)
leaq 8(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movl $8, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z22__device_stub__Z3fooPiPi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3fooPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3fooPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
//xfail:BOOGIE_ERROR
//--warp-sync=32 --blockDim=32 --gridDim=1 --equality-abstraction --no-inline
//kernel.cu:10
#include <cuda.h>
#include <cuda_runtime_api.h>
#include <stdio.h>
#include <assert.h>
#define N 2//32
__global__ void foo(int * A) {
A[0] = 1;
A[1] = 1;
A[threadIdx.x] = 0;
//__assert(A[0] == 1 | A[1] == 1 | A[2] == 1);
}
int main(){
int *b;
int *dev_b;
b = (int*)malloc(N*sizeof(int));
for (int i = 0; i < N; ++i){
b[i] = 2;
}
cudaMalloc((void**)&dev_b, N*sizeof(int));
cudaMemcpy(dev_b, b, N*sizeof(int), cudaMemcpyHostToDevice);
foo<<<1,N>>>(dev_b);
//ESBMC_verify_kernel(foo, 1, N, dev_b);
cudaMemcpy(b, dev_b, N*sizeof(int), cudaMemcpyDeviceToHost);
for (int i = 0; i < N; ++i){
assert(b[i] == 0 || b[i] == 1);
}
free(b);
cudaFree(dev_b);
}
|
//xfail:BOOGIE_ERROR
//--warp-sync=32 --blockDim=32 --gridDim=1 --equality-abstraction --no-inline
//kernel.cu:10
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
#include <assert.h>
#define N 2//32
__global__ void foo(int * A) {
A[0] = 1;
A[1] = 1;
A[threadIdx.x] = 0;
//__assert(A[0] == 1 | A[1] == 1 | A[2] == 1);
}
int main(){
int *b;
int *dev_b;
b = (int*)malloc(N*sizeof(int));
for (int i = 0; i < N; ++i){
b[i] = 2;
}
hipMalloc((void**)&dev_b, N*sizeof(int));
hipMemcpy(dev_b, b, N*sizeof(int), hipMemcpyHostToDevice);
foo<<<1,N>>>(dev_b);
//ESBMC_verify_kernel(foo, 1, N, dev_b);
hipMemcpy(b, dev_b, N*sizeof(int), hipMemcpyDeviceToHost);
for (int i = 0; i < N; ++i){
assert(b[i] == 0 || b[i] == 1);
}
free(b);
hipFree(dev_b);
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
//xfail:BOOGIE_ERROR
//--warp-sync=32 --blockDim=32 --gridDim=1 --equality-abstraction --no-inline
//kernel.cu:10
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
#include <assert.h>
#define N 2//32
__global__ void foo(int * A) {
A[0] = 1;
A[1] = 1;
A[threadIdx.x] = 0;
//__assert(A[0] == 1 | A[1] == 1 | A[2] == 1);
}
int main(){
int *b;
int *dev_b;
b = (int*)malloc(N*sizeof(int));
for (int i = 0; i < N; ++i){
b[i] = 2;
}
hipMalloc((void**)&dev_b, N*sizeof(int));
hipMemcpy(dev_b, b, N*sizeof(int), hipMemcpyHostToDevice);
foo<<<1,N>>>(dev_b);
//ESBMC_verify_kernel(foo, 1, N, dev_b);
hipMemcpy(b, dev_b, N*sizeof(int), hipMemcpyDeviceToHost);
for (int i = 0; i < N; ++i){
assert(b[i] == 0 || b[i] == 1);
}
free(b);
hipFree(dev_b);
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3fooPi
.globl _Z3fooPi
.p2align 8
.type _Z3fooPi,@function
_Z3fooPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v1, 1 :: v_dual_lshlrev_b32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_store_b64 v3, v[1:2], s[0:1]
global_store_b32 v0, v3, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3fooPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3fooPi, .Lfunc_end0-_Z3fooPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3fooPi
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z3fooPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
//xfail:BOOGIE_ERROR
//--warp-sync=32 --blockDim=32 --gridDim=1 --equality-abstraction --no-inline
//kernel.cu:10
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
#include <assert.h>
#define N 2//32
__global__ void foo(int * A) {
A[0] = 1;
A[1] = 1;
A[threadIdx.x] = 0;
//__assert(A[0] == 1 | A[1] == 1 | A[2] == 1);
}
int main(){
int *b;
int *dev_b;
b = (int*)malloc(N*sizeof(int));
for (int i = 0; i < N; ++i){
b[i] = 2;
}
hipMalloc((void**)&dev_b, N*sizeof(int));
hipMemcpy(dev_b, b, N*sizeof(int), hipMemcpyHostToDevice);
foo<<<1,N>>>(dev_b);
//ESBMC_verify_kernel(foo, 1, N, dev_b);
hipMemcpy(b, dev_b, N*sizeof(int), hipMemcpyDeviceToHost);
for (int i = 0; i < N; ++i){
assert(b[i] == 0 || b[i] == 1);
}
free(b);
hipFree(dev_b);
}
|
.text
.file "main.hip"
.globl _Z18__device_stub__fooPi # -- Begin function _Z18__device_stub__fooPi
.p2align 4, 0x90
.type _Z18__device_stub__fooPi,@function
_Z18__device_stub__fooPi: # @_Z18__device_stub__fooPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3fooPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z18__device_stub__fooPi, .Lfunc_end0-_Z18__device_stub__fooPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
movl $8, %edi
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $2, (%rbx,%rax,4)
incq %rax
cmpq $1, %rax
je .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $8, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3fooPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $8, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3fooPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3fooPi,@object # @_Z3fooPi
.section .rodata,"a",@progbits
.globl _Z3fooPi
.p2align 3, 0x0
_Z3fooPi:
.quad _Z18__device_stub__fooPi
.size _Z3fooPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3fooPi"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__fooPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3fooPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z3fooPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0070*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*0080*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x000fe2000c101904 */
/*0090*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x001fca00078e0005 */
/*00a0*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3fooPi
.globl _Z3fooPi
.p2align 8
.type _Z3fooPi,@function
_Z3fooPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v1, 1 :: v_dual_lshlrev_b32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_store_b64 v3, v[1:2], s[0:1]
global_store_b32 v0, v3, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3fooPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3fooPi, .Lfunc_end0-_Z3fooPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3fooPi
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z3fooPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001ba16b_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z3fooPiPi
.type _Z22__device_stub__Z3fooPiPi, @function
_Z22__device_stub__Z3fooPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3fooPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z22__device_stub__Z3fooPiPi, .-_Z22__device_stub__Z3fooPiPi
.globl _Z3fooPi
.type _Z3fooPi, @function
_Z3fooPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3fooPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3fooPi, .-_Z3fooPi
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $8, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, (%rax)
movl $2, 4(%rax)
leaq 8(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movl $8, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z22__device_stub__Z3fooPiPi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3fooPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3fooPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "main.hip"
.globl _Z18__device_stub__fooPi # -- Begin function _Z18__device_stub__fooPi
.p2align 4, 0x90
.type _Z18__device_stub__fooPi,@function
_Z18__device_stub__fooPi: # @_Z18__device_stub__fooPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3fooPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z18__device_stub__fooPi, .Lfunc_end0-_Z18__device_stub__fooPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
movl $8, %edi
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $2, (%rbx,%rax,4)
incq %rax
cmpq $1, %rax
je .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $8, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3fooPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $8, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3fooPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3fooPi,@object # @_Z3fooPi
.section .rodata,"a",@progbits
.globl _Z3fooPi
.p2align 3, 0x0
_Z3fooPi:
.quad _Z18__device_stub__fooPi
.size _Z3fooPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3fooPi"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__fooPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3fooPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <time.h>
#include <iostream>
#define TIMER_CREATE(t) \
cudaEvent_t t##_start, t##_end; \
cudaEventCreate(&t##_start); \
cudaEventCreate(&t##_end);
#define TIMER_START(t) \
cudaEventRecord(t##_start); \
cudaEventSynchronize(t##_start); \
#define TIMER_END(t) \
cudaEventRecord(t##_end); \
cudaEventSynchronize(t##_end); \
cudaEventElapsedTime(&t, t##_start, t##_end); \
cudaEventDestroy(t##_start); \
cudaEventDestroy(t##_end);
#define TILE_SIZE 16
#define BLOCK_SIZE_1D 256
#define NUM_BINS 256
#define CUDA_TIMING
#define DEBUG
#define WARP_SIZE 32
#define R 9
unsigned char *input_gpu;
unsigned char *output_gpu;
double CLOCK() {
struct timespec t;
clock_gettime(CLOCK_MONOTONIC, &t);
return (t.tv_sec * 1000)+(t.tv_nsec*1e-6);
}
/*******************************************************/
/* Cuda Error Function */
/*******************************************************/
inline cudaError_t checkCuda(cudaError_t result) {
#if defined(DEBUG) || defined(_DEBUG)
if (result != cudaSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", cudaGetErrorString(result));
exit(-1);
}
#endif
return result;
}
// Add GPU kernel and functions
// HERE!!!
__global__ void kernel(unsigned char *input, unsigned int *output_cdf,
//unsigned char *output,
unsigned int im_size, unsigned int *cdf_min){
/*
int x = blockIdx.x*TILE_SIZE+threadIdx.x;
int y = blockIdx.y*TILE_SIZE+threadIdx.y;
int location = y*TILE_SIZE*gridDim.x+x;
input[location] = round(float(output_cdf[input[location]] - *cdf_min)/float(im_size/4 - *cdf_min) * (NUM_BINS - 1));
*/
int location = blockIdx.x * blockDim.x+threadIdx.x;
input[location] = float(output_cdf[input[location]] - *cdf_min)/float(im_size/64 - *cdf_min) * (NUM_BINS - 1);
//printf("the final: %d .", int(output[location]));
}
__global__ void get_histogram(unsigned char *input,
unsigned int *output_histogram
//int offset
){
/*
int x = blockIdx.x*TILE_SIZE+threadIdx.x;
int y = blockIdx.y*TILE_SIZE+threadIdx.y;
//if(x % 4 == 0 && y % 4 == 0){
if(x & 1 && y & 1){
int location = offset + y*TILE_SIZE*gridDim.x+x;
atomicAdd(&(output_histogram[input[location]]), 1);
}*/
if( !(threadIdx.x & 63)){
int location = blockIdx.x * blockDim.x+threadIdx.x;
atomicAdd(&(output_histogram[input[location]]), 1);
}
//__syncthreads();
}
__global__ void get_cdf_prefixSum(unsigned int *histogram)
{
int tid = threadIdx.x;
//USE SHARED MEMORY - COMON WE ARE EXPERIENCED PROGRAMMERS
__shared__ int Cache[256];
Cache[tid] = histogram[tid];
__syncthreads();
int space = 1;
//BEGIN
for (int i = 0; i < 8; i++)
{
int temp = Cache[tid];
int neighbor = 0;
if ((tid - space) >= 0)
{
neighbor = Cache[tid - space];
}
__syncthreads(); //AFTER LOADING
if (tid < space)
{
//DO NOTHING
}
else
{
Cache[tid] = temp + neighbor;
}
space = space * 2;
__syncthreads();
}
//REWRITE RESULTS TO MAIN MEMORY
histogram[tid] = Cache[tid];
}
/*
__global__ void get_cdf_naive(unsigned int *output_histogram,
unsigned int *output_cdf,
int n)
{
unsigned int d_hist_idx = blockDim.x * blockIdx.x + threadIdx.x;
if (d_hist_idx >= n)
{
return;
}
unsigned int cdf_val = 0;
for (int i = 0; i <= d_hist_idx; ++i)
{
cdf_val = cdf_val + output_histogram[i];
}
output_cdf[d_hist_idx] = cdf_val;
}*/
__global__ void reductionMin(unsigned int *sdata, unsigned int *results, int n)
{
// extern __shared__ int sdata[];
unsigned int tx = threadIdx.x;
// block-wide reduction
for(unsigned int offset = blockDim.x>>1; offset > 0; offset >>= 1)
{
__syncthreads();
if(tx < offset)
{
if(sdata[tx + offset] < sdata[tx] || sdata[tx] == 0)
sdata[tx] = sdata[tx + offset];
}
}
// finally, thread 0 writes the result
if(threadIdx.x == 0)
{
// the result is per-block
*results = sdata[0];
}
}
__global__ void kernel_warmup(unsigned char *input,
unsigned char *output){
int x = blockIdx.x*TILE_SIZE+threadIdx.x;
int y = blockIdx.y*TILE_SIZE+threadIdx.y;
int location = y*TILE_SIZE*gridDim.x+x;
output[location] = x%255;
}
void histogram_gpu(unsigned char *data,
unsigned int height,
unsigned int width){
int gridXSize = 1 + (( width - 1) / TILE_SIZE);
int gridYSize = 1 + ((height - 1) / TILE_SIZE);
int gridSize_1D = 1 + (NUM_BINS - 1)/ BLOCK_SIZE_1D;
int gridSize1D_2D = 1 + (( width*height - 1) / BLOCK_SIZE_1D);
int XSize = gridXSize*TILE_SIZE;
int YSize = gridYSize*TILE_SIZE;
// Both are the same size (CPU/GPU).
int size = XSize*YSize;
// CPU
unsigned int *cdf_gpu = new unsigned int [NUM_BINS];
// Pinned
//unsigned char *data_pinned;
// GPU
unsigned int *output_histogram;
//unsigned int *output_cdf;
unsigned int *cdf_min;
// Pageable to Pinned memory
//cudaMallocHost((void**)&data_pinned, size*sizeof(unsigned char));
//memcpy(data_pinned, data, size*sizeof(unsigned char));
// Allocate arrays in GPU memory
checkCuda(cudaMalloc((void**)&input_gpu , size*sizeof(unsigned char)));
checkCuda(cudaMalloc((void**)&output_histogram , NUM_BINS*sizeof(unsigned int)));
//checkCuda(cudaMalloc((void**)&output_cdf , NUM_BINS*sizeof(unsigned int)));
checkCuda(cudaMalloc((void**)&cdf_min , sizeof(unsigned int)));
checkCuda(cudaMemset(output_histogram , 0 , NUM_BINS*sizeof(unsigned int)));
//checkCuda(cudaMemset(output_cdf , 0 , NUM_BINS*sizeof(unsigned int)));
checkCuda(cudaMemset(cdf_min, 0, sizeof(unsigned int)));
// Grid & Block Size
//dim3 dimGrid2D(gridXSize, gridYSize);
//dim3 dimBlock2D(TILE_SIZE, TILE_SIZE);
// create streams
/*
const int nStreams = 2;
const int streamSize = width*height/nStreams;
std:: cout << "stream size: " << streamSize<<std::endl;
const int streamBytes = streamSize * sizeof(unsigned char);
cudaStream_t stream[nStreams];
for (int i = 0; i < nStreams; ++i){
checkCuda(cudaStreamCreate(&stream[i]));
}
*/
// Copy data to GPU
checkCuda(cudaMemcpy(input_gpu,
data,
size*sizeof(unsigned char),
cudaMemcpyHostToDevice));
//checkCuda(cudaDeviceSynchronize());
// Execute algorithm
dim3 dimGrid1D(gridSize_1D);
dim3 dimBlock1D(BLOCK_SIZE_1D);
dim3 dimGrid1D_2D(gridSize1D_2D);
dim3 dimBlock1D_2D(BLOCK_SIZE_1D);
// Kernel Call
#if defined(CUDA_TIMING)
float Ktime;
TIMER_CREATE(Ktime);
TIMER_START(Ktime);
#endif
get_histogram<<<dimGrid1D_2D, dimBlock1D_2D>>>(input_gpu, output_histogram);
//get_cdf_naive<<<dimGrid1D, dimBlock1D>>>(output_histogram, output_cdf, NUM_BINS);
get_cdf_prefixSum<<<1, 256>>>(output_histogram);
reductionMin<<<1, 256>>>(output_histogram, cdf_min, 256);
//checkCuda(cudaPeekAtLastError());
//checkCuda(cudaDeviceSynchronize());
// Retrieve results from the GPU
/*
checkCuda(cudaMemcpy(cdf_gpu,
output_cdf,
NUM_BINS*sizeof(unsigned int),
cudaMemcpyDeviceToHost));
// Free resources and end the program
*/
/*
unsigned int cdf_min = INT_MAX;
for (int i = 0; i < NUM_BINS; i++){
if(cdf_gpu[i] != 0 && cdf_gpu[i] < cdf_min){
cdf_min = cdf_gpu[i];
}
}*/
// std::cout << "cdf min : " << cdf_min << std::endl;
kernel<<<dimGrid1D_2D, dimBlock1D_2D>>>(input_gpu, output_histogram, width*height, cdf_min);
checkCuda(cudaPeekAtLastError());
checkCuda(cudaDeviceSynchronize());
#if defined(CUDA_TIMING)
TIMER_END(Ktime);
printf("Kernel Execution Time: %f ms\n", Ktime);
#endif
checkCuda(cudaMemcpy(data,
input_gpu,
size*sizeof(unsigned char),
cudaMemcpyDeviceToHost));
//memcpy(data, data_pinned, size*sizeof(unsigned char));
//checkCuda(cudaFreeHost(data_pinned));
checkCuda(cudaFree(output_histogram));
checkCuda(cudaFree(cdf_min));
//checkCuda(cudaFree(output_cdf));
//checkCuda(cudaFree(output_gpu));
checkCuda(cudaFree(input_gpu));
/*
for(int i = 0; i < NUM_BINS; i++){
std::cout << "Value " << i << " : " << probability_gpu[i] << " " << cdf_gpu[i] << std::endl;
}*/
/*
for(int i = 0; i < NUM_BINS*NUM_PARTS; i++){
std::cout << "Value " << i << " : " << hist_local_gpu[i] << " " << std::endl;
} */
/*
for (long int i = 0; i < 4990464; i++){
std::cout << data[i] << " ";
}*/
}
void histogram_gpu_warmup(unsigned char *data,
unsigned int height,
unsigned int width){
int gridXSize = 1 + (( width - 1) / TILE_SIZE);
int gridYSize = 1 + ((height - 1) / TILE_SIZE);
int XSize = gridXSize*TILE_SIZE;
int YSize = gridYSize*TILE_SIZE;
// Both are the same size (CPU/GPU).
int size = XSize*YSize;
// Allocate arrays in GPU memory
checkCuda(cudaMalloc((void**)&input_gpu , size*sizeof(unsigned char)));
checkCuda(cudaMalloc((void**)&output_gpu , size*sizeof(unsigned char)));
checkCuda(cudaMemset(output_gpu , 0 , size*sizeof(unsigned char)));
// Copy data to GPU
checkCuda(cudaMemcpy(input_gpu,
data,
size*sizeof(char),
cudaMemcpyHostToDevice));
checkCuda(cudaDeviceSynchronize());
// Execute algorithm
dim3 dimGrid(gridXSize, gridYSize);
dim3 dimBlock(TILE_SIZE, TILE_SIZE);
kernel_warmup <<<dimGrid, dimBlock>>>(input_gpu,
output_gpu);
checkCuda(cudaDeviceSynchronize());
// Retrieve results from the GPU
checkCuda(cudaMemcpy(data,
output_gpu,
size*sizeof(unsigned char),
cudaMemcpyDeviceToHost));
// Free resources and end the program
checkCuda(cudaFree(output_gpu));
checkCuda(cudaFree(input_gpu));
}
|
.file "tmpxft_00064b58_00000000-6_heq.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5CLOCKv
.type _Z5CLOCKv, @function
_Z5CLOCKv:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rsi
movl $1, %edi
call clock_gettime@PLT
imulq $1000, (%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
mulsd .LC0(%rip), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z5CLOCKv, .-_Z5CLOCKv
.globl _Z31__device_stub__Z6kernelPhPjjS0_PhPjjS0_
.type _Z31__device_stub__Z6kernelPhPjjS0_PhPjjS0_, @function
_Z31__device_stub__Z6kernelPhPjjS0_PhPjjS0_:
.LFB3697:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPhPjjS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z31__device_stub__Z6kernelPhPjjS0_PhPjjS0_, .-_Z31__device_stub__Z6kernelPhPjjS0_PhPjjS0_
.globl _Z6kernelPhPjjS0_
.type _Z6kernelPhPjjS0_, @function
_Z6kernelPhPjjS0_:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6kernelPhPjjS0_PhPjjS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z6kernelPhPjjS0_, .-_Z6kernelPhPjjS0_
.globl _Z35__device_stub__Z13get_histogramPhPjPhPj
.type _Z35__device_stub__Z13get_histogramPhPjPhPj, @function
_Z35__device_stub__Z13get_histogramPhPjPhPj:
.LFB3699:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13get_histogramPhPj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z35__device_stub__Z13get_histogramPhPjPhPj, .-_Z35__device_stub__Z13get_histogramPhPjPhPj
.globl _Z13get_histogramPhPj
.type _Z13get_histogramPhPj, @function
_Z13get_histogramPhPj:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13get_histogramPhPjPhPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z13get_histogramPhPj, .-_Z13get_histogramPhPj
.globl _Z37__device_stub__Z17get_cdf_prefixSumPjPj
.type _Z37__device_stub__Z17get_cdf_prefixSumPjPj, @function
_Z37__device_stub__Z17get_cdf_prefixSumPjPj:
.LFB3701:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17get_cdf_prefixSumPj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _Z37__device_stub__Z17get_cdf_prefixSumPjPj, .-_Z37__device_stub__Z17get_cdf_prefixSumPjPj
.globl _Z17get_cdf_prefixSumPj
.type _Z17get_cdf_prefixSumPj, @function
_Z17get_cdf_prefixSumPj:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z17get_cdf_prefixSumPjPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _Z17get_cdf_prefixSumPj, .-_Z17get_cdf_prefixSumPj
.globl _Z35__device_stub__Z12reductionMinPjS_iPjS_i
.type _Z35__device_stub__Z12reductionMinPjS_iPjS_i, @function
_Z35__device_stub__Z12reductionMinPjS_iPjS_i:
.LFB3703:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12reductionMinPjS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3703:
.size _Z35__device_stub__Z12reductionMinPjS_iPjS_i, .-_Z35__device_stub__Z12reductionMinPjS_iPjS_i
.globl _Z12reductionMinPjS_i
.type _Z12reductionMinPjS_i, @function
_Z12reductionMinPjS_i:
.LFB3704:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12reductionMinPjS_iPjS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _Z12reductionMinPjS_i, .-_Z12reductionMinPjS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "CUDA Runtime Error: %s\n"
.LC2:
.string "Kernel Execution Time: %f ms\n"
.text
.globl _Z13histogram_gpuPhjj
.type _Z13histogram_gpuPhjj, @function
_Z13histogram_gpuPhjj:
.LFB3671:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $104, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %r12
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl %edx, %r13d
imull %esi, %r13d
leal -1(%r13), %ebp
shrl $8, %ebp
addl $1, %ebp
leal -1(%rdx), %ebx
shrl $4, %ebx
addl $1, %ebx
subl $1, %esi
shrl $4, %esi
addl $1, %esi
imull %esi, %ebx
sall $8, %ebx
movslq %ebx, %rbx
movq %rbx, %rsi
leaq input_gpu(%rip), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L58
leaq 8(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L59
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L60
movl $1024, %edx
movl $0, %esi
movq 8(%rsp), %rdi
call cudaMemset@PLT
testl %eax, %eax
jne .L61
movl $4, %edx
movl $0, %esi
movq 16(%rsp), %rdi
call cudaMemset@PLT
testl %eax, %eax
jne .L62
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq input_gpu(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L63
movl %ebp, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $256, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl 60(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movq 40(%rsp), %rdi
movl 48(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L64
.L46:
movl $256, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
.L47:
movl $256, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L66
.L48:
movl 60(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movq 40(%rsp), %rdi
movl 48(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L67
.L49:
call cudaPeekAtLastError@PLT
testl %eax, %eax
jne .L68
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L69
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 76(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
pxor %xmm0, %xmm0
cvtss2sd 76(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbx, %rdx
movq input_gpu(%rip), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L70
movq 8(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L71
movq 16(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L72
movq input_gpu(%rip), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L73
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L74
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L59:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L60:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L61:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L62:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L63:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L64:
movq 8(%rsp), %rsi
movq input_gpu(%rip), %rdi
call _Z35__device_stub__Z13get_histogramPhPjPhPj
jmp .L46
.L65:
movq 8(%rsp), %rdi
call _Z37__device_stub__Z17get_cdf_prefixSumPjPj
jmp .L47
.L66:
movl $256, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z12reductionMinPjS_iPjS_i
jmp .L48
.L67:
movq 16(%rsp), %rcx
movl %r13d, %edx
movq 8(%rsp), %rsi
movq input_gpu(%rip), %rdi
call _Z31__device_stub__Z6kernelPhPjjS0_PhPjjS0_
jmp .L49
.L68:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L69:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L70:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L71:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L72:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L73:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L74:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size _Z13histogram_gpuPhjj, .-_Z13histogram_gpuPhjj
.globl _Z35__device_stub__Z13kernel_warmupPhS_PhS_
.type _Z35__device_stub__Z13kernel_warmupPhS_PhS_, @function
_Z35__device_stub__Z13kernel_warmupPhS_PhS_:
.LFB3705:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L79
.L75:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L80
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L79:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13kernel_warmupPhS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L75
.L80:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3705:
.size _Z35__device_stub__Z13kernel_warmupPhS_PhS_, .-_Z35__device_stub__Z13kernel_warmupPhS_PhS_
.globl _Z13kernel_warmupPhS_
.type _Z13kernel_warmupPhS_, @function
_Z13kernel_warmupPhS_:
.LFB3706:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13kernel_warmupPhS_PhS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3706:
.size _Z13kernel_warmupPhS_, .-_Z13kernel_warmupPhS_
.globl _Z20histogram_gpu_warmupPhjj
.type _Z20histogram_gpu_warmupPhjj, @function
_Z20histogram_gpu_warmupPhjj:
.LFB3672:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
leal -1(%rdx), %r12d
shrl $4, %r12d
addl $1, %r12d
subl $1, %esi
shrl $4, %esi
leal 1(%rsi), %ebp
movl %r12d, %ebx
imull %ebp, %ebx
sall $8, %ebx
movslq %ebx, %rbx
movq %rbx, %rsi
leaq input_gpu(%rip), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L95
movq %rbx, %rsi
leaq output_gpu(%rip), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L96
movq %rbx, %rdx
movl $0, %esi
movq output_gpu(%rip), %rdi
call cudaMemset@PLT
testl %eax, %eax
jne .L97
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq input_gpu(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L98
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L99
movl %r12d, 8(%rsp)
movl %ebp, 12(%rsp)
movl $16, 20(%rsp)
movl $16, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L100
.L89:
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L101
movl $2, %ecx
movq %rbx, %rdx
movq output_gpu(%rip), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L102
movq output_gpu(%rip), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L103
movq input_gpu(%rip), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L104
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L95:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L96:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L97:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L98:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L99:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L100:
movq output_gpu(%rip), %rsi
movq input_gpu(%rip), %rdi
call _Z35__device_stub__Z13kernel_warmupPhS_PhS_
jmp .L89
.L101:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L102:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L103:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L104:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE3672:
.size _Z20histogram_gpu_warmupPhjj, .-_Z20histogram_gpu_warmupPhjj
.section .rodata.str1.1
.LC3:
.string "_Z13kernel_warmupPhS_"
.LC4:
.string "_Z12reductionMinPjS_i"
.LC5:
.string "_Z17get_cdf_prefixSumPj"
.LC6:
.string "_Z13get_histogramPhPj"
.LC7:
.string "_Z6kernelPhPjjS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3708:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kernel_warmupPhS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z12reductionMinPjS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z17get_cdf_prefixSumPj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z13get_histogramPhPj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPhPjjS0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3708:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl output_gpu
.bss
.align 8
.type output_gpu, @object
.size output_gpu, 8
output_gpu:
.zero 8
.globl input_gpu
.align 8
.type input_gpu, @object
.size input_gpu, 8
input_gpu:
.zero 8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <time.h>
#include <iostream>
#define TIMER_CREATE(t) \
cudaEvent_t t##_start, t##_end; \
cudaEventCreate(&t##_start); \
cudaEventCreate(&t##_end);
#define TIMER_START(t) \
cudaEventRecord(t##_start); \
cudaEventSynchronize(t##_start); \
#define TIMER_END(t) \
cudaEventRecord(t##_end); \
cudaEventSynchronize(t##_end); \
cudaEventElapsedTime(&t, t##_start, t##_end); \
cudaEventDestroy(t##_start); \
cudaEventDestroy(t##_end);
#define TILE_SIZE 16
#define BLOCK_SIZE_1D 256
#define NUM_BINS 256
#define CUDA_TIMING
#define DEBUG
#define WARP_SIZE 32
#define R 9
unsigned char *input_gpu;
unsigned char *output_gpu;
double CLOCK() {
struct timespec t;
clock_gettime(CLOCK_MONOTONIC, &t);
return (t.tv_sec * 1000)+(t.tv_nsec*1e-6);
}
/*******************************************************/
/* Cuda Error Function */
/*******************************************************/
inline cudaError_t checkCuda(cudaError_t result) {
#if defined(DEBUG) || defined(_DEBUG)
if (result != cudaSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", cudaGetErrorString(result));
exit(-1);
}
#endif
return result;
}
// Add GPU kernel and functions
// HERE!!!
__global__ void kernel(unsigned char *input, unsigned int *output_cdf,
//unsigned char *output,
unsigned int im_size, unsigned int *cdf_min){
/*
int x = blockIdx.x*TILE_SIZE+threadIdx.x;
int y = blockIdx.y*TILE_SIZE+threadIdx.y;
int location = y*TILE_SIZE*gridDim.x+x;
input[location] = round(float(output_cdf[input[location]] - *cdf_min)/float(im_size/4 - *cdf_min) * (NUM_BINS - 1));
*/
int location = blockIdx.x * blockDim.x+threadIdx.x;
input[location] = float(output_cdf[input[location]] - *cdf_min)/float(im_size/64 - *cdf_min) * (NUM_BINS - 1);
//printf("the final: %d .", int(output[location]));
}
__global__ void get_histogram(unsigned char *input,
unsigned int *output_histogram
//int offset
){
/*
int x = blockIdx.x*TILE_SIZE+threadIdx.x;
int y = blockIdx.y*TILE_SIZE+threadIdx.y;
//if(x % 4 == 0 && y % 4 == 0){
if(x & 1 && y & 1){
int location = offset + y*TILE_SIZE*gridDim.x+x;
atomicAdd(&(output_histogram[input[location]]), 1);
}*/
if( !(threadIdx.x & 63)){
int location = blockIdx.x * blockDim.x+threadIdx.x;
atomicAdd(&(output_histogram[input[location]]), 1);
}
//__syncthreads();
}
__global__ void get_cdf_prefixSum(unsigned int *histogram)
{
int tid = threadIdx.x;
//USE SHARED MEMORY - COMON WE ARE EXPERIENCED PROGRAMMERS
__shared__ int Cache[256];
Cache[tid] = histogram[tid];
__syncthreads();
int space = 1;
//BEGIN
for (int i = 0; i < 8; i++)
{
int temp = Cache[tid];
int neighbor = 0;
if ((tid - space) >= 0)
{
neighbor = Cache[tid - space];
}
__syncthreads(); //AFTER LOADING
if (tid < space)
{
//DO NOTHING
}
else
{
Cache[tid] = temp + neighbor;
}
space = space * 2;
__syncthreads();
}
//REWRITE RESULTS TO MAIN MEMORY
histogram[tid] = Cache[tid];
}
/*
__global__ void get_cdf_naive(unsigned int *output_histogram,
unsigned int *output_cdf,
int n)
{
unsigned int d_hist_idx = blockDim.x * blockIdx.x + threadIdx.x;
if (d_hist_idx >= n)
{
return;
}
unsigned int cdf_val = 0;
for (int i = 0; i <= d_hist_idx; ++i)
{
cdf_val = cdf_val + output_histogram[i];
}
output_cdf[d_hist_idx] = cdf_val;
}*/
__global__ void reductionMin(unsigned int *sdata, unsigned int *results, int n)
{
// extern __shared__ int sdata[];
unsigned int tx = threadIdx.x;
// block-wide reduction
for(unsigned int offset = blockDim.x>>1; offset > 0; offset >>= 1)
{
__syncthreads();
if(tx < offset)
{
if(sdata[tx + offset] < sdata[tx] || sdata[tx] == 0)
sdata[tx] = sdata[tx + offset];
}
}
// finally, thread 0 writes the result
if(threadIdx.x == 0)
{
// the result is per-block
*results = sdata[0];
}
}
__global__ void kernel_warmup(unsigned char *input,
unsigned char *output){
int x = blockIdx.x*TILE_SIZE+threadIdx.x;
int y = blockIdx.y*TILE_SIZE+threadIdx.y;
int location = y*TILE_SIZE*gridDim.x+x;
output[location] = x%255;
}
void histogram_gpu(unsigned char *data,
unsigned int height,
unsigned int width){
int gridXSize = 1 + (( width - 1) / TILE_SIZE);
int gridYSize = 1 + ((height - 1) / TILE_SIZE);
int gridSize_1D = 1 + (NUM_BINS - 1)/ BLOCK_SIZE_1D;
int gridSize1D_2D = 1 + (( width*height - 1) / BLOCK_SIZE_1D);
int XSize = gridXSize*TILE_SIZE;
int YSize = gridYSize*TILE_SIZE;
// Both are the same size (CPU/GPU).
int size = XSize*YSize;
// CPU
unsigned int *cdf_gpu = new unsigned int [NUM_BINS];
// Pinned
//unsigned char *data_pinned;
// GPU
unsigned int *output_histogram;
//unsigned int *output_cdf;
unsigned int *cdf_min;
// Pageable to Pinned memory
//cudaMallocHost((void**)&data_pinned, size*sizeof(unsigned char));
//memcpy(data_pinned, data, size*sizeof(unsigned char));
// Allocate arrays in GPU memory
checkCuda(cudaMalloc((void**)&input_gpu , size*sizeof(unsigned char)));
checkCuda(cudaMalloc((void**)&output_histogram , NUM_BINS*sizeof(unsigned int)));
//checkCuda(cudaMalloc((void**)&output_cdf , NUM_BINS*sizeof(unsigned int)));
checkCuda(cudaMalloc((void**)&cdf_min , sizeof(unsigned int)));
checkCuda(cudaMemset(output_histogram , 0 , NUM_BINS*sizeof(unsigned int)));
//checkCuda(cudaMemset(output_cdf , 0 , NUM_BINS*sizeof(unsigned int)));
checkCuda(cudaMemset(cdf_min, 0, sizeof(unsigned int)));
// Grid & Block Size
//dim3 dimGrid2D(gridXSize, gridYSize);
//dim3 dimBlock2D(TILE_SIZE, TILE_SIZE);
// create streams
/*
const int nStreams = 2;
const int streamSize = width*height/nStreams;
std:: cout << "stream size: " << streamSize<<std::endl;
const int streamBytes = streamSize * sizeof(unsigned char);
cudaStream_t stream[nStreams];
for (int i = 0; i < nStreams; ++i){
checkCuda(cudaStreamCreate(&stream[i]));
}
*/
// Copy data to GPU
checkCuda(cudaMemcpy(input_gpu,
data,
size*sizeof(unsigned char),
cudaMemcpyHostToDevice));
//checkCuda(cudaDeviceSynchronize());
// Execute algorithm
dim3 dimGrid1D(gridSize_1D);
dim3 dimBlock1D(BLOCK_SIZE_1D);
dim3 dimGrid1D_2D(gridSize1D_2D);
dim3 dimBlock1D_2D(BLOCK_SIZE_1D);
// Kernel Call
#if defined(CUDA_TIMING)
float Ktime;
TIMER_CREATE(Ktime);
TIMER_START(Ktime);
#endif
get_histogram<<<dimGrid1D_2D, dimBlock1D_2D>>>(input_gpu, output_histogram);
//get_cdf_naive<<<dimGrid1D, dimBlock1D>>>(output_histogram, output_cdf, NUM_BINS);
get_cdf_prefixSum<<<1, 256>>>(output_histogram);
reductionMin<<<1, 256>>>(output_histogram, cdf_min, 256);
//checkCuda(cudaPeekAtLastError());
//checkCuda(cudaDeviceSynchronize());
// Retrieve results from the GPU
/*
checkCuda(cudaMemcpy(cdf_gpu,
output_cdf,
NUM_BINS*sizeof(unsigned int),
cudaMemcpyDeviceToHost));
// Free resources and end the program
*/
/*
unsigned int cdf_min = INT_MAX;
for (int i = 0; i < NUM_BINS; i++){
if(cdf_gpu[i] != 0 && cdf_gpu[i] < cdf_min){
cdf_min = cdf_gpu[i];
}
}*/
// std::cout << "cdf min : " << cdf_min << std::endl;
kernel<<<dimGrid1D_2D, dimBlock1D_2D>>>(input_gpu, output_histogram, width*height, cdf_min);
checkCuda(cudaPeekAtLastError());
checkCuda(cudaDeviceSynchronize());
#if defined(CUDA_TIMING)
TIMER_END(Ktime);
printf("Kernel Execution Time: %f ms\n", Ktime);
#endif
checkCuda(cudaMemcpy(data,
input_gpu,
size*sizeof(unsigned char),
cudaMemcpyDeviceToHost));
//memcpy(data, data_pinned, size*sizeof(unsigned char));
//checkCuda(cudaFreeHost(data_pinned));
checkCuda(cudaFree(output_histogram));
checkCuda(cudaFree(cdf_min));
//checkCuda(cudaFree(output_cdf));
//checkCuda(cudaFree(output_gpu));
checkCuda(cudaFree(input_gpu));
/*
for(int i = 0; i < NUM_BINS; i++){
std::cout << "Value " << i << " : " << probability_gpu[i] << " " << cdf_gpu[i] << std::endl;
}*/
/*
for(int i = 0; i < NUM_BINS*NUM_PARTS; i++){
std::cout << "Value " << i << " : " << hist_local_gpu[i] << " " << std::endl;
} */
/*
for (long int i = 0; i < 4990464; i++){
std::cout << data[i] << " ";
}*/
}
void histogram_gpu_warmup(unsigned char *data,
unsigned int height,
unsigned int width){
int gridXSize = 1 + (( width - 1) / TILE_SIZE);
int gridYSize = 1 + ((height - 1) / TILE_SIZE);
int XSize = gridXSize*TILE_SIZE;
int YSize = gridYSize*TILE_SIZE;
// Both are the same size (CPU/GPU).
int size = XSize*YSize;
// Allocate arrays in GPU memory
checkCuda(cudaMalloc((void**)&input_gpu , size*sizeof(unsigned char)));
checkCuda(cudaMalloc((void**)&output_gpu , size*sizeof(unsigned char)));
checkCuda(cudaMemset(output_gpu , 0 , size*sizeof(unsigned char)));
// Copy data to GPU
checkCuda(cudaMemcpy(input_gpu,
data,
size*sizeof(char),
cudaMemcpyHostToDevice));
checkCuda(cudaDeviceSynchronize());
// Execute algorithm
dim3 dimGrid(gridXSize, gridYSize);
dim3 dimBlock(TILE_SIZE, TILE_SIZE);
kernel_warmup <<<dimGrid, dimBlock>>>(input_gpu,
output_gpu);
checkCuda(cudaDeviceSynchronize());
// Retrieve results from the GPU
checkCuda(cudaMemcpy(data,
output_gpu,
size*sizeof(unsigned char),
cudaMemcpyDeviceToHost));
// Free resources and end the program
checkCuda(cudaFree(output_gpu));
checkCuda(cudaFree(input_gpu));
}
|
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <time.h>
#include <iostream>
#define TIMER_CREATE(t) \
hipEvent_t t##_start, t##_end; \
hipEventCreate(&t##_start); \
hipEventCreate(&t##_end);
#define TIMER_START(t) \
hipEventRecord(t##_start); \
hipEventSynchronize(t##_start); \
#define TIMER_END(t) \
hipEventRecord(t##_end); \
hipEventSynchronize(t##_end); \
hipEventElapsedTime(&t, t##_start, t##_end); \
hipEventDestroy(t##_start); \
hipEventDestroy(t##_end);
#define TILE_SIZE 16
#define BLOCK_SIZE_1D 256
#define NUM_BINS 256
#define CUDA_TIMING
#define DEBUG
#define WARP_SIZE 32
#define R 9
unsigned char *input_gpu;
unsigned char *output_gpu;
double CLOCK() {
struct timespec t;
clock_gettime(CLOCK_MONOTONIC, &t);
return (t.tv_sec * 1000)+(t.tv_nsec*1e-6);
}
/*******************************************************/
/* Cuda Error Function */
/*******************************************************/
inline hipError_t checkCuda(hipError_t result) {
#if defined(DEBUG) || defined(_DEBUG)
if (result != hipSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", hipGetErrorString(result));
exit(-1);
}
#endif
return result;
}
// Add GPU kernel and functions
// HERE!!!
__global__ void kernel(unsigned char *input, unsigned int *output_cdf,
//unsigned char *output,
unsigned int im_size, unsigned int *cdf_min){
/*
int x = blockIdx.x*TILE_SIZE+threadIdx.x;
int y = blockIdx.y*TILE_SIZE+threadIdx.y;
int location = y*TILE_SIZE*gridDim.x+x;
input[location] = round(float(output_cdf[input[location]] - *cdf_min)/float(im_size/4 - *cdf_min) * (NUM_BINS - 1));
*/
int location = blockIdx.x * blockDim.x+threadIdx.x;
input[location] = float(output_cdf[input[location]] - *cdf_min)/float(im_size/64 - *cdf_min) * (NUM_BINS - 1);
//printf("the final: %d .", int(output[location]));
}
__global__ void get_histogram(unsigned char *input,
unsigned int *output_histogram
//int offset
){
/*
int x = blockIdx.x*TILE_SIZE+threadIdx.x;
int y = blockIdx.y*TILE_SIZE+threadIdx.y;
//if(x % 4 == 0 && y % 4 == 0){
if(x & 1 && y & 1){
int location = offset + y*TILE_SIZE*gridDim.x+x;
atomicAdd(&(output_histogram[input[location]]), 1);
}*/
if( !(threadIdx.x & 63)){
int location = blockIdx.x * blockDim.x+threadIdx.x;
atomicAdd(&(output_histogram[input[location]]), 1);
}
//__syncthreads();
}
__global__ void get_cdf_prefixSum(unsigned int *histogram)
{
int tid = threadIdx.x;
//USE SHARED MEMORY - COMON WE ARE EXPERIENCED PROGRAMMERS
__shared__ int Cache[256];
Cache[tid] = histogram[tid];
__syncthreads();
int space = 1;
//BEGIN
for (int i = 0; i < 8; i++)
{
int temp = Cache[tid];
int neighbor = 0;
if ((tid - space) >= 0)
{
neighbor = Cache[tid - space];
}
__syncthreads(); //AFTER LOADING
if (tid < space)
{
//DO NOTHING
}
else
{
Cache[tid] = temp + neighbor;
}
space = space * 2;
__syncthreads();
}
//REWRITE RESULTS TO MAIN MEMORY
histogram[tid] = Cache[tid];
}
/*
__global__ void get_cdf_naive(unsigned int *output_histogram,
unsigned int *output_cdf,
int n)
{
unsigned int d_hist_idx = blockDim.x * blockIdx.x + threadIdx.x;
if (d_hist_idx >= n)
{
return;
}
unsigned int cdf_val = 0;
for (int i = 0; i <= d_hist_idx; ++i)
{
cdf_val = cdf_val + output_histogram[i];
}
output_cdf[d_hist_idx] = cdf_val;
}*/
__global__ void reductionMin(unsigned int *sdata, unsigned int *results, int n)
{
// extern __shared__ int sdata[];
unsigned int tx = threadIdx.x;
// block-wide reduction
for(unsigned int offset = blockDim.x>>1; offset > 0; offset >>= 1)
{
__syncthreads();
if(tx < offset)
{
if(sdata[tx + offset] < sdata[tx] || sdata[tx] == 0)
sdata[tx] = sdata[tx + offset];
}
}
// finally, thread 0 writes the result
if(threadIdx.x == 0)
{
// the result is per-block
*results = sdata[0];
}
}
__global__ void kernel_warmup(unsigned char *input,
unsigned char *output){
int x = blockIdx.x*TILE_SIZE+threadIdx.x;
int y = blockIdx.y*TILE_SIZE+threadIdx.y;
int location = y*TILE_SIZE*gridDim.x+x;
output[location] = x%255;
}
void histogram_gpu(unsigned char *data,
unsigned int height,
unsigned int width){
int gridXSize = 1 + (( width - 1) / TILE_SIZE);
int gridYSize = 1 + ((height - 1) / TILE_SIZE);
int gridSize_1D = 1 + (NUM_BINS - 1)/ BLOCK_SIZE_1D;
int gridSize1D_2D = 1 + (( width*height - 1) / BLOCK_SIZE_1D);
int XSize = gridXSize*TILE_SIZE;
int YSize = gridYSize*TILE_SIZE;
// Both are the same size (CPU/GPU).
int size = XSize*YSize;
// CPU
unsigned int *cdf_gpu = new unsigned int [NUM_BINS];
// Pinned
//unsigned char *data_pinned;
// GPU
unsigned int *output_histogram;
//unsigned int *output_cdf;
unsigned int *cdf_min;
// Pageable to Pinned memory
//cudaMallocHost((void**)&data_pinned, size*sizeof(unsigned char));
//memcpy(data_pinned, data, size*sizeof(unsigned char));
// Allocate arrays in GPU memory
checkCuda(hipMalloc((void**)&input_gpu , size*sizeof(unsigned char)));
checkCuda(hipMalloc((void**)&output_histogram , NUM_BINS*sizeof(unsigned int)));
//checkCuda(cudaMalloc((void**)&output_cdf , NUM_BINS*sizeof(unsigned int)));
checkCuda(hipMalloc((void**)&cdf_min , sizeof(unsigned int)));
checkCuda(hipMemset(output_histogram , 0 , NUM_BINS*sizeof(unsigned int)));
//checkCuda(cudaMemset(output_cdf , 0 , NUM_BINS*sizeof(unsigned int)));
checkCuda(hipMemset(cdf_min, 0, sizeof(unsigned int)));
// Grid & Block Size
//dim3 dimGrid2D(gridXSize, gridYSize);
//dim3 dimBlock2D(TILE_SIZE, TILE_SIZE);
// create streams
/*
const int nStreams = 2;
const int streamSize = width*height/nStreams;
std:: cout << "stream size: " << streamSize<<std::endl;
const int streamBytes = streamSize * sizeof(unsigned char);
cudaStream_t stream[nStreams];
for (int i = 0; i < nStreams; ++i){
checkCuda(cudaStreamCreate(&stream[i]));
}
*/
// Copy data to GPU
checkCuda(hipMemcpy(input_gpu,
data,
size*sizeof(unsigned char),
hipMemcpyHostToDevice));
//checkCuda(cudaDeviceSynchronize());
// Execute algorithm
dim3 dimGrid1D(gridSize_1D);
dim3 dimBlock1D(BLOCK_SIZE_1D);
dim3 dimGrid1D_2D(gridSize1D_2D);
dim3 dimBlock1D_2D(BLOCK_SIZE_1D);
// Kernel Call
#if defined(CUDA_TIMING)
float Ktime;
TIMER_CREATE(Ktime);
TIMER_START(Ktime);
#endif
get_histogram<<<dimGrid1D_2D, dimBlock1D_2D>>>(input_gpu, output_histogram);
//get_cdf_naive<<<dimGrid1D, dimBlock1D>>>(output_histogram, output_cdf, NUM_BINS);
get_cdf_prefixSum<<<1, 256>>>(output_histogram);
reductionMin<<<1, 256>>>(output_histogram, cdf_min, 256);
//checkCuda(cudaPeekAtLastError());
//checkCuda(cudaDeviceSynchronize());
// Retrieve results from the GPU
/*
checkCuda(cudaMemcpy(cdf_gpu,
output_cdf,
NUM_BINS*sizeof(unsigned int),
cudaMemcpyDeviceToHost));
// Free resources and end the program
*/
/*
unsigned int cdf_min = INT_MAX;
for (int i = 0; i < NUM_BINS; i++){
if(cdf_gpu[i] != 0 && cdf_gpu[i] < cdf_min){
cdf_min = cdf_gpu[i];
}
}*/
// std::cout << "cdf min : " << cdf_min << std::endl;
kernel<<<dimGrid1D_2D, dimBlock1D_2D>>>(input_gpu, output_histogram, width*height, cdf_min);
checkCuda(hipPeekAtLastError());
checkCuda(hipDeviceSynchronize());
#if defined(CUDA_TIMING)
TIMER_END(Ktime);
printf("Kernel Execution Time: %f ms\n", Ktime);
#endif
checkCuda(hipMemcpy(data,
input_gpu,
size*sizeof(unsigned char),
hipMemcpyDeviceToHost));
//memcpy(data, data_pinned, size*sizeof(unsigned char));
//checkCuda(cudaFreeHost(data_pinned));
checkCuda(hipFree(output_histogram));
checkCuda(hipFree(cdf_min));
//checkCuda(cudaFree(output_cdf));
//checkCuda(cudaFree(output_gpu));
checkCuda(hipFree(input_gpu));
/*
for(int i = 0; i < NUM_BINS; i++){
std::cout << "Value " << i << " : " << probability_gpu[i] << " " << cdf_gpu[i] << std::endl;
}*/
/*
for(int i = 0; i < NUM_BINS*NUM_PARTS; i++){
std::cout << "Value " << i << " : " << hist_local_gpu[i] << " " << std::endl;
} */
/*
for (long int i = 0; i < 4990464; i++){
std::cout << data[i] << " ";
}*/
}
void histogram_gpu_warmup(unsigned char *data,
unsigned int height,
unsigned int width){
int gridXSize = 1 + (( width - 1) / TILE_SIZE);
int gridYSize = 1 + ((height - 1) / TILE_SIZE);
int XSize = gridXSize*TILE_SIZE;
int YSize = gridYSize*TILE_SIZE;
// Both are the same size (CPU/GPU).
int size = XSize*YSize;
// Allocate arrays in GPU memory
checkCuda(hipMalloc((void**)&input_gpu , size*sizeof(unsigned char)));
checkCuda(hipMalloc((void**)&output_gpu , size*sizeof(unsigned char)));
checkCuda(hipMemset(output_gpu , 0 , size*sizeof(unsigned char)));
// Copy data to GPU
checkCuda(hipMemcpy(input_gpu,
data,
size*sizeof(char),
hipMemcpyHostToDevice));
checkCuda(hipDeviceSynchronize());
// Execute algorithm
dim3 dimGrid(gridXSize, gridYSize);
dim3 dimBlock(TILE_SIZE, TILE_SIZE);
kernel_warmup <<<dimGrid, dimBlock>>>(input_gpu,
output_gpu);
checkCuda(hipDeviceSynchronize());
// Retrieve results from the GPU
checkCuda(hipMemcpy(data,
output_gpu,
size*sizeof(unsigned char),
hipMemcpyDeviceToHost));
// Free resources and end the program
checkCuda(hipFree(output_gpu));
checkCuda(hipFree(input_gpu));
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <time.h>
#include <iostream>
#define TIMER_CREATE(t) \
hipEvent_t t##_start, t##_end; \
hipEventCreate(&t##_start); \
hipEventCreate(&t##_end);
#define TIMER_START(t) \
hipEventRecord(t##_start); \
hipEventSynchronize(t##_start); \
#define TIMER_END(t) \
hipEventRecord(t##_end); \
hipEventSynchronize(t##_end); \
hipEventElapsedTime(&t, t##_start, t##_end); \
hipEventDestroy(t##_start); \
hipEventDestroy(t##_end);
#define TILE_SIZE 16
#define BLOCK_SIZE_1D 256
#define NUM_BINS 256
#define CUDA_TIMING
#define DEBUG
#define WARP_SIZE 32
#define R 9
unsigned char *input_gpu;
unsigned char *output_gpu;
double CLOCK() {
struct timespec t;
clock_gettime(CLOCK_MONOTONIC, &t);
return (t.tv_sec * 1000)+(t.tv_nsec*1e-6);
}
/*******************************************************/
/* Cuda Error Function */
/*******************************************************/
inline hipError_t checkCuda(hipError_t result) {
#if defined(DEBUG) || defined(_DEBUG)
if (result != hipSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", hipGetErrorString(result));
exit(-1);
}
#endif
return result;
}
// Add GPU kernel and functions
// HERE!!!
__global__ void kernel(unsigned char *input, unsigned int *output_cdf,
//unsigned char *output,
unsigned int im_size, unsigned int *cdf_min){
/*
int x = blockIdx.x*TILE_SIZE+threadIdx.x;
int y = blockIdx.y*TILE_SIZE+threadIdx.y;
int location = y*TILE_SIZE*gridDim.x+x;
input[location] = round(float(output_cdf[input[location]] - *cdf_min)/float(im_size/4 - *cdf_min) * (NUM_BINS - 1));
*/
int location = blockIdx.x * blockDim.x+threadIdx.x;
input[location] = float(output_cdf[input[location]] - *cdf_min)/float(im_size/64 - *cdf_min) * (NUM_BINS - 1);
//printf("the final: %d .", int(output[location]));
}
__global__ void get_histogram(unsigned char *input,
unsigned int *output_histogram
//int offset
){
/*
int x = blockIdx.x*TILE_SIZE+threadIdx.x;
int y = blockIdx.y*TILE_SIZE+threadIdx.y;
//if(x % 4 == 0 && y % 4 == 0){
if(x & 1 && y & 1){
int location = offset + y*TILE_SIZE*gridDim.x+x;
atomicAdd(&(output_histogram[input[location]]), 1);
}*/
if( !(threadIdx.x & 63)){
int location = blockIdx.x * blockDim.x+threadIdx.x;
atomicAdd(&(output_histogram[input[location]]), 1);
}
//__syncthreads();
}
__global__ void get_cdf_prefixSum(unsigned int *histogram)
{
int tid = threadIdx.x;
//USE SHARED MEMORY - COMON WE ARE EXPERIENCED PROGRAMMERS
__shared__ int Cache[256];
Cache[tid] = histogram[tid];
__syncthreads();
int space = 1;
//BEGIN
for (int i = 0; i < 8; i++)
{
int temp = Cache[tid];
int neighbor = 0;
if ((tid - space) >= 0)
{
neighbor = Cache[tid - space];
}
__syncthreads(); //AFTER LOADING
if (tid < space)
{
//DO NOTHING
}
else
{
Cache[tid] = temp + neighbor;
}
space = space * 2;
__syncthreads();
}
//REWRITE RESULTS TO MAIN MEMORY
histogram[tid] = Cache[tid];
}
/*
__global__ void get_cdf_naive(unsigned int *output_histogram,
unsigned int *output_cdf,
int n)
{
unsigned int d_hist_idx = blockDim.x * blockIdx.x + threadIdx.x;
if (d_hist_idx >= n)
{
return;
}
unsigned int cdf_val = 0;
for (int i = 0; i <= d_hist_idx; ++i)
{
cdf_val = cdf_val + output_histogram[i];
}
output_cdf[d_hist_idx] = cdf_val;
}*/
__global__ void reductionMin(unsigned int *sdata, unsigned int *results, int n)
{
// extern __shared__ int sdata[];
unsigned int tx = threadIdx.x;
// block-wide reduction
for(unsigned int offset = blockDim.x>>1; offset > 0; offset >>= 1)
{
__syncthreads();
if(tx < offset)
{
if(sdata[tx + offset] < sdata[tx] || sdata[tx] == 0)
sdata[tx] = sdata[tx + offset];
}
}
// finally, thread 0 writes the result
if(threadIdx.x == 0)
{
// the result is per-block
*results = sdata[0];
}
}
__global__ void kernel_warmup(unsigned char *input,
unsigned char *output){
int x = blockIdx.x*TILE_SIZE+threadIdx.x;
int y = blockIdx.y*TILE_SIZE+threadIdx.y;
int location = y*TILE_SIZE*gridDim.x+x;
output[location] = x%255;
}
void histogram_gpu(unsigned char *data,
unsigned int height,
unsigned int width){
int gridXSize = 1 + (( width - 1) / TILE_SIZE);
int gridYSize = 1 + ((height - 1) / TILE_SIZE);
int gridSize_1D = 1 + (NUM_BINS - 1)/ BLOCK_SIZE_1D;
int gridSize1D_2D = 1 + (( width*height - 1) / BLOCK_SIZE_1D);
int XSize = gridXSize*TILE_SIZE;
int YSize = gridYSize*TILE_SIZE;
// Both are the same size (CPU/GPU).
int size = XSize*YSize;
// CPU
unsigned int *cdf_gpu = new unsigned int [NUM_BINS];
// Pinned
//unsigned char *data_pinned;
// GPU
unsigned int *output_histogram;
//unsigned int *output_cdf;
unsigned int *cdf_min;
// Pageable to Pinned memory
//cudaMallocHost((void**)&data_pinned, size*sizeof(unsigned char));
//memcpy(data_pinned, data, size*sizeof(unsigned char));
// Allocate arrays in GPU memory
checkCuda(hipMalloc((void**)&input_gpu , size*sizeof(unsigned char)));
checkCuda(hipMalloc((void**)&output_histogram , NUM_BINS*sizeof(unsigned int)));
//checkCuda(cudaMalloc((void**)&output_cdf , NUM_BINS*sizeof(unsigned int)));
checkCuda(hipMalloc((void**)&cdf_min , sizeof(unsigned int)));
checkCuda(hipMemset(output_histogram , 0 , NUM_BINS*sizeof(unsigned int)));
//checkCuda(cudaMemset(output_cdf , 0 , NUM_BINS*sizeof(unsigned int)));
checkCuda(hipMemset(cdf_min, 0, sizeof(unsigned int)));
// Grid & Block Size
//dim3 dimGrid2D(gridXSize, gridYSize);
//dim3 dimBlock2D(TILE_SIZE, TILE_SIZE);
// create streams
/*
const int nStreams = 2;
const int streamSize = width*height/nStreams;
std:: cout << "stream size: " << streamSize<<std::endl;
const int streamBytes = streamSize * sizeof(unsigned char);
cudaStream_t stream[nStreams];
for (int i = 0; i < nStreams; ++i){
checkCuda(cudaStreamCreate(&stream[i]));
}
*/
// Copy data to GPU
checkCuda(hipMemcpy(input_gpu,
data,
size*sizeof(unsigned char),
hipMemcpyHostToDevice));
//checkCuda(cudaDeviceSynchronize());
// Execute algorithm
dim3 dimGrid1D(gridSize_1D);
dim3 dimBlock1D(BLOCK_SIZE_1D);
dim3 dimGrid1D_2D(gridSize1D_2D);
dim3 dimBlock1D_2D(BLOCK_SIZE_1D);
// Kernel Call
#if defined(CUDA_TIMING)
float Ktime;
TIMER_CREATE(Ktime);
TIMER_START(Ktime);
#endif
get_histogram<<<dimGrid1D_2D, dimBlock1D_2D>>>(input_gpu, output_histogram);
//get_cdf_naive<<<dimGrid1D, dimBlock1D>>>(output_histogram, output_cdf, NUM_BINS);
get_cdf_prefixSum<<<1, 256>>>(output_histogram);
reductionMin<<<1, 256>>>(output_histogram, cdf_min, 256);
//checkCuda(cudaPeekAtLastError());
//checkCuda(cudaDeviceSynchronize());
// Retrieve results from the GPU
/*
checkCuda(cudaMemcpy(cdf_gpu,
output_cdf,
NUM_BINS*sizeof(unsigned int),
cudaMemcpyDeviceToHost));
// Free resources and end the program
*/
/*
unsigned int cdf_min = INT_MAX;
for (int i = 0; i < NUM_BINS; i++){
if(cdf_gpu[i] != 0 && cdf_gpu[i] < cdf_min){
cdf_min = cdf_gpu[i];
}
}*/
// std::cout << "cdf min : " << cdf_min << std::endl;
kernel<<<dimGrid1D_2D, dimBlock1D_2D>>>(input_gpu, output_histogram, width*height, cdf_min);
checkCuda(hipPeekAtLastError());
checkCuda(hipDeviceSynchronize());
#if defined(CUDA_TIMING)
TIMER_END(Ktime);
printf("Kernel Execution Time: %f ms\n", Ktime);
#endif
checkCuda(hipMemcpy(data,
input_gpu,
size*sizeof(unsigned char),
hipMemcpyDeviceToHost));
//memcpy(data, data_pinned, size*sizeof(unsigned char));
//checkCuda(cudaFreeHost(data_pinned));
checkCuda(hipFree(output_histogram));
checkCuda(hipFree(cdf_min));
//checkCuda(cudaFree(output_cdf));
//checkCuda(cudaFree(output_gpu));
checkCuda(hipFree(input_gpu));
/*
for(int i = 0; i < NUM_BINS; i++){
std::cout << "Value " << i << " : " << probability_gpu[i] << " " << cdf_gpu[i] << std::endl;
}*/
/*
for(int i = 0; i < NUM_BINS*NUM_PARTS; i++){
std::cout << "Value " << i << " : " << hist_local_gpu[i] << " " << std::endl;
} */
/*
for (long int i = 0; i < 4990464; i++){
std::cout << data[i] << " ";
}*/
}
void histogram_gpu_warmup(unsigned char *data,
unsigned int height,
unsigned int width){
int gridXSize = 1 + (( width - 1) / TILE_SIZE);
int gridYSize = 1 + ((height - 1) / TILE_SIZE);
int XSize = gridXSize*TILE_SIZE;
int YSize = gridYSize*TILE_SIZE;
// Both are the same size (CPU/GPU).
int size = XSize*YSize;
// Allocate arrays in GPU memory
checkCuda(hipMalloc((void**)&input_gpu , size*sizeof(unsigned char)));
checkCuda(hipMalloc((void**)&output_gpu , size*sizeof(unsigned char)));
checkCuda(hipMemset(output_gpu , 0 , size*sizeof(unsigned char)));
// Copy data to GPU
checkCuda(hipMemcpy(input_gpu,
data,
size*sizeof(char),
hipMemcpyHostToDevice));
checkCuda(hipDeviceSynchronize());
// Execute algorithm
dim3 dimGrid(gridXSize, gridYSize);
dim3 dimBlock(TILE_SIZE, TILE_SIZE);
kernel_warmup <<<dimGrid, dimBlock>>>(input_gpu,
output_gpu);
checkCuda(hipDeviceSynchronize());
// Retrieve results from the GPU
checkCuda(hipMemcpy(data,
output_gpu,
size*sizeof(unsigned char),
hipMemcpyDeviceToHost));
// Free resources and end the program
checkCuda(hipFree(output_gpu));
checkCuda(hipFree(input_gpu));
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPhPjjS0_
.globl _Z6kernelPhPjjS0_
.p2align 8
.type _Z6kernelPhPjjS0_,@function
_Z6kernelPhPjjS0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_clause 0x1
s_load_b32 s2, s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
v_add_co_u32 v0, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v2, vcc_lo
global_load_u8 v2, v[0:1], off
s_waitcnt lgkmcnt(0)
s_load_b32 s0, s[0:1], 0x0
s_lshr_b32 s1, s2, 6
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v2, 2, v2
global_load_b32 v2, v2, s[6:7]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_subrev_nc_u32_e32 v2, s0, v2
s_sub_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v3, s0
v_cvt_f32_u32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v4, null, v3, v3, v2
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v2, v3, v2
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v6
v_div_fmas_f32 v4, v4, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v4, v3, v2
v_mul_f32_e32 v2, 0x437f0000, v2
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v2, v2
global_store_b8 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPhPjjS0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPhPjjS0_, .Lfunc_end0-_Z6kernelPhPjjS0_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13get_histogramPhPj
.globl _Z13get_histogramPhPj
.p2align 8
.type _Z13get_histogramPhPj,@function
_Z13get_histogramPhPj:
v_and_b32_e32 v1, 63, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_add_co_u32 v0, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_load_u8 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, 1 :: v_dual_lshlrev_b32 v0, 2, v0
global_atomic_add_u32 v0, v1, s[2:3]
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13get_histogramPhPj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13get_histogramPhPj, .Lfunc_end1-_Z13get_histogramPhPj
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17get_cdf_prefixSumPj
.globl _Z17get_cdf_prefixSumPj
.p2align 8
.type _Z17get_cdf_prefixSumPj,@function
_Z17get_cdf_prefixSumPj:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v0
s_mov_b32 s0, 1
s_mov_b32 s1, 8
s_waitcnt lgkmcnt(0)
global_load_b32 v4, v3, s[2:3]
v_add_co_u32 v1, s2, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, s3, 0, s2
s_waitcnt vmcnt(0)
ds_store_b32 v3, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB2_2
.p2align 6
.LBB2_1:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s1, s1, -1
s_lshl_b32 s0, s0, 1
s_cmp_eq_u32 s1, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB2_6
.LBB2_2:
ds_load_b32 v4, v3
v_subrev_nc_u32_e32 v6, s0, v0
v_mov_b32_e32 v5, 0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_lt_i32_e32 -1, v6
s_cbranch_execz .LBB2_4
v_lshlrev_b32_e32 v5, 2, v6
ds_load_b32 v5, v5
.LBB2_4:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_le_u32_e64 s0, v0
s_cbranch_execz .LBB2_1
v_add_nc_u32_e32 v4, v5, v4
ds_store_b32 v3, v4
s_branch .LBB2_1
.LBB2_6:
s_set_inst_prefetch_distance 0x2
ds_load_b32 v0, v3
s_waitcnt lgkmcnt(0)
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17get_cdf_prefixSumPj
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z17get_cdf_prefixSumPj, .Lfunc_end2-_Z17get_cdf_prefixSumPj
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12reductionMinPjS_i
.globl _Z12reductionMinPjS_i
.p2align 8
.type _Z12reductionMinPjS_i,@function
_Z12reductionMinPjS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_lt_u16_e64 s5, s4, 2
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB3_6
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
s_and_b32 s4, 0xffff, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshr_b32 s4, s4, 1
v_add_co_u32 v3, s5, s2, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, null, s3, 0, s5
s_set_inst_prefetch_distance 0x1
s_branch .LBB3_3
.p2align 6
.LBB3_2:
s_or_b32 exec_lo, exec_lo, s5
s_lshr_b32 s5, s4, 1
s_cmp_lt_u32 s4, 2
s_mov_b32 s4, s5
s_cbranch_scc1 .LBB3_6
.LBB3_3:
s_mov_b32 s5, exec_lo
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB3_2
v_add_nc_u32_e32 v1, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_clause 0x1
global_load_b32 v7, v[3:4], off
global_load_b32 v1, v[5:6], off
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v5, -1, v7
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ge_u32_e32 vcc_lo, v5, v1
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB3_2
global_store_b32 v[3:4], v1, off
s_branch .LBB3_2
.LBB3_6:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB3_8
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
global_load_b32 v1, v0, s[2:3]
s_waitcnt vmcnt(0) lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB3_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12reductionMinPjS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z12reductionMinPjS_i, .Lfunc_end3-_Z12reductionMinPjS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13kernel_warmupPhS_
.globl _Z13kernel_warmupPhS_
.p2align 8
.type _Z13kernel_warmupPhS_,@function
_Z13kernel_warmupPhS_:
s_load_b32 s2, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_lshrrev_b32_e32 v2, 6, v0
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v0, s14, 4, v1
v_and_b32_e32 v1, 0x3ff0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_i32 v2, v0, 0x80808081
v_lshl_add_u32 v3, s15, 8, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v2, v0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s2, v3, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v2, 31, v4
v_lshrrev_b32_e32 v3, 7, v4
v_ashrrev_i32_e32 v4, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add3_u32 v2, v3, v2, v0
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v4, vcc_lo
global_store_b8 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13kernel_warmupPhS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z13kernel_warmupPhS_, .Lfunc_end4-_Z13kernel_warmupPhS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPhPjjS0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPhPjjS0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13get_histogramPhPj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13get_histogramPhPj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17get_cdf_prefixSumPj
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z17get_cdf_prefixSumPj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12reductionMinPjS_i
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z12reductionMinPjS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13kernel_warmupPhS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13kernel_warmupPhS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <time.h>
#include <iostream>
#define TIMER_CREATE(t) \
hipEvent_t t##_start, t##_end; \
hipEventCreate(&t##_start); \
hipEventCreate(&t##_end);
#define TIMER_START(t) \
hipEventRecord(t##_start); \
hipEventSynchronize(t##_start); \
#define TIMER_END(t) \
hipEventRecord(t##_end); \
hipEventSynchronize(t##_end); \
hipEventElapsedTime(&t, t##_start, t##_end); \
hipEventDestroy(t##_start); \
hipEventDestroy(t##_end);
#define TILE_SIZE 16
#define BLOCK_SIZE_1D 256
#define NUM_BINS 256
#define CUDA_TIMING
#define DEBUG
#define WARP_SIZE 32
#define R 9
unsigned char *input_gpu;
unsigned char *output_gpu;
double CLOCK() {
struct timespec t;
clock_gettime(CLOCK_MONOTONIC, &t);
return (t.tv_sec * 1000)+(t.tv_nsec*1e-6);
}
/*******************************************************/
/* Cuda Error Function */
/*******************************************************/
inline hipError_t checkCuda(hipError_t result) {
#if defined(DEBUG) || defined(_DEBUG)
if (result != hipSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", hipGetErrorString(result));
exit(-1);
}
#endif
return result;
}
// Add GPU kernel and functions
// HERE!!!
__global__ void kernel(unsigned char *input, unsigned int *output_cdf,
//unsigned char *output,
unsigned int im_size, unsigned int *cdf_min){
/*
int x = blockIdx.x*TILE_SIZE+threadIdx.x;
int y = blockIdx.y*TILE_SIZE+threadIdx.y;
int location = y*TILE_SIZE*gridDim.x+x;
input[location] = round(float(output_cdf[input[location]] - *cdf_min)/float(im_size/4 - *cdf_min) * (NUM_BINS - 1));
*/
int location = blockIdx.x * blockDim.x+threadIdx.x;
input[location] = float(output_cdf[input[location]] - *cdf_min)/float(im_size/64 - *cdf_min) * (NUM_BINS - 1);
//printf("the final: %d .", int(output[location]));
}
__global__ void get_histogram(unsigned char *input,
unsigned int *output_histogram
//int offset
){
/*
int x = blockIdx.x*TILE_SIZE+threadIdx.x;
int y = blockIdx.y*TILE_SIZE+threadIdx.y;
//if(x % 4 == 0 && y % 4 == 0){
if(x & 1 && y & 1){
int location = offset + y*TILE_SIZE*gridDim.x+x;
atomicAdd(&(output_histogram[input[location]]), 1);
}*/
if( !(threadIdx.x & 63)){
int location = blockIdx.x * blockDim.x+threadIdx.x;
atomicAdd(&(output_histogram[input[location]]), 1);
}
//__syncthreads();
}
__global__ void get_cdf_prefixSum(unsigned int *histogram)
{
int tid = threadIdx.x;
//USE SHARED MEMORY - COMON WE ARE EXPERIENCED PROGRAMMERS
__shared__ int Cache[256];
Cache[tid] = histogram[tid];
__syncthreads();
int space = 1;
//BEGIN
for (int i = 0; i < 8; i++)
{
int temp = Cache[tid];
int neighbor = 0;
if ((tid - space) >= 0)
{
neighbor = Cache[tid - space];
}
__syncthreads(); //AFTER LOADING
if (tid < space)
{
//DO NOTHING
}
else
{
Cache[tid] = temp + neighbor;
}
space = space * 2;
__syncthreads();
}
//REWRITE RESULTS TO MAIN MEMORY
histogram[tid] = Cache[tid];
}
/*
__global__ void get_cdf_naive(unsigned int *output_histogram,
unsigned int *output_cdf,
int n)
{
unsigned int d_hist_idx = blockDim.x * blockIdx.x + threadIdx.x;
if (d_hist_idx >= n)
{
return;
}
unsigned int cdf_val = 0;
for (int i = 0; i <= d_hist_idx; ++i)
{
cdf_val = cdf_val + output_histogram[i];
}
output_cdf[d_hist_idx] = cdf_val;
}*/
__global__ void reductionMin(unsigned int *sdata, unsigned int *results, int n)
{
// extern __shared__ int sdata[];
unsigned int tx = threadIdx.x;
// block-wide reduction
for(unsigned int offset = blockDim.x>>1; offset > 0; offset >>= 1)
{
__syncthreads();
if(tx < offset)
{
if(sdata[tx + offset] < sdata[tx] || sdata[tx] == 0)
sdata[tx] = sdata[tx + offset];
}
}
// finally, thread 0 writes the result
if(threadIdx.x == 0)
{
// the result is per-block
*results = sdata[0];
}
}
__global__ void kernel_warmup(unsigned char *input,
unsigned char *output){
int x = blockIdx.x*TILE_SIZE+threadIdx.x;
int y = blockIdx.y*TILE_SIZE+threadIdx.y;
int location = y*TILE_SIZE*gridDim.x+x;
output[location] = x%255;
}
void histogram_gpu(unsigned char *data,
unsigned int height,
unsigned int width){
int gridXSize = 1 + (( width - 1) / TILE_SIZE);
int gridYSize = 1 + ((height - 1) / TILE_SIZE);
int gridSize_1D = 1 + (NUM_BINS - 1)/ BLOCK_SIZE_1D;
int gridSize1D_2D = 1 + (( width*height - 1) / BLOCK_SIZE_1D);
int XSize = gridXSize*TILE_SIZE;
int YSize = gridYSize*TILE_SIZE;
// Both are the same size (CPU/GPU).
int size = XSize*YSize;
// CPU
unsigned int *cdf_gpu = new unsigned int [NUM_BINS];
// Pinned
//unsigned char *data_pinned;
// GPU
unsigned int *output_histogram;
//unsigned int *output_cdf;
unsigned int *cdf_min;
// Pageable to Pinned memory
//cudaMallocHost((void**)&data_pinned, size*sizeof(unsigned char));
//memcpy(data_pinned, data, size*sizeof(unsigned char));
// Allocate arrays in GPU memory
checkCuda(hipMalloc((void**)&input_gpu , size*sizeof(unsigned char)));
checkCuda(hipMalloc((void**)&output_histogram , NUM_BINS*sizeof(unsigned int)));
//checkCuda(cudaMalloc((void**)&output_cdf , NUM_BINS*sizeof(unsigned int)));
checkCuda(hipMalloc((void**)&cdf_min , sizeof(unsigned int)));
checkCuda(hipMemset(output_histogram , 0 , NUM_BINS*sizeof(unsigned int)));
//checkCuda(cudaMemset(output_cdf , 0 , NUM_BINS*sizeof(unsigned int)));
checkCuda(hipMemset(cdf_min, 0, sizeof(unsigned int)));
// Grid & Block Size
//dim3 dimGrid2D(gridXSize, gridYSize);
//dim3 dimBlock2D(TILE_SIZE, TILE_SIZE);
// create streams
/*
const int nStreams = 2;
const int streamSize = width*height/nStreams;
std:: cout << "stream size: " << streamSize<<std::endl;
const int streamBytes = streamSize * sizeof(unsigned char);
cudaStream_t stream[nStreams];
for (int i = 0; i < nStreams; ++i){
checkCuda(cudaStreamCreate(&stream[i]));
}
*/
// Copy data to GPU
checkCuda(hipMemcpy(input_gpu,
data,
size*sizeof(unsigned char),
hipMemcpyHostToDevice));
//checkCuda(cudaDeviceSynchronize());
// Execute algorithm
dim3 dimGrid1D(gridSize_1D);
dim3 dimBlock1D(BLOCK_SIZE_1D);
dim3 dimGrid1D_2D(gridSize1D_2D);
dim3 dimBlock1D_2D(BLOCK_SIZE_1D);
// Kernel Call
#if defined(CUDA_TIMING)
float Ktime;
TIMER_CREATE(Ktime);
TIMER_START(Ktime);
#endif
get_histogram<<<dimGrid1D_2D, dimBlock1D_2D>>>(input_gpu, output_histogram);
//get_cdf_naive<<<dimGrid1D, dimBlock1D>>>(output_histogram, output_cdf, NUM_BINS);
get_cdf_prefixSum<<<1, 256>>>(output_histogram);
reductionMin<<<1, 256>>>(output_histogram, cdf_min, 256);
//checkCuda(cudaPeekAtLastError());
//checkCuda(cudaDeviceSynchronize());
// Retrieve results from the GPU
/*
checkCuda(cudaMemcpy(cdf_gpu,
output_cdf,
NUM_BINS*sizeof(unsigned int),
cudaMemcpyDeviceToHost));
// Free resources and end the program
*/
/*
unsigned int cdf_min = INT_MAX;
for (int i = 0; i < NUM_BINS; i++){
if(cdf_gpu[i] != 0 && cdf_gpu[i] < cdf_min){
cdf_min = cdf_gpu[i];
}
}*/
// std::cout << "cdf min : " << cdf_min << std::endl;
kernel<<<dimGrid1D_2D, dimBlock1D_2D>>>(input_gpu, output_histogram, width*height, cdf_min);
checkCuda(hipPeekAtLastError());
checkCuda(hipDeviceSynchronize());
#if defined(CUDA_TIMING)
TIMER_END(Ktime);
printf("Kernel Execution Time: %f ms\n", Ktime);
#endif
checkCuda(hipMemcpy(data,
input_gpu,
size*sizeof(unsigned char),
hipMemcpyDeviceToHost));
//memcpy(data, data_pinned, size*sizeof(unsigned char));
//checkCuda(cudaFreeHost(data_pinned));
checkCuda(hipFree(output_histogram));
checkCuda(hipFree(cdf_min));
//checkCuda(cudaFree(output_cdf));
//checkCuda(cudaFree(output_gpu));
checkCuda(hipFree(input_gpu));
/*
for(int i = 0; i < NUM_BINS; i++){
std::cout << "Value " << i << " : " << probability_gpu[i] << " " << cdf_gpu[i] << std::endl;
}*/
/*
for(int i = 0; i < NUM_BINS*NUM_PARTS; i++){
std::cout << "Value " << i << " : " << hist_local_gpu[i] << " " << std::endl;
} */
/*
for (long int i = 0; i < 4990464; i++){
std::cout << data[i] << " ";
}*/
}
void histogram_gpu_warmup(unsigned char *data,
unsigned int height,
unsigned int width){
int gridXSize = 1 + (( width - 1) / TILE_SIZE);
int gridYSize = 1 + ((height - 1) / TILE_SIZE);
int XSize = gridXSize*TILE_SIZE;
int YSize = gridYSize*TILE_SIZE;
// Both are the same size (CPU/GPU).
int size = XSize*YSize;
// Allocate arrays in GPU memory
checkCuda(hipMalloc((void**)&input_gpu , size*sizeof(unsigned char)));
checkCuda(hipMalloc((void**)&output_gpu , size*sizeof(unsigned char)));
checkCuda(hipMemset(output_gpu , 0 , size*sizeof(unsigned char)));
// Copy data to GPU
checkCuda(hipMemcpy(input_gpu,
data,
size*sizeof(char),
hipMemcpyHostToDevice));
checkCuda(hipDeviceSynchronize());
// Execute algorithm
dim3 dimGrid(gridXSize, gridYSize);
dim3 dimBlock(TILE_SIZE, TILE_SIZE);
kernel_warmup <<<dimGrid, dimBlock>>>(input_gpu,
output_gpu);
checkCuda(hipDeviceSynchronize());
// Retrieve results from the GPU
checkCuda(hipMemcpy(data,
output_gpu,
size*sizeof(unsigned char),
hipMemcpyDeviceToHost));
// Free resources and end the program
checkCuda(hipFree(output_gpu));
checkCuda(hipFree(input_gpu));
}
|
.text
.file "heq.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z5CLOCKv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z5CLOCKv
.p2align 4, 0x90
.type _Z5CLOCKv,@function
_Z5CLOCKv: # @_Z5CLOCKv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rsi
movl $1, %edi
callq clock_gettime
imulq $1000, 8(%rsp), %rax # imm = 0x3E8
cvtsi2sd %rax, %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z5CLOCKv, .Lfunc_end0-_Z5CLOCKv
.cfi_endproc
# -- End function
.globl _Z21__device_stub__kernelPhPjjS0_ # -- Begin function _Z21__device_stub__kernelPhPjjS0_
.p2align 4, 0x90
.type _Z21__device_stub__kernelPhPjjS0_,@function
_Z21__device_stub__kernelPhPjjS0_: # @_Z21__device_stub__kernelPhPjjS0_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPhPjjS0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z21__device_stub__kernelPhPjjS0_, .Lfunc_end1-_Z21__device_stub__kernelPhPjjS0_
.cfi_endproc
# -- End function
.globl _Z28__device_stub__get_histogramPhPj # -- Begin function _Z28__device_stub__get_histogramPhPj
.p2align 4, 0x90
.type _Z28__device_stub__get_histogramPhPj,@function
_Z28__device_stub__get_histogramPhPj: # @_Z28__device_stub__get_histogramPhPj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13get_histogramPhPj, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z28__device_stub__get_histogramPhPj, .Lfunc_end2-_Z28__device_stub__get_histogramPhPj
.cfi_endproc
# -- End function
.globl _Z32__device_stub__get_cdf_prefixSumPj # -- Begin function _Z32__device_stub__get_cdf_prefixSumPj
.p2align 4, 0x90
.type _Z32__device_stub__get_cdf_prefixSumPj,@function
_Z32__device_stub__get_cdf_prefixSumPj: # @_Z32__device_stub__get_cdf_prefixSumPj
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z17get_cdf_prefixSumPj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z32__device_stub__get_cdf_prefixSumPj, .Lfunc_end3-_Z32__device_stub__get_cdf_prefixSumPj
.cfi_endproc
# -- End function
.globl _Z27__device_stub__reductionMinPjS_i # -- Begin function _Z27__device_stub__reductionMinPjS_i
.p2align 4, 0x90
.type _Z27__device_stub__reductionMinPjS_i,@function
_Z27__device_stub__reductionMinPjS_i: # @_Z27__device_stub__reductionMinPjS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12reductionMinPjS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z27__device_stub__reductionMinPjS_i, .Lfunc_end4-_Z27__device_stub__reductionMinPjS_i
.cfi_endproc
# -- End function
.globl _Z28__device_stub__kernel_warmupPhS_ # -- Begin function _Z28__device_stub__kernel_warmupPhS_
.p2align 4, 0x90
.type _Z28__device_stub__kernel_warmupPhS_,@function
_Z28__device_stub__kernel_warmupPhS_: # @_Z28__device_stub__kernel_warmupPhS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13kernel_warmupPhS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end5:
.size _Z28__device_stub__kernel_warmupPhS_, .Lfunc_end5-_Z28__device_stub__kernel_warmupPhS_
.cfi_endproc
# -- End function
.globl _Z13histogram_gpuPhjj # -- Begin function _Z13histogram_gpuPhjj
.p2align 4, 0x90
.type _Z13histogram_gpuPhjj,@function
_Z13histogram_gpuPhjj: # @_Z13histogram_gpuPhjj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r15d
movl %esi, %r12d
movq %rdi, %rbx
leal -1(%r15), %eax
andl $-16, %eax
leal -1(%r12), %ecx
andl $-16, %ecx
addl $16, %eax
addl $16, %ecx
imull %eax, %ecx
movslq %ecx, %r14
movl $input_gpu, %edi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB6_21
# %bb.1: # %_Z9checkCuda10hipError_t.exit
leaq 56(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
testl %eax, %eax
jne .LBB6_21
# %bb.2: # %_Z9checkCuda10hipError_t.exit42
leaq 88(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB6_21
# %bb.3: # %_Z9checkCuda10hipError_t.exit44
movq 56(%rsp), %rdi
movl $1024, %edx # imm = 0x400
xorl %esi, %esi
callq hipMemset
testl %eax, %eax
jne .LBB6_21
# %bb.4: # %_Z9checkCuda10hipError_t.exit46
movq 88(%rsp), %rdi
movl $4, %edx
xorl %esi, %esi
callq hipMemset
testl %eax, %eax
jne .LBB6_21
# %bb.5: # %_Z9checkCuda10hipError_t.exit48
movq input_gpu(%rip), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB6_21
# %bb.6: # %_Z9checkCuda10hipError_t.exit50
imull %r12d, %r15d
leal -1(%r15), %eax
shrl $8, %eax
incl %eax
movabsq $4294967552, %r12 # imm = 0x100000100
movl %eax, %eax
leaq (%rax,%r12), %r13
addq $-256, %r13
leaq 80(%rsp), %rdi
callq hipEventCreate
leaq 72(%rsp), %rdi
callq hipEventCreate
movq 80(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 80(%rsp), %rdi
callq hipEventSynchronize
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_8
# %bb.7:
movq input_gpu(%rip), %rax
movq 56(%rsp), %rcx
movq %rax, 32(%rsp)
movq %rcx, 24(%rsp)
leaq 32(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rdi
leaq 40(%rsp), %rsi
movq %rsp, %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13get_histogramPhPj, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_8:
leaq -255(%r12), %rbp
movq %rbp, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_10
# %bb.9:
movq 56(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, (%rsp)
leaq 96(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movq %rsp, %r9
movl $_Z17get_cdf_prefixSumPj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_10:
movq %rbp, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_12
# %bb.11:
movq 56(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 32(%rsp)
movq %rcx, 24(%rsp)
movl $256, 136(%rsp) # imm = 0x100
leaq 32(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 136(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rdi
leaq 40(%rsp), %rsi
movq %rsp, %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12reductionMinPjS_i, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_12:
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_14
# %bb.13:
movq input_gpu(%rip), %rax
movq 56(%rsp), %rcx
movq 88(%rsp), %rdx
movq %rax, 32(%rsp)
movq %rcx, 24(%rsp)
movl %r15d, 148(%rsp)
movq %rdx, (%rsp)
leaq 32(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 148(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 136(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6kernelPhPjjS0_, %edi
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_14:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB6_21
# %bb.15: # %_Z9checkCuda10hipError_t.exit70
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB6_21
# %bb.16: # %_Z9checkCuda10hipError_t.exit72
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 72(%rsp), %rdi
callq hipEventSynchronize
movq 80(%rsp), %rsi
movq 72(%rsp), %rdx
leaq 96(%rsp), %rdi
callq hipEventElapsedTime
movq 80(%rsp), %rdi
callq hipEventDestroy
movq 72(%rsp), %rdi
callq hipEventDestroy
movss 96(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq input_gpu(%rip), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB6_21
# %bb.17: # %_Z9checkCuda10hipError_t.exit74
movq 56(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB6_21
# %bb.18: # %_Z9checkCuda10hipError_t.exit76
movq 88(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB6_21
# %bb.19: # %_Z9checkCuda10hipError_t.exit78
movq input_gpu(%rip), %rdi
callq hipFree
testl %eax, %eax
jne .LBB6_21
# %bb.20: # %_Z9checkCuda10hipError_t.exit80
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_21:
.cfi_def_cfa_offset 208
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end6:
.size _Z13histogram_gpuPhjj, .Lfunc_end6-_Z13histogram_gpuPhjj
.cfi_endproc
# -- End function
.globl _Z20histogram_gpu_warmupPhjj # -- Begin function _Z20histogram_gpu_warmupPhjj
.p2align 4, 0x90
.type _Z20histogram_gpu_warmupPhjj,@function
_Z20histogram_gpu_warmupPhjj: # @_Z20histogram_gpu_warmupPhjj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $88, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movl %esi, %r15d
movq %rdi, %rbx
decl %ebp
shrl $4, %ebp
incl %ebp
decl %r15d
shrl $4, %r15d
incl %r15d
movl %r15d, %r14d
imull %ebp, %r14d
shll $8, %r14d
movl $input_gpu, %edi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB7_12
# %bb.1: # %_Z9checkCuda10hipError_t.exit
movl $output_gpu, %edi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB7_12
# %bb.2: # %_Z9checkCuda10hipError_t.exit21
movq output_gpu(%rip), %rdi
xorl %esi, %esi
movq %r14, %rdx
callq hipMemset
testl %eax, %eax
jne .LBB7_12
# %bb.3: # %_Z9checkCuda10hipError_t.exit23
movq input_gpu(%rip), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_12
# %bb.4: # %_Z9checkCuda10hipError_t.exit25
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB7_12
# %bb.5: # %_Z9checkCuda10hipError_t.exit27
movl %ebp, %eax
shlq $32, %r15
orq %rax, %r15
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_7
# %bb.6:
movq input_gpu(%rip), %rax
movq output_gpu(%rip), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13kernel_warmupPhS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_7:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB7_12
# %bb.8: # %_Z9checkCuda10hipError_t.exit29
movq output_gpu(%rip), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_12
# %bb.9: # %_Z9checkCuda10hipError_t.exit31
movq output_gpu(%rip), %rdi
callq hipFree
testl %eax, %eax
jne .LBB7_12
# %bb.10: # %_Z9checkCuda10hipError_t.exit33
movq input_gpu(%rip), %rdi
callq hipFree
testl %eax, %eax
jne .LBB7_12
# %bb.11: # %_Z9checkCuda10hipError_t.exit35
addq $88, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB7_12:
.cfi_def_cfa_offset 128
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end7:
.size _Z20histogram_gpu_warmupPhjj, .Lfunc_end7-_Z20histogram_gpu_warmupPhjj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPhPjjS0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13get_histogramPhPj, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17get_cdf_prefixSumPj, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12reductionMinPjS_i, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kernel_warmupPhS_, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type input_gpu,@object # @input_gpu
.bss
.globl input_gpu
.p2align 3, 0x0
input_gpu:
.quad 0
.size input_gpu, 8
.type output_gpu,@object # @output_gpu
.globl output_gpu
.p2align 3, 0x0
output_gpu:
.quad 0
.size output_gpu, 8
.type _Z6kernelPhPjjS0_,@object # @_Z6kernelPhPjjS0_
.section .rodata,"a",@progbits
.globl _Z6kernelPhPjjS0_
.p2align 3, 0x0
_Z6kernelPhPjjS0_:
.quad _Z21__device_stub__kernelPhPjjS0_
.size _Z6kernelPhPjjS0_, 8
.type _Z13get_histogramPhPj,@object # @_Z13get_histogramPhPj
.globl _Z13get_histogramPhPj
.p2align 3, 0x0
_Z13get_histogramPhPj:
.quad _Z28__device_stub__get_histogramPhPj
.size _Z13get_histogramPhPj, 8
.type _Z17get_cdf_prefixSumPj,@object # @_Z17get_cdf_prefixSumPj
.globl _Z17get_cdf_prefixSumPj
.p2align 3, 0x0
_Z17get_cdf_prefixSumPj:
.quad _Z32__device_stub__get_cdf_prefixSumPj
.size _Z17get_cdf_prefixSumPj, 8
.type _Z12reductionMinPjS_i,@object # @_Z12reductionMinPjS_i
.globl _Z12reductionMinPjS_i
.p2align 3, 0x0
_Z12reductionMinPjS_i:
.quad _Z27__device_stub__reductionMinPjS_i
.size _Z12reductionMinPjS_i, 8
.type _Z13kernel_warmupPhS_,@object # @_Z13kernel_warmupPhS_
.globl _Z13kernel_warmupPhS_
.p2align 3, 0x0
_Z13kernel_warmupPhS_:
.quad _Z28__device_stub__kernel_warmupPhS_
.size _Z13kernel_warmupPhS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Kernel Execution Time: %f ms\n"
.size .L.str, 30
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CUDA Runtime Error: %s\n"
.size .L.str.1, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPhPjjS0_"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13get_histogramPhPj"
.size .L__unnamed_2, 22
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z17get_cdf_prefixSumPj"
.size .L__unnamed_3, 24
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z12reductionMinPjS_i"
.size .L__unnamed_4, 22
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z13kernel_warmupPhS_"
.size .L__unnamed_5, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPhPjjS0_
.addrsig_sym _Z28__device_stub__get_histogramPhPj
.addrsig_sym _Z32__device_stub__get_cdf_prefixSumPj
.addrsig_sym _Z27__device_stub__reductionMinPjS_i
.addrsig_sym _Z28__device_stub__kernel_warmupPhS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym input_gpu
.addrsig_sym output_gpu
.addrsig_sym _Z6kernelPhPjjS0_
.addrsig_sym _Z13get_histogramPhPj
.addrsig_sym _Z17get_cdf_prefixSumPj
.addrsig_sym _Z12reductionMinPjS_i
.addrsig_sym _Z13kernel_warmupPhS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00064b58_00000000-6_heq.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5CLOCKv
.type _Z5CLOCKv, @function
_Z5CLOCKv:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rsi
movl $1, %edi
call clock_gettime@PLT
imulq $1000, (%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
mulsd .LC0(%rip), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z5CLOCKv, .-_Z5CLOCKv
.globl _Z31__device_stub__Z6kernelPhPjjS0_PhPjjS0_
.type _Z31__device_stub__Z6kernelPhPjjS0_PhPjjS0_, @function
_Z31__device_stub__Z6kernelPhPjjS0_PhPjjS0_:
.LFB3697:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPhPjjS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z31__device_stub__Z6kernelPhPjjS0_PhPjjS0_, .-_Z31__device_stub__Z6kernelPhPjjS0_PhPjjS0_
.globl _Z6kernelPhPjjS0_
.type _Z6kernelPhPjjS0_, @function
_Z6kernelPhPjjS0_:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6kernelPhPjjS0_PhPjjS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z6kernelPhPjjS0_, .-_Z6kernelPhPjjS0_
.globl _Z35__device_stub__Z13get_histogramPhPjPhPj
.type _Z35__device_stub__Z13get_histogramPhPjPhPj, @function
_Z35__device_stub__Z13get_histogramPhPjPhPj:
.LFB3699:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13get_histogramPhPj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z35__device_stub__Z13get_histogramPhPjPhPj, .-_Z35__device_stub__Z13get_histogramPhPjPhPj
.globl _Z13get_histogramPhPj
.type _Z13get_histogramPhPj, @function
_Z13get_histogramPhPj:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13get_histogramPhPjPhPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z13get_histogramPhPj, .-_Z13get_histogramPhPj
.globl _Z37__device_stub__Z17get_cdf_prefixSumPjPj
.type _Z37__device_stub__Z17get_cdf_prefixSumPjPj, @function
_Z37__device_stub__Z17get_cdf_prefixSumPjPj:
.LFB3701:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17get_cdf_prefixSumPj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _Z37__device_stub__Z17get_cdf_prefixSumPjPj, .-_Z37__device_stub__Z17get_cdf_prefixSumPjPj
.globl _Z17get_cdf_prefixSumPj
.type _Z17get_cdf_prefixSumPj, @function
_Z17get_cdf_prefixSumPj:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z17get_cdf_prefixSumPjPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _Z17get_cdf_prefixSumPj, .-_Z17get_cdf_prefixSumPj
.globl _Z35__device_stub__Z12reductionMinPjS_iPjS_i
.type _Z35__device_stub__Z12reductionMinPjS_iPjS_i, @function
_Z35__device_stub__Z12reductionMinPjS_iPjS_i:
.LFB3703:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12reductionMinPjS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3703:
.size _Z35__device_stub__Z12reductionMinPjS_iPjS_i, .-_Z35__device_stub__Z12reductionMinPjS_iPjS_i
.globl _Z12reductionMinPjS_i
.type _Z12reductionMinPjS_i, @function
_Z12reductionMinPjS_i:
.LFB3704:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12reductionMinPjS_iPjS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _Z12reductionMinPjS_i, .-_Z12reductionMinPjS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "CUDA Runtime Error: %s\n"
.LC2:
.string "Kernel Execution Time: %f ms\n"
.text
.globl _Z13histogram_gpuPhjj
.type _Z13histogram_gpuPhjj, @function
_Z13histogram_gpuPhjj:
.LFB3671:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $104, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %r12
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl %edx, %r13d
imull %esi, %r13d
leal -1(%r13), %ebp
shrl $8, %ebp
addl $1, %ebp
leal -1(%rdx), %ebx
shrl $4, %ebx
addl $1, %ebx
subl $1, %esi
shrl $4, %esi
addl $1, %esi
imull %esi, %ebx
sall $8, %ebx
movslq %ebx, %rbx
movq %rbx, %rsi
leaq input_gpu(%rip), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L58
leaq 8(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L59
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L60
movl $1024, %edx
movl $0, %esi
movq 8(%rsp), %rdi
call cudaMemset@PLT
testl %eax, %eax
jne .L61
movl $4, %edx
movl $0, %esi
movq 16(%rsp), %rdi
call cudaMemset@PLT
testl %eax, %eax
jne .L62
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq input_gpu(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L63
movl %ebp, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $256, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl 60(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movq 40(%rsp), %rdi
movl 48(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L64
.L46:
movl $256, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
.L47:
movl $256, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L66
.L48:
movl 60(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movq 40(%rsp), %rdi
movl 48(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L67
.L49:
call cudaPeekAtLastError@PLT
testl %eax, %eax
jne .L68
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L69
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 76(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
pxor %xmm0, %xmm0
cvtss2sd 76(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbx, %rdx
movq input_gpu(%rip), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L70
movq 8(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L71
movq 16(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L72
movq input_gpu(%rip), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L73
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L74
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L59:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L60:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L61:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L62:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L63:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L64:
movq 8(%rsp), %rsi
movq input_gpu(%rip), %rdi
call _Z35__device_stub__Z13get_histogramPhPjPhPj
jmp .L46
.L65:
movq 8(%rsp), %rdi
call _Z37__device_stub__Z17get_cdf_prefixSumPjPj
jmp .L47
.L66:
movl $256, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z12reductionMinPjS_iPjS_i
jmp .L48
.L67:
movq 16(%rsp), %rcx
movl %r13d, %edx
movq 8(%rsp), %rsi
movq input_gpu(%rip), %rdi
call _Z31__device_stub__Z6kernelPhPjjS0_PhPjjS0_
jmp .L49
.L68:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L69:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L70:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L71:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L72:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L73:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L74:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size _Z13histogram_gpuPhjj, .-_Z13histogram_gpuPhjj
.globl _Z35__device_stub__Z13kernel_warmupPhS_PhS_
.type _Z35__device_stub__Z13kernel_warmupPhS_PhS_, @function
_Z35__device_stub__Z13kernel_warmupPhS_PhS_:
.LFB3705:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L79
.L75:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L80
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L79:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13kernel_warmupPhS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L75
.L80:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3705:
.size _Z35__device_stub__Z13kernel_warmupPhS_PhS_, .-_Z35__device_stub__Z13kernel_warmupPhS_PhS_
.globl _Z13kernel_warmupPhS_
.type _Z13kernel_warmupPhS_, @function
_Z13kernel_warmupPhS_:
.LFB3706:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13kernel_warmupPhS_PhS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3706:
.size _Z13kernel_warmupPhS_, .-_Z13kernel_warmupPhS_
.globl _Z20histogram_gpu_warmupPhjj
.type _Z20histogram_gpu_warmupPhjj, @function
_Z20histogram_gpu_warmupPhjj:
.LFB3672:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
leal -1(%rdx), %r12d
shrl $4, %r12d
addl $1, %r12d
subl $1, %esi
shrl $4, %esi
leal 1(%rsi), %ebp
movl %r12d, %ebx
imull %ebp, %ebx
sall $8, %ebx
movslq %ebx, %rbx
movq %rbx, %rsi
leaq input_gpu(%rip), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L95
movq %rbx, %rsi
leaq output_gpu(%rip), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L96
movq %rbx, %rdx
movl $0, %esi
movq output_gpu(%rip), %rdi
call cudaMemset@PLT
testl %eax, %eax
jne .L97
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq input_gpu(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L98
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L99
movl %r12d, 8(%rsp)
movl %ebp, 12(%rsp)
movl $16, 20(%rsp)
movl $16, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L100
.L89:
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L101
movl $2, %ecx
movq %rbx, %rdx
movq output_gpu(%rip), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L102
movq output_gpu(%rip), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L103
movq input_gpu(%rip), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L104
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L95:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L96:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L97:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L98:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L99:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L100:
movq output_gpu(%rip), %rsi
movq input_gpu(%rip), %rdi
call _Z35__device_stub__Z13kernel_warmupPhS_PhS_
jmp .L89
.L101:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L102:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L103:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L104:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE3672:
.size _Z20histogram_gpu_warmupPhjj, .-_Z20histogram_gpu_warmupPhjj
.section .rodata.str1.1
.LC3:
.string "_Z13kernel_warmupPhS_"
.LC4:
.string "_Z12reductionMinPjS_i"
.LC5:
.string "_Z17get_cdf_prefixSumPj"
.LC6:
.string "_Z13get_histogramPhPj"
.LC7:
.string "_Z6kernelPhPjjS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3708:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kernel_warmupPhS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z12reductionMinPjS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z17get_cdf_prefixSumPj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z13get_histogramPhPj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPhPjjS0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3708:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl output_gpu
.bss
.align 8
.type output_gpu, @object
.size output_gpu, 8
output_gpu:
.zero 8
.globl input_gpu
.align 8
.type input_gpu, @object
.size input_gpu, 8
input_gpu:
.zero 8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "heq.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z5CLOCKv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z5CLOCKv
.p2align 4, 0x90
.type _Z5CLOCKv,@function
_Z5CLOCKv: # @_Z5CLOCKv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rsi
movl $1, %edi
callq clock_gettime
imulq $1000, 8(%rsp), %rax # imm = 0x3E8
cvtsi2sd %rax, %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z5CLOCKv, .Lfunc_end0-_Z5CLOCKv
.cfi_endproc
# -- End function
.globl _Z21__device_stub__kernelPhPjjS0_ # -- Begin function _Z21__device_stub__kernelPhPjjS0_
.p2align 4, 0x90
.type _Z21__device_stub__kernelPhPjjS0_,@function
_Z21__device_stub__kernelPhPjjS0_: # @_Z21__device_stub__kernelPhPjjS0_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPhPjjS0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z21__device_stub__kernelPhPjjS0_, .Lfunc_end1-_Z21__device_stub__kernelPhPjjS0_
.cfi_endproc
# -- End function
.globl _Z28__device_stub__get_histogramPhPj # -- Begin function _Z28__device_stub__get_histogramPhPj
.p2align 4, 0x90
.type _Z28__device_stub__get_histogramPhPj,@function
_Z28__device_stub__get_histogramPhPj: # @_Z28__device_stub__get_histogramPhPj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13get_histogramPhPj, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z28__device_stub__get_histogramPhPj, .Lfunc_end2-_Z28__device_stub__get_histogramPhPj
.cfi_endproc
# -- End function
.globl _Z32__device_stub__get_cdf_prefixSumPj # -- Begin function _Z32__device_stub__get_cdf_prefixSumPj
.p2align 4, 0x90
.type _Z32__device_stub__get_cdf_prefixSumPj,@function
_Z32__device_stub__get_cdf_prefixSumPj: # @_Z32__device_stub__get_cdf_prefixSumPj
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z17get_cdf_prefixSumPj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z32__device_stub__get_cdf_prefixSumPj, .Lfunc_end3-_Z32__device_stub__get_cdf_prefixSumPj
.cfi_endproc
# -- End function
.globl _Z27__device_stub__reductionMinPjS_i # -- Begin function _Z27__device_stub__reductionMinPjS_i
.p2align 4, 0x90
.type _Z27__device_stub__reductionMinPjS_i,@function
_Z27__device_stub__reductionMinPjS_i: # @_Z27__device_stub__reductionMinPjS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12reductionMinPjS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z27__device_stub__reductionMinPjS_i, .Lfunc_end4-_Z27__device_stub__reductionMinPjS_i
.cfi_endproc
# -- End function
.globl _Z28__device_stub__kernel_warmupPhS_ # -- Begin function _Z28__device_stub__kernel_warmupPhS_
.p2align 4, 0x90
.type _Z28__device_stub__kernel_warmupPhS_,@function
_Z28__device_stub__kernel_warmupPhS_: # @_Z28__device_stub__kernel_warmupPhS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13kernel_warmupPhS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end5:
.size _Z28__device_stub__kernel_warmupPhS_, .Lfunc_end5-_Z28__device_stub__kernel_warmupPhS_
.cfi_endproc
# -- End function
.globl _Z13histogram_gpuPhjj # -- Begin function _Z13histogram_gpuPhjj
.p2align 4, 0x90
.type _Z13histogram_gpuPhjj,@function
_Z13histogram_gpuPhjj: # @_Z13histogram_gpuPhjj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r15d
movl %esi, %r12d
movq %rdi, %rbx
leal -1(%r15), %eax
andl $-16, %eax
leal -1(%r12), %ecx
andl $-16, %ecx
addl $16, %eax
addl $16, %ecx
imull %eax, %ecx
movslq %ecx, %r14
movl $input_gpu, %edi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB6_21
# %bb.1: # %_Z9checkCuda10hipError_t.exit
leaq 56(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
testl %eax, %eax
jne .LBB6_21
# %bb.2: # %_Z9checkCuda10hipError_t.exit42
leaq 88(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB6_21
# %bb.3: # %_Z9checkCuda10hipError_t.exit44
movq 56(%rsp), %rdi
movl $1024, %edx # imm = 0x400
xorl %esi, %esi
callq hipMemset
testl %eax, %eax
jne .LBB6_21
# %bb.4: # %_Z9checkCuda10hipError_t.exit46
movq 88(%rsp), %rdi
movl $4, %edx
xorl %esi, %esi
callq hipMemset
testl %eax, %eax
jne .LBB6_21
# %bb.5: # %_Z9checkCuda10hipError_t.exit48
movq input_gpu(%rip), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB6_21
# %bb.6: # %_Z9checkCuda10hipError_t.exit50
imull %r12d, %r15d
leal -1(%r15), %eax
shrl $8, %eax
incl %eax
movabsq $4294967552, %r12 # imm = 0x100000100
movl %eax, %eax
leaq (%rax,%r12), %r13
addq $-256, %r13
leaq 80(%rsp), %rdi
callq hipEventCreate
leaq 72(%rsp), %rdi
callq hipEventCreate
movq 80(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 80(%rsp), %rdi
callq hipEventSynchronize
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_8
# %bb.7:
movq input_gpu(%rip), %rax
movq 56(%rsp), %rcx
movq %rax, 32(%rsp)
movq %rcx, 24(%rsp)
leaq 32(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rdi
leaq 40(%rsp), %rsi
movq %rsp, %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13get_histogramPhPj, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_8:
leaq -255(%r12), %rbp
movq %rbp, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_10
# %bb.9:
movq 56(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, (%rsp)
leaq 96(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movq %rsp, %r9
movl $_Z17get_cdf_prefixSumPj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_10:
movq %rbp, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_12
# %bb.11:
movq 56(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 32(%rsp)
movq %rcx, 24(%rsp)
movl $256, 136(%rsp) # imm = 0x100
leaq 32(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 136(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rdi
leaq 40(%rsp), %rsi
movq %rsp, %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12reductionMinPjS_i, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_12:
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_14
# %bb.13:
movq input_gpu(%rip), %rax
movq 56(%rsp), %rcx
movq 88(%rsp), %rdx
movq %rax, 32(%rsp)
movq %rcx, 24(%rsp)
movl %r15d, 148(%rsp)
movq %rdx, (%rsp)
leaq 32(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 148(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 136(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6kernelPhPjjS0_, %edi
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_14:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB6_21
# %bb.15: # %_Z9checkCuda10hipError_t.exit70
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB6_21
# %bb.16: # %_Z9checkCuda10hipError_t.exit72
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 72(%rsp), %rdi
callq hipEventSynchronize
movq 80(%rsp), %rsi
movq 72(%rsp), %rdx
leaq 96(%rsp), %rdi
callq hipEventElapsedTime
movq 80(%rsp), %rdi
callq hipEventDestroy
movq 72(%rsp), %rdi
callq hipEventDestroy
movss 96(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq input_gpu(%rip), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB6_21
# %bb.17: # %_Z9checkCuda10hipError_t.exit74
movq 56(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB6_21
# %bb.18: # %_Z9checkCuda10hipError_t.exit76
movq 88(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB6_21
# %bb.19: # %_Z9checkCuda10hipError_t.exit78
movq input_gpu(%rip), %rdi
callq hipFree
testl %eax, %eax
jne .LBB6_21
# %bb.20: # %_Z9checkCuda10hipError_t.exit80
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_21:
.cfi_def_cfa_offset 208
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end6:
.size _Z13histogram_gpuPhjj, .Lfunc_end6-_Z13histogram_gpuPhjj
.cfi_endproc
# -- End function
.globl _Z20histogram_gpu_warmupPhjj # -- Begin function _Z20histogram_gpu_warmupPhjj
.p2align 4, 0x90
.type _Z20histogram_gpu_warmupPhjj,@function
_Z20histogram_gpu_warmupPhjj: # @_Z20histogram_gpu_warmupPhjj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $88, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movl %esi, %r15d
movq %rdi, %rbx
decl %ebp
shrl $4, %ebp
incl %ebp
decl %r15d
shrl $4, %r15d
incl %r15d
movl %r15d, %r14d
imull %ebp, %r14d
shll $8, %r14d
movl $input_gpu, %edi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB7_12
# %bb.1: # %_Z9checkCuda10hipError_t.exit
movl $output_gpu, %edi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB7_12
# %bb.2: # %_Z9checkCuda10hipError_t.exit21
movq output_gpu(%rip), %rdi
xorl %esi, %esi
movq %r14, %rdx
callq hipMemset
testl %eax, %eax
jne .LBB7_12
# %bb.3: # %_Z9checkCuda10hipError_t.exit23
movq input_gpu(%rip), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_12
# %bb.4: # %_Z9checkCuda10hipError_t.exit25
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB7_12
# %bb.5: # %_Z9checkCuda10hipError_t.exit27
movl %ebp, %eax
shlq $32, %r15
orq %rax, %r15
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_7
# %bb.6:
movq input_gpu(%rip), %rax
movq output_gpu(%rip), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13kernel_warmupPhS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_7:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB7_12
# %bb.8: # %_Z9checkCuda10hipError_t.exit29
movq output_gpu(%rip), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_12
# %bb.9: # %_Z9checkCuda10hipError_t.exit31
movq output_gpu(%rip), %rdi
callq hipFree
testl %eax, %eax
jne .LBB7_12
# %bb.10: # %_Z9checkCuda10hipError_t.exit33
movq input_gpu(%rip), %rdi
callq hipFree
testl %eax, %eax
jne .LBB7_12
# %bb.11: # %_Z9checkCuda10hipError_t.exit35
addq $88, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB7_12:
.cfi_def_cfa_offset 128
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end7:
.size _Z20histogram_gpu_warmupPhjj, .Lfunc_end7-_Z20histogram_gpu_warmupPhjj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPhPjjS0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13get_histogramPhPj, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17get_cdf_prefixSumPj, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12reductionMinPjS_i, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kernel_warmupPhS_, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type input_gpu,@object # @input_gpu
.bss
.globl input_gpu
.p2align 3, 0x0
input_gpu:
.quad 0
.size input_gpu, 8
.type output_gpu,@object # @output_gpu
.globl output_gpu
.p2align 3, 0x0
output_gpu:
.quad 0
.size output_gpu, 8
.type _Z6kernelPhPjjS0_,@object # @_Z6kernelPhPjjS0_
.section .rodata,"a",@progbits
.globl _Z6kernelPhPjjS0_
.p2align 3, 0x0
_Z6kernelPhPjjS0_:
.quad _Z21__device_stub__kernelPhPjjS0_
.size _Z6kernelPhPjjS0_, 8
.type _Z13get_histogramPhPj,@object # @_Z13get_histogramPhPj
.globl _Z13get_histogramPhPj
.p2align 3, 0x0
_Z13get_histogramPhPj:
.quad _Z28__device_stub__get_histogramPhPj
.size _Z13get_histogramPhPj, 8
.type _Z17get_cdf_prefixSumPj,@object # @_Z17get_cdf_prefixSumPj
.globl _Z17get_cdf_prefixSumPj
.p2align 3, 0x0
_Z17get_cdf_prefixSumPj:
.quad _Z32__device_stub__get_cdf_prefixSumPj
.size _Z17get_cdf_prefixSumPj, 8
.type _Z12reductionMinPjS_i,@object # @_Z12reductionMinPjS_i
.globl _Z12reductionMinPjS_i
.p2align 3, 0x0
_Z12reductionMinPjS_i:
.quad _Z27__device_stub__reductionMinPjS_i
.size _Z12reductionMinPjS_i, 8
.type _Z13kernel_warmupPhS_,@object # @_Z13kernel_warmupPhS_
.globl _Z13kernel_warmupPhS_
.p2align 3, 0x0
_Z13kernel_warmupPhS_:
.quad _Z28__device_stub__kernel_warmupPhS_
.size _Z13kernel_warmupPhS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Kernel Execution Time: %f ms\n"
.size .L.str, 30
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CUDA Runtime Error: %s\n"
.size .L.str.1, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPhPjjS0_"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13get_histogramPhPj"
.size .L__unnamed_2, 22
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z17get_cdf_prefixSumPj"
.size .L__unnamed_3, 24
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z12reductionMinPjS_i"
.size .L__unnamed_4, 22
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z13kernel_warmupPhS_"
.size .L__unnamed_5, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPhPjjS0_
.addrsig_sym _Z28__device_stub__get_histogramPhPj
.addrsig_sym _Z32__device_stub__get_cdf_prefixSumPj
.addrsig_sym _Z27__device_stub__reductionMinPjS_i
.addrsig_sym _Z28__device_stub__kernel_warmupPhS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym input_gpu
.addrsig_sym output_gpu
.addrsig_sym _Z6kernelPhPjjS0_
.addrsig_sym _Z13get_histogramPhPj
.addrsig_sym _Z17get_cdf_prefixSumPj
.addrsig_sym _Z12reductionMinPjS_i
.addrsig_sym _Z13kernel_warmupPhS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
//created by xianglizhi, code follows exactly tensorflow fill example which is below
//compile cmd is nvcc -std=c++11 -O3 -I /usr/local/cuda/include -L /usr/local/cuda/lib64 -L /usr/local/lib fill.cu -o fill
//running ./fill
/*
* .html# Output tensor has shape [2, 3].
fill([2, 3], 9) ==> [[9, 9, 9]
[9, 9, 9]]
*/
#include <stdio.h>
#include <cuda.h>
#include <malloc.h>
#include <cstdlib>
#include <time.h>
#include <iostream>
#include <sys/types.h>
#include <errno.h>
#include <vector>
template<class T>
__global__ void fill(T *input, T value, unsigned int linear_input_shape){
unsigned int global_id = blockIdx.x * blockDim.x + threadIdx.x;
if(global_id >= linear_input_shape){
return;
}
input[global_id] = value;
}
int main(int argc, char *argv[]){
float *float_matrix;//declared output buffer
int *int_matrix;//declared output buffer
// assuming desired matrix shape is 3,4,5, now we malloc the needed buffer in GPU
cudaMalloc(&float_matrix,3*4*5*sizeof(float));
cudaMalloc(&int_matrix,3*4*5*sizeof(int));
//we fix block size to 64, feel free to change
dim3 block(64);
//how many blocks we need for this job, for here we need (3*4*5 - 1)/64 + 1 blocks
dim3 grid((3*4*5 - 1)/64 + 1);
//fill<float><<<grid,block>>>(float_matrx,1.0f,3*4*5);
fill<int><<<grid,block>>>(int_matrix,1,3*4*5);
int *host_buffer = (int *)malloc(3*4*5*sizeof(int));
cudaMemcpy(host_buffer,int_matrix,3*4*5*sizeof(int),cudaMemcpyDeviceToHost);
for(unsigned int i = 0; i < 3*4*5; ++i){
std::cout<<host_buffer[i]<<" ";
}
std::cout<<std::endl;
return 0;
}
|
code for sm_80
Function : _Z4fillIiEvPT_S0_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x16c], PT ; /* 0x00005b0002007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R5, c[0x0][0x168] ; /* 0x00005a0000057a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0003 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
//created by xianglizhi, code follows exactly tensorflow fill example which is below
//compile cmd is nvcc -std=c++11 -O3 -I /usr/local/cuda/include -L /usr/local/cuda/lib64 -L /usr/local/lib fill.cu -o fill
//running ./fill
/*
* .html# Output tensor has shape [2, 3].
fill([2, 3], 9) ==> [[9, 9, 9]
[9, 9, 9]]
*/
#include <stdio.h>
#include <cuda.h>
#include <malloc.h>
#include <cstdlib>
#include <time.h>
#include <iostream>
#include <sys/types.h>
#include <errno.h>
#include <vector>
template<class T>
__global__ void fill(T *input, T value, unsigned int linear_input_shape){
unsigned int global_id = blockIdx.x * blockDim.x + threadIdx.x;
if(global_id >= linear_input_shape){
return;
}
input[global_id] = value;
}
int main(int argc, char *argv[]){
float *float_matrix;//declared output buffer
int *int_matrix;//declared output buffer
// assuming desired matrix shape is 3,4,5, now we malloc the needed buffer in GPU
cudaMalloc(&float_matrix,3*4*5*sizeof(float));
cudaMalloc(&int_matrix,3*4*5*sizeof(int));
//we fix block size to 64, feel free to change
dim3 block(64);
//how many blocks we need for this job, for here we need (3*4*5 - 1)/64 + 1 blocks
dim3 grid((3*4*5 - 1)/64 + 1);
//fill<float><<<grid,block>>>(float_matrx,1.0f,3*4*5);
fill<int><<<grid,block>>>(int_matrix,1,3*4*5);
int *host_buffer = (int *)malloc(3*4*5*sizeof(int));
cudaMemcpy(host_buffer,int_matrix,3*4*5*sizeof(int),cudaMemcpyDeviceToHost);
for(unsigned int i = 0; i < 3*4*5; ++i){
std::cout<<host_buffer[i]<<" ";
}
std::cout<<std::endl;
return 0;
}
|
.file "tmpxft_00068afb_00000000-6_fill.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.section .text._Z4fillIiEvPT_S0_j,"axG",@progbits,_Z4fillIiEvPT_S0_j,comdat
.weak _Z4fillIiEvPT_S0_j
.type _Z4fillIiEvPT_S0_j, @function
_Z4fillIiEvPT_S0_j:
.LFB4364:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movl %esi, (%rsp)
movl %edx, 4(%rsp)
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4fillIiEvPT_S0_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4364:
.size _Z4fillIiEvPT_S0_j, .-_Z4fillIiEvPT_S0_j
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4037:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4037:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl main
.type main, @function
main:
.LFB4034:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $240, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $240, %esi
call cudaMalloc@PLT
movl $64, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L10:
movl $240, %edi
call malloc@PLT
movq %rax, %rbp
movl $2, %ecx
movl $240, %edx
movq 8(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movq %rbp, %rbx
addq $240, %rbp
leaq _ZSt4cout(%rip), %r13
leaq .LC0(%rip), %r12
.L11:
movl (%rbx), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, %rbp
jne .L11
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl $60, %edx
movl $1, %esi
movq 8(%rsp), %rdi
call _Z4fillIiEvPT_S0_j
jmp .L10
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4034:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z4fillIiEvPT_S0_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z4fillIiEvPT_S0_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4062:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
//created by xianglizhi, code follows exactly tensorflow fill example which is below
//compile cmd is nvcc -std=c++11 -O3 -I /usr/local/cuda/include -L /usr/local/cuda/lib64 -L /usr/local/lib fill.cu -o fill
//running ./fill
/*
* .html# Output tensor has shape [2, 3].
fill([2, 3], 9) ==> [[9, 9, 9]
[9, 9, 9]]
*/
#include <stdio.h>
#include <cuda.h>
#include <malloc.h>
#include <cstdlib>
#include <time.h>
#include <iostream>
#include <sys/types.h>
#include <errno.h>
#include <vector>
template<class T>
__global__ void fill(T *input, T value, unsigned int linear_input_shape){
unsigned int global_id = blockIdx.x * blockDim.x + threadIdx.x;
if(global_id >= linear_input_shape){
return;
}
input[global_id] = value;
}
int main(int argc, char *argv[]){
float *float_matrix;//declared output buffer
int *int_matrix;//declared output buffer
// assuming desired matrix shape is 3,4,5, now we malloc the needed buffer in GPU
cudaMalloc(&float_matrix,3*4*5*sizeof(float));
cudaMalloc(&int_matrix,3*4*5*sizeof(int));
//we fix block size to 64, feel free to change
dim3 block(64);
//how many blocks we need for this job, for here we need (3*4*5 - 1)/64 + 1 blocks
dim3 grid((3*4*5 - 1)/64 + 1);
//fill<float><<<grid,block>>>(float_matrx,1.0f,3*4*5);
fill<int><<<grid,block>>>(int_matrix,1,3*4*5);
int *host_buffer = (int *)malloc(3*4*5*sizeof(int));
cudaMemcpy(host_buffer,int_matrix,3*4*5*sizeof(int),cudaMemcpyDeviceToHost);
for(unsigned int i = 0; i < 3*4*5; ++i){
std::cout<<host_buffer[i]<<" ";
}
std::cout<<std::endl;
return 0;
}
|
//created by xianglizhi, code follows exactly tensorflow fill example which is below
//compile cmd is nvcc -std=c++11 -O3 -I /usr/local/cuda/include -L /usr/local/cuda/lib64 -L /usr/local/lib fill.cu -o fill
//running ./fill
/*
* .html# Output tensor has shape [2, 3].
fill([2, 3], 9) ==> [[9, 9, 9]
[9, 9, 9]]
*/
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <malloc.h>
#include <cstdlib>
#include <time.h>
#include <iostream>
#include <sys/types.h>
#include <errno.h>
#include <vector>
template<class T>
__global__ void fill(T *input, T value, unsigned int linear_input_shape){
unsigned int global_id = blockIdx.x * blockDim.x + threadIdx.x;
if(global_id >= linear_input_shape){
return;
}
input[global_id] = value;
}
int main(int argc, char *argv[]){
float *float_matrix;//declared output buffer
int *int_matrix;//declared output buffer
// assuming desired matrix shape is 3,4,5, now we malloc the needed buffer in GPU
hipMalloc(&float_matrix,3*4*5*sizeof(float));
hipMalloc(&int_matrix,3*4*5*sizeof(int));
//we fix block size to 64, feel free to change
dim3 block(64);
//how many blocks we need for this job, for here we need (3*4*5 - 1)/64 + 1 blocks
dim3 grid((3*4*5 - 1)/64 + 1);
//fill<float><<<grid,block>>>(float_matrx,1.0f,3*4*5);
fill<int><<<grid,block>>>(int_matrix,1,3*4*5);
int *host_buffer = (int *)malloc(3*4*5*sizeof(int));
hipMemcpy(host_buffer,int_matrix,3*4*5*sizeof(int),hipMemcpyDeviceToHost);
for(unsigned int i = 0; i < 3*4*5; ++i){
std::cout<<host_buffer[i]<<" ";
}
std::cout<<std::endl;
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
//created by xianglizhi, code follows exactly tensorflow fill example which is below
//compile cmd is nvcc -std=c++11 -O3 -I /usr/local/cuda/include -L /usr/local/cuda/lib64 -L /usr/local/lib fill.cu -o fill
//running ./fill
/*
* .html# Output tensor has shape [2, 3].
fill([2, 3], 9) ==> [[9, 9, 9]
[9, 9, 9]]
*/
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <malloc.h>
#include <cstdlib>
#include <time.h>
#include <iostream>
#include <sys/types.h>
#include <errno.h>
#include <vector>
template<class T>
__global__ void fill(T *input, T value, unsigned int linear_input_shape){
unsigned int global_id = blockIdx.x * blockDim.x + threadIdx.x;
if(global_id >= linear_input_shape){
return;
}
input[global_id] = value;
}
int main(int argc, char *argv[]){
float *float_matrix;//declared output buffer
int *int_matrix;//declared output buffer
// assuming desired matrix shape is 3,4,5, now we malloc the needed buffer in GPU
hipMalloc(&float_matrix,3*4*5*sizeof(float));
hipMalloc(&int_matrix,3*4*5*sizeof(int));
//we fix block size to 64, feel free to change
dim3 block(64);
//how many blocks we need for this job, for here we need (3*4*5 - 1)/64 + 1 blocks
dim3 grid((3*4*5 - 1)/64 + 1);
//fill<float><<<grid,block>>>(float_matrx,1.0f,3*4*5);
fill<int><<<grid,block>>>(int_matrix,1,3*4*5);
int *host_buffer = (int *)malloc(3*4*5*sizeof(int));
hipMemcpy(host_buffer,int_matrix,3*4*5*sizeof(int),hipMemcpyDeviceToHost);
for(unsigned int i = 0; i < 3*4*5; ++i){
std::cout<<host_buffer[i]<<" ";
}
std::cout<<std::endl;
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z4fillIiEvPT_S0_j,"axG",@progbits,_Z4fillIiEvPT_S0_j,comdat
.protected _Z4fillIiEvPT_S0_j
.globl _Z4fillIiEvPT_S0_j
.p2align 8
.type _Z4fillIiEvPT_S0_j,@function
_Z4fillIiEvPT_S0_j:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_mov_b32_e32 v2, s0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4fillIiEvPT_S0_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z4fillIiEvPT_S0_j,"axG",@progbits,_Z4fillIiEvPT_S0_j,comdat
.Lfunc_end0:
.size _Z4fillIiEvPT_S0_j, .Lfunc_end0-_Z4fillIiEvPT_S0_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4fillIiEvPT_S0_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4fillIiEvPT_S0_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
//created by xianglizhi, code follows exactly tensorflow fill example which is below
//compile cmd is nvcc -std=c++11 -O3 -I /usr/local/cuda/include -L /usr/local/cuda/lib64 -L /usr/local/lib fill.cu -o fill
//running ./fill
/*
* .html# Output tensor has shape [2, 3].
fill([2, 3], 9) ==> [[9, 9, 9]
[9, 9, 9]]
*/
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <malloc.h>
#include <cstdlib>
#include <time.h>
#include <iostream>
#include <sys/types.h>
#include <errno.h>
#include <vector>
template<class T>
__global__ void fill(T *input, T value, unsigned int linear_input_shape){
unsigned int global_id = blockIdx.x * blockDim.x + threadIdx.x;
if(global_id >= linear_input_shape){
return;
}
input[global_id] = value;
}
int main(int argc, char *argv[]){
float *float_matrix;//declared output buffer
int *int_matrix;//declared output buffer
// assuming desired matrix shape is 3,4,5, now we malloc the needed buffer in GPU
hipMalloc(&float_matrix,3*4*5*sizeof(float));
hipMalloc(&int_matrix,3*4*5*sizeof(int));
//we fix block size to 64, feel free to change
dim3 block(64);
//how many blocks we need for this job, for here we need (3*4*5 - 1)/64 + 1 blocks
dim3 grid((3*4*5 - 1)/64 + 1);
//fill<float><<<grid,block>>>(float_matrx,1.0f,3*4*5);
fill<int><<<grid,block>>>(int_matrix,1,3*4*5);
int *host_buffer = (int *)malloc(3*4*5*sizeof(int));
hipMemcpy(host_buffer,int_matrix,3*4*5*sizeof(int),hipMemcpyDeviceToHost);
for(unsigned int i = 0; i < 3*4*5; ++i){
std::cout<<host_buffer[i]<<" ";
}
std::cout<<std::endl;
return 0;
}
|
.text
.file "fill.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 112(%rsp), %rdi
movl $240, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $240, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 63(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $1, 12(%rsp)
movl $60, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4fillIiEvPT_S0_j, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
movl $240, %edi
callq malloc
movq %rax, %rbx
movq 16(%rsp), %rsi
movl $240, %edx
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq $60, %r14
jne .LBB0_3
# %bb.4:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_9
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_7
# %bb.6:
movzbl 67(%rbx), %eax
jmp .LBB0_8
.LBB0_7:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_9:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .text._Z19__device_stub__fillIiEvPT_S0_j,"axG",@progbits,_Z19__device_stub__fillIiEvPT_S0_j,comdat
.weak _Z19__device_stub__fillIiEvPT_S0_j # -- Begin function _Z19__device_stub__fillIiEvPT_S0_j
.p2align 4, 0x90
.type _Z19__device_stub__fillIiEvPT_S0_j,@function
_Z19__device_stub__fillIiEvPT_S0_j: # @_Z19__device_stub__fillIiEvPT_S0_j
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4fillIiEvPT_S0_j, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z19__device_stub__fillIiEvPT_S0_j, .Lfunc_end1-_Z19__device_stub__fillIiEvPT_S0_j
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4fillIiEvPT_S0_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4fillIiEvPT_S0_j,@object # @_Z4fillIiEvPT_S0_j
.section .rodata._Z4fillIiEvPT_S0_j,"aG",@progbits,_Z4fillIiEvPT_S0_j,comdat
.weak _Z4fillIiEvPT_S0_j
.p2align 3, 0x0
_Z4fillIiEvPT_S0_j:
.quad _Z19__device_stub__fillIiEvPT_S0_j
.size _Z4fillIiEvPT_S0_j, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4fillIiEvPT_S0_j"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__fillIiEvPT_S0_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4fillIiEvPT_S0_j
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z4fillIiEvPT_S0_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x16c], PT ; /* 0x00005b0002007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R5, c[0x0][0x168] ; /* 0x00005a0000057a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0003 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z4fillIiEvPT_S0_j,"axG",@progbits,_Z4fillIiEvPT_S0_j,comdat
.protected _Z4fillIiEvPT_S0_j
.globl _Z4fillIiEvPT_S0_j
.p2align 8
.type _Z4fillIiEvPT_S0_j,@function
_Z4fillIiEvPT_S0_j:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_mov_b32_e32 v2, s0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4fillIiEvPT_S0_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z4fillIiEvPT_S0_j,"axG",@progbits,_Z4fillIiEvPT_S0_j,comdat
.Lfunc_end0:
.size _Z4fillIiEvPT_S0_j, .Lfunc_end0-_Z4fillIiEvPT_S0_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4fillIiEvPT_S0_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4fillIiEvPT_S0_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00068afb_00000000-6_fill.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.section .text._Z4fillIiEvPT_S0_j,"axG",@progbits,_Z4fillIiEvPT_S0_j,comdat
.weak _Z4fillIiEvPT_S0_j
.type _Z4fillIiEvPT_S0_j, @function
_Z4fillIiEvPT_S0_j:
.LFB4364:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movl %esi, (%rsp)
movl %edx, 4(%rsp)
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4fillIiEvPT_S0_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4364:
.size _Z4fillIiEvPT_S0_j, .-_Z4fillIiEvPT_S0_j
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4037:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4037:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl main
.type main, @function
main:
.LFB4034:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $240, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $240, %esi
call cudaMalloc@PLT
movl $64, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L10:
movl $240, %edi
call malloc@PLT
movq %rax, %rbp
movl $2, %ecx
movl $240, %edx
movq 8(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movq %rbp, %rbx
addq $240, %rbp
leaq _ZSt4cout(%rip), %r13
leaq .LC0(%rip), %r12
.L11:
movl (%rbx), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, %rbp
jne .L11
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl $60, %edx
movl $1, %esi
movq 8(%rsp), %rdi
call _Z4fillIiEvPT_S0_j
jmp .L10
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4034:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z4fillIiEvPT_S0_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z4fillIiEvPT_S0_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4062:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "fill.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 112(%rsp), %rdi
movl $240, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $240, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 63(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $1, 12(%rsp)
movl $60, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4fillIiEvPT_S0_j, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
movl $240, %edi
callq malloc
movq %rax, %rbx
movq 16(%rsp), %rsi
movl $240, %edx
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq $60, %r14
jne .LBB0_3
# %bb.4:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_9
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_7
# %bb.6:
movzbl 67(%rbx), %eax
jmp .LBB0_8
.LBB0_7:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_9:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .text._Z19__device_stub__fillIiEvPT_S0_j,"axG",@progbits,_Z19__device_stub__fillIiEvPT_S0_j,comdat
.weak _Z19__device_stub__fillIiEvPT_S0_j # -- Begin function _Z19__device_stub__fillIiEvPT_S0_j
.p2align 4, 0x90
.type _Z19__device_stub__fillIiEvPT_S0_j,@function
_Z19__device_stub__fillIiEvPT_S0_j: # @_Z19__device_stub__fillIiEvPT_S0_j
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4fillIiEvPT_S0_j, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z19__device_stub__fillIiEvPT_S0_j, .Lfunc_end1-_Z19__device_stub__fillIiEvPT_S0_j
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4fillIiEvPT_S0_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4fillIiEvPT_S0_j,@object # @_Z4fillIiEvPT_S0_j
.section .rodata._Z4fillIiEvPT_S0_j,"aG",@progbits,_Z4fillIiEvPT_S0_j,comdat
.weak _Z4fillIiEvPT_S0_j
.p2align 3, 0x0
_Z4fillIiEvPT_S0_j:
.quad _Z19__device_stub__fillIiEvPT_S0_j
.size _Z4fillIiEvPT_S0_j, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4fillIiEvPT_S0_j"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__fillIiEvPT_S0_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4fillIiEvPT_S0_j
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
/*
This program launches a kernel on 256 GPU threads
Author: Martin Wass
*/
#include <stdio.h> // printf
// __global__ qualifier states the kernel is launched by host and ran on device
__global__ void greeting() {
int threadnum = blockIdx.x*blockDim.x + threadIdx.x;
printf("Hey world, from thread %d\n", threadnum);
}
int main() {
greeting<<<1, 256>>>(); // Launch kernel on 256 threads per block and 1 block
cudaDeviceSynchronize();
return 0;
}
|
code for sm_80
Function : _Z8greetingv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0070*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fca0007f1e0ff */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe400000e06ff */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*00a0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e260000000a00 */
/*00b0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0003e40000100800 */
/*00c0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*00d0*/ MOV R11, 0x140 ; /* 0x00000140000b7802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R20, 0xc0 ; /* 0x000000c000147802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*0100*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x002fe40000000f00 */
/*0110*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0120*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0130*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x001fea0003c00000 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
/*
This program launches a kernel on 256 GPU threads
Author: Martin Wass
*/
#include <stdio.h> // printf
// __global__ qualifier states the kernel is launched by host and ran on device
__global__ void greeting() {
int threadnum = blockIdx.x*blockDim.x + threadIdx.x;
printf("Hey world, from thread %d\n", threadnum);
}
int main() {
greeting<<<1, 256>>>(); // Launch kernel on 256 threads per block and 1 block
cudaDeviceSynchronize();
return 0;
}
|
.file "tmpxft_001521cf_00000000-6_exercise_1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8greetingvv
.type _Z26__device_stub__Z8greetingvv, @function
_Z26__device_stub__Z8greetingvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8greetingv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z8greetingvv, .-_Z26__device_stub__Z8greetingvv
.globl _Z8greetingv
.type _Z8greetingv, @function
_Z8greetingv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8greetingvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8greetingv, .-_Z8greetingv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z26__device_stub__Z8greetingvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8greetingv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8greetingv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/*
This program launches a kernel on 256 GPU threads
Author: Martin Wass
*/
#include <stdio.h> // printf
// __global__ qualifier states the kernel is launched by host and ran on device
__global__ void greeting() {
int threadnum = blockIdx.x*blockDim.x + threadIdx.x;
printf("Hey world, from thread %d\n", threadnum);
}
int main() {
greeting<<<1, 256>>>(); // Launch kernel on 256 threads per block and 1 block
cudaDeviceSynchronize();
return 0;
}
|
/*
This program launches a kernel on 256 GPU threads
Author: Martin Wass
*/
#include <hip/hip_runtime.h>
#include <stdio.h> // printf
// __global__ qualifier states the kernel is launched by host and ran on device
__global__ void greeting() {
int threadnum = blockIdx.x*blockDim.x + threadIdx.x;
printf("Hey world, from thread %d\n", threadnum);
}
int main() {
greeting<<<1, 256>>>(); // Launch kernel on 256 threads per block and 1 block
hipDeviceSynchronize();
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
/*
This program launches a kernel on 256 GPU threads
Author: Martin Wass
*/
#include <hip/hip_runtime.h>
#include <stdio.h> // printf
// __global__ qualifier states the kernel is launched by host and ran on device
__global__ void greeting() {
int threadnum = blockIdx.x*blockDim.x + threadIdx.x;
printf("Hey world, from thread %d\n", threadnum);
}
int main() {
greeting<<<1, 256>>>(); // Launch kernel on 256 threads per block and 1 block
hipDeviceSynchronize();
return 0;
}
|
.text
.file "exercise_1.hip"
.globl _Z23__device_stub__greetingv # -- Begin function _Z23__device_stub__greetingv
.p2align 4, 0x90
.type _Z23__device_stub__greetingv,@function
_Z23__device_stub__greetingv: # @_Z23__device_stub__greetingv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8greetingv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__greetingv, .Lfunc_end0-_Z23__device_stub__greetingv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8greetingv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8greetingv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8greetingv,@object # @_Z8greetingv
.section .rodata,"a",@progbits
.globl _Z8greetingv
.p2align 3, 0x0
_Z8greetingv:
.quad _Z23__device_stub__greetingv
.size _Z8greetingv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8greetingv"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__greetingv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8greetingv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001521cf_00000000-6_exercise_1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8greetingvv
.type _Z26__device_stub__Z8greetingvv, @function
_Z26__device_stub__Z8greetingvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8greetingv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z8greetingvv, .-_Z26__device_stub__Z8greetingvv
.globl _Z8greetingv
.type _Z8greetingv, @function
_Z8greetingv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8greetingvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8greetingv, .-_Z8greetingv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z26__device_stub__Z8greetingvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8greetingv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8greetingv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "exercise_1.hip"
.globl _Z23__device_stub__greetingv # -- Begin function _Z23__device_stub__greetingv
.p2align 4, 0x90
.type _Z23__device_stub__greetingv,@function
_Z23__device_stub__greetingv: # @_Z23__device_stub__greetingv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8greetingv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__greetingv, .Lfunc_end0-_Z23__device_stub__greetingv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8greetingv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8greetingv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8greetingv,@object # @_Z8greetingv
.section .rodata,"a",@progbits
.globl _Z8greetingv
.p2align 3, 0x0
_Z8greetingv:
.quad _Z23__device_stub__greetingv
.size _Z8greetingv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8greetingv"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__greetingv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8greetingv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <cuda.h>
//void Algorithm1();
void Algorithm4(int m, int n, int l);
//for gemm 4 algorithm
#define BLOCK_SIZE_x 16
#define BLOCK_SIZE_y 4
template<int block_size_x, int block_size_y>
__global__ void device_Matrix_multi(const double* const device_matrix_A,const double* const device_matrix_B,double* device_matrix_C,const int m,const int n,const int l)
{
const int threadid_x = threadIdx.x;
const int threadid_y = threadIdx.y;
const int blockid_x = blockIdx.x;
const int blockid_y = blockIdx.y;
__shared__ double matrix_B_shared[block_size_x][block_size_x+1];
double c[block_size_x];
for (int i = 0; i< block_size_x; i++)
{
c[i] = 0.0;
}
int idx_A = blockid_x*block_size_x*block_size_y + threadid_x + threadid_y*block_size_x;
int idx_B = threadid_x + (blockid_y*block_size_x + threadid_y)*n;
int idx_B_last = idx_B + n;
int col_A = 0;
do
{
for(int i = 0; i < block_size_x; i += block_size_y)
matrix_B_shared[threadid_x][threadid_y + i] = device_matrix_B[idx_B + i*n];
idx_B += block_size_x;
__syncthreads();
int i_bound = min(block_size_x, n - col_A);
for (int i = 0; i < i_bound; i++, idx_A+=m)
{
for (int j = 0; j < block_size_x; j++)
{
c[j] += device_matrix_A[idx_A]*matrix_B_shared[i][j];
}
}
col_A += block_size_x;
__syncthreads();
}while (idx_B < idx_B_last);
if (blockid_x*block_size_x*block_size_y + threadid_x + threadid_y*block_size_x < m)
{
int idx_D = blockid_x*block_size_x*block_size_y + (threadid_x + threadid_y*block_size_x) + blockid_y*block_size_x*m;
int i_bound = min(block_size_x, l - blockid_y*block_size_x);
for (int i = 0; i < i_bound; i++, idx_D += m)
{
device_matrix_C[idx_D] = c[i];
}
}
}
int main()
{
Algorithm4(32, 32, 32);
Algorithm4(64, 64, 64);
Algorithm4(128,128, 128);
Algorithm4(256, 256, 256);
Algorithm4(512, 512, 512);
Algorithm4(1024, 1024, 1024);
Algorithm4(2048, 2048, 2048);
Algorithm4(4096, 4096, 4096);
}
void Algorithm4(int m, int n, int l) {
printf("inside function");
double* matrix_A;
double* matrix_B;
double* matrix_C;
double *device_matrix_A;
double *device_matrix_B;
double *device_matrix_C;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float milliseconds = 0;
// Allocate the device memory
matrix_A = (double*)malloc( m*n* sizeof(double));
matrix_B = (double*)malloc( m*l* sizeof(double));
matrix_C = (double*)malloc( m*l*sizeof(double));
cudaMalloc(&device_matrix_A, m*n*sizeof(double));
cudaMalloc(&device_matrix_B, n*l*sizeof(double));
cudaMalloc(&device_matrix_C, m*l*sizeof(double));
for(int i = 0; i < m; i++)
{
for(int j = 0; j <n; j++){
matrix_A[i *n + j] = rand()%10;
matrix_B[i *n + j] = rand()%10;
matrix_C[i *n + j] = 0;
}
}
// Copy data from the host memory to the device memory
cudaMemcpy(device_matrix_A, matrix_A, m*n*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(device_matrix_B, matrix_B, n*l*sizeof(double), cudaMemcpyHostToDevice);
dim3 nthreads(0, 0);
dim3 nblocks(0, 0); // Launch the kernel
nthreads.x = BLOCK_SIZE_x;
nthreads.y = BLOCK_SIZE_y;
nblocks.x = (m + nthreads.x*nthreads.y - 1)/(nthreads.x*nthreads.y);
nblocks.y = (l + nthreads.x - 1)/nthreads.x;
cudaEventRecord(start);
printf("nuumber of blocks in x = %d\n", nblocks.x);
printf("nuumber of blocks in y = %d\n", nblocks.y);
printf("number of threads in x = %d\n", nthreads.x);
printf("number of threads in y =%d\n", nthreads.y);
printf("total threads = %d", nblocks.x*nblocks.y*nthreads.x*nthreads.y);
device_Matrix_multi<BLOCK_SIZE_x, BLOCK_SIZE_y> <<<nblocks, nthreads>>> ( device_matrix_A,device_matrix_B, device_matrix_C,m,n,l
);
// Copy data from the device memory to the host memory
cudaMemcpy(matrix_C, device_matrix_C, m*l*sizeof(double), cudaMemcpyDeviceToHost);
cudaEventRecord(stop);
for(int i=0; i<m;i++){
for(int j =0; j<n; j++){
}
}
cudaEventElapsedTime(&milliseconds, start, stop);
printf("elaspsed = %f ms\n\n\n", milliseconds);
// Free the device memory
cudaFree(device_matrix_A);
cudaFree(device_matrix_B);
cudaFree(device_matrix_C);
free(matrix_A);
free(matrix_B);
free(matrix_C);
}
|
code for sm_80
Function : _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0020*/ ULDC UR7, c[0x0][0x17c] ; /* 0x00005f0000077ab9 */
/* 0x000fe20000000800 */
/*0030*/ CS2R R50, SRZ ; /* 0x0000000000327805 */
/* 0x000fe2000001ff00 */
/*0040*/ CS2R R52, SRZ ; /* 0x0000000000347805 */
/* 0x000fe2000001ff00 */
/*0050*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002600 */
/*0060*/ CS2R R56, SRZ ; /* 0x0000000000387805 */
/* 0x000fe2000001ff00 */
/*0070*/ CS2R R48, SRZ ; /* 0x0000000000307805 */
/* 0x000fe2000001ff00 */
/*0080*/ CS2R R36, SRZ ; /* 0x0000000000247805 */
/* 0x000fe2000001ff00 */
/*0090*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*00a0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*00b0*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe2000001ff00 */
/*00c0*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fe2000001ff00 */
/*00d0*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e620000002100 */
/*00e0*/ CS2R R14, SRZ ; /* 0x00000000000e7805 */
/* 0x000fe2000001ff00 */
/*00f0*/ CS2R R38, SRZ ; /* 0x0000000000267805 */
/* 0x000fe2000001ff00 */
/*0100*/ CS2R R54, SRZ ; /* 0x0000000000367805 */
/* 0x000fe2000001ff00 */
/*0110*/ CS2R R46, SRZ ; /* 0x00000000002e7805 */
/* 0x000fe2000001ff00 */
/*0120*/ CS2R R44, SRZ ; /* 0x00000000002c7805 */
/* 0x000fe2000001ff00 */
/*0130*/ CS2R R42, SRZ ; /* 0x00000000002a7805 */
/* 0x000fe2000001ff00 */
/*0140*/ CS2R R40, SRZ ; /* 0x0000000000287805 */
/* 0x000fe2000001ff00 */
/*0150*/ CS2R R60, SRZ ; /* 0x00000000003c7805 */
/* 0x000fe2000001ff00 */
/*0160*/ ULOP3.LUT UR10, URZ, UR7, URZ, 0x33, !UPT ; /* 0x000000073f0a7292 */
/* 0x000fc4000f8e333f */
/*0170*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fe40000000a00 */
/*0180*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0190*/ USHF.L.U32 UR7, UR7, 0x2, URZ ; /* 0x0000000207077899 */
/* 0x000fe2000800063f */
/*01a0*/ LEA R3, R2, R5, 0x4 ; /* 0x0000000502037211 */
/* 0x001fe200078e20ff */
/*01b0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*01c0*/ IMAD R0, R0, 0x40, R4 ; /* 0x0000004000007824 */
/* 0x002fc600078e0204 */
/*01d0*/ IMAD R3, R3, c[0x0][0x17c], R4 ; /* 0x00005f0003037a24 */
/* 0x000fe400078e0204 */
/*01e0*/ IMAD R0, R5, 0x10, R0 ; /* 0x0000001005007824 */
/* 0x000fe400078e0200 */
/*01f0*/ IMAD R2, R4, 0x11, R5 ; /* 0x0000001104027824 */
/* 0x000fe200078e0205 */
/*0200*/ IADD3 R6, R3, c[0x0][0x17c], RZ ; /* 0x00005f0003067a10 */
/* 0x000fe40007ffe0ff */
/*0210*/ MOV R4, R0 ; /* 0x0000000000047202 */
/* 0x000fe40000000f00 */
/*0220*/ MOV R20, UR7 ; /* 0x0000000700147c02 */
/* 0x009fe20008000f00 */
/*0230*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe400078e00ff */
/*0240*/ IMAD.U32 R19, RZ, RZ, UR7 ; /* 0x00000007ff137e24 */
/* 0x000fe2000f8e00ff */
/*0250*/ IADD3 R20, R20, UR7, R3 ; /* 0x0000000714147c10 */
/* 0x000fe2000fffe003 */
/*0260*/ IMAD.WIDE R16, R3, R5, c[0x0][0x168] ; /* 0x00005a0003107625 */
/* 0x000fc600078e0205 */
/*0270*/ IADD3 R22, R20.reuse, UR7, RZ ; /* 0x0000000714167c10 */
/* 0x040fe2000fffe0ff */
/*0280*/ IMAD.WIDE R20, R20, R5, c[0x0][0x168] ; /* 0x00005a0014147625 */
/* 0x000fc800078e0205 */
/*0290*/ IMAD.WIDE R18, R19, 0x8, R16 ; /* 0x0000000813127825 */
/* 0x000fe400078e0210 */
/*02a0*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000c10107981 */
/* 0x000ea4000c1e1b00 */
/*02b0*/ IMAD.WIDE R22, R22, R5, c[0x0][0x168] ; /* 0x00005a0016167625 */
/* 0x000fe400078e0205 */
/*02c0*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000c12127981 */
/* 0x000ee8000c1e1b00 */
/*02d0*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000c14147981 */
/* 0x000f28000c1e1b00 */
/*02e0*/ LDG.E.64 R22, [R22.64] ; /* 0x0000000c16167981 */
/* 0x000f62000c1e1b00 */
/*02f0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0300*/ ULDC UR6, c[0x0][0x17c] ; /* 0x00005f0000067ab9 */
/* 0x000fc40000000800 */
/*0310*/ UISETP.GE.AND UP0, UPT, UR5, UR6, UPT ; /* 0x000000060500728c */
/* 0x000fcc000bf06270 */
/*0320*/ PLOP3.LUT P1, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f2f008 */
/*0330*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc80007ffe0ff */
/*0340*/ ISETP.GE.AND P0, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x000fe20003f06270 */
/*0350*/ STS.64 [R2.X8], R16 ; /* 0x0000001002007388 */
/* 0x0041e80000008a00 */
/*0360*/ STS.64 [R2.X8+0x20], R18 ; /* 0x0000201202007388 */
/* 0x0081e80000008a00 */
/*0370*/ STS.64 [R2.X8+0x40], R20 ; /* 0x0000401402007388 */
/* 0x0101e80000008a00 */
/*0380*/ STS.64 [R2.X8+0x60], R22 ; /* 0x0000601602007388 */
/* 0x0201e80000008a00 */
/*0390*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03a0*/ @P1 BRA 0xa20 ; /* 0x0000067000001947 */
/* 0x000fea0003800000 */
/*03b0*/ UIADD3 UR6, UR10, UR4, URZ ; /* 0x000000040a067290 */
/* 0x000fc8000fffe03f */
/*03c0*/ UISETP.LT.AND UP0, UPT, UR6, -0x11, UPT ; /* 0xffffffef0600788c */
/* 0x000fc8000bf01270 */
/*03d0*/ USEL UR6, UR6, 0xffffffef, !UP0 ; /* 0xffffffef06067887 */
/* 0x000fc8000c000000 */
/*03e0*/ ULOP3.LUT UR8, URZ, UR6, URZ, 0x33, !UPT ; /* 0x000000063f087292 */
/* 0x000fc8000f8e333f */
/*03f0*/ UISETP.LT.AND UP0, UPT, UR8, 0x1, UPT ; /* 0x000000010800788c */
/* 0x000fc8000bf01270 */
/*0400*/ USEL UR8, UR8, 0x1, !UP0 ; /* 0x0000000108087887 */
/* 0x000fe4000c000000 */
/*0410*/ UISETP.GT.AND UP0, UPT, UR6, -0x3, UPT ; /* 0xfffffffd0600788c */
/* 0x000fe4000bf04270 */
/*0420*/ ULOP3.LUT UR9, UR8, 0x1, URZ, 0xc0, !UPT ; /* 0x0000000108097892 */
/* 0x000fe4000f8ec03f */
/*0430*/ UMOV UR6, URZ ; /* 0x0000003f00067c82 */
/* 0x000fe40008000000 */
/*0440*/ PLOP3.LUT P2, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f4f008 */
/*0450*/ ISETP.NE.AND P1, PT, RZ, UR9, PT ; /* 0x00000009ff007c0c */
/* 0x000fd6000bf25270 */
/*0460*/ @P2 BRA 0x850 ; /* 0x000003e000002947 */
/* 0x000fea0003800000 */
/*0470*/ UIADD3 UR8, UR8, -UR9, URZ ; /* 0x8000000908087290 */
/* 0x000fe4000fffe03f */
/*0480*/ UMOV UR6, URZ ; /* 0x0000003f00067c82 */
/* 0x000fe40008000000 */
/*0490*/ IMAD.WIDE R62, R4, R5, c[0x0][0x160] ; /* 0x00005800043e7625 */
/* 0x004fca00078e0205 */
/*04a0*/ LDG.E.64 R58, [R62.64] ; /* 0x0000000c3e3a7981 */
/* 0x000ea2000c1e1b00 */
/*04b0*/ IMAD.WIDE R32, R5, c[0x0][0x178], R62 ; /* 0x00005e0005207a25 */
/* 0x000fcc00078e023e */
/*04c0*/ LDG.E.64 R32, [R32.64] ; /* 0x0000000c20207981 */
/* 0x000ee2000c1e1b00 */
/*04d0*/ UIMAD UR9, UR6, 0x88, URZ ; /* 0x00000088060978a4 */
/* 0x000fe2000f8e023f */
/*04e0*/ MOV R7, c[0x0][0x178] ; /* 0x00005e0000077a02 */
/* 0x000fe20000000f00 */
/*04f0*/ UIADD3 UR8, UR8, -0x2, URZ ; /* 0xfffffffe08087890 */
/* 0x000fe4000fffe03f */
/*0500*/ UIADD3 UR6, UR6, 0x2, URZ ; /* 0x0000000206067890 */
/* 0x000fe4000fffe03f */
/*0510*/ IMAD R4, R7, 0x2, R4 ; /* 0x0000000207047824 */
/* 0x000fe400078e0204 */
/*0520*/ ISETP.NE.AND P2, PT, RZ, UR8, PT ; /* 0x00000008ff007c0c */
/* 0x000fe2000bf45270 */
/*0530*/ LDS.128 R20, [UR9] ; /* 0x00000009ff147984 */
/* 0x001ea80008000c00 */
/*0540*/ LDS.128 R24, [UR9+0x10] ; /* 0x00001009ff187984 */
/* 0x000e280008000c00 */
/*0550*/ LDS.128 R28, [UR9+0x20] ; /* 0x00002009ff1c7984 */
/* 0x000e680008000c00 */
/*0560*/ LDS.128 R16, [UR9+0x30] ; /* 0x00003009ff107984 */
/* 0x000f220008000c00 */
/*0570*/ DFMA R34, R20, R58, R60 ; /* 0x0000003a1422722b */
/* 0x004fc8000000003c */
/*0580*/ DFMA R60, R58.reuse, R22, R40 ; /* 0x000000163a3c722b */
/* 0x0404e40000000028 */
/*0590*/ LDS.128 R20, [UR9+0x40] ; /* 0x00004009ff147984 */
/* 0x004ea40008000c00 */
/*05a0*/ DFMA R66, R58.reuse, R24, R42 ; /* 0x000000183a42722b */
/* 0x041164000000002a */
/*05b0*/ LDS.128 R40, [UR9+0x90] ; /* 0x00009009ff287984 */
/* 0x001fe40008000c00 */
/*05c0*/ DFMA R68, R58.reuse, R26, R44 ; /* 0x0000001a3a44722b */
/* 0x040024000000002c */
/*05d0*/ LDS.128 R24, [UR9+0x50] ; /* 0x00005009ff187984 */
/* 0x001e240008000c00 */
/*05e0*/ DFMA R72, R58, R28, R46 ; /* 0x0000001c3a48722b */
/* 0x002204000000002e */
/*05f0*/ LDS.128 R44, [UR9+0xa0] ; /* 0x0000a009ff2c7984 */
/* 0x002fe40008000c00 */
/*0600*/ DFMA R54, R58.reuse, R30, R54 ; /* 0x0000001e3a36722b */
/* 0x0403e40000000036 */
/*0610*/ LDS.128 R28, [UR9+0x60] ; /* 0x00006009ff1c7984 */
/* 0x002e640008000c00 */
/*0620*/ DFMA R64, R58, R16, R38 ; /* 0x000000103a40722b */
/* 0x010fc80000000026 */
/*0630*/ DFMA R14, R58.reuse, R18, R14 ; /* 0x000000123a0e722b */
/* 0x0409e4000000000e */
/*0640*/ LDS.128 R16, [UR9+0x70] ; /* 0x00007009ff107984 */
/* 0x010f240008000c00 */
/*0650*/ DFMA R62, R58, R20, R10 ; /* 0x000000143a3e722b */
/* 0x004fc8000000000a */
/*0660*/ DFMA R12, R58.reuse, R22, R12 ; /* 0x000000163a0c722b */
/* 0x0405e4000000000c */
/*0670*/ LDS.128 R20, [UR9+0xf0] ; /* 0x0000f009ff147984 */
/* 0x004ea40008000c00 */
/*0680*/ DFMA R70, R58.reuse, R24, R8 ; /* 0x000000183a46722b */
/* 0x0411e40000000008 */
/*0690*/ LDS.128 R8, [UR9+0xc0] ; /* 0x0000c009ff087984 */
/* 0x001e240008000c00 */
/*06a0*/ DFMA R74, R58.reuse, R26, R36 ; /* 0x0000001a3a4a722b */
/* 0x0407e40000000024 */
/*06b0*/ LDS.128 R36, [UR9+0xb0] ; /* 0x0000b009ff247984 */
/* 0x008ee40008000c00 */
/*06c0*/ DFMA R28, R58, R28, R48 ; /* 0x0000001c3a1c722b */
/* 0x002fc40000000030 */
/*06d0*/ LDS.128 R24, [UR9+0xd0] ; /* 0x0000d009ff187984 */
/* 0x000e640008000c00 */
/*06e0*/ DFMA R30, R58, R30, R56 ; /* 0x0000001e3a1e722b */
/* 0x000e880000000038 */
/*06f0*/ DFMA R52, R58, R16, R52 ; /* 0x000000103a34722b */
/* 0x010f080000000034 */
/*0700*/ DFMA R50, R58, R18, R50 ; /* 0x000000123a32722b */
/* 0x0008240000000032 */
/*0710*/ LDS.128 R16, [UR9+0xe0] ; /* 0x0000e009ff107984 */
/* 0x010f240008000c00 */
/*0720*/ DFMA R40, R32.reuse, R40, R60 ; /* 0x000000282028722b */
/* 0x040a24000000003c */
/*0730*/ LDS.64 R60, [UR9+0x88] ; /* 0x00008809ff3c7984 */
/* 0x020f640008000a00 */
/*0740*/ DFMA R42, R32.reuse, R42, R66 ; /* 0x0000002a202a722b */
/* 0x0400240000000042 */
/*0750*/ LDS.64 R58, [UR9+0x100] ; /* 0x00010009ff3a7984 */
/* 0x000f640008000a00 */
/*0760*/ DFMA R44, R32, R44, R68 ; /* 0x0000002c202c722b */
/* 0x0000080000000044 */
/*0770*/ DFMA R46, R32, R46, R72 ; /* 0x0000002e202e722b */
/* 0x0000080000000048 */
/*0780*/ DFMA R56, R32, R20, R30 ; /* 0x000000142038722b */
/* 0x004408000000001e */
/*0790*/ DFMA R14, R32, R8, R14 ; /* 0x00000008200e722b */
/* 0x001408000000000e */
/*07a0*/ DFMA R54, R32, R36, R54 ; /* 0x000000242036722b */
/* 0x0084c80000000036 */
/*07b0*/ DFMA R38, R32, R38, R64 ; /* 0x000000262026722b */
/* 0x0004080000000040 */
/*07c0*/ DFMA R10, R32, R10, R62 ; /* 0x0000000a200a722b */
/* 0x000408000000003e */
/*07d0*/ DFMA R12, R32, R24, R12 ; /* 0x00000018200c722b */
/* 0x002448000000000c */
/*07e0*/ DFMA R8, R32, R26, R70 ; /* 0x0000001a2008722b */
/* 0x0004080000000046 */
/*07f0*/ DFMA R36, R32, R16, R74 ; /* 0x000000102024722b */
/* 0x010508000000004a */
/*0800*/ DFMA R48, R32, R18, R28 ; /* 0x000000122030722b */
/* 0x000408000000001c */
/*0810*/ DFMA R52, R32, R22, R52 ; /* 0x000000162034722b */
/* 0x0004080000000034 */
/*0820*/ DFMA R60, R60, R32, R34 ; /* 0x000000203c3c722b */
/* 0x0204080000000022 */
/*0830*/ DFMA R50, R32, R58, R50 ; /* 0x0000003a2032722b */
/* 0x0004220000000032 */
/*0840*/ @P2 BRA 0x490 ; /* 0xfffffc4000002947 */
/* 0x01afea000383ffff */
/*0850*/ @!P1 BRA 0xa20 ; /* 0x000001c000009947 */
/* 0x000fea0003800000 */
/*0860*/ IMAD.WIDE R58, R4, R5, c[0x0][0x160] ; /* 0x00005800043a7625 */
/* 0x004fcc00078e0205 */
/*0870*/ LDG.E.64 R58, [R58.64] ; /* 0x0000000c3a3a7981 */
/* 0x000ea2000c1e1b00 */
/*0880*/ UIMAD UR6, UR6, 0x88, URZ ; /* 0x00000088060678a4 */
/* 0x000fe2000f8e023f */
/*0890*/ IADD3 R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a10 */
/* 0x000fd00007ffe0ff */
/*08a0*/ LDS.128 R20, [UR6] ; /* 0x00000006ff147984 */
/* 0x001ea80008000c00 */
/*08b0*/ LDS.128 R24, [UR6+0x10] ; /* 0x00001006ff187984 */
/* 0x000e280008000c00 */
/*08c0*/ LDS.128 R28, [UR6+0x20] ; /* 0x00002006ff1c7984 */
/* 0x000e680008000c00 */
/*08d0*/ LDS.128 R16, [UR6+0x30] ; /* 0x00003006ff107984 */
/* 0x000ee80008000c00 */
/*08e0*/ LDS.128 R32, [UR6+0x70] ; /* 0x00007006ff207984 */
/* 0x000f220008000c00 */
/*08f0*/ DFMA R60, R20, R58, R60 ; /* 0x0000003a143c722b */
/* 0x004e88000000003c */
/*0900*/ DFMA R40, R58.reuse, R22, R40 ; /* 0x000000163a28722b */
/* 0x040a240000000028 */
/*0910*/ LDS.128 R20, [UR6+0x40] ; /* 0x00004006ff147984 */
/* 0x020f640008000c00 */
/*0920*/ DFMA R42, R58, R24, R42 ; /* 0x000000183a2a722b */
/* 0x001e08000000002a */
/*0930*/ DFMA R44, R58.reuse, R26, R44 ; /* 0x0000001a3a2c722b */
/* 0x040024000000002c */
/*0940*/ LDS.128 R24, [UR6+0x50] ; /* 0x00005006ff187984 */
/* 0x001e240008000c00 */
/*0950*/ DFMA R46, R58, R28, R46 ; /* 0x0000001c3a2e722b */
/* 0x002e48000000002e */
/*0960*/ DFMA R54, R58.reuse, R30, R54 ; /* 0x0000001e3a36722b */
/* 0x0402240000000036 */
/*0970*/ LDS.128 R28, [UR6+0x60] ; /* 0x00006006ff1c7984 */
/* 0x002e640008000c00 */
/*0980*/ DFMA R38, R58, R16, R38 ; /* 0x000000103a26722b */
/* 0x0086080000000026 */
/*0990*/ DFMA R14, R58, R18, R14 ; /* 0x000000123a0e722b */
/* 0x000608000000000e */
/*09a0*/ DFMA R52, R58, R32, R52 ; /* 0x000000203a34722b */
/* 0x0107080000000034 */
/*09b0*/ DFMA R50, R58, R34, R50 ; /* 0x000000223a32722b */
/* 0x0006080000000032 */
/*09c0*/ DFMA R10, R58, R20, R10 ; /* 0x000000143a0a722b */
/* 0x020608000000000a */
/*09d0*/ DFMA R12, R58, R22, R12 ; /* 0x000000163a0c722b */
/* 0x000608000000000c */
/*09e0*/ DFMA R8, R58, R24, R8 ; /* 0x000000183a08722b */
/* 0x0016080000000008 */
/*09f0*/ DFMA R36, R58, R26, R36 ; /* 0x0000001a3a24722b */
/* 0x0006080000000024 */
/*0a00*/ DFMA R48, R58, R28, R48 ; /* 0x0000001c3a30722b */
/* 0x0026480000000030 */
/*0a10*/ DFMA R56, R58, R30, R56 ; /* 0x0000001e3a38722b */
/* 0x0006080000000038 */
/*0a20*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x016fe20000010000 */
/*0a30*/ UIADD3 UR5, UR5, 0x10, URZ ; /* 0x0000001005057890 */
/* 0x000fe4000fffe03f */
/*0a40*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fc6000fffe03f */
/*0a50*/ @!P0 BRA 0x220 ; /* 0xfffff7c000008947 */
/* 0x000fea000383ffff */
/*0a60*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0a70*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0a80*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e640000002600 */
/*0a90*/ SHF.L.U32 R3, R3, 0x4, RZ ; /* 0x0000000403037819 */
/* 0x002fc800000006ff */
/*0aa0*/ IADD3 R2, -R3, c[0x0][0x180], RZ ; /* 0x0000600003027a10 */
/* 0x001fc80007ffe1ff */
/*0ab0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*0ac0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0ad0*/ IMNMX R2, R2, 0x10, PT ; /* 0x0000001002027817 */
/* 0x000fe20003800200 */
/*0ae0*/ IMAD R6, R3, c[0x0][0x178], R0 ; /* 0x00005e0003067a24 */
/* 0x000fc600078e0200 */
/*0af0*/ ISETP.GE.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fe20003f06270 */
/*0b00*/ IMAD.WIDE R6, R6, R5, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fca00078e0205 */
/*0b10*/ STG.E.64 [R6.64], R60 ; /* 0x0000003c06007986 */
/* 0x0001ee000c101b0c */
/*0b20*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0b30*/ ISETP.NE.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fe20003f05270 */
/*0b40*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0b50*/ STG.E.64 [R6.64], R40 ; /* 0x0000002806007986 */
/* 0x0001ee000c101b0c */
/*0b60*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0b70*/ ISETP.GE.AND P0, PT, R2, 0x4, PT ; /* 0x000000040200780c */
/* 0x000fe20003f06270 */
/*0b80*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0b90*/ STG.E.64 [R6.64], R42 ; /* 0x0000002a06007986 */
/* 0x0001ee000c101b0c */
/*0ba0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0bb0*/ ISETP.NE.AND P0, PT, R2, 0x4, PT ; /* 0x000000040200780c */
/* 0x000fe20003f05270 */
/*0bc0*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0bd0*/ STG.E.64 [R6.64], R44 ; /* 0x0000002c06007986 */
/* 0x0001ee000c101b0c */
/*0be0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0bf0*/ ISETP.GE.AND P0, PT, R2, 0x6, PT ; /* 0x000000060200780c */
/* 0x000fe20003f06270 */
/*0c00*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0c10*/ STG.E.64 [R6.64], R46 ; /* 0x0000002e06007986 */
/* 0x0001ee000c101b0c */
/*0c20*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0c30*/ ISETP.NE.AND P0, PT, R2, 0x6, PT ; /* 0x000000060200780c */
/* 0x000fe20003f05270 */
/*0c40*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0c50*/ STG.E.64 [R6.64], R54 ; /* 0x0000003606007986 */
/* 0x0001ee000c101b0c */
/*0c60*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0c70*/ ISETP.GE.AND P0, PT, R2, 0x8, PT ; /* 0x000000080200780c */
/* 0x000fe20003f06270 */
/*0c80*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0c90*/ STG.E.64 [R6.64], R38 ; /* 0x0000002606007986 */
/* 0x0001ee000c101b0c */
/*0ca0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0cb0*/ ISETP.NE.AND P0, PT, R2, 0x8, PT ; /* 0x000000080200780c */
/* 0x000fe20003f05270 */
/*0cc0*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0cd0*/ STG.E.64 [R6.64], R14 ; /* 0x0000000e06007986 */
/* 0x0001ee000c101b0c */
/*0ce0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0cf0*/ ISETP.GE.AND P0, PT, R2, 0xa, PT ; /* 0x0000000a0200780c */
/* 0x000fe20003f06270 */
/*0d00*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0d10*/ STG.E.64 [R6.64], R10 ; /* 0x0000000a06007986 */
/* 0x0001ee000c101b0c */
/*0d20*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0d30*/ ISETP.NE.AND P0, PT, R2, 0xa, PT ; /* 0x0000000a0200780c */
/* 0x000fe20003f05270 */
/*0d40*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0d50*/ STG.E.64 [R6.64], R12 ; /* 0x0000000c06007986 */
/* 0x0001ee000c101b0c */
/*0d60*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0d70*/ ISETP.GE.AND P0, PT, R2, 0xc, PT ; /* 0x0000000c0200780c */
/* 0x000fe20003f06270 */
/*0d80*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0d90*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x0001ee000c101b0c */
/*0da0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0db0*/ ISETP.NE.AND P0, PT, R2, 0xc, PT ; /* 0x0000000c0200780c */
/* 0x000fe20003f05270 */
/*0dc0*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0dd0*/ STG.E.64 [R6.64], R36 ; /* 0x0000002406007986 */
/* 0x0001ee000c101b0c */
/*0de0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0df0*/ ISETP.GE.AND P0, PT, R2, 0xe, PT ; /* 0x0000000e0200780c */
/* 0x000fe20003f06270 */
/*0e00*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0e10*/ STG.E.64 [R6.64], R48 ; /* 0x0000003006007986 */
/* 0x0001ee000c101b0c */
/*0e20*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0e30*/ ISETP.NE.AND P0, PT, R2, 0xe, PT ; /* 0x0000000e0200780c */
/* 0x000fe20003f05270 */
/*0e40*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0e50*/ STG.E.64 [R6.64], R56 ; /* 0x0000003806007986 */
/* 0x0001ee000c101b0c */
/*0e60*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0e70*/ ISETP.GE.AND P0, PT, R2, 0x10, PT ; /* 0x000000100200780c */
/* 0x000fe20003f06270 */
/*0e80*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0e90*/ STG.E.64 [R6.64], R52 ; /* 0x0000003406007986 */
/* 0x0001ee000c101b0c */
/*0ea0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0eb0*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0ec0*/ STG.E.64 [R6.64], R50 ; /* 0x0000003206007986 */
/* 0x000fe2000c101b0c */
/*0ed0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ee0*/ BRA 0xee0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <cuda.h>
//void Algorithm1();
void Algorithm4(int m, int n, int l);
//for gemm 4 algorithm
#define BLOCK_SIZE_x 16
#define BLOCK_SIZE_y 4
template<int block_size_x, int block_size_y>
__global__ void device_Matrix_multi(const double* const device_matrix_A,const double* const device_matrix_B,double* device_matrix_C,const int m,const int n,const int l)
{
const int threadid_x = threadIdx.x;
const int threadid_y = threadIdx.y;
const int blockid_x = blockIdx.x;
const int blockid_y = blockIdx.y;
__shared__ double matrix_B_shared[block_size_x][block_size_x+1];
double c[block_size_x];
for (int i = 0; i< block_size_x; i++)
{
c[i] = 0.0;
}
int idx_A = blockid_x*block_size_x*block_size_y + threadid_x + threadid_y*block_size_x;
int idx_B = threadid_x + (blockid_y*block_size_x + threadid_y)*n;
int idx_B_last = idx_B + n;
int col_A = 0;
do
{
for(int i = 0; i < block_size_x; i += block_size_y)
matrix_B_shared[threadid_x][threadid_y + i] = device_matrix_B[idx_B + i*n];
idx_B += block_size_x;
__syncthreads();
int i_bound = min(block_size_x, n - col_A);
for (int i = 0; i < i_bound; i++, idx_A+=m)
{
for (int j = 0; j < block_size_x; j++)
{
c[j] += device_matrix_A[idx_A]*matrix_B_shared[i][j];
}
}
col_A += block_size_x;
__syncthreads();
}while (idx_B < idx_B_last);
if (blockid_x*block_size_x*block_size_y + threadid_x + threadid_y*block_size_x < m)
{
int idx_D = blockid_x*block_size_x*block_size_y + (threadid_x + threadid_y*block_size_x) + blockid_y*block_size_x*m;
int i_bound = min(block_size_x, l - blockid_y*block_size_x);
for (int i = 0; i < i_bound; i++, idx_D += m)
{
device_matrix_C[idx_D] = c[i];
}
}
}
int main()
{
Algorithm4(32, 32, 32);
Algorithm4(64, 64, 64);
Algorithm4(128,128, 128);
Algorithm4(256, 256, 256);
Algorithm4(512, 512, 512);
Algorithm4(1024, 1024, 1024);
Algorithm4(2048, 2048, 2048);
Algorithm4(4096, 4096, 4096);
}
void Algorithm4(int m, int n, int l) {
printf("inside function");
double* matrix_A;
double* matrix_B;
double* matrix_C;
double *device_matrix_A;
double *device_matrix_B;
double *device_matrix_C;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float milliseconds = 0;
// Allocate the device memory
matrix_A = (double*)malloc( m*n* sizeof(double));
matrix_B = (double*)malloc( m*l* sizeof(double));
matrix_C = (double*)malloc( m*l*sizeof(double));
cudaMalloc(&device_matrix_A, m*n*sizeof(double));
cudaMalloc(&device_matrix_B, n*l*sizeof(double));
cudaMalloc(&device_matrix_C, m*l*sizeof(double));
for(int i = 0; i < m; i++)
{
for(int j = 0; j <n; j++){
matrix_A[i *n + j] = rand()%10;
matrix_B[i *n + j] = rand()%10;
matrix_C[i *n + j] = 0;
}
}
// Copy data from the host memory to the device memory
cudaMemcpy(device_matrix_A, matrix_A, m*n*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(device_matrix_B, matrix_B, n*l*sizeof(double), cudaMemcpyHostToDevice);
dim3 nthreads(0, 0);
dim3 nblocks(0, 0); // Launch the kernel
nthreads.x = BLOCK_SIZE_x;
nthreads.y = BLOCK_SIZE_y;
nblocks.x = (m + nthreads.x*nthreads.y - 1)/(nthreads.x*nthreads.y);
nblocks.y = (l + nthreads.x - 1)/nthreads.x;
cudaEventRecord(start);
printf("nuumber of blocks in x = %d\n", nblocks.x);
printf("nuumber of blocks in y = %d\n", nblocks.y);
printf("number of threads in x = %d\n", nthreads.x);
printf("number of threads in y =%d\n", nthreads.y);
printf("total threads = %d", nblocks.x*nblocks.y*nthreads.x*nthreads.y);
device_Matrix_multi<BLOCK_SIZE_x, BLOCK_SIZE_y> <<<nblocks, nthreads>>> ( device_matrix_A,device_matrix_B, device_matrix_C,m,n,l
);
// Copy data from the device memory to the host memory
cudaMemcpy(matrix_C, device_matrix_C, m*l*sizeof(double), cudaMemcpyDeviceToHost);
cudaEventRecord(stop);
for(int i=0; i<m;i++){
for(int j =0; j<n; j++){
}
}
cudaEventElapsedTime(&milliseconds, start, stop);
printf("elaspsed = %f ms\n\n\n", milliseconds);
// Free the device memory
cudaFree(device_matrix_A);
cudaFree(device_matrix_B);
cudaFree(device_matrix_C);
free(matrix_A);
free(matrix_B);
free(matrix_C);
}
|
.file "tmpxft_001362ad_00000000-6_algorithm4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL60__device_stub__Z19device_Matrix_multiILi16ELi4EEvPKdS1_PdiiiPKdS0_Pdiii, @function
_ZL60__device_stub__Z19device_Matrix_multiILi16ELi4EEvPKdS1_PdiiiPKdS0_Pdiii:
.LFB2085:
.cfi_startproc
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _ZL60__device_stub__Z19device_Matrix_multiILi16ELi4EEvPKdS1_PdiiiPKdS0_Pdiii, .-_ZL60__device_stub__Z19device_Matrix_multiILi16ELi4EEvPKdS1_PdiiiPKdS0_Pdiii
.section .text._Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii,"axG",@progbits,_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii,comdat
.weak _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.type _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii, @function
_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii:
.LFB2135:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL60__device_stub__Z19device_Matrix_multiILi16ELi4EEvPKdS1_PdiiiPKdS0_Pdiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2135:
.size _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii, .-_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "inside function"
.LC3:
.string "nuumber of blocks in x = %d\n"
.LC4:
.string "nuumber of blocks in y = %d\n"
.LC5:
.string "number of threads in x = %d\n"
.LC6:
.string "number of threads in y =%d\n"
.LC7:
.string "total threads = %d"
.LC8:
.string "elaspsed = %f ms\n\n\n"
.text
.globl _Z10Algorithm4iii
.type _Z10Algorithm4iii, @function
_Z10Algorithm4iii:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movl %edi, %r14d
movl %esi, %r12d
movl %edx, %ebp
movl %edx, 28(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
leaq 88(%rsp), %rdi
call cudaEventCreate@PLT
movl $0x00000000, 52(%rsp)
movl %r14d, %eax
imull %r12d, %eax
cltq
leaq 0(,%rax,8), %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
movl %r14d, 24(%rsp)
movl %r14d, %eax
imull %ebp, %eax
cltq
leaq 0(,%rax,8), %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r14
movq %r13, 16(%rsp)
movq %r13, %rdi
call malloc@PLT
movq %rax, %r13
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
imull %r12d, %ebp
movl %ebp, %eax
cltq
leaq 0(,%rax,8), %rbp
leaq 64(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq 16(%rsp), %rsi
call cudaMalloc@PLT
cmpl $0, 24(%rsp)
jle .L12
movl $0, %ecx
movl $0, %edx
movslq %r12d, %rax
movq %rax, 8(%rsp)
movq %rbx, 32(%rsp)
movq %rbp, 40(%rsp)
movl %r12d, %esi
movl %edx, %r12d
jmp .L13
.L15:
movslq %ecx, %rbp
leaq 0(,%rbp,8), %rbx
movq 8(%rsp), %rax
addq %rax, %rbp
salq $3, %rbp
movl %ecx, (%rsp)
movl %esi, 4(%rsp)
.L14:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%r15,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%r14,%rbx)
movq $0x000000000, 0(%r13,%rbx)
addq $8, %rbx
cmpq %rbp, %rbx
jne .L14
movl (%rsp), %ecx
movl 4(%rsp), %esi
.L16:
addl $1, %r12d
addl %esi, %ecx
cmpl %r12d, 24(%rsp)
je .L29
.L13:
testl %esi, %esi
jg .L15
jmp .L16
.L29:
movq 32(%rsp), %rbx
movq 40(%rsp), %rbp
movl %esi, %r12d
.L12:
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r14, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 104(%rsp)
movl $1, 116(%rsp)
movl 24(%rsp), %eax
leal 63(%rax), %ebp
shrl $6, %ebp
movl 28(%rsp), %eax
leal 15(%rax), %ebx
shrl $4, %ebx
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movl %ebp, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %edx
imull %ebx, %edx
sall $6, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, 108(%rsp)
movl %ebx, 112(%rsp)
movl $16, 96(%rsp)
movl $4, 100(%rsp)
movl 104(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movq 108(%rsp), %rdi
movl 116(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L17:
movl $2, %ecx
movq 16(%rsp), %rdx
movq 72(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %edx
movl 24(%rsp), %ecx
cmpl $0, 24(%rsp)
jg .L18
.L19:
leaq 52(%rsp), %rdi
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movl 28(%rsp), %r9d
movl %r12d, %r8d
movl 24(%rsp), %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _ZL60__device_stub__Z19device_Matrix_multiILi16ELi4EEvPKdS1_PdiiiPKdS0_Pdiii
jmp .L17
.L20:
addl $1, %eax
cmpl %eax, %r12d
jne .L20
.L21:
addl $1, %edx
cmpl %edx, %ecx
je .L19
.L18:
movl $0, %eax
testl %r12d, %r12d
jg .L20
jmp .L21
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z10Algorithm4iii, .-_Z10Algorithm4iii
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $32, %edx
movl $32, %esi
movl $32, %edi
call _Z10Algorithm4iii
movl $64, %edx
movl $64, %esi
movl $64, %edi
call _Z10Algorithm4iii
movl $128, %edx
movl $128, %esi
movl $128, %edi
call _Z10Algorithm4iii
movl $256, %edx
movl $256, %esi
movl $256, %edi
call _Z10Algorithm4iii
movl $512, %edx
movl $512, %esi
movl $512, %edi
call _Z10Algorithm4iii
movl $1024, %edx
movl $1024, %esi
movl $1024, %edi
call _Z10Algorithm4iii
movl $2048, %edx
movl $2048, %esi
movl $2048, %edi
call _Z10Algorithm4iii
movl $4096, %edx
movl $4096, %esi
movl $4096, %edi
call _Z10Algorithm4iii
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <cuda.h>
//void Algorithm1();
void Algorithm4(int m, int n, int l);
//for gemm 4 algorithm
#define BLOCK_SIZE_x 16
#define BLOCK_SIZE_y 4
template<int block_size_x, int block_size_y>
__global__ void device_Matrix_multi(const double* const device_matrix_A,const double* const device_matrix_B,double* device_matrix_C,const int m,const int n,const int l)
{
const int threadid_x = threadIdx.x;
const int threadid_y = threadIdx.y;
const int blockid_x = blockIdx.x;
const int blockid_y = blockIdx.y;
__shared__ double matrix_B_shared[block_size_x][block_size_x+1];
double c[block_size_x];
for (int i = 0; i< block_size_x; i++)
{
c[i] = 0.0;
}
int idx_A = blockid_x*block_size_x*block_size_y + threadid_x + threadid_y*block_size_x;
int idx_B = threadid_x + (blockid_y*block_size_x + threadid_y)*n;
int idx_B_last = idx_B + n;
int col_A = 0;
do
{
for(int i = 0; i < block_size_x; i += block_size_y)
matrix_B_shared[threadid_x][threadid_y + i] = device_matrix_B[idx_B + i*n];
idx_B += block_size_x;
__syncthreads();
int i_bound = min(block_size_x, n - col_A);
for (int i = 0; i < i_bound; i++, idx_A+=m)
{
for (int j = 0; j < block_size_x; j++)
{
c[j] += device_matrix_A[idx_A]*matrix_B_shared[i][j];
}
}
col_A += block_size_x;
__syncthreads();
}while (idx_B < idx_B_last);
if (blockid_x*block_size_x*block_size_y + threadid_x + threadid_y*block_size_x < m)
{
int idx_D = blockid_x*block_size_x*block_size_y + (threadid_x + threadid_y*block_size_x) + blockid_y*block_size_x*m;
int i_bound = min(block_size_x, l - blockid_y*block_size_x);
for (int i = 0; i < i_bound; i++, idx_D += m)
{
device_matrix_C[idx_D] = c[i];
}
}
}
int main()
{
Algorithm4(32, 32, 32);
Algorithm4(64, 64, 64);
Algorithm4(128,128, 128);
Algorithm4(256, 256, 256);
Algorithm4(512, 512, 512);
Algorithm4(1024, 1024, 1024);
Algorithm4(2048, 2048, 2048);
Algorithm4(4096, 4096, 4096);
}
void Algorithm4(int m, int n, int l) {
printf("inside function");
double* matrix_A;
double* matrix_B;
double* matrix_C;
double *device_matrix_A;
double *device_matrix_B;
double *device_matrix_C;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float milliseconds = 0;
// Allocate the device memory
matrix_A = (double*)malloc( m*n* sizeof(double));
matrix_B = (double*)malloc( m*l* sizeof(double));
matrix_C = (double*)malloc( m*l*sizeof(double));
cudaMalloc(&device_matrix_A, m*n*sizeof(double));
cudaMalloc(&device_matrix_B, n*l*sizeof(double));
cudaMalloc(&device_matrix_C, m*l*sizeof(double));
for(int i = 0; i < m; i++)
{
for(int j = 0; j <n; j++){
matrix_A[i *n + j] = rand()%10;
matrix_B[i *n + j] = rand()%10;
matrix_C[i *n + j] = 0;
}
}
// Copy data from the host memory to the device memory
cudaMemcpy(device_matrix_A, matrix_A, m*n*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(device_matrix_B, matrix_B, n*l*sizeof(double), cudaMemcpyHostToDevice);
dim3 nthreads(0, 0);
dim3 nblocks(0, 0); // Launch the kernel
nthreads.x = BLOCK_SIZE_x;
nthreads.y = BLOCK_SIZE_y;
nblocks.x = (m + nthreads.x*nthreads.y - 1)/(nthreads.x*nthreads.y);
nblocks.y = (l + nthreads.x - 1)/nthreads.x;
cudaEventRecord(start);
printf("nuumber of blocks in x = %d\n", nblocks.x);
printf("nuumber of blocks in y = %d\n", nblocks.y);
printf("number of threads in x = %d\n", nthreads.x);
printf("number of threads in y =%d\n", nthreads.y);
printf("total threads = %d", nblocks.x*nblocks.y*nthreads.x*nthreads.y);
device_Matrix_multi<BLOCK_SIZE_x, BLOCK_SIZE_y> <<<nblocks, nthreads>>> ( device_matrix_A,device_matrix_B, device_matrix_C,m,n,l
);
// Copy data from the device memory to the host memory
cudaMemcpy(matrix_C, device_matrix_C, m*l*sizeof(double), cudaMemcpyDeviceToHost);
cudaEventRecord(stop);
for(int i=0; i<m;i++){
for(int j =0; j<n; j++){
}
}
cudaEventElapsedTime(&milliseconds, start, stop);
printf("elaspsed = %f ms\n\n\n", milliseconds);
// Free the device memory
cudaFree(device_matrix_A);
cudaFree(device_matrix_B);
cudaFree(device_matrix_C);
free(matrix_A);
free(matrix_B);
free(matrix_C);
}
|
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
//void Algorithm1();
void Algorithm4(int m, int n, int l);
//for gemm 4 algorithm
#define BLOCK_SIZE_x 16
#define BLOCK_SIZE_y 4
template<int block_size_x, int block_size_y>
__global__ void device_Matrix_multi(const double* const device_matrix_A,const double* const device_matrix_B,double* device_matrix_C,const int m,const int n,const int l)
{
const int threadid_x = threadIdx.x;
const int threadid_y = threadIdx.y;
const int blockid_x = blockIdx.x;
const int blockid_y = blockIdx.y;
__shared__ double matrix_B_shared[block_size_x][block_size_x+1];
double c[block_size_x];
for (int i = 0; i< block_size_x; i++)
{
c[i] = 0.0;
}
int idx_A = blockid_x*block_size_x*block_size_y + threadid_x + threadid_y*block_size_x;
int idx_B = threadid_x + (blockid_y*block_size_x + threadid_y)*n;
int idx_B_last = idx_B + n;
int col_A = 0;
do
{
for(int i = 0; i < block_size_x; i += block_size_y)
matrix_B_shared[threadid_x][threadid_y + i] = device_matrix_B[idx_B + i*n];
idx_B += block_size_x;
__syncthreads();
int i_bound = min(block_size_x, n - col_A);
for (int i = 0; i < i_bound; i++, idx_A+=m)
{
for (int j = 0; j < block_size_x; j++)
{
c[j] += device_matrix_A[idx_A]*matrix_B_shared[i][j];
}
}
col_A += block_size_x;
__syncthreads();
}while (idx_B < idx_B_last);
if (blockid_x*block_size_x*block_size_y + threadid_x + threadid_y*block_size_x < m)
{
int idx_D = blockid_x*block_size_x*block_size_y + (threadid_x + threadid_y*block_size_x) + blockid_y*block_size_x*m;
int i_bound = min(block_size_x, l - blockid_y*block_size_x);
for (int i = 0; i < i_bound; i++, idx_D += m)
{
device_matrix_C[idx_D] = c[i];
}
}
}
int main()
{
Algorithm4(32, 32, 32);
Algorithm4(64, 64, 64);
Algorithm4(128,128, 128);
Algorithm4(256, 256, 256);
Algorithm4(512, 512, 512);
Algorithm4(1024, 1024, 1024);
Algorithm4(2048, 2048, 2048);
Algorithm4(4096, 4096, 4096);
}
void Algorithm4(int m, int n, int l) {
printf("inside function");
double* matrix_A;
double* matrix_B;
double* matrix_C;
double *device_matrix_A;
double *device_matrix_B;
double *device_matrix_C;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float milliseconds = 0;
// Allocate the device memory
matrix_A = (double*)malloc( m*n* sizeof(double));
matrix_B = (double*)malloc( m*l* sizeof(double));
matrix_C = (double*)malloc( m*l*sizeof(double));
hipMalloc(&device_matrix_A, m*n*sizeof(double));
hipMalloc(&device_matrix_B, n*l*sizeof(double));
hipMalloc(&device_matrix_C, m*l*sizeof(double));
for(int i = 0; i < m; i++)
{
for(int j = 0; j <n; j++){
matrix_A[i *n + j] = rand()%10;
matrix_B[i *n + j] = rand()%10;
matrix_C[i *n + j] = 0;
}
}
// Copy data from the host memory to the device memory
hipMemcpy(device_matrix_A, matrix_A, m*n*sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(device_matrix_B, matrix_B, n*l*sizeof(double), hipMemcpyHostToDevice);
dim3 nthreads(0, 0);
dim3 nblocks(0, 0); // Launch the kernel
nthreads.x = BLOCK_SIZE_x;
nthreads.y = BLOCK_SIZE_y;
nblocks.x = (m + nthreads.x*nthreads.y - 1)/(nthreads.x*nthreads.y);
nblocks.y = (l + nthreads.x - 1)/nthreads.x;
hipEventRecord(start);
printf("nuumber of blocks in x = %d\n", nblocks.x);
printf("nuumber of blocks in y = %d\n", nblocks.y);
printf("number of threads in x = %d\n", nthreads.x);
printf("number of threads in y =%d\n", nthreads.y);
printf("total threads = %d", nblocks.x*nblocks.y*nthreads.x*nthreads.y);
device_Matrix_multi<BLOCK_SIZE_x, BLOCK_SIZE_y> <<<nblocks, nthreads>>> ( device_matrix_A,device_matrix_B, device_matrix_C,m,n,l
);
// Copy data from the device memory to the host memory
hipMemcpy(matrix_C, device_matrix_C, m*l*sizeof(double), hipMemcpyDeviceToHost);
hipEventRecord(stop);
for(int i=0; i<m;i++){
for(int j =0; j<n; j++){
}
}
hipEventElapsedTime(&milliseconds, start, stop);
printf("elaspsed = %f ms\n\n\n", milliseconds);
// Free the device memory
hipFree(device_matrix_A);
hipFree(device_matrix_B);
hipFree(device_matrix_C);
free(matrix_A);
free(matrix_B);
free(matrix_C);
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
//void Algorithm1();
void Algorithm4(int m, int n, int l);
//for gemm 4 algorithm
#define BLOCK_SIZE_x 16
#define BLOCK_SIZE_y 4
template<int block_size_x, int block_size_y>
__global__ void device_Matrix_multi(const double* const device_matrix_A,const double* const device_matrix_B,double* device_matrix_C,const int m,const int n,const int l)
{
const int threadid_x = threadIdx.x;
const int threadid_y = threadIdx.y;
const int blockid_x = blockIdx.x;
const int blockid_y = blockIdx.y;
__shared__ double matrix_B_shared[block_size_x][block_size_x+1];
double c[block_size_x];
for (int i = 0; i< block_size_x; i++)
{
c[i] = 0.0;
}
int idx_A = blockid_x*block_size_x*block_size_y + threadid_x + threadid_y*block_size_x;
int idx_B = threadid_x + (blockid_y*block_size_x + threadid_y)*n;
int idx_B_last = idx_B + n;
int col_A = 0;
do
{
for(int i = 0; i < block_size_x; i += block_size_y)
matrix_B_shared[threadid_x][threadid_y + i] = device_matrix_B[idx_B + i*n];
idx_B += block_size_x;
__syncthreads();
int i_bound = min(block_size_x, n - col_A);
for (int i = 0; i < i_bound; i++, idx_A+=m)
{
for (int j = 0; j < block_size_x; j++)
{
c[j] += device_matrix_A[idx_A]*matrix_B_shared[i][j];
}
}
col_A += block_size_x;
__syncthreads();
}while (idx_B < idx_B_last);
if (blockid_x*block_size_x*block_size_y + threadid_x + threadid_y*block_size_x < m)
{
int idx_D = blockid_x*block_size_x*block_size_y + (threadid_x + threadid_y*block_size_x) + blockid_y*block_size_x*m;
int i_bound = min(block_size_x, l - blockid_y*block_size_x);
for (int i = 0; i < i_bound; i++, idx_D += m)
{
device_matrix_C[idx_D] = c[i];
}
}
}
int main()
{
Algorithm4(32, 32, 32);
Algorithm4(64, 64, 64);
Algorithm4(128,128, 128);
Algorithm4(256, 256, 256);
Algorithm4(512, 512, 512);
Algorithm4(1024, 1024, 1024);
Algorithm4(2048, 2048, 2048);
Algorithm4(4096, 4096, 4096);
}
void Algorithm4(int m, int n, int l) {
printf("inside function");
double* matrix_A;
double* matrix_B;
double* matrix_C;
double *device_matrix_A;
double *device_matrix_B;
double *device_matrix_C;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float milliseconds = 0;
// Allocate the device memory
matrix_A = (double*)malloc( m*n* sizeof(double));
matrix_B = (double*)malloc( m*l* sizeof(double));
matrix_C = (double*)malloc( m*l*sizeof(double));
hipMalloc(&device_matrix_A, m*n*sizeof(double));
hipMalloc(&device_matrix_B, n*l*sizeof(double));
hipMalloc(&device_matrix_C, m*l*sizeof(double));
for(int i = 0; i < m; i++)
{
for(int j = 0; j <n; j++){
matrix_A[i *n + j] = rand()%10;
matrix_B[i *n + j] = rand()%10;
matrix_C[i *n + j] = 0;
}
}
// Copy data from the host memory to the device memory
hipMemcpy(device_matrix_A, matrix_A, m*n*sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(device_matrix_B, matrix_B, n*l*sizeof(double), hipMemcpyHostToDevice);
dim3 nthreads(0, 0);
dim3 nblocks(0, 0); // Launch the kernel
nthreads.x = BLOCK_SIZE_x;
nthreads.y = BLOCK_SIZE_y;
nblocks.x = (m + nthreads.x*nthreads.y - 1)/(nthreads.x*nthreads.y);
nblocks.y = (l + nthreads.x - 1)/nthreads.x;
hipEventRecord(start);
printf("nuumber of blocks in x = %d\n", nblocks.x);
printf("nuumber of blocks in y = %d\n", nblocks.y);
printf("number of threads in x = %d\n", nthreads.x);
printf("number of threads in y =%d\n", nthreads.y);
printf("total threads = %d", nblocks.x*nblocks.y*nthreads.x*nthreads.y);
device_Matrix_multi<BLOCK_SIZE_x, BLOCK_SIZE_y> <<<nblocks, nthreads>>> ( device_matrix_A,device_matrix_B, device_matrix_C,m,n,l
);
// Copy data from the device memory to the host memory
hipMemcpy(matrix_C, device_matrix_C, m*l*sizeof(double), hipMemcpyDeviceToHost);
hipEventRecord(stop);
for(int i=0; i<m;i++){
for(int j =0; j<n; j++){
}
}
hipEventElapsedTime(&milliseconds, start, stop);
printf("elaspsed = %f ms\n\n\n", milliseconds);
// Free the device memory
hipFree(device_matrix_A);
hipFree(device_matrix_B);
hipFree(device_matrix_C);
free(matrix_A);
free(matrix_B);
free(matrix_C);
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii,"axG",@progbits,_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii,comdat
.protected _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.globl _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.p2align 8
.type _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii,@function
_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii:
s_mov_b64 s[2:3], 0
.LBB0_1:
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s4, s2, 1
s_add_u32 s2, s2, 1
s_mov_b32 m0, s4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 16
v_movreld_b32_e32 v1, 0
v_movreld_b32_e32 v2, 0
s_cbranch_scc0 .LBB0_1
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v35, v0, 10, 10
s_lshl_b32 s10, s15, 4
v_and_b32_e32 v0, 0x3ff, v0
s_lshl_b32 s11, s14, 6
s_mov_b32 s13, 0
v_add_nc_u32_e32 v36, s10, v35
v_lshlrev_b32_e32 v37, 4, v35
s_mov_b32 s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v38, s11, v0, v37
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[33:34], null, v36, s3, v[0:1]
v_lshlrev_b32_e32 v34, 3, v35
s_lshl_b32 s12, s3, 2
s_mov_b32 s14, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mad_u32_u24 v39, v0, 0x88, v34
v_mov_b32_e32 v34, v38
v_add_nc_u32_e32 v40, s3, v33
s_branch .LBB0_4
.LBB0_3:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v33, 16, v33
s_add_i32 s15, s15, 16
s_add_i32 s14, s14, -16
s_barrier
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v33, v40
buffer_gl0_inv
s_or_b32 s13, vcc_lo, s13
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_11
.LBB0_4:
v_mov_b32_e32 v35, v33
v_mov_b32_e32 v41, v39
s_mov_b32 s8, -4
.LBB0_5:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v36, 31, v35
s_add_i32 s8, s8, 4
s_cmp_gt_u32 s8, 11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[42:43], 3, v[35:36]
v_add_nc_u32_e32 v35, s12, v35
v_add_co_u32 v42, vcc_lo, s6, v42
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v43, vcc_lo, s7, v43, vcc_lo
global_load_b64 v[42:43], v[42:43], off
s_waitcnt vmcnt(0)
ds_store_b64 v41, v[42:43]
v_add_nc_u32_e32 v41, 32, v41
s_cbranch_scc0 .LBB0_5
s_cmp_ge_i32 s15, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_3
v_med3_i32 v41, s14, 1, 16
s_mov_b32 s16, 0
s_mov_b32 s17, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_8:
v_ashrrev_i32_e32 v35, 31, v34
s_mov_b64 s[8:9], 0
s_mov_b32 s18, s16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[35:36], 3, v[34:35]
v_add_co_u32 v35, vcc_lo, s4, v35
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v36, vcc_lo, s5, v36, vcc_lo
global_load_b64 v[35:36], v[35:36], off
.LBB0_9:
v_mov_b32_e32 v42, s18
s_lshl_b32 s19, s8, 1
s_add_u32 s8, s8, 1
s_mov_b32 m0, s19
s_addc_u32 s9, s9, 0
ds_load_b64 v[42:43], v42
v_movrels_b32_e32 v45, v2
v_movrels_b32_e32 v44, v1
s_add_i32 s18, s18, 8
s_cmp_eq_u32 s8, 16
s_waitcnt vmcnt(0) lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[42:43], v[35:36], v[42:43], v[44:45]
v_movreld_b32_e32 v1, v42
s_delay_alu instid0(VALU_DEP_2)
v_movreld_b32_e32 v2, v43
s_cbranch_scc0 .LBB0_9
s_add_i32 s17, s17, 1
v_add_nc_u32_e32 v34, s2, v34
v_cmp_eq_u32_e32 vcc_lo, s17, v41
s_addk_i32 s16, 0x88
s_cbranch_vccz .LBB0_8
s_branch .LBB0_3
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v38
s_cbranch_execz .LBB0_15
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_sub_i32 s3, s3, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_15
v_add_nc_u32_e32 v0, v37, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_mul_i32 s10, s10, s2
s_mov_b64 s[4:5], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add3_u32 v33, s10, s11, v0
v_med3_i32 v0, s3, 1, 16
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[2:3], s[2:3], 3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v34, 31, v33
v_lshlrev_b64 v[33:34], 3, v[33:34]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v33, vcc_lo, s0, v33
v_add_co_ci_u32_e32 v34, vcc_lo, s1, v34, vcc_lo
.LBB0_14:
s_lshl_b32 s0, s4, 1
s_add_u32 s4, s4, 1
s_mov_b32 m0, s0
v_cmp_ne_u32_e32 vcc_lo, s4, v0
v_movrels_b32_e32 v36, v2
v_movrels_b32_e32 v35, v1
s_addc_u32 s5, s5, 0
global_store_b64 v[33:34], v[35:36], off
v_add_co_u32 v33, s0, v33, s2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v34, s0, s3, v34, s0
s_cbranch_vccnz .LBB0_14
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.amdhsa_group_segment_fixed_size 2176
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 46
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii,"axG",@progbits,_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii,comdat
.Lfunc_end0:
.size _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii, .Lfunc_end0-_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2176
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 46
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
//void Algorithm1();
void Algorithm4(int m, int n, int l);
//for gemm 4 algorithm
#define BLOCK_SIZE_x 16
#define BLOCK_SIZE_y 4
template<int block_size_x, int block_size_y>
__global__ void device_Matrix_multi(const double* const device_matrix_A,const double* const device_matrix_B,double* device_matrix_C,const int m,const int n,const int l)
{
const int threadid_x = threadIdx.x;
const int threadid_y = threadIdx.y;
const int blockid_x = blockIdx.x;
const int blockid_y = blockIdx.y;
__shared__ double matrix_B_shared[block_size_x][block_size_x+1];
double c[block_size_x];
for (int i = 0; i< block_size_x; i++)
{
c[i] = 0.0;
}
int idx_A = blockid_x*block_size_x*block_size_y + threadid_x + threadid_y*block_size_x;
int idx_B = threadid_x + (blockid_y*block_size_x + threadid_y)*n;
int idx_B_last = idx_B + n;
int col_A = 0;
do
{
for(int i = 0; i < block_size_x; i += block_size_y)
matrix_B_shared[threadid_x][threadid_y + i] = device_matrix_B[idx_B + i*n];
idx_B += block_size_x;
__syncthreads();
int i_bound = min(block_size_x, n - col_A);
for (int i = 0; i < i_bound; i++, idx_A+=m)
{
for (int j = 0; j < block_size_x; j++)
{
c[j] += device_matrix_A[idx_A]*matrix_B_shared[i][j];
}
}
col_A += block_size_x;
__syncthreads();
}while (idx_B < idx_B_last);
if (blockid_x*block_size_x*block_size_y + threadid_x + threadid_y*block_size_x < m)
{
int idx_D = blockid_x*block_size_x*block_size_y + (threadid_x + threadid_y*block_size_x) + blockid_y*block_size_x*m;
int i_bound = min(block_size_x, l - blockid_y*block_size_x);
for (int i = 0; i < i_bound; i++, idx_D += m)
{
device_matrix_C[idx_D] = c[i];
}
}
}
int main()
{
Algorithm4(32, 32, 32);
Algorithm4(64, 64, 64);
Algorithm4(128,128, 128);
Algorithm4(256, 256, 256);
Algorithm4(512, 512, 512);
Algorithm4(1024, 1024, 1024);
Algorithm4(2048, 2048, 2048);
Algorithm4(4096, 4096, 4096);
}
void Algorithm4(int m, int n, int l) {
printf("inside function");
double* matrix_A;
double* matrix_B;
double* matrix_C;
double *device_matrix_A;
double *device_matrix_B;
double *device_matrix_C;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float milliseconds = 0;
// Allocate the device memory
matrix_A = (double*)malloc( m*n* sizeof(double));
matrix_B = (double*)malloc( m*l* sizeof(double));
matrix_C = (double*)malloc( m*l*sizeof(double));
hipMalloc(&device_matrix_A, m*n*sizeof(double));
hipMalloc(&device_matrix_B, n*l*sizeof(double));
hipMalloc(&device_matrix_C, m*l*sizeof(double));
for(int i = 0; i < m; i++)
{
for(int j = 0; j <n; j++){
matrix_A[i *n + j] = rand()%10;
matrix_B[i *n + j] = rand()%10;
matrix_C[i *n + j] = 0;
}
}
// Copy data from the host memory to the device memory
hipMemcpy(device_matrix_A, matrix_A, m*n*sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(device_matrix_B, matrix_B, n*l*sizeof(double), hipMemcpyHostToDevice);
dim3 nthreads(0, 0);
dim3 nblocks(0, 0); // Launch the kernel
nthreads.x = BLOCK_SIZE_x;
nthreads.y = BLOCK_SIZE_y;
nblocks.x = (m + nthreads.x*nthreads.y - 1)/(nthreads.x*nthreads.y);
nblocks.y = (l + nthreads.x - 1)/nthreads.x;
hipEventRecord(start);
printf("nuumber of blocks in x = %d\n", nblocks.x);
printf("nuumber of blocks in y = %d\n", nblocks.y);
printf("number of threads in x = %d\n", nthreads.x);
printf("number of threads in y =%d\n", nthreads.y);
printf("total threads = %d", nblocks.x*nblocks.y*nthreads.x*nthreads.y);
device_Matrix_multi<BLOCK_SIZE_x, BLOCK_SIZE_y> <<<nblocks, nthreads>>> ( device_matrix_A,device_matrix_B, device_matrix_C,m,n,l
);
// Copy data from the device memory to the host memory
hipMemcpy(matrix_C, device_matrix_C, m*l*sizeof(double), hipMemcpyDeviceToHost);
hipEventRecord(stop);
for(int i=0; i<m;i++){
for(int j =0; j<n; j++){
}
}
hipEventElapsedTime(&milliseconds, start, stop);
printf("elaspsed = %f ms\n\n\n", milliseconds);
// Free the device memory
hipFree(device_matrix_A);
hipFree(device_matrix_B);
hipFree(device_matrix_C);
free(matrix_A);
free(matrix_B);
free(matrix_C);
}
|
.text
.file "algorithm4.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $32, %edi
movl $32, %esi
movl $32, %edx
callq _Z10Algorithm4iii
movl $64, %edi
movl $64, %esi
movl $64, %edx
callq _Z10Algorithm4iii
movl $128, %edi
movl $128, %esi
movl $128, %edx
callq _Z10Algorithm4iii
movl $256, %edi # imm = 0x100
movl $256, %esi # imm = 0x100
movl $256, %edx # imm = 0x100
callq _Z10Algorithm4iii
movl $512, %edi # imm = 0x200
movl $512, %esi # imm = 0x200
movl $512, %edx # imm = 0x200
callq _Z10Algorithm4iii
movl $1024, %edi # imm = 0x400
movl $1024, %esi # imm = 0x400
movl $1024, %edx # imm = 0x400
callq _Z10Algorithm4iii
movl $2048, %edi # imm = 0x800
movl $2048, %esi # imm = 0x800
movl $2048, %edx # imm = 0x800
callq _Z10Algorithm4iii
movl $4096, %edi # imm = 0x1000
movl $4096, %esi # imm = 0x1000
movl $4096, %edx # imm = 0x1000
callq _Z10Algorithm4iii
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z10Algorithm4iii # -- Begin function _Z10Algorithm4iii
.p2align 4, 0x90
.type _Z10Algorithm4iii,@function
_Z10Algorithm4iii: # @_Z10Algorithm4iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r14d
movl %esi, %ebp
movl %edi, %r15d
xorl %eax, %eax
movq %rax, 32(%rsp) # 8-byte Spill
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 104(%rsp), %rdi
callq hipEventCreate
leaq 96(%rsp), %rdi
callq hipEventCreate
movl $0, 12(%rsp)
movl %ebp, %eax
imull %r15d, %eax
movslq %eax, %r12
shlq $3, %r12
movq %r12, %rdi
callq malloc
movq %rax, 24(%rsp) # 8-byte Spill
movl %r14d, %eax
imull %r15d, %eax
movslq %eax, %rbx
shlq $3, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, 88(%rsp) # 8-byte Spill
leaq 56(%rsp), %rdi
movq %r12, 120(%rsp) # 8-byte Spill
movq %r12, %rsi
callq hipMalloc
movq %r14, 128(%rsp) # 8-byte Spill
movl %r14d, %eax
imull %ebp, %eax
movslq %eax, %rsi
shlq $3, %rsi
leaq 48(%rsp), %rdi
movq %rsi, 112(%rsp) # 8-byte Spill
callq hipMalloc
leaq 40(%rsp), %rdi
movq %rbx, 136(%rsp) # 8-byte Spill
movq %rbx, %rsi
callq hipMalloc
movq %r15, 80(%rsp) # 8-byte Spill
testl %r15d, %r15d
movl %ebp, 8(%rsp) # 4-byte Spill
jle .LBB1_6
# %bb.1: # %.preheader89.lr.ph
movl 80(%rsp), %eax # 4-byte Reload
movq %rax, 144(%rsp) # 8-byte Spill
movl %ebp, %r12d
xorl %r13d, %r13d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r13
movl 8(%rsp), %ebp # 4-byte Reload
movq 32(%rsp), %rax # 8-byte Reload
addl %ebp, %eax
movq %rax, 32(%rsp) # 8-byte Spill
cmpq 144(%rsp), %r13 # 8-byte Folded Reload
je .LBB1_6
.LBB1_2: # %.preheader89
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %ebp, %ebp
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl 32(%rsp), %eax # 4-byte Reload
movq 88(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r15
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %rbp
movq 24(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%r14,%rbx,8)
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rbp,%rbx,8)
movq $0, (%r15,%rbx,8)
incq %rbx
cmpq %rbx, %r12
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge92
movq 56(%rsp), %rdi
movq 24(%rsp), %rsi # 8-byte Reload
movq 120(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq 16(%rsp), %rsi # 8-byte Reload
movq 112(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 80(%rsp), %rbp # 8-byte Reload
leal 63(%rbp), %r12d
movl %r12d, %r14d
shrl $6, %r14d
movq 128(%rsp), %r15 # 8-byte Reload
leal 15(%r15), %r13d
shrl $4, %r13d
movq %r13, %rbx
shlq $32, %rbx
orq %r14, %rbx
movq 104(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $.L.str.1, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movl %r13d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl $16, %esi
xorl %eax, %eax
callq printf
movl $.L.str.4, %edi
movl $4, %esi
xorl %eax, %eax
callq printf
andl $-64, %r12d
imull %r13d, %r12d
movl $.L.str.5, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movabsq $17179869200, %rdx # imm = 0x400000010
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 216(%rsp)
movq %rcx, 208(%rsp)
movq %rdx, 200(%rsp)
movl %ebp, 76(%rsp)
movl 8(%rsp), %eax # 4-byte Reload
movl %eax, 72(%rsp)
movl %r15d, 68(%rsp)
leaq 216(%rsp), %rax
movq %rax, 224(%rsp)
leaq 208(%rsp), %rax
movq %rax, 232(%rsp)
leaq 200(%rsp), %rax
movq %rax, 240(%rsp)
leaq 76(%rsp), %rax
movq %rax, 248(%rsp)
leaq 72(%rsp), %rax
movq %rax, 256(%rsp)
leaq 68(%rsp), %rax
movq %rax, 264(%rsp)
leaq 184(%rsp), %rdi
leaq 168(%rsp), %rsi
leaq 160(%rsp), %rdx
leaq 152(%rsp), %rcx
callq __hipPopCallConfiguration
movq 184(%rsp), %rsi
movl 192(%rsp), %edx
movq 168(%rsp), %rcx
movl 176(%rsp), %r8d
leaq 224(%rsp), %r9
movl $_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii, %edi
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8: # %._crit_edge94
movq 40(%rsp), %rsi
movq 88(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movq 136(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 104(%rsp), %rsi
movq 96(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi # 8-byte Reload
callq free
movq 16(%rsp), %rdi # 8-byte Reload
callq free
movq %rbx, %rdi
callq free
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10Algorithm4iii, .Lfunc_end1-_Z10Algorithm4iii
.cfi_endproc
# -- End function
.section .text._Z34__device_stub__device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii,"axG",@progbits,_Z34__device_stub__device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii,comdat
.weak _Z34__device_stub__device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii # -- Begin function _Z34__device_stub__device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.p2align 4, 0x90
.type _Z34__device_stub__device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii,@function
_Z34__device_stub__device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii: # @_Z34__device_stub__device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z34__device_stub__device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii, .Lfunc_end2-_Z34__device_stub__device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "inside function"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "nuumber of blocks in x = %d\n"
.size .L.str.1, 29
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "nuumber of blocks in y = %d\n"
.size .L.str.2, 29
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "number of threads in x = %d\n"
.size .L.str.3, 29
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "number of threads in y =%d\n"
.size .L.str.4, 28
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "total threads = %d"
.size .L.str.5, 19
.type _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii,@object # @_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.section .rodata._Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii,"aG",@progbits,_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii,comdat
.weak _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.p2align 3, 0x0
_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii:
.quad _Z34__device_stub__device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.size _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "elaspsed = %f ms\n\n\n"
.size .L.str.6, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii"
.size .L__unnamed_1, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0020*/ ULDC UR7, c[0x0][0x17c] ; /* 0x00005f0000077ab9 */
/* 0x000fe20000000800 */
/*0030*/ CS2R R50, SRZ ; /* 0x0000000000327805 */
/* 0x000fe2000001ff00 */
/*0040*/ CS2R R52, SRZ ; /* 0x0000000000347805 */
/* 0x000fe2000001ff00 */
/*0050*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002600 */
/*0060*/ CS2R R56, SRZ ; /* 0x0000000000387805 */
/* 0x000fe2000001ff00 */
/*0070*/ CS2R R48, SRZ ; /* 0x0000000000307805 */
/* 0x000fe2000001ff00 */
/*0080*/ CS2R R36, SRZ ; /* 0x0000000000247805 */
/* 0x000fe2000001ff00 */
/*0090*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*00a0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*00b0*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe2000001ff00 */
/*00c0*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fe2000001ff00 */
/*00d0*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e620000002100 */
/*00e0*/ CS2R R14, SRZ ; /* 0x00000000000e7805 */
/* 0x000fe2000001ff00 */
/*00f0*/ CS2R R38, SRZ ; /* 0x0000000000267805 */
/* 0x000fe2000001ff00 */
/*0100*/ CS2R R54, SRZ ; /* 0x0000000000367805 */
/* 0x000fe2000001ff00 */
/*0110*/ CS2R R46, SRZ ; /* 0x00000000002e7805 */
/* 0x000fe2000001ff00 */
/*0120*/ CS2R R44, SRZ ; /* 0x00000000002c7805 */
/* 0x000fe2000001ff00 */
/*0130*/ CS2R R42, SRZ ; /* 0x00000000002a7805 */
/* 0x000fe2000001ff00 */
/*0140*/ CS2R R40, SRZ ; /* 0x0000000000287805 */
/* 0x000fe2000001ff00 */
/*0150*/ CS2R R60, SRZ ; /* 0x00000000003c7805 */
/* 0x000fe2000001ff00 */
/*0160*/ ULOP3.LUT UR10, URZ, UR7, URZ, 0x33, !UPT ; /* 0x000000073f0a7292 */
/* 0x000fc4000f8e333f */
/*0170*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fe40000000a00 */
/*0180*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0190*/ USHF.L.U32 UR7, UR7, 0x2, URZ ; /* 0x0000000207077899 */
/* 0x000fe2000800063f */
/*01a0*/ LEA R3, R2, R5, 0x4 ; /* 0x0000000502037211 */
/* 0x001fe200078e20ff */
/*01b0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*01c0*/ IMAD R0, R0, 0x40, R4 ; /* 0x0000004000007824 */
/* 0x002fc600078e0204 */
/*01d0*/ IMAD R3, R3, c[0x0][0x17c], R4 ; /* 0x00005f0003037a24 */
/* 0x000fe400078e0204 */
/*01e0*/ IMAD R0, R5, 0x10, R0 ; /* 0x0000001005007824 */
/* 0x000fe400078e0200 */
/*01f0*/ IMAD R2, R4, 0x11, R5 ; /* 0x0000001104027824 */
/* 0x000fe200078e0205 */
/*0200*/ IADD3 R6, R3, c[0x0][0x17c], RZ ; /* 0x00005f0003067a10 */
/* 0x000fe40007ffe0ff */
/*0210*/ MOV R4, R0 ; /* 0x0000000000047202 */
/* 0x000fe40000000f00 */
/*0220*/ MOV R20, UR7 ; /* 0x0000000700147c02 */
/* 0x009fe20008000f00 */
/*0230*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe400078e00ff */
/*0240*/ IMAD.U32 R19, RZ, RZ, UR7 ; /* 0x00000007ff137e24 */
/* 0x000fe2000f8e00ff */
/*0250*/ IADD3 R20, R20, UR7, R3 ; /* 0x0000000714147c10 */
/* 0x000fe2000fffe003 */
/*0260*/ IMAD.WIDE R16, R3, R5, c[0x0][0x168] ; /* 0x00005a0003107625 */
/* 0x000fc600078e0205 */
/*0270*/ IADD3 R22, R20.reuse, UR7, RZ ; /* 0x0000000714167c10 */
/* 0x040fe2000fffe0ff */
/*0280*/ IMAD.WIDE R20, R20, R5, c[0x0][0x168] ; /* 0x00005a0014147625 */
/* 0x000fc800078e0205 */
/*0290*/ IMAD.WIDE R18, R19, 0x8, R16 ; /* 0x0000000813127825 */
/* 0x000fe400078e0210 */
/*02a0*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000c10107981 */
/* 0x000ea4000c1e1b00 */
/*02b0*/ IMAD.WIDE R22, R22, R5, c[0x0][0x168] ; /* 0x00005a0016167625 */
/* 0x000fe400078e0205 */
/*02c0*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000c12127981 */
/* 0x000ee8000c1e1b00 */
/*02d0*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000c14147981 */
/* 0x000f28000c1e1b00 */
/*02e0*/ LDG.E.64 R22, [R22.64] ; /* 0x0000000c16167981 */
/* 0x000f62000c1e1b00 */
/*02f0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0300*/ ULDC UR6, c[0x0][0x17c] ; /* 0x00005f0000067ab9 */
/* 0x000fc40000000800 */
/*0310*/ UISETP.GE.AND UP0, UPT, UR5, UR6, UPT ; /* 0x000000060500728c */
/* 0x000fcc000bf06270 */
/*0320*/ PLOP3.LUT P1, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f2f008 */
/*0330*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc80007ffe0ff */
/*0340*/ ISETP.GE.AND P0, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x000fe20003f06270 */
/*0350*/ STS.64 [R2.X8], R16 ; /* 0x0000001002007388 */
/* 0x0041e80000008a00 */
/*0360*/ STS.64 [R2.X8+0x20], R18 ; /* 0x0000201202007388 */
/* 0x0081e80000008a00 */
/*0370*/ STS.64 [R2.X8+0x40], R20 ; /* 0x0000401402007388 */
/* 0x0101e80000008a00 */
/*0380*/ STS.64 [R2.X8+0x60], R22 ; /* 0x0000601602007388 */
/* 0x0201e80000008a00 */
/*0390*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03a0*/ @P1 BRA 0xa20 ; /* 0x0000067000001947 */
/* 0x000fea0003800000 */
/*03b0*/ UIADD3 UR6, UR10, UR4, URZ ; /* 0x000000040a067290 */
/* 0x000fc8000fffe03f */
/*03c0*/ UISETP.LT.AND UP0, UPT, UR6, -0x11, UPT ; /* 0xffffffef0600788c */
/* 0x000fc8000bf01270 */
/*03d0*/ USEL UR6, UR6, 0xffffffef, !UP0 ; /* 0xffffffef06067887 */
/* 0x000fc8000c000000 */
/*03e0*/ ULOP3.LUT UR8, URZ, UR6, URZ, 0x33, !UPT ; /* 0x000000063f087292 */
/* 0x000fc8000f8e333f */
/*03f0*/ UISETP.LT.AND UP0, UPT, UR8, 0x1, UPT ; /* 0x000000010800788c */
/* 0x000fc8000bf01270 */
/*0400*/ USEL UR8, UR8, 0x1, !UP0 ; /* 0x0000000108087887 */
/* 0x000fe4000c000000 */
/*0410*/ UISETP.GT.AND UP0, UPT, UR6, -0x3, UPT ; /* 0xfffffffd0600788c */
/* 0x000fe4000bf04270 */
/*0420*/ ULOP3.LUT UR9, UR8, 0x1, URZ, 0xc0, !UPT ; /* 0x0000000108097892 */
/* 0x000fe4000f8ec03f */
/*0430*/ UMOV UR6, URZ ; /* 0x0000003f00067c82 */
/* 0x000fe40008000000 */
/*0440*/ PLOP3.LUT P2, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f4f008 */
/*0450*/ ISETP.NE.AND P1, PT, RZ, UR9, PT ; /* 0x00000009ff007c0c */
/* 0x000fd6000bf25270 */
/*0460*/ @P2 BRA 0x850 ; /* 0x000003e000002947 */
/* 0x000fea0003800000 */
/*0470*/ UIADD3 UR8, UR8, -UR9, URZ ; /* 0x8000000908087290 */
/* 0x000fe4000fffe03f */
/*0480*/ UMOV UR6, URZ ; /* 0x0000003f00067c82 */
/* 0x000fe40008000000 */
/*0490*/ IMAD.WIDE R62, R4, R5, c[0x0][0x160] ; /* 0x00005800043e7625 */
/* 0x004fca00078e0205 */
/*04a0*/ LDG.E.64 R58, [R62.64] ; /* 0x0000000c3e3a7981 */
/* 0x000ea2000c1e1b00 */
/*04b0*/ IMAD.WIDE R32, R5, c[0x0][0x178], R62 ; /* 0x00005e0005207a25 */
/* 0x000fcc00078e023e */
/*04c0*/ LDG.E.64 R32, [R32.64] ; /* 0x0000000c20207981 */
/* 0x000ee2000c1e1b00 */
/*04d0*/ UIMAD UR9, UR6, 0x88, URZ ; /* 0x00000088060978a4 */
/* 0x000fe2000f8e023f */
/*04e0*/ MOV R7, c[0x0][0x178] ; /* 0x00005e0000077a02 */
/* 0x000fe20000000f00 */
/*04f0*/ UIADD3 UR8, UR8, -0x2, URZ ; /* 0xfffffffe08087890 */
/* 0x000fe4000fffe03f */
/*0500*/ UIADD3 UR6, UR6, 0x2, URZ ; /* 0x0000000206067890 */
/* 0x000fe4000fffe03f */
/*0510*/ IMAD R4, R7, 0x2, R4 ; /* 0x0000000207047824 */
/* 0x000fe400078e0204 */
/*0520*/ ISETP.NE.AND P2, PT, RZ, UR8, PT ; /* 0x00000008ff007c0c */
/* 0x000fe2000bf45270 */
/*0530*/ LDS.128 R20, [UR9] ; /* 0x00000009ff147984 */
/* 0x001ea80008000c00 */
/*0540*/ LDS.128 R24, [UR9+0x10] ; /* 0x00001009ff187984 */
/* 0x000e280008000c00 */
/*0550*/ LDS.128 R28, [UR9+0x20] ; /* 0x00002009ff1c7984 */
/* 0x000e680008000c00 */
/*0560*/ LDS.128 R16, [UR9+0x30] ; /* 0x00003009ff107984 */
/* 0x000f220008000c00 */
/*0570*/ DFMA R34, R20, R58, R60 ; /* 0x0000003a1422722b */
/* 0x004fc8000000003c */
/*0580*/ DFMA R60, R58.reuse, R22, R40 ; /* 0x000000163a3c722b */
/* 0x0404e40000000028 */
/*0590*/ LDS.128 R20, [UR9+0x40] ; /* 0x00004009ff147984 */
/* 0x004ea40008000c00 */
/*05a0*/ DFMA R66, R58.reuse, R24, R42 ; /* 0x000000183a42722b */
/* 0x041164000000002a */
/*05b0*/ LDS.128 R40, [UR9+0x90] ; /* 0x00009009ff287984 */
/* 0x001fe40008000c00 */
/*05c0*/ DFMA R68, R58.reuse, R26, R44 ; /* 0x0000001a3a44722b */
/* 0x040024000000002c */
/*05d0*/ LDS.128 R24, [UR9+0x50] ; /* 0x00005009ff187984 */
/* 0x001e240008000c00 */
/*05e0*/ DFMA R72, R58, R28, R46 ; /* 0x0000001c3a48722b */
/* 0x002204000000002e */
/*05f0*/ LDS.128 R44, [UR9+0xa0] ; /* 0x0000a009ff2c7984 */
/* 0x002fe40008000c00 */
/*0600*/ DFMA R54, R58.reuse, R30, R54 ; /* 0x0000001e3a36722b */
/* 0x0403e40000000036 */
/*0610*/ LDS.128 R28, [UR9+0x60] ; /* 0x00006009ff1c7984 */
/* 0x002e640008000c00 */
/*0620*/ DFMA R64, R58, R16, R38 ; /* 0x000000103a40722b */
/* 0x010fc80000000026 */
/*0630*/ DFMA R14, R58.reuse, R18, R14 ; /* 0x000000123a0e722b */
/* 0x0409e4000000000e */
/*0640*/ LDS.128 R16, [UR9+0x70] ; /* 0x00007009ff107984 */
/* 0x010f240008000c00 */
/*0650*/ DFMA R62, R58, R20, R10 ; /* 0x000000143a3e722b */
/* 0x004fc8000000000a */
/*0660*/ DFMA R12, R58.reuse, R22, R12 ; /* 0x000000163a0c722b */
/* 0x0405e4000000000c */
/*0670*/ LDS.128 R20, [UR9+0xf0] ; /* 0x0000f009ff147984 */
/* 0x004ea40008000c00 */
/*0680*/ DFMA R70, R58.reuse, R24, R8 ; /* 0x000000183a46722b */
/* 0x0411e40000000008 */
/*0690*/ LDS.128 R8, [UR9+0xc0] ; /* 0x0000c009ff087984 */
/* 0x001e240008000c00 */
/*06a0*/ DFMA R74, R58.reuse, R26, R36 ; /* 0x0000001a3a4a722b */
/* 0x0407e40000000024 */
/*06b0*/ LDS.128 R36, [UR9+0xb0] ; /* 0x0000b009ff247984 */
/* 0x008ee40008000c00 */
/*06c0*/ DFMA R28, R58, R28, R48 ; /* 0x0000001c3a1c722b */
/* 0x002fc40000000030 */
/*06d0*/ LDS.128 R24, [UR9+0xd0] ; /* 0x0000d009ff187984 */
/* 0x000e640008000c00 */
/*06e0*/ DFMA R30, R58, R30, R56 ; /* 0x0000001e3a1e722b */
/* 0x000e880000000038 */
/*06f0*/ DFMA R52, R58, R16, R52 ; /* 0x000000103a34722b */
/* 0x010f080000000034 */
/*0700*/ DFMA R50, R58, R18, R50 ; /* 0x000000123a32722b */
/* 0x0008240000000032 */
/*0710*/ LDS.128 R16, [UR9+0xe0] ; /* 0x0000e009ff107984 */
/* 0x010f240008000c00 */
/*0720*/ DFMA R40, R32.reuse, R40, R60 ; /* 0x000000282028722b */
/* 0x040a24000000003c */
/*0730*/ LDS.64 R60, [UR9+0x88] ; /* 0x00008809ff3c7984 */
/* 0x020f640008000a00 */
/*0740*/ DFMA R42, R32.reuse, R42, R66 ; /* 0x0000002a202a722b */
/* 0x0400240000000042 */
/*0750*/ LDS.64 R58, [UR9+0x100] ; /* 0x00010009ff3a7984 */
/* 0x000f640008000a00 */
/*0760*/ DFMA R44, R32, R44, R68 ; /* 0x0000002c202c722b */
/* 0x0000080000000044 */
/*0770*/ DFMA R46, R32, R46, R72 ; /* 0x0000002e202e722b */
/* 0x0000080000000048 */
/*0780*/ DFMA R56, R32, R20, R30 ; /* 0x000000142038722b */
/* 0x004408000000001e */
/*0790*/ DFMA R14, R32, R8, R14 ; /* 0x00000008200e722b */
/* 0x001408000000000e */
/*07a0*/ DFMA R54, R32, R36, R54 ; /* 0x000000242036722b */
/* 0x0084c80000000036 */
/*07b0*/ DFMA R38, R32, R38, R64 ; /* 0x000000262026722b */
/* 0x0004080000000040 */
/*07c0*/ DFMA R10, R32, R10, R62 ; /* 0x0000000a200a722b */
/* 0x000408000000003e */
/*07d0*/ DFMA R12, R32, R24, R12 ; /* 0x00000018200c722b */
/* 0x002448000000000c */
/*07e0*/ DFMA R8, R32, R26, R70 ; /* 0x0000001a2008722b */
/* 0x0004080000000046 */
/*07f0*/ DFMA R36, R32, R16, R74 ; /* 0x000000102024722b */
/* 0x010508000000004a */
/*0800*/ DFMA R48, R32, R18, R28 ; /* 0x000000122030722b */
/* 0x000408000000001c */
/*0810*/ DFMA R52, R32, R22, R52 ; /* 0x000000162034722b */
/* 0x0004080000000034 */
/*0820*/ DFMA R60, R60, R32, R34 ; /* 0x000000203c3c722b */
/* 0x0204080000000022 */
/*0830*/ DFMA R50, R32, R58, R50 ; /* 0x0000003a2032722b */
/* 0x0004220000000032 */
/*0840*/ @P2 BRA 0x490 ; /* 0xfffffc4000002947 */
/* 0x01afea000383ffff */
/*0850*/ @!P1 BRA 0xa20 ; /* 0x000001c000009947 */
/* 0x000fea0003800000 */
/*0860*/ IMAD.WIDE R58, R4, R5, c[0x0][0x160] ; /* 0x00005800043a7625 */
/* 0x004fcc00078e0205 */
/*0870*/ LDG.E.64 R58, [R58.64] ; /* 0x0000000c3a3a7981 */
/* 0x000ea2000c1e1b00 */
/*0880*/ UIMAD UR6, UR6, 0x88, URZ ; /* 0x00000088060678a4 */
/* 0x000fe2000f8e023f */
/*0890*/ IADD3 R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a10 */
/* 0x000fd00007ffe0ff */
/*08a0*/ LDS.128 R20, [UR6] ; /* 0x00000006ff147984 */
/* 0x001ea80008000c00 */
/*08b0*/ LDS.128 R24, [UR6+0x10] ; /* 0x00001006ff187984 */
/* 0x000e280008000c00 */
/*08c0*/ LDS.128 R28, [UR6+0x20] ; /* 0x00002006ff1c7984 */
/* 0x000e680008000c00 */
/*08d0*/ LDS.128 R16, [UR6+0x30] ; /* 0x00003006ff107984 */
/* 0x000ee80008000c00 */
/*08e0*/ LDS.128 R32, [UR6+0x70] ; /* 0x00007006ff207984 */
/* 0x000f220008000c00 */
/*08f0*/ DFMA R60, R20, R58, R60 ; /* 0x0000003a143c722b */
/* 0x004e88000000003c */
/*0900*/ DFMA R40, R58.reuse, R22, R40 ; /* 0x000000163a28722b */
/* 0x040a240000000028 */
/*0910*/ LDS.128 R20, [UR6+0x40] ; /* 0x00004006ff147984 */
/* 0x020f640008000c00 */
/*0920*/ DFMA R42, R58, R24, R42 ; /* 0x000000183a2a722b */
/* 0x001e08000000002a */
/*0930*/ DFMA R44, R58.reuse, R26, R44 ; /* 0x0000001a3a2c722b */
/* 0x040024000000002c */
/*0940*/ LDS.128 R24, [UR6+0x50] ; /* 0x00005006ff187984 */
/* 0x001e240008000c00 */
/*0950*/ DFMA R46, R58, R28, R46 ; /* 0x0000001c3a2e722b */
/* 0x002e48000000002e */
/*0960*/ DFMA R54, R58.reuse, R30, R54 ; /* 0x0000001e3a36722b */
/* 0x0402240000000036 */
/*0970*/ LDS.128 R28, [UR6+0x60] ; /* 0x00006006ff1c7984 */
/* 0x002e640008000c00 */
/*0980*/ DFMA R38, R58, R16, R38 ; /* 0x000000103a26722b */
/* 0x0086080000000026 */
/*0990*/ DFMA R14, R58, R18, R14 ; /* 0x000000123a0e722b */
/* 0x000608000000000e */
/*09a0*/ DFMA R52, R58, R32, R52 ; /* 0x000000203a34722b */
/* 0x0107080000000034 */
/*09b0*/ DFMA R50, R58, R34, R50 ; /* 0x000000223a32722b */
/* 0x0006080000000032 */
/*09c0*/ DFMA R10, R58, R20, R10 ; /* 0x000000143a0a722b */
/* 0x020608000000000a */
/*09d0*/ DFMA R12, R58, R22, R12 ; /* 0x000000163a0c722b */
/* 0x000608000000000c */
/*09e0*/ DFMA R8, R58, R24, R8 ; /* 0x000000183a08722b */
/* 0x0016080000000008 */
/*09f0*/ DFMA R36, R58, R26, R36 ; /* 0x0000001a3a24722b */
/* 0x0006080000000024 */
/*0a00*/ DFMA R48, R58, R28, R48 ; /* 0x0000001c3a30722b */
/* 0x0026480000000030 */
/*0a10*/ DFMA R56, R58, R30, R56 ; /* 0x0000001e3a38722b */
/* 0x0006080000000038 */
/*0a20*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x016fe20000010000 */
/*0a30*/ UIADD3 UR5, UR5, 0x10, URZ ; /* 0x0000001005057890 */
/* 0x000fe4000fffe03f */
/*0a40*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fc6000fffe03f */
/*0a50*/ @!P0 BRA 0x220 ; /* 0xfffff7c000008947 */
/* 0x000fea000383ffff */
/*0a60*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0a70*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0a80*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e640000002600 */
/*0a90*/ SHF.L.U32 R3, R3, 0x4, RZ ; /* 0x0000000403037819 */
/* 0x002fc800000006ff */
/*0aa0*/ IADD3 R2, -R3, c[0x0][0x180], RZ ; /* 0x0000600003027a10 */
/* 0x001fc80007ffe1ff */
/*0ab0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*0ac0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0ad0*/ IMNMX R2, R2, 0x10, PT ; /* 0x0000001002027817 */
/* 0x000fe20003800200 */
/*0ae0*/ IMAD R6, R3, c[0x0][0x178], R0 ; /* 0x00005e0003067a24 */
/* 0x000fc600078e0200 */
/*0af0*/ ISETP.GE.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fe20003f06270 */
/*0b00*/ IMAD.WIDE R6, R6, R5, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fca00078e0205 */
/*0b10*/ STG.E.64 [R6.64], R60 ; /* 0x0000003c06007986 */
/* 0x0001ee000c101b0c */
/*0b20*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0b30*/ ISETP.NE.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fe20003f05270 */
/*0b40*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0b50*/ STG.E.64 [R6.64], R40 ; /* 0x0000002806007986 */
/* 0x0001ee000c101b0c */
/*0b60*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0b70*/ ISETP.GE.AND P0, PT, R2, 0x4, PT ; /* 0x000000040200780c */
/* 0x000fe20003f06270 */
/*0b80*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0b90*/ STG.E.64 [R6.64], R42 ; /* 0x0000002a06007986 */
/* 0x0001ee000c101b0c */
/*0ba0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0bb0*/ ISETP.NE.AND P0, PT, R2, 0x4, PT ; /* 0x000000040200780c */
/* 0x000fe20003f05270 */
/*0bc0*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0bd0*/ STG.E.64 [R6.64], R44 ; /* 0x0000002c06007986 */
/* 0x0001ee000c101b0c */
/*0be0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0bf0*/ ISETP.GE.AND P0, PT, R2, 0x6, PT ; /* 0x000000060200780c */
/* 0x000fe20003f06270 */
/*0c00*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0c10*/ STG.E.64 [R6.64], R46 ; /* 0x0000002e06007986 */
/* 0x0001ee000c101b0c */
/*0c20*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0c30*/ ISETP.NE.AND P0, PT, R2, 0x6, PT ; /* 0x000000060200780c */
/* 0x000fe20003f05270 */
/*0c40*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0c50*/ STG.E.64 [R6.64], R54 ; /* 0x0000003606007986 */
/* 0x0001ee000c101b0c */
/*0c60*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0c70*/ ISETP.GE.AND P0, PT, R2, 0x8, PT ; /* 0x000000080200780c */
/* 0x000fe20003f06270 */
/*0c80*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0c90*/ STG.E.64 [R6.64], R38 ; /* 0x0000002606007986 */
/* 0x0001ee000c101b0c */
/*0ca0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0cb0*/ ISETP.NE.AND P0, PT, R2, 0x8, PT ; /* 0x000000080200780c */
/* 0x000fe20003f05270 */
/*0cc0*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0cd0*/ STG.E.64 [R6.64], R14 ; /* 0x0000000e06007986 */
/* 0x0001ee000c101b0c */
/*0ce0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0cf0*/ ISETP.GE.AND P0, PT, R2, 0xa, PT ; /* 0x0000000a0200780c */
/* 0x000fe20003f06270 */
/*0d00*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0d10*/ STG.E.64 [R6.64], R10 ; /* 0x0000000a06007986 */
/* 0x0001ee000c101b0c */
/*0d20*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0d30*/ ISETP.NE.AND P0, PT, R2, 0xa, PT ; /* 0x0000000a0200780c */
/* 0x000fe20003f05270 */
/*0d40*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0d50*/ STG.E.64 [R6.64], R12 ; /* 0x0000000c06007986 */
/* 0x0001ee000c101b0c */
/*0d60*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0d70*/ ISETP.GE.AND P0, PT, R2, 0xc, PT ; /* 0x0000000c0200780c */
/* 0x000fe20003f06270 */
/*0d80*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0d90*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x0001ee000c101b0c */
/*0da0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0db0*/ ISETP.NE.AND P0, PT, R2, 0xc, PT ; /* 0x0000000c0200780c */
/* 0x000fe20003f05270 */
/*0dc0*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0dd0*/ STG.E.64 [R6.64], R36 ; /* 0x0000002406007986 */
/* 0x0001ee000c101b0c */
/*0de0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0df0*/ ISETP.GE.AND P0, PT, R2, 0xe, PT ; /* 0x0000000e0200780c */
/* 0x000fe20003f06270 */
/*0e00*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0e10*/ STG.E.64 [R6.64], R48 ; /* 0x0000003006007986 */
/* 0x0001ee000c101b0c */
/*0e20*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0e30*/ ISETP.NE.AND P0, PT, R2, 0xe, PT ; /* 0x0000000e0200780c */
/* 0x000fe20003f05270 */
/*0e40*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0e50*/ STG.E.64 [R6.64], R56 ; /* 0x0000003806007986 */
/* 0x0001ee000c101b0c */
/*0e60*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0e70*/ ISETP.GE.AND P0, PT, R2, 0x10, PT ; /* 0x000000100200780c */
/* 0x000fe20003f06270 */
/*0e80*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0e90*/ STG.E.64 [R6.64], R52 ; /* 0x0000003406007986 */
/* 0x0001ee000c101b0c */
/*0ea0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0eb0*/ IMAD.WIDE R6, R5, c[0x0][0x178], R6 ; /* 0x00005e0005067a25 */
/* 0x001fca00078e0206 */
/*0ec0*/ STG.E.64 [R6.64], R50 ; /* 0x0000003206007986 */
/* 0x000fe2000c101b0c */
/*0ed0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ee0*/ BRA 0xee0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii,"axG",@progbits,_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii,comdat
.protected _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.globl _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.p2align 8
.type _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii,@function
_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii:
s_mov_b64 s[2:3], 0
.LBB0_1:
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s4, s2, 1
s_add_u32 s2, s2, 1
s_mov_b32 m0, s4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 16
v_movreld_b32_e32 v1, 0
v_movreld_b32_e32 v2, 0
s_cbranch_scc0 .LBB0_1
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v35, v0, 10, 10
s_lshl_b32 s10, s15, 4
v_and_b32_e32 v0, 0x3ff, v0
s_lshl_b32 s11, s14, 6
s_mov_b32 s13, 0
v_add_nc_u32_e32 v36, s10, v35
v_lshlrev_b32_e32 v37, 4, v35
s_mov_b32 s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v38, s11, v0, v37
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[33:34], null, v36, s3, v[0:1]
v_lshlrev_b32_e32 v34, 3, v35
s_lshl_b32 s12, s3, 2
s_mov_b32 s14, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mad_u32_u24 v39, v0, 0x88, v34
v_mov_b32_e32 v34, v38
v_add_nc_u32_e32 v40, s3, v33
s_branch .LBB0_4
.LBB0_3:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v33, 16, v33
s_add_i32 s15, s15, 16
s_add_i32 s14, s14, -16
s_barrier
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v33, v40
buffer_gl0_inv
s_or_b32 s13, vcc_lo, s13
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_11
.LBB0_4:
v_mov_b32_e32 v35, v33
v_mov_b32_e32 v41, v39
s_mov_b32 s8, -4
.LBB0_5:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v36, 31, v35
s_add_i32 s8, s8, 4
s_cmp_gt_u32 s8, 11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[42:43], 3, v[35:36]
v_add_nc_u32_e32 v35, s12, v35
v_add_co_u32 v42, vcc_lo, s6, v42
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v43, vcc_lo, s7, v43, vcc_lo
global_load_b64 v[42:43], v[42:43], off
s_waitcnt vmcnt(0)
ds_store_b64 v41, v[42:43]
v_add_nc_u32_e32 v41, 32, v41
s_cbranch_scc0 .LBB0_5
s_cmp_ge_i32 s15, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_3
v_med3_i32 v41, s14, 1, 16
s_mov_b32 s16, 0
s_mov_b32 s17, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_8:
v_ashrrev_i32_e32 v35, 31, v34
s_mov_b64 s[8:9], 0
s_mov_b32 s18, s16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[35:36], 3, v[34:35]
v_add_co_u32 v35, vcc_lo, s4, v35
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v36, vcc_lo, s5, v36, vcc_lo
global_load_b64 v[35:36], v[35:36], off
.LBB0_9:
v_mov_b32_e32 v42, s18
s_lshl_b32 s19, s8, 1
s_add_u32 s8, s8, 1
s_mov_b32 m0, s19
s_addc_u32 s9, s9, 0
ds_load_b64 v[42:43], v42
v_movrels_b32_e32 v45, v2
v_movrels_b32_e32 v44, v1
s_add_i32 s18, s18, 8
s_cmp_eq_u32 s8, 16
s_waitcnt vmcnt(0) lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[42:43], v[35:36], v[42:43], v[44:45]
v_movreld_b32_e32 v1, v42
s_delay_alu instid0(VALU_DEP_2)
v_movreld_b32_e32 v2, v43
s_cbranch_scc0 .LBB0_9
s_add_i32 s17, s17, 1
v_add_nc_u32_e32 v34, s2, v34
v_cmp_eq_u32_e32 vcc_lo, s17, v41
s_addk_i32 s16, 0x88
s_cbranch_vccz .LBB0_8
s_branch .LBB0_3
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v38
s_cbranch_execz .LBB0_15
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_sub_i32 s3, s3, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_15
v_add_nc_u32_e32 v0, v37, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_mul_i32 s10, s10, s2
s_mov_b64 s[4:5], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add3_u32 v33, s10, s11, v0
v_med3_i32 v0, s3, 1, 16
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[2:3], s[2:3], 3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v34, 31, v33
v_lshlrev_b64 v[33:34], 3, v[33:34]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v33, vcc_lo, s0, v33
v_add_co_ci_u32_e32 v34, vcc_lo, s1, v34, vcc_lo
.LBB0_14:
s_lshl_b32 s0, s4, 1
s_add_u32 s4, s4, 1
s_mov_b32 m0, s0
v_cmp_ne_u32_e32 vcc_lo, s4, v0
v_movrels_b32_e32 v36, v2
v_movrels_b32_e32 v35, v1
s_addc_u32 s5, s5, 0
global_store_b64 v[33:34], v[35:36], off
v_add_co_u32 v33, s0, v33, s2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v34, s0, s3, v34, s0
s_cbranch_vccnz .LBB0_14
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.amdhsa_group_segment_fixed_size 2176
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 46
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii,"axG",@progbits,_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii,comdat
.Lfunc_end0:
.size _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii, .Lfunc_end0-_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2176
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 46
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001362ad_00000000-6_algorithm4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL60__device_stub__Z19device_Matrix_multiILi16ELi4EEvPKdS1_PdiiiPKdS0_Pdiii, @function
_ZL60__device_stub__Z19device_Matrix_multiILi16ELi4EEvPKdS1_PdiiiPKdS0_Pdiii:
.LFB2085:
.cfi_startproc
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _ZL60__device_stub__Z19device_Matrix_multiILi16ELi4EEvPKdS1_PdiiiPKdS0_Pdiii, .-_ZL60__device_stub__Z19device_Matrix_multiILi16ELi4EEvPKdS1_PdiiiPKdS0_Pdiii
.section .text._Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii,"axG",@progbits,_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii,comdat
.weak _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.type _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii, @function
_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii:
.LFB2135:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL60__device_stub__Z19device_Matrix_multiILi16ELi4EEvPKdS1_PdiiiPKdS0_Pdiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2135:
.size _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii, .-_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "inside function"
.LC3:
.string "nuumber of blocks in x = %d\n"
.LC4:
.string "nuumber of blocks in y = %d\n"
.LC5:
.string "number of threads in x = %d\n"
.LC6:
.string "number of threads in y =%d\n"
.LC7:
.string "total threads = %d"
.LC8:
.string "elaspsed = %f ms\n\n\n"
.text
.globl _Z10Algorithm4iii
.type _Z10Algorithm4iii, @function
_Z10Algorithm4iii:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movl %edi, %r14d
movl %esi, %r12d
movl %edx, %ebp
movl %edx, 28(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
leaq 88(%rsp), %rdi
call cudaEventCreate@PLT
movl $0x00000000, 52(%rsp)
movl %r14d, %eax
imull %r12d, %eax
cltq
leaq 0(,%rax,8), %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
movl %r14d, 24(%rsp)
movl %r14d, %eax
imull %ebp, %eax
cltq
leaq 0(,%rax,8), %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r14
movq %r13, 16(%rsp)
movq %r13, %rdi
call malloc@PLT
movq %rax, %r13
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
imull %r12d, %ebp
movl %ebp, %eax
cltq
leaq 0(,%rax,8), %rbp
leaq 64(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq 16(%rsp), %rsi
call cudaMalloc@PLT
cmpl $0, 24(%rsp)
jle .L12
movl $0, %ecx
movl $0, %edx
movslq %r12d, %rax
movq %rax, 8(%rsp)
movq %rbx, 32(%rsp)
movq %rbp, 40(%rsp)
movl %r12d, %esi
movl %edx, %r12d
jmp .L13
.L15:
movslq %ecx, %rbp
leaq 0(,%rbp,8), %rbx
movq 8(%rsp), %rax
addq %rax, %rbp
salq $3, %rbp
movl %ecx, (%rsp)
movl %esi, 4(%rsp)
.L14:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%r15,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%r14,%rbx)
movq $0x000000000, 0(%r13,%rbx)
addq $8, %rbx
cmpq %rbp, %rbx
jne .L14
movl (%rsp), %ecx
movl 4(%rsp), %esi
.L16:
addl $1, %r12d
addl %esi, %ecx
cmpl %r12d, 24(%rsp)
je .L29
.L13:
testl %esi, %esi
jg .L15
jmp .L16
.L29:
movq 32(%rsp), %rbx
movq 40(%rsp), %rbp
movl %esi, %r12d
.L12:
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r14, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 104(%rsp)
movl $1, 116(%rsp)
movl 24(%rsp), %eax
leal 63(%rax), %ebp
shrl $6, %ebp
movl 28(%rsp), %eax
leal 15(%rax), %ebx
shrl $4, %ebx
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movl %ebp, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %edx
imull %ebx, %edx
sall $6, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, 108(%rsp)
movl %ebx, 112(%rsp)
movl $16, 96(%rsp)
movl $4, 100(%rsp)
movl 104(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movq 108(%rsp), %rdi
movl 116(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L17:
movl $2, %ecx
movq 16(%rsp), %rdx
movq 72(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %edx
movl 24(%rsp), %ecx
cmpl $0, 24(%rsp)
jg .L18
.L19:
leaq 52(%rsp), %rdi
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movl 28(%rsp), %r9d
movl %r12d, %r8d
movl 24(%rsp), %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _ZL60__device_stub__Z19device_Matrix_multiILi16ELi4EEvPKdS1_PdiiiPKdS0_Pdiii
jmp .L17
.L20:
addl $1, %eax
cmpl %eax, %r12d
jne .L20
.L21:
addl $1, %edx
cmpl %edx, %ecx
je .L19
.L18:
movl $0, %eax
testl %r12d, %r12d
jg .L20
jmp .L21
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z10Algorithm4iii, .-_Z10Algorithm4iii
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $32, %edx
movl $32, %esi
movl $32, %edi
call _Z10Algorithm4iii
movl $64, %edx
movl $64, %esi
movl $64, %edi
call _Z10Algorithm4iii
movl $128, %edx
movl $128, %esi
movl $128, %edi
call _Z10Algorithm4iii
movl $256, %edx
movl $256, %esi
movl $256, %edi
call _Z10Algorithm4iii
movl $512, %edx
movl $512, %esi
movl $512, %edi
call _Z10Algorithm4iii
movl $1024, %edx
movl $1024, %esi
movl $1024, %edi
call _Z10Algorithm4iii
movl $2048, %edx
movl $2048, %esi
movl $2048, %edi
call _Z10Algorithm4iii
movl $4096, %edx
movl $4096, %esi
movl $4096, %edi
call _Z10Algorithm4iii
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "algorithm4.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $32, %edi
movl $32, %esi
movl $32, %edx
callq _Z10Algorithm4iii
movl $64, %edi
movl $64, %esi
movl $64, %edx
callq _Z10Algorithm4iii
movl $128, %edi
movl $128, %esi
movl $128, %edx
callq _Z10Algorithm4iii
movl $256, %edi # imm = 0x100
movl $256, %esi # imm = 0x100
movl $256, %edx # imm = 0x100
callq _Z10Algorithm4iii
movl $512, %edi # imm = 0x200
movl $512, %esi # imm = 0x200
movl $512, %edx # imm = 0x200
callq _Z10Algorithm4iii
movl $1024, %edi # imm = 0x400
movl $1024, %esi # imm = 0x400
movl $1024, %edx # imm = 0x400
callq _Z10Algorithm4iii
movl $2048, %edi # imm = 0x800
movl $2048, %esi # imm = 0x800
movl $2048, %edx # imm = 0x800
callq _Z10Algorithm4iii
movl $4096, %edi # imm = 0x1000
movl $4096, %esi # imm = 0x1000
movl $4096, %edx # imm = 0x1000
callq _Z10Algorithm4iii
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z10Algorithm4iii # -- Begin function _Z10Algorithm4iii
.p2align 4, 0x90
.type _Z10Algorithm4iii,@function
_Z10Algorithm4iii: # @_Z10Algorithm4iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r14d
movl %esi, %ebp
movl %edi, %r15d
xorl %eax, %eax
movq %rax, 32(%rsp) # 8-byte Spill
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 104(%rsp), %rdi
callq hipEventCreate
leaq 96(%rsp), %rdi
callq hipEventCreate
movl $0, 12(%rsp)
movl %ebp, %eax
imull %r15d, %eax
movslq %eax, %r12
shlq $3, %r12
movq %r12, %rdi
callq malloc
movq %rax, 24(%rsp) # 8-byte Spill
movl %r14d, %eax
imull %r15d, %eax
movslq %eax, %rbx
shlq $3, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, 88(%rsp) # 8-byte Spill
leaq 56(%rsp), %rdi
movq %r12, 120(%rsp) # 8-byte Spill
movq %r12, %rsi
callq hipMalloc
movq %r14, 128(%rsp) # 8-byte Spill
movl %r14d, %eax
imull %ebp, %eax
movslq %eax, %rsi
shlq $3, %rsi
leaq 48(%rsp), %rdi
movq %rsi, 112(%rsp) # 8-byte Spill
callq hipMalloc
leaq 40(%rsp), %rdi
movq %rbx, 136(%rsp) # 8-byte Spill
movq %rbx, %rsi
callq hipMalloc
movq %r15, 80(%rsp) # 8-byte Spill
testl %r15d, %r15d
movl %ebp, 8(%rsp) # 4-byte Spill
jle .LBB1_6
# %bb.1: # %.preheader89.lr.ph
movl 80(%rsp), %eax # 4-byte Reload
movq %rax, 144(%rsp) # 8-byte Spill
movl %ebp, %r12d
xorl %r13d, %r13d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r13
movl 8(%rsp), %ebp # 4-byte Reload
movq 32(%rsp), %rax # 8-byte Reload
addl %ebp, %eax
movq %rax, 32(%rsp) # 8-byte Spill
cmpq 144(%rsp), %r13 # 8-byte Folded Reload
je .LBB1_6
.LBB1_2: # %.preheader89
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %ebp, %ebp
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl 32(%rsp), %eax # 4-byte Reload
movq 88(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r15
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %rbp
movq 24(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%r14,%rbx,8)
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rbp,%rbx,8)
movq $0, (%r15,%rbx,8)
incq %rbx
cmpq %rbx, %r12
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge92
movq 56(%rsp), %rdi
movq 24(%rsp), %rsi # 8-byte Reload
movq 120(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq 16(%rsp), %rsi # 8-byte Reload
movq 112(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 80(%rsp), %rbp # 8-byte Reload
leal 63(%rbp), %r12d
movl %r12d, %r14d
shrl $6, %r14d
movq 128(%rsp), %r15 # 8-byte Reload
leal 15(%r15), %r13d
shrl $4, %r13d
movq %r13, %rbx
shlq $32, %rbx
orq %r14, %rbx
movq 104(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $.L.str.1, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movl %r13d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl $16, %esi
xorl %eax, %eax
callq printf
movl $.L.str.4, %edi
movl $4, %esi
xorl %eax, %eax
callq printf
andl $-64, %r12d
imull %r13d, %r12d
movl $.L.str.5, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movabsq $17179869200, %rdx # imm = 0x400000010
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 216(%rsp)
movq %rcx, 208(%rsp)
movq %rdx, 200(%rsp)
movl %ebp, 76(%rsp)
movl 8(%rsp), %eax # 4-byte Reload
movl %eax, 72(%rsp)
movl %r15d, 68(%rsp)
leaq 216(%rsp), %rax
movq %rax, 224(%rsp)
leaq 208(%rsp), %rax
movq %rax, 232(%rsp)
leaq 200(%rsp), %rax
movq %rax, 240(%rsp)
leaq 76(%rsp), %rax
movq %rax, 248(%rsp)
leaq 72(%rsp), %rax
movq %rax, 256(%rsp)
leaq 68(%rsp), %rax
movq %rax, 264(%rsp)
leaq 184(%rsp), %rdi
leaq 168(%rsp), %rsi
leaq 160(%rsp), %rdx
leaq 152(%rsp), %rcx
callq __hipPopCallConfiguration
movq 184(%rsp), %rsi
movl 192(%rsp), %edx
movq 168(%rsp), %rcx
movl 176(%rsp), %r8d
leaq 224(%rsp), %r9
movl $_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii, %edi
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8: # %._crit_edge94
movq 40(%rsp), %rsi
movq 88(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movq 136(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 104(%rsp), %rsi
movq 96(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi # 8-byte Reload
callq free
movq 16(%rsp), %rdi # 8-byte Reload
callq free
movq %rbx, %rdi
callq free
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10Algorithm4iii, .Lfunc_end1-_Z10Algorithm4iii
.cfi_endproc
# -- End function
.section .text._Z34__device_stub__device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii,"axG",@progbits,_Z34__device_stub__device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii,comdat
.weak _Z34__device_stub__device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii # -- Begin function _Z34__device_stub__device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.p2align 4, 0x90
.type _Z34__device_stub__device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii,@function
_Z34__device_stub__device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii: # @_Z34__device_stub__device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z34__device_stub__device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii, .Lfunc_end2-_Z34__device_stub__device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "inside function"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "nuumber of blocks in x = %d\n"
.size .L.str.1, 29
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "nuumber of blocks in y = %d\n"
.size .L.str.2, 29
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "number of threads in x = %d\n"
.size .L.str.3, 29
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "number of threads in y =%d\n"
.size .L.str.4, 28
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "total threads = %d"
.size .L.str.5, 19
.type _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii,@object # @_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.section .rodata._Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii,"aG",@progbits,_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii,comdat
.weak _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.p2align 3, 0x0
_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii:
.quad _Z34__device_stub__device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.size _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "elaspsed = %f ms\n\n\n"
.size .L.str.6, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii"
.size .L__unnamed_1, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19device_Matrix_multiILi16ELi4EEvPKdS1_Pdiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <sys/time.h>
#define SIZE 1024
__global__ void Add(int *c, int *a, int *b, int n){
int i = threadIdx.x;
if (i < n) {
c[i] = a[i] + b[i];
}
}
__global__ void Add_f(float *c, float *a, float *b, float n){
int i = threadIdx.x;
if (i < n) {
c[i] = a[i] + b[i];
}
}
/********************* calculate read and write bandwidth****************************/
int bandwidth(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
for (int i=1 ; i <= 1024*1024; i = i * 1024) {
double size_0 = i;
// Allocate memory block(in CPU), returns a pointer
a = (int *)malloc(size_0*sizeof(int));
b = (int *)malloc(size_0*sizeof(int));
c = (int *)malloc(size_0*sizeof(int));
// Allocate memory block(in GPU), returns a pointer
cudaMalloc( &d_a, size_0*sizeof(int));
cudaMalloc( &d_b, size_0*sizeof(int));
cudaMalloc( &d_c, size_0*sizeof(int));
// structure for calculate the interval
struct timeval start_read, end_read;
struct timeval start_write, end_write;
for (int j = 0; j < size_0; ++j) {
a[j] = j;
b[j] = j;
c[j] = 0;
}
gettimeofday(&start_read, NULL);
for (int i = 0; i < 1000000; i++) {
cudaMemcpy( d_a, a, size_0*sizeof(int), cudaMemcpyHostToDevice ); // copy memory from CPU to GPU
cudaMemcpy( d_b, b, size_0*sizeof(int), cudaMemcpyHostToDevice );
cudaMemcpy( d_c, c, size_0*sizeof(int), cudaMemcpyHostToDevice );
}
gettimeofday(&end_read, NULL);
// read_bandwidth = the size of memory copied from CPU to GPU / interval
float read_bandwidth = ((float)size_0*sizeof(int)*3*1000000)/(1000.0*(end_read.tv_sec-start_read.tv_sec)+(end_read.tv_usec-start_read.tv_usec)/1000.0);
// (((size_0/(1024*1024))*3)*(1e6))/ (1000*1000*(end_read.tv_sec - start_read.tv_sec) + (end_read.tv_usec - start_read.tv_usec));
printf ("with the size of %lf bytes, the read_bandwidth is %lf MBps\n ", size_0, read_bandwidth/1000.0);
Add<<< 1, size_0 >>>(a, b, c, size_0);
gettimeofday(&start_write, NULL);
for (int i = 0; i < 1000000; i++) {
cudaMemcpy( c, d_c, size_0*sizeof(int), cudaMemcpyDeviceToHost ); // copy memory from GPU to CPU
}
gettimeofday(&end_write, NULL);
// read_bandwidth = the size of memory copied from GPU to CPU / interval
float write_bandwidth = ((float)size_0*sizeof(int)*1000000)/ ((float)(end_write.tv_sec - start_write.tv_sec)*1000.0*1000.0 +(float)(end_write.tv_usec - start_write.tv_usec));
printf ("with the size of %lf bytes, the write_bandwidth is %lf MBps\n ", size_0, write_bandwidth);
}
// free memory
free(a);
free(b);
free(c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
}
/******************* claculate FLOPS and IOPS **********************/
int Operations(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
float *a_f, *b_f, *c_f;
float *d_a_f, *d_b_f, *d_c_f;
// declare interger and float variable(pointer) for calculation
a = (int *)malloc(SIZE*sizeof(int));
b = (int *)malloc(SIZE*sizeof(int));
c = (int *)malloc(SIZE*sizeof(int));
a_f = (float *)malloc(SIZE*sizeof(float));
b_f = (float *)malloc(SIZE*sizeof(float));
c_f = (float *)malloc(SIZE*sizeof(float));
cudaMalloc( &d_a, SIZE*sizeof(int));
cudaMalloc( &d_b, SIZE*sizeof(int));
cudaMalloc( &d_c, SIZE*sizeof(int));
cudaMalloc( &d_a_f, SIZE*sizeof(float));
cudaMalloc( &d_b_f, SIZE*sizeof(float));
cudaMalloc( &d_c_f, SIZE*sizeof(float));
struct timeval start_seq, end_seq;
struct timeval start_f, end_f;
int i = 0;
for (i = 0; i < SIZE; ++i) {
a[i] = i;
b[i] = i;
c[i] = 0;
}
for (i = 0; i < SIZE; ++i) {
a_f[i] = i * 1.0;
b_f[i] = i * 1.0;
c_f[i] = 0.0;
}
cudaMemcpy( d_a, a, SIZE*sizeof(int), cudaMemcpyHostToDevice );
cudaMemcpy( d_b, b, SIZE*sizeof(int), cudaMemcpyHostToDevice );
cudaMemcpy( d_c, c, SIZE*sizeof(int), cudaMemcpyHostToDevice );
cudaMemcpy( d_a_f, a_f, SIZE*sizeof(float), cudaMemcpyHostToDevice );
cudaMemcpy( d_b_f, b_f, SIZE*sizeof(float), cudaMemcpyHostToDevice );
cudaMemcpy( d_c_f, c_f, SIZE*sizeof(float), cudaMemcpyHostToDevice );
gettimeofday(&start_seq, NULL);
int n = 0;
// loop here is used to extend the operating time of CPU
for (n = 0; n < 1000; n++) {
Add<<< 1, SIZE >>>(a, b, c, SIZE); // calculate a[ ] + b[ ] (interger)
}
gettimeofday(&end_seq, NULL);
gettimeofday(&start_f, NULL);
for (n = 0; n < 1000; n++) {
Add_f<<< 1, SIZE >>>(a_f, b_f, c_f, SIZE); // calculate a[ ] + b[ ] (float)
}
gettimeofday(&end_f, NULL);
// IOPS = size * loop / interval
float IOPS = ((SIZE*1000)/ ((1000.0 * (end_seq.tv_sec - start_seq.tv_sec) + (end_seq.tv_usec - start_seq.tv_usec) / 1000.0)/1000)/1e9);
printf("the IOPS is %30f GIOPS\n", IOPS);
// FLOPS = size * loop / interval
float FLOPS = ((SIZE*1000)/ ((1000.0 * (end_f.tv_sec - start_f.tv_sec) + (end_f.tv_usec - start_f.tv_usec) / 1000.0)/1000)/1e9);
printf("the FLOPS is %30f GFLOPS\n", FLOPS);
//cudaMemcpy( c, d_c, SIZE*sizeof(int), cudaMemcpyDeviceToHost );
//for (int i = 0; i < 10; ++i) {
//printf("c[%d] = %d\n", i, c[i]);
//}
// free memory
free(a);
free(b);
free(c);
free(a_f);
free(b_f);
free(c_f);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
cudaFree(d_a_f);
cudaFree(d_b_f);
cudaFree(d_c_f);
return 0;
}
int main(void){
bandwidth();
Operations();
return 0;
}
|
code for sm_80
Function : _Z5Add_fPfS_S_f
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0020*/ I2F R0, R6 ; /* 0x0000000600007306 */
/* 0x001e240000201400 */
/*0030*/ FSETP.GEU.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0b */
/* 0x001fda0003f0e000 */
/*0040*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0050*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0070*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0080*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*00c0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00d0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3AddPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <sys/time.h>
#define SIZE 1024
__global__ void Add(int *c, int *a, int *b, int n){
int i = threadIdx.x;
if (i < n) {
c[i] = a[i] + b[i];
}
}
__global__ void Add_f(float *c, float *a, float *b, float n){
int i = threadIdx.x;
if (i < n) {
c[i] = a[i] + b[i];
}
}
/********************* calculate read and write bandwidth****************************/
int bandwidth(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
for (int i=1 ; i <= 1024*1024; i = i * 1024) {
double size_0 = i;
// Allocate memory block(in CPU), returns a pointer
a = (int *)malloc(size_0*sizeof(int));
b = (int *)malloc(size_0*sizeof(int));
c = (int *)malloc(size_0*sizeof(int));
// Allocate memory block(in GPU), returns a pointer
cudaMalloc( &d_a, size_0*sizeof(int));
cudaMalloc( &d_b, size_0*sizeof(int));
cudaMalloc( &d_c, size_0*sizeof(int));
// structure for calculate the interval
struct timeval start_read, end_read;
struct timeval start_write, end_write;
for (int j = 0; j < size_0; ++j) {
a[j] = j;
b[j] = j;
c[j] = 0;
}
gettimeofday(&start_read, NULL);
for (int i = 0; i < 1000000; i++) {
cudaMemcpy( d_a, a, size_0*sizeof(int), cudaMemcpyHostToDevice ); // copy memory from CPU to GPU
cudaMemcpy( d_b, b, size_0*sizeof(int), cudaMemcpyHostToDevice );
cudaMemcpy( d_c, c, size_0*sizeof(int), cudaMemcpyHostToDevice );
}
gettimeofday(&end_read, NULL);
// read_bandwidth = the size of memory copied from CPU to GPU / interval
float read_bandwidth = ((float)size_0*sizeof(int)*3*1000000)/(1000.0*(end_read.tv_sec-start_read.tv_sec)+(end_read.tv_usec-start_read.tv_usec)/1000.0);
// (((size_0/(1024*1024))*3)*(1e6))/ (1000*1000*(end_read.tv_sec - start_read.tv_sec) + (end_read.tv_usec - start_read.tv_usec));
printf ("with the size of %lf bytes, the read_bandwidth is %lf MBps\n ", size_0, read_bandwidth/1000.0);
Add<<< 1, size_0 >>>(a, b, c, size_0);
gettimeofday(&start_write, NULL);
for (int i = 0; i < 1000000; i++) {
cudaMemcpy( c, d_c, size_0*sizeof(int), cudaMemcpyDeviceToHost ); // copy memory from GPU to CPU
}
gettimeofday(&end_write, NULL);
// read_bandwidth = the size of memory copied from GPU to CPU / interval
float write_bandwidth = ((float)size_0*sizeof(int)*1000000)/ ((float)(end_write.tv_sec - start_write.tv_sec)*1000.0*1000.0 +(float)(end_write.tv_usec - start_write.tv_usec));
printf ("with the size of %lf bytes, the write_bandwidth is %lf MBps\n ", size_0, write_bandwidth);
}
// free memory
free(a);
free(b);
free(c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
}
/******************* claculate FLOPS and IOPS **********************/
int Operations(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
float *a_f, *b_f, *c_f;
float *d_a_f, *d_b_f, *d_c_f;
// declare interger and float variable(pointer) for calculation
a = (int *)malloc(SIZE*sizeof(int));
b = (int *)malloc(SIZE*sizeof(int));
c = (int *)malloc(SIZE*sizeof(int));
a_f = (float *)malloc(SIZE*sizeof(float));
b_f = (float *)malloc(SIZE*sizeof(float));
c_f = (float *)malloc(SIZE*sizeof(float));
cudaMalloc( &d_a, SIZE*sizeof(int));
cudaMalloc( &d_b, SIZE*sizeof(int));
cudaMalloc( &d_c, SIZE*sizeof(int));
cudaMalloc( &d_a_f, SIZE*sizeof(float));
cudaMalloc( &d_b_f, SIZE*sizeof(float));
cudaMalloc( &d_c_f, SIZE*sizeof(float));
struct timeval start_seq, end_seq;
struct timeval start_f, end_f;
int i = 0;
for (i = 0; i < SIZE; ++i) {
a[i] = i;
b[i] = i;
c[i] = 0;
}
for (i = 0; i < SIZE; ++i) {
a_f[i] = i * 1.0;
b_f[i] = i * 1.0;
c_f[i] = 0.0;
}
cudaMemcpy( d_a, a, SIZE*sizeof(int), cudaMemcpyHostToDevice );
cudaMemcpy( d_b, b, SIZE*sizeof(int), cudaMemcpyHostToDevice );
cudaMemcpy( d_c, c, SIZE*sizeof(int), cudaMemcpyHostToDevice );
cudaMemcpy( d_a_f, a_f, SIZE*sizeof(float), cudaMemcpyHostToDevice );
cudaMemcpy( d_b_f, b_f, SIZE*sizeof(float), cudaMemcpyHostToDevice );
cudaMemcpy( d_c_f, c_f, SIZE*sizeof(float), cudaMemcpyHostToDevice );
gettimeofday(&start_seq, NULL);
int n = 0;
// loop here is used to extend the operating time of CPU
for (n = 0; n < 1000; n++) {
Add<<< 1, SIZE >>>(a, b, c, SIZE); // calculate a[ ] + b[ ] (interger)
}
gettimeofday(&end_seq, NULL);
gettimeofday(&start_f, NULL);
for (n = 0; n < 1000; n++) {
Add_f<<< 1, SIZE >>>(a_f, b_f, c_f, SIZE); // calculate a[ ] + b[ ] (float)
}
gettimeofday(&end_f, NULL);
// IOPS = size * loop / interval
float IOPS = ((SIZE*1000)/ ((1000.0 * (end_seq.tv_sec - start_seq.tv_sec) + (end_seq.tv_usec - start_seq.tv_usec) / 1000.0)/1000)/1e9);
printf("the IOPS is %30f GIOPS\n", IOPS);
// FLOPS = size * loop / interval
float FLOPS = ((SIZE*1000)/ ((1000.0 * (end_f.tv_sec - start_f.tv_sec) + (end_f.tv_usec - start_f.tv_usec) / 1000.0)/1000)/1e9);
printf("the FLOPS is %30f GFLOPS\n", FLOPS);
//cudaMemcpy( c, d_c, SIZE*sizeof(int), cudaMemcpyDeviceToHost );
//for (int i = 0; i < 10; ++i) {
//printf("c[%d] = %d\n", i, c[i]);
//}
// free memory
free(a);
free(b);
free(c);
free(a_f);
free(b_f);
free(c_f);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
cudaFree(d_a_f);
cudaFree(d_b_f);
cudaFree(d_c_f);
return 0;
}
int main(void){
bandwidth();
Operations();
return 0;
}
|
.file "tmpxft_0018475b_00000000-6_CUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3AddPiS_S_iPiS_S_i
.type _Z27__device_stub__Z3AddPiS_S_iPiS_S_i, @function
_Z27__device_stub__Z3AddPiS_S_iPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3AddPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z27__device_stub__Z3AddPiS_S_iPiS_S_i, .-_Z27__device_stub__Z3AddPiS_S_iPiS_S_i
.globl _Z3AddPiS_S_i
.type _Z3AddPiS_S_i, @function
_Z3AddPiS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3AddPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z3AddPiS_S_i, .-_Z3AddPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "with the size of %lf bytes, the read_bandwidth is %lf MBps\n "
.align 8
.LC7:
.string "with the size of %lf bytes, the write_bandwidth is %lf MBps\n "
.text
.globl _Z9bandwidthv
.type _Z9bandwidthv, @function
_Z9bandwidthv:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $3, 12(%rsp)
movl $1, %r15d
jmp .L19
.L12:
subsd .LC1(%rip), %xmm0
cvttsd2siq %xmm0, %rbx
btcq $63, %rbx
.L13:
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %r15d, %r15d
jle .L14
movslq %r15d, %rdx
movl $0, %eax
.L15:
movl %eax, (%r14,%rax,4)
movl %eax, 0(%r13,%rax,4)
movl $0, (%r12,%rax,4)
addq $1, %rax
cmpq %rdx, %rax
jne .L15
.L14:
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1000000, %ebp
.L16:
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
subl $1, %ebp
jne .L16
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movsd (%rsp), %xmm6
pxor %xmm0, %xmm0
cvtsd2ss %xmm6, %xmm0
movaps %xmm0, %xmm4
mulss .LC2(%rip), %xmm4
movss %xmm4, 8(%rsp)
movaps %xmm4, %xmm1
mulss .LC3(%rip), %xmm1
mulss .LC4(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
movq 64(%rsp), %rax
subq 48(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movsd .LC5(%rip), %xmm2
mulsd %xmm2, %xmm0
movq 72(%rsp), %rax
subq 56(%rsp), %rax
pxor %xmm3, %xmm3
cvtsi2sdq %rax, %xmm3
divsd %xmm2, %xmm3
addsd %xmm3, %xmm0
divsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm1
cvtss2sd %xmm1, %xmm1
divsd %xmm2, %xmm1
movapd %xmm6, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl %r15d, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L17:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1000000, %ebp
.L18:
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
subl $1, %ebp
jne .L18
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movss 8(%rsp), %xmm1
mulss .LC4(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
movq 96(%rsp), %rax
subq 80(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
cvtss2sd %xmm0, %xmm0
movsd .LC5(%rip), %xmm2
mulsd %xmm2, %xmm0
mulsd %xmm2, %xmm0
movq 104(%rsp), %rax
subq 88(%rsp), %rax
pxor %xmm2, %xmm2
cvtsi2ssq %rax, %xmm2
cvtss2sd %xmm2, %xmm2
addsd %xmm2, %xmm0
divsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm1
cvtss2sd %xmm1, %xmm1
movsd (%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
sall $10, %r15d
subl $1, 12(%rsp)
je .L27
.L19:
pxor %xmm5, %xmm5
cvtsi2sdl %r15d, %xmm5
movsd %xmm5, (%rsp)
movsd .LC0(%rip), %xmm0
mulsd %xmm5, %xmm0
comisd .LC1(%rip), %xmm0
jnb .L12
cvttsd2siq %xmm0, %rbx
jmp .L13
.L26:
movl %r15d, %ecx
movq %r12, %rdx
movq %r13, %rsi
movq %r14, %rdi
call _Z27__device_stub__Z3AddPiS_S_iPiS_S_i
jmp .L17
.L27:
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z9bandwidthv, .-_Z9bandwidthv
.globl _Z29__device_stub__Z5Add_fPfS_S_fPfS_S_f
.type _Z29__device_stub__Z5Add_fPfS_S_fPfS_S_f, @function
_Z29__device_stub__Z5Add_fPfS_S_fPfS_S_f:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5Add_fPfS_S_f(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z29__device_stub__Z5Add_fPfS_S_fPfS_S_f, .-_Z29__device_stub__Z5Add_fPfS_S_fPfS_S_f
.globl _Z5Add_fPfS_S_f
.type _Z5Add_fPfS_S_f, @function
_Z5Add_fPfS_S_f:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5Add_fPfS_S_fPfS_S_f
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z5Add_fPfS_S_f, .-_Z5Add_fPfS_S_f
.section .rodata.str1.1,"aMS",@progbits,1
.LC12:
.string "the IOPS is %30f GIOPS\n"
.LC13:
.string "the FLOPS is %30f GFLOPS\n"
.text
.globl _Z10Operationsv
.type _Z10Operationsv, @function
_Z10Operationsv:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movl $4096, %edi
call malloc@PLT
movq %rax, %r15
movl $4096, %edi
call malloc@PLT
movq %rax, %r14
movl $4096, %edi
call malloc@PLT
movq %rax, %r13
movl $4096, %edi
call malloc@PLT
movq %rax, %r12
movl $4096, %edi
call malloc@PLT
movq %rax, %rbp
movl $4096, %edi
call malloc@PLT
movq %rax, 8(%rsp)
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $0, %eax
.L38:
movl %eax, (%r15,%rax,4)
movl %eax, (%r14,%rax,4)
movl $0, 0(%r13,%rax,4)
addq $1, %rax
cmpq $1024, %rax
jne .L38
movl $0, %eax
.L39:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r12,%rax,4)
movss %xmm0, 0(%rbp,%rax,4)
movq 8(%rsp), %rbx
movl $0x00000000, (%rbx,%rax,4)
addq $1, %rax
cmpq $1024, %rax
jne .L39
movl $1, %ecx
movl $4096, %edx
movq %r15, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %rbp, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq 8(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1000, %ebx
jmp .L41
.L40:
subl $1, %ebx
je .L50
.L41:
movl $1024, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 128(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L40
movl $1024, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq %r15, %rdi
call _Z27__device_stub__Z3AddPiS_S_iPiS_S_i
jmp .L40
.L50:
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 112(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1000, %ebx
jmp .L43
.L42:
subl $1, %ebx
je .L51
.L43:
movl $1024, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 128(%rsp), %rdx
movl $1, %ecx
movq 68(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L42
movss .LC9(%rip), %xmm0
movq 8(%rsp), %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z29__device_stub__Z5Add_fPfS_S_fPfS_S_f
jmp .L42
.L51:
leaq 128(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 96(%rsp), %rax
subq 80(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
mulsd .LC5(%rip), %xmm1
movq 104(%rsp), %rax
subq 88(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC5(%rip), %xmm0
addsd %xmm0, %xmm1
divsd .LC5(%rip), %xmm1
movsd .LC10(%rip), %xmm0
divsd %xmm1, %xmm0
divsd .LC11(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 128(%rsp), %rax
subq 112(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
mulsd .LC5(%rip), %xmm1
movq 136(%rsp), %rax
subq 120(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC5(%rip), %xmm0
addsd %xmm0, %xmm1
divsd .LC5(%rip), %xmm1
movsd .LC10(%rip), %xmm0
divsd %xmm1, %xmm0
divsd .LC11(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L52
movl $0, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z10Operationsv, .-_Z10Operationsv
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z9bandwidthv
call _Z10Operationsv
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z5Add_fPfS_S_f"
.LC15:
.string "_Z3AddPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z5Add_fPfS_S_f(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z3AddPiS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1074790400
.align 8
.LC1:
.long 0
.long 1138753536
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1082130432
.align 4
.LC3:
.long 1077936128
.align 4
.LC4:
.long 1232348160
.section .rodata.cst8
.align 8
.LC5:
.long 0
.long 1083129856
.section .rodata.cst4
.align 4
.LC9:
.long 1149239296
.section .rodata.cst8
.align 8
.LC10:
.long 0
.long 1093615616
.align 8
.LC11:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <sys/time.h>
#define SIZE 1024
__global__ void Add(int *c, int *a, int *b, int n){
int i = threadIdx.x;
if (i < n) {
c[i] = a[i] + b[i];
}
}
__global__ void Add_f(float *c, float *a, float *b, float n){
int i = threadIdx.x;
if (i < n) {
c[i] = a[i] + b[i];
}
}
/********************* calculate read and write bandwidth****************************/
int bandwidth(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
for (int i=1 ; i <= 1024*1024; i = i * 1024) {
double size_0 = i;
// Allocate memory block(in CPU), returns a pointer
a = (int *)malloc(size_0*sizeof(int));
b = (int *)malloc(size_0*sizeof(int));
c = (int *)malloc(size_0*sizeof(int));
// Allocate memory block(in GPU), returns a pointer
cudaMalloc( &d_a, size_0*sizeof(int));
cudaMalloc( &d_b, size_0*sizeof(int));
cudaMalloc( &d_c, size_0*sizeof(int));
// structure for calculate the interval
struct timeval start_read, end_read;
struct timeval start_write, end_write;
for (int j = 0; j < size_0; ++j) {
a[j] = j;
b[j] = j;
c[j] = 0;
}
gettimeofday(&start_read, NULL);
for (int i = 0; i < 1000000; i++) {
cudaMemcpy( d_a, a, size_0*sizeof(int), cudaMemcpyHostToDevice ); // copy memory from CPU to GPU
cudaMemcpy( d_b, b, size_0*sizeof(int), cudaMemcpyHostToDevice );
cudaMemcpy( d_c, c, size_0*sizeof(int), cudaMemcpyHostToDevice );
}
gettimeofday(&end_read, NULL);
// read_bandwidth = the size of memory copied from CPU to GPU / interval
float read_bandwidth = ((float)size_0*sizeof(int)*3*1000000)/(1000.0*(end_read.tv_sec-start_read.tv_sec)+(end_read.tv_usec-start_read.tv_usec)/1000.0);
// (((size_0/(1024*1024))*3)*(1e6))/ (1000*1000*(end_read.tv_sec - start_read.tv_sec) + (end_read.tv_usec - start_read.tv_usec));
printf ("with the size of %lf bytes, the read_bandwidth is %lf MBps\n ", size_0, read_bandwidth/1000.0);
Add<<< 1, size_0 >>>(a, b, c, size_0);
gettimeofday(&start_write, NULL);
for (int i = 0; i < 1000000; i++) {
cudaMemcpy( c, d_c, size_0*sizeof(int), cudaMemcpyDeviceToHost ); // copy memory from GPU to CPU
}
gettimeofday(&end_write, NULL);
// read_bandwidth = the size of memory copied from GPU to CPU / interval
float write_bandwidth = ((float)size_0*sizeof(int)*1000000)/ ((float)(end_write.tv_sec - start_write.tv_sec)*1000.0*1000.0 +(float)(end_write.tv_usec - start_write.tv_usec));
printf ("with the size of %lf bytes, the write_bandwidth is %lf MBps\n ", size_0, write_bandwidth);
}
// free memory
free(a);
free(b);
free(c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
}
/******************* claculate FLOPS and IOPS **********************/
int Operations(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
float *a_f, *b_f, *c_f;
float *d_a_f, *d_b_f, *d_c_f;
// declare interger and float variable(pointer) for calculation
a = (int *)malloc(SIZE*sizeof(int));
b = (int *)malloc(SIZE*sizeof(int));
c = (int *)malloc(SIZE*sizeof(int));
a_f = (float *)malloc(SIZE*sizeof(float));
b_f = (float *)malloc(SIZE*sizeof(float));
c_f = (float *)malloc(SIZE*sizeof(float));
cudaMalloc( &d_a, SIZE*sizeof(int));
cudaMalloc( &d_b, SIZE*sizeof(int));
cudaMalloc( &d_c, SIZE*sizeof(int));
cudaMalloc( &d_a_f, SIZE*sizeof(float));
cudaMalloc( &d_b_f, SIZE*sizeof(float));
cudaMalloc( &d_c_f, SIZE*sizeof(float));
struct timeval start_seq, end_seq;
struct timeval start_f, end_f;
int i = 0;
for (i = 0; i < SIZE; ++i) {
a[i] = i;
b[i] = i;
c[i] = 0;
}
for (i = 0; i < SIZE; ++i) {
a_f[i] = i * 1.0;
b_f[i] = i * 1.0;
c_f[i] = 0.0;
}
cudaMemcpy( d_a, a, SIZE*sizeof(int), cudaMemcpyHostToDevice );
cudaMemcpy( d_b, b, SIZE*sizeof(int), cudaMemcpyHostToDevice );
cudaMemcpy( d_c, c, SIZE*sizeof(int), cudaMemcpyHostToDevice );
cudaMemcpy( d_a_f, a_f, SIZE*sizeof(float), cudaMemcpyHostToDevice );
cudaMemcpy( d_b_f, b_f, SIZE*sizeof(float), cudaMemcpyHostToDevice );
cudaMemcpy( d_c_f, c_f, SIZE*sizeof(float), cudaMemcpyHostToDevice );
gettimeofday(&start_seq, NULL);
int n = 0;
// loop here is used to extend the operating time of CPU
for (n = 0; n < 1000; n++) {
Add<<< 1, SIZE >>>(a, b, c, SIZE); // calculate a[ ] + b[ ] (interger)
}
gettimeofday(&end_seq, NULL);
gettimeofday(&start_f, NULL);
for (n = 0; n < 1000; n++) {
Add_f<<< 1, SIZE >>>(a_f, b_f, c_f, SIZE); // calculate a[ ] + b[ ] (float)
}
gettimeofday(&end_f, NULL);
// IOPS = size * loop / interval
float IOPS = ((SIZE*1000)/ ((1000.0 * (end_seq.tv_sec - start_seq.tv_sec) + (end_seq.tv_usec - start_seq.tv_usec) / 1000.0)/1000)/1e9);
printf("the IOPS is %30f GIOPS\n", IOPS);
// FLOPS = size * loop / interval
float FLOPS = ((SIZE*1000)/ ((1000.0 * (end_f.tv_sec - start_f.tv_sec) + (end_f.tv_usec - start_f.tv_usec) / 1000.0)/1000)/1e9);
printf("the FLOPS is %30f GFLOPS\n", FLOPS);
//cudaMemcpy( c, d_c, SIZE*sizeof(int), cudaMemcpyDeviceToHost );
//for (int i = 0; i < 10; ++i) {
//printf("c[%d] = %d\n", i, c[i]);
//}
// free memory
free(a);
free(b);
free(c);
free(a_f);
free(b_f);
free(c_f);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
cudaFree(d_a_f);
cudaFree(d_b_f);
cudaFree(d_c_f);
return 0;
}
int main(void){
bandwidth();
Operations();
return 0;
}
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
#define SIZE 1024
__global__ void Add(int *c, int *a, int *b, int n){
int i = threadIdx.x;
if (i < n) {
c[i] = a[i] + b[i];
}
}
__global__ void Add_f(float *c, float *a, float *b, float n){
int i = threadIdx.x;
if (i < n) {
c[i] = a[i] + b[i];
}
}
/********************* calculate read and write bandwidth****************************/
int bandwidth(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
for (int i=1 ; i <= 1024*1024; i = i * 1024) {
double size_0 = i;
// Allocate memory block(in CPU), returns a pointer
a = (int *)malloc(size_0*sizeof(int));
b = (int *)malloc(size_0*sizeof(int));
c = (int *)malloc(size_0*sizeof(int));
// Allocate memory block(in GPU), returns a pointer
hipMalloc( &d_a, size_0*sizeof(int));
hipMalloc( &d_b, size_0*sizeof(int));
hipMalloc( &d_c, size_0*sizeof(int));
// structure for calculate the interval
struct timeval start_read, end_read;
struct timeval start_write, end_write;
for (int j = 0; j < size_0; ++j) {
a[j] = j;
b[j] = j;
c[j] = 0;
}
gettimeofday(&start_read, NULL);
for (int i = 0; i < 1000000; i++) {
hipMemcpy( d_a, a, size_0*sizeof(int), hipMemcpyHostToDevice ); // copy memory from CPU to GPU
hipMemcpy( d_b, b, size_0*sizeof(int), hipMemcpyHostToDevice );
hipMemcpy( d_c, c, size_0*sizeof(int), hipMemcpyHostToDevice );
}
gettimeofday(&end_read, NULL);
// read_bandwidth = the size of memory copied from CPU to GPU / interval
float read_bandwidth = ((float)size_0*sizeof(int)*3*1000000)/(1000.0*(end_read.tv_sec-start_read.tv_sec)+(end_read.tv_usec-start_read.tv_usec)/1000.0);
// (((size_0/(1024*1024))*3)*(1e6))/ (1000*1000*(end_read.tv_sec - start_read.tv_sec) + (end_read.tv_usec - start_read.tv_usec));
printf ("with the size of %lf bytes, the read_bandwidth is %lf MBps\n ", size_0, read_bandwidth/1000.0);
Add<<< 1, size_0 >>>(a, b, c, size_0);
gettimeofday(&start_write, NULL);
for (int i = 0; i < 1000000; i++) {
hipMemcpy( c, d_c, size_0*sizeof(int), hipMemcpyDeviceToHost ); // copy memory from GPU to CPU
}
gettimeofday(&end_write, NULL);
// read_bandwidth = the size of memory copied from GPU to CPU / interval
float write_bandwidth = ((float)size_0*sizeof(int)*1000000)/ ((float)(end_write.tv_sec - start_write.tv_sec)*1000.0*1000.0 +(float)(end_write.tv_usec - start_write.tv_usec));
printf ("with the size of %lf bytes, the write_bandwidth is %lf MBps\n ", size_0, write_bandwidth);
}
// free memory
free(a);
free(b);
free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
}
/******************* claculate FLOPS and IOPS **********************/
int Operations(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
float *a_f, *b_f, *c_f;
float *d_a_f, *d_b_f, *d_c_f;
// declare interger and float variable(pointer) for calculation
a = (int *)malloc(SIZE*sizeof(int));
b = (int *)malloc(SIZE*sizeof(int));
c = (int *)malloc(SIZE*sizeof(int));
a_f = (float *)malloc(SIZE*sizeof(float));
b_f = (float *)malloc(SIZE*sizeof(float));
c_f = (float *)malloc(SIZE*sizeof(float));
hipMalloc( &d_a, SIZE*sizeof(int));
hipMalloc( &d_b, SIZE*sizeof(int));
hipMalloc( &d_c, SIZE*sizeof(int));
hipMalloc( &d_a_f, SIZE*sizeof(float));
hipMalloc( &d_b_f, SIZE*sizeof(float));
hipMalloc( &d_c_f, SIZE*sizeof(float));
struct timeval start_seq, end_seq;
struct timeval start_f, end_f;
int i = 0;
for (i = 0; i < SIZE; ++i) {
a[i] = i;
b[i] = i;
c[i] = 0;
}
for (i = 0; i < SIZE; ++i) {
a_f[i] = i * 1.0;
b_f[i] = i * 1.0;
c_f[i] = 0.0;
}
hipMemcpy( d_a, a, SIZE*sizeof(int), hipMemcpyHostToDevice );
hipMemcpy( d_b, b, SIZE*sizeof(int), hipMemcpyHostToDevice );
hipMemcpy( d_c, c, SIZE*sizeof(int), hipMemcpyHostToDevice );
hipMemcpy( d_a_f, a_f, SIZE*sizeof(float), hipMemcpyHostToDevice );
hipMemcpy( d_b_f, b_f, SIZE*sizeof(float), hipMemcpyHostToDevice );
hipMemcpy( d_c_f, c_f, SIZE*sizeof(float), hipMemcpyHostToDevice );
gettimeofday(&start_seq, NULL);
int n = 0;
// loop here is used to extend the operating time of CPU
for (n = 0; n < 1000; n++) {
Add<<< 1, SIZE >>>(a, b, c, SIZE); // calculate a[ ] + b[ ] (interger)
}
gettimeofday(&end_seq, NULL);
gettimeofday(&start_f, NULL);
for (n = 0; n < 1000; n++) {
Add_f<<< 1, SIZE >>>(a_f, b_f, c_f, SIZE); // calculate a[ ] + b[ ] (float)
}
gettimeofday(&end_f, NULL);
// IOPS = size * loop / interval
float IOPS = ((SIZE*1000)/ ((1000.0 * (end_seq.tv_sec - start_seq.tv_sec) + (end_seq.tv_usec - start_seq.tv_usec) / 1000.0)/1000)/1e9);
printf("the IOPS is %30f GIOPS\n", IOPS);
// FLOPS = size * loop / interval
float FLOPS = ((SIZE*1000)/ ((1000.0 * (end_f.tv_sec - start_f.tv_sec) + (end_f.tv_usec - start_f.tv_usec) / 1000.0)/1000)/1e9);
printf("the FLOPS is %30f GFLOPS\n", FLOPS);
//cudaMemcpy( c, d_c, SIZE*sizeof(int), cudaMemcpyDeviceToHost );
//for (int i = 0; i < 10; ++i) {
//printf("c[%d] = %d\n", i, c[i]);
//}
// free memory
free(a);
free(b);
free(c);
free(a_f);
free(b_f);
free(c_f);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
hipFree(d_a_f);
hipFree(d_b_f);
hipFree(d_c_f);
return 0;
}
int main(void){
bandwidth();
Operations();
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
#define SIZE 1024
__global__ void Add(int *c, int *a, int *b, int n){
int i = threadIdx.x;
if (i < n) {
c[i] = a[i] + b[i];
}
}
__global__ void Add_f(float *c, float *a, float *b, float n){
int i = threadIdx.x;
if (i < n) {
c[i] = a[i] + b[i];
}
}
/********************* calculate read and write bandwidth****************************/
int bandwidth(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
for (int i=1 ; i <= 1024*1024; i = i * 1024) {
double size_0 = i;
// Allocate memory block(in CPU), returns a pointer
a = (int *)malloc(size_0*sizeof(int));
b = (int *)malloc(size_0*sizeof(int));
c = (int *)malloc(size_0*sizeof(int));
// Allocate memory block(in GPU), returns a pointer
hipMalloc( &d_a, size_0*sizeof(int));
hipMalloc( &d_b, size_0*sizeof(int));
hipMalloc( &d_c, size_0*sizeof(int));
// structure for calculate the interval
struct timeval start_read, end_read;
struct timeval start_write, end_write;
for (int j = 0; j < size_0; ++j) {
a[j] = j;
b[j] = j;
c[j] = 0;
}
gettimeofday(&start_read, NULL);
for (int i = 0; i < 1000000; i++) {
hipMemcpy( d_a, a, size_0*sizeof(int), hipMemcpyHostToDevice ); // copy memory from CPU to GPU
hipMemcpy( d_b, b, size_0*sizeof(int), hipMemcpyHostToDevice );
hipMemcpy( d_c, c, size_0*sizeof(int), hipMemcpyHostToDevice );
}
gettimeofday(&end_read, NULL);
// read_bandwidth = the size of memory copied from CPU to GPU / interval
float read_bandwidth = ((float)size_0*sizeof(int)*3*1000000)/(1000.0*(end_read.tv_sec-start_read.tv_sec)+(end_read.tv_usec-start_read.tv_usec)/1000.0);
// (((size_0/(1024*1024))*3)*(1e6))/ (1000*1000*(end_read.tv_sec - start_read.tv_sec) + (end_read.tv_usec - start_read.tv_usec));
printf ("with the size of %lf bytes, the read_bandwidth is %lf MBps\n ", size_0, read_bandwidth/1000.0);
Add<<< 1, size_0 >>>(a, b, c, size_0);
gettimeofday(&start_write, NULL);
for (int i = 0; i < 1000000; i++) {
hipMemcpy( c, d_c, size_0*sizeof(int), hipMemcpyDeviceToHost ); // copy memory from GPU to CPU
}
gettimeofday(&end_write, NULL);
// read_bandwidth = the size of memory copied from GPU to CPU / interval
float write_bandwidth = ((float)size_0*sizeof(int)*1000000)/ ((float)(end_write.tv_sec - start_write.tv_sec)*1000.0*1000.0 +(float)(end_write.tv_usec - start_write.tv_usec));
printf ("with the size of %lf bytes, the write_bandwidth is %lf MBps\n ", size_0, write_bandwidth);
}
// free memory
free(a);
free(b);
free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
}
/******************* claculate FLOPS and IOPS **********************/
int Operations(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
float *a_f, *b_f, *c_f;
float *d_a_f, *d_b_f, *d_c_f;
// declare interger and float variable(pointer) for calculation
a = (int *)malloc(SIZE*sizeof(int));
b = (int *)malloc(SIZE*sizeof(int));
c = (int *)malloc(SIZE*sizeof(int));
a_f = (float *)malloc(SIZE*sizeof(float));
b_f = (float *)malloc(SIZE*sizeof(float));
c_f = (float *)malloc(SIZE*sizeof(float));
hipMalloc( &d_a, SIZE*sizeof(int));
hipMalloc( &d_b, SIZE*sizeof(int));
hipMalloc( &d_c, SIZE*sizeof(int));
hipMalloc( &d_a_f, SIZE*sizeof(float));
hipMalloc( &d_b_f, SIZE*sizeof(float));
hipMalloc( &d_c_f, SIZE*sizeof(float));
struct timeval start_seq, end_seq;
struct timeval start_f, end_f;
int i = 0;
for (i = 0; i < SIZE; ++i) {
a[i] = i;
b[i] = i;
c[i] = 0;
}
for (i = 0; i < SIZE; ++i) {
a_f[i] = i * 1.0;
b_f[i] = i * 1.0;
c_f[i] = 0.0;
}
hipMemcpy( d_a, a, SIZE*sizeof(int), hipMemcpyHostToDevice );
hipMemcpy( d_b, b, SIZE*sizeof(int), hipMemcpyHostToDevice );
hipMemcpy( d_c, c, SIZE*sizeof(int), hipMemcpyHostToDevice );
hipMemcpy( d_a_f, a_f, SIZE*sizeof(float), hipMemcpyHostToDevice );
hipMemcpy( d_b_f, b_f, SIZE*sizeof(float), hipMemcpyHostToDevice );
hipMemcpy( d_c_f, c_f, SIZE*sizeof(float), hipMemcpyHostToDevice );
gettimeofday(&start_seq, NULL);
int n = 0;
// loop here is used to extend the operating time of CPU
for (n = 0; n < 1000; n++) {
Add<<< 1, SIZE >>>(a, b, c, SIZE); // calculate a[ ] + b[ ] (interger)
}
gettimeofday(&end_seq, NULL);
gettimeofday(&start_f, NULL);
for (n = 0; n < 1000; n++) {
Add_f<<< 1, SIZE >>>(a_f, b_f, c_f, SIZE); // calculate a[ ] + b[ ] (float)
}
gettimeofday(&end_f, NULL);
// IOPS = size * loop / interval
float IOPS = ((SIZE*1000)/ ((1000.0 * (end_seq.tv_sec - start_seq.tv_sec) + (end_seq.tv_usec - start_seq.tv_usec) / 1000.0)/1000)/1e9);
printf("the IOPS is %30f GIOPS\n", IOPS);
// FLOPS = size * loop / interval
float FLOPS = ((SIZE*1000)/ ((1000.0 * (end_f.tv_sec - start_f.tv_sec) + (end_f.tv_usec - start_f.tv_usec) / 1000.0)/1000)/1e9);
printf("the FLOPS is %30f GFLOPS\n", FLOPS);
//cudaMemcpy( c, d_c, SIZE*sizeof(int), cudaMemcpyDeviceToHost );
//for (int i = 0; i < 10; ++i) {
//printf("c[%d] = %d\n", i, c[i]);
//}
// free memory
free(a);
free(b);
free(c);
free(a_f);
free(b_f);
free(c_f);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
hipFree(d_a_f);
hipFree(d_b_f);
hipFree(d_c_f);
return 0;
}
int main(void){
bandwidth();
Operations();
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3AddPiS_S_i
.globl _Z3AddPiS_S_i
.p2align 8
.type _Z3AddPiS_S_i,@function
_Z3AddPiS_S_i:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[4:5]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3AddPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3AddPiS_S_i, .Lfunc_end0-_Z3AddPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5Add_fPfS_S_f
.globl _Z5Add_fPfS_S_f
.p2align 8
.type _Z5Add_fPfS_S_f,@function
_Z5Add_fPfS_S_f:
s_load_b32 s2, s[0:1], 0x18
v_cvt_f32_i32_e32 v1, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_f32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[4:5]
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5Add_fPfS_S_f
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z5Add_fPfS_S_f, .Lfunc_end1-_Z5Add_fPfS_S_f
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3AddPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z3AddPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5Add_fPfS_S_f
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z5Add_fPfS_S_f.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
#define SIZE 1024
__global__ void Add(int *c, int *a, int *b, int n){
int i = threadIdx.x;
if (i < n) {
c[i] = a[i] + b[i];
}
}
__global__ void Add_f(float *c, float *a, float *b, float n){
int i = threadIdx.x;
if (i < n) {
c[i] = a[i] + b[i];
}
}
/********************* calculate read and write bandwidth****************************/
int bandwidth(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
for (int i=1 ; i <= 1024*1024; i = i * 1024) {
double size_0 = i;
// Allocate memory block(in CPU), returns a pointer
a = (int *)malloc(size_0*sizeof(int));
b = (int *)malloc(size_0*sizeof(int));
c = (int *)malloc(size_0*sizeof(int));
// Allocate memory block(in GPU), returns a pointer
hipMalloc( &d_a, size_0*sizeof(int));
hipMalloc( &d_b, size_0*sizeof(int));
hipMalloc( &d_c, size_0*sizeof(int));
// structure for calculate the interval
struct timeval start_read, end_read;
struct timeval start_write, end_write;
for (int j = 0; j < size_0; ++j) {
a[j] = j;
b[j] = j;
c[j] = 0;
}
gettimeofday(&start_read, NULL);
for (int i = 0; i < 1000000; i++) {
hipMemcpy( d_a, a, size_0*sizeof(int), hipMemcpyHostToDevice ); // copy memory from CPU to GPU
hipMemcpy( d_b, b, size_0*sizeof(int), hipMemcpyHostToDevice );
hipMemcpy( d_c, c, size_0*sizeof(int), hipMemcpyHostToDevice );
}
gettimeofday(&end_read, NULL);
// read_bandwidth = the size of memory copied from CPU to GPU / interval
float read_bandwidth = ((float)size_0*sizeof(int)*3*1000000)/(1000.0*(end_read.tv_sec-start_read.tv_sec)+(end_read.tv_usec-start_read.tv_usec)/1000.0);
// (((size_0/(1024*1024))*3)*(1e6))/ (1000*1000*(end_read.tv_sec - start_read.tv_sec) + (end_read.tv_usec - start_read.tv_usec));
printf ("with the size of %lf bytes, the read_bandwidth is %lf MBps\n ", size_0, read_bandwidth/1000.0);
Add<<< 1, size_0 >>>(a, b, c, size_0);
gettimeofday(&start_write, NULL);
for (int i = 0; i < 1000000; i++) {
hipMemcpy( c, d_c, size_0*sizeof(int), hipMemcpyDeviceToHost ); // copy memory from GPU to CPU
}
gettimeofday(&end_write, NULL);
// read_bandwidth = the size of memory copied from GPU to CPU / interval
float write_bandwidth = ((float)size_0*sizeof(int)*1000000)/ ((float)(end_write.tv_sec - start_write.tv_sec)*1000.0*1000.0 +(float)(end_write.tv_usec - start_write.tv_usec));
printf ("with the size of %lf bytes, the write_bandwidth is %lf MBps\n ", size_0, write_bandwidth);
}
// free memory
free(a);
free(b);
free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
}
/******************* claculate FLOPS and IOPS **********************/
int Operations(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
float *a_f, *b_f, *c_f;
float *d_a_f, *d_b_f, *d_c_f;
// declare interger and float variable(pointer) for calculation
a = (int *)malloc(SIZE*sizeof(int));
b = (int *)malloc(SIZE*sizeof(int));
c = (int *)malloc(SIZE*sizeof(int));
a_f = (float *)malloc(SIZE*sizeof(float));
b_f = (float *)malloc(SIZE*sizeof(float));
c_f = (float *)malloc(SIZE*sizeof(float));
hipMalloc( &d_a, SIZE*sizeof(int));
hipMalloc( &d_b, SIZE*sizeof(int));
hipMalloc( &d_c, SIZE*sizeof(int));
hipMalloc( &d_a_f, SIZE*sizeof(float));
hipMalloc( &d_b_f, SIZE*sizeof(float));
hipMalloc( &d_c_f, SIZE*sizeof(float));
struct timeval start_seq, end_seq;
struct timeval start_f, end_f;
int i = 0;
for (i = 0; i < SIZE; ++i) {
a[i] = i;
b[i] = i;
c[i] = 0;
}
for (i = 0; i < SIZE; ++i) {
a_f[i] = i * 1.0;
b_f[i] = i * 1.0;
c_f[i] = 0.0;
}
hipMemcpy( d_a, a, SIZE*sizeof(int), hipMemcpyHostToDevice );
hipMemcpy( d_b, b, SIZE*sizeof(int), hipMemcpyHostToDevice );
hipMemcpy( d_c, c, SIZE*sizeof(int), hipMemcpyHostToDevice );
hipMemcpy( d_a_f, a_f, SIZE*sizeof(float), hipMemcpyHostToDevice );
hipMemcpy( d_b_f, b_f, SIZE*sizeof(float), hipMemcpyHostToDevice );
hipMemcpy( d_c_f, c_f, SIZE*sizeof(float), hipMemcpyHostToDevice );
gettimeofday(&start_seq, NULL);
int n = 0;
// loop here is used to extend the operating time of CPU
for (n = 0; n < 1000; n++) {
Add<<< 1, SIZE >>>(a, b, c, SIZE); // calculate a[ ] + b[ ] (interger)
}
gettimeofday(&end_seq, NULL);
gettimeofday(&start_f, NULL);
for (n = 0; n < 1000; n++) {
Add_f<<< 1, SIZE >>>(a_f, b_f, c_f, SIZE); // calculate a[ ] + b[ ] (float)
}
gettimeofday(&end_f, NULL);
// IOPS = size * loop / interval
float IOPS = ((SIZE*1000)/ ((1000.0 * (end_seq.tv_sec - start_seq.tv_sec) + (end_seq.tv_usec - start_seq.tv_usec) / 1000.0)/1000)/1e9);
printf("the IOPS is %30f GIOPS\n", IOPS);
// FLOPS = size * loop / interval
float FLOPS = ((SIZE*1000)/ ((1000.0 * (end_f.tv_sec - start_f.tv_sec) + (end_f.tv_usec - start_f.tv_usec) / 1000.0)/1000)/1e9);
printf("the FLOPS is %30f GFLOPS\n", FLOPS);
//cudaMemcpy( c, d_c, SIZE*sizeof(int), cudaMemcpyDeviceToHost );
//for (int i = 0; i < 10; ++i) {
//printf("c[%d] = %d\n", i, c[i]);
//}
// free memory
free(a);
free(b);
free(c);
free(a_f);
free(b_f);
free(c_f);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
hipFree(d_a_f);
hipFree(d_b_f);
hipFree(d_c_f);
return 0;
}
int main(void){
bandwidth();
Operations();
return 0;
}
|
.text
.file "CUDA.hip"
.globl _Z18__device_stub__AddPiS_S_i # -- Begin function _Z18__device_stub__AddPiS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__AddPiS_S_i,@function
_Z18__device_stub__AddPiS_S_i: # @_Z18__device_stub__AddPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3AddPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__AddPiS_S_i, .Lfunc_end0-_Z18__device_stub__AddPiS_S_i
.cfi_endproc
# -- End function
.globl _Z20__device_stub__Add_fPfS_S_f # -- Begin function _Z20__device_stub__Add_fPfS_S_f
.p2align 4, 0x90
.type _Z20__device_stub__Add_fPfS_S_f,@function
_Z20__device_stub__Add_fPfS_S_f: # @_Z20__device_stub__Add_fPfS_S_f
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5Add_fPfS_S_f, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z20__device_stub__Add_fPfS_S_f, .Lfunc_end1-_Z20__device_stub__Add_fPfS_S_f
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9bandwidthv
.LCPI2_0:
.quad 0x4010000000000000 # double 4
.LCPI2_1:
.quad 0x43e0000000000000 # double 9.2233720368547758E+18
.LCPI2_5:
.quad 0x408f400000000000 # double 1000
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_2:
.long 0x40800000 # float 4
.LCPI2_3:
.long 0x40400000 # float 3
.LCPI2_4:
.long 0x49742400 # float 1.0E+6
.text
.globl _Z9bandwidthv
.p2align 4, 0x90
.type _Z9bandwidthv,@function
_Z9bandwidthv: # @_Z9bandwidthv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967296, %rax # imm = 0x100000000
movl $1, %r14d
incq %rax
movq %rax, 104(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
# Child Loop BB2_4 Depth 2
# Child Loop BB2_8 Depth 2
xorps %xmm0, %xmm0
cvtsi2sd %r14d, %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
mulsd .LCPI2_0(%rip), %xmm0
cvttsd2si %xmm0, %rax
movq %rax, %rcx
sarq $63, %rcx
subsd .LCPI2_1(%rip), %xmm0
cvttsd2si %xmm0, %rbx
andq %rcx, %rbx
orq %rax, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r15
movq %rbx, %rdi
callq malloc
movq %rax, %r12
movq %rbx, %rdi
callq malloc
movq %rax, %r13
leaq 56(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movsd 8(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %eax, (%r15,%rax,4)
movl %eax, (%r12,%rax,4)
movl $0, (%r13,%rax,4)
incq %rax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
ucomisd %xmm0, %xmm1
ja .LBB2_2
# %bb.3: # %._crit_edge
# in Loop: Header=BB2_1 Depth=1
leaq 184(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $1000000, %ebp # imm = 0xF4240
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movq 56(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq %r12, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
decl %ebp
jne .LBB2_4
# %bb.5: # in Loop: Header=BB2_1 Depth=1
leaq 168(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2ss %r14d, %xmm0
mulss .LCPI2_2(%rip), %xmm0
movss %xmm0, 24(%rsp) # 4-byte Spill
mulss .LCPI2_3(%rip), %xmm0
mulss .LCPI2_4(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq 168(%rsp), %rax
movq 176(%rsp), %rcx
subq 184(%rsp), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
subq 192(%rsp), %rcx
cvtsi2sd %rcx, %xmm2
movsd .LCPI2_5(%rip), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm3, %xmm1
divsd %xmm3, %xmm2
addsd %xmm1, %xmm2
divsd %xmm2, %xmm0
cvtsd2ss %xmm0, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
divsd %xmm3, %xmm1
movl $.L.str, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $2, %al
callq printf
movl %r14d, %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdx
movq 104(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6: # in Loop: Header=BB2_1 Depth=1
movq %r15, 160(%rsp)
movq %r12, 152(%rsp)
movq %r13, 144(%rsp)
movl %r14d, 28(%rsp)
leaq 160(%rsp), %rax
movq %rax, 64(%rsp)
leaq 152(%rsp), %rax
movq %rax, 72(%rsp)
leaq 144(%rsp), %rax
movq %rax, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 88(%rsp)
leaq 32(%rsp), %rdi
leaq 128(%rsp), %rsi
leaq 120(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 128(%rsp), %rcx
movl 136(%rsp), %r8d
movl $_Z3AddPiS_S_i, %edi
leaq 64(%rsp), %r9
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7: # in Loop: Header=BB2_1 Depth=1
leaq 64(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $1000000, %ebp # imm = 0xF4240
.p2align 4, 0x90
.LBB2_8: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movq 16(%rsp), %rsi
movq %r13, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
decl %ebp
jne .LBB2_8
# %bb.9: # in Loop: Header=BB2_1 Depth=1
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 32(%rsp), %rax
subq 64(%rsp), %rax
movss 24(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
mulss .LCPI2_4(%rip), %xmm1
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
cvtss2sd %xmm1, %xmm1
movq 40(%rsp), %rax
subq 72(%rsp), %rax
cvtss2sd %xmm0, %xmm0
xorps %xmm2, %xmm2
cvtsi2ss %rax, %xmm2
movsd .LCPI2_5(%rip), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm3, %xmm0
mulsd %xmm3, %xmm0
cvtss2sd %xmm2, %xmm2
addsd %xmm0, %xmm2
divsd %xmm2, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movl $.L.str.1, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $2, %al
callq printf
movl %r14d, %eax
shll $10, %eax
cmpl $1025, %r14d # imm = 0x401
movl %eax, %r14d
jb .LBB2_1
# %bb.10:
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq %r13, %rdi
callq free
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9bandwidthv, .Lfunc_end2-_Z9bandwidthv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z10Operationsv
.LCPI3_0:
.quad 0x408f400000000000 # double 1000
.LCPI3_1:
.quad 0x412f400000000000 # double 1024000
.LCPI3_2:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl _Z10Operationsv
.p2align 4, 0x90
.type _Z10Operationsv,@function
_Z10Operationsv: # @_Z10Operationsv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbp
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r15
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r12
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r13
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, 8(%rsp) # 8-byte Spill
leaq 216(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 208(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 200(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 192(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 184(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 176(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
xorl %ebx, %ebx
movl $4096, %edx # imm = 0x1000
movq %r15, 16(%rsp) # 8-byte Spill
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movl %ebx, (%rbp,%rbx,4)
movl %ebx, (%r14,%rbx,4)
incq %rbx
cmpq $1024, %rbx # imm = 0x400
jne .LBB3_1
# %bb.2: # %.preheader.preheader
xorl %ebx, %ebx
movl $4096, %edx # imm = 0x1000
movq 8(%rsp), %rdi # 8-byte Reload
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB3_3: # %.preheader
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ebx, %xmm0
movss %xmm0, (%r12,%rbx,4)
movss %xmm0, (%r13,%rbx,4)
incq %rbx
cmpq $1024, %rbx # imm = 0x400
jne .LBB3_3
# %bb.4:
movabsq $4294967297, %r15 # imm = 0x100000001
movq 216(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %rbp, 136(%rsp) # 8-byte Spill
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpy
movq 208(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 200(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq 16(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 192(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 184(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movq 176(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq 8(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
leaq 232(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $1000, %ebx # imm = 0x3E8
leaq 1023(%r15), %rbp
jmp .LBB3_5
.p2align 4, 0x90
.LBB3_7: # in Loop: Header=BB3_5 Depth=1
decl %ebx
je .LBB3_8
.LBB3_5: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_7
# %bb.6: # in Loop: Header=BB3_5 Depth=1
movq 136(%rsp), %rax # 8-byte Reload
movq %rax, 80(%rsp)
movq %r14, 64(%rsp)
movq 16(%rsp), %rax # 8-byte Reload
movq %rax, 48(%rsp)
movl $1024, 24(%rsp) # imm = 0x400
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rdi
leaq 144(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 160(%rsp), %rsi
movl 168(%rsp), %edx
movq 144(%rsp), %rcx
movl 152(%rsp), %r8d
movl $_Z3AddPiS_S_i, %edi
leaq 96(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_7
.LBB3_8:
leaq 160(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
leaq 144(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $1000, %ebx # imm = 0x3E8
jmp .LBB3_9
.p2align 4, 0x90
.LBB3_11: # in Loop: Header=BB3_9 Depth=1
decl %ebx
je .LBB3_12
.LBB3_9: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_11
# %bb.10: # in Loop: Header=BB3_9 Depth=1
movq %r12, 48(%rsp)
movq %r13, 40(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movq %rax, 32(%rsp)
movl $1149239296, 60(%rsp) # imm = 0x44800000
leaq 48(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rax
movq %rax, 112(%rsp)
leaq 60(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 224(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z5Add_fPfS_S_f, %edi
leaq 96(%rsp), %r9
pushq 224(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_11
.LBB3_12:
leaq 96(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 160(%rsp), %rax
subq 232(%rsp), %rax
movq 168(%rsp), %rcx
cvtsi2sd %rax, %xmm0
movsd .LCPI3_0(%rip), %xmm2 # xmm2 = mem[0],zero
subq 240(%rsp), %rcx
cvtsi2sd %rcx, %xmm1
mulsd %xmm2, %xmm0
divsd %xmm2, %xmm1
addsd %xmm0, %xmm1
divsd %xmm2, %xmm1
movsd .LCPI3_1(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
divsd .LCPI3_2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq 96(%rsp), %rax
subq 144(%rsp), %rax
movq 104(%rsp), %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd .LCPI3_0(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm2, %xmm0
subq 152(%rsp), %rcx
xorps %xmm1, %xmm1
cvtsi2sd %rcx, %xmm1
divsd %xmm2, %xmm1
addsd %xmm0, %xmm1
divsd %xmm2, %xmm1
movsd .LCPI3_1(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
divsd .LCPI3_2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 136(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
movq 16(%rsp), %rdi # 8-byte Reload
callq free
movq %r12, %rdi
callq free
movq %r13, %rdi
callq free
movq 8(%rsp), %rdi # 8-byte Reload
callq free
movq 216(%rsp), %rdi
callq hipFree
movq 208(%rsp), %rdi
callq hipFree
movq 200(%rsp), %rdi
callq hipFree
movq 192(%rsp), %rdi
callq hipFree
movq 184(%rsp), %rdi
callq hipFree
movq 176(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z10Operationsv, .Lfunc_end3-_Z10Operationsv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z9bandwidthv
callq _Z10Operationsv
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3AddPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5Add_fPfS_S_f, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3AddPiS_S_i,@object # @_Z3AddPiS_S_i
.section .rodata,"a",@progbits
.globl _Z3AddPiS_S_i
.p2align 3, 0x0
_Z3AddPiS_S_i:
.quad _Z18__device_stub__AddPiS_S_i
.size _Z3AddPiS_S_i, 8
.type _Z5Add_fPfS_S_f,@object # @_Z5Add_fPfS_S_f
.globl _Z5Add_fPfS_S_f
.p2align 3, 0x0
_Z5Add_fPfS_S_f:
.quad _Z20__device_stub__Add_fPfS_S_f
.size _Z5Add_fPfS_S_f, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "with the size of %lf bytes, the read_bandwidth is %lf MBps\n "
.size .L.str, 61
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "with the size of %lf bytes, the write_bandwidth is %lf MBps\n "
.size .L.str.1, 62
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "the IOPS is %30f GIOPS\n"
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "the FLOPS is %30f GFLOPS\n"
.size .L.str.3, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3AddPiS_S_i"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5Add_fPfS_S_f"
.size .L__unnamed_2, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__AddPiS_S_i
.addrsig_sym _Z20__device_stub__Add_fPfS_S_f
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3AddPiS_S_i
.addrsig_sym _Z5Add_fPfS_S_f
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z5Add_fPfS_S_f
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0020*/ I2F R0, R6 ; /* 0x0000000600007306 */
/* 0x001e240000201400 */
/*0030*/ FSETP.GEU.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0b */
/* 0x001fda0003f0e000 */
/*0040*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0050*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0070*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0080*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*00c0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00d0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3AddPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3AddPiS_S_i
.globl _Z3AddPiS_S_i
.p2align 8
.type _Z3AddPiS_S_i,@function
_Z3AddPiS_S_i:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[4:5]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3AddPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3AddPiS_S_i, .Lfunc_end0-_Z3AddPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5Add_fPfS_S_f
.globl _Z5Add_fPfS_S_f
.p2align 8
.type _Z5Add_fPfS_S_f,@function
_Z5Add_fPfS_S_f:
s_load_b32 s2, s[0:1], 0x18
v_cvt_f32_i32_e32 v1, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_f32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[4:5]
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5Add_fPfS_S_f
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z5Add_fPfS_S_f, .Lfunc_end1-_Z5Add_fPfS_S_f
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3AddPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z3AddPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5Add_fPfS_S_f
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z5Add_fPfS_S_f.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0018475b_00000000-6_CUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3AddPiS_S_iPiS_S_i
.type _Z27__device_stub__Z3AddPiS_S_iPiS_S_i, @function
_Z27__device_stub__Z3AddPiS_S_iPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3AddPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z27__device_stub__Z3AddPiS_S_iPiS_S_i, .-_Z27__device_stub__Z3AddPiS_S_iPiS_S_i
.globl _Z3AddPiS_S_i
.type _Z3AddPiS_S_i, @function
_Z3AddPiS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3AddPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z3AddPiS_S_i, .-_Z3AddPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "with the size of %lf bytes, the read_bandwidth is %lf MBps\n "
.align 8
.LC7:
.string "with the size of %lf bytes, the write_bandwidth is %lf MBps\n "
.text
.globl _Z9bandwidthv
.type _Z9bandwidthv, @function
_Z9bandwidthv:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $3, 12(%rsp)
movl $1, %r15d
jmp .L19
.L12:
subsd .LC1(%rip), %xmm0
cvttsd2siq %xmm0, %rbx
btcq $63, %rbx
.L13:
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %r15d, %r15d
jle .L14
movslq %r15d, %rdx
movl $0, %eax
.L15:
movl %eax, (%r14,%rax,4)
movl %eax, 0(%r13,%rax,4)
movl $0, (%r12,%rax,4)
addq $1, %rax
cmpq %rdx, %rax
jne .L15
.L14:
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1000000, %ebp
.L16:
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
subl $1, %ebp
jne .L16
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movsd (%rsp), %xmm6
pxor %xmm0, %xmm0
cvtsd2ss %xmm6, %xmm0
movaps %xmm0, %xmm4
mulss .LC2(%rip), %xmm4
movss %xmm4, 8(%rsp)
movaps %xmm4, %xmm1
mulss .LC3(%rip), %xmm1
mulss .LC4(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
movq 64(%rsp), %rax
subq 48(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movsd .LC5(%rip), %xmm2
mulsd %xmm2, %xmm0
movq 72(%rsp), %rax
subq 56(%rsp), %rax
pxor %xmm3, %xmm3
cvtsi2sdq %rax, %xmm3
divsd %xmm2, %xmm3
addsd %xmm3, %xmm0
divsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm1
cvtss2sd %xmm1, %xmm1
divsd %xmm2, %xmm1
movapd %xmm6, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl %r15d, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L17:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1000000, %ebp
.L18:
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
subl $1, %ebp
jne .L18
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movss 8(%rsp), %xmm1
mulss .LC4(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
movq 96(%rsp), %rax
subq 80(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
cvtss2sd %xmm0, %xmm0
movsd .LC5(%rip), %xmm2
mulsd %xmm2, %xmm0
mulsd %xmm2, %xmm0
movq 104(%rsp), %rax
subq 88(%rsp), %rax
pxor %xmm2, %xmm2
cvtsi2ssq %rax, %xmm2
cvtss2sd %xmm2, %xmm2
addsd %xmm2, %xmm0
divsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm1
cvtss2sd %xmm1, %xmm1
movsd (%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
sall $10, %r15d
subl $1, 12(%rsp)
je .L27
.L19:
pxor %xmm5, %xmm5
cvtsi2sdl %r15d, %xmm5
movsd %xmm5, (%rsp)
movsd .LC0(%rip), %xmm0
mulsd %xmm5, %xmm0
comisd .LC1(%rip), %xmm0
jnb .L12
cvttsd2siq %xmm0, %rbx
jmp .L13
.L26:
movl %r15d, %ecx
movq %r12, %rdx
movq %r13, %rsi
movq %r14, %rdi
call _Z27__device_stub__Z3AddPiS_S_iPiS_S_i
jmp .L17
.L27:
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z9bandwidthv, .-_Z9bandwidthv
.globl _Z29__device_stub__Z5Add_fPfS_S_fPfS_S_f
.type _Z29__device_stub__Z5Add_fPfS_S_fPfS_S_f, @function
_Z29__device_stub__Z5Add_fPfS_S_fPfS_S_f:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5Add_fPfS_S_f(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z29__device_stub__Z5Add_fPfS_S_fPfS_S_f, .-_Z29__device_stub__Z5Add_fPfS_S_fPfS_S_f
.globl _Z5Add_fPfS_S_f
.type _Z5Add_fPfS_S_f, @function
_Z5Add_fPfS_S_f:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5Add_fPfS_S_fPfS_S_f
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z5Add_fPfS_S_f, .-_Z5Add_fPfS_S_f
.section .rodata.str1.1,"aMS",@progbits,1
.LC12:
.string "the IOPS is %30f GIOPS\n"
.LC13:
.string "the FLOPS is %30f GFLOPS\n"
.text
.globl _Z10Operationsv
.type _Z10Operationsv, @function
_Z10Operationsv:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movl $4096, %edi
call malloc@PLT
movq %rax, %r15
movl $4096, %edi
call malloc@PLT
movq %rax, %r14
movl $4096, %edi
call malloc@PLT
movq %rax, %r13
movl $4096, %edi
call malloc@PLT
movq %rax, %r12
movl $4096, %edi
call malloc@PLT
movq %rax, %rbp
movl $4096, %edi
call malloc@PLT
movq %rax, 8(%rsp)
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $0, %eax
.L38:
movl %eax, (%r15,%rax,4)
movl %eax, (%r14,%rax,4)
movl $0, 0(%r13,%rax,4)
addq $1, %rax
cmpq $1024, %rax
jne .L38
movl $0, %eax
.L39:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r12,%rax,4)
movss %xmm0, 0(%rbp,%rax,4)
movq 8(%rsp), %rbx
movl $0x00000000, (%rbx,%rax,4)
addq $1, %rax
cmpq $1024, %rax
jne .L39
movl $1, %ecx
movl $4096, %edx
movq %r15, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %rbp, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq 8(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1000, %ebx
jmp .L41
.L40:
subl $1, %ebx
je .L50
.L41:
movl $1024, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 128(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L40
movl $1024, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq %r15, %rdi
call _Z27__device_stub__Z3AddPiS_S_iPiS_S_i
jmp .L40
.L50:
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 112(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1000, %ebx
jmp .L43
.L42:
subl $1, %ebx
je .L51
.L43:
movl $1024, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 128(%rsp), %rdx
movl $1, %ecx
movq 68(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L42
movss .LC9(%rip), %xmm0
movq 8(%rsp), %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z29__device_stub__Z5Add_fPfS_S_fPfS_S_f
jmp .L42
.L51:
leaq 128(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 96(%rsp), %rax
subq 80(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
mulsd .LC5(%rip), %xmm1
movq 104(%rsp), %rax
subq 88(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC5(%rip), %xmm0
addsd %xmm0, %xmm1
divsd .LC5(%rip), %xmm1
movsd .LC10(%rip), %xmm0
divsd %xmm1, %xmm0
divsd .LC11(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 128(%rsp), %rax
subq 112(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
mulsd .LC5(%rip), %xmm1
movq 136(%rsp), %rax
subq 120(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC5(%rip), %xmm0
addsd %xmm0, %xmm1
divsd .LC5(%rip), %xmm1
movsd .LC10(%rip), %xmm0
divsd %xmm1, %xmm0
divsd .LC11(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L52
movl $0, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z10Operationsv, .-_Z10Operationsv
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z9bandwidthv
call _Z10Operationsv
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z5Add_fPfS_S_f"
.LC15:
.string "_Z3AddPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z5Add_fPfS_S_f(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z3AddPiS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1074790400
.align 8
.LC1:
.long 0
.long 1138753536
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1082130432
.align 4
.LC3:
.long 1077936128
.align 4
.LC4:
.long 1232348160
.section .rodata.cst8
.align 8
.LC5:
.long 0
.long 1083129856
.section .rodata.cst4
.align 4
.LC9:
.long 1149239296
.section .rodata.cst8
.align 8
.LC10:
.long 0
.long 1093615616
.align 8
.LC11:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "CUDA.hip"
.globl _Z18__device_stub__AddPiS_S_i # -- Begin function _Z18__device_stub__AddPiS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__AddPiS_S_i,@function
_Z18__device_stub__AddPiS_S_i: # @_Z18__device_stub__AddPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3AddPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__AddPiS_S_i, .Lfunc_end0-_Z18__device_stub__AddPiS_S_i
.cfi_endproc
# -- End function
.globl _Z20__device_stub__Add_fPfS_S_f # -- Begin function _Z20__device_stub__Add_fPfS_S_f
.p2align 4, 0x90
.type _Z20__device_stub__Add_fPfS_S_f,@function
_Z20__device_stub__Add_fPfS_S_f: # @_Z20__device_stub__Add_fPfS_S_f
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5Add_fPfS_S_f, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z20__device_stub__Add_fPfS_S_f, .Lfunc_end1-_Z20__device_stub__Add_fPfS_S_f
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9bandwidthv
.LCPI2_0:
.quad 0x4010000000000000 # double 4
.LCPI2_1:
.quad 0x43e0000000000000 # double 9.2233720368547758E+18
.LCPI2_5:
.quad 0x408f400000000000 # double 1000
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_2:
.long 0x40800000 # float 4
.LCPI2_3:
.long 0x40400000 # float 3
.LCPI2_4:
.long 0x49742400 # float 1.0E+6
.text
.globl _Z9bandwidthv
.p2align 4, 0x90
.type _Z9bandwidthv,@function
_Z9bandwidthv: # @_Z9bandwidthv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967296, %rax # imm = 0x100000000
movl $1, %r14d
incq %rax
movq %rax, 104(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
# Child Loop BB2_4 Depth 2
# Child Loop BB2_8 Depth 2
xorps %xmm0, %xmm0
cvtsi2sd %r14d, %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
mulsd .LCPI2_0(%rip), %xmm0
cvttsd2si %xmm0, %rax
movq %rax, %rcx
sarq $63, %rcx
subsd .LCPI2_1(%rip), %xmm0
cvttsd2si %xmm0, %rbx
andq %rcx, %rbx
orq %rax, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r15
movq %rbx, %rdi
callq malloc
movq %rax, %r12
movq %rbx, %rdi
callq malloc
movq %rax, %r13
leaq 56(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movsd 8(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %eax, (%r15,%rax,4)
movl %eax, (%r12,%rax,4)
movl $0, (%r13,%rax,4)
incq %rax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
ucomisd %xmm0, %xmm1
ja .LBB2_2
# %bb.3: # %._crit_edge
# in Loop: Header=BB2_1 Depth=1
leaq 184(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $1000000, %ebp # imm = 0xF4240
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movq 56(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq %r12, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
decl %ebp
jne .LBB2_4
# %bb.5: # in Loop: Header=BB2_1 Depth=1
leaq 168(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2ss %r14d, %xmm0
mulss .LCPI2_2(%rip), %xmm0
movss %xmm0, 24(%rsp) # 4-byte Spill
mulss .LCPI2_3(%rip), %xmm0
mulss .LCPI2_4(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq 168(%rsp), %rax
movq 176(%rsp), %rcx
subq 184(%rsp), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
subq 192(%rsp), %rcx
cvtsi2sd %rcx, %xmm2
movsd .LCPI2_5(%rip), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm3, %xmm1
divsd %xmm3, %xmm2
addsd %xmm1, %xmm2
divsd %xmm2, %xmm0
cvtsd2ss %xmm0, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
divsd %xmm3, %xmm1
movl $.L.str, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $2, %al
callq printf
movl %r14d, %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdx
movq 104(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6: # in Loop: Header=BB2_1 Depth=1
movq %r15, 160(%rsp)
movq %r12, 152(%rsp)
movq %r13, 144(%rsp)
movl %r14d, 28(%rsp)
leaq 160(%rsp), %rax
movq %rax, 64(%rsp)
leaq 152(%rsp), %rax
movq %rax, 72(%rsp)
leaq 144(%rsp), %rax
movq %rax, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 88(%rsp)
leaq 32(%rsp), %rdi
leaq 128(%rsp), %rsi
leaq 120(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 128(%rsp), %rcx
movl 136(%rsp), %r8d
movl $_Z3AddPiS_S_i, %edi
leaq 64(%rsp), %r9
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7: # in Loop: Header=BB2_1 Depth=1
leaq 64(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $1000000, %ebp # imm = 0xF4240
.p2align 4, 0x90
.LBB2_8: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movq 16(%rsp), %rsi
movq %r13, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
decl %ebp
jne .LBB2_8
# %bb.9: # in Loop: Header=BB2_1 Depth=1
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 32(%rsp), %rax
subq 64(%rsp), %rax
movss 24(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
mulss .LCPI2_4(%rip), %xmm1
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
cvtss2sd %xmm1, %xmm1
movq 40(%rsp), %rax
subq 72(%rsp), %rax
cvtss2sd %xmm0, %xmm0
xorps %xmm2, %xmm2
cvtsi2ss %rax, %xmm2
movsd .LCPI2_5(%rip), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm3, %xmm0
mulsd %xmm3, %xmm0
cvtss2sd %xmm2, %xmm2
addsd %xmm0, %xmm2
divsd %xmm2, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movl $.L.str.1, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $2, %al
callq printf
movl %r14d, %eax
shll $10, %eax
cmpl $1025, %r14d # imm = 0x401
movl %eax, %r14d
jb .LBB2_1
# %bb.10:
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq %r13, %rdi
callq free
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9bandwidthv, .Lfunc_end2-_Z9bandwidthv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z10Operationsv
.LCPI3_0:
.quad 0x408f400000000000 # double 1000
.LCPI3_1:
.quad 0x412f400000000000 # double 1024000
.LCPI3_2:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl _Z10Operationsv
.p2align 4, 0x90
.type _Z10Operationsv,@function
_Z10Operationsv: # @_Z10Operationsv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbp
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r15
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r12
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r13
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, 8(%rsp) # 8-byte Spill
leaq 216(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 208(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 200(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 192(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 184(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 176(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
xorl %ebx, %ebx
movl $4096, %edx # imm = 0x1000
movq %r15, 16(%rsp) # 8-byte Spill
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movl %ebx, (%rbp,%rbx,4)
movl %ebx, (%r14,%rbx,4)
incq %rbx
cmpq $1024, %rbx # imm = 0x400
jne .LBB3_1
# %bb.2: # %.preheader.preheader
xorl %ebx, %ebx
movl $4096, %edx # imm = 0x1000
movq 8(%rsp), %rdi # 8-byte Reload
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB3_3: # %.preheader
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ebx, %xmm0
movss %xmm0, (%r12,%rbx,4)
movss %xmm0, (%r13,%rbx,4)
incq %rbx
cmpq $1024, %rbx # imm = 0x400
jne .LBB3_3
# %bb.4:
movabsq $4294967297, %r15 # imm = 0x100000001
movq 216(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %rbp, 136(%rsp) # 8-byte Spill
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpy
movq 208(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 200(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq 16(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 192(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 184(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movq 176(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq 8(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
leaq 232(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $1000, %ebx # imm = 0x3E8
leaq 1023(%r15), %rbp
jmp .LBB3_5
.p2align 4, 0x90
.LBB3_7: # in Loop: Header=BB3_5 Depth=1
decl %ebx
je .LBB3_8
.LBB3_5: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_7
# %bb.6: # in Loop: Header=BB3_5 Depth=1
movq 136(%rsp), %rax # 8-byte Reload
movq %rax, 80(%rsp)
movq %r14, 64(%rsp)
movq 16(%rsp), %rax # 8-byte Reload
movq %rax, 48(%rsp)
movl $1024, 24(%rsp) # imm = 0x400
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rdi
leaq 144(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 160(%rsp), %rsi
movl 168(%rsp), %edx
movq 144(%rsp), %rcx
movl 152(%rsp), %r8d
movl $_Z3AddPiS_S_i, %edi
leaq 96(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_7
.LBB3_8:
leaq 160(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
leaq 144(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $1000, %ebx # imm = 0x3E8
jmp .LBB3_9
.p2align 4, 0x90
.LBB3_11: # in Loop: Header=BB3_9 Depth=1
decl %ebx
je .LBB3_12
.LBB3_9: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_11
# %bb.10: # in Loop: Header=BB3_9 Depth=1
movq %r12, 48(%rsp)
movq %r13, 40(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movq %rax, 32(%rsp)
movl $1149239296, 60(%rsp) # imm = 0x44800000
leaq 48(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rax
movq %rax, 112(%rsp)
leaq 60(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 224(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z5Add_fPfS_S_f, %edi
leaq 96(%rsp), %r9
pushq 224(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_11
.LBB3_12:
leaq 96(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 160(%rsp), %rax
subq 232(%rsp), %rax
movq 168(%rsp), %rcx
cvtsi2sd %rax, %xmm0
movsd .LCPI3_0(%rip), %xmm2 # xmm2 = mem[0],zero
subq 240(%rsp), %rcx
cvtsi2sd %rcx, %xmm1
mulsd %xmm2, %xmm0
divsd %xmm2, %xmm1
addsd %xmm0, %xmm1
divsd %xmm2, %xmm1
movsd .LCPI3_1(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
divsd .LCPI3_2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq 96(%rsp), %rax
subq 144(%rsp), %rax
movq 104(%rsp), %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd .LCPI3_0(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm2, %xmm0
subq 152(%rsp), %rcx
xorps %xmm1, %xmm1
cvtsi2sd %rcx, %xmm1
divsd %xmm2, %xmm1
addsd %xmm0, %xmm1
divsd %xmm2, %xmm1
movsd .LCPI3_1(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
divsd .LCPI3_2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 136(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
movq 16(%rsp), %rdi # 8-byte Reload
callq free
movq %r12, %rdi
callq free
movq %r13, %rdi
callq free
movq 8(%rsp), %rdi # 8-byte Reload
callq free
movq 216(%rsp), %rdi
callq hipFree
movq 208(%rsp), %rdi
callq hipFree
movq 200(%rsp), %rdi
callq hipFree
movq 192(%rsp), %rdi
callq hipFree
movq 184(%rsp), %rdi
callq hipFree
movq 176(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z10Operationsv, .Lfunc_end3-_Z10Operationsv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z9bandwidthv
callq _Z10Operationsv
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3AddPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5Add_fPfS_S_f, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3AddPiS_S_i,@object # @_Z3AddPiS_S_i
.section .rodata,"a",@progbits
.globl _Z3AddPiS_S_i
.p2align 3, 0x0
_Z3AddPiS_S_i:
.quad _Z18__device_stub__AddPiS_S_i
.size _Z3AddPiS_S_i, 8
.type _Z5Add_fPfS_S_f,@object # @_Z5Add_fPfS_S_f
.globl _Z5Add_fPfS_S_f
.p2align 3, 0x0
_Z5Add_fPfS_S_f:
.quad _Z20__device_stub__Add_fPfS_S_f
.size _Z5Add_fPfS_S_f, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "with the size of %lf bytes, the read_bandwidth is %lf MBps\n "
.size .L.str, 61
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "with the size of %lf bytes, the write_bandwidth is %lf MBps\n "
.size .L.str.1, 62
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "the IOPS is %30f GIOPS\n"
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "the FLOPS is %30f GFLOPS\n"
.size .L.str.3, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3AddPiS_S_i"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5Add_fPfS_S_f"
.size .L__unnamed_2, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__AddPiS_S_i
.addrsig_sym _Z20__device_stub__Add_fPfS_S_f
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3AddPiS_S_i
.addrsig_sym _Z5Add_fPfS_S_f
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include<iostream>
#include<cuda.h>
using namespace std;
#define N 10
__global__ void add(int *a,int *b,int *c){
int tid=threadIdx.x;
if(tid<N)
c[tid]=a[tid]+b[tid];
}
int main(){
int a[N],b[N],c[N];
int *dev_a,*dev_b,*dev_c;
cudaMalloc(&dev_a,N*sizeof(int));
cudaMalloc(&dev_b,N*sizeof(int));
cudaMalloc(&dev_c,N*sizeof(int));
for(int i=0;i<N;i++){
a[i]=i;
b[i]=i*i;
}
cudaMemcpy(dev_a,a,N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_b,b,N*sizeof(int),cudaMemcpyHostToDevice);
add<<<1,N>>>(dev_a,dev_b,dev_c);//一个计算单元是一个kernel，即一个grid，我觉得第一个数是block数量，第二个是每一个blokc含有的thread数量
cudaMemcpy(c,dev_c,N*sizeof(int),cudaMemcpyDeviceToHost);
for(int i=0;i<N;i++){
cout<<c[i]<<endl;
}
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return 0;
}
|
code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x9, PT ; /* 0x000000090600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include<iostream>
#include<cuda.h>
using namespace std;
#define N 10
__global__ void add(int *a,int *b,int *c){
int tid=threadIdx.x;
if(tid<N)
c[tid]=a[tid]+b[tid];
}
int main(){
int a[N],b[N],c[N];
int *dev_a,*dev_b,*dev_c;
cudaMalloc(&dev_a,N*sizeof(int));
cudaMalloc(&dev_b,N*sizeof(int));
cudaMalloc(&dev_c,N*sizeof(int));
for(int i=0;i<N;i++){
a[i]=i;
b[i]=i*i;
}
cudaMemcpy(dev_a,a,N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_b,b,N*sizeof(int),cudaMemcpyHostToDevice);
add<<<1,N>>>(dev_a,dev_b,dev_c);//一个计算单元是一个kernel，即一个grid，我觉得第一个数是block数量，第二个是每一个blokc含有的thread数量
cudaMemcpy(c,dev_c,N*sizeof(int),cudaMemcpyDeviceToHost);
for(int i=0;i<N;i++){
cout<<c[i]<<endl;
}
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return 0;
}
|
.file "tmpxft_0019fab1_00000000-6_add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $192, %rsp
.cfi_def_cfa_offset 240
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movl %eax, 48(%rsp,%rax,4)
movl %eax, %edx
imull %eax, %edx
movl %edx, 96(%rsp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L12
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L13:
leaq 144(%rsp), %rbp
movl $2, %ecx
movl $40, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq 184(%rsp), %r13
leaq _ZSt4cout(%rip), %r12
jmp .L18
.L23:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L13
.L26:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L24
call _ZSt16__throw_bad_castv@PLT
.L24:
call __stack_chk_fail@PLT
.L16:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
.L17:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $4, %rbp
cmpq %r13, %rbp
je .L25
.L18:
movl 0(%rbp), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .L26
cmpb $0, 56(%r14)
je .L16
movzbl 67(%r14), %esi
jmp .L17
.L25:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $0, %eax
addq $192, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include<iostream>
#include<cuda.h>
using namespace std;
#define N 10
__global__ void add(int *a,int *b,int *c){
int tid=threadIdx.x;
if(tid<N)
c[tid]=a[tid]+b[tid];
}
int main(){
int a[N],b[N],c[N];
int *dev_a,*dev_b,*dev_c;
cudaMalloc(&dev_a,N*sizeof(int));
cudaMalloc(&dev_b,N*sizeof(int));
cudaMalloc(&dev_c,N*sizeof(int));
for(int i=0;i<N;i++){
a[i]=i;
b[i]=i*i;
}
cudaMemcpy(dev_a,a,N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_b,b,N*sizeof(int),cudaMemcpyHostToDevice);
add<<<1,N>>>(dev_a,dev_b,dev_c);//一个计算单元是一个kernel，即一个grid，我觉得第一个数是block数量，第二个是每一个blokc含有的thread数量
cudaMemcpy(c,dev_c,N*sizeof(int),cudaMemcpyDeviceToHost);
for(int i=0;i<N;i++){
cout<<c[i]<<endl;
}
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return 0;
}
|
#include<iostream>
#include<hip/hip_runtime.h>
using namespace std;
#define N 10
__global__ void add(int *a,int *b,int *c){
int tid=threadIdx.x;
if(tid<N)
c[tid]=a[tid]+b[tid];
}
int main(){
int a[N],b[N],c[N];
int *dev_a,*dev_b,*dev_c;
hipMalloc(&dev_a,N*sizeof(int));
hipMalloc(&dev_b,N*sizeof(int));
hipMalloc(&dev_c,N*sizeof(int));
for(int i=0;i<N;i++){
a[i]=i;
b[i]=i*i;
}
hipMemcpy(dev_a,a,N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_b,b,N*sizeof(int),hipMemcpyHostToDevice);
add<<<1,N>>>(dev_a,dev_b,dev_c);//一个计算单元是一个kernel，即一个grid，我觉得第一个数是block数量，第二个是每一个blokc含有的thread数量
hipMemcpy(c,dev_c,N*sizeof(int),hipMemcpyDeviceToHost);
for(int i=0;i<N;i++){
cout<<c[i]<<endl;
}
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include<iostream>
#include<hip/hip_runtime.h>
using namespace std;
#define N 10
__global__ void add(int *a,int *b,int *c){
int tid=threadIdx.x;
if(tid<N)
c[tid]=a[tid]+b[tid];
}
int main(){
int a[N],b[N],c[N];
int *dev_a,*dev_b,*dev_c;
hipMalloc(&dev_a,N*sizeof(int));
hipMalloc(&dev_b,N*sizeof(int));
hipMalloc(&dev_c,N*sizeof(int));
for(int i=0;i<N;i++){
a[i]=i;
b[i]=i*i;
}
hipMemcpy(dev_a,a,N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_b,b,N*sizeof(int),hipMemcpyHostToDevice);
add<<<1,N>>>(dev_a,dev_b,dev_c);//一个计算单元是一个kernel，即一个grid，我觉得第一个数是block数量，第二个是每一个blokc含有的thread数量
hipMemcpy(c,dev_c,N*sizeof(int),hipMemcpyDeviceToHost);
for(int i=0;i<N;i++){
cout<<c[i]<<endl;
}
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 10, v0
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include<iostream>
#include<hip/hip_runtime.h>
using namespace std;
#define N 10
__global__ void add(int *a,int *b,int *c){
int tid=threadIdx.x;
if(tid<N)
c[tid]=a[tid]+b[tid];
}
int main(){
int a[N],b[N],c[N];
int *dev_a,*dev_b,*dev_c;
hipMalloc(&dev_a,N*sizeof(int));
hipMalloc(&dev_b,N*sizeof(int));
hipMalloc(&dev_c,N*sizeof(int));
for(int i=0;i<N;i++){
a[i]=i;
b[i]=i*i;
}
hipMemcpy(dev_a,a,N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_b,b,N*sizeof(int),hipMemcpyHostToDevice);
add<<<1,N>>>(dev_a,dev_b,dev_c);//一个计算单元是一个kernel，即一个grid，我觉得第一个数是block数量，第二个是每一个blokc含有的thread数量
hipMemcpy(c,dev_c,N*sizeof(int),hipMemcpyDeviceToHost);
for(int i=0;i<N;i++){
cout<<c[i]<<endl;
}
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
}
|
.text
.file "add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $240, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 192(%rsp,%rax,4)
movl %eax, %ecx
imull %eax, %ecx
movl %ecx, 144(%rsp,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
leaq 192(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 144(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_5 Depth=1
movq %rbx, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_5 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r14
cmpq $10, %r14
je .LBB1_10
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 96(%rsp,%r14,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_11
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_5 Depth=1
cmpb $0, 56(%rbx)
je .LBB1_8
# %bb.7: # in Loop: Header=BB1_5 Depth=1
movzbl 67(%rbx), %ecx
jmp .LBB1_9
.LBB1_10:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $240, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 272
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x9, PT ; /* 0x000000090600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 10, v0
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0019fab1_00000000-6_add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $192, %rsp
.cfi_def_cfa_offset 240
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movl %eax, 48(%rsp,%rax,4)
movl %eax, %edx
imull %eax, %edx
movl %edx, 96(%rsp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L12
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L13:
leaq 144(%rsp), %rbp
movl $2, %ecx
movl $40, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq 184(%rsp), %r13
leaq _ZSt4cout(%rip), %r12
jmp .L18
.L23:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L13
.L26:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L24
call _ZSt16__throw_bad_castv@PLT
.L24:
call __stack_chk_fail@PLT
.L16:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
.L17:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $4, %rbp
cmpq %r13, %rbp
je .L25
.L18:
movl 0(%rbp), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .L26
cmpb $0, 56(%r14)
je .L16
movzbl 67(%r14), %esi
jmp .L17
.L25:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $0, %eax
addq $192, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $240, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 192(%rsp,%rax,4)
movl %eax, %ecx
imull %eax, %ecx
movl %ecx, 144(%rsp,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
leaq 192(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 144(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_5 Depth=1
movq %rbx, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_5 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r14
cmpq $10, %r14
je .LBB1_10
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 96(%rsp,%r14,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_11
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_5 Depth=1
cmpb $0, 56(%rbx)
je .LBB1_8
# %bb.7: # in Loop: Header=BB1_5 Depth=1
movzbl 67(%rbx), %ecx
jmp .LBB1_9
.LBB1_10:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $240, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 272
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
//pass
//--blockDim=64 --gridDim=1 --no-inline
#include "cuda.h"
__global__ void foo(int* glob) {
int a;
int* p;
a = 0;
p = &a;
*p = threadIdx.x;
glob[*p] = threadIdx.x;
}
|
code for sm_80
Function : _Z3fooPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x001fca00078e0202 */
/*0050*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
//pass
//--blockDim=64 --gridDim=1 --no-inline
#include "cuda.h"
__global__ void foo(int* glob) {
int a;
int* p;
a = 0;
p = &a;
*p = threadIdx.x;
glob[*p] = threadIdx.x;
}
|
.file "tmpxft_00093739_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z3fooPiPi
.type _Z22__device_stub__Z3fooPiPi, @function
_Z22__device_stub__Z3fooPiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3fooPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z22__device_stub__Z3fooPiPi, .-_Z22__device_stub__Z3fooPiPi
.globl _Z3fooPi
.type _Z3fooPi, @function
_Z3fooPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3fooPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3fooPi, .-_Z3fooPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3fooPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3fooPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
//pass
//--blockDim=64 --gridDim=1 --no-inline
#include "cuda.h"
__global__ void foo(int* glob) {
int a;
int* p;
a = 0;
p = &a;
*p = threadIdx.x;
glob[*p] = threadIdx.x;
}
|
//pass
//--blockDim=64 --gridDim=1 --no-inline
#include "hip/hip_runtime.h"
__global__ void foo(int* glob) {
int a;
int* p;
a = 0;
p = &a;
*p = threadIdx.x;
glob[*p] = threadIdx.x;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
//pass
//--blockDim=64 --gridDim=1 --no-inline
#include "hip/hip_runtime.h"
__global__ void foo(int* glob) {
int a;
int* p;
a = 0;
p = &a;
*p = threadIdx.x;
glob[*p] = threadIdx.x;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3fooPi
.globl _Z3fooPi
.p2align 8
.type _Z3fooPi,@function
_Z3fooPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3fooPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3fooPi, .Lfunc_end0-_Z3fooPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3fooPi
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z3fooPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
//pass
//--blockDim=64 --gridDim=1 --no-inline
#include "hip/hip_runtime.h"
__global__ void foo(int* glob) {
int a;
int* p;
a = 0;
p = &a;
*p = threadIdx.x;
glob[*p] = threadIdx.x;
}
|
.text
.file "kernel.hip"
.globl _Z18__device_stub__fooPi # -- Begin function _Z18__device_stub__fooPi
.p2align 4, 0x90
.type _Z18__device_stub__fooPi,@function
_Z18__device_stub__fooPi: # @_Z18__device_stub__fooPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3fooPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z18__device_stub__fooPi, .Lfunc_end0-_Z18__device_stub__fooPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3fooPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3fooPi,@object # @_Z3fooPi
.section .rodata,"a",@progbits
.globl _Z3fooPi
.p2align 3, 0x0
_Z3fooPi:
.quad _Z18__device_stub__fooPi
.size _Z3fooPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3fooPi"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__fooPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3fooPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z3fooPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x001fca00078e0202 */
/*0050*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3fooPi
.globl _Z3fooPi
.p2align 8
.type _Z3fooPi,@function
_Z3fooPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3fooPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3fooPi, .Lfunc_end0-_Z3fooPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3fooPi
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z3fooPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00093739_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z3fooPiPi
.type _Z22__device_stub__Z3fooPiPi, @function
_Z22__device_stub__Z3fooPiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3fooPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z22__device_stub__Z3fooPiPi, .-_Z22__device_stub__Z3fooPiPi
.globl _Z3fooPi
.type _Z3fooPi, @function
_Z3fooPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3fooPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3fooPi, .-_Z3fooPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3fooPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3fooPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "kernel.hip"
.globl _Z18__device_stub__fooPi # -- Begin function _Z18__device_stub__fooPi
.p2align 4, 0x90
.type _Z18__device_stub__fooPi,@function
_Z18__device_stub__fooPi: # @_Z18__device_stub__fooPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3fooPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z18__device_stub__fooPi, .Lfunc_end0-_Z18__device_stub__fooPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3fooPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3fooPi,@object # @_Z3fooPi
.section .rodata,"a",@progbits
.globl _Z3fooPi
.p2align 3, 0x0
_Z3fooPi:
.quad _Z18__device_stub__fooPi
.size _Z3fooPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3fooPi"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__fooPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3fooPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <cuda_runtime.h>
#include <cuda.h>
#define TILE_WIDTH 32
#define IPAD 1
void matricMul(int *A, int *B, int *C, int size) {
for (int col = 0; col < size; col++) {
for (int row = 0; row < size; row++){
int outidx = col * size + row;
for (int idx = 0; idx < size; idx++)
C[outidx] += A[col*size+idx] * B[idx*size+row];
}
}
}
void matrixMulCheck(int *C_test, int *C_cuda, int size) {
bool ResultFlag = true;
// Print the result
for (int i = 0; i < size; i++) {
if (C_test[i] != C_cuda[i]) {
ResultFlag = false;
printf("Error: C_test[%d] = %d; C_cuda[%d] = %d;\n", i, C_test[i], i, C_cuda[i]);
break;
}
}
if (ResultFlag == true) printf("Matrix Multiplication OK!\n");
else printf("Matrix Multiplication Error!\n");
}
__global__ void matrixMulGSmemPadd (int *A, int *B, int *C, int size) {
// Static shared memory
__shared__ int ds_A[TILE_WIDTH][TILE_WIDTH+IPAD];
__shared__ int ds_B[TILE_WIDTH][TILE_WIDTH+IPAD];
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = blockIdx.y * TILE_WIDTH + ty;
int col = blockIdx.x * TILE_WIDTH + tx;
int Cval = 0;
for (int i = 0; i < (size/TILE_WIDTH); i++) {
if ((row < size) && (i*TILE_WIDTH+tx < size)) ds_A[ty][tx] = A[row*size+i*TILE_WIDTH+tx];
else ds_A[ty][tx] = 0;
if ((col < size) && (i*TILE_WIDTH+ty < size)) ds_B[ty][tx] = B[col+size*(i*TILE_WIDTH+ty)];
else ds_B[ty][tx] = 0;
__syncthreads();
for (int j = 0; j < TILE_WIDTH; j++) Cval += ds_A[ty][j] * ds_B[j][tx];
__syncthreads();
}
if (row < size && col < size) C[row * size + col] = Cval;
}
int main() {
int nx = 1600;
int ny = 1600;
int dimx = 32;
int dimy = 16;
dim3 block(dimx, dimy); // Block dimension 32x16
dim3 grid((nx+block.x-1)/block.x, (ny+block.y-1)/block.y);
int MatrixSize = nx * ny;
int BufferSize = MatrixSize * sizeof(int);
int *h_A;
int *h_B;
int *h_C;
int *C_test;
// Host memory allocation
h_A = (int*)malloc(BufferSize);
h_B = (int*)malloc(BufferSize);
h_C = (int*)malloc(BufferSize);
C_test = (int*)malloc(BufferSize);
// Data input
for (int i = 0; i < nx; i++) {
h_A[i] = i % 100;
h_B[i] = i % 100;
h_C[i] = 0;
C_test[i] = 0;
}
int *d_A;
int *d_B;
int *d_C;
// Device memory allocation
cudaMalloc((void**)&d_A, BufferSize);
cudaMalloc((void**)&d_B, BufferSize);
cudaMalloc((void**)&d_C, BufferSize);
// Copy data from Host to Device
cudaMemcpy(d_A, h_A, BufferSize, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, BufferSize, cudaMemcpyHostToDevice);
// Matrix Multiplication
matrixMulGSmemPadd<<<grid, block, TILE_WIDTH*(TILE_WIDTH+1)*sizeof(int)>>>(d_A, d_B, d_C, nx);
// Copy result from Device to Host
cudaMemcpy(h_C, d_C, BufferSize, cudaMemcpyDeviceToHost);
// Check result
matricMul(h_A, h_B, C_test, nx);
matrixMulCheck(C_test, h_C, nx);
// Free memory
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
free(h_A);
free(h_B);
free(h_C);
free(C_test);
return 0;
}
|
code for sm_80
Function : _Z18matrixMulGSmemPaddPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ MOV R5, c[0x0][0x178] ; /* 0x00005e0000057a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R16, -RZ, RZ, 0, 0 ; /* 0x00000000ff107435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P1, PT, R5, 0x20, PT ; /* 0x000000200500780c */
/* 0x000fc60003f26270 */
/*0070*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0080*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0090*/ LEA R0, R7, R4, 0x5 ; /* 0x0000000407007211 */
/* 0x001fc800078e28ff */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f06270 */
/*00b0*/ LEA R3, R3, R2, 0x5 ; /* 0x0000000203037211 */
/* 0x002fc800078e28ff */
/*00c0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fe20000706670 */
/*00d0*/ @!P1 BRA 0x960 ; /* 0x0000088000009947 */
/* 0x000fd80003800000 */
/*00e0*/ MOV R11, 0x4 ; /* 0x00000004000b7802 */
/* 0x000fe20000000f00 */
/*00f0*/ IMAD R10, R3, c[0x0][0x178], R4.reuse ; /* 0x00005e00030a7a24 */
/* 0x100fe200078e0204 */
/*0100*/ SHF.R.S32.HI R5, RZ, 0x1f, R5 ; /* 0x0000001fff057819 */
/* 0x000fe20000011405 */
/*0110*/ IMAD R8, R2, c[0x0][0x178], R4 ; /* 0x00005e0002087a24 */
/* 0x000fe200078e0204 */
/*0120*/ MOV R16, RZ ; /* 0x000000ff00107202 */
/* 0x000fe20000000f00 */
/*0130*/ IMAD.WIDE R10, R10, R11, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fe200078e020b */
/*0140*/ LEA.HI R9, R5, c[0x0][0x178], RZ, 0x5 ; /* 0x00005e0005097a11 */
/* 0x000fe200078f28ff */
/*0150*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0160*/ LEA R8, R7, R8, 0x5 ; /* 0x0000000807087211 */
/* 0x000fe200078e28ff */
/*0170*/ IMAD R7, R2, 0x84, RZ ; /* 0x0000008402077824 */
/* 0x000fe200078e02ff */
/*0180*/ MOV R5, R11 ; /* 0x0000000b00057202 */
/* 0x000fc40000000f00 */
/*0190*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe40000000f00 */
/*01a0*/ SHF.R.S32.HI R11, RZ, 0x5, R9 ; /* 0x00000005ff0b7819 */
/* 0x000fe40000011409 */
/*01b0*/ LEA R10, R4.reuse, 0x1080, 0x2 ; /* 0x00001080040a7811 */
/* 0x040fe400078e10ff */
/*01c0*/ LEA R9, R4, R7, 0x2 ; /* 0x0000000704097211 */
/* 0x000fe400078e10ff */
/*01d0*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fe20003f26270 */
/*01e0*/ HFMA2.MMA R18, -RZ, RZ, 0, 0 ; /* 0x00000000ff127435 */
/* 0x000fe200000001ff */
/*01f0*/ ISETP.GE.AND P2, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fe40003f46270 */
/*0200*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x178], P1 ; /* 0x00005e0000007a0c */
/* 0x000fc40000f26670 */
/*0210*/ ISETP.GE.OR P2, PT, R3, c[0x0][0x178], P2 ; /* 0x00005e0003007a0c */
/* 0x000fe40001746670 */
/*0220*/ MOV R20, RZ ; /* 0x000000ff00147202 */
/* 0x000fd20000000f00 */
/*0230*/ @!P1 MOV R13, 0x4 ; /* 0x00000004000d9802 */
/* 0x000fe40000000f00 */
/*0240*/ @!P2 MOV R14, R6 ; /* 0x00000006000ea202 */
/* 0x000fe40000000f00 */
/*0250*/ @!P2 MOV R15, R5 ; /* 0x00000005000fa202 */
/* 0x000fe20000000f00 */
/*0260*/ @!P1 IMAD.WIDE R12, R8, R13, c[0x0][0x168] ; /* 0x00005a00080c9625 */
/* 0x000fc800078e020d */
/*0270*/ @!P2 LDG.E R18, [R14.64] ; /* 0x000000060e12a981 */
/* 0x000ea8000c1e1900 */
/*0280*/ @!P1 LDG.E R20, [R12.64] ; /* 0x000000060c149981 */
/* 0x000ee2000c1e1900 */
/*0290*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*02a0*/ IADD3 R6, P2, R6, 0x80, RZ ; /* 0x0000008006067810 */
/* 0x000fe40007f5e0ff */
/*02b0*/ IADD3 R2, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x000fe40007ffe0ff */
/*02c0*/ IADD3 R4, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x000fc40007ffe0ff */
/*02d0*/ ISETP.LE.AND P1, PT, R11, UR4, PT ; /* 0x000000040b007c0c */
/* 0x000fe4000bf23270 */
/*02e0*/ IADD3.X R5, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff057210 */
/* 0x000fe200017fe4ff */
/*02f0*/ STS [R9], R18 ; /* 0x0000001209007388 */
/* 0x004fe80000000800 */
/*0300*/ STS [R9+0x1080], R20 ; /* 0x0010801409007388 */
/* 0x008fe80000000800 */
/*0310*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0320*/ LDS R19, [R10] ; /* 0x000000000a137984 */
/* 0x000fe80000000800 */
/*0330*/ LDS R21, [R7] ; /* 0x0000000007157984 */
/* 0x000e280000000800 */
/*0340*/ LDS R29, [R10+0x84] ; /* 0x000084000a1d7984 */
/* 0x000fe80000000800 */
/*0350*/ LDS R12, [R7+0x4] ; /* 0x00000400070c7984 */
/* 0x000e680000000800 */
/*0360*/ LDS R28, [R10+0x108] ; /* 0x000108000a1c7984 */
/* 0x000fe80000000800 */
/*0370*/ LDS R27, [R7+0x8] ; /* 0x00000800071b7984 */
/* 0x000ea80000000800 */
/*0380*/ LDS R17, [R10+0x18c] ; /* 0x00018c000a117984 */
/* 0x000fe80000000800 */
/*0390*/ LDS R24, [R7+0xc] ; /* 0x00000c0007187984 */
/* 0x000ee80000000800 */
/*03a0*/ LDS R25, [R10+0x210] ; /* 0x000210000a197984 */
/* 0x000fe80000000800 */
/*03b0*/ LDS R26, [R7+0x10] ; /* 0x00001000071a7984 */
/* 0x000f280000000800 */
/*03c0*/ LDS R22, [R10+0x294] ; /* 0x000294000a167984 */
/* 0x000fe80000000800 */
/*03d0*/ LDS R23, [R7+0x14] ; /* 0x0000140007177984 */
/* 0x000f620000000800 */
/*03e0*/ IMAD R19, R19, R21, R16 ; /* 0x0000001513137224 */
/* 0x001fc600078e0210 */
/*03f0*/ LDS R20, [R10+0x318] ; /* 0x000318000a147984 */
/* 0x000fe80000000800 */
/*0400*/ LDS R21, [R7+0x18] ; /* 0x0000180007157984 */
/* 0x000e220000000800 */
/*0410*/ IMAD R12, R29, R12, R19 ; /* 0x0000000c1d0c7224 */
/* 0x002fc600078e0213 */
/*0420*/ LDS R18, [R10+0x39c] ; /* 0x00039c000a127984 */
/* 0x000fe80000000800 */
/*0430*/ LDS R19, [R7+0x1c] ; /* 0x00001c0007137984 */
/* 0x000e620000000800 */
/*0440*/ IMAD R27, R28, R27, R12 ; /* 0x0000001b1c1b7224 */
/* 0x004fc600078e020c */
/*0450*/ LDS R14, [R10+0x420] ; /* 0x000420000a0e7984 */
/* 0x000fe80000000800 */
/*0460*/ LDS R15, [R7+0x20] ; /* 0x00002000070f7984 */
/* 0x000ea20000000800 */
/*0470*/ IMAD R17, R17, R24, R27 ; /* 0x0000001811117224 */
/* 0x008fc600078e021b */
/*0480*/ LDS R12, [R10+0x4a4] ; /* 0x0004a4000a0c7984 */
/* 0x000fe80000000800 */
/*0490*/ LDS R13, [R7+0x24] ; /* 0x00002400070d7984 */
/* 0x000ee20000000800 */
/*04a0*/ IMAD R25, R25, R26, R17 ; /* 0x0000001a19197224 */
/* 0x010fc600078e0211 */
/*04b0*/ LDS R16, [R10+0x528] ; /* 0x000528000a107984 */
/* 0x000fe80000000800 */
/*04c0*/ LDS R17, [R7+0x28] ; /* 0x0000280007117984 */
/* 0x000f220000000800 */
/*04d0*/ IMAD R25, R22, R23, R25 ; /* 0x0000001716197224 */
/* 0x020fc600078e0219 */
/*04e0*/ LDS R22, [R10+0x5ac] ; /* 0x0005ac000a167984 */
/* 0x000fe80000000800 */
/*04f0*/ LDS R23, [R7+0x2c] ; /* 0x00002c0007177984 */
/* 0x000f620000000800 */
/*0500*/ IMAD R20, R20, R21, R25 ; /* 0x0000001514147224 */
/* 0x001fc600078e0219 */
/*0510*/ LDS R24, [R10+0x630] ; /* 0x000630000a187984 */
/* 0x000fe80000000800 */
/*0520*/ LDS R25, [R7+0x30] ; /* 0x0000300007197984 */
/* 0x000e220000000800 */
/*0530*/ IMAD R18, R18, R19, R20 ; /* 0x0000001312127224 */
/* 0x002fc600078e0214 */
/*0540*/ LDS R20, [R10+0x6b4] ; /* 0x0006b4000a147984 */
/* 0x000fe80000000800 */
/*0550*/ LDS R21, [R7+0x34] ; /* 0x0000340007157984 */
/* 0x000e620000000800 */
/*0560*/ IMAD R14, R14, R15, R18 ; /* 0x0000000f0e0e7224 */
/* 0x004fc600078e0212 */
/*0570*/ LDS R18, [R10+0x738] ; /* 0x000738000a127984 */
/* 0x000fe80000000800 */
/*0580*/ LDS R19, [R7+0x38] ; /* 0x0000380007137984 */
/* 0x000ea20000000800 */
/*0590*/ IMAD R26, R12, R13, R14 ; /* 0x0000000d0c1a7224 */
/* 0x008fc600078e020e */
/*05a0*/ LDS R12, [R10+0x7bc] ; /* 0x0007bc000a0c7984 */
/* 0x000fe80000000800 */
/*05b0*/ LDS R13, [R7+0x3c] ; /* 0x00003c00070d7984 */
/* 0x000ee20000000800 */
/*05c0*/ IMAD R26, R16, R17, R26 ; /* 0x00000011101a7224 */
/* 0x010fc600078e021a */
/*05d0*/ LDS R14, [R10+0x840] ; /* 0x000840000a0e7984 */
/* 0x000fe80000000800 */
/*05e0*/ LDS R15, [R7+0x40] ; /* 0x00004000070f7984 */
/* 0x000f220000000800 */
/*05f0*/ IMAD R22, R22, R23, R26 ; /* 0x0000001716167224 */
/* 0x020fc600078e021a */
/*0600*/ LDS R16, [R10+0x8c4] ; /* 0x0008c4000a107984 */
/* 0x000fe80000000800 */
/*0610*/ LDS R17, [R7+0x44] ; /* 0x0000440007117984 */
/* 0x000f620000000800 */
/*0620*/ IMAD R24, R24, R25, R22 ; /* 0x0000001918187224 */
/* 0x001fc600078e0216 */
/*0630*/ LDS R22, [R10+0x948] ; /* 0x000948000a167984 */
/* 0x000fe80000000800 */
/*0640*/ LDS R23, [R7+0x48] ; /* 0x0000480007177984 */
/* 0x000e220000000800 */
/*0650*/ IMAD R24, R20, R21, R24 ; /* 0x0000001514187224 */
/* 0x002fc600078e0218 */
/*0660*/ LDS R20, [R10+0x9cc] ; /* 0x0009cc000a147984 */
/* 0x000fe80000000800 */
/*0670*/ LDS R21, [R7+0x4c] ; /* 0x00004c0007157984 */
/* 0x000e620000000800 */
/*0680*/ IMAD R24, R18, R19, R24 ; /* 0x0000001312187224 */
/* 0x004fc600078e0218 */
/*0690*/ LDS R18, [R10+0xa50] ; /* 0x000a50000a127984 */
/* 0x000fe80000000800 */
/*06a0*/ LDS R19, [R7+0x50] ; /* 0x0000500007137984 */
/* 0x000ea20000000800 */
/*06b0*/ IMAD R24, R12, R13, R24 ; /* 0x0000000d0c187224 */
/* 0x008fc600078e0218 */
/*06c0*/ LDS R13, [R10+0xad4] ; /* 0x000ad4000a0d7984 */
/* 0x000fe80000000800 */
/*06d0*/ LDS R12, [R7+0x54] ; /* 0x00005400070c7984 */
/* 0x000ee20000000800 */
/*06e0*/ IMAD R26, R14, R15, R24 ; /* 0x0000000f0e1a7224 */
/* 0x010fc600078e0218 */
/*06f0*/ LDS R25, [R10+0xb58] ; /* 0x000b58000a197984 */
/* 0x000fe80000000800 */
/*0700*/ LDS R24, [R7+0x58] ; /* 0x0000580007187984 */
/* 0x000f220000000800 */
/*0710*/ IMAD R26, R16, R17, R26 ; /* 0x00000011101a7224 */
/* 0x020fc600078e021a */
/*0720*/ LDS R15, [R10+0xbdc] ; /* 0x000bdc000a0f7984 */
/* 0x000fe80000000800 */
/*0730*/ LDS R14, [R7+0x5c] ; /* 0x00005c00070e7984 */
/* 0x000f620000000800 */
/*0740*/ IMAD R22, R22, R23, R26 ; /* 0x0000001716167224 */
/* 0x001fc600078e021a */
/*0750*/ LDS R17, [R10+0xc60] ; /* 0x000c60000a117984 */
/* 0x000fe80000000800 */
/*0760*/ LDS R16, [R7+0x60] ; /* 0x0000600007107984 */
/* 0x000e220000000800 */
/*0770*/ IMAD R22, R20, R21, R22 ; /* 0x0000001514167224 */
/* 0x002fc600078e0216 */
/*0780*/ LDS R21, [R10+0xce4] ; /* 0x000ce4000a157984 */
/* 0x000fe80000000800 */
/*0790*/ LDS R20, [R7+0x64] ; /* 0x0000640007147984 */
/* 0x000e620000000800 */
/*07a0*/ IMAD R22, R18, R19, R22 ; /* 0x0000001312167224 */
/* 0x004fc600078e0216 */
/*07b0*/ LDS R18, [R10+0xd68] ; /* 0x000d68000a127984 */
/* 0x000fe80000000800 */
/*07c0*/ LDS R19, [R7+0x68] ; /* 0x0000680007137984 */
/* 0x000ea20000000800 */
/*07d0*/ IMAD R22, R13, R12, R22 ; /* 0x0000000c0d167224 */
/* 0x008fc600078e0216 */
/*07e0*/ LDS R12, [R10+0xdec] ; /* 0x000dec000a0c7984 */
/* 0x000fe80000000800 */
/*07f0*/ LDS R13, [R7+0x6c] ; /* 0x00006c00070d7984 */
/* 0x000ee20000000800 */
/*0800*/ IMAD R24, R25, R24, R22 ; /* 0x0000001819187224 */
/* 0x010fc600078e0216 */
/*0810*/ LDS R22, [R10+0xe70] ; /* 0x000e70000a167984 */
/* 0x000fe80000000800 */
/*0820*/ LDS R23, [R7+0x70] ; /* 0x0000700007177984 */
/* 0x000f220000000800 */
/*0830*/ IMAD R26, R15, R14, R24 ; /* 0x0000000e0f1a7224 */
/* 0x020fc600078e0218 */
/*0840*/ LDS R24, [R10+0xef4] ; /* 0x000ef4000a187984 */
/* 0x000fe80000000800 */
/*0850*/ LDS R25, [R7+0x74] ; /* 0x0000740007197984 */
/* 0x000f620000000800 */
/*0860*/ IMAD R26, R17, R16, R26 ; /* 0x00000010111a7224 */
/* 0x001fc600078e021a */
/*0870*/ LDS R14, [R10+0xf78] ; /* 0x000f78000a0e7984 */
/* 0x000fe80000000800 */
/*0880*/ LDS R15, [R7+0x78] ; /* 0x00007800070f7984 */
/* 0x000e220000000800 */
/*0890*/ IMAD R20, R21, R20, R26 ; /* 0x0000001415147224 */
/* 0x002fc600078e021a */
/*08a0*/ LDS R16, [R10+0xffc] ; /* 0x000ffc000a107984 */
/* 0x000fe80000000800 */
/*08b0*/ LDS R17, [R7+0x7c] ; /* 0x00007c0007117984 */
/* 0x000e620000000800 */
/*08c0*/ IMAD R18, R18, R19, R20 ; /* 0x0000001312127224 */
/* 0x004fc800078e0214 */
/*08d0*/ IMAD R12, R12, R13, R18 ; /* 0x0000000d0c0c7224 */
/* 0x008fe200078e0212 */
/*08e0*/ MOV R13, c[0x0][0x178] ; /* 0x00005e00000d7a02 */
/* 0x000fc80000000f00 */
/*08f0*/ LEA R8, R13, R8, 0x5 ; /* 0x000000080d087211 */
/* 0x000fe200078e28ff */
/*0900*/ IMAD R12, R22, R23, R12 ; /* 0x00000017160c7224 */
/* 0x010fc800078e020c */
/*0910*/ IMAD R12, R24, R25, R12 ; /* 0x00000019180c7224 */
/* 0x020fc800078e020c */
/*0920*/ IMAD R12, R14, R15, R12 ; /* 0x0000000f0e0c7224 */
/* 0x001fc800078e020c */
/*0930*/ IMAD R16, R16, R17, R12 ; /* 0x0000001110107224 */
/* 0x002fe200078e020c */
/*0940*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0950*/ @!P1 BRA 0x1d0 ; /* 0xfffff87000009947 */
/* 0x000fea000383ffff */
/*0960*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0970*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0980*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x000fd200078e0200 */
/*0990*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*09a0*/ STG.E [R2.64], R16 ; /* 0x0000001002007986 */
/* 0x000fe2000c101906 */
/*09b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09c0*/ BRA 0x9c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <cuda_runtime.h>
#include <cuda.h>
#define TILE_WIDTH 32
#define IPAD 1
void matricMul(int *A, int *B, int *C, int size) {
for (int col = 0; col < size; col++) {
for (int row = 0; row < size; row++){
int outidx = col * size + row;
for (int idx = 0; idx < size; idx++)
C[outidx] += A[col*size+idx] * B[idx*size+row];
}
}
}
void matrixMulCheck(int *C_test, int *C_cuda, int size) {
bool ResultFlag = true;
// Print the result
for (int i = 0; i < size; i++) {
if (C_test[i] != C_cuda[i]) {
ResultFlag = false;
printf("Error: C_test[%d] = %d; C_cuda[%d] = %d;\n", i, C_test[i], i, C_cuda[i]);
break;
}
}
if (ResultFlag == true) printf("Matrix Multiplication OK!\n");
else printf("Matrix Multiplication Error!\n");
}
__global__ void matrixMulGSmemPadd (int *A, int *B, int *C, int size) {
// Static shared memory
__shared__ int ds_A[TILE_WIDTH][TILE_WIDTH+IPAD];
__shared__ int ds_B[TILE_WIDTH][TILE_WIDTH+IPAD];
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = blockIdx.y * TILE_WIDTH + ty;
int col = blockIdx.x * TILE_WIDTH + tx;
int Cval = 0;
for (int i = 0; i < (size/TILE_WIDTH); i++) {
if ((row < size) && (i*TILE_WIDTH+tx < size)) ds_A[ty][tx] = A[row*size+i*TILE_WIDTH+tx];
else ds_A[ty][tx] = 0;
if ((col < size) && (i*TILE_WIDTH+ty < size)) ds_B[ty][tx] = B[col+size*(i*TILE_WIDTH+ty)];
else ds_B[ty][tx] = 0;
__syncthreads();
for (int j = 0; j < TILE_WIDTH; j++) Cval += ds_A[ty][j] * ds_B[j][tx];
__syncthreads();
}
if (row < size && col < size) C[row * size + col] = Cval;
}
int main() {
int nx = 1600;
int ny = 1600;
int dimx = 32;
int dimy = 16;
dim3 block(dimx, dimy); // Block dimension 32x16
dim3 grid((nx+block.x-1)/block.x, (ny+block.y-1)/block.y);
int MatrixSize = nx * ny;
int BufferSize = MatrixSize * sizeof(int);
int *h_A;
int *h_B;
int *h_C;
int *C_test;
// Host memory allocation
h_A = (int*)malloc(BufferSize);
h_B = (int*)malloc(BufferSize);
h_C = (int*)malloc(BufferSize);
C_test = (int*)malloc(BufferSize);
// Data input
for (int i = 0; i < nx; i++) {
h_A[i] = i % 100;
h_B[i] = i % 100;
h_C[i] = 0;
C_test[i] = 0;
}
int *d_A;
int *d_B;
int *d_C;
// Device memory allocation
cudaMalloc((void**)&d_A, BufferSize);
cudaMalloc((void**)&d_B, BufferSize);
cudaMalloc((void**)&d_C, BufferSize);
// Copy data from Host to Device
cudaMemcpy(d_A, h_A, BufferSize, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, BufferSize, cudaMemcpyHostToDevice);
// Matrix Multiplication
matrixMulGSmemPadd<<<grid, block, TILE_WIDTH*(TILE_WIDTH+1)*sizeof(int)>>>(d_A, d_B, d_C, nx);
// Copy result from Device to Host
cudaMemcpy(h_C, d_C, BufferSize, cudaMemcpyDeviceToHost);
// Check result
matricMul(h_A, h_B, C_test, nx);
matrixMulCheck(C_test, h_C, nx);
// Free memory
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
free(h_A);
free(h_B);
free(h_C);
free(C_test);
return 0;
}
|
.file "tmpxft_00036512_00000000-6_matrixMulGSmemPadd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9matricMulPiS_S_i
.type _Z9matricMulPiS_S_i, @function
_Z9matricMulPiS_S_i:
.LFB2057:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L11
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r8
movq %rsi, %r12
movq %rdx, %rbp
movl %ecx, %ebx
movslq %ecx, %rdi
salq $2, %rdi
movq %r8, %r11
addq %rdi, %r8
movl $0, %r13d
movl $0, %r14d
jmp .L5
.L8:
movl %eax, %r10d
.L7:
movq %r9, %rcx
movq %r11, %rax
.L6:
movl (%rax), %edx
imull (%rcx), %edx
addl %edx, (%rsi)
addq $4, %rax
addq %rdi, %rcx
cmpq %r8, %rax
jne .L6
leal 1(%r10), %eax
addq $4, %r9
addq $4, %rsi
cmpl %eax, %ebx
jne .L8
leal 1(%r13), %eax
addq %rdi, %r11
addq %rdi, %r8
addq %rdi, %rbp
cmpl %r10d, %r13d
je .L3
movl %eax, %r13d
.L5:
movq %r12, %r9
movq %rbp, %rsi
movl %r14d, %r10d
jmp .L7
.L3:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
ret
.cfi_endproc
.LFE2057:
.size _Z9matricMulPiS_S_i, .-_Z9matricMulPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Error: C_test[%d] = %d; C_cuda[%d] = %d;\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Matrix Multiplication Error!\n"
.LC2:
.string "Matrix Multiplication OK!\n"
.text
.globl _Z14matrixMulCheckPiS_i
.type _Z14matrixMulCheckPiS_i, @function
_Z14matrixMulCheckPiS_i:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
testl %edx, %edx
jle .L15
movslq %edx, %rdx
movl $0, %r8d
.L18:
movl (%rdi,%r8,4), %ecx
movl (%rsi,%r8,4), %r9d
cmpl %r9d, %ecx
jne .L21
addq $1, %r8
cmpq %rdx, %r8
jne .L18
.L15:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L14:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl %r8d, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L14
.cfi_endproc
.LFE2058:
.size _Z14matrixMulCheckPiS_i, .-_Z14matrixMulCheckPiS_i
.globl _Z43__device_stub__Z18matrixMulGSmemPaddPiS_S_iPiS_S_i
.type _Z43__device_stub__Z18matrixMulGSmemPaddPiS_S_iPiS_S_i, @function
_Z43__device_stub__Z18matrixMulGSmemPaddPiS_S_iPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18matrixMulGSmemPaddPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z43__device_stub__Z18matrixMulGSmemPaddPiS_S_iPiS_S_i, .-_Z43__device_stub__Z18matrixMulGSmemPaddPiS_S_iPiS_S_i
.globl _Z18matrixMulGSmemPaddPiS_S_i
.type _Z18matrixMulGSmemPaddPiS_S_i, @function
_Z18matrixMulGSmemPaddPiS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z18matrixMulGSmemPaddPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z18matrixMulGSmemPaddPiS_S_i, .-_Z18matrixMulGSmemPaddPiS_S_i
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1, 40(%rsp)
movl $50, 44(%rsp)
movl $100, 48(%rsp)
movl $1, 52(%rsp)
movl $10240000, %edi
call malloc@PLT
movq %rax, %r13
movl $10240000, %edi
call malloc@PLT
movq %rax, %r12
movl $10240000, %edi
call malloc@PLT
movq %rax, %rbp
movl $10240000, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %edx
.L31:
movslq %edx, %rax
imulq $1374389535, %rax, %rax
sarq $37, %rax
movl %edx, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $100, %eax, %ecx
movl %edx, %eax
subl %ecx, %eax
movl %eax, 0(%r13,%rdx,4)
movl %eax, (%r12,%rdx,4)
movl $0, 0(%rbp,%rdx,4)
movl $0, (%rbx,%rdx,4)
addq $1, %rdx
cmpq $1600, %rdx
jne .L31
leaq 8(%rsp), %rdi
movl $10240000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $10240000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $10240000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $10240000, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $10240000, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 32(%rsp)
movl $16, 36(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $4224, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L32:
movl $2, %ecx
movl $10240000, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $1600, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z9matricMulPiS_S_i
movl $1600, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z14matrixMulCheckPiS_i
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L37
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movl $1600, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z43__device_stub__Z18matrixMulGSmemPaddPiS_S_iPiS_S_i
jmp .L32
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z18matrixMulGSmemPaddPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z18matrixMulGSmemPaddPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <cuda_runtime.h>
#include <cuda.h>
#define TILE_WIDTH 32
#define IPAD 1
void matricMul(int *A, int *B, int *C, int size) {
for (int col = 0; col < size; col++) {
for (int row = 0; row < size; row++){
int outidx = col * size + row;
for (int idx = 0; idx < size; idx++)
C[outidx] += A[col*size+idx] * B[idx*size+row];
}
}
}
void matrixMulCheck(int *C_test, int *C_cuda, int size) {
bool ResultFlag = true;
// Print the result
for (int i = 0; i < size; i++) {
if (C_test[i] != C_cuda[i]) {
ResultFlag = false;
printf("Error: C_test[%d] = %d; C_cuda[%d] = %d;\n", i, C_test[i], i, C_cuda[i]);
break;
}
}
if (ResultFlag == true) printf("Matrix Multiplication OK!\n");
else printf("Matrix Multiplication Error!\n");
}
__global__ void matrixMulGSmemPadd (int *A, int *B, int *C, int size) {
// Static shared memory
__shared__ int ds_A[TILE_WIDTH][TILE_WIDTH+IPAD];
__shared__ int ds_B[TILE_WIDTH][TILE_WIDTH+IPAD];
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = blockIdx.y * TILE_WIDTH + ty;
int col = blockIdx.x * TILE_WIDTH + tx;
int Cval = 0;
for (int i = 0; i < (size/TILE_WIDTH); i++) {
if ((row < size) && (i*TILE_WIDTH+tx < size)) ds_A[ty][tx] = A[row*size+i*TILE_WIDTH+tx];
else ds_A[ty][tx] = 0;
if ((col < size) && (i*TILE_WIDTH+ty < size)) ds_B[ty][tx] = B[col+size*(i*TILE_WIDTH+ty)];
else ds_B[ty][tx] = 0;
__syncthreads();
for (int j = 0; j < TILE_WIDTH; j++) Cval += ds_A[ty][j] * ds_B[j][tx];
__syncthreads();
}
if (row < size && col < size) C[row * size + col] = Cval;
}
int main() {
int nx = 1600;
int ny = 1600;
int dimx = 32;
int dimy = 16;
dim3 block(dimx, dimy); // Block dimension 32x16
dim3 grid((nx+block.x-1)/block.x, (ny+block.y-1)/block.y);
int MatrixSize = nx * ny;
int BufferSize = MatrixSize * sizeof(int);
int *h_A;
int *h_B;
int *h_C;
int *C_test;
// Host memory allocation
h_A = (int*)malloc(BufferSize);
h_B = (int*)malloc(BufferSize);
h_C = (int*)malloc(BufferSize);
C_test = (int*)malloc(BufferSize);
// Data input
for (int i = 0; i < nx; i++) {
h_A[i] = i % 100;
h_B[i] = i % 100;
h_C[i] = 0;
C_test[i] = 0;
}
int *d_A;
int *d_B;
int *d_C;
// Device memory allocation
cudaMalloc((void**)&d_A, BufferSize);
cudaMalloc((void**)&d_B, BufferSize);
cudaMalloc((void**)&d_C, BufferSize);
// Copy data from Host to Device
cudaMemcpy(d_A, h_A, BufferSize, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, BufferSize, cudaMemcpyHostToDevice);
// Matrix Multiplication
matrixMulGSmemPadd<<<grid, block, TILE_WIDTH*(TILE_WIDTH+1)*sizeof(int)>>>(d_A, d_B, d_C, nx);
// Copy result from Device to Host
cudaMemcpy(h_C, d_C, BufferSize, cudaMemcpyDeviceToHost);
// Check result
matricMul(h_A, h_B, C_test, nx);
matrixMulCheck(C_test, h_C, nx);
// Free memory
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
free(h_A);
free(h_B);
free(h_C);
free(C_test);
return 0;
}
|
#include <stdio.h>
#include <hip/hip_runtime.h>
#define TILE_WIDTH 32
#define IPAD 1
void matricMul(int *A, int *B, int *C, int size) {
for (int col = 0; col < size; col++) {
for (int row = 0; row < size; row++){
int outidx = col * size + row;
for (int idx = 0; idx < size; idx++)
C[outidx] += A[col*size+idx] * B[idx*size+row];
}
}
}
void matrixMulCheck(int *C_test, int *C_cuda, int size) {
bool ResultFlag = true;
// Print the result
for (int i = 0; i < size; i++) {
if (C_test[i] != C_cuda[i]) {
ResultFlag = false;
printf("Error: C_test[%d] = %d; C_cuda[%d] = %d;\n", i, C_test[i], i, C_cuda[i]);
break;
}
}
if (ResultFlag == true) printf("Matrix Multiplication OK!\n");
else printf("Matrix Multiplication Error!\n");
}
__global__ void matrixMulGSmemPadd (int *A, int *B, int *C, int size) {
// Static shared memory
__shared__ int ds_A[TILE_WIDTH][TILE_WIDTH+IPAD];
__shared__ int ds_B[TILE_WIDTH][TILE_WIDTH+IPAD];
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = blockIdx.y * TILE_WIDTH + ty;
int col = blockIdx.x * TILE_WIDTH + tx;
int Cval = 0;
for (int i = 0; i < (size/TILE_WIDTH); i++) {
if ((row < size) && (i*TILE_WIDTH+tx < size)) ds_A[ty][tx] = A[row*size+i*TILE_WIDTH+tx];
else ds_A[ty][tx] = 0;
if ((col < size) && (i*TILE_WIDTH+ty < size)) ds_B[ty][tx] = B[col+size*(i*TILE_WIDTH+ty)];
else ds_B[ty][tx] = 0;
__syncthreads();
for (int j = 0; j < TILE_WIDTH; j++) Cval += ds_A[ty][j] * ds_B[j][tx];
__syncthreads();
}
if (row < size && col < size) C[row * size + col] = Cval;
}
int main() {
int nx = 1600;
int ny = 1600;
int dimx = 32;
int dimy = 16;
dim3 block(dimx, dimy); // Block dimension 32x16
dim3 grid((nx+block.x-1)/block.x, (ny+block.y-1)/block.y);
int MatrixSize = nx * ny;
int BufferSize = MatrixSize * sizeof(int);
int *h_A;
int *h_B;
int *h_C;
int *C_test;
// Host memory allocation
h_A = (int*)malloc(BufferSize);
h_B = (int*)malloc(BufferSize);
h_C = (int*)malloc(BufferSize);
C_test = (int*)malloc(BufferSize);
// Data input
for (int i = 0; i < nx; i++) {
h_A[i] = i % 100;
h_B[i] = i % 100;
h_C[i] = 0;
C_test[i] = 0;
}
int *d_A;
int *d_B;
int *d_C;
// Device memory allocation
hipMalloc((void**)&d_A, BufferSize);
hipMalloc((void**)&d_B, BufferSize);
hipMalloc((void**)&d_C, BufferSize);
// Copy data from Host to Device
hipMemcpy(d_A, h_A, BufferSize, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, BufferSize, hipMemcpyHostToDevice);
// Matrix Multiplication
matrixMulGSmemPadd<<<grid, block, TILE_WIDTH*(TILE_WIDTH+1)*sizeof(int)>>>(d_A, d_B, d_C, nx);
// Copy result from Device to Host
hipMemcpy(h_C, d_C, BufferSize, hipMemcpyDeviceToHost);
// Check result
matricMul(h_A, h_B, C_test, nx);
matrixMulCheck(C_test, h_C, nx);
// Free memory
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
free(C_test);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <stdio.h>
#include <hip/hip_runtime.h>
#define TILE_WIDTH 32
#define IPAD 1
void matricMul(int *A, int *B, int *C, int size) {
for (int col = 0; col < size; col++) {
for (int row = 0; row < size; row++){
int outidx = col * size + row;
for (int idx = 0; idx < size; idx++)
C[outidx] += A[col*size+idx] * B[idx*size+row];
}
}
}
void matrixMulCheck(int *C_test, int *C_cuda, int size) {
bool ResultFlag = true;
// Print the result
for (int i = 0; i < size; i++) {
if (C_test[i] != C_cuda[i]) {
ResultFlag = false;
printf("Error: C_test[%d] = %d; C_cuda[%d] = %d;\n", i, C_test[i], i, C_cuda[i]);
break;
}
}
if (ResultFlag == true) printf("Matrix Multiplication OK!\n");
else printf("Matrix Multiplication Error!\n");
}
__global__ void matrixMulGSmemPadd (int *A, int *B, int *C, int size) {
// Static shared memory
__shared__ int ds_A[TILE_WIDTH][TILE_WIDTH+IPAD];
__shared__ int ds_B[TILE_WIDTH][TILE_WIDTH+IPAD];
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = blockIdx.y * TILE_WIDTH + ty;
int col = blockIdx.x * TILE_WIDTH + tx;
int Cval = 0;
for (int i = 0; i < (size/TILE_WIDTH); i++) {
if ((row < size) && (i*TILE_WIDTH+tx < size)) ds_A[ty][tx] = A[row*size+i*TILE_WIDTH+tx];
else ds_A[ty][tx] = 0;
if ((col < size) && (i*TILE_WIDTH+ty < size)) ds_B[ty][tx] = B[col+size*(i*TILE_WIDTH+ty)];
else ds_B[ty][tx] = 0;
__syncthreads();
for (int j = 0; j < TILE_WIDTH; j++) Cval += ds_A[ty][j] * ds_B[j][tx];
__syncthreads();
}
if (row < size && col < size) C[row * size + col] = Cval;
}
int main() {
int nx = 1600;
int ny = 1600;
int dimx = 32;
int dimy = 16;
dim3 block(dimx, dimy); // Block dimension 32x16
dim3 grid((nx+block.x-1)/block.x, (ny+block.y-1)/block.y);
int MatrixSize = nx * ny;
int BufferSize = MatrixSize * sizeof(int);
int *h_A;
int *h_B;
int *h_C;
int *C_test;
// Host memory allocation
h_A = (int*)malloc(BufferSize);
h_B = (int*)malloc(BufferSize);
h_C = (int*)malloc(BufferSize);
C_test = (int*)malloc(BufferSize);
// Data input
for (int i = 0; i < nx; i++) {
h_A[i] = i % 100;
h_B[i] = i % 100;
h_C[i] = 0;
C_test[i] = 0;
}
int *d_A;
int *d_B;
int *d_C;
// Device memory allocation
hipMalloc((void**)&d_A, BufferSize);
hipMalloc((void**)&d_B, BufferSize);
hipMalloc((void**)&d_C, BufferSize);
// Copy data from Host to Device
hipMemcpy(d_A, h_A, BufferSize, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, BufferSize, hipMemcpyHostToDevice);
// Matrix Multiplication
matrixMulGSmemPadd<<<grid, block, TILE_WIDTH*(TILE_WIDTH+1)*sizeof(int)>>>(d_A, d_B, d_C, nx);
// Copy result from Device to Host
hipMemcpy(h_C, d_C, BufferSize, hipMemcpyDeviceToHost);
// Check result
matricMul(h_A, h_B, C_test, nx);
matrixMulCheck(C_test, h_C, nx);
// Free memory
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
free(C_test);
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18matrixMulGSmemPaddPiS_S_i
.globl _Z18matrixMulGSmemPaddPiS_S_i
.p2align 8
.type _Z18matrixMulGSmemPaddPiS_S_i,@function
_Z18matrixMulGSmemPaddPiS_S_i:
s_load_b32 s8, s[0:1], 0x18
v_bfe_u32 v6, v0, 10, 10
v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v1, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v5, s15, 5, v6
v_lshl_add_u32 v0, s14, 5, v1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s8, 32
s_cbranch_scc1 .LBB0_17
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v1
s_ashr_i32 s2, s8, 31
v_cmp_gt_i32_e32 vcc_lo, s8, v5
s_lshr_b32 s2, s2, 27
v_cmp_le_i32_e64 s9, s8, v5
v_add_nc_u32_e32 v9, 0x1080, v2
v_mad_u64_u32 v[3:4], null, v5, s8, v[1:2]
s_add_i32 s3, s8, s2
v_mad_u32_u24 v7, v6, 0x84, v2
v_mov_b32_e32 v2, 0
v_mul_u32_u24_e32 v8, 0x84, v6
v_cmp_gt_i32_e64 s2, s8, v0
v_cmp_le_i32_e64 s10, s8, v0
v_mad_u32_u24 v4, v6, 0x84, v9
v_mov_b32_e32 v10, 0
s_ashr_i32 s11, s3, 5
s_mov_b32 s12, 0
.LBB0_2:
s_mov_b32 s3, s9
s_mov_b32 s13, 0
s_and_saveexec_b32 s14, vcc_lo
s_lshl_b32 s15, s12, 5
s_mov_b32 s13, exec_lo
v_add_nc_u32_e32 v12, s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_le_i32_e64 s3, s8, v12
v_mov_b32_e32 v12, s15
s_and_not1_b32 s15, s9, exec_lo
s_and_b32 s3, s3, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s15, s3
s_or_b32 exec_lo, exec_lo, s14
s_and_saveexec_b32 s14, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s14
s_cbranch_execz .LBB0_6
s_and_not1_b32 s13, s13, exec_lo
ds_store_b32 v7, v10
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s14, s13
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v13, v3, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v13, s3, s4, v13
v_add_co_ci_u32_e64 v14, s3, s5, v14, s3
global_load_b32 v13, v[13:14], off
s_waitcnt vmcnt(0)
ds_store_b32 v7, v13
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s14
s_mov_b32 s13, 0
s_mov_b32 s3, s10
s_and_saveexec_b32 s14, s2
v_lshl_add_u32 v11, s12, 5, v6
s_and_not1_b32 s15, s10, exec_lo
s_mov_b32 s13, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s3, s8, v11
s_and_b32 s3, s3, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s15, s3
s_or_b32 exec_lo, exec_lo, s14
s_and_saveexec_b32 s14, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s14
s_cbranch_execz .LBB0_12
s_and_not1_b32 s13, s13, exec_lo
ds_store_b32 v4, v10
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s14, s13
s_cbranch_execz .LBB0_14
v_mad_u64_u32 v[13:14], null, v11, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v13, s3, s6, v13
v_add_co_ci_u32_e64 v14, s3, s7, v14, s3
global_load_b32 v13, v[13:14], off
s_waitcnt vmcnt(0)
ds_store_b32 v4, v13
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s14
v_mov_b32_e32 v13, v9
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_15:
v_add_nc_u32_e32 v14, s3, v8
s_add_i32 s3, s3, 4
ds_load_b32 v16, v13
ds_load_b32 v17, v14
s_cmpk_eq_i32 s3, 0x80
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[14:15], null, v16, v17, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v2, v14 :: v_dual_add_nc_u32 v13, 0x84, v13
s_cbranch_scc0 .LBB0_15
s_add_i32 s12, s12, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s12, s11
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_17:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_max_i32_e32 v1, v5, v0
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_19
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v5, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18matrixMulGSmemPaddPiS_S_i
.amdhsa_group_segment_fixed_size 8448
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18matrixMulGSmemPaddPiS_S_i, .Lfunc_end0-_Z18matrixMulGSmemPaddPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 8448
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18matrixMulGSmemPaddPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18matrixMulGSmemPaddPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <stdio.h>
#include <hip/hip_runtime.h>
#define TILE_WIDTH 32
#define IPAD 1
void matricMul(int *A, int *B, int *C, int size) {
for (int col = 0; col < size; col++) {
for (int row = 0; row < size; row++){
int outidx = col * size + row;
for (int idx = 0; idx < size; idx++)
C[outidx] += A[col*size+idx] * B[idx*size+row];
}
}
}
void matrixMulCheck(int *C_test, int *C_cuda, int size) {
bool ResultFlag = true;
// Print the result
for (int i = 0; i < size; i++) {
if (C_test[i] != C_cuda[i]) {
ResultFlag = false;
printf("Error: C_test[%d] = %d; C_cuda[%d] = %d;\n", i, C_test[i], i, C_cuda[i]);
break;
}
}
if (ResultFlag == true) printf("Matrix Multiplication OK!\n");
else printf("Matrix Multiplication Error!\n");
}
__global__ void matrixMulGSmemPadd (int *A, int *B, int *C, int size) {
// Static shared memory
__shared__ int ds_A[TILE_WIDTH][TILE_WIDTH+IPAD];
__shared__ int ds_B[TILE_WIDTH][TILE_WIDTH+IPAD];
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = blockIdx.y * TILE_WIDTH + ty;
int col = blockIdx.x * TILE_WIDTH + tx;
int Cval = 0;
for (int i = 0; i < (size/TILE_WIDTH); i++) {
if ((row < size) && (i*TILE_WIDTH+tx < size)) ds_A[ty][tx] = A[row*size+i*TILE_WIDTH+tx];
else ds_A[ty][tx] = 0;
if ((col < size) && (i*TILE_WIDTH+ty < size)) ds_B[ty][tx] = B[col+size*(i*TILE_WIDTH+ty)];
else ds_B[ty][tx] = 0;
__syncthreads();
for (int j = 0; j < TILE_WIDTH; j++) Cval += ds_A[ty][j] * ds_B[j][tx];
__syncthreads();
}
if (row < size && col < size) C[row * size + col] = Cval;
}
int main() {
int nx = 1600;
int ny = 1600;
int dimx = 32;
int dimy = 16;
dim3 block(dimx, dimy); // Block dimension 32x16
dim3 grid((nx+block.x-1)/block.x, (ny+block.y-1)/block.y);
int MatrixSize = nx * ny;
int BufferSize = MatrixSize * sizeof(int);
int *h_A;
int *h_B;
int *h_C;
int *C_test;
// Host memory allocation
h_A = (int*)malloc(BufferSize);
h_B = (int*)malloc(BufferSize);
h_C = (int*)malloc(BufferSize);
C_test = (int*)malloc(BufferSize);
// Data input
for (int i = 0; i < nx; i++) {
h_A[i] = i % 100;
h_B[i] = i % 100;
h_C[i] = 0;
C_test[i] = 0;
}
int *d_A;
int *d_B;
int *d_C;
// Device memory allocation
hipMalloc((void**)&d_A, BufferSize);
hipMalloc((void**)&d_B, BufferSize);
hipMalloc((void**)&d_C, BufferSize);
// Copy data from Host to Device
hipMemcpy(d_A, h_A, BufferSize, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, BufferSize, hipMemcpyHostToDevice);
// Matrix Multiplication
matrixMulGSmemPadd<<<grid, block, TILE_WIDTH*(TILE_WIDTH+1)*sizeof(int)>>>(d_A, d_B, d_C, nx);
// Copy result from Device to Host
hipMemcpy(h_C, d_C, BufferSize, hipMemcpyDeviceToHost);
// Check result
matricMul(h_A, h_B, C_test, nx);
matrixMulCheck(C_test, h_C, nx);
// Free memory
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
free(C_test);
return 0;
}
|
.text
.file "matrixMulGSmemPadd.hip"
.globl _Z9matricMulPiS_S_i # -- Begin function _Z9matricMulPiS_S_i
.p2align 4, 0x90
.type _Z9matricMulPiS_S_i,@function
_Z9matricMulPiS_S_i: # @_Z9matricMulPiS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, -8(%rsp) # 8-byte Spill
testl %ecx, %ecx
jle .LBB0_7
# %bb.1: # %.preheader.lr.ph
movl %ecx, %eax
leaq (,%rax,4), %r8
xorl %edx, %edx
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
# Child Loop BB0_4 Depth 3
movl %edx, %r11d
leaq (%rdi,%r11,4), %r11
movq %r10, %rbx
imulq %rax, %rbx
movq -8(%rsp), %r9 # 8-byte Reload
leaq (%r9,%rbx,4), %rbx
movq %rsi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_3: # %.lr.ph
# Parent Loop BB0_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_4 Depth 3
movl (%rbx,%r15,4), %ebp
movq %r14, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# Parent Loop BB0_3 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r12), %r9d
imull (%r11,%r13,4), %r9d
addl %r9d, %ebp
movl %ebp, (%rbx,%r15,4)
incq %r13
addq %r8, %r12
cmpq %r13, %rax
jne .LBB0_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB0_3 Depth=2
incq %r15
addq $4, %r14
cmpq %rax, %r15
jne .LBB0_3
# %bb.6: # %._crit_edge27
# in Loop: Header=BB0_2 Depth=1
incq %r10
addl %ecx, %edx
cmpq %rax, %r10
jne .LBB0_2
.LBB0_7: # %._crit_edge29
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z9matricMulPiS_S_i, .Lfunc_end0-_Z9matricMulPiS_S_i
.cfi_endproc
# -- End function
.globl _Z14matrixMulCheckPiS_i # -- Begin function _Z14matrixMulCheckPiS_i
.p2align 4, 0x90
.type _Z14matrixMulCheckPiS_i,@function
_Z14matrixMulCheckPiS_i: # @_Z14matrixMulCheckPiS_i
.cfi_startproc
# %bb.0:
movq %rdi, %rax
movl $.Lstr.1, %edi
testl %edx, %edx
jle puts@PLT # TAILCALL
# %bb.1: # %.lr.ph.preheader
movl %edx, %r9d
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rax,%rcx,4), %edx
movl (%rsi,%rcx,4), %r8d
cmpl %r8d, %edx
jne .LBB1_3
# %bb.4: # in Loop: Header=BB1_2 Depth=1
incq %rcx
cmpq %rcx, %r9
jne .LBB1_2
# %bb.5: # %.critedge
jmp puts@PLT # TAILCALL
.LBB1_3:
pushq %rax
.cfi_def_cfa_offset 16
movl $.L.str, %edi
movl %ecx, %esi
# kill: def $ecx killed $ecx killed $rcx
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
addq $8, %rsp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end1:
.size _Z14matrixMulCheckPiS_i, .Lfunc_end1-_Z14matrixMulCheckPiS_i
.cfi_endproc
# -- End function
.globl _Z33__device_stub__matrixMulGSmemPaddPiS_S_i # -- Begin function _Z33__device_stub__matrixMulGSmemPaddPiS_S_i
.p2align 4, 0x90
.type _Z33__device_stub__matrixMulGSmemPaddPiS_S_i,@function
_Z33__device_stub__matrixMulGSmemPaddPiS_S_i: # @_Z33__device_stub__matrixMulGSmemPaddPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18matrixMulGSmemPaddPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z33__device_stub__matrixMulGSmemPaddPiS_S_i, .Lfunc_end2-_Z33__device_stub__matrixMulGSmemPaddPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $10240000, %edi # imm = 0x9C4000
callq malloc
movq %rax, %rbx
movl $10240000, %edi # imm = 0x9C4000
callq malloc
movq %rax, %r14
movl $10240000, %edi # imm = 0x9C4000
callq malloc
movq %rax, %r15
movl $10240000, %edi # imm = 0x9C4000
callq malloc
movq %rax, %r12
xorl %r13d, %r13d
movl $6400, %edx # imm = 0x1900
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
movl $6400, %edx # imm = 0x1900
movq %r12, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movl %r13d, %eax
imulq $1374389535, %rax, %rax # imm = 0x51EB851F
shrq $37, %rax
imull $100, %eax, %eax
movl %r13d, %ecx
subl %eax, %ecx
movl %ecx, (%rbx,%r13,4)
movl %ecx, (%r14,%r13,4)
incq %r13
cmpq $1600, %r13 # imm = 0x640
jne .LBB3_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $10240000, %esi # imm = 0x9C4000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $10240000, %esi # imm = 0x9C4000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $10240000, %esi # imm = 0x9C4000
callq hipMalloc
movq 24(%rsp), %rdi
movl $10240000, %edx # imm = 0x9C4000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $10240000, %edx # imm = 0x9C4000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $429496729650, %rdi # imm = 0x6400000032
movabsq $68719476768, %rdx # imm = 0x1000000020
movl $4224, %r8d # imm = 0x1080
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1600, 36(%rsp) # imm = 0x640
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z18matrixMulGSmemPaddPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
movq 8(%rsp), %rsi
movl $10240000, %edx # imm = 0x9C4000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
movq %rbx, %rcx
.p2align 4, 0x90
.LBB3_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
# Child Loop BB3_7 Depth 3
imulq $6400, %rax, %rdx # imm = 0x1900
addq %r12, %rdx
movq %r14, %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB3_6: # %.lr.ph.i
# Parent Loop BB3_5 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_7 Depth 3
movl (%rdx,%rdi,4), %r8d
movq %rsi, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB3_7: # Parent Loop BB3_5 Depth=1
# Parent Loop BB3_6 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r9), %r11d
imull (%rcx,%r10,4), %r11d
addl %r11d, %r8d
incq %r10
addq $6400, %r9 # imm = 0x1900
cmpq $1600, %r10 # imm = 0x640
jne .LBB3_7
# %bb.8: # %._crit_edge.i
# in Loop: Header=BB3_6 Depth=2
movl %r8d, (%rdx,%rdi,4)
incq %rdi
addq $4, %rsi
cmpq $1600, %rdi # imm = 0x640
jne .LBB3_6
# %bb.9: # %._crit_edge27.i
# in Loop: Header=BB3_5 Depth=1
incq %rax
addq $6400, %rcx # imm = 0x1900
cmpq $1600, %rax # imm = 0x640
jne .LBB3_5
# %bb.10: # %.lr.ph.i50.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_11: # %.lr.ph.i50
# =>This Inner Loop Header: Depth=1
movl (%r12,%rcx,4), %edx
movl (%r15,%rcx,4), %r8d
cmpl %r8d, %edx
jne .LBB3_12
# %bb.13: # in Loop: Header=BB3_11 Depth=1
incq %rcx
cmpq $1600, %rcx # imm = 0x640
jne .LBB3_11
# %bb.14:
movl $.Lstr.1, %edi
jmp .LBB3_15
.LBB3_12:
movl $.L.str, %edi
movl %ecx, %esi
# kill: def $ecx killed $ecx killed $rcx
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
.LBB3_15: # %_Z14matrixMulCheckPiS_i.exit
callq puts@PLT
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18matrixMulGSmemPaddPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: C_test[%d] = %d
.size .L.str, 42
.type _Z18matrixMulGSmemPaddPiS_S_i,@object # @_Z18matrixMulGSmemPaddPiS_S_i
.section .rodata,"a",@progbits
.globl _Z18matrixMulGSmemPaddPiS_S_i
.p2align 3, 0x0
_Z18matrixMulGSmemPaddPiS_S_i:
.quad _Z33__device_stub__matrixMulGSmemPaddPiS_S_i
.size _Z18matrixMulGSmemPaddPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18matrixMulGSmemPaddPiS_S_i"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Matrix Multiplication Error!"
.size .Lstr, 29
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Matrix Multiplication OK!"
.size .Lstr.1, 26
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__matrixMulGSmemPaddPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18matrixMulGSmemPaddPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z18matrixMulGSmemPaddPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ MOV R5, c[0x0][0x178] ; /* 0x00005e0000057a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R16, -RZ, RZ, 0, 0 ; /* 0x00000000ff107435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P1, PT, R5, 0x20, PT ; /* 0x000000200500780c */
/* 0x000fc60003f26270 */
/*0070*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0080*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0090*/ LEA R0, R7, R4, 0x5 ; /* 0x0000000407007211 */
/* 0x001fc800078e28ff */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f06270 */
/*00b0*/ LEA R3, R3, R2, 0x5 ; /* 0x0000000203037211 */
/* 0x002fc800078e28ff */
/*00c0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fe20000706670 */
/*00d0*/ @!P1 BRA 0x960 ; /* 0x0000088000009947 */
/* 0x000fd80003800000 */
/*00e0*/ MOV R11, 0x4 ; /* 0x00000004000b7802 */
/* 0x000fe20000000f00 */
/*00f0*/ IMAD R10, R3, c[0x0][0x178], R4.reuse ; /* 0x00005e00030a7a24 */
/* 0x100fe200078e0204 */
/*0100*/ SHF.R.S32.HI R5, RZ, 0x1f, R5 ; /* 0x0000001fff057819 */
/* 0x000fe20000011405 */
/*0110*/ IMAD R8, R2, c[0x0][0x178], R4 ; /* 0x00005e0002087a24 */
/* 0x000fe200078e0204 */
/*0120*/ MOV R16, RZ ; /* 0x000000ff00107202 */
/* 0x000fe20000000f00 */
/*0130*/ IMAD.WIDE R10, R10, R11, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fe200078e020b */
/*0140*/ LEA.HI R9, R5, c[0x0][0x178], RZ, 0x5 ; /* 0x00005e0005097a11 */
/* 0x000fe200078f28ff */
/*0150*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0160*/ LEA R8, R7, R8, 0x5 ; /* 0x0000000807087211 */
/* 0x000fe200078e28ff */
/*0170*/ IMAD R7, R2, 0x84, RZ ; /* 0x0000008402077824 */
/* 0x000fe200078e02ff */
/*0180*/ MOV R5, R11 ; /* 0x0000000b00057202 */
/* 0x000fc40000000f00 */
/*0190*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe40000000f00 */
/*01a0*/ SHF.R.S32.HI R11, RZ, 0x5, R9 ; /* 0x00000005ff0b7819 */
/* 0x000fe40000011409 */
/*01b0*/ LEA R10, R4.reuse, 0x1080, 0x2 ; /* 0x00001080040a7811 */
/* 0x040fe400078e10ff */
/*01c0*/ LEA R9, R4, R7, 0x2 ; /* 0x0000000704097211 */
/* 0x000fe400078e10ff */
/*01d0*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fe20003f26270 */
/*01e0*/ HFMA2.MMA R18, -RZ, RZ, 0, 0 ; /* 0x00000000ff127435 */
/* 0x000fe200000001ff */
/*01f0*/ ISETP.GE.AND P2, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fe40003f46270 */
/*0200*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x178], P1 ; /* 0x00005e0000007a0c */
/* 0x000fc40000f26670 */
/*0210*/ ISETP.GE.OR P2, PT, R3, c[0x0][0x178], P2 ; /* 0x00005e0003007a0c */
/* 0x000fe40001746670 */
/*0220*/ MOV R20, RZ ; /* 0x000000ff00147202 */
/* 0x000fd20000000f00 */
/*0230*/ @!P1 MOV R13, 0x4 ; /* 0x00000004000d9802 */
/* 0x000fe40000000f00 */
/*0240*/ @!P2 MOV R14, R6 ; /* 0x00000006000ea202 */
/* 0x000fe40000000f00 */
/*0250*/ @!P2 MOV R15, R5 ; /* 0x00000005000fa202 */
/* 0x000fe20000000f00 */
/*0260*/ @!P1 IMAD.WIDE R12, R8, R13, c[0x0][0x168] ; /* 0x00005a00080c9625 */
/* 0x000fc800078e020d */
/*0270*/ @!P2 LDG.E R18, [R14.64] ; /* 0x000000060e12a981 */
/* 0x000ea8000c1e1900 */
/*0280*/ @!P1 LDG.E R20, [R12.64] ; /* 0x000000060c149981 */
/* 0x000ee2000c1e1900 */
/*0290*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*02a0*/ IADD3 R6, P2, R6, 0x80, RZ ; /* 0x0000008006067810 */
/* 0x000fe40007f5e0ff */
/*02b0*/ IADD3 R2, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x000fe40007ffe0ff */
/*02c0*/ IADD3 R4, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x000fc40007ffe0ff */
/*02d0*/ ISETP.LE.AND P1, PT, R11, UR4, PT ; /* 0x000000040b007c0c */
/* 0x000fe4000bf23270 */
/*02e0*/ IADD3.X R5, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff057210 */
/* 0x000fe200017fe4ff */
/*02f0*/ STS [R9], R18 ; /* 0x0000001209007388 */
/* 0x004fe80000000800 */
/*0300*/ STS [R9+0x1080], R20 ; /* 0x0010801409007388 */
/* 0x008fe80000000800 */
/*0310*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0320*/ LDS R19, [R10] ; /* 0x000000000a137984 */
/* 0x000fe80000000800 */
/*0330*/ LDS R21, [R7] ; /* 0x0000000007157984 */
/* 0x000e280000000800 */
/*0340*/ LDS R29, [R10+0x84] ; /* 0x000084000a1d7984 */
/* 0x000fe80000000800 */
/*0350*/ LDS R12, [R7+0x4] ; /* 0x00000400070c7984 */
/* 0x000e680000000800 */
/*0360*/ LDS R28, [R10+0x108] ; /* 0x000108000a1c7984 */
/* 0x000fe80000000800 */
/*0370*/ LDS R27, [R7+0x8] ; /* 0x00000800071b7984 */
/* 0x000ea80000000800 */
/*0380*/ LDS R17, [R10+0x18c] ; /* 0x00018c000a117984 */
/* 0x000fe80000000800 */
/*0390*/ LDS R24, [R7+0xc] ; /* 0x00000c0007187984 */
/* 0x000ee80000000800 */
/*03a0*/ LDS R25, [R10+0x210] ; /* 0x000210000a197984 */
/* 0x000fe80000000800 */
/*03b0*/ LDS R26, [R7+0x10] ; /* 0x00001000071a7984 */
/* 0x000f280000000800 */
/*03c0*/ LDS R22, [R10+0x294] ; /* 0x000294000a167984 */
/* 0x000fe80000000800 */
/*03d0*/ LDS R23, [R7+0x14] ; /* 0x0000140007177984 */
/* 0x000f620000000800 */
/*03e0*/ IMAD R19, R19, R21, R16 ; /* 0x0000001513137224 */
/* 0x001fc600078e0210 */
/*03f0*/ LDS R20, [R10+0x318] ; /* 0x000318000a147984 */
/* 0x000fe80000000800 */
/*0400*/ LDS R21, [R7+0x18] ; /* 0x0000180007157984 */
/* 0x000e220000000800 */
/*0410*/ IMAD R12, R29, R12, R19 ; /* 0x0000000c1d0c7224 */
/* 0x002fc600078e0213 */
/*0420*/ LDS R18, [R10+0x39c] ; /* 0x00039c000a127984 */
/* 0x000fe80000000800 */
/*0430*/ LDS R19, [R7+0x1c] ; /* 0x00001c0007137984 */
/* 0x000e620000000800 */
/*0440*/ IMAD R27, R28, R27, R12 ; /* 0x0000001b1c1b7224 */
/* 0x004fc600078e020c */
/*0450*/ LDS R14, [R10+0x420] ; /* 0x000420000a0e7984 */
/* 0x000fe80000000800 */
/*0460*/ LDS R15, [R7+0x20] ; /* 0x00002000070f7984 */
/* 0x000ea20000000800 */
/*0470*/ IMAD R17, R17, R24, R27 ; /* 0x0000001811117224 */
/* 0x008fc600078e021b */
/*0480*/ LDS R12, [R10+0x4a4] ; /* 0x0004a4000a0c7984 */
/* 0x000fe80000000800 */
/*0490*/ LDS R13, [R7+0x24] ; /* 0x00002400070d7984 */
/* 0x000ee20000000800 */
/*04a0*/ IMAD R25, R25, R26, R17 ; /* 0x0000001a19197224 */
/* 0x010fc600078e0211 */
/*04b0*/ LDS R16, [R10+0x528] ; /* 0x000528000a107984 */
/* 0x000fe80000000800 */
/*04c0*/ LDS R17, [R7+0x28] ; /* 0x0000280007117984 */
/* 0x000f220000000800 */
/*04d0*/ IMAD R25, R22, R23, R25 ; /* 0x0000001716197224 */
/* 0x020fc600078e0219 */
/*04e0*/ LDS R22, [R10+0x5ac] ; /* 0x0005ac000a167984 */
/* 0x000fe80000000800 */
/*04f0*/ LDS R23, [R7+0x2c] ; /* 0x00002c0007177984 */
/* 0x000f620000000800 */
/*0500*/ IMAD R20, R20, R21, R25 ; /* 0x0000001514147224 */
/* 0x001fc600078e0219 */
/*0510*/ LDS R24, [R10+0x630] ; /* 0x000630000a187984 */
/* 0x000fe80000000800 */
/*0520*/ LDS R25, [R7+0x30] ; /* 0x0000300007197984 */
/* 0x000e220000000800 */
/*0530*/ IMAD R18, R18, R19, R20 ; /* 0x0000001312127224 */
/* 0x002fc600078e0214 */
/*0540*/ LDS R20, [R10+0x6b4] ; /* 0x0006b4000a147984 */
/* 0x000fe80000000800 */
/*0550*/ LDS R21, [R7+0x34] ; /* 0x0000340007157984 */
/* 0x000e620000000800 */
/*0560*/ IMAD R14, R14, R15, R18 ; /* 0x0000000f0e0e7224 */
/* 0x004fc600078e0212 */
/*0570*/ LDS R18, [R10+0x738] ; /* 0x000738000a127984 */
/* 0x000fe80000000800 */
/*0580*/ LDS R19, [R7+0x38] ; /* 0x0000380007137984 */
/* 0x000ea20000000800 */
/*0590*/ IMAD R26, R12, R13, R14 ; /* 0x0000000d0c1a7224 */
/* 0x008fc600078e020e */
/*05a0*/ LDS R12, [R10+0x7bc] ; /* 0x0007bc000a0c7984 */
/* 0x000fe80000000800 */
/*05b0*/ LDS R13, [R7+0x3c] ; /* 0x00003c00070d7984 */
/* 0x000ee20000000800 */
/*05c0*/ IMAD R26, R16, R17, R26 ; /* 0x00000011101a7224 */
/* 0x010fc600078e021a */
/*05d0*/ LDS R14, [R10+0x840] ; /* 0x000840000a0e7984 */
/* 0x000fe80000000800 */
/*05e0*/ LDS R15, [R7+0x40] ; /* 0x00004000070f7984 */
/* 0x000f220000000800 */
/*05f0*/ IMAD R22, R22, R23, R26 ; /* 0x0000001716167224 */
/* 0x020fc600078e021a */
/*0600*/ LDS R16, [R10+0x8c4] ; /* 0x0008c4000a107984 */
/* 0x000fe80000000800 */
/*0610*/ LDS R17, [R7+0x44] ; /* 0x0000440007117984 */
/* 0x000f620000000800 */
/*0620*/ IMAD R24, R24, R25, R22 ; /* 0x0000001918187224 */
/* 0x001fc600078e0216 */
/*0630*/ LDS R22, [R10+0x948] ; /* 0x000948000a167984 */
/* 0x000fe80000000800 */
/*0640*/ LDS R23, [R7+0x48] ; /* 0x0000480007177984 */
/* 0x000e220000000800 */
/*0650*/ IMAD R24, R20, R21, R24 ; /* 0x0000001514187224 */
/* 0x002fc600078e0218 */
/*0660*/ LDS R20, [R10+0x9cc] ; /* 0x0009cc000a147984 */
/* 0x000fe80000000800 */
/*0670*/ LDS R21, [R7+0x4c] ; /* 0x00004c0007157984 */
/* 0x000e620000000800 */
/*0680*/ IMAD R24, R18, R19, R24 ; /* 0x0000001312187224 */
/* 0x004fc600078e0218 */
/*0690*/ LDS R18, [R10+0xa50] ; /* 0x000a50000a127984 */
/* 0x000fe80000000800 */
/*06a0*/ LDS R19, [R7+0x50] ; /* 0x0000500007137984 */
/* 0x000ea20000000800 */
/*06b0*/ IMAD R24, R12, R13, R24 ; /* 0x0000000d0c187224 */
/* 0x008fc600078e0218 */
/*06c0*/ LDS R13, [R10+0xad4] ; /* 0x000ad4000a0d7984 */
/* 0x000fe80000000800 */
/*06d0*/ LDS R12, [R7+0x54] ; /* 0x00005400070c7984 */
/* 0x000ee20000000800 */
/*06e0*/ IMAD R26, R14, R15, R24 ; /* 0x0000000f0e1a7224 */
/* 0x010fc600078e0218 */
/*06f0*/ LDS R25, [R10+0xb58] ; /* 0x000b58000a197984 */
/* 0x000fe80000000800 */
/*0700*/ LDS R24, [R7+0x58] ; /* 0x0000580007187984 */
/* 0x000f220000000800 */
/*0710*/ IMAD R26, R16, R17, R26 ; /* 0x00000011101a7224 */
/* 0x020fc600078e021a */
/*0720*/ LDS R15, [R10+0xbdc] ; /* 0x000bdc000a0f7984 */
/* 0x000fe80000000800 */
/*0730*/ LDS R14, [R7+0x5c] ; /* 0x00005c00070e7984 */
/* 0x000f620000000800 */
/*0740*/ IMAD R22, R22, R23, R26 ; /* 0x0000001716167224 */
/* 0x001fc600078e021a */
/*0750*/ LDS R17, [R10+0xc60] ; /* 0x000c60000a117984 */
/* 0x000fe80000000800 */
/*0760*/ LDS R16, [R7+0x60] ; /* 0x0000600007107984 */
/* 0x000e220000000800 */
/*0770*/ IMAD R22, R20, R21, R22 ; /* 0x0000001514167224 */
/* 0x002fc600078e0216 */
/*0780*/ LDS R21, [R10+0xce4] ; /* 0x000ce4000a157984 */
/* 0x000fe80000000800 */
/*0790*/ LDS R20, [R7+0x64] ; /* 0x0000640007147984 */
/* 0x000e620000000800 */
/*07a0*/ IMAD R22, R18, R19, R22 ; /* 0x0000001312167224 */
/* 0x004fc600078e0216 */
/*07b0*/ LDS R18, [R10+0xd68] ; /* 0x000d68000a127984 */
/* 0x000fe80000000800 */
/*07c0*/ LDS R19, [R7+0x68] ; /* 0x0000680007137984 */
/* 0x000ea20000000800 */
/*07d0*/ IMAD R22, R13, R12, R22 ; /* 0x0000000c0d167224 */
/* 0x008fc600078e0216 */
/*07e0*/ LDS R12, [R10+0xdec] ; /* 0x000dec000a0c7984 */
/* 0x000fe80000000800 */
/*07f0*/ LDS R13, [R7+0x6c] ; /* 0x00006c00070d7984 */
/* 0x000ee20000000800 */
/*0800*/ IMAD R24, R25, R24, R22 ; /* 0x0000001819187224 */
/* 0x010fc600078e0216 */
/*0810*/ LDS R22, [R10+0xe70] ; /* 0x000e70000a167984 */
/* 0x000fe80000000800 */
/*0820*/ LDS R23, [R7+0x70] ; /* 0x0000700007177984 */
/* 0x000f220000000800 */
/*0830*/ IMAD R26, R15, R14, R24 ; /* 0x0000000e0f1a7224 */
/* 0x020fc600078e0218 */
/*0840*/ LDS R24, [R10+0xef4] ; /* 0x000ef4000a187984 */
/* 0x000fe80000000800 */
/*0850*/ LDS R25, [R7+0x74] ; /* 0x0000740007197984 */
/* 0x000f620000000800 */
/*0860*/ IMAD R26, R17, R16, R26 ; /* 0x00000010111a7224 */
/* 0x001fc600078e021a */
/*0870*/ LDS R14, [R10+0xf78] ; /* 0x000f78000a0e7984 */
/* 0x000fe80000000800 */
/*0880*/ LDS R15, [R7+0x78] ; /* 0x00007800070f7984 */
/* 0x000e220000000800 */
/*0890*/ IMAD R20, R21, R20, R26 ; /* 0x0000001415147224 */
/* 0x002fc600078e021a */
/*08a0*/ LDS R16, [R10+0xffc] ; /* 0x000ffc000a107984 */
/* 0x000fe80000000800 */
/*08b0*/ LDS R17, [R7+0x7c] ; /* 0x00007c0007117984 */
/* 0x000e620000000800 */
/*08c0*/ IMAD R18, R18, R19, R20 ; /* 0x0000001312127224 */
/* 0x004fc800078e0214 */
/*08d0*/ IMAD R12, R12, R13, R18 ; /* 0x0000000d0c0c7224 */
/* 0x008fe200078e0212 */
/*08e0*/ MOV R13, c[0x0][0x178] ; /* 0x00005e00000d7a02 */
/* 0x000fc80000000f00 */
/*08f0*/ LEA R8, R13, R8, 0x5 ; /* 0x000000080d087211 */
/* 0x000fe200078e28ff */
/*0900*/ IMAD R12, R22, R23, R12 ; /* 0x00000017160c7224 */
/* 0x010fc800078e020c */
/*0910*/ IMAD R12, R24, R25, R12 ; /* 0x00000019180c7224 */
/* 0x020fc800078e020c */
/*0920*/ IMAD R12, R14, R15, R12 ; /* 0x0000000f0e0c7224 */
/* 0x001fc800078e020c */
/*0930*/ IMAD R16, R16, R17, R12 ; /* 0x0000001110107224 */
/* 0x002fe200078e020c */
/*0940*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0950*/ @!P1 BRA 0x1d0 ; /* 0xfffff87000009947 */
/* 0x000fea000383ffff */
/*0960*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0970*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0980*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x000fd200078e0200 */
/*0990*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*09a0*/ STG.E [R2.64], R16 ; /* 0x0000001002007986 */
/* 0x000fe2000c101906 */
/*09b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09c0*/ BRA 0x9c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18matrixMulGSmemPaddPiS_S_i
.globl _Z18matrixMulGSmemPaddPiS_S_i
.p2align 8
.type _Z18matrixMulGSmemPaddPiS_S_i,@function
_Z18matrixMulGSmemPaddPiS_S_i:
s_load_b32 s8, s[0:1], 0x18
v_bfe_u32 v6, v0, 10, 10
v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v1, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v5, s15, 5, v6
v_lshl_add_u32 v0, s14, 5, v1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s8, 32
s_cbranch_scc1 .LBB0_17
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v1
s_ashr_i32 s2, s8, 31
v_cmp_gt_i32_e32 vcc_lo, s8, v5
s_lshr_b32 s2, s2, 27
v_cmp_le_i32_e64 s9, s8, v5
v_add_nc_u32_e32 v9, 0x1080, v2
v_mad_u64_u32 v[3:4], null, v5, s8, v[1:2]
s_add_i32 s3, s8, s2
v_mad_u32_u24 v7, v6, 0x84, v2
v_mov_b32_e32 v2, 0
v_mul_u32_u24_e32 v8, 0x84, v6
v_cmp_gt_i32_e64 s2, s8, v0
v_cmp_le_i32_e64 s10, s8, v0
v_mad_u32_u24 v4, v6, 0x84, v9
v_mov_b32_e32 v10, 0
s_ashr_i32 s11, s3, 5
s_mov_b32 s12, 0
.LBB0_2:
s_mov_b32 s3, s9
s_mov_b32 s13, 0
s_and_saveexec_b32 s14, vcc_lo
s_lshl_b32 s15, s12, 5
s_mov_b32 s13, exec_lo
v_add_nc_u32_e32 v12, s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_le_i32_e64 s3, s8, v12
v_mov_b32_e32 v12, s15
s_and_not1_b32 s15, s9, exec_lo
s_and_b32 s3, s3, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s15, s3
s_or_b32 exec_lo, exec_lo, s14
s_and_saveexec_b32 s14, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s14
s_cbranch_execz .LBB0_6
s_and_not1_b32 s13, s13, exec_lo
ds_store_b32 v7, v10
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s14, s13
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v13, v3, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v13, s3, s4, v13
v_add_co_ci_u32_e64 v14, s3, s5, v14, s3
global_load_b32 v13, v[13:14], off
s_waitcnt vmcnt(0)
ds_store_b32 v7, v13
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s14
s_mov_b32 s13, 0
s_mov_b32 s3, s10
s_and_saveexec_b32 s14, s2
v_lshl_add_u32 v11, s12, 5, v6
s_and_not1_b32 s15, s10, exec_lo
s_mov_b32 s13, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s3, s8, v11
s_and_b32 s3, s3, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s15, s3
s_or_b32 exec_lo, exec_lo, s14
s_and_saveexec_b32 s14, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s14
s_cbranch_execz .LBB0_12
s_and_not1_b32 s13, s13, exec_lo
ds_store_b32 v4, v10
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s14, s13
s_cbranch_execz .LBB0_14
v_mad_u64_u32 v[13:14], null, v11, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v13, s3, s6, v13
v_add_co_ci_u32_e64 v14, s3, s7, v14, s3
global_load_b32 v13, v[13:14], off
s_waitcnt vmcnt(0)
ds_store_b32 v4, v13
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s14
v_mov_b32_e32 v13, v9
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_15:
v_add_nc_u32_e32 v14, s3, v8
s_add_i32 s3, s3, 4
ds_load_b32 v16, v13
ds_load_b32 v17, v14
s_cmpk_eq_i32 s3, 0x80
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[14:15], null, v16, v17, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v2, v14 :: v_dual_add_nc_u32 v13, 0x84, v13
s_cbranch_scc0 .LBB0_15
s_add_i32 s12, s12, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s12, s11
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_17:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_max_i32_e32 v1, v5, v0
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_19
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v5, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18matrixMulGSmemPaddPiS_S_i
.amdhsa_group_segment_fixed_size 8448
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18matrixMulGSmemPaddPiS_S_i, .Lfunc_end0-_Z18matrixMulGSmemPaddPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 8448
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18matrixMulGSmemPaddPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18matrixMulGSmemPaddPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00036512_00000000-6_matrixMulGSmemPadd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9matricMulPiS_S_i
.type _Z9matricMulPiS_S_i, @function
_Z9matricMulPiS_S_i:
.LFB2057:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L11
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r8
movq %rsi, %r12
movq %rdx, %rbp
movl %ecx, %ebx
movslq %ecx, %rdi
salq $2, %rdi
movq %r8, %r11
addq %rdi, %r8
movl $0, %r13d
movl $0, %r14d
jmp .L5
.L8:
movl %eax, %r10d
.L7:
movq %r9, %rcx
movq %r11, %rax
.L6:
movl (%rax), %edx
imull (%rcx), %edx
addl %edx, (%rsi)
addq $4, %rax
addq %rdi, %rcx
cmpq %r8, %rax
jne .L6
leal 1(%r10), %eax
addq $4, %r9
addq $4, %rsi
cmpl %eax, %ebx
jne .L8
leal 1(%r13), %eax
addq %rdi, %r11
addq %rdi, %r8
addq %rdi, %rbp
cmpl %r10d, %r13d
je .L3
movl %eax, %r13d
.L5:
movq %r12, %r9
movq %rbp, %rsi
movl %r14d, %r10d
jmp .L7
.L3:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
ret
.cfi_endproc
.LFE2057:
.size _Z9matricMulPiS_S_i, .-_Z9matricMulPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Error: C_test[%d] = %d; C_cuda[%d] = %d;\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Matrix Multiplication Error!\n"
.LC2:
.string "Matrix Multiplication OK!\n"
.text
.globl _Z14matrixMulCheckPiS_i
.type _Z14matrixMulCheckPiS_i, @function
_Z14matrixMulCheckPiS_i:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
testl %edx, %edx
jle .L15
movslq %edx, %rdx
movl $0, %r8d
.L18:
movl (%rdi,%r8,4), %ecx
movl (%rsi,%r8,4), %r9d
cmpl %r9d, %ecx
jne .L21
addq $1, %r8
cmpq %rdx, %r8
jne .L18
.L15:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L14:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl %r8d, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L14
.cfi_endproc
.LFE2058:
.size _Z14matrixMulCheckPiS_i, .-_Z14matrixMulCheckPiS_i
.globl _Z43__device_stub__Z18matrixMulGSmemPaddPiS_S_iPiS_S_i
.type _Z43__device_stub__Z18matrixMulGSmemPaddPiS_S_iPiS_S_i, @function
_Z43__device_stub__Z18matrixMulGSmemPaddPiS_S_iPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18matrixMulGSmemPaddPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z43__device_stub__Z18matrixMulGSmemPaddPiS_S_iPiS_S_i, .-_Z43__device_stub__Z18matrixMulGSmemPaddPiS_S_iPiS_S_i
.globl _Z18matrixMulGSmemPaddPiS_S_i
.type _Z18matrixMulGSmemPaddPiS_S_i, @function
_Z18matrixMulGSmemPaddPiS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z18matrixMulGSmemPaddPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z18matrixMulGSmemPaddPiS_S_i, .-_Z18matrixMulGSmemPaddPiS_S_i
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1, 40(%rsp)
movl $50, 44(%rsp)
movl $100, 48(%rsp)
movl $1, 52(%rsp)
movl $10240000, %edi
call malloc@PLT
movq %rax, %r13
movl $10240000, %edi
call malloc@PLT
movq %rax, %r12
movl $10240000, %edi
call malloc@PLT
movq %rax, %rbp
movl $10240000, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %edx
.L31:
movslq %edx, %rax
imulq $1374389535, %rax, %rax
sarq $37, %rax
movl %edx, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $100, %eax, %ecx
movl %edx, %eax
subl %ecx, %eax
movl %eax, 0(%r13,%rdx,4)
movl %eax, (%r12,%rdx,4)
movl $0, 0(%rbp,%rdx,4)
movl $0, (%rbx,%rdx,4)
addq $1, %rdx
cmpq $1600, %rdx
jne .L31
leaq 8(%rsp), %rdi
movl $10240000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $10240000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $10240000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $10240000, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $10240000, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 32(%rsp)
movl $16, 36(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $4224, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L32:
movl $2, %ecx
movl $10240000, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $1600, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z9matricMulPiS_S_i
movl $1600, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z14matrixMulCheckPiS_i
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L37
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movl $1600, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z43__device_stub__Z18matrixMulGSmemPaddPiS_S_iPiS_S_i
jmp .L32
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z18matrixMulGSmemPaddPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z18matrixMulGSmemPaddPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "matrixMulGSmemPadd.hip"
.globl _Z9matricMulPiS_S_i # -- Begin function _Z9matricMulPiS_S_i
.p2align 4, 0x90
.type _Z9matricMulPiS_S_i,@function
_Z9matricMulPiS_S_i: # @_Z9matricMulPiS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, -8(%rsp) # 8-byte Spill
testl %ecx, %ecx
jle .LBB0_7
# %bb.1: # %.preheader.lr.ph
movl %ecx, %eax
leaq (,%rax,4), %r8
xorl %edx, %edx
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
# Child Loop BB0_4 Depth 3
movl %edx, %r11d
leaq (%rdi,%r11,4), %r11
movq %r10, %rbx
imulq %rax, %rbx
movq -8(%rsp), %r9 # 8-byte Reload
leaq (%r9,%rbx,4), %rbx
movq %rsi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_3: # %.lr.ph
# Parent Loop BB0_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_4 Depth 3
movl (%rbx,%r15,4), %ebp
movq %r14, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# Parent Loop BB0_3 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r12), %r9d
imull (%r11,%r13,4), %r9d
addl %r9d, %ebp
movl %ebp, (%rbx,%r15,4)
incq %r13
addq %r8, %r12
cmpq %r13, %rax
jne .LBB0_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB0_3 Depth=2
incq %r15
addq $4, %r14
cmpq %rax, %r15
jne .LBB0_3
# %bb.6: # %._crit_edge27
# in Loop: Header=BB0_2 Depth=1
incq %r10
addl %ecx, %edx
cmpq %rax, %r10
jne .LBB0_2
.LBB0_7: # %._crit_edge29
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z9matricMulPiS_S_i, .Lfunc_end0-_Z9matricMulPiS_S_i
.cfi_endproc
# -- End function
.globl _Z14matrixMulCheckPiS_i # -- Begin function _Z14matrixMulCheckPiS_i
.p2align 4, 0x90
.type _Z14matrixMulCheckPiS_i,@function
_Z14matrixMulCheckPiS_i: # @_Z14matrixMulCheckPiS_i
.cfi_startproc
# %bb.0:
movq %rdi, %rax
movl $.Lstr.1, %edi
testl %edx, %edx
jle puts@PLT # TAILCALL
# %bb.1: # %.lr.ph.preheader
movl %edx, %r9d
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rax,%rcx,4), %edx
movl (%rsi,%rcx,4), %r8d
cmpl %r8d, %edx
jne .LBB1_3
# %bb.4: # in Loop: Header=BB1_2 Depth=1
incq %rcx
cmpq %rcx, %r9
jne .LBB1_2
# %bb.5: # %.critedge
jmp puts@PLT # TAILCALL
.LBB1_3:
pushq %rax
.cfi_def_cfa_offset 16
movl $.L.str, %edi
movl %ecx, %esi
# kill: def $ecx killed $ecx killed $rcx
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
addq $8, %rsp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end1:
.size _Z14matrixMulCheckPiS_i, .Lfunc_end1-_Z14matrixMulCheckPiS_i
.cfi_endproc
# -- End function
.globl _Z33__device_stub__matrixMulGSmemPaddPiS_S_i # -- Begin function _Z33__device_stub__matrixMulGSmemPaddPiS_S_i
.p2align 4, 0x90
.type _Z33__device_stub__matrixMulGSmemPaddPiS_S_i,@function
_Z33__device_stub__matrixMulGSmemPaddPiS_S_i: # @_Z33__device_stub__matrixMulGSmemPaddPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18matrixMulGSmemPaddPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z33__device_stub__matrixMulGSmemPaddPiS_S_i, .Lfunc_end2-_Z33__device_stub__matrixMulGSmemPaddPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $10240000, %edi # imm = 0x9C4000
callq malloc
movq %rax, %rbx
movl $10240000, %edi # imm = 0x9C4000
callq malloc
movq %rax, %r14
movl $10240000, %edi # imm = 0x9C4000
callq malloc
movq %rax, %r15
movl $10240000, %edi # imm = 0x9C4000
callq malloc
movq %rax, %r12
xorl %r13d, %r13d
movl $6400, %edx # imm = 0x1900
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
movl $6400, %edx # imm = 0x1900
movq %r12, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movl %r13d, %eax
imulq $1374389535, %rax, %rax # imm = 0x51EB851F
shrq $37, %rax
imull $100, %eax, %eax
movl %r13d, %ecx
subl %eax, %ecx
movl %ecx, (%rbx,%r13,4)
movl %ecx, (%r14,%r13,4)
incq %r13
cmpq $1600, %r13 # imm = 0x640
jne .LBB3_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $10240000, %esi # imm = 0x9C4000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $10240000, %esi # imm = 0x9C4000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $10240000, %esi # imm = 0x9C4000
callq hipMalloc
movq 24(%rsp), %rdi
movl $10240000, %edx # imm = 0x9C4000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $10240000, %edx # imm = 0x9C4000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $429496729650, %rdi # imm = 0x6400000032
movabsq $68719476768, %rdx # imm = 0x1000000020
movl $4224, %r8d # imm = 0x1080
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1600, 36(%rsp) # imm = 0x640
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z18matrixMulGSmemPaddPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
movq 8(%rsp), %rsi
movl $10240000, %edx # imm = 0x9C4000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
movq %rbx, %rcx
.p2align 4, 0x90
.LBB3_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
# Child Loop BB3_7 Depth 3
imulq $6400, %rax, %rdx # imm = 0x1900
addq %r12, %rdx
movq %r14, %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB3_6: # %.lr.ph.i
# Parent Loop BB3_5 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_7 Depth 3
movl (%rdx,%rdi,4), %r8d
movq %rsi, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB3_7: # Parent Loop BB3_5 Depth=1
# Parent Loop BB3_6 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r9), %r11d
imull (%rcx,%r10,4), %r11d
addl %r11d, %r8d
incq %r10
addq $6400, %r9 # imm = 0x1900
cmpq $1600, %r10 # imm = 0x640
jne .LBB3_7
# %bb.8: # %._crit_edge.i
# in Loop: Header=BB3_6 Depth=2
movl %r8d, (%rdx,%rdi,4)
incq %rdi
addq $4, %rsi
cmpq $1600, %rdi # imm = 0x640
jne .LBB3_6
# %bb.9: # %._crit_edge27.i
# in Loop: Header=BB3_5 Depth=1
incq %rax
addq $6400, %rcx # imm = 0x1900
cmpq $1600, %rax # imm = 0x640
jne .LBB3_5
# %bb.10: # %.lr.ph.i50.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_11: # %.lr.ph.i50
# =>This Inner Loop Header: Depth=1
movl (%r12,%rcx,4), %edx
movl (%r15,%rcx,4), %r8d
cmpl %r8d, %edx
jne .LBB3_12
# %bb.13: # in Loop: Header=BB3_11 Depth=1
incq %rcx
cmpq $1600, %rcx # imm = 0x640
jne .LBB3_11
# %bb.14:
movl $.Lstr.1, %edi
jmp .LBB3_15
.LBB3_12:
movl $.L.str, %edi
movl %ecx, %esi
# kill: def $ecx killed $ecx killed $rcx
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
.LBB3_15: # %_Z14matrixMulCheckPiS_i.exit
callq puts@PLT
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18matrixMulGSmemPaddPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: C_test[%d] = %d
.size .L.str, 42
.type _Z18matrixMulGSmemPaddPiS_S_i,@object # @_Z18matrixMulGSmemPaddPiS_S_i
.section .rodata,"a",@progbits
.globl _Z18matrixMulGSmemPaddPiS_S_i
.p2align 3, 0x0
_Z18matrixMulGSmemPaddPiS_S_i:
.quad _Z33__device_stub__matrixMulGSmemPaddPiS_S_i
.size _Z18matrixMulGSmemPaddPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18matrixMulGSmemPaddPiS_S_i"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Matrix Multiplication Error!"
.size .Lstr, 29
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Matrix Multiplication OK!"
.size .Lstr.1, 26
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__matrixMulGSmemPaddPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18matrixMulGSmemPaddPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <cuda_runtime_api.h>
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
using namespace std;
cudaStream_t createStreamWithFlags(){
cudaStream_t stream;
cudaStreamCreateWithFlags(&stream, cudaStreamNonBlocking);
return stream;
}
|
code for sm_80
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <cuda_runtime_api.h>
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
using namespace std;
cudaStream_t createStreamWithFlags(){
cudaStream_t stream;
cudaStreamCreateWithFlags(&stream, cudaStreamNonBlocking);
return stream;
}
|
.file "tmpxft_00073c5b_00000000-6_streamCreator.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z21createStreamWithFlagsv
.type _Z21createStreamWithFlagsv, @function
_Z21createStreamWithFlagsv:
.LFB3669:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %esi
call cudaStreamCreateWithFlags@PLT
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L6
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z21createStreamWithFlagsv, .-_Z21createStreamWithFlagsv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <cuda_runtime_api.h>
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
using namespace std;
cudaStream_t createStreamWithFlags(){
cudaStream_t stream;
cudaStreamCreateWithFlags(&stream, cudaStreamNonBlocking);
return stream;
}
|
#include <hip/hip_runtime_api.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
using namespace std;
hipStream_t createStreamWithFlags(){
hipStream_t stream;
hipStreamCreateWithFlags(&stream, hipStreamNonBlocking);
return stream;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime_api.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
using namespace std;
hipStream_t createStreamWithFlags(){
hipStream_t stream;
hipStreamCreateWithFlags(&stream, hipStreamNonBlocking);
return stream;
}
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime_api.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
using namespace std;
hipStream_t createStreamWithFlags(){
hipStream_t stream;
hipStreamCreateWithFlags(&stream, hipStreamNonBlocking);
return stream;
}
|
.text
.file "streamCreator.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21createStreamWithFlagsv # -- Begin function _Z21createStreamWithFlagsv
.p2align 4, 0x90
.type _Z21createStreamWithFlagsv,@function
_Z21createStreamWithFlagsv: # @_Z21createStreamWithFlagsv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rsp, %rdi
movl $1, %esi
callq hipStreamCreateWithFlags
movq (%rsp), %rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z21createStreamWithFlagsv, .Lfunc_end0-_Z21createStreamWithFlagsv
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00073c5b_00000000-6_streamCreator.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z21createStreamWithFlagsv
.type _Z21createStreamWithFlagsv, @function
_Z21createStreamWithFlagsv:
.LFB3669:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %esi
call cudaStreamCreateWithFlags@PLT
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L6
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z21createStreamWithFlagsv, .-_Z21createStreamWithFlagsv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "streamCreator.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21createStreamWithFlagsv # -- Begin function _Z21createStreamWithFlagsv
.p2align 4, 0x90
.type _Z21createStreamWithFlagsv,@function
_Z21createStreamWithFlagsv: # @_Z21createStreamWithFlagsv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rsp, %rdi
movl $1, %esi
callq hipStreamCreateWithFlags
movq (%rsp), %rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z21createStreamWithFlagsv, .Lfunc_end0-_Z21createStreamWithFlagsv
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <random>
int getRandom(int n) {
std::random_device rd;
std::mt19937 gen(rd());
std::uniform_int_distribution<> dis(0, n);
return dis(gen);
}
__global__
void check(int *fDictX, int *fDictY, int sizeOfFDict, int *currInjective) {
int idxInit = blockIdx.x * blockDim.x + threadIdx.x; // this is the initial global index
if (idxInit < sizeOfFDict) { // make sure we're not out of bounds
// grid-stride loop
for (int idx = idxInit; idx <= sizeOfFDict; idx += blockDim.x * gridDim.x) {
// this inner loop will do the work for a thread in each grid
for (int i=idx; i < sizeOfFDict; i++) {
if (fDictY[idx] == fDictY[i] && fDictX[idx] != fDictX[i]) {
currInjective[idx] = 0; // this will insert a zero into INJECTIVE
break;
}
}
}
}
}
extern "C" {
int injective(int maxDomain, int maxCodomain) {
// declare the arrays
int *domainX, *domainY, *INJECTIVE;
// allocated Unified Memory
cudaMallocManaged(&domainX, maxDomain*sizeof(int));
cudaMallocManaged(&domainY, maxDomain*sizeof(int));
cudaMallocManaged(&INJECTIVE, maxDomain*sizeof(int));
// initialize function
for (int i = 0; i < maxDomain; i++) {
domainX[i] = i;
domainY[i] = getRandom(maxCodomain);
INJECTIVE[i] = 1; // here we assume that the function is injective
}
// actually make the kernel call
// this is currently running with thread blocks of size 256. I may find a better number
// to tune that too. It's <<< numBlocks, numThreads >>>
check<<<(maxDomain+255)/256, 256>>>(domainX, domainY, maxDomain, INJECTIVE);
cudaDeviceSynchronize(); // sync the host and device
// error checking
if (cudaSuccess != cudaGetLastError()) {
cudaFree(domainX);
cudaFree(domainY);
cudaFree(INJECTIVE);
return -1; // this will be used to raise a RuntimeError
}
// free the unified memory
cudaFree(domainX);
cudaFree(domainY);
for (int i = 0; i < maxDomain; i++) {
if (INJECTIVE[i] == 0) { // 0 => false so the function is not injective
cudaFree(INJECTIVE);
return 0;
}
}
cudaFree(INJECTIVE);
return 1; // the function is injective
}
}
|
code for sm_80
Function : _Z5checkPiS_iS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06270 */
/*0080*/ BSSY B0, 0x270 ; /* 0x000001e000007945 */
/* 0x000fd80003800000 */
/*0090*/ @P0 BRA 0x260 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*00b0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0205 */
/*00c0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000162000c1e1900 */
/*00d0*/ SHF.R.S32.HI R9, RZ, 0x1f, R0.reuse ; /* 0x0000001fff097819 */
/* 0x100fe20000011400 */
/*00e0*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0000 */
/*00f0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0205 */
/*0100*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x001fc800078e00ff */
/*0110*/ IMAD.WIDE R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fcc00078e0203 */
/*0120*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0130*/ BSSY B1, 0x1f0 ; /* 0x000000b000017945 */
/* 0x000fe20003800000 */
/*0140*/ ISETP.NE.AND P0, PT, R11, R2, PT ; /* 0x000000020b00720c */
/* 0x024fda0003f05270 */
/*0150*/ @P0 BRA 0x1e0 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0160*/ SHF.R.S32.HI R3, RZ, 0x1f, R6 ; /* 0x0000001fff037819 */
/* 0x000fe20000011406 */
/*0170*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea2000c1e1900 */
/*0180*/ LEA R2, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006027a11 */
/* 0x000fc800078010ff */
/*0190*/ LEA.HI.X R3, R6, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590006037a11 */
/* 0x000fca00000f1403 */
/*01a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*01b0*/ ISETP.NE.AND P0, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x004fda0003f05270 */
/*01c0*/ @P0 BREAK B1 ; /* 0x0000000000010942 */
/* 0x000fe20003800000 */
/*01d0*/ @P0 BRA 0x230 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*01e0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*01f0*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fc80007ffe0ff */
/*0200*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fda0003f06270 */
/*0210*/ @!P0 BRA 0x100 ; /* 0xfffffee000008947 */
/* 0x000fea000383ffff */
/*0220*/ BRA 0x260 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0230*/ LEA R2, P0, R0, c[0x0][0x178], 0x2 ; /* 0x00005e0000027a11 */
/* 0x000fc800078010ff */
/*0240*/ LEA.HI.X R3, R0, c[0x0][0x17c], R9, 0x2, P0 ; /* 0x00005f0000037a11 */
/* 0x000fca00000f1409 */
/*0250*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e8000c101904 */
/*0260*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0270*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x001fc800078e00ff */
/*0280*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x000fca00078e0200 */
/*0290*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f04270 */
/*02a0*/ @!P0 BRA 0x70 ; /* 0xfffffdc000008947 */
/* 0x000fea000383ffff */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <random>
int getRandom(int n) {
std::random_device rd;
std::mt19937 gen(rd());
std::uniform_int_distribution<> dis(0, n);
return dis(gen);
}
__global__
void check(int *fDictX, int *fDictY, int sizeOfFDict, int *currInjective) {
int idxInit = blockIdx.x * blockDim.x + threadIdx.x; // this is the initial global index
if (idxInit < sizeOfFDict) { // make sure we're not out of bounds
// grid-stride loop
for (int idx = idxInit; idx <= sizeOfFDict; idx += blockDim.x * gridDim.x) {
// this inner loop will do the work for a thread in each grid
for (int i=idx; i < sizeOfFDict; i++) {
if (fDictY[idx] == fDictY[i] && fDictX[idx] != fDictX[i]) {
currInjective[idx] = 0; // this will insert a zero into INJECTIVE
break;
}
}
}
}
}
extern "C" {
int injective(int maxDomain, int maxCodomain) {
// declare the arrays
int *domainX, *domainY, *INJECTIVE;
// allocated Unified Memory
cudaMallocManaged(&domainX, maxDomain*sizeof(int));
cudaMallocManaged(&domainY, maxDomain*sizeof(int));
cudaMallocManaged(&INJECTIVE, maxDomain*sizeof(int));
// initialize function
for (int i = 0; i < maxDomain; i++) {
domainX[i] = i;
domainY[i] = getRandom(maxCodomain);
INJECTIVE[i] = 1; // here we assume that the function is injective
}
// actually make the kernel call
// this is currently running with thread blocks of size 256. I may find a better number
// to tune that too. It's <<< numBlocks, numThreads >>>
check<<<(maxDomain+255)/256, 256>>>(domainX, domainY, maxDomain, INJECTIVE);
cudaDeviceSynchronize(); // sync the host and device
// error checking
if (cudaSuccess != cudaGetLastError()) {
cudaFree(domainX);
cudaFree(domainY);
cudaFree(INJECTIVE);
return -1; // this will be used to raise a RuntimeError
}
// free the unified memory
cudaFree(domainX);
cudaFree(domainY);
for (int i = 0; i < maxDomain; i++) {
if (INJECTIVE[i] == 0) { // 0 => false so the function is not injective
cudaFree(INJECTIVE);
return 0;
}
}
cudaFree(INJECTIVE);
return 1; // the function is injective
}
}
|
.file "tmpxft_001723c8_00000000-6_checkInjective.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4145:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4145:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z5checkPiS_iS_PiS_iS_
.type _Z29__device_stub__Z5checkPiS_iS_PiS_iS_, @function
_Z29__device_stub__Z5checkPiS_iS_PiS_iS_:
.LFB4167:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5checkPiS_iS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4167:
.size _Z29__device_stub__Z5checkPiS_iS_PiS_iS_, .-_Z29__device_stub__Z5checkPiS_iS_PiS_iS_
.globl _Z5checkPiS_iS_
.type _Z5checkPiS_iS_, @function
_Z5checkPiS_iS_:
.LFB4168:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5checkPiS_iS_PiS_iS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4168:
.size _Z5checkPiS_iS_, .-_Z5checkPiS_iS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5checkPiS_iS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4170:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5checkPiS_iS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4170:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv,comdat
.align 2
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv, @function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv:
.LFB4804:
.cfi_startproc
endbr64
movq %rdi, %rdx
leaq 1816(%rdi), %r9
movq %rdi, %rcx
movl $2567483615, %r8d
.L15:
movq (%rcx), %rax
andq $-2147483648, %rax
movq 8(%rcx), %rsi
andl $2147483647, %esi
orq %rsi, %rax
movq %rax, %rsi
shrq %rsi
xorq 3176(%rcx), %rsi
andl $1, %eax
cmovne %r8, %rax
xorq %rsi, %rax
movq %rax, (%rcx)
addq $8, %rcx
cmpq %r9, %rcx
jne .L15
leaq 3168(%rdi), %r8
movl $2567483615, %esi
.L17:
movq 1816(%rdx), %rax
andq $-2147483648, %rax
movq 1824(%rdx), %rcx
andl $2147483647, %ecx
orq %rcx, %rax
movq %rax, %rcx
shrq %rcx
xorq (%rdx), %rcx
andl $1, %eax
cmovne %rsi, %rax
xorq %rcx, %rax
movq %rax, 1816(%rdx)
addq $8, %rdx
cmpq %r8, %rdx
jne .L17
movq 4984(%rdi), %rax
andq $-2147483648, %rax
movq (%rdi), %rdx
andl $2147483647, %edx
orq %rdx, %rax
movq %rax, %rdx
shrq %rdx
xorq 3168(%rdi), %rdx
andl $1, %eax
movl $2567483615, %ecx
cmovne %rcx, %rax
xorq %rdx, %rax
movq %rax, 4984(%rdi)
movq $0, 4992(%rdi)
ret
.cfi_endproc
.LFE4804:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv, .-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,comdat
.align 2
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, @function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv:
.LFB4743:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
cmpq $623, 4992(%rdi)
ja .L24
.L22:
movq 4992(%rbx), %rax
leaq 1(%rax), %rdx
movq %rdx, 4992(%rbx)
movq (%rbx,%rax,8), %rax
movq %rax, %rdx
shrq $11, %rdx
movl %edx, %edx
xorq %rax, %rdx
movq %rdx, %rax
salq $7, %rax
andl $2636928640, %eax
xorq %rdx, %rax
movq %rax, %rdx
salq $15, %rdx
andl $4022730752, %edx
xorq %rax, %rdx
movq %rdx, %rax
shrq $18, %rax
xorq %rdx, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
jmp .L22
.cfi_endproc
.LFE4743:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, .-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.section .text._ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,"axG",@progbits,_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,comdat
.align 2
.weak _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.type _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE, @function
_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE:
.LFB4642:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbp
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movslq 4(%rdx), %rbx
movslq (%rdx), %rax
subq %rax, %rbx
movl $4294967294, %eax
cmpq %rbx, %rax
jnb .L36
movq %rdi, %r14
movq %rbx, %rax
shrq $32, %rax
je .L30
movq %rsp, %r15
.L34:
movl $0, (%rsp)
movl $-1, 4(%rsp)
movq %r15, %rdx
movq %rbp, %rsi
movq %r14, %rdi
call _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
movq %rax, %r13
salq $32, %r13
movq %rbp, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
addq %r13, %rax
cmpq %rax, %rbx
jb .L34
cmpq %r13, %rax
jb .L34
jmp .L29
.L36:
addq $1, %rbx
movq %rsi, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %rbx, %rax
movq %rax, %rcx
cmpl %ebx, %eax
jnb .L27
movl %ebx, %eax
negl %eax
movl $0, %edx
divl %ebx
movl %edx, %r13d
cmpl %edx, %ecx
jnb .L27
.L28:
movq %rbp, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %rbx, %rax
movq %rax, %rcx
cmpl %r13d, %eax
jb .L28
.L27:
movq %rcx, %rax
shrq $32, %rax
.L29:
addl (%r12), %eax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L37
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movq %rsi, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
jmp .L29
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4642:
.size _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE, .-_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.text
.globl _Z9getRandomi
.type _Z9getRandomi, @function
_Z9getRandomi:
.LFB4141:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4141
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $4096, %rsp
.cfi_def_cfa_offset 4112
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 8208
orq $0, (%rsp)
subq $1840, %rsp
.cfi_def_cfa_offset 10048
movl %edi, %ebx
movq %fs:40, %rax
movq %rax, 10024(%rsp)
xorl %eax, %eax
leaq 5024(%rsp), %rsi
leaq 5040(%rsp), %rax
movq %rax, 5024(%rsp)
movl $1634100580, 5040(%rsp)
movl $1953264993, 5043(%rsp)
movq $7, 5032(%rsp)
movb $0, 5047(%rsp)
leaq 16(%rsp), %rdi
.LEHB0:
call _ZNSt13random_device7_M_initERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@PLT
.LEHE0:
movq 5024(%rsp), %rdi
leaq 5040(%rsp), %rax
cmpq %rax, %rdi
je .L39
movq 5040(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L39:
leaq 16(%rsp), %rdi
.LEHB1:
call _ZNSt13random_device9_M_getvalEv@PLT
.LEHE1:
movl %eax, %eax
movq %rax, 5024(%rsp)
movl $1, %ecx
movabsq $945986875574848801, %rdi
.L43:
movq 5016(%rsp,%rcx,8), %rax
movq %rax, %rdx
shrq $30, %rdx
xorq %rdx, %rax
imulq $1812433253, %rax, %rsi
movq %rcx, %rdx
shrq $4, %rdx
movq %rdx, %rax
mulq %rdi
shrq %rdx
imulq $624, %rdx, %rdx
movq %rcx, %rax
subq %rdx, %rax
addl %esi, %eax
movq %rax, 5024(%rsp,%rcx,8)
addq $1, %rcx
cmpq $624, %rcx
jne .L43
movq $624, 10016(%rsp)
movl $0, 8(%rsp)
movl %ebx, 12(%rsp)
leaq 8(%rsp), %rdi
leaq 5024(%rsp), %rsi
movq %rdi, %rdx
call _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
movl %eax, %ebx
leaq 16(%rsp), %rdi
call _ZNSt13random_device7_M_finiEv@PLT
movq 10024(%rsp), %rax
subq %fs:40, %rax
jne .L52
movl %ebx, %eax
addq $10032, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 5024(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 10024(%rsp), %rax
subq %fs:40, %rax
je .L42
call __stack_chk_fail@PLT
.L42:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L47:
endbr64
movq %rax, %rbx
leaq 16(%rsp), %rdi
call _ZNSt13random_device7_M_finiEv@PLT
movq 10024(%rsp), %rax
subq %fs:40, %rax
je .L45
call __stack_chk_fail@PLT
.L45:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4141:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4141:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4141-.LLSDACSB4141
.LLSDACSB4141:
.uleb128 .LEHB0-.LFB4141
.uleb128 .LEHE0-.LEHB0
.uleb128 .L48-.LFB4141
.uleb128 0
.uleb128 .LEHB1-.LFB4141
.uleb128 .LEHE1-.LEHB1
.uleb128 .L47-.LFB4141
.uleb128 0
.uleb128 .LEHB2-.LFB4141
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB4141
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE4141:
.text
.size _Z9getRandomi, .-_Z9getRandomi
.globl injective
.type injective, @function
injective:
.LFB4142:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %r14d
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movslq %edi, %r13
leaq 0(,%r13,4), %r12
leaq 8(%rsp), %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
testl %r14d, %r14d
jle .L54
movl $0, %ebx
.L55:
movq 8(%rsp), %rax
movl %ebx, (%rax,%rbx,4)
movq 16(%rsp), %rax
leaq (%rax,%rbx,4), %r15
movl %ebp, %edi
call _Z9getRandomi
movl %eax, (%r15)
movq 24(%rsp), %rax
movl $1, (%rax,%rbx,4)
addq $1, %rbx
cmpq %rbx, %r13
jne .L55
.L54:
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leal 510(%r14), %eax
movl %r14d, %edx
addl $255, %edx
cmovns %edx, %eax
sarl $8, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L66
.L56:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L67
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
testl %r14d, %r14d
jle .L59
movq 24(%rsp), %rdi
movq %rdi, %rax
addq %rdi, %r12
.L61:
movl (%rax), %ebx
testl %ebx, %ebx
je .L68
addq $4, %rax
cmpq %r12, %rax
jne .L61
.L59:
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $1, %ebx
jmp .L53
.L66:
movq 24(%rsp), %rcx
movl %r14d, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z5checkPiS_iS_PiS_iS_
jmp .L56
.L67:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $-1, %ebx
.L53:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L69
movl %ebx, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
call cudaFree@PLT
jmp .L53
.L69:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4142:
.size injective, .-injective
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
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You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <random>
int getRandom(int n) {
std::random_device rd;
std::mt19937 gen(rd());
std::uniform_int_distribution<> dis(0, n);
return dis(gen);
}
__global__
void check(int *fDictX, int *fDictY, int sizeOfFDict, int *currInjective) {
int idxInit = blockIdx.x * blockDim.x + threadIdx.x; // this is the initial global index
if (idxInit < sizeOfFDict) { // make sure we're not out of bounds
// grid-stride loop
for (int idx = idxInit; idx <= sizeOfFDict; idx += blockDim.x * gridDim.x) {
// this inner loop will do the work for a thread in each grid
for (int i=idx; i < sizeOfFDict; i++) {
if (fDictY[idx] == fDictY[i] && fDictX[idx] != fDictX[i]) {
currInjective[idx] = 0; // this will insert a zero into INJECTIVE
break;
}
}
}
}
}
extern "C" {
int injective(int maxDomain, int maxCodomain) {
// declare the arrays
int *domainX, *domainY, *INJECTIVE;
// allocated Unified Memory
cudaMallocManaged(&domainX, maxDomain*sizeof(int));
cudaMallocManaged(&domainY, maxDomain*sizeof(int));
cudaMallocManaged(&INJECTIVE, maxDomain*sizeof(int));
// initialize function
for (int i = 0; i < maxDomain; i++) {
domainX[i] = i;
domainY[i] = getRandom(maxCodomain);
INJECTIVE[i] = 1; // here we assume that the function is injective
}
// actually make the kernel call
// this is currently running with thread blocks of size 256. I may find a better number
// to tune that too. It's <<< numBlocks, numThreads >>>
check<<<(maxDomain+255)/256, 256>>>(domainX, domainY, maxDomain, INJECTIVE);
cudaDeviceSynchronize(); // sync the host and device
// error checking
if (cudaSuccess != cudaGetLastError()) {
cudaFree(domainX);
cudaFree(domainY);
cudaFree(INJECTIVE);
return -1; // this will be used to raise a RuntimeError
}
// free the unified memory
cudaFree(domainX);
cudaFree(domainY);
for (int i = 0; i < maxDomain; i++) {
if (INJECTIVE[i] == 0) { // 0 => false so the function is not injective
cudaFree(INJECTIVE);
return 0;
}
}
cudaFree(INJECTIVE);
return 1; // the function is injective
}
}
|
#include <hip/hip_runtime.h>
#include <random>
int getRandom(int n) {
std::random_device rd;
std::mt19937 gen(rd());
std::uniform_int_distribution<> dis(0, n);
return dis(gen);
}
__global__
void check(int *fDictX, int *fDictY, int sizeOfFDict, int *currInjective) {
int idxInit = blockIdx.x * blockDim.x + threadIdx.x; // this is the initial global index
if (idxInit < sizeOfFDict) { // make sure we're not out of bounds
// grid-stride loop
for (int idx = idxInit; idx <= sizeOfFDict; idx += blockDim.x * gridDim.x) {
// this inner loop will do the work for a thread in each grid
for (int i=idx; i < sizeOfFDict; i++) {
if (fDictY[idx] == fDictY[i] && fDictX[idx] != fDictX[i]) {
currInjective[idx] = 0; // this will insert a zero into INJECTIVE
break;
}
}
}
}
}
extern "C" {
int injective(int maxDomain, int maxCodomain) {
// declare the arrays
int *domainX, *domainY, *INJECTIVE;
// allocated Unified Memory
hipMallocManaged(&domainX, maxDomain*sizeof(int));
hipMallocManaged(&domainY, maxDomain*sizeof(int));
hipMallocManaged(&INJECTIVE, maxDomain*sizeof(int));
// initialize function
for (int i = 0; i < maxDomain; i++) {
domainX[i] = i;
domainY[i] = getRandom(maxCodomain);
INJECTIVE[i] = 1; // here we assume that the function is injective
}
// actually make the kernel call
// this is currently running with thread blocks of size 256. I may find a better number
// to tune that too. It's <<< numBlocks, numThreads >>>
check<<<(maxDomain+255)/256, 256>>>(domainX, domainY, maxDomain, INJECTIVE);
hipDeviceSynchronize(); // sync the host and device
// error checking
if (hipSuccess != hipGetLastError()) {
hipFree(domainX);
hipFree(domainY);
hipFree(INJECTIVE);
return -1; // this will be used to raise a RuntimeError
}
// free the unified memory
hipFree(domainX);
hipFree(domainY);
for (int i = 0; i < maxDomain; i++) {
if (INJECTIVE[i] == 0) { // 0 => false so the function is not injective
hipFree(INJECTIVE);
return 0;
}
}
hipFree(INJECTIVE);
return 1; // the function is injective
}
}
|
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