system
stringclasses 7
values | input
stringlengths 10
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You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z11generateImgPhS_S_P4int4ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0040*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R9, R9, c[0x0][0x0], R0 ; /* 0x0000000009097a24 */
/* 0x001fe400078e0200 */
/*0070*/ IMAD R0, R2, c[0x0][0x4], R3 ; /* 0x0000010002007a24 */
/* 0x002fc800078e0203 */
/*0080*/ IMAD R9, R0, c[0x0][0x184], R9 ; /* 0x0000610000097a24 */
/* 0x000fca00078e0209 */
/*0090*/ SHF.R.S32.HI R0, RZ, 0x1f, R9 ; /* 0x0000001fff007819 */
/* 0x000fe40000011409 */
/*00a0*/ IADD3 R2, P0, R9, c[0x0][0x160], RZ ; /* 0x0000580009027a10 */
/* 0x000fc80007f1e0ff */
/*00b0*/ IADD3.X R3, R0, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000037a10 */
/* 0x000fca00007fe4ff */
/*00c0*/ LDG.E.U8 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1100 */
/*00d0*/ BSSY B0, 0x170 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*00e0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff067624 */
/* 0x000fe200078e00ff */
/*00f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0100*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x004fda0003f25270 */
/*0110*/ @P1 BRA 0x160 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R4, P0, R9, c[0x0][0x170], RZ ; /* 0x00005c0009047a10 */
/* 0x000fc80007f1e0ff */
/*0130*/ IADD3.X R5, R0, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0000057a10 */
/* 0x000fca00007fe4ff */
/*0140*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1100 */
/*0150*/ ISETP.EQ.AND P0, PT, R4, c[0x0][0x180], PT ; /* 0x0000600004007a0c */
/* 0x004fd00003f02270 */
/*0160*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.EQ.OR P0, PT, R6, 0x1, !P0 ; /* 0x000000010600780c */
/* 0x000fda0004702670 */
/*0180*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0190*/ LEA R4, P0, R9, c[0x0][0x178], 0x4 ; /* 0x00005e0009047a11 */
/* 0x000fc800078020ff */
/*01a0*/ LEA.HI.X R5, R9, c[0x0][0x17c], R0, 0x4, P0 ; /* 0x00005f0009057a11 */
/* 0x000fcc00000f2400 */
/*01b0*/ LDG.E.128 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1d00 */
/*01c0*/ IADD3 R10, P0, R4, c[0x0][0x160], RZ ; /* 0x00005800040a7a10 */
/* 0x004fe40007f1e0ff */
/*01d0*/ IADD3 R12, P1, R5.reuse, c[0x0][0x160], RZ ; /* 0x00005800050c7a10 */
/* 0x040fe40007f3e0ff */
/*01e0*/ IADD3 R14, P2, R6, c[0x0][0x160], RZ ; /* 0x00005800060e7a10 */
/* 0x000fe40007f5e0ff */
/*01f0*/ LEA.HI.X.SX32 R11, R4, c[0x0][0x164], 0x1, P0 ; /* 0x00005900040b7a11 */
/* 0x000fe400000f0eff */
/*0200*/ LEA.HI.X.SX32 R13, R5, c[0x0][0x164], 0x1, P1 ; /* 0x00005900050d7a11 */
/* 0x000fc400008f0eff */
/*0210*/ IADD3 R16, P0, R7.reuse, c[0x0][0x160], RZ ; /* 0x0000580007107a10 */
/* 0x040fe20007f1e0ff */
/*0220*/ LDG.E.U8 R8, [R10.64] ; /* 0x000000040a087981 */
/* 0x0000a2000c1e1100 */
/*0230*/ LEA.HI.X.SX32 R15, R6, c[0x0][0x164], 0x1, P2 ; /* 0x00005900060f7a11 */
/* 0x000fe400010f0eff */
/*0240*/ LEA.HI.X.SX32 R17, R7, c[0x0][0x164], 0x1, P0 ; /* 0x0000590007117a11 */
/* 0x000fe200000f0eff */
/*0250*/ LDG.E.U8 R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ea8000c1e1100 */
/*0260*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea8000c1e1100 */
/*0270*/ LDG.E.U8 R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee2000c1e1100 */
/*0280*/ ISETP.NE.AND P3, PT, R5, -0x1, PT ; /* 0xffffffff0500780c */
/* 0x000fe20003f65270 */
/*0290*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe200078e00ff */
/*02a0*/ ISETP.NE.AND P0, PT, R4, -0x1, PT ; /* 0xffffffff0400780c */
/* 0x000fc40003f05270 */
/*02b0*/ ISETP.NE.AND P1, PT, R6, -0x1, PT ; /* 0xffffffff0600780c */
/* 0x000fe40003f25270 */
/*02c0*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fe40004000000 */
/*02d0*/ ISETP.NE.AND P2, PT, R7, -0x1, PT ; /* 0xffffffff0700780c */
/* 0x000fca0003f45270 */
/*02e0*/ @P3 SEL R4, R5, 0x2, !P0 ; /* 0x0000000205043807 */
/* 0x000fe40004000000 */
/*02f0*/ SEL R5, RZ, 0x1, !P1 ; /* 0x00000001ff057807 */
/* 0x000fca0004800000 */
/*0300*/ IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104047824 */
/* 0x000fca00078e0205 */
/*0310*/ IADD3 R11, R4, 0x1, RZ ; /* 0x00000001040b7810 */
/* 0x001fe20007ffe0ff */
/*0320*/ @!P2 IMAD.MOV R11, RZ, RZ, R4 ; /* 0x000000ffff0ba224 */
/* 0x000fc800078e0204 */
/*0330*/ I2F.U32.RP R6, R11 ; /* 0x0000000b00067306 */
/* 0x000e300000209000 */
/*0340*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0350*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0360*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0370*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0380*/ IMAD.MOV R10, RZ, RZ, -R5 ; /* 0x000000ffff0a7224 */
/* 0x002fc800078e0a05 */
/*0390*/ IMAD R7, R10, R11, RZ ; /* 0x0000000b0a077224 */
/* 0x000fc800078e02ff */
/*03a0*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fe200078e0004 */
/*03b0*/ ISETP.NE.U32.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f45070 */
/*03c0*/ IADD3 R8, R14, R13, R8 ; /* 0x0000000d0e087210 */
/* 0x004fca0007ffe008 */
/*03d0*/ IMAD.IADD R8, R8, 0x1, R17 ; /* 0x0000000108087824 */
/* 0x008fc800078e0211 */
/*03e0*/ IMAD.HI.U32 R7, R5, R8, RZ ; /* 0x0000000805077227 */
/* 0x000fc800078e00ff */
/*03f0*/ IMAD.MOV R5, RZ, RZ, -R7 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a07 */
/*0400*/ IMAD R8, R5, R11, R8 ; /* 0x0000000b05087224 */
/* 0x000fca00078e0208 */
/*0410*/ ISETP.GE.U32.AND P0, PT, R8, R11, PT ; /* 0x0000000b0800720c */
/* 0x000fda0003f06070 */
/*0420*/ @P0 IMAD.IADD R8, R8, 0x1, -R11 ; /* 0x0000000108080824 */
/* 0x000fca00078e0a0b */
/*0430*/ ISETP.GE.U32.AND P1, PT, R8, R11, PT ; /* 0x0000000b0800720c */
/* 0x000fe40003f26070 */
/*0440*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fe40007ffe0ff */
/*0450*/ IADD3 R4, P0, R9, c[0x0][0x168], RZ ; /* 0x00005a0009047a10 */
/* 0x000fc80007f1e0ff */
/*0460*/ IADD3.X R5, R0, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0000057a10 */
/* 0x000fca00007fe4ff */
/*0470*/ @P1 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107071810 */
/* 0x000fe40007ffe0ff */
/*0480*/ @!P2 LOP3.LUT R7, RZ, R11, RZ, 0x33, !PT ; /* 0x0000000bff07a212 */
/* 0x000fca00078e33ff */
/*0490*/ STG.E.U8 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101104 */
/*04a0*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101104 */
/*04b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04c0*/ BRA 0x4c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11generateImgPhS_S_P15HIP_vector_typeIiLj4EEii
.globl _Z11generateImgPhS_S_P15HIP_vector_typeIiLj4EEii
.p2align 8
.type _Z11generateImgPhS_S_P15HIP_vector_typeIiLj4EEii,@function
_Z11generateImgPhS_S_P15HIP_vector_typeIiLj4EEii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s5, s[0:1], 0x24
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_load_b64 s[2:3], s[0:1], 0x0
s_mul_i32 s14, s14, s4
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s5
v_add3_u32 v0, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
global_load_u8 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u16_e32 0, v4
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s6, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
s_cmp_lg_u32 s6, 1
s_cselect_b32 s4, -1, 0
global_load_u8 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s6, v4
s_and_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x18
v_lshlrev_b64 v[4:5], 4, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b128 v[4:7], v[4:5], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v9, 31, v4
v_ashrrev_i32_e32 v10, 31, v5
v_add_co_u32 v15, vcc_lo, s2, v4
v_ashrrev_i32_e32 v12, 31, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v16, vcc_lo, s3, v9, vcc_lo
v_add_co_u32 v17, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v18, vcc_lo, s3, v10, vcc_lo
v_ashrrev_i32_e32 v14, 31, v7
v_add_co_u32 v19, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v20, vcc_lo, s3, v12, vcc_lo
s_clause 0x1
global_load_u8 v21, v[15:16], off
global_load_u8 v17, v[17:18], off
v_add_co_u32 v15, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v16, vcc_lo, s3, v14, vcc_lo
s_clause 0x1
global_load_u8 v18, v[19:20], off
global_load_u8 v15, v[15:16], off
v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v11, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u64_e32 vcc_lo, -1, v[8:9]
v_mov_b32_e32 v9, v5
v_cndmask_b32_e64 v4, 0, 1, vcc_lo
v_cndmask_b32_e64 v5, 1, 2, vcc_lo
v_cmp_ne_u64_e32 vcc_lo, -1, v[11:12]
v_cndmask_b32_e64 v6, 0, 1, vcc_lo
v_cmp_eq_u64_e32 vcc_lo, -1, v[9:10]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v13, v7 :: v_dual_cndmask_b32 v4, v5, v4
v_cmp_ne_u64_e32 vcc_lo, -1, v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u16 v4, v4, v6
v_cndmask_b32_e64 v5, 0, 1, vcc_lo
v_add_nc_u16 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cvt_f32_ubyte0_e32 v4, v4
s_waitcnt vmcnt(2)
v_add_nc_u16 v6, v17, v21
s_waitcnt vmcnt(1)
v_add_nc_u16 v5, v6, v18
v_rcp_iflag_f32_e32 v6, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u16 v5, v5, v15
v_and_b32_e32 v5, 0xffff, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v6, v5, v6
v_trunc_f32_e32 v6, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v5, -v6, v4, v5
v_cvt_u32_f32_e32 v6, v6
v_cmp_ge_f32_e64 vcc_lo, |v5|, |v4|
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v6, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b8 v[2:3], v4, off
global_store_b8 v[0:1], v4, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11generateImgPhS_S_P15HIP_vector_typeIiLj4EEii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 22
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11generateImgPhS_S_P15HIP_vector_typeIiLj4EEii, .Lfunc_end0-_Z11generateImgPhS_S_P15HIP_vector_typeIiLj4EEii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11generateImgPhS_S_P15HIP_vector_typeIiLj4EEii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11generateImgPhS_S_P15HIP_vector_typeIiLj4EEii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 22
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
/*
**********************************************
* CS314 Principles of Programming Languages *
* Spring 2020 *
**********************************************
*/
#include <stdio.h>
#include <stdlib.h>
__global__ void check_handshaking_gpu(int * strongNeighbor, int * matches, int numNodes) {
/*YOUR CODE HERE*/
int tid = blockIdx.x * blockDim.x + threadIdx.x;//this is the thread id and will be used as index
while( tid < numNodes )//as long as thread id is within numNodes(array bounds)
{
if( tid == strongNeighbor[strongNeighbor[tid]] )
{
if( matches[tid] == -1 && matches[strongNeighbor[tid]] == -1 )//both need to equal -1, both nodes are unmatched
{
matches[tid] = strongNeighbor[tid];
matches[strongNeighbor[tid]] = strongNeighbor[strongNeighbor[tid]];
}
}
tid += ( blockDim.x * gridDim.x );
}
return;
}
|
code for sm_80
Function : _Z21check_handshaking_gpuPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0080*/ IMAD.WIDE R6, R0, R5, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fca00078e0205 */
/*0090*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IMAD.WIDE R2, R10, R5, c[0x0][0x160] ; /* 0x000058000a027625 */
/* 0x004fcc00078e0205 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ BSSY B0, 0x220 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*00d0*/ ISETP.NE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x004fda0003f05270 */
/*00e0*/ @P0 BRA 0x210 ; /* 0x0000012000000947 */
/* 0x000fea0003800000 */
/*00f0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe40000011400 */
/*0100*/ LEA R8, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000087a11 */
/* 0x000fc800078010ff */
/*0110*/ LEA.HI.X R9, R0, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0000097a11 */
/* 0x000fca00000f1403 */
/*0120*/ LDG.E R2, [R8.64] ; /* 0x0000000408027981 */
/* 0x000ea4000c1e1900 */
/*0130*/ ISETP.NE.AND P0, PT, R2, -0x1, PT ; /* 0xffffffff0200780c */
/* 0x004fda0003f05270 */
/*0140*/ @P0 BRA 0x210 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*0150*/ SHF.R.S32.HI R3, RZ, 0x1f, R10 ; /* 0x0000001fff037819 */
/* 0x000fe4000001140a */
/*0160*/ LEA R2, P0, R10, c[0x0][0x168], 0x2 ; /* 0x00005a000a027a11 */
/* 0x000fc800078010ff */
/*0170*/ LEA.HI.X R3, R10, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b000a037a11 */
/* 0x000fca00000f1403 */
/*0180*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*0190*/ ISETP.NE.AND P0, PT, R2, -0x1, PT ; /* 0xffffffff0200780c */
/* 0x004fda0003f05270 */
/*01a0*/ @P0 BRA 0x210 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*01b0*/ STG.E [R8.64], R10 ; /* 0x0000000a08007986 */
/* 0x0001e8000c101904 */
/*01c0*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x000ea4000c1e1900 */
/*01d0*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x004fcc00078e0205 */
/*01e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*01f0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*0200*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0041e4000c101904 */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x001fc800078e00ff */
/*0230*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x000fca00078e0200 */
/*0240*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0250*/ @!P0 BRA 0x70 ; /* 0xfffffe1000008947 */
/* 0x000fea000383ffff */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
/*
**********************************************
* CS314 Principles of Programming Languages *
* Spring 2020 *
**********************************************
*/
#include <stdio.h>
#include <stdlib.h>
__global__ void check_handshaking_gpu(int * strongNeighbor, int * matches, int numNodes) {
/*YOUR CODE HERE*/
int tid = blockIdx.x * blockDim.x + threadIdx.x;//this is the thread id and will be used as index
while( tid < numNodes )//as long as thread id is within numNodes(array bounds)
{
if( tid == strongNeighbor[strongNeighbor[tid]] )
{
if( matches[tid] == -1 && matches[strongNeighbor[tid]] == -1 )//both need to equal -1, both nodes are unmatched
{
matches[tid] = strongNeighbor[tid];
matches[strongNeighbor[tid]] = strongNeighbor[strongNeighbor[tid]];
}
}
tid += ( blockDim.x * gridDim.x );
}
return;
}
|
.file "tmpxft_00113131_00000000-6_check_handshaking.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z21check_handshaking_gpuPiS_iPiS_i
.type _Z44__device_stub__Z21check_handshaking_gpuPiS_iPiS_i, @function
_Z44__device_stub__Z21check_handshaking_gpuPiS_iPiS_i:
.LFB2081:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21check_handshaking_gpuPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z44__device_stub__Z21check_handshaking_gpuPiS_iPiS_i, .-_Z44__device_stub__Z21check_handshaking_gpuPiS_iPiS_i
.globl _Z21check_handshaking_gpuPiS_i
.type _Z21check_handshaking_gpuPiS_i, @function
_Z21check_handshaking_gpuPiS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z21check_handshaking_gpuPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z21check_handshaking_gpuPiS_i, .-_Z21check_handshaking_gpuPiS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21check_handshaking_gpuPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21check_handshaking_gpuPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/*
**********************************************
* CS314 Principles of Programming Languages *
* Spring 2020 *
**********************************************
*/
#include <stdio.h>
#include <stdlib.h>
__global__ void check_handshaking_gpu(int * strongNeighbor, int * matches, int numNodes) {
/*YOUR CODE HERE*/
int tid = blockIdx.x * blockDim.x + threadIdx.x;//this is the thread id and will be used as index
while( tid < numNodes )//as long as thread id is within numNodes(array bounds)
{
if( tid == strongNeighbor[strongNeighbor[tid]] )
{
if( matches[tid] == -1 && matches[strongNeighbor[tid]] == -1 )//both need to equal -1, both nodes are unmatched
{
matches[tid] = strongNeighbor[tid];
matches[strongNeighbor[tid]] = strongNeighbor[strongNeighbor[tid]];
}
}
tid += ( blockDim.x * gridDim.x );
}
return;
}
|
/*
**********************************************
* CS314 Principles of Programming Languages *
* Spring 2020 *
**********************************************
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void check_handshaking_gpu(int * strongNeighbor, int * matches, int numNodes) {
/*YOUR CODE HERE*/
int tid = blockIdx.x * blockDim.x + threadIdx.x;//this is the thread id and will be used as index
while( tid < numNodes )//as long as thread id is within numNodes(array bounds)
{
if( tid == strongNeighbor[strongNeighbor[tid]] )
{
if( matches[tid] == -1 && matches[strongNeighbor[tid]] == -1 )//both need to equal -1, both nodes are unmatched
{
matches[tid] = strongNeighbor[tid];
matches[strongNeighbor[tid]] = strongNeighbor[strongNeighbor[tid]];
}
}
tid += ( blockDim.x * gridDim.x );
}
return;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
/*
**********************************************
* CS314 Principles of Programming Languages *
* Spring 2020 *
**********************************************
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void check_handshaking_gpu(int * strongNeighbor, int * matches, int numNodes) {
/*YOUR CODE HERE*/
int tid = blockIdx.x * blockDim.x + threadIdx.x;//this is the thread id and will be used as index
while( tid < numNodes )//as long as thread id is within numNodes(array bounds)
{
if( tid == strongNeighbor[strongNeighbor[tid]] )
{
if( matches[tid] == -1 && matches[strongNeighbor[tid]] == -1 )//both need to equal -1, both nodes are unmatched
{
matches[tid] = strongNeighbor[tid];
matches[strongNeighbor[tid]] = strongNeighbor[strongNeighbor[tid]];
}
}
tid += ( blockDim.x * gridDim.x );
}
return;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21check_handshaking_gpuPiS_i
.globl _Z21check_handshaking_gpuPiS_i
.p2align 8
.type _Z21check_handshaking_gpuPiS_i,@function
_Z21check_handshaking_gpuPiS_i:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_7
s_load_b32 s6, s[2:3], 0x0
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s5, s6, s5
s_mov_b32 s6, 0
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v1, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s4, v1
s_or_b32 s6, vcc_lo, s6
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB0_7
.LBB0_3:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v8, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[5:6], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v6, vcc_lo
global_load_b32 v0, v[9:10], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 v1, v0
s_cbranch_execz .LBB0_2
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v0, v[7:8], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, -1, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v0, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, -1, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
global_store_b32 v[7:8], v4, off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v0, v[4:5], off
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v0, off
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21check_handshaking_gpuPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21check_handshaking_gpuPiS_i, .Lfunc_end0-_Z21check_handshaking_gpuPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21check_handshaking_gpuPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21check_handshaking_gpuPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
/*
**********************************************
* CS314 Principles of Programming Languages *
* Spring 2020 *
**********************************************
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void check_handshaking_gpu(int * strongNeighbor, int * matches, int numNodes) {
/*YOUR CODE HERE*/
int tid = blockIdx.x * blockDim.x + threadIdx.x;//this is the thread id and will be used as index
while( tid < numNodes )//as long as thread id is within numNodes(array bounds)
{
if( tid == strongNeighbor[strongNeighbor[tid]] )
{
if( matches[tid] == -1 && matches[strongNeighbor[tid]] == -1 )//both need to equal -1, both nodes are unmatched
{
matches[tid] = strongNeighbor[tid];
matches[strongNeighbor[tid]] = strongNeighbor[strongNeighbor[tid]];
}
}
tid += ( blockDim.x * gridDim.x );
}
return;
}
|
.text
.file "check_handshaking.hip"
.globl _Z36__device_stub__check_handshaking_gpuPiS_i # -- Begin function _Z36__device_stub__check_handshaking_gpuPiS_i
.p2align 4, 0x90
.type _Z36__device_stub__check_handshaking_gpuPiS_i,@function
_Z36__device_stub__check_handshaking_gpuPiS_i: # @_Z36__device_stub__check_handshaking_gpuPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21check_handshaking_gpuPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z36__device_stub__check_handshaking_gpuPiS_i, .Lfunc_end0-_Z36__device_stub__check_handshaking_gpuPiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21check_handshaking_gpuPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21check_handshaking_gpuPiS_i,@object # @_Z21check_handshaking_gpuPiS_i
.section .rodata,"a",@progbits
.globl _Z21check_handshaking_gpuPiS_i
.p2align 3, 0x0
_Z21check_handshaking_gpuPiS_i:
.quad _Z36__device_stub__check_handshaking_gpuPiS_i
.size _Z21check_handshaking_gpuPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21check_handshaking_gpuPiS_i"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__check_handshaking_gpuPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21check_handshaking_gpuPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z21check_handshaking_gpuPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0080*/ IMAD.WIDE R6, R0, R5, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fca00078e0205 */
/*0090*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IMAD.WIDE R2, R10, R5, c[0x0][0x160] ; /* 0x000058000a027625 */
/* 0x004fcc00078e0205 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ BSSY B0, 0x220 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*00d0*/ ISETP.NE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x004fda0003f05270 */
/*00e0*/ @P0 BRA 0x210 ; /* 0x0000012000000947 */
/* 0x000fea0003800000 */
/*00f0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe40000011400 */
/*0100*/ LEA R8, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000087a11 */
/* 0x000fc800078010ff */
/*0110*/ LEA.HI.X R9, R0, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0000097a11 */
/* 0x000fca00000f1403 */
/*0120*/ LDG.E R2, [R8.64] ; /* 0x0000000408027981 */
/* 0x000ea4000c1e1900 */
/*0130*/ ISETP.NE.AND P0, PT, R2, -0x1, PT ; /* 0xffffffff0200780c */
/* 0x004fda0003f05270 */
/*0140*/ @P0 BRA 0x210 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*0150*/ SHF.R.S32.HI R3, RZ, 0x1f, R10 ; /* 0x0000001fff037819 */
/* 0x000fe4000001140a */
/*0160*/ LEA R2, P0, R10, c[0x0][0x168], 0x2 ; /* 0x00005a000a027a11 */
/* 0x000fc800078010ff */
/*0170*/ LEA.HI.X R3, R10, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b000a037a11 */
/* 0x000fca00000f1403 */
/*0180*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*0190*/ ISETP.NE.AND P0, PT, R2, -0x1, PT ; /* 0xffffffff0200780c */
/* 0x004fda0003f05270 */
/*01a0*/ @P0 BRA 0x210 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*01b0*/ STG.E [R8.64], R10 ; /* 0x0000000a08007986 */
/* 0x0001e8000c101904 */
/*01c0*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x000ea4000c1e1900 */
/*01d0*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x004fcc00078e0205 */
/*01e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*01f0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*0200*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0041e4000c101904 */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x001fc800078e00ff */
/*0230*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x000fca00078e0200 */
/*0240*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0250*/ @!P0 BRA 0x70 ; /* 0xfffffe1000008947 */
/* 0x000fea000383ffff */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21check_handshaking_gpuPiS_i
.globl _Z21check_handshaking_gpuPiS_i
.p2align 8
.type _Z21check_handshaking_gpuPiS_i,@function
_Z21check_handshaking_gpuPiS_i:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_7
s_load_b32 s6, s[2:3], 0x0
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s5, s6, s5
s_mov_b32 s6, 0
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v1, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s4, v1
s_or_b32 s6, vcc_lo, s6
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB0_7
.LBB0_3:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v8, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[5:6], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v6, vcc_lo
global_load_b32 v0, v[9:10], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 v1, v0
s_cbranch_execz .LBB0_2
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v0, v[7:8], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, -1, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v0, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, -1, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
global_store_b32 v[7:8], v4, off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v0, v[4:5], off
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v0, off
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21check_handshaking_gpuPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21check_handshaking_gpuPiS_i, .Lfunc_end0-_Z21check_handshaking_gpuPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21check_handshaking_gpuPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21check_handshaking_gpuPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00113131_00000000-6_check_handshaking.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z21check_handshaking_gpuPiS_iPiS_i
.type _Z44__device_stub__Z21check_handshaking_gpuPiS_iPiS_i, @function
_Z44__device_stub__Z21check_handshaking_gpuPiS_iPiS_i:
.LFB2081:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21check_handshaking_gpuPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z44__device_stub__Z21check_handshaking_gpuPiS_iPiS_i, .-_Z44__device_stub__Z21check_handshaking_gpuPiS_iPiS_i
.globl _Z21check_handshaking_gpuPiS_i
.type _Z21check_handshaking_gpuPiS_i, @function
_Z21check_handshaking_gpuPiS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z21check_handshaking_gpuPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z21check_handshaking_gpuPiS_i, .-_Z21check_handshaking_gpuPiS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21check_handshaking_gpuPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21check_handshaking_gpuPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "check_handshaking.hip"
.globl _Z36__device_stub__check_handshaking_gpuPiS_i # -- Begin function _Z36__device_stub__check_handshaking_gpuPiS_i
.p2align 4, 0x90
.type _Z36__device_stub__check_handshaking_gpuPiS_i,@function
_Z36__device_stub__check_handshaking_gpuPiS_i: # @_Z36__device_stub__check_handshaking_gpuPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21check_handshaking_gpuPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z36__device_stub__check_handshaking_gpuPiS_i, .Lfunc_end0-_Z36__device_stub__check_handshaking_gpuPiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21check_handshaking_gpuPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21check_handshaking_gpuPiS_i,@object # @_Z21check_handshaking_gpuPiS_i
.section .rodata,"a",@progbits
.globl _Z21check_handshaking_gpuPiS_i
.p2align 3, 0x0
_Z21check_handshaking_gpuPiS_i:
.quad _Z36__device_stub__check_handshaking_gpuPiS_i
.size _Z21check_handshaking_gpuPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21check_handshaking_gpuPiS_i"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__check_handshaking_gpuPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21check_handshaking_gpuPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
/* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float* var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16) {
for (int i=0; i < var_1; ++i) {
comp = (var_3 / (+1.7978E34f - (var_4 - (var_5 * +1.5645E-8f))));
var_2[i] = atanf((-0.0f * (+0.0f + (var_6 / -1.8126E-23f - var_7 - var_8))));
float tmp_1 = var_9 / +1.5703E9f;
comp = tmp_1 * var_2[i] * (var_10 - +1.4446E-36f);
if (comp >= +1.7516E36f / (var_11 / (-1.0045E36f / var_12))) {
comp += +1.8739E36f * (var_13 * (+1.5092E15f + +1.8891E-35f));
float tmp_2 = (-1.1125E-41f / cosf(-1.7053E-44f * +1.7129E-42f));
float tmp_3 = -1.1475E-37f / (var_14 / var_15);
comp = tmp_3 + tmp_2 + (var_16 / +1.9488E-30f);
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float* tmp_3 = initPointer( atof(argv[3]) );
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17);
cudaDeviceSynchronize();
return 0;
}
|
.file "tmpxft_0002920e_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z42__device_stub__Z7computefiPffffffffffffffffiPfffffffffffffff
.type _Z42__device_stub__Z7computefiPffffffffffffffffiPfffffffffffffff, @function
_Z42__device_stub__Z7computefiPffffffffffffffffiPfffffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movq %rsi, 32(%rsp)
movss %xmm1, 28(%rsp)
movss %xmm2, 24(%rsp)
movss %xmm3, 20(%rsp)
movss %xmm4, 16(%rsp)
movss %xmm5, 12(%rsp)
movss %xmm6, 8(%rsp)
movss %xmm7, 4(%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 4(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
leaq 288(%rsp), %rax
movq %rax, 208(%rsp)
leaq 296(%rsp), %rax
movq %rax, 216(%rsp)
leaq 304(%rsp), %rax
movq %rax, 224(%rsp)
leaq 312(%rsp), %rax
movq %rax, 232(%rsp)
leaq 320(%rsp), %rax
movq %rax, 240(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 280
pushq 56(%rsp)
.cfi_def_cfa_offset 288
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7computefiPfffffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z42__device_stub__Z7computefiPffffffffffffffffiPfffffffffffffff, .-_Z42__device_stub__Z7computefiPffffffffffffffffiPfffffffffffffff
.globl _Z7computefiPfffffffffffffff
.type _Z7computefiPfffffffffffffff, @function
_Z7computefiPfffffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movss 128(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 120(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 112(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 104(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 96(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 88(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 80(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z42__device_stub__Z7computefiPffffffffffffffffiPfffffffffffffff
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefiPfffffffffffffff, .-_Z7computefiPfffffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $160, %rsp
.cfi_def_cfa_offset 192
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r12
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movl $1, 148(%rsp)
movl $1, 152(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 148(%rsp), %rdx
movl $1, %ecx
movq 136(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $160, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 120(%rsp), %xmm0
subq $64, %rsp
.cfi_def_cfa_offset 256
pxor %xmm1, %xmm1
cvtsd2ss 72(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 80(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 88(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 96(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 104(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 112(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 120(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 128(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 136(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 144(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 152(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 160(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 168(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 176(%rsp), %xmm1
movq %r12, %rsi
movl %ebp, %edi
call _Z42__device_stub__Z7computefiPffffffffffffffffiPfffffffffffffff
addq $64, %rsp
.cfi_def_cfa_offset 192
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7computefiPfffffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefiPfffffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float* var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16) {
for (int i=0; i < var_1; ++i) {
comp = (var_3 / (+1.7978E34f - (var_4 - (var_5 * +1.5645E-8f))));
var_2[i] = atanf((-0.0f * (+0.0f + (var_6 / -1.8126E-23f - var_7 - var_8))));
float tmp_1 = var_9 / +1.5703E9f;
comp = tmp_1 * var_2[i] * (var_10 - +1.4446E-36f);
if (comp >= +1.7516E36f / (var_11 / (-1.0045E36f / var_12))) {
comp += +1.8739E36f * (var_13 * (+1.5092E15f + +1.8891E-35f));
float tmp_2 = (-1.1125E-41f / cosf(-1.7053E-44f * +1.7129E-42f));
float tmp_3 = -1.1475E-37f / (var_14 / var_15);
comp = tmp_3 + tmp_2 + (var_16 / +1.9488E-30f);
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float* tmp_3 = initPointer( atof(argv[3]) );
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17);
cudaDeviceSynchronize();
return 0;
}
|
/* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float* var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16) {
for (int i=0; i < var_1; ++i) {
comp = (var_3 / (+1.7978E34f - (var_4 - (var_5 * +1.5645E-8f))));
var_2[i] = atanf((-0.0f * (+0.0f + (var_6 / -1.8126E-23f - var_7 - var_8))));
float tmp_1 = var_9 / +1.5703E9f;
comp = tmp_1 * var_2[i] * (var_10 - +1.4446E-36f);
if (comp >= +1.7516E36f / (var_11 / (-1.0045E36f / var_12))) {
comp += +1.8739E36f * (var_13 * (+1.5092E15f + +1.8891E-35f));
float tmp_2 = (-1.1125E-41f / cosf(-1.7053E-44f * +1.7129E-42f));
float tmp_3 = -1.1475E-37f / (var_14 / var_15);
comp = tmp_3 + tmp_2 + (var_16 / +1.9488E-30f);
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float* tmp_3 = initPointer( atof(argv[3]) );
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17);
hipDeviceSynchronize();
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
/* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float* var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16) {
for (int i=0; i < var_1; ++i) {
comp = (var_3 / (+1.7978E34f - (var_4 - (var_5 * +1.5645E-8f))));
var_2[i] = atanf((-0.0f * (+0.0f + (var_6 / -1.8126E-23f - var_7 - var_8))));
float tmp_1 = var_9 / +1.5703E9f;
comp = tmp_1 * var_2[i] * (var_10 - +1.4446E-36f);
if (comp >= +1.7516E36f / (var_11 / (-1.0045E36f / var_12))) {
comp += +1.8739E36f * (var_13 * (+1.5092E15f + +1.8891E-35f));
float tmp_2 = (-1.1125E-41f / cosf(-1.7053E-44f * +1.7129E-42f));
float tmp_3 = -1.1475E-37f / (var_14 / var_15);
comp = tmp_3 + tmp_2 + (var_16 / +1.9488E-30f);
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float* tmp_3 = initPointer( atof(argv[3]) );
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17);
hipDeviceSynchronize();
return 0;
}
|
.text
.file "test.hip"
.globl _Z22__device_stub__computefiPfffffffffffffff # -- Begin function _Z22__device_stub__computefiPfffffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefiPfffffffffffffff,@function
_Z22__device_stub__computefiPfffffffffffffff: # @_Z22__device_stub__computefiPfffffffffffffff
.cfi_startproc
# %bb.0:
subq $232, %rsp
.cfi_def_cfa_offset 240
movss %xmm0, 36(%rsp)
movl %edi, 32(%rsp)
movq %rsi, 88(%rsp)
movss %xmm1, 28(%rsp)
movss %xmm2, 24(%rsp)
movss %xmm3, 20(%rsp)
movss %xmm4, 16(%rsp)
movss %xmm5, 12(%rsp)
movss %xmm6, 8(%rsp)
movss %xmm7, 4(%rsp)
leaq 36(%rsp), %rax
movq %rax, 96(%rsp)
leaq 32(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 28(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 4(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
leaq 272(%rsp), %rax
movq %rax, 208(%rsp)
leaq 280(%rsp), %rax
movq %rax, 216(%rsp)
leaq 288(%rsp), %rax
movq %rax, 224(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computefiPfffffffffffffff, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $248, %rsp
.cfi_adjust_cfa_offset -248
retq
.Lfunc_end0:
.size _Z22__device_stub__computefiPfffffffffffffff, .Lfunc_end0-_Z22__device_stub__computefiPfffffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $376, %rsp # imm = 0x178
.cfi_def_cfa_offset 416
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r15
movq 8(%rsi), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movq 16(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r15), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r14
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq $10, %r12
jne .LBB2_1
# %bb.2: # %_Z11initPointerf.exit
movq 32(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, (%rsp) # 8-byte Spill
movq 40(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 48(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 56(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 152(%rsp) # 8-byte Spill
movq 64(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq 72(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 136(%rsp) # 8-byte Spill
movq 80(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 128(%rsp) # 8-byte Spill
movq 88(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq 96(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 112(%rsp) # 8-byte Spill
movq 104(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq 112(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 96(%rsp) # 8-byte Spill
movq 120(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 88(%rsp) # 8-byte Spill
movq 128(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 80(%rsp) # 8-byte Spill
movq 136(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 72(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movsd 72(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movsd 80(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
cvtsd2ss %xmm1, %xmm1
movsd 88(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
cvtsd2ss %xmm2, %xmm2
movsd 96(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
cvtsd2ss %xmm3, %xmm3
movsd 104(%rsp), %xmm4 # 8-byte Reload
# xmm4 = mem[0],zero
cvtsd2ss %xmm4, %xmm4
movsd 112(%rsp), %xmm5 # 8-byte Reload
# xmm5 = mem[0],zero
cvtsd2ss %xmm5, %xmm5
movsd 120(%rsp), %xmm6 # 8-byte Reload
# xmm6 = mem[0],zero
cvtsd2ss %xmm6, %xmm6
movsd 128(%rsp), %xmm7 # 8-byte Reload
# xmm7 = mem[0],zero
cvtsd2ss %xmm7, %xmm7
movsd 136(%rsp), %xmm8 # 8-byte Reload
# xmm8 = mem[0],zero
cvtsd2ss %xmm8, %xmm8
movsd 144(%rsp), %xmm9 # 8-byte Reload
# xmm9 = mem[0],zero
cvtsd2ss %xmm9, %xmm9
movsd 152(%rsp), %xmm10 # 8-byte Reload
# xmm10 = mem[0],zero
cvtsd2ss %xmm10, %xmm10
movsd 160(%rsp), %xmm11 # 8-byte Reload
# xmm11 = mem[0],zero
cvtsd2ss %xmm11, %xmm11
movsd 168(%rsp), %xmm12 # 8-byte Reload
# xmm12 = mem[0],zero
cvtsd2ss %xmm12, %xmm12
movsd (%rsp), %xmm13 # 8-byte Reload
# xmm13 = mem[0],zero
cvtsd2ss %xmm13, %xmm13
movsd 176(%rsp), %xmm14 # 8-byte Reload
# xmm14 = mem[0],zero
cvtsd2ss %xmm14, %xmm14
movss %xmm14, 68(%rsp)
movl %ebx, 64(%rsp)
movq %r14, 232(%rsp)
movss %xmm13, 60(%rsp)
movss %xmm12, 56(%rsp)
movss %xmm11, 52(%rsp)
movss %xmm10, 48(%rsp)
movss %xmm9, 44(%rsp)
movss %xmm8, 40(%rsp)
movss %xmm7, 36(%rsp)
movss %xmm6, 32(%rsp)
movss %xmm5, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm3, 20(%rsp)
movss %xmm2, 16(%rsp)
movss %xmm1, 12(%rsp)
movss %xmm0, 8(%rsp)
leaq 68(%rsp), %rax
movq %rax, 240(%rsp)
leaq 64(%rsp), %rax
movq %rax, 248(%rsp)
leaq 232(%rsp), %rax
movq %rax, 256(%rsp)
leaq 60(%rsp), %rax
movq %rax, 264(%rsp)
leaq 56(%rsp), %rax
movq %rax, 272(%rsp)
leaq 52(%rsp), %rax
movq %rax, 280(%rsp)
leaq 48(%rsp), %rax
movq %rax, 288(%rsp)
leaq 44(%rsp), %rax
movq %rax, 296(%rsp)
leaq 40(%rsp), %rax
movq %rax, 304(%rsp)
leaq 36(%rsp), %rax
movq %rax, 312(%rsp)
leaq 32(%rsp), %rax
movq %rax, 320(%rsp)
leaq 28(%rsp), %rax
movq %rax, 328(%rsp)
leaq 24(%rsp), %rax
movq %rax, 336(%rsp)
leaq 20(%rsp), %rax
movq %rax, 344(%rsp)
leaq 16(%rsp), %rax
movq %rax, 352(%rsp)
leaq 12(%rsp), %rax
movq %rax, 360(%rsp)
leaq 8(%rsp), %rax
movq %rax, 368(%rsp)
leaq 216(%rsp), %rdi
leaq 200(%rsp), %rsi
leaq 192(%rsp), %rdx
leaq 184(%rsp), %rcx
callq __hipPopCallConfiguration
movq 216(%rsp), %rsi
movl 224(%rsp), %edx
movq 200(%rsp), %rcx
movl 208(%rsp), %r8d
leaq 240(%rsp), %r9
movl $_Z7computefiPfffffffffffffff, %edi
pushq 184(%rsp)
.cfi_adjust_cfa_offset 8
pushq 200(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $376, %rsp # imm = 0x178
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefiPfffffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefiPfffffffffffffff,@object # @_Z7computefiPfffffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefiPfffffffffffffff
.p2align 3, 0x0
_Z7computefiPfffffffffffffff:
.quad _Z22__device_stub__computefiPfffffffffffffff
.size _Z7computefiPfffffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefiPfffffffffffffff"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefiPfffffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefiPfffffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0002920e_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z42__device_stub__Z7computefiPffffffffffffffffiPfffffffffffffff
.type _Z42__device_stub__Z7computefiPffffffffffffffffiPfffffffffffffff, @function
_Z42__device_stub__Z7computefiPffffffffffffffffiPfffffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movq %rsi, 32(%rsp)
movss %xmm1, 28(%rsp)
movss %xmm2, 24(%rsp)
movss %xmm3, 20(%rsp)
movss %xmm4, 16(%rsp)
movss %xmm5, 12(%rsp)
movss %xmm6, 8(%rsp)
movss %xmm7, 4(%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 4(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
leaq 288(%rsp), %rax
movq %rax, 208(%rsp)
leaq 296(%rsp), %rax
movq %rax, 216(%rsp)
leaq 304(%rsp), %rax
movq %rax, 224(%rsp)
leaq 312(%rsp), %rax
movq %rax, 232(%rsp)
leaq 320(%rsp), %rax
movq %rax, 240(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 280
pushq 56(%rsp)
.cfi_def_cfa_offset 288
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7computefiPfffffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z42__device_stub__Z7computefiPffffffffffffffffiPfffffffffffffff, .-_Z42__device_stub__Z7computefiPffffffffffffffffiPfffffffffffffff
.globl _Z7computefiPfffffffffffffff
.type _Z7computefiPfffffffffffffff, @function
_Z7computefiPfffffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movss 128(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 120(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 112(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 104(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 96(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 88(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 80(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z42__device_stub__Z7computefiPffffffffffffffffiPfffffffffffffff
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefiPfffffffffffffff, .-_Z7computefiPfffffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $160, %rsp
.cfi_def_cfa_offset 192
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r12
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movl $1, 148(%rsp)
movl $1, 152(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 148(%rsp), %rdx
movl $1, %ecx
movq 136(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $160, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 120(%rsp), %xmm0
subq $64, %rsp
.cfi_def_cfa_offset 256
pxor %xmm1, %xmm1
cvtsd2ss 72(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 80(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 88(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 96(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 104(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 112(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 120(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 128(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 136(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 144(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 152(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 160(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 168(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 176(%rsp), %xmm1
movq %r12, %rsi
movl %ebp, %edi
call _Z42__device_stub__Z7computefiPffffffffffffffffiPfffffffffffffff
addq $64, %rsp
.cfi_def_cfa_offset 192
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7computefiPfffffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefiPfffffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "test.hip"
.globl _Z22__device_stub__computefiPfffffffffffffff # -- Begin function _Z22__device_stub__computefiPfffffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefiPfffffffffffffff,@function
_Z22__device_stub__computefiPfffffffffffffff: # @_Z22__device_stub__computefiPfffffffffffffff
.cfi_startproc
# %bb.0:
subq $232, %rsp
.cfi_def_cfa_offset 240
movss %xmm0, 36(%rsp)
movl %edi, 32(%rsp)
movq %rsi, 88(%rsp)
movss %xmm1, 28(%rsp)
movss %xmm2, 24(%rsp)
movss %xmm3, 20(%rsp)
movss %xmm4, 16(%rsp)
movss %xmm5, 12(%rsp)
movss %xmm6, 8(%rsp)
movss %xmm7, 4(%rsp)
leaq 36(%rsp), %rax
movq %rax, 96(%rsp)
leaq 32(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 28(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 4(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
leaq 272(%rsp), %rax
movq %rax, 208(%rsp)
leaq 280(%rsp), %rax
movq %rax, 216(%rsp)
leaq 288(%rsp), %rax
movq %rax, 224(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computefiPfffffffffffffff, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $248, %rsp
.cfi_adjust_cfa_offset -248
retq
.Lfunc_end0:
.size _Z22__device_stub__computefiPfffffffffffffff, .Lfunc_end0-_Z22__device_stub__computefiPfffffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $376, %rsp # imm = 0x178
.cfi_def_cfa_offset 416
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r15
movq 8(%rsi), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movq 16(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r15), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r14
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq $10, %r12
jne .LBB2_1
# %bb.2: # %_Z11initPointerf.exit
movq 32(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, (%rsp) # 8-byte Spill
movq 40(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 48(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 56(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 152(%rsp) # 8-byte Spill
movq 64(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq 72(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 136(%rsp) # 8-byte Spill
movq 80(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 128(%rsp) # 8-byte Spill
movq 88(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq 96(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 112(%rsp) # 8-byte Spill
movq 104(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq 112(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 96(%rsp) # 8-byte Spill
movq 120(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 88(%rsp) # 8-byte Spill
movq 128(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 80(%rsp) # 8-byte Spill
movq 136(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 72(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movsd 72(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movsd 80(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
cvtsd2ss %xmm1, %xmm1
movsd 88(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
cvtsd2ss %xmm2, %xmm2
movsd 96(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
cvtsd2ss %xmm3, %xmm3
movsd 104(%rsp), %xmm4 # 8-byte Reload
# xmm4 = mem[0],zero
cvtsd2ss %xmm4, %xmm4
movsd 112(%rsp), %xmm5 # 8-byte Reload
# xmm5 = mem[0],zero
cvtsd2ss %xmm5, %xmm5
movsd 120(%rsp), %xmm6 # 8-byte Reload
# xmm6 = mem[0],zero
cvtsd2ss %xmm6, %xmm6
movsd 128(%rsp), %xmm7 # 8-byte Reload
# xmm7 = mem[0],zero
cvtsd2ss %xmm7, %xmm7
movsd 136(%rsp), %xmm8 # 8-byte Reload
# xmm8 = mem[0],zero
cvtsd2ss %xmm8, %xmm8
movsd 144(%rsp), %xmm9 # 8-byte Reload
# xmm9 = mem[0],zero
cvtsd2ss %xmm9, %xmm9
movsd 152(%rsp), %xmm10 # 8-byte Reload
# xmm10 = mem[0],zero
cvtsd2ss %xmm10, %xmm10
movsd 160(%rsp), %xmm11 # 8-byte Reload
# xmm11 = mem[0],zero
cvtsd2ss %xmm11, %xmm11
movsd 168(%rsp), %xmm12 # 8-byte Reload
# xmm12 = mem[0],zero
cvtsd2ss %xmm12, %xmm12
movsd (%rsp), %xmm13 # 8-byte Reload
# xmm13 = mem[0],zero
cvtsd2ss %xmm13, %xmm13
movsd 176(%rsp), %xmm14 # 8-byte Reload
# xmm14 = mem[0],zero
cvtsd2ss %xmm14, %xmm14
movss %xmm14, 68(%rsp)
movl %ebx, 64(%rsp)
movq %r14, 232(%rsp)
movss %xmm13, 60(%rsp)
movss %xmm12, 56(%rsp)
movss %xmm11, 52(%rsp)
movss %xmm10, 48(%rsp)
movss %xmm9, 44(%rsp)
movss %xmm8, 40(%rsp)
movss %xmm7, 36(%rsp)
movss %xmm6, 32(%rsp)
movss %xmm5, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm3, 20(%rsp)
movss %xmm2, 16(%rsp)
movss %xmm1, 12(%rsp)
movss %xmm0, 8(%rsp)
leaq 68(%rsp), %rax
movq %rax, 240(%rsp)
leaq 64(%rsp), %rax
movq %rax, 248(%rsp)
leaq 232(%rsp), %rax
movq %rax, 256(%rsp)
leaq 60(%rsp), %rax
movq %rax, 264(%rsp)
leaq 56(%rsp), %rax
movq %rax, 272(%rsp)
leaq 52(%rsp), %rax
movq %rax, 280(%rsp)
leaq 48(%rsp), %rax
movq %rax, 288(%rsp)
leaq 44(%rsp), %rax
movq %rax, 296(%rsp)
leaq 40(%rsp), %rax
movq %rax, 304(%rsp)
leaq 36(%rsp), %rax
movq %rax, 312(%rsp)
leaq 32(%rsp), %rax
movq %rax, 320(%rsp)
leaq 28(%rsp), %rax
movq %rax, 328(%rsp)
leaq 24(%rsp), %rax
movq %rax, 336(%rsp)
leaq 20(%rsp), %rax
movq %rax, 344(%rsp)
leaq 16(%rsp), %rax
movq %rax, 352(%rsp)
leaq 12(%rsp), %rax
movq %rax, 360(%rsp)
leaq 8(%rsp), %rax
movq %rax, 368(%rsp)
leaq 216(%rsp), %rdi
leaq 200(%rsp), %rsi
leaq 192(%rsp), %rdx
leaq 184(%rsp), %rcx
callq __hipPopCallConfiguration
movq 216(%rsp), %rsi
movl 224(%rsp), %edx
movq 200(%rsp), %rcx
movl 208(%rsp), %r8d
leaq 240(%rsp), %r9
movl $_Z7computefiPfffffffffffffff, %edi
pushq 184(%rsp)
.cfi_adjust_cfa_offset 8
pushq 200(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $376, %rsp # imm = 0x178
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefiPfffffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefiPfffffffffffffff,@object # @_Z7computefiPfffffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefiPfffffffffffffff
.p2align 3, 0x0
_Z7computefiPfffffffffffffff:
.quad _Z22__device_stub__computefiPfffffffffffffff
.size _Z7computefiPfffffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefiPfffffffffffffff"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefiPfffffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefiPfffffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
/* CUDA FFT Library */
/* written by Viktor K. Decyk, UCLA */
#include <stdlib.h>
#include <stdio.h>
#include "cuda.h"
#include <cufft.h>
extern int nblock_size;
extern int maxgsx;
static cudaError_t crc;
static cufftResult cfrc;
static cufftHandle planrx, planxr, planrxn, planxrn;
static cufftHandle plany, planyn;
__global__ void gpuctpose4(float2 f[], float2 g[], int nx, int ny,
int nxv, int nyv);
__global__ void gpuctpose4n(float2 fn[], float2 gn[], int nx, int ny,
int ndim, int nxv, int nyv);
/*--------------------------------------------------------------------*/
__global__ void gpusctpose4(float2 f[], float2 g[], float ani, int nx,
int ny, int nxv, int nyv) {
/* scaled complex transpose using blocking algorithm with gaps */
/* local data */
int j, k, js, ks, joff, koff, mx, mxv;
float2 a;
/* The size of the shared memory array is as follows: */
/* float2 shm2[(mx + 1)*mx]; */
extern __shared__ float2 shm2[];
mx = blockDim.x;
mxv = mx + 1;
joff = mx*blockIdx.x;
koff = mx*blockIdx.y;
js = threadIdx.x;
ks = threadIdx.y;
/* copy into block */
j = js + joff;
k = ks + koff;
if ((j < nx) && (k < ny)) {
shm2[js+mxv*ks] = f[j+nxv*k];
}
__syncthreads();
/* copy out from block with scaling */
j = ks + joff;
k = js + koff;
if ((j < nx) && (k < ny)) {
a = shm2[ks+mxv*js];
a.x = ani*a.x;
a.y = ani*a.y;
g[k+nyv*j] = a;
}
return;
}
/*--------------------------------------------------------------------*/
__global__ void gpusctpose4n(float2 fn[], float2 gn[], float ani,
int nx, int ny, int ndim, int nxv,
int nyv) {
/* scaled complex vector transpose using blocking algorithm with gaps */
/* ndim = vector dimension */
/* local data */
int i, j, k, js, ks, joff, koff, mx, mxv, nmxv, nnxv, nnyv, jj, kk;
float2 a;
/* The size of the shared memory array is as follows: */
/* float2 shmn2[ndim*(mx + 1)*mx]; */
extern __shared__ float2 shmn2[];
mx = blockDim.x;
mxv = mx + 1;
joff = mx*blockIdx.x;
koff = mx*blockIdx.y;
js = threadIdx.x;
ks = threadIdx.y;
nmxv = ndim*mxv;
nnxv = ndim*nxv;
nnyv = ndim*nyv;
/* copy into block */
j = js + joff;
k = ks + koff;
if ((j < nx) && (k < ny)) {
jj = j + nnxv*k;
kk = js + nmxv*ks;
for (i = 0; i < ndim; i++) {
shmn2[kk+mxv*i] = fn[jj+nxv*i];
}
}
__syncthreads();
/* copy out from block with scaling */
j = ks + joff;
k = js + koff;
if ((j < nx) && (k < ny)) {
kk = k + nnyv*j;
jj = ks + nmxv*js;
for (i = 0; i < ndim; i++) {
a = shmn2[jj+mxv*i];
a.x = ani*a.x;
a.y = ani*a.y;
gn[kk+nyv*i] = a;
}
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcuinit(int nx, int ny, int ndim) {
cfrc = cufftPlan1d(&planrx,nx,CUFFT_R2C,ny);
if (cfrc) {
printf("cufftPlan1d planrx error=%d\n",cfrc);
exit(1);
}
cfrc = cufftPlan1d(&planxr,nx,CUFFT_C2R,ny);
if (cfrc) {
printf("cufftPlan1d planxr error=%d\n",cfrc);
exit(1);
}
cfrc = cufftPlan1d(&planrxn,nx,CUFFT_R2C,ndim*ny);
if (cfrc) {
printf("cufftPlan1d planrxn error=%d\n",cfrc);
exit(1);
}
cfrc = cufftPlan1d(&planxrn,nx,CUFFT_C2R,ndim*ny);
if (cfrc) {
printf("cufftPlan1d planxrn error=%d\n",cfrc);
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2cuinit(int nx, int ny, int ndim) {
int nxh1;
nxh1 = nx/2 + 1;
cfrc = cufftPlan1d(&plany,ny,CUFFT_C2C,nxh1);
if (cfrc) {
printf("cufftPlan1d plany error=%d\n",cfrc);
exit(1);
}
cfrc = cufftPlan1d(&planyn,ny,CUFFT_C2C,ndim*nxh1);
if (cfrc) {
printf("cufftPlan1d planyn error=%d\n",cfrc);
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcudel() {
cfrc = cufftDestroy(planrx);
if (cfrc) {
printf("cufftDestroy planrx error=%d\n",cfrc);
exit(1);
}
cfrc = cufftDestroy(planxr);
if (cfrc) {
printf("cufftDestroy planxr error=%d\n",cfrc);
exit(1);
}
cfrc = cufftDestroy(planrxn);
if (cfrc) {
printf("cufftDestroy planrxn error=%d\n",cfrc);
exit(1);
}
cfrc = cufftDestroy(planxrn);
if (cfrc) {
printf("cufftDestroy planxrn error=%d\n",cfrc);
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2cudel() {
cfrc = cufftDestroy(plany);
if (cfrc) {
printf("cufftDestroy plany error=%d\n",cfrc);
exit(1);
}
cfrc = cufftDestroy(planyn);
if (cfrc) {
printf("cufftDestroy planyn error=%d\n",cfrc);
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcu(float2 f[], float2 g[], int isign,
int indx, int indy, int nxh1d, int nyd) {
/* wrapper function for real to complex fft, without packed data */
/* uses 1D real to complex and complex to complex NVIDIA FFTs */
/* nxh1d must be = nx/2+1 */
/* local data */
int nx, nxh1, ny, ns;
int mx = 16;
float ani;
dim3 dimBlock(nblock_size);
dim3 dimBlockt(mx,mx);
/* calculate range of indices */
nx = 1L<<indx;
nxh1 = nx/2 + 1;
ny = 1L<<indy;
dim3 dimGridtx((nxh1-1)/mx+1,(ny-1)/mx+1);
dim3 dimGridty((ny-1)/mx+1,(nxh1-1)/mx+1);
ns = (mx+1)*mx*sizeof(float2);
/* inverse fourier transform */
if (isign < 0) {
/* perform x fft */
cfrc = cufftExecR2C(planrx,(cufftReal *)f,(cufftComplex *)f);
/* cudaThreadSynchronize(); */
if (cfrc) {
printf("cufftExecR2C(-1) planrx error=%d\n",cfrc);
exit(1);
}
/* transpose f to g and normalize */
ani = 1.0f/(((float) nx)*((float) ny));
crc = cudaGetLastError();
gpusctpose4<<<dimGridtx,dimBlockt,ns>>>(f,g,ani,nxh1,ny,nxh1d,
nyd);
/* cudaThreadSynchronize(); */
crc = cudaGetLastError();
if (crc) {
printf("gpusctpose4 error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
/* perform y fft */
cfrc = cufftExecC2C(plany,(cufftComplex *)g,(cufftComplex *)g,
CUFFT_FORWARD);
cudaThreadSynchronize();
if (cfrc) {
printf("cufftExecC2C(-1) plany error=%d\n",cfrc);
exit(1);
}
}
/* forward fourier transform */
else if (isign > 0) {
/* perform y fft */
cfrc = cufftExecC2C(plany,(cufftComplex *)g,(cufftComplex *)g,
CUFFT_INVERSE);
/* cudaThreadSynchronize(); */
if (cfrc) {
printf("cufftExecC2C(1) plany error=%d\n",cfrc);
exit(1);
}
/* transpose g to f */
crc = cudaGetLastError();
gpuctpose4<<<dimGridty,dimBlockt,ns>>>(g,f,ny,nxh1,nyd,nxh1d);
/* cudaThreadSynchronize(); */
crc = cudaGetLastError();
if (crc) {
printf("gpuctpose4 error=%d:%s\n",crc,cudaGetErrorString(crc));
exit(1);
}
/* perform x fft */
cfrc = cufftExecC2R(planxr,(cufftComplex *)f,(cufftReal *)f);
cudaThreadSynchronize();
if (cfrc) {
printf("cufftExecC2R(1) planxr error=%d\n",cfrc);
exit(1);
}
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcun(float2 fn[], float2 gn[], int isign,
int indx, int indy, int ndim, int nxh1d,
int nyd) {
/* wrapper function for real to complex fft, without packed data */
/* for vector data */
/* uses 1D real to complex and complex to complex NVIDIA FFTs */
/* ndim = vector dimension */
/* nxh1d must be = nx/2+1 */
/* local data */
int nx, nxh1, ny, ns;
int mx = 16;
float ani;
dim3 dimBlock(nblock_size);
dim3 dimBlockt(mx,mx);
/* calculate range of indices */
nx = 1L<<indx;
nxh1 = nx/2 + 1;
ny = 1L<<indy;
dim3 dimGridtx((nxh1-1)/mx+1,(ny-1)/mx+1);
dim3 dimGridty((ny-1)/mx+1,(nxh1-1)/mx+1);
ns = ndim*(mx+1)*mx*sizeof(float2);
/* inverse fourier transform */
if (isign < 0) {
/* perform x fft */
cfrc = cufftExecR2C(planrxn,(cufftReal *)fn,(cufftComplex *)fn);
/* cudaThreadSynchronize(); */
if (cfrc) {
printf("cufftExecR2C(-1) planrxn error=%d\n",cfrc);
exit(1);
}
/* transpose f to g and normalize */
ani = 1.0f/(((float) nx)*((float) ny));
crc = cudaGetLastError();
gpusctpose4n<<<dimGridtx,dimBlockt,ns>>>(fn,gn,ani,nxh1,ny,ndim,
nxh1d,nyd);
/* cudaThreadSynchronize(); */
crc = cudaGetLastError();
if (crc) {
printf("gpusctpose4n error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
/* perform y fft */
cfrc = cufftExecC2C(planyn,(cufftComplex *)gn,(cufftComplex *)gn,
CUFFT_FORWARD);
cudaThreadSynchronize();
if (cfrc) {
printf("cufftExecC2C(-1) planyn error=%d\n",cfrc);
exit(1);
}
}
/* forward fourier transform */
else if (isign > 0) {
/* perform y fft */
cfrc = cufftExecC2C(planyn,(cufftComplex *)gn,(cufftComplex *)gn,
CUFFT_INVERSE);
/* cudaThreadSynchronize(); */
if (cfrc) {
printf("cufftExecC2C(1) planyn error=%d\n",cfrc);
exit(1);
}
/* transpose g to f */
crc = cudaGetLastError();
gpuctpose4n<<<dimGridty,dimBlockt,ns>>>(gn,fn,ny,nxh1,ndim,nyd,
nxh1d);
/* cudaThreadSynchronize(); */
crc = cudaGetLastError();
if (crc) {
printf("gpuctpose4n error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
/* perform x fft */
cfrc = cufftExecC2R(planxrn,(cufftComplex *)fn,(cufftReal *)fn);
cudaThreadSynchronize();
if (cfrc) {
printf("cufftExecC2R(1) planxrn error=%d\n",cfrc);
exit(1);
}
}
return;
}
/* Interfaces to Fortran */
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcuinit_(int *nx, int *ny, int *ndim) {
gpufft2rrcuinit(*nx,*ny,*ndim);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2cuinit_(int *nx, int *ny, int *ndim) {
gpufft2cuinit(*nx,*ny,*ndim);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcudel_() {
gpufft2rrcudel();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2cudel_() {
gpufft2cudel();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcu_(unsigned long *gp_f, unsigned long *gp_g,
int *isign, int *indx, int *indy,
int *nxh1d, int *nyd) {
float2 *f, *g;
f = (float2 *)*gp_f;
g = (float2 *)*gp_g;
gpufft2rrcu(f,g,*isign,*indx,*indy,*nxh1d,*nyd);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcun_(unsigned long *gp_fn,
unsigned long *gp_gn, int *isign,
int *indx, int *indy, int *ndim,
int *nxh1d, int *nyd) {
float2 *fn, *gn;
fn = (float2 *)*gp_fn;
gn = (float2 *)*gp_gn;
gpufft2rrcun(fn,gn,*isign,*indx,*indy,*ndim,*nxh1d,*nyd);
return;
}
|
.file "tmpxft_00004677_00000000-6_gpufft2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cufftPlan1d planrx error=%d\n"
.LC1:
.string "cufftPlan1d planxr error=%d\n"
.LC2:
.string "cufftPlan1d planrxn error=%d\n"
.LC3:
.string "cufftPlan1d planxrn error=%d\n"
.text
.globl gpufft2rrcuinit
.type gpufft2rrcuinit, @function
gpufft2rrcuinit:
.LFB2080:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %edi, %ebp
movl %esi, %ebx
movl %edx, %r12d
movl %esi, %ecx
movl $42, %edx
movl %edi, %esi
leaq _ZL6planrx(%rip), %rdi
call cufftPlan1d@PLT
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .L9
movl %ebx, %ecx
movl $44, %edx
movl %ebp, %esi
leaq _ZL6planxr(%rip), %rdi
call cufftPlan1d@PLT
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .L10
imull %r12d, %ebx
movl %ebx, %ecx
movl $42, %edx
movl %ebp, %esi
leaq _ZL7planrxn(%rip), %rdi
call cufftPlan1d@PLT
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .L11
movl %ebx, %ecx
movl $44, %edx
movl %ebp, %esi
leaq _ZL7planxrn(%rip), %rdi
call cufftPlan1d@PLT
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .L12
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
movl %eax, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L10:
movl %eax, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L11:
movl %eax, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L12:
movl %eax, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2080:
.size gpufft2rrcuinit, .-gpufft2rrcuinit
.section .rodata.str1.1
.LC4:
.string "cufftPlan1d plany error=%d\n"
.LC5:
.string "cufftPlan1d planyn error=%d\n"
.text
.globl gpufft2cuinit
.type gpufft2cuinit, @function
gpufft2cuinit:
.LFB2081:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %esi, %ebp
movl %edx, %r12d
movl %edi, %eax
shrl $31, %eax
leal (%rax,%rdi), %ebx
sarl %ebx
addl $1, %ebx
movl %ebx, %ecx
movl $41, %edx
leaq _ZL5plany(%rip), %rdi
call cufftPlan1d@PLT
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .L17
movl %ebx, %ecx
imull %r12d, %ecx
movl $41, %edx
movl %ebp, %esi
leaq _ZL6planyn(%rip), %rdi
call cufftPlan1d@PLT
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .L18
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl %eax, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L18:
movl %eax, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2081:
.size gpufft2cuinit, .-gpufft2cuinit
.section .rodata.str1.1
.LC6:
.string "cufftDestroy planrx error=%d\n"
.LC7:
.string "cufftDestroy planxr error=%d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "cufftDestroy planrxn error=%d\n"
.align 8
.LC9:
.string "cufftDestroy planxrn error=%d\n"
.text
.globl gpufft2rrcudel
.type gpufft2rrcudel, @function
gpufft2rrcudel:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl _ZL6planrx(%rip), %edi
call cufftDestroy@PLT
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .L25
movl _ZL6planxr(%rip), %edi
call cufftDestroy@PLT
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .L26
movl _ZL7planrxn(%rip), %edi
call cufftDestroy@PLT
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .L27
movl _ZL7planxrn(%rip), %edi
call cufftDestroy@PLT
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .L28
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl %eax, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L26:
movl %eax, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L27:
movl %eax, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L28:
movl %eax, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2082:
.size gpufft2rrcudel, .-gpufft2rrcudel
.section .rodata.str1.1
.LC10:
.string "cufftDestroy plany error=%d\n"
.LC11:
.string "cufftDestroy planyn error=%d\n"
.text
.globl gpufft2cudel
.type gpufft2cudel, @function
gpufft2cudel:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl _ZL5plany(%rip), %edi
call cufftDestroy@PLT
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .L33
movl _ZL6planyn(%rip), %edi
call cufftDestroy@PLT
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .L34
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movl %eax, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
movl %eax, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2083:
.size gpufft2cudel, .-gpufft2cudel
.globl gpufft2rrcuinit_
.type gpufft2rrcuinit_, @function
gpufft2rrcuinit_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl (%rdx), %edx
movl (%rsi), %esi
movl (%rdi), %edi
call gpufft2rrcuinit
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size gpufft2rrcuinit_, .-gpufft2rrcuinit_
.globl gpufft2cuinit_
.type gpufft2cuinit_, @function
gpufft2cuinit_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl (%rdx), %edx
movl (%rsi), %esi
movl (%rdi), %edi
call gpufft2cuinit
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size gpufft2cuinit_, .-gpufft2cuinit_
.globl gpufft2rrcudel_
.type gpufft2rrcudel_, @function
gpufft2rrcudel_:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call gpufft2rrcudel
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size gpufft2rrcudel_, .-gpufft2rrcudel_
.globl gpufft2cudel_
.type gpufft2cudel_, @function
gpufft2cudel_:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call gpufft2cudel
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size gpufft2cudel_, .-gpufft2cudel_
.globl _Z45__device_stub__Z11gpusctpose4P6float2S0_fiiiiP6float2S0_fiiii
.type _Z45__device_stub__Z11gpusctpose4P6float2S0_fiiiiP6float2S0_fiiii, @function
_Z45__device_stub__Z11gpusctpose4P6float2S0_fiiiiP6float2S0_fiiii:
.LFB2116:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movss %xmm0, 28(%rsp)
movl %edx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11gpusctpose4P6float2S0_fiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2116:
.size _Z45__device_stub__Z11gpusctpose4P6float2S0_fiiiiP6float2S0_fiiii, .-_Z45__device_stub__Z11gpusctpose4P6float2S0_fiiiiP6float2S0_fiiii
.globl _Z11gpusctpose4P6float2S0_fiiii
.type _Z11gpusctpose4P6float2S0_fiiii, @function
_Z11gpusctpose4P6float2S0_fiiii:
.LFB2117:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z11gpusctpose4P6float2S0_fiiiiP6float2S0_fiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2117:
.size _Z11gpusctpose4P6float2S0_fiiii, .-_Z11gpusctpose4P6float2S0_fiiii
.section .rodata.str1.8
.align 8
.LC12:
.string "cufftExecR2C(-1) planrx error=%d\n"
.section .rodata.str1.1
.LC14:
.string "gpusctpose4 error=%d:%s\n"
.section .rodata.str1.8
.align 8
.LC15:
.string "cufftExecC2C(-1) plany error=%d\n"
.align 8
.LC16:
.string "cufftExecC2C(1) plany error=%d\n"
.section .rodata.str1.1
.LC17:
.string "gpuctpose4 error=%d:%s\n"
.section .rodata.str1.8
.align 8
.LC18:
.string "cufftExecC2R(1) planxr error=%d\n"
.text
.globl gpufft2rrcu
.type gpufft2rrcu, @function
gpufft2rrcu:
.LFB2084:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r13
movq %rsi, %r14
movl %edx, %esi
movl %r9d, %r15d
movl $16, 28(%rsp)
movl $16, 32(%rsp)
movl $1, 36(%rsp)
movl $1, %ebx
movq %rbx, %r12
salq %cl, %r12
movl %r12d, %ebp
shrl $31, %ebp
addl %r12d, %ebp
sarl %ebp
addl $1, %ebp
movl %r8d, %ecx
salq %cl, %rbx
movl %ebx, 12(%rsp)
leal 14(%rbx), %edx
movl %ebx, %eax
subl $1, %eax
cmovns %eax, %edx
sarl $4, %edx
addl $1, %edx
leal 31(%r12), %eax
testl %r12d, %r12d
cmovns %r12d, %eax
sarl $5, %eax
addl $1, %eax
movl %eax, 40(%rsp)
movl %edx, 44(%rsp)
movl $1, 48(%rsp)
movl %edx, 52(%rsp)
movl %eax, 56(%rsp)
movl $1, 60(%rsp)
testl %esi, %esi
js .L61
jg .L62
.L51:
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
movq %rdi, %rdx
movq %rdi, %rsi
movl _ZL6planrx(%rip), %edi
call cufftExecR2C@PLT
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .L63
call cudaGetLastError@PLT
movl %eax, _ZL3crc(%rip)
movl 36(%rsp), %ecx
movl $0, %r9d
movl $2176, %r8d
movq 28(%rsp), %rdx
movq 40(%rsp), %rdi
movl 48(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L64
.L54:
call cudaGetLastError@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L65
movl $-1, %ecx
movq %r14, %rdx
movq %r14, %rsi
movl _ZL5plany(%rip), %edi
call cufftExecC2C@PLT
movl %eax, _ZL4cfrc(%rip)
call cudaThreadSynchronize@PLT
movl _ZL4cfrc(%rip), %edx
testl %edx, %edx
je .L51
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L63:
movl %eax, %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L64:
pxor %xmm1, %xmm1
cvtsi2ssl %r12d, %xmm1
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
mulss %xmm0, %xmm1
movss .LC13(%rip), %xmm0
divss %xmm1, %xmm0
movl 128(%rsp), %r9d
movl %r15d, %r8d
movl 12(%rsp), %ecx
movl %ebp, %edx
movq %r14, %rsi
movq %r13, %rdi
call _Z45__device_stub__Z11gpusctpose4P6float2S0_fiiiiP6float2S0_fiiii
jmp .L54
.L65:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L62:
movl $1, %ecx
movq %r14, %rdx
movq %r14, %rsi
movl _ZL5plany(%rip), %edi
call cufftExecC2C@PLT
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .L66
call cudaGetLastError@PLT
movl %eax, _ZL3crc(%rip)
movl 36(%rsp), %ecx
movl $0, %r9d
movl $2176, %r8d
movq 28(%rsp), %rdx
movq 52(%rsp), %rdi
movl 60(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L67
.L58:
call cudaGetLastError@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L68
movq %r13, %rdx
movq %r13, %rsi
movl _ZL6planxr(%rip), %edi
call cufftExecC2R@PLT
movl %eax, _ZL4cfrc(%rip)
call cudaThreadSynchronize@PLT
movl _ZL4cfrc(%rip), %edx
testl %edx, %edx
je .L51
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L66:
movl %eax, %edx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L67:
movl %r15d, %r9d
movl 128(%rsp), %r8d
movl %ebp, %ecx
movl 12(%rsp), %edx
movq %r13, %rsi
movq %r14, %rdi
call _Z10gpuctpose4P6float2S0_iiii@PLT
jmp .L58
.L68:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2084:
.size gpufft2rrcu, .-gpufft2rrcu
.globl gpufft2rrcu_
.type gpufft2rrcu_, @function
gpufft2rrcu_:
.LFB2090:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl (%r9), %r9d
movl (%r8), %r8d
movl (%rcx), %ecx
movl (%rdx), %edx
movq (%rsi), %rsi
movq (%rdi), %rdi
movq 24(%rsp), %rax
movl (%rax), %eax
pushq %rax
.cfi_def_cfa_offset 32
call gpufft2rrcu
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size gpufft2rrcu_, .-gpufft2rrcu_
.globl _Z47__device_stub__Z12gpusctpose4nP6float2S0_fiiiiiP6float2S0_fiiiii
.type _Z47__device_stub__Z12gpusctpose4nP6float2S0_fiiiiiP6float2S0_fiiiii, @function
_Z47__device_stub__Z12gpusctpose4nP6float2S0_fiiiiiP6float2S0_fiiiii:
.LFB2118:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movss %xmm0, 28(%rsp)
movl %edx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 208(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L75
.L71:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L76
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L75:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12gpusctpose4nP6float2S0_fiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L71
.L76:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2118:
.size _Z47__device_stub__Z12gpusctpose4nP6float2S0_fiiiiiP6float2S0_fiiiii, .-_Z47__device_stub__Z12gpusctpose4nP6float2S0_fiiiiiP6float2S0_fiiiii
.globl _Z12gpusctpose4nP6float2S0_fiiiii
.type _Z12gpusctpose4nP6float2S0_fiiiii, @function
_Z12gpusctpose4nP6float2S0_fiiiii:
.LFB2119:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z47__device_stub__Z12gpusctpose4nP6float2S0_fiiiiiP6float2S0_fiiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2119:
.size _Z12gpusctpose4nP6float2S0_fiiiii, .-_Z12gpusctpose4nP6float2S0_fiiiii
.section .rodata.str1.8
.align 8
.LC19:
.string "cufftExecR2C(-1) planrxn error=%d\n"
.section .rodata.str1.1
.LC20:
.string "gpusctpose4n error=%d:%s\n"
.section .rodata.str1.8
.align 8
.LC21:
.string "cufftExecC2C(-1) planyn error=%d\n"
.align 8
.LC22:
.string "cufftExecC2C(1) planyn error=%d\n"
.section .rodata.str1.1
.LC23:
.string "gpuctpose4n error=%d:%s\n"
.section .rodata.str1.8
.align 8
.LC24:
.string "cufftExecC2R(1) planxrn error=%d\n"
.text
.globl gpufft2rrcun
.type gpufft2rrcun, @function
gpufft2rrcun:
.LFB2085:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r12
movq %rsi, %r13
movl %edx, %esi
movl %r9d, %r14d
movl $16, 28(%rsp)
movl $16, 32(%rsp)
movl $1, 36(%rsp)
movl $1, %ebx
movq %rbx, %rbp
salq %cl, %rbp
movl %ebp, %eax
shrl $31, %eax
addl %ebp, %eax
sarl %eax
addl $1, %eax
movl %eax, 8(%rsp)
movl %r8d, %ecx
salq %cl, %rbx
movl %ebx, 12(%rsp)
leal 14(%rbx), %edx
movl %ebx, %eax
subl $1, %eax
cmovns %eax, %edx
sarl $4, %edx
addl $1, %edx
leal 31(%rbp), %eax
testl %ebp, %ebp
cmovns %ebp, %eax
sarl $5, %eax
addl $1, %eax
movl %eax, 40(%rsp)
movl %edx, 44(%rsp)
movl $1, 48(%rsp)
movl %edx, 52(%rsp)
movl %eax, 56(%rsp)
movl $1, 60(%rsp)
imull $272, %r9d, %r15d
sall $3, %r15d
testl %esi, %esi
js .L89
jg .L90
.L79:
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L89:
.cfi_restore_state
movq %rdi, %rdx
movq %rdi, %rsi
movl _ZL7planrxn(%rip), %edi
call cufftExecR2C@PLT
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .L91
call cudaGetLastError@PLT
movl %eax, _ZL3crc(%rip)
movl 36(%rsp), %ecx
movl $0, %r9d
movslq %r15d, %r8
movq 28(%rsp), %rdx
movq 40(%rsp), %rdi
movl 48(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L92
.L82:
call cudaGetLastError@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L93
movl $-1, %ecx
movq %r13, %rdx
movq %r13, %rsi
movl _ZL6planyn(%rip), %edi
call cufftExecC2C@PLT
movl %eax, _ZL4cfrc(%rip)
call cudaThreadSynchronize@PLT
movl _ZL4cfrc(%rip), %edx
testl %edx, %edx
je .L79
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L91:
movl %eax, %edx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L92:
pxor %xmm1, %xmm1
cvtsi2ssl %ebp, %xmm1
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
mulss %xmm0, %xmm1
movss .LC13(%rip), %xmm0
divss %xmm1, %xmm0
subq $8, %rsp
.cfi_def_cfa_offset 136
movl 144(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 144
movl 144(%rsp), %r9d
movl %r14d, %r8d
movl 28(%rsp), %ecx
movl 24(%rsp), %edx
movq %r13, %rsi
movq %r12, %rdi
call _Z47__device_stub__Z12gpusctpose4nP6float2S0_fiiiiiP6float2S0_fiiiii
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L82
.L93:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L90:
movl $1, %ecx
movq %r13, %rdx
movq %r13, %rsi
movl _ZL6planyn(%rip), %edi
call cufftExecC2C@PLT
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .L94
call cudaGetLastError@PLT
movl %eax, _ZL3crc(%rip)
movl 36(%rsp), %ecx
movl $0, %r9d
movslq %r15d, %r8
movq 28(%rsp), %rdx
movq 52(%rsp), %rdi
movl 60(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L95
.L86:
call cudaGetLastError@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L96
movq %r12, %rdx
movq %r12, %rsi
movl _ZL7planxrn(%rip), %edi
call cufftExecC2R@PLT
movl %eax, _ZL4cfrc(%rip)
call cudaThreadSynchronize@PLT
movl _ZL4cfrc(%rip), %edx
testl %edx, %edx
je .L79
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L94:
movl %eax, %edx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L95:
subq $8, %rsp
.cfi_def_cfa_offset 136
movl 136(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 144
movl 152(%rsp), %r9d
movl %r14d, %r8d
movl 24(%rsp), %ecx
movl 28(%rsp), %edx
movq %r12, %rsi
movq %r13, %rdi
call _Z11gpuctpose4nP6float2S0_iiiii@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L86
.L96:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2085:
.size gpufft2rrcun, .-gpufft2rrcun
.globl gpufft2rrcun_
.type gpufft2rrcun_, @function
gpufft2rrcun_:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl (%r9), %r9d
movl (%r8), %r8d
movl (%rcx), %ecx
movl (%rdx), %edx
movq (%rsi), %rsi
movq (%rdi), %rdi
movq 24(%rsp), %rax
movl (%rax), %eax
pushq %rax
.cfi_def_cfa_offset 24
movq 24(%rsp), %rax
movl (%rax), %eax
pushq %rax
.cfi_def_cfa_offset 32
call gpufft2rrcun
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size gpufft2rrcun_, .-gpufft2rrcun_
.section .rodata.str1.8
.align 8
.LC25:
.string "_Z12gpusctpose4nP6float2S0_fiiiii"
.align 8
.LC26:
.string "_Z11gpusctpose4P6float2S0_fiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2121:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC25(%rip), %rdx
movq %rdx, %rcx
leaq _Z12gpusctpose4nP6float2S0_fiiiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC26(%rip), %rdx
movq %rdx, %rcx
leaq _Z11gpusctpose4P6float2S0_fiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2121:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL6planyn
.comm _ZL6planyn,4,4
.local _ZL5plany
.comm _ZL5plany,4,4
.local _ZL7planxrn
.comm _ZL7planxrn,4,4
.local _ZL7planrxn
.comm _ZL7planrxn,4,4
.local _ZL6planxr
.comm _ZL6planxr,4,4
.local _ZL6planrx
.comm _ZL6planrx,4,4
.local _ZL4cfrc
.comm _ZL4cfrc,4,4
.local _ZL3crc
.comm _ZL3crc,4,4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC13:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/* CUDA FFT Library */
/* written by Viktor K. Decyk, UCLA */
#include <stdlib.h>
#include <stdio.h>
#include "cuda.h"
#include <cufft.h>
extern int nblock_size;
extern int maxgsx;
static cudaError_t crc;
static cufftResult cfrc;
static cufftHandle planrx, planxr, planrxn, planxrn;
static cufftHandle plany, planyn;
__global__ void gpuctpose4(float2 f[], float2 g[], int nx, int ny,
int nxv, int nyv);
__global__ void gpuctpose4n(float2 fn[], float2 gn[], int nx, int ny,
int ndim, int nxv, int nyv);
/*--------------------------------------------------------------------*/
__global__ void gpusctpose4(float2 f[], float2 g[], float ani, int nx,
int ny, int nxv, int nyv) {
/* scaled complex transpose using blocking algorithm with gaps */
/* local data */
int j, k, js, ks, joff, koff, mx, mxv;
float2 a;
/* The size of the shared memory array is as follows: */
/* float2 shm2[(mx + 1)*mx]; */
extern __shared__ float2 shm2[];
mx = blockDim.x;
mxv = mx + 1;
joff = mx*blockIdx.x;
koff = mx*blockIdx.y;
js = threadIdx.x;
ks = threadIdx.y;
/* copy into block */
j = js + joff;
k = ks + koff;
if ((j < nx) && (k < ny)) {
shm2[js+mxv*ks] = f[j+nxv*k];
}
__syncthreads();
/* copy out from block with scaling */
j = ks + joff;
k = js + koff;
if ((j < nx) && (k < ny)) {
a = shm2[ks+mxv*js];
a.x = ani*a.x;
a.y = ani*a.y;
g[k+nyv*j] = a;
}
return;
}
/*--------------------------------------------------------------------*/
__global__ void gpusctpose4n(float2 fn[], float2 gn[], float ani,
int nx, int ny, int ndim, int nxv,
int nyv) {
/* scaled complex vector transpose using blocking algorithm with gaps */
/* ndim = vector dimension */
/* local data */
int i, j, k, js, ks, joff, koff, mx, mxv, nmxv, nnxv, nnyv, jj, kk;
float2 a;
/* The size of the shared memory array is as follows: */
/* float2 shmn2[ndim*(mx + 1)*mx]; */
extern __shared__ float2 shmn2[];
mx = blockDim.x;
mxv = mx + 1;
joff = mx*blockIdx.x;
koff = mx*blockIdx.y;
js = threadIdx.x;
ks = threadIdx.y;
nmxv = ndim*mxv;
nnxv = ndim*nxv;
nnyv = ndim*nyv;
/* copy into block */
j = js + joff;
k = ks + koff;
if ((j < nx) && (k < ny)) {
jj = j + nnxv*k;
kk = js + nmxv*ks;
for (i = 0; i < ndim; i++) {
shmn2[kk+mxv*i] = fn[jj+nxv*i];
}
}
__syncthreads();
/* copy out from block with scaling */
j = ks + joff;
k = js + koff;
if ((j < nx) && (k < ny)) {
kk = k + nnyv*j;
jj = ks + nmxv*js;
for (i = 0; i < ndim; i++) {
a = shmn2[jj+mxv*i];
a.x = ani*a.x;
a.y = ani*a.y;
gn[kk+nyv*i] = a;
}
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcuinit(int nx, int ny, int ndim) {
cfrc = cufftPlan1d(&planrx,nx,CUFFT_R2C,ny);
if (cfrc) {
printf("cufftPlan1d planrx error=%d\n",cfrc);
exit(1);
}
cfrc = cufftPlan1d(&planxr,nx,CUFFT_C2R,ny);
if (cfrc) {
printf("cufftPlan1d planxr error=%d\n",cfrc);
exit(1);
}
cfrc = cufftPlan1d(&planrxn,nx,CUFFT_R2C,ndim*ny);
if (cfrc) {
printf("cufftPlan1d planrxn error=%d\n",cfrc);
exit(1);
}
cfrc = cufftPlan1d(&planxrn,nx,CUFFT_C2R,ndim*ny);
if (cfrc) {
printf("cufftPlan1d planxrn error=%d\n",cfrc);
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2cuinit(int nx, int ny, int ndim) {
int nxh1;
nxh1 = nx/2 + 1;
cfrc = cufftPlan1d(&plany,ny,CUFFT_C2C,nxh1);
if (cfrc) {
printf("cufftPlan1d plany error=%d\n",cfrc);
exit(1);
}
cfrc = cufftPlan1d(&planyn,ny,CUFFT_C2C,ndim*nxh1);
if (cfrc) {
printf("cufftPlan1d planyn error=%d\n",cfrc);
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcudel() {
cfrc = cufftDestroy(planrx);
if (cfrc) {
printf("cufftDestroy planrx error=%d\n",cfrc);
exit(1);
}
cfrc = cufftDestroy(planxr);
if (cfrc) {
printf("cufftDestroy planxr error=%d\n",cfrc);
exit(1);
}
cfrc = cufftDestroy(planrxn);
if (cfrc) {
printf("cufftDestroy planrxn error=%d\n",cfrc);
exit(1);
}
cfrc = cufftDestroy(planxrn);
if (cfrc) {
printf("cufftDestroy planxrn error=%d\n",cfrc);
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2cudel() {
cfrc = cufftDestroy(plany);
if (cfrc) {
printf("cufftDestroy plany error=%d\n",cfrc);
exit(1);
}
cfrc = cufftDestroy(planyn);
if (cfrc) {
printf("cufftDestroy planyn error=%d\n",cfrc);
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcu(float2 f[], float2 g[], int isign,
int indx, int indy, int nxh1d, int nyd) {
/* wrapper function for real to complex fft, without packed data */
/* uses 1D real to complex and complex to complex NVIDIA FFTs */
/* nxh1d must be = nx/2+1 */
/* local data */
int nx, nxh1, ny, ns;
int mx = 16;
float ani;
dim3 dimBlock(nblock_size);
dim3 dimBlockt(mx,mx);
/* calculate range of indices */
nx = 1L<<indx;
nxh1 = nx/2 + 1;
ny = 1L<<indy;
dim3 dimGridtx((nxh1-1)/mx+1,(ny-1)/mx+1);
dim3 dimGridty((ny-1)/mx+1,(nxh1-1)/mx+1);
ns = (mx+1)*mx*sizeof(float2);
/* inverse fourier transform */
if (isign < 0) {
/* perform x fft */
cfrc = cufftExecR2C(planrx,(cufftReal *)f,(cufftComplex *)f);
/* cudaThreadSynchronize(); */
if (cfrc) {
printf("cufftExecR2C(-1) planrx error=%d\n",cfrc);
exit(1);
}
/* transpose f to g and normalize */
ani = 1.0f/(((float) nx)*((float) ny));
crc = cudaGetLastError();
gpusctpose4<<<dimGridtx,dimBlockt,ns>>>(f,g,ani,nxh1,ny,nxh1d,
nyd);
/* cudaThreadSynchronize(); */
crc = cudaGetLastError();
if (crc) {
printf("gpusctpose4 error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
/* perform y fft */
cfrc = cufftExecC2C(plany,(cufftComplex *)g,(cufftComplex *)g,
CUFFT_FORWARD);
cudaThreadSynchronize();
if (cfrc) {
printf("cufftExecC2C(-1) plany error=%d\n",cfrc);
exit(1);
}
}
/* forward fourier transform */
else if (isign > 0) {
/* perform y fft */
cfrc = cufftExecC2C(plany,(cufftComplex *)g,(cufftComplex *)g,
CUFFT_INVERSE);
/* cudaThreadSynchronize(); */
if (cfrc) {
printf("cufftExecC2C(1) plany error=%d\n",cfrc);
exit(1);
}
/* transpose g to f */
crc = cudaGetLastError();
gpuctpose4<<<dimGridty,dimBlockt,ns>>>(g,f,ny,nxh1,nyd,nxh1d);
/* cudaThreadSynchronize(); */
crc = cudaGetLastError();
if (crc) {
printf("gpuctpose4 error=%d:%s\n",crc,cudaGetErrorString(crc));
exit(1);
}
/* perform x fft */
cfrc = cufftExecC2R(planxr,(cufftComplex *)f,(cufftReal *)f);
cudaThreadSynchronize();
if (cfrc) {
printf("cufftExecC2R(1) planxr error=%d\n",cfrc);
exit(1);
}
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcun(float2 fn[], float2 gn[], int isign,
int indx, int indy, int ndim, int nxh1d,
int nyd) {
/* wrapper function for real to complex fft, without packed data */
/* for vector data */
/* uses 1D real to complex and complex to complex NVIDIA FFTs */
/* ndim = vector dimension */
/* nxh1d must be = nx/2+1 */
/* local data */
int nx, nxh1, ny, ns;
int mx = 16;
float ani;
dim3 dimBlock(nblock_size);
dim3 dimBlockt(mx,mx);
/* calculate range of indices */
nx = 1L<<indx;
nxh1 = nx/2 + 1;
ny = 1L<<indy;
dim3 dimGridtx((nxh1-1)/mx+1,(ny-1)/mx+1);
dim3 dimGridty((ny-1)/mx+1,(nxh1-1)/mx+1);
ns = ndim*(mx+1)*mx*sizeof(float2);
/* inverse fourier transform */
if (isign < 0) {
/* perform x fft */
cfrc = cufftExecR2C(planrxn,(cufftReal *)fn,(cufftComplex *)fn);
/* cudaThreadSynchronize(); */
if (cfrc) {
printf("cufftExecR2C(-1) planrxn error=%d\n",cfrc);
exit(1);
}
/* transpose f to g and normalize */
ani = 1.0f/(((float) nx)*((float) ny));
crc = cudaGetLastError();
gpusctpose4n<<<dimGridtx,dimBlockt,ns>>>(fn,gn,ani,nxh1,ny,ndim,
nxh1d,nyd);
/* cudaThreadSynchronize(); */
crc = cudaGetLastError();
if (crc) {
printf("gpusctpose4n error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
/* perform y fft */
cfrc = cufftExecC2C(planyn,(cufftComplex *)gn,(cufftComplex *)gn,
CUFFT_FORWARD);
cudaThreadSynchronize();
if (cfrc) {
printf("cufftExecC2C(-1) planyn error=%d\n",cfrc);
exit(1);
}
}
/* forward fourier transform */
else if (isign > 0) {
/* perform y fft */
cfrc = cufftExecC2C(planyn,(cufftComplex *)gn,(cufftComplex *)gn,
CUFFT_INVERSE);
/* cudaThreadSynchronize(); */
if (cfrc) {
printf("cufftExecC2C(1) planyn error=%d\n",cfrc);
exit(1);
}
/* transpose g to f */
crc = cudaGetLastError();
gpuctpose4n<<<dimGridty,dimBlockt,ns>>>(gn,fn,ny,nxh1,ndim,nyd,
nxh1d);
/* cudaThreadSynchronize(); */
crc = cudaGetLastError();
if (crc) {
printf("gpuctpose4n error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
/* perform x fft */
cfrc = cufftExecC2R(planxrn,(cufftComplex *)fn,(cufftReal *)fn);
cudaThreadSynchronize();
if (cfrc) {
printf("cufftExecC2R(1) planxrn error=%d\n",cfrc);
exit(1);
}
}
return;
}
/* Interfaces to Fortran */
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcuinit_(int *nx, int *ny, int *ndim) {
gpufft2rrcuinit(*nx,*ny,*ndim);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2cuinit_(int *nx, int *ny, int *ndim) {
gpufft2cuinit(*nx,*ny,*ndim);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcudel_() {
gpufft2rrcudel();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2cudel_() {
gpufft2cudel();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcu_(unsigned long *gp_f, unsigned long *gp_g,
int *isign, int *indx, int *indy,
int *nxh1d, int *nyd) {
float2 *f, *g;
f = (float2 *)*gp_f;
g = (float2 *)*gp_g;
gpufft2rrcu(f,g,*isign,*indx,*indy,*nxh1d,*nyd);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcun_(unsigned long *gp_fn,
unsigned long *gp_gn, int *isign,
int *indx, int *indy, int *ndim,
int *nxh1d, int *nyd) {
float2 *fn, *gn;
fn = (float2 *)*gp_fn;
gn = (float2 *)*gp_gn;
gpufft2rrcun(fn,gn,*isign,*indx,*indy,*ndim,*nxh1d,*nyd);
return;
}
|
/* CUDA FFT Library */
/* written by Viktor K. Decyk, UCLA */
#include <stdlib.h>
#include <stdio.h>
#include "hip/hip_runtime.h"
#include <hipfft/hipfft.h>
extern int nblock_size;
extern int maxgsx;
static hipError_t crc;
static hipfftResult cfrc;
static hipfftHandle planrx, planxr, planrxn, planxrn;
static hipfftHandle plany, planyn;
__global__ void gpuctpose4(float2 f[], float2 g[], int nx, int ny,
int nxv, int nyv);
__global__ void gpuctpose4n(float2 fn[], float2 gn[], int nx, int ny,
int ndim, int nxv, int nyv);
/*--------------------------------------------------------------------*/
__global__ void gpusctpose4(float2 f[], float2 g[], float ani, int nx,
int ny, int nxv, int nyv) {
/* scaled complex transpose using blocking algorithm with gaps */
/* local data */
int j, k, js, ks, joff, koff, mx, mxv;
float2 a;
/* The size of the shared memory array is as follows: */
/* float2 shm2[(mx + 1)*mx]; */
extern __shared__ float2 shm2[];
mx = blockDim.x;
mxv = mx + 1;
joff = mx*blockIdx.x;
koff = mx*blockIdx.y;
js = threadIdx.x;
ks = threadIdx.y;
/* copy into block */
j = js + joff;
k = ks + koff;
if ((j < nx) && (k < ny)) {
shm2[js+mxv*ks] = f[j+nxv*k];
}
__syncthreads();
/* copy out from block with scaling */
j = ks + joff;
k = js + koff;
if ((j < nx) && (k < ny)) {
a = shm2[ks+mxv*js];
a.x = ani*a.x;
a.y = ani*a.y;
g[k+nyv*j] = a;
}
return;
}
/*--------------------------------------------------------------------*/
__global__ void gpusctpose4n(float2 fn[], float2 gn[], float ani,
int nx, int ny, int ndim, int nxv,
int nyv) {
/* scaled complex vector transpose using blocking algorithm with gaps */
/* ndim = vector dimension */
/* local data */
int i, j, k, js, ks, joff, koff, mx, mxv, nmxv, nnxv, nnyv, jj, kk;
float2 a;
/* The size of the shared memory array is as follows: */
/* float2 shmn2[ndim*(mx + 1)*mx]; */
extern __shared__ float2 shmn2[];
mx = blockDim.x;
mxv = mx + 1;
joff = mx*blockIdx.x;
koff = mx*blockIdx.y;
js = threadIdx.x;
ks = threadIdx.y;
nmxv = ndim*mxv;
nnxv = ndim*nxv;
nnyv = ndim*nyv;
/* copy into block */
j = js + joff;
k = ks + koff;
if ((j < nx) && (k < ny)) {
jj = j + nnxv*k;
kk = js + nmxv*ks;
for (i = 0; i < ndim; i++) {
shmn2[kk+mxv*i] = fn[jj+nxv*i];
}
}
__syncthreads();
/* copy out from block with scaling */
j = ks + joff;
k = js + koff;
if ((j < nx) && (k < ny)) {
kk = k + nnyv*j;
jj = ks + nmxv*js;
for (i = 0; i < ndim; i++) {
a = shmn2[jj+mxv*i];
a.x = ani*a.x;
a.y = ani*a.y;
gn[kk+nyv*i] = a;
}
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcuinit(int nx, int ny, int ndim) {
cfrc = hipfftPlan1d(&planrx,nx,HIPFFT_R2C,ny);
if (cfrc) {
printf("hipfftPlan1d planrx error=%d\n",cfrc);
exit(1);
}
cfrc = hipfftPlan1d(&planxr,nx,HIPFFT_C2R,ny);
if (cfrc) {
printf("hipfftPlan1d planxr error=%d\n",cfrc);
exit(1);
}
cfrc = hipfftPlan1d(&planrxn,nx,HIPFFT_R2C,ndim*ny);
if (cfrc) {
printf("hipfftPlan1d planrxn error=%d\n",cfrc);
exit(1);
}
cfrc = hipfftPlan1d(&planxrn,nx,HIPFFT_C2R,ndim*ny);
if (cfrc) {
printf("hipfftPlan1d planxrn error=%d\n",cfrc);
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2cuinit(int nx, int ny, int ndim) {
int nxh1;
nxh1 = nx/2 + 1;
cfrc = hipfftPlan1d(&plany,ny,HIPFFT_C2C,nxh1);
if (cfrc) {
printf("hipfftPlan1d plany error=%d\n",cfrc);
exit(1);
}
cfrc = hipfftPlan1d(&planyn,ny,HIPFFT_C2C,ndim*nxh1);
if (cfrc) {
printf("hipfftPlan1d planyn error=%d\n",cfrc);
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcudel() {
cfrc = hipfftDestroy(planrx);
if (cfrc) {
printf("hipfftDestroy planrx error=%d\n",cfrc);
exit(1);
}
cfrc = hipfftDestroy(planxr);
if (cfrc) {
printf("hipfftDestroy planxr error=%d\n",cfrc);
exit(1);
}
cfrc = hipfftDestroy(planrxn);
if (cfrc) {
printf("hipfftDestroy planrxn error=%d\n",cfrc);
exit(1);
}
cfrc = hipfftDestroy(planxrn);
if (cfrc) {
printf("hipfftDestroy planxrn error=%d\n",cfrc);
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2cudel() {
cfrc = hipfftDestroy(plany);
if (cfrc) {
printf("hipfftDestroy plany error=%d\n",cfrc);
exit(1);
}
cfrc = hipfftDestroy(planyn);
if (cfrc) {
printf("hipfftDestroy planyn error=%d\n",cfrc);
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcu(float2 f[], float2 g[], int isign,
int indx, int indy, int nxh1d, int nyd) {
/* wrapper function for real to complex fft, without packed data */
/* uses 1D real to complex and complex to complex NVIDIA FFTs */
/* nxh1d must be = nx/2+1 */
/* local data */
int nx, nxh1, ny, ns;
int mx = 16;
float ani;
dim3 dimBlock(nblock_size);
dim3 dimBlockt(mx,mx);
/* calculate range of indices */
nx = 1L<<indx;
nxh1 = nx/2 + 1;
ny = 1L<<indy;
dim3 dimGridtx((nxh1-1)/mx+1,(ny-1)/mx+1);
dim3 dimGridty((ny-1)/mx+1,(nxh1-1)/mx+1);
ns = (mx+1)*mx*sizeof(float2);
/* inverse fourier transform */
if (isign < 0) {
/* perform x fft */
cfrc = hipfftExecR2C(planrx,(hipfftReal *)f,(hipfftComplex *)f);
/* cudaThreadSynchronize(); */
if (cfrc) {
printf("cufftExecR2C(-1) planrx error=%d\n",cfrc);
exit(1);
}
/* transpose f to g and normalize */
ani = 1.0f/(((float) nx)*((float) ny));
crc = hipGetLastError();
gpusctpose4<<<dimGridtx,dimBlockt,ns>>>(f,g,ani,nxh1,ny,nxh1d,
nyd);
/* cudaThreadSynchronize(); */
crc = hipGetLastError();
if (crc) {
printf("gpusctpose4 error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
/* perform y fft */
cfrc = hipfftExecC2C(plany,(hipfftComplex *)g,(hipfftComplex *)g,
HIPFFT_FORWARD);
hipDeviceSynchronize();
if (cfrc) {
printf("cufftExecC2C(-1) plany error=%d\n",cfrc);
exit(1);
}
}
/* forward fourier transform */
else if (isign > 0) {
/* perform y fft */
cfrc = hipfftExecC2C(plany,(hipfftComplex *)g,(hipfftComplex *)g,
HIPFFT_BACKWARD);
/* cudaThreadSynchronize(); */
if (cfrc) {
printf("cufftExecC2C(1) plany error=%d\n",cfrc);
exit(1);
}
/* transpose g to f */
crc = hipGetLastError();
gpuctpose4<<<dimGridty,dimBlockt,ns>>>(g,f,ny,nxh1,nyd,nxh1d);
/* cudaThreadSynchronize(); */
crc = hipGetLastError();
if (crc) {
printf("gpuctpose4 error=%d:%s\n",crc,hipGetErrorString(crc));
exit(1);
}
/* perform x fft */
cfrc = hipfftExecC2R(planxr,(hipfftComplex *)f,(hipfftReal *)f);
hipDeviceSynchronize();
if (cfrc) {
printf("cufftExecC2R(1) planxr error=%d\n",cfrc);
exit(1);
}
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcun(float2 fn[], float2 gn[], int isign,
int indx, int indy, int ndim, int nxh1d,
int nyd) {
/* wrapper function for real to complex fft, without packed data */
/* for vector data */
/* uses 1D real to complex and complex to complex NVIDIA FFTs */
/* ndim = vector dimension */
/* nxh1d must be = nx/2+1 */
/* local data */
int nx, nxh1, ny, ns;
int mx = 16;
float ani;
dim3 dimBlock(nblock_size);
dim3 dimBlockt(mx,mx);
/* calculate range of indices */
nx = 1L<<indx;
nxh1 = nx/2 + 1;
ny = 1L<<indy;
dim3 dimGridtx((nxh1-1)/mx+1,(ny-1)/mx+1);
dim3 dimGridty((ny-1)/mx+1,(nxh1-1)/mx+1);
ns = ndim*(mx+1)*mx*sizeof(float2);
/* inverse fourier transform */
if (isign < 0) {
/* perform x fft */
cfrc = hipfftExecR2C(planrxn,(hipfftReal *)fn,(hipfftComplex *)fn);
/* cudaThreadSynchronize(); */
if (cfrc) {
printf("cufftExecR2C(-1) planrxn error=%d\n",cfrc);
exit(1);
}
/* transpose f to g and normalize */
ani = 1.0f/(((float) nx)*((float) ny));
crc = hipGetLastError();
gpusctpose4n<<<dimGridtx,dimBlockt,ns>>>(fn,gn,ani,nxh1,ny,ndim,
nxh1d,nyd);
/* cudaThreadSynchronize(); */
crc = hipGetLastError();
if (crc) {
printf("gpusctpose4n error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
/* perform y fft */
cfrc = hipfftExecC2C(planyn,(hipfftComplex *)gn,(hipfftComplex *)gn,
HIPFFT_FORWARD);
hipDeviceSynchronize();
if (cfrc) {
printf("cufftExecC2C(-1) planyn error=%d\n",cfrc);
exit(1);
}
}
/* forward fourier transform */
else if (isign > 0) {
/* perform y fft */
cfrc = hipfftExecC2C(planyn,(hipfftComplex *)gn,(hipfftComplex *)gn,
HIPFFT_BACKWARD);
/* cudaThreadSynchronize(); */
if (cfrc) {
printf("cufftExecC2C(1) planyn error=%d\n",cfrc);
exit(1);
}
/* transpose g to f */
crc = hipGetLastError();
gpuctpose4n<<<dimGridty,dimBlockt,ns>>>(gn,fn,ny,nxh1,ndim,nyd,
nxh1d);
/* cudaThreadSynchronize(); */
crc = hipGetLastError();
if (crc) {
printf("gpuctpose4n error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
/* perform x fft */
cfrc = hipfftExecC2R(planxrn,(hipfftComplex *)fn,(hipfftReal *)fn);
hipDeviceSynchronize();
if (cfrc) {
printf("cufftExecC2R(1) planxrn error=%d\n",cfrc);
exit(1);
}
}
return;
}
/* Interfaces to Fortran */
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcuinit_(int *nx, int *ny, int *ndim) {
gpufft2rrcuinit(*nx,*ny,*ndim);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2cuinit_(int *nx, int *ny, int *ndim) {
gpufft2cuinit(*nx,*ny,*ndim);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcudel_() {
gpufft2rrcudel();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2cudel_() {
gpufft2cudel();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcu_(unsigned long *gp_f, unsigned long *gp_g,
int *isign, int *indx, int *indy,
int *nxh1d, int *nyd) {
float2 *f, *g;
f = (float2 *)*gp_f;
g = (float2 *)*gp_g;
gpufft2rrcu(f,g,*isign,*indx,*indy,*nxh1d,*nyd);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcun_(unsigned long *gp_fn,
unsigned long *gp_gn, int *isign,
int *indx, int *indy, int *ndim,
int *nxh1d, int *nyd) {
float2 *fn, *gn;
fn = (float2 *)*gp_fn;
gn = (float2 *)*gp_gn;
gpufft2rrcun(fn,gn,*isign,*indx,*indy,*ndim,*nxh1d,*nyd);
return;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
/* CUDA FFT Library */
/* written by Viktor K. Decyk, UCLA */
#include <stdlib.h>
#include <stdio.h>
#include "hip/hip_runtime.h"
#include <hipfft/hipfft.h>
extern int nblock_size;
extern int maxgsx;
static hipError_t crc;
static hipfftResult cfrc;
static hipfftHandle planrx, planxr, planrxn, planxrn;
static hipfftHandle plany, planyn;
__global__ void gpuctpose4(float2 f[], float2 g[], int nx, int ny,
int nxv, int nyv);
__global__ void gpuctpose4n(float2 fn[], float2 gn[], int nx, int ny,
int ndim, int nxv, int nyv);
/*--------------------------------------------------------------------*/
__global__ void gpusctpose4(float2 f[], float2 g[], float ani, int nx,
int ny, int nxv, int nyv) {
/* scaled complex transpose using blocking algorithm with gaps */
/* local data */
int j, k, js, ks, joff, koff, mx, mxv;
float2 a;
/* The size of the shared memory array is as follows: */
/* float2 shm2[(mx + 1)*mx]; */
extern __shared__ float2 shm2[];
mx = blockDim.x;
mxv = mx + 1;
joff = mx*blockIdx.x;
koff = mx*blockIdx.y;
js = threadIdx.x;
ks = threadIdx.y;
/* copy into block */
j = js + joff;
k = ks + koff;
if ((j < nx) && (k < ny)) {
shm2[js+mxv*ks] = f[j+nxv*k];
}
__syncthreads();
/* copy out from block with scaling */
j = ks + joff;
k = js + koff;
if ((j < nx) && (k < ny)) {
a = shm2[ks+mxv*js];
a.x = ani*a.x;
a.y = ani*a.y;
g[k+nyv*j] = a;
}
return;
}
/*--------------------------------------------------------------------*/
__global__ void gpusctpose4n(float2 fn[], float2 gn[], float ani,
int nx, int ny, int ndim, int nxv,
int nyv) {
/* scaled complex vector transpose using blocking algorithm with gaps */
/* ndim = vector dimension */
/* local data */
int i, j, k, js, ks, joff, koff, mx, mxv, nmxv, nnxv, nnyv, jj, kk;
float2 a;
/* The size of the shared memory array is as follows: */
/* float2 shmn2[ndim*(mx + 1)*mx]; */
extern __shared__ float2 shmn2[];
mx = blockDim.x;
mxv = mx + 1;
joff = mx*blockIdx.x;
koff = mx*blockIdx.y;
js = threadIdx.x;
ks = threadIdx.y;
nmxv = ndim*mxv;
nnxv = ndim*nxv;
nnyv = ndim*nyv;
/* copy into block */
j = js + joff;
k = ks + koff;
if ((j < nx) && (k < ny)) {
jj = j + nnxv*k;
kk = js + nmxv*ks;
for (i = 0; i < ndim; i++) {
shmn2[kk+mxv*i] = fn[jj+nxv*i];
}
}
__syncthreads();
/* copy out from block with scaling */
j = ks + joff;
k = js + koff;
if ((j < nx) && (k < ny)) {
kk = k + nnyv*j;
jj = ks + nmxv*js;
for (i = 0; i < ndim; i++) {
a = shmn2[jj+mxv*i];
a.x = ani*a.x;
a.y = ani*a.y;
gn[kk+nyv*i] = a;
}
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcuinit(int nx, int ny, int ndim) {
cfrc = hipfftPlan1d(&planrx,nx,HIPFFT_R2C,ny);
if (cfrc) {
printf("hipfftPlan1d planrx error=%d\n",cfrc);
exit(1);
}
cfrc = hipfftPlan1d(&planxr,nx,HIPFFT_C2R,ny);
if (cfrc) {
printf("hipfftPlan1d planxr error=%d\n",cfrc);
exit(1);
}
cfrc = hipfftPlan1d(&planrxn,nx,HIPFFT_R2C,ndim*ny);
if (cfrc) {
printf("hipfftPlan1d planrxn error=%d\n",cfrc);
exit(1);
}
cfrc = hipfftPlan1d(&planxrn,nx,HIPFFT_C2R,ndim*ny);
if (cfrc) {
printf("hipfftPlan1d planxrn error=%d\n",cfrc);
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2cuinit(int nx, int ny, int ndim) {
int nxh1;
nxh1 = nx/2 + 1;
cfrc = hipfftPlan1d(&plany,ny,HIPFFT_C2C,nxh1);
if (cfrc) {
printf("hipfftPlan1d plany error=%d\n",cfrc);
exit(1);
}
cfrc = hipfftPlan1d(&planyn,ny,HIPFFT_C2C,ndim*nxh1);
if (cfrc) {
printf("hipfftPlan1d planyn error=%d\n",cfrc);
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcudel() {
cfrc = hipfftDestroy(planrx);
if (cfrc) {
printf("hipfftDestroy planrx error=%d\n",cfrc);
exit(1);
}
cfrc = hipfftDestroy(planxr);
if (cfrc) {
printf("hipfftDestroy planxr error=%d\n",cfrc);
exit(1);
}
cfrc = hipfftDestroy(planrxn);
if (cfrc) {
printf("hipfftDestroy planrxn error=%d\n",cfrc);
exit(1);
}
cfrc = hipfftDestroy(planxrn);
if (cfrc) {
printf("hipfftDestroy planxrn error=%d\n",cfrc);
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2cudel() {
cfrc = hipfftDestroy(plany);
if (cfrc) {
printf("hipfftDestroy plany error=%d\n",cfrc);
exit(1);
}
cfrc = hipfftDestroy(planyn);
if (cfrc) {
printf("hipfftDestroy planyn error=%d\n",cfrc);
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcu(float2 f[], float2 g[], int isign,
int indx, int indy, int nxh1d, int nyd) {
/* wrapper function for real to complex fft, without packed data */
/* uses 1D real to complex and complex to complex NVIDIA FFTs */
/* nxh1d must be = nx/2+1 */
/* local data */
int nx, nxh1, ny, ns;
int mx = 16;
float ani;
dim3 dimBlock(nblock_size);
dim3 dimBlockt(mx,mx);
/* calculate range of indices */
nx = 1L<<indx;
nxh1 = nx/2 + 1;
ny = 1L<<indy;
dim3 dimGridtx((nxh1-1)/mx+1,(ny-1)/mx+1);
dim3 dimGridty((ny-1)/mx+1,(nxh1-1)/mx+1);
ns = (mx+1)*mx*sizeof(float2);
/* inverse fourier transform */
if (isign < 0) {
/* perform x fft */
cfrc = hipfftExecR2C(planrx,(hipfftReal *)f,(hipfftComplex *)f);
/* cudaThreadSynchronize(); */
if (cfrc) {
printf("cufftExecR2C(-1) planrx error=%d\n",cfrc);
exit(1);
}
/* transpose f to g and normalize */
ani = 1.0f/(((float) nx)*((float) ny));
crc = hipGetLastError();
gpusctpose4<<<dimGridtx,dimBlockt,ns>>>(f,g,ani,nxh1,ny,nxh1d,
nyd);
/* cudaThreadSynchronize(); */
crc = hipGetLastError();
if (crc) {
printf("gpusctpose4 error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
/* perform y fft */
cfrc = hipfftExecC2C(plany,(hipfftComplex *)g,(hipfftComplex *)g,
HIPFFT_FORWARD);
hipDeviceSynchronize();
if (cfrc) {
printf("cufftExecC2C(-1) plany error=%d\n",cfrc);
exit(1);
}
}
/* forward fourier transform */
else if (isign > 0) {
/* perform y fft */
cfrc = hipfftExecC2C(plany,(hipfftComplex *)g,(hipfftComplex *)g,
HIPFFT_BACKWARD);
/* cudaThreadSynchronize(); */
if (cfrc) {
printf("cufftExecC2C(1) plany error=%d\n",cfrc);
exit(1);
}
/* transpose g to f */
crc = hipGetLastError();
gpuctpose4<<<dimGridty,dimBlockt,ns>>>(g,f,ny,nxh1,nyd,nxh1d);
/* cudaThreadSynchronize(); */
crc = hipGetLastError();
if (crc) {
printf("gpuctpose4 error=%d:%s\n",crc,hipGetErrorString(crc));
exit(1);
}
/* perform x fft */
cfrc = hipfftExecC2R(planxr,(hipfftComplex *)f,(hipfftReal *)f);
hipDeviceSynchronize();
if (cfrc) {
printf("cufftExecC2R(1) planxr error=%d\n",cfrc);
exit(1);
}
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcun(float2 fn[], float2 gn[], int isign,
int indx, int indy, int ndim, int nxh1d,
int nyd) {
/* wrapper function for real to complex fft, without packed data */
/* for vector data */
/* uses 1D real to complex and complex to complex NVIDIA FFTs */
/* ndim = vector dimension */
/* nxh1d must be = nx/2+1 */
/* local data */
int nx, nxh1, ny, ns;
int mx = 16;
float ani;
dim3 dimBlock(nblock_size);
dim3 dimBlockt(mx,mx);
/* calculate range of indices */
nx = 1L<<indx;
nxh1 = nx/2 + 1;
ny = 1L<<indy;
dim3 dimGridtx((nxh1-1)/mx+1,(ny-1)/mx+1);
dim3 dimGridty((ny-1)/mx+1,(nxh1-1)/mx+1);
ns = ndim*(mx+1)*mx*sizeof(float2);
/* inverse fourier transform */
if (isign < 0) {
/* perform x fft */
cfrc = hipfftExecR2C(planrxn,(hipfftReal *)fn,(hipfftComplex *)fn);
/* cudaThreadSynchronize(); */
if (cfrc) {
printf("cufftExecR2C(-1) planrxn error=%d\n",cfrc);
exit(1);
}
/* transpose f to g and normalize */
ani = 1.0f/(((float) nx)*((float) ny));
crc = hipGetLastError();
gpusctpose4n<<<dimGridtx,dimBlockt,ns>>>(fn,gn,ani,nxh1,ny,ndim,
nxh1d,nyd);
/* cudaThreadSynchronize(); */
crc = hipGetLastError();
if (crc) {
printf("gpusctpose4n error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
/* perform y fft */
cfrc = hipfftExecC2C(planyn,(hipfftComplex *)gn,(hipfftComplex *)gn,
HIPFFT_FORWARD);
hipDeviceSynchronize();
if (cfrc) {
printf("cufftExecC2C(-1) planyn error=%d\n",cfrc);
exit(1);
}
}
/* forward fourier transform */
else if (isign > 0) {
/* perform y fft */
cfrc = hipfftExecC2C(planyn,(hipfftComplex *)gn,(hipfftComplex *)gn,
HIPFFT_BACKWARD);
/* cudaThreadSynchronize(); */
if (cfrc) {
printf("cufftExecC2C(1) planyn error=%d\n",cfrc);
exit(1);
}
/* transpose g to f */
crc = hipGetLastError();
gpuctpose4n<<<dimGridty,dimBlockt,ns>>>(gn,fn,ny,nxh1,ndim,nyd,
nxh1d);
/* cudaThreadSynchronize(); */
crc = hipGetLastError();
if (crc) {
printf("gpuctpose4n error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
/* perform x fft */
cfrc = hipfftExecC2R(planxrn,(hipfftComplex *)fn,(hipfftReal *)fn);
hipDeviceSynchronize();
if (cfrc) {
printf("cufftExecC2R(1) planxrn error=%d\n",cfrc);
exit(1);
}
}
return;
}
/* Interfaces to Fortran */
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcuinit_(int *nx, int *ny, int *ndim) {
gpufft2rrcuinit(*nx,*ny,*ndim);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2cuinit_(int *nx, int *ny, int *ndim) {
gpufft2cuinit(*nx,*ny,*ndim);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcudel_() {
gpufft2rrcudel();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2cudel_() {
gpufft2cudel();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcu_(unsigned long *gp_f, unsigned long *gp_g,
int *isign, int *indx, int *indy,
int *nxh1d, int *nyd) {
float2 *f, *g;
f = (float2 *)*gp_f;
g = (float2 *)*gp_g;
gpufft2rrcu(f,g,*isign,*indx,*indy,*nxh1d,*nyd);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcun_(unsigned long *gp_fn,
unsigned long *gp_gn, int *isign,
int *indx, int *indy, int *ndim,
int *nxh1d, int *nyd) {
float2 *fn, *gn;
fn = (float2 *)*gp_fn;
gn = (float2 *)*gp_gn;
gpufft2rrcun(fn,gn,*isign,*indx,*indy,*ndim,*nxh1d,*nyd);
return;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11gpusctpose4P15HIP_vector_typeIfLj2EES1_fiiii
.globl _Z11gpusctpose4P15HIP_vector_typeIfLj2EES1_fiiii
.p2align 8
.type _Z11gpusctpose4P15HIP_vector_typeIfLj2EES1_fiiii,@function
_Z11gpusctpose4P15HIP_vector_typeIfLj2EES1_fiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x14
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
s_mul_i32 s14, s14, s3
s_mul_i32 s15, s15, s3
v_add_nc_u32_e32 v0, s14, v1
v_add_nc_u32_e32 v3, s15, v2
s_add_i32 s3, s3, 1
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v3
s_and_b32 s6, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s6
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b32 s8, s[0:1], 0x1c
s_load_b64 s[6:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[4:5], null, v3, s8, v[0:1]
v_mad_u32_u24 v0, s3, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshl_add_u32 v0, v0, 3, 0
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[4:5]
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b64 v[3:4], v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b64 v0, v[3:4]
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v3, s14, v2
v_add_nc_u32_e32 v0, s15, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmp_gt_i32_e32 vcc_lo, s4, v3
v_cmp_gt_i32_e64 s2, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_4
v_mad_u32_u24 v1, s3, v1, v2
s_clause 0x2
s_load_b32 s2, s[0:1], 0x20
s_load_b32 s3, s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x8
v_lshl_add_u32 v1, v1, 3, 0
ds_load_2addr_b32 v[1:2], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[4:5], null, v3, s2, v[0:1]
v_dual_mul_f32 v0, s3, v1 :: v_dual_mul_f32 v1, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[3:4], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v4, vcc_lo
global_store_b64 v[2:3], v[0:1], off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11gpusctpose4P15HIP_vector_typeIfLj2EES1_fiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11gpusctpose4P15HIP_vector_typeIfLj2EES1_fiiii, .Lfunc_end0-_Z11gpusctpose4P15HIP_vector_typeIfLj2EES1_fiiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12gpusctpose4nP15HIP_vector_typeIfLj2EES1_fiiiii
.globl _Z12gpusctpose4nP15HIP_vector_typeIfLj2EES1_fiiiii
.p2align 8
.type _Z12gpusctpose4nP15HIP_vector_typeIfLj2EES1_fiiiii,@function
_Z12gpusctpose4nP15HIP_vector_typeIfLj2EES1_fiiiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x14
s_load_b32 s6, s[0:1], 0x1c
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
s_mul_i32 s14, s14, s7
s_mul_i32 s15, s15, s7
v_add_nc_u32_e32 v1, s14, v2
v_add_nc_u32_e32 v0, s15, v3
s_add_i32 s8, s7, 1
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s9, s2
s_cbranch_execz .LBB1_4
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB1_4
s_clause 0x1
s_load_b32 s10, s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x0
v_mul_lo_u32 v1, v3, s6
v_lshlrev_b32_e32 v4, 3, v2
s_mov_b32 s12, s6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v1, s8
v_lshlrev_b32_e32 v1, 3, v1
s_waitcnt lgkmcnt(0)
s_mul_i32 s11, s10, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v0, s11, v0
v_add3_u32 v4, v1, v4, 0
s_lshl_b32 s11, s7, 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_add_i32 s11, s11, 8
v_add3_u32 v0, v2, v0, s14
.LBB1_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s12, s12, -1
s_cmp_lg_u32 s12, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 3, v[0:1]
v_add_nc_u32_e32 v0, s10, v0
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b64 v[5:6], v[5:6], off
s_waitcnt vmcnt(0)
ds_store_b64 v4, v[5:6]
v_add_nc_u32_e32 v4, s11, v4
s_cbranch_scc1 .LBB1_3
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s9
v_add_nc_u32_e32 v0, s14, v3
v_add_nc_u32_e32 v1, s15, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmp_gt_i32_e32 vcc_lo, s4, v0
v_cmp_gt_i32_e64 s2, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_8
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB1_8
s_load_b32 s4, s[0:1], 0x24
v_mul_lo_u32 v1, v2, s6
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s0, s[0:1], 0x10
v_lshlrev_b32_e32 v3, 3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v1, s8
v_lshlrev_b32_e32 v1, 3, v1
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s4, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add3_u32 v3, v1, v3, 0
v_mul_lo_u32 v0, s1, v0
s_lshl_b32 s1, s7, 3
s_add_i32 s1, s1, 8
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v0, v2, v0, s15
.p2align 6
.LBB1_7:
ds_load_2addr_b32 v[4:5], v3 offset1:1
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v3, s1, v3
s_add_i32 s6, s6, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_lg_u32 s6, 0
v_lshlrev_b64 v[1:2], 3, v[0:1]
v_add_nc_u32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_waitcnt lgkmcnt(0)
v_dual_mul_f32 v4, s0, v4 :: v_dual_mul_f32 v5, s0, v5
global_store_b64 v[1:2], v[4:5], off
s_cbranch_scc1 .LBB1_7
.LBB1_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12gpusctpose4nP15HIP_vector_typeIfLj2EES1_fiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12gpusctpose4nP15HIP_vector_typeIfLj2EES1_fiiiii, .Lfunc_end1-_Z12gpusctpose4nP15HIP_vector_typeIfLj2EES1_fiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
- .offset: 160
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11gpusctpose4P15HIP_vector_typeIfLj2EES1_fiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11gpusctpose4P15HIP_vector_typeIfLj2EES1_fiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
- .offset: 160
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12gpusctpose4nP15HIP_vector_typeIfLj2EES1_fiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12gpusctpose4nP15HIP_vector_typeIfLj2EES1_fiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
/* CUDA FFT Library */
/* written by Viktor K. Decyk, UCLA */
#include <stdlib.h>
#include <stdio.h>
#include "hip/hip_runtime.h"
#include <hipfft/hipfft.h>
extern int nblock_size;
extern int maxgsx;
static hipError_t crc;
static hipfftResult cfrc;
static hipfftHandle planrx, planxr, planrxn, planxrn;
static hipfftHandle plany, planyn;
__global__ void gpuctpose4(float2 f[], float2 g[], int nx, int ny,
int nxv, int nyv);
__global__ void gpuctpose4n(float2 fn[], float2 gn[], int nx, int ny,
int ndim, int nxv, int nyv);
/*--------------------------------------------------------------------*/
__global__ void gpusctpose4(float2 f[], float2 g[], float ani, int nx,
int ny, int nxv, int nyv) {
/* scaled complex transpose using blocking algorithm with gaps */
/* local data */
int j, k, js, ks, joff, koff, mx, mxv;
float2 a;
/* The size of the shared memory array is as follows: */
/* float2 shm2[(mx + 1)*mx]; */
extern __shared__ float2 shm2[];
mx = blockDim.x;
mxv = mx + 1;
joff = mx*blockIdx.x;
koff = mx*blockIdx.y;
js = threadIdx.x;
ks = threadIdx.y;
/* copy into block */
j = js + joff;
k = ks + koff;
if ((j < nx) && (k < ny)) {
shm2[js+mxv*ks] = f[j+nxv*k];
}
__syncthreads();
/* copy out from block with scaling */
j = ks + joff;
k = js + koff;
if ((j < nx) && (k < ny)) {
a = shm2[ks+mxv*js];
a.x = ani*a.x;
a.y = ani*a.y;
g[k+nyv*j] = a;
}
return;
}
/*--------------------------------------------------------------------*/
__global__ void gpusctpose4n(float2 fn[], float2 gn[], float ani,
int nx, int ny, int ndim, int nxv,
int nyv) {
/* scaled complex vector transpose using blocking algorithm with gaps */
/* ndim = vector dimension */
/* local data */
int i, j, k, js, ks, joff, koff, mx, mxv, nmxv, nnxv, nnyv, jj, kk;
float2 a;
/* The size of the shared memory array is as follows: */
/* float2 shmn2[ndim*(mx + 1)*mx]; */
extern __shared__ float2 shmn2[];
mx = blockDim.x;
mxv = mx + 1;
joff = mx*blockIdx.x;
koff = mx*blockIdx.y;
js = threadIdx.x;
ks = threadIdx.y;
nmxv = ndim*mxv;
nnxv = ndim*nxv;
nnyv = ndim*nyv;
/* copy into block */
j = js + joff;
k = ks + koff;
if ((j < nx) && (k < ny)) {
jj = j + nnxv*k;
kk = js + nmxv*ks;
for (i = 0; i < ndim; i++) {
shmn2[kk+mxv*i] = fn[jj+nxv*i];
}
}
__syncthreads();
/* copy out from block with scaling */
j = ks + joff;
k = js + koff;
if ((j < nx) && (k < ny)) {
kk = k + nnyv*j;
jj = ks + nmxv*js;
for (i = 0; i < ndim; i++) {
a = shmn2[jj+mxv*i];
a.x = ani*a.x;
a.y = ani*a.y;
gn[kk+nyv*i] = a;
}
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcuinit(int nx, int ny, int ndim) {
cfrc = hipfftPlan1d(&planrx,nx,HIPFFT_R2C,ny);
if (cfrc) {
printf("hipfftPlan1d planrx error=%d\n",cfrc);
exit(1);
}
cfrc = hipfftPlan1d(&planxr,nx,HIPFFT_C2R,ny);
if (cfrc) {
printf("hipfftPlan1d planxr error=%d\n",cfrc);
exit(1);
}
cfrc = hipfftPlan1d(&planrxn,nx,HIPFFT_R2C,ndim*ny);
if (cfrc) {
printf("hipfftPlan1d planrxn error=%d\n",cfrc);
exit(1);
}
cfrc = hipfftPlan1d(&planxrn,nx,HIPFFT_C2R,ndim*ny);
if (cfrc) {
printf("hipfftPlan1d planxrn error=%d\n",cfrc);
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2cuinit(int nx, int ny, int ndim) {
int nxh1;
nxh1 = nx/2 + 1;
cfrc = hipfftPlan1d(&plany,ny,HIPFFT_C2C,nxh1);
if (cfrc) {
printf("hipfftPlan1d plany error=%d\n",cfrc);
exit(1);
}
cfrc = hipfftPlan1d(&planyn,ny,HIPFFT_C2C,ndim*nxh1);
if (cfrc) {
printf("hipfftPlan1d planyn error=%d\n",cfrc);
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcudel() {
cfrc = hipfftDestroy(planrx);
if (cfrc) {
printf("hipfftDestroy planrx error=%d\n",cfrc);
exit(1);
}
cfrc = hipfftDestroy(planxr);
if (cfrc) {
printf("hipfftDestroy planxr error=%d\n",cfrc);
exit(1);
}
cfrc = hipfftDestroy(planrxn);
if (cfrc) {
printf("hipfftDestroy planrxn error=%d\n",cfrc);
exit(1);
}
cfrc = hipfftDestroy(planxrn);
if (cfrc) {
printf("hipfftDestroy planxrn error=%d\n",cfrc);
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2cudel() {
cfrc = hipfftDestroy(plany);
if (cfrc) {
printf("hipfftDestroy plany error=%d\n",cfrc);
exit(1);
}
cfrc = hipfftDestroy(planyn);
if (cfrc) {
printf("hipfftDestroy planyn error=%d\n",cfrc);
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcu(float2 f[], float2 g[], int isign,
int indx, int indy, int nxh1d, int nyd) {
/* wrapper function for real to complex fft, without packed data */
/* uses 1D real to complex and complex to complex NVIDIA FFTs */
/* nxh1d must be = nx/2+1 */
/* local data */
int nx, nxh1, ny, ns;
int mx = 16;
float ani;
dim3 dimBlock(nblock_size);
dim3 dimBlockt(mx,mx);
/* calculate range of indices */
nx = 1L<<indx;
nxh1 = nx/2 + 1;
ny = 1L<<indy;
dim3 dimGridtx((nxh1-1)/mx+1,(ny-1)/mx+1);
dim3 dimGridty((ny-1)/mx+1,(nxh1-1)/mx+1);
ns = (mx+1)*mx*sizeof(float2);
/* inverse fourier transform */
if (isign < 0) {
/* perform x fft */
cfrc = hipfftExecR2C(planrx,(hipfftReal *)f,(hipfftComplex *)f);
/* cudaThreadSynchronize(); */
if (cfrc) {
printf("cufftExecR2C(-1) planrx error=%d\n",cfrc);
exit(1);
}
/* transpose f to g and normalize */
ani = 1.0f/(((float) nx)*((float) ny));
crc = hipGetLastError();
gpusctpose4<<<dimGridtx,dimBlockt,ns>>>(f,g,ani,nxh1,ny,nxh1d,
nyd);
/* cudaThreadSynchronize(); */
crc = hipGetLastError();
if (crc) {
printf("gpusctpose4 error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
/* perform y fft */
cfrc = hipfftExecC2C(plany,(hipfftComplex *)g,(hipfftComplex *)g,
HIPFFT_FORWARD);
hipDeviceSynchronize();
if (cfrc) {
printf("cufftExecC2C(-1) plany error=%d\n",cfrc);
exit(1);
}
}
/* forward fourier transform */
else if (isign > 0) {
/* perform y fft */
cfrc = hipfftExecC2C(plany,(hipfftComplex *)g,(hipfftComplex *)g,
HIPFFT_BACKWARD);
/* cudaThreadSynchronize(); */
if (cfrc) {
printf("cufftExecC2C(1) plany error=%d\n",cfrc);
exit(1);
}
/* transpose g to f */
crc = hipGetLastError();
gpuctpose4<<<dimGridty,dimBlockt,ns>>>(g,f,ny,nxh1,nyd,nxh1d);
/* cudaThreadSynchronize(); */
crc = hipGetLastError();
if (crc) {
printf("gpuctpose4 error=%d:%s\n",crc,hipGetErrorString(crc));
exit(1);
}
/* perform x fft */
cfrc = hipfftExecC2R(planxr,(hipfftComplex *)f,(hipfftReal *)f);
hipDeviceSynchronize();
if (cfrc) {
printf("cufftExecC2R(1) planxr error=%d\n",cfrc);
exit(1);
}
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcun(float2 fn[], float2 gn[], int isign,
int indx, int indy, int ndim, int nxh1d,
int nyd) {
/* wrapper function for real to complex fft, without packed data */
/* for vector data */
/* uses 1D real to complex and complex to complex NVIDIA FFTs */
/* ndim = vector dimension */
/* nxh1d must be = nx/2+1 */
/* local data */
int nx, nxh1, ny, ns;
int mx = 16;
float ani;
dim3 dimBlock(nblock_size);
dim3 dimBlockt(mx,mx);
/* calculate range of indices */
nx = 1L<<indx;
nxh1 = nx/2 + 1;
ny = 1L<<indy;
dim3 dimGridtx((nxh1-1)/mx+1,(ny-1)/mx+1);
dim3 dimGridty((ny-1)/mx+1,(nxh1-1)/mx+1);
ns = ndim*(mx+1)*mx*sizeof(float2);
/* inverse fourier transform */
if (isign < 0) {
/* perform x fft */
cfrc = hipfftExecR2C(planrxn,(hipfftReal *)fn,(hipfftComplex *)fn);
/* cudaThreadSynchronize(); */
if (cfrc) {
printf("cufftExecR2C(-1) planrxn error=%d\n",cfrc);
exit(1);
}
/* transpose f to g and normalize */
ani = 1.0f/(((float) nx)*((float) ny));
crc = hipGetLastError();
gpusctpose4n<<<dimGridtx,dimBlockt,ns>>>(fn,gn,ani,nxh1,ny,ndim,
nxh1d,nyd);
/* cudaThreadSynchronize(); */
crc = hipGetLastError();
if (crc) {
printf("gpusctpose4n error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
/* perform y fft */
cfrc = hipfftExecC2C(planyn,(hipfftComplex *)gn,(hipfftComplex *)gn,
HIPFFT_FORWARD);
hipDeviceSynchronize();
if (cfrc) {
printf("cufftExecC2C(-1) planyn error=%d\n",cfrc);
exit(1);
}
}
/* forward fourier transform */
else if (isign > 0) {
/* perform y fft */
cfrc = hipfftExecC2C(planyn,(hipfftComplex *)gn,(hipfftComplex *)gn,
HIPFFT_BACKWARD);
/* cudaThreadSynchronize(); */
if (cfrc) {
printf("cufftExecC2C(1) planyn error=%d\n",cfrc);
exit(1);
}
/* transpose g to f */
crc = hipGetLastError();
gpuctpose4n<<<dimGridty,dimBlockt,ns>>>(gn,fn,ny,nxh1,ndim,nyd,
nxh1d);
/* cudaThreadSynchronize(); */
crc = hipGetLastError();
if (crc) {
printf("gpuctpose4n error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
/* perform x fft */
cfrc = hipfftExecC2R(planxrn,(hipfftComplex *)fn,(hipfftReal *)fn);
hipDeviceSynchronize();
if (cfrc) {
printf("cufftExecC2R(1) planxrn error=%d\n",cfrc);
exit(1);
}
}
return;
}
/* Interfaces to Fortran */
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcuinit_(int *nx, int *ny, int *ndim) {
gpufft2rrcuinit(*nx,*ny,*ndim);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2cuinit_(int *nx, int *ny, int *ndim) {
gpufft2cuinit(*nx,*ny,*ndim);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcudel_() {
gpufft2rrcudel();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2cudel_() {
gpufft2cudel();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcu_(unsigned long *gp_f, unsigned long *gp_g,
int *isign, int *indx, int *indy,
int *nxh1d, int *nyd) {
float2 *f, *g;
f = (float2 *)*gp_f;
g = (float2 *)*gp_g;
gpufft2rrcu(f,g,*isign,*indx,*indy,*nxh1d,*nyd);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpufft2rrcun_(unsigned long *gp_fn,
unsigned long *gp_gn, int *isign,
int *indx, int *indy, int *ndim,
int *nxh1d, int *nyd) {
float2 *fn, *gn;
fn = (float2 *)*gp_fn;
gn = (float2 *)*gp_gn;
gpufft2rrcun(fn,gn,*isign,*indx,*indy,*ndim,*nxh1d,*nyd);
return;
}
|
.text
.file "gpufft2.hip"
.globl _Z26__device_stub__gpusctpose4P15HIP_vector_typeIfLj2EES1_fiiii # -- Begin function _Z26__device_stub__gpusctpose4P15HIP_vector_typeIfLj2EES1_fiiii
.p2align 4, 0x90
.type _Z26__device_stub__gpusctpose4P15HIP_vector_typeIfLj2EES1_fiiii,@function
_Z26__device_stub__gpusctpose4P15HIP_vector_typeIfLj2EES1_fiiii: # @_Z26__device_stub__gpusctpose4P15HIP_vector_typeIfLj2EES1_fiiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movss %xmm0, 28(%rsp)
movl %edx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11gpusctpose4P15HIP_vector_typeIfLj2EES1_fiiii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__gpusctpose4P15HIP_vector_typeIfLj2EES1_fiiii, .Lfunc_end0-_Z26__device_stub__gpusctpose4P15HIP_vector_typeIfLj2EES1_fiiii
.cfi_endproc
# -- End function
.globl _Z27__device_stub__gpusctpose4nP15HIP_vector_typeIfLj2EES1_fiiiii # -- Begin function _Z27__device_stub__gpusctpose4nP15HIP_vector_typeIfLj2EES1_fiiiii
.p2align 4, 0x90
.type _Z27__device_stub__gpusctpose4nP15HIP_vector_typeIfLj2EES1_fiiiii,@function
_Z27__device_stub__gpusctpose4nP15HIP_vector_typeIfLj2EES1_fiiiii: # @_Z27__device_stub__gpusctpose4nP15HIP_vector_typeIfLj2EES1_fiiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movss %xmm0, 28(%rsp)
movl %edx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12gpusctpose4nP15HIP_vector_typeIfLj2EES1_fiiiii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _Z27__device_stub__gpusctpose4nP15HIP_vector_typeIfLj2EES1_fiiiii, .Lfunc_end1-_Z27__device_stub__gpusctpose4nP15HIP_vector_typeIfLj2EES1_fiiiii
.cfi_endproc
# -- End function
.globl gpufft2rrcuinit # -- Begin function gpufft2rrcuinit
.p2align 4, 0x90
.type gpufft2rrcuinit,@function
gpufft2rrcuinit: # @gpufft2rrcuinit
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %r14d
movl %edi, %ebp
movl $_ZL6planrx, %edi
movl %ebp, %esi
movl $42, %edx
movl %r14d, %ecx
callq hipfftPlan1d
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .LBB2_1
# %bb.3:
movl $_ZL6planxr, %edi
movl %ebp, %esi
movl $44, %edx
movl %r14d, %ecx
callq hipfftPlan1d
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .LBB2_4
# %bb.5:
imull %r14d, %ebx
movl $_ZL7planrxn, %edi
movl %ebp, %esi
movl $42, %edx
movl %ebx, %ecx
callq hipfftPlan1d
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .LBB2_6
# %bb.7:
movl $_ZL7planxrn, %edi
movl %ebp, %esi
movl $44, %edx
movl %ebx, %ecx
callq hipfftPlan1d
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .LBB2_8
# %bb.9:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 32
movl $.L.str, %edi
jmp .LBB2_2
.LBB2_4:
movl $.L.str.1, %edi
jmp .LBB2_2
.LBB2_6:
movl $.L.str.2, %edi
jmp .LBB2_2
.LBB2_8:
movl $.L.str.3, %edi
.LBB2_2:
movl %eax, %esi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size gpufft2rrcuinit, .Lfunc_end2-gpufft2rrcuinit
.cfi_endproc
# -- End function
.globl gpufft2cuinit # -- Begin function gpufft2cuinit
.p2align 4, 0x90
.type gpufft2cuinit,@function
gpufft2cuinit: # @gpufft2cuinit
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %edx, %r14d
movl %esi, %ebp
movl %edi, %ebx
shrl $31, %ebx
addl %edi, %ebx
sarl %ebx
incl %ebx
movl $_ZL5plany, %edi
movl $41, %edx
movl %ebx, %ecx
callq hipfftPlan1d
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .LBB3_1
# %bb.3:
imull %r14d, %ebx
movl $_ZL6planyn, %edi
movl %ebp, %esi
movl $41, %edx
movl %ebx, %ecx
callq hipfftPlan1d
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .LBB3_4
# %bb.5:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_1:
.cfi_def_cfa_offset 32
movl $.L.str.4, %edi
jmp .LBB3_2
.LBB3_4:
movl $.L.str.5, %edi
.LBB3_2:
movl %eax, %esi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end3:
.size gpufft2cuinit, .Lfunc_end3-gpufft2cuinit
.cfi_endproc
# -- End function
.globl gpufft2rrcudel # -- Begin function gpufft2rrcudel
.p2align 4, 0x90
.type gpufft2rrcudel,@function
gpufft2rrcudel: # @gpufft2rrcudel
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq _ZL6planrx(%rip), %rdi
callq hipfftDestroy
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .LBB4_1
# %bb.3:
movq _ZL6planxr(%rip), %rdi
callq hipfftDestroy
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .LBB4_4
# %bb.5:
movq _ZL7planrxn(%rip), %rdi
callq hipfftDestroy
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .LBB4_6
# %bb.7:
movq _ZL7planxrn(%rip), %rdi
callq hipfftDestroy
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .LBB4_8
# %bb.9:
popq %rax
.cfi_def_cfa_offset 8
retq
.LBB4_1:
.cfi_def_cfa_offset 16
movl $.L.str.6, %edi
jmp .LBB4_2
.LBB4_4:
movl $.L.str.7, %edi
jmp .LBB4_2
.LBB4_6:
movl $.L.str.8, %edi
jmp .LBB4_2
.LBB4_8:
movl $.L.str.9, %edi
.LBB4_2:
movl %eax, %esi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end4:
.size gpufft2rrcudel, .Lfunc_end4-gpufft2rrcudel
.cfi_endproc
# -- End function
.globl gpufft2cudel # -- Begin function gpufft2cudel
.p2align 4, 0x90
.type gpufft2cudel,@function
gpufft2cudel: # @gpufft2cudel
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq _ZL5plany(%rip), %rdi
callq hipfftDestroy
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .LBB5_1
# %bb.3:
movq _ZL6planyn(%rip), %rdi
callq hipfftDestroy
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .LBB5_4
# %bb.5:
popq %rax
.cfi_def_cfa_offset 8
retq
.LBB5_1:
.cfi_def_cfa_offset 16
movl $.L.str.10, %edi
jmp .LBB5_2
.LBB5_4:
movl $.L.str.11, %edi
.LBB5_2:
movl %eax, %esi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end5:
.size gpufft2cudel, .Lfunc_end5-gpufft2cudel
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function gpufft2rrcu
.LCPI6_0:
.long 0x3f800000 # float 1
.text
.globl gpufft2rrcu
.p2align 4, 0x90
.type gpufft2rrcu,@function
gpufft2rrcu: # @gpufft2rrcu
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %r14
movl $1, %r15d
movl $1, %ebx
# kill: def $cl killed $cl killed $ecx
shlq %cl, %rbx
movl %ebx, %r12d
shrl $31, %r12d
addl %ebx, %r12d
sarl %r12d
incl %r12d
movl %r8d, %ecx
shlq %cl, %r15
leal 31(%rbx), %eax
testl %ebx, %ebx
cmovnsl %ebx, %eax
sarl $5, %eax
incl %eax
leal -1(%r15), %ecx
leal 14(%r15), %r13d
testl %ecx, %ecx
cmovnsl %ecx, %r13d
sarl $4, %r13d
incl %r13d
shlq $32, %r13
orq %rax, %r13
movq %r13, %rbp
rolq $32, %rbp
testl %edx, %edx
js .LBB6_1
# %bb.12:
je .LBB6_21
# %bb.13:
movl %r9d, %r13d
movq _ZL5plany(%rip), %rdi
movq %rsi, %rbx
movq %rsi, %rdx
movl $1, %ecx
callq hipfftExecC2C
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .LBB6_14
# %bb.15:
callq hipGetLastError
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $2176, %r8d # imm = 0x880
movq %rbp, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_17
# %bb.16:
movq %rbx, %rdi
movq %r14, %rsi
movl %r15d, %edx
movl %r12d, %ecx
movl 208(%rsp), %r8d
movl %r13d, %r9d
callq _Z25__device_stub__gpuctpose4P15HIP_vector_typeIfLj2EES1_iiii
.LBB6_17:
callq hipGetLastError
testl %eax, %eax
jne .LBB6_18
# %bb.19:
movq _ZL6planxr(%rip), %rdi
movq %r14, %rsi
movq %r14, %rdx
callq hipfftExecC2R
movl %eax, _ZL4cfrc(%rip)
callq hipDeviceSynchronize
movl _ZL4cfrc(%rip), %esi
testl %esi, %esi
je .LBB6_21
# %bb.20:
movl $.L.str.17, %edi
jmp .LBB6_4
.LBB6_1:
movl %r9d, %ebp
movq %rsi, 24(%rsp) # 8-byte Spill
movq _ZL6planrx(%rip), %rdi
movq %r14, %rsi
movq %r14, %rdx
callq hipfftExecR2C
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .LBB6_2
# %bb.5:
callq hipGetLastError
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $2176, %r8d # imm = 0x880
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_7
# %bb.6:
cvtsi2ss %ebx, %xmm0
cvtsi2ss %r15d, %xmm1
mulss %xmm0, %xmm1
movss .LCPI6_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss %xmm1, %xmm0
movq %r14, 88(%rsp)
movq 24(%rsp), %rax # 8-byte Reload
movq %rax, 80(%rsp)
movss %xmm0, 20(%rsp)
movl %r12d, 16(%rsp)
movl %r15d, 12(%rsp)
movl %ebp, 8(%rsp)
movl 208(%rsp), %eax
movl %eax, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11gpusctpose4P15HIP_vector_typeIfLj2EES1_fiiii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_7:
callq hipGetLastError
testl %eax, %eax
jne .LBB6_8
# %bb.10:
movq _ZL5plany(%rip), %rdi
movq 24(%rsp), %rdx # 8-byte Reload
movq %rdx, %rsi
movl $-1, %ecx
callq hipfftExecC2C
movl %eax, _ZL4cfrc(%rip)
callq hipDeviceSynchronize
movl _ZL4cfrc(%rip), %esi
testl %esi, %esi
jne .LBB6_11
.LBB6_21:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_14:
.cfi_def_cfa_offset 208
movl $.L.str.15, %edi
jmp .LBB6_3
.LBB6_18:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.16, %edi
jmp .LBB6_9
.LBB6_2:
movl $.L.str.12, %edi
.LBB6_3:
movl %eax, %esi
jmp .LBB6_4
.LBB6_8:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.13, %edi
.LBB6_9:
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB6_11:
movl $.L.str.14, %edi
.LBB6_4:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end6:
.size gpufft2rrcu, .Lfunc_end6-gpufft2rrcu
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function gpufft2rrcun
.LCPI7_0:
.long 0x3f800000 # float 1
.text
.globl gpufft2rrcun
.p2align 4, 0x90
.type gpufft2rrcun,@function
gpufft2rrcun: # @gpufft2rrcun
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %r10
movl $1, %r12d
movl $1, %ebp
# kill: def $cl killed $cl killed $ecx
shlq %cl, %rbp
movl %ebp, %r13d
shrl $31, %r13d
addl %ebp, %r13d
sarl %r13d
incl %r13d
movl %r8d, %ecx
shlq %cl, %r12
leal 31(%rbp), %eax
testl %ebp, %ebp
cmovnsl %ebp, %eax
sarl $5, %eax
incl %eax
leal -1(%r12), %ecx
leal 14(%r12), %r15d
testl %ecx, %ecx
cmovnsl %ecx, %r15d
sarl $4, %r15d
incl %r15d
shlq $32, %r15
orq %rax, %r15
movq %r15, %rbx
rolq $32, %rbx
imull $2176, %r9d, %r14d # imm = 0x880
testl %edx, %edx
js .LBB7_1
# %bb.12:
je .LBB7_21
# %bb.13:
movl %r9d, 12(%rsp) # 4-byte Spill
movq %r10, %rbp
movq _ZL6planyn(%rip), %rdi
movq %rsi, %r15
movq %rsi, %rdx
movl $1, %ecx
callq hipfftExecC2C
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .LBB7_14
# %bb.15:
callq hipGetLastError
movslq %r14d, %r8
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_17
# %bb.16:
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movq %r15, %rdi
movq %rbp, %rsi
movl %r12d, %edx
movl %r13d, %ecx
movl 20(%rsp), %r8d # 4-byte Reload
movl 256(%rsp), %r9d
movl 248(%rsp), %eax
pushq %rax
.cfi_adjust_cfa_offset 8
callq _Z26__device_stub__gpuctpose4nP15HIP_vector_typeIfLj2EES1_iiiii
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_17:
callq hipGetLastError
testl %eax, %eax
jne .LBB7_18
# %bb.19:
movq _ZL7planxrn(%rip), %rdi
movq %rbp, %rsi
movq %rbp, %rdx
callq hipfftExecC2R
movl %eax, _ZL4cfrc(%rip)
callq hipDeviceSynchronize
movl _ZL4cfrc(%rip), %esi
testl %esi, %esi
je .LBB7_21
# %bb.20:
movl $.L.str.23, %edi
jmp .LBB7_4
.LBB7_1:
movl %r9d, 12(%rsp) # 4-byte Spill
movq %rsi, 40(%rsp) # 8-byte Spill
movq _ZL7planrxn(%rip), %rdi
movq %r10, %rsi
movq %r10, %rbx
movq %r10, %rdx
callq hipfftExecR2C
movl %eax, _ZL4cfrc(%rip)
testl %eax, %eax
jne .LBB7_2
# %bb.5:
callq hipGetLastError
movslq %r14d, %r8
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_7
# %bb.6:
cvtsi2ss %ebp, %xmm0
cvtsi2ss %r12d, %xmm1
mulss %xmm0, %xmm1
movss .LCPI7_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss %xmm1, %xmm0
movq %rbx, 104(%rsp)
movq 40(%rsp), %rax # 8-byte Reload
movq %rax, 96(%rsp)
movss %xmm0, 36(%rsp)
movl %r13d, 32(%rsp)
movl %r12d, 28(%rsp)
movl 12(%rsp), %eax # 4-byte Reload
movl %eax, 24(%rsp)
movl 240(%rsp), %eax
movl %eax, 20(%rsp)
movl 248(%rsp), %eax
movl %eax, 16(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12gpusctpose4nP15HIP_vector_typeIfLj2EES1_fiiiii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_7:
callq hipGetLastError
testl %eax, %eax
jne .LBB7_8
# %bb.10:
movq _ZL6planyn(%rip), %rdi
movq 40(%rsp), %rdx # 8-byte Reload
movq %rdx, %rsi
movl $-1, %ecx
callq hipfftExecC2C
movl %eax, _ZL4cfrc(%rip)
callq hipDeviceSynchronize
movl _ZL4cfrc(%rip), %esi
testl %esi, %esi
jne .LBB7_11
.LBB7_21:
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB7_14:
.cfi_def_cfa_offset 240
movl $.L.str.21, %edi
jmp .LBB7_3
.LBB7_18:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.22, %edi
jmp .LBB7_9
.LBB7_2:
movl $.L.str.18, %edi
.LBB7_3:
movl %eax, %esi
jmp .LBB7_4
.LBB7_8:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.19, %edi
.LBB7_9:
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB7_11:
movl $.L.str.20, %edi
.LBB7_4:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end7:
.size gpufft2rrcun, .Lfunc_end7-gpufft2rrcun
.cfi_endproc
# -- End function
.globl gpufft2rrcuinit_ # -- Begin function gpufft2rrcuinit_
.p2align 4, 0x90
.type gpufft2rrcuinit_,@function
gpufft2rrcuinit_: # @gpufft2rrcuinit_
.cfi_startproc
# %bb.0:
movl (%rdi), %edi
movl (%rsi), %esi
movl (%rdx), %edx
jmp gpufft2rrcuinit # TAILCALL
.Lfunc_end8:
.size gpufft2rrcuinit_, .Lfunc_end8-gpufft2rrcuinit_
.cfi_endproc
# -- End function
.globl gpufft2cuinit_ # -- Begin function gpufft2cuinit_
.p2align 4, 0x90
.type gpufft2cuinit_,@function
gpufft2cuinit_: # @gpufft2cuinit_
.cfi_startproc
# %bb.0:
movl (%rdi), %edi
movl (%rsi), %esi
movl (%rdx), %edx
jmp gpufft2cuinit # TAILCALL
.Lfunc_end9:
.size gpufft2cuinit_, .Lfunc_end9-gpufft2cuinit_
.cfi_endproc
# -- End function
.globl gpufft2rrcudel_ # -- Begin function gpufft2rrcudel_
.p2align 4, 0x90
.type gpufft2rrcudel_,@function
gpufft2rrcudel_: # @gpufft2rrcudel_
.cfi_startproc
# %bb.0:
jmp gpufft2rrcudel # TAILCALL
.Lfunc_end10:
.size gpufft2rrcudel_, .Lfunc_end10-gpufft2rrcudel_
.cfi_endproc
# -- End function
.globl gpufft2cudel_ # -- Begin function gpufft2cudel_
.p2align 4, 0x90
.type gpufft2cudel_,@function
gpufft2cudel_: # @gpufft2cudel_
.cfi_startproc
# %bb.0:
jmp gpufft2cudel # TAILCALL
.Lfunc_end11:
.size gpufft2cudel_, .Lfunc_end11-gpufft2cudel_
.cfi_endproc
# -- End function
.globl gpufft2rrcu_ # -- Begin function gpufft2rrcu_
.p2align 4, 0x90
.type gpufft2rrcu_,@function
gpufft2rrcu_: # @gpufft2rrcu_
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq 16(%rsp), %rax
movq (%rdi), %rdi
movq (%rsi), %rsi
movl (%rdx), %edx
movl (%rcx), %ecx
movl (%r8), %r8d
movl (%r9), %r9d
movl (%rax), %eax
movl %eax, (%rsp)
callq gpufft2rrcu
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end12:
.size gpufft2rrcu_, .Lfunc_end12-gpufft2rrcu_
.cfi_endproc
# -- End function
.globl gpufft2rrcun_ # -- Begin function gpufft2rrcun_
.p2align 4, 0x90
.type gpufft2rrcun_,@function
gpufft2rrcun_: # @gpufft2rrcun_
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq 24(%rsp), %rax
movq 16(%rsp), %r10
movq (%rdi), %rdi
movq (%rsi), %rsi
movl (%rdx), %edx
movl (%rcx), %ecx
movl (%r8), %r8d
movl (%r9), %r9d
movl (%r10), %r10d
movl (%rax), %eax
pushq %rax
.cfi_adjust_cfa_offset 8
pushq %r10
.cfi_adjust_cfa_offset 8
callq gpufft2rrcun
addq $16, %rsp
.cfi_adjust_cfa_offset -16
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end13:
.size gpufft2rrcun_, .Lfunc_end13-gpufft2rrcun_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB14_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB14_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11gpusctpose4P15HIP_vector_typeIfLj2EES1_fiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12gpusctpose4nP15HIP_vector_typeIfLj2EES1_fiiiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end14:
.size __hip_module_ctor, .Lfunc_end14-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB15_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB15_2:
retq
.Lfunc_end15:
.size __hip_module_dtor, .Lfunc_end15-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11gpusctpose4P15HIP_vector_typeIfLj2EES1_fiiii,@object # @_Z11gpusctpose4P15HIP_vector_typeIfLj2EES1_fiiii
.section .rodata,"a",@progbits
.globl _Z11gpusctpose4P15HIP_vector_typeIfLj2EES1_fiiii
.p2align 3, 0x0
_Z11gpusctpose4P15HIP_vector_typeIfLj2EES1_fiiii:
.quad _Z26__device_stub__gpusctpose4P15HIP_vector_typeIfLj2EES1_fiiii
.size _Z11gpusctpose4P15HIP_vector_typeIfLj2EES1_fiiii, 8
.type _Z12gpusctpose4nP15HIP_vector_typeIfLj2EES1_fiiiii,@object # @_Z12gpusctpose4nP15HIP_vector_typeIfLj2EES1_fiiiii
.globl _Z12gpusctpose4nP15HIP_vector_typeIfLj2EES1_fiiiii
.p2align 3, 0x0
_Z12gpusctpose4nP15HIP_vector_typeIfLj2EES1_fiiiii:
.quad _Z27__device_stub__gpusctpose4nP15HIP_vector_typeIfLj2EES1_fiiiii
.size _Z12gpusctpose4nP15HIP_vector_typeIfLj2EES1_fiiiii, 8
.type _ZL6planrx,@object # @_ZL6planrx
.local _ZL6planrx
.comm _ZL6planrx,8,8
.type _ZL4cfrc,@object # @_ZL4cfrc
.local _ZL4cfrc
.comm _ZL4cfrc,4,4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "hipfftPlan1d planrx error=%d\n"
.size .L.str, 30
.type _ZL6planxr,@object # @_ZL6planxr
.local _ZL6planxr
.comm _ZL6planxr,8,8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipfftPlan1d planxr error=%d\n"
.size .L.str.1, 30
.type _ZL7planrxn,@object # @_ZL7planrxn
.local _ZL7planrxn
.comm _ZL7planrxn,8,8
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipfftPlan1d planrxn error=%d\n"
.size .L.str.2, 31
.type _ZL7planxrn,@object # @_ZL7planxrn
.local _ZL7planxrn
.comm _ZL7planxrn,8,8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipfftPlan1d planxrn error=%d\n"
.size .L.str.3, 31
.type _ZL5plany,@object # @_ZL5plany
.local _ZL5plany
.comm _ZL5plany,8,8
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipfftPlan1d plany error=%d\n"
.size .L.str.4, 29
.type _ZL6planyn,@object # @_ZL6planyn
.local _ZL6planyn
.comm _ZL6planyn,8,8
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipfftPlan1d planyn error=%d\n"
.size .L.str.5, 30
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipfftDestroy planrx error=%d\n"
.size .L.str.6, 31
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipfftDestroy planxr error=%d\n"
.size .L.str.7, 31
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "hipfftDestroy planrxn error=%d\n"
.size .L.str.8, 32
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "hipfftDestroy planxrn error=%d\n"
.size .L.str.9, 32
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "hipfftDestroy plany error=%d\n"
.size .L.str.10, 30
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "hipfftDestroy planyn error=%d\n"
.size .L.str.11, 31
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "cufftExecR2C(-1) planrx error=%d\n"
.size .L.str.12, 34
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "gpusctpose4 error=%d:%s\n"
.size .L.str.13, 25
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "cufftExecC2C(-1) plany error=%d\n"
.size .L.str.14, 33
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "cufftExecC2C(1) plany error=%d\n"
.size .L.str.15, 32
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "gpuctpose4 error=%d:%s\n"
.size .L.str.16, 24
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "cufftExecC2R(1) planxr error=%d\n"
.size .L.str.17, 33
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "cufftExecR2C(-1) planrxn error=%d\n"
.size .L.str.18, 35
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "gpusctpose4n error=%d:%s\n"
.size .L.str.19, 26
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "cufftExecC2C(-1) planyn error=%d\n"
.size .L.str.20, 34
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "cufftExecC2C(1) planyn error=%d\n"
.size .L.str.21, 33
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "gpuctpose4n error=%d:%s\n"
.size .L.str.22, 25
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "cufftExecC2R(1) planxrn error=%d\n"
.size .L.str.23, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11gpusctpose4P15HIP_vector_typeIfLj2EES1_fiiii"
.size .L__unnamed_1, 49
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12gpusctpose4nP15HIP_vector_typeIfLj2EES1_fiiiii"
.size .L__unnamed_2, 51
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__gpusctpose4P15HIP_vector_typeIfLj2EES1_fiiii
.addrsig_sym _Z27__device_stub__gpusctpose4nP15HIP_vector_typeIfLj2EES1_fiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11gpusctpose4P15HIP_vector_typeIfLj2EES1_fiiii
.addrsig_sym _Z12gpusctpose4nP15HIP_vector_typeIfLj2EES1_fiiiii
.addrsig_sym _ZL6planrx
.addrsig_sym _ZL6planxr
.addrsig_sym _ZL7planrxn
.addrsig_sym _ZL7planxrn
.addrsig_sym _ZL5plany
.addrsig_sym _ZL6planyn
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
// VectorAdd.cu
#include <stdio.h>
#include <cuda.h> 2
#include <stdlib.h>
#define N 10 // size of vectors
#define B 1 // blocks in the grid
#define T 10 // threads in a block
__global__ void add (int *a,int *b, int *c) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < N) {
c[tid] = a[tid]+b[tid];
}
}
int main(void) {
int a[N],b[N],c[N];
int *dev_a, *dev_b, *dev_c;
cudaMalloc((void**)&dev_a,N * sizeof(int));
cudaMalloc((void**)&dev_b,N * sizeof(int));
cudaMalloc((void**)&dev_c,N * sizeof(int));
for (int i=0;i<N;i++) {
a[i] = i;
b[i] = i*1;
}
cudaMemcpy(dev_a, a , N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b , N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_c, c , N*sizeof(int),cudaMemcpyHostToDevice);
add<<<B,T>>>(dev_a,dev_b,dev_c);
cudaMemcpy(c,dev_c,N*sizeof(int),cudaMemcpyDeviceToHost);
for (int i=0;i<N;i++) {
printf("%d+%d=%d\n",a[i],b[i],c[i]);
}
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return 0;
}
|
code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0x9, PT ; /* 0x000000090600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
// VectorAdd.cu
#include <stdio.h>
#include <cuda.h> 2
#include <stdlib.h>
#define N 10 // size of vectors
#define B 1 // blocks in the grid
#define T 10 // threads in a block
__global__ void add (int *a,int *b, int *c) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < N) {
c[tid] = a[tid]+b[tid];
}
}
int main(void) {
int a[N],b[N],c[N];
int *dev_a, *dev_b, *dev_c;
cudaMalloc((void**)&dev_a,N * sizeof(int));
cudaMalloc((void**)&dev_b,N * sizeof(int));
cudaMalloc((void**)&dev_c,N * sizeof(int));
for (int i=0;i<N;i++) {
a[i] = i;
b[i] = i*1;
}
cudaMemcpy(dev_a, a , N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b , N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_c, c , N*sizeof(int),cudaMemcpyHostToDevice);
add<<<B,T>>>(dev_a,dev_b,dev_c);
cudaMemcpy(c,dev_c,N*sizeof(int),cudaMemcpyDeviceToHost);
for (int i=0;i<N;i++) {
printf("%d+%d=%d\n",a[i],b[i],c[i]);
}
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return 0;
}
|
.file "tmpxft_00022397_00000000-6_VectorAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d+%d=%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $200, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movl %eax, 48(%rsp,%rax,4)
movl %eax, 96(%rsp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L12
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 144(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 144(%rsp), %rdi
movl $2, %ecx
movl $40, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movl 96(%rsp,%rbx), %ecx
movl 48(%rsp,%rbx), %edx
movl 144(%rsp,%rbx), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L14
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
// VectorAdd.cu
#include <stdio.h>
#include <cuda.h> 2
#include <stdlib.h>
#define N 10 // size of vectors
#define B 1 // blocks in the grid
#define T 10 // threads in a block
__global__ void add (int *a,int *b, int *c) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < N) {
c[tid] = a[tid]+b[tid];
}
}
int main(void) {
int a[N],b[N],c[N];
int *dev_a, *dev_b, *dev_c;
cudaMalloc((void**)&dev_a,N * sizeof(int));
cudaMalloc((void**)&dev_b,N * sizeof(int));
cudaMalloc((void**)&dev_c,N * sizeof(int));
for (int i=0;i<N;i++) {
a[i] = i;
b[i] = i*1;
}
cudaMemcpy(dev_a, a , N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b , N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_c, c , N*sizeof(int),cudaMemcpyHostToDevice);
add<<<B,T>>>(dev_a,dev_b,dev_c);
cudaMemcpy(c,dev_c,N*sizeof(int),cudaMemcpyDeviceToHost);
for (int i=0;i<N;i++) {
printf("%d+%d=%d\n",a[i],b[i],c[i]);
}
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return 0;
}
|
// VectorAdd.cu
#include <stdio.h>
#include <hip/hip_runtime.h> 2
#include <stdlib.h>
#define N 10 // size of vectors
#define B 1 // blocks in the grid
#define T 10 // threads in a block
__global__ void add (int *a,int *b, int *c) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < N) {
c[tid] = a[tid]+b[tid];
}
}
int main(void) {
int a[N],b[N],c[N];
int *dev_a, *dev_b, *dev_c;
hipMalloc((void**)&dev_a,N * sizeof(int));
hipMalloc((void**)&dev_b,N * sizeof(int));
hipMalloc((void**)&dev_c,N * sizeof(int));
for (int i=0;i<N;i++) {
a[i] = i;
b[i] = i*1;
}
hipMemcpy(dev_a, a , N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_b, b , N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_c, c , N*sizeof(int),hipMemcpyHostToDevice);
add<<<B,T>>>(dev_a,dev_b,dev_c);
hipMemcpy(c,dev_c,N*sizeof(int),hipMemcpyDeviceToHost);
for (int i=0;i<N;i++) {
printf("%d+%d=%d\n",a[i],b[i],c[i]);
}
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
// VectorAdd.cu
#include <stdio.h>
#include <hip/hip_runtime.h> 2
#include <stdlib.h>
#define N 10 // size of vectors
#define B 1 // blocks in the grid
#define T 10 // threads in a block
__global__ void add (int *a,int *b, int *c) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < N) {
c[tid] = a[tid]+b[tid];
}
}
int main(void) {
int a[N],b[N],c[N];
int *dev_a, *dev_b, *dev_c;
hipMalloc((void**)&dev_a,N * sizeof(int));
hipMalloc((void**)&dev_b,N * sizeof(int));
hipMalloc((void**)&dev_c,N * sizeof(int));
for (int i=0;i<N;i++) {
a[i] = i;
b[i] = i*1;
}
hipMemcpy(dev_a, a , N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_b, b , N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_c, c , N*sizeof(int),hipMemcpyHostToDevice);
add<<<B,T>>>(dev_a,dev_b,dev_c);
hipMemcpy(c,dev_c,N*sizeof(int),hipMemcpyDeviceToHost);
for (int i=0;i<N;i++) {
printf("%d+%d=%d\n",a[i],b[i],c[i]);
}
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 10, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
// VectorAdd.cu
#include <stdio.h>
#include <hip/hip_runtime.h> 2
#include <stdlib.h>
#define N 10 // size of vectors
#define B 1 // blocks in the grid
#define T 10 // threads in a block
__global__ void add (int *a,int *b, int *c) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < N) {
c[tid] = a[tid]+b[tid];
}
}
int main(void) {
int a[N],b[N],c[N];
int *dev_a, *dev_b, *dev_c;
hipMalloc((void**)&dev_a,N * sizeof(int));
hipMalloc((void**)&dev_b,N * sizeof(int));
hipMalloc((void**)&dev_c,N * sizeof(int));
for (int i=0;i<N;i++) {
a[i] = i;
b[i] = i*1;
}
hipMemcpy(dev_a, a , N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_b, b , N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_c, c , N*sizeof(int),hipMemcpyHostToDevice);
add<<<B,T>>>(dev_a,dev_b,dev_c);
hipMemcpy(c,dev_c,N*sizeof(int),hipMemcpyDeviceToHost);
for (int i=0;i<N;i++) {
printf("%d+%d=%d\n",a[i],b[i],c[i]);
}
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
}
|
.text
.file "VectorAdd.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $272, %rsp # imm = 0x110
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -16
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 224(%rsp,%rax,4)
movl %eax, 176(%rsp,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
leaq 224(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 176(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
leaq 128(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 128(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 224(%rsp,%rbx,4), %esi
movl 176(%rsp,%rbx,4), %edx
movl 128(%rsp,%rbx,4), %ecx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_5
# %bb.6:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $272, %rsp # imm = 0x110
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d+%d=%d\n"
.size .L.str, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0x9, PT ; /* 0x000000090600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 10, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00022397_00000000-6_VectorAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d+%d=%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $200, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movl %eax, 48(%rsp,%rax,4)
movl %eax, 96(%rsp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L12
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 144(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 144(%rsp), %rdi
movl $2, %ecx
movl $40, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movl 96(%rsp,%rbx), %ecx
movl 48(%rsp,%rbx), %edx
movl 144(%rsp,%rbx), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L14
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "VectorAdd.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $272, %rsp # imm = 0x110
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -16
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 224(%rsp,%rax,4)
movl %eax, 176(%rsp,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
leaq 224(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 176(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
leaq 128(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 128(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 224(%rsp,%rbx,4), %esi
movl 176(%rsp,%rbx,4), %edx
movl 128(%rsp,%rbx,4), %ecx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_5
# %bb.6:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $272, %rsp # imm = 0x110
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d+%d=%d\n"
.size .L.str, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <math.h>
#include <cuda.h>
__host__ void checkCudaState(cudaError_t& cudaState,const char *message){
/* it will print an error message if there is */
if(cudaState != cudaSuccess) printf("%s",message);
}
__device__ void swap(int *points,uint lowIndex,uint upIndex){
/* it will swap two points */
int aux = points[lowIndex];
points[lowIndex] = points[upIndex];
points[upIndex] = aux;
}
__global__ void sort(int *points,uint phase,uint n){
/* it will sort with points array with respect to phase*/
uint ti = blockIdx.x*blockDim.x+threadIdx.x;
if(ti >= n || ti == 0) return;
if(ti%phase == 0){ // multiplier phase
uint top = ti, lower = (top - phase) + 1;
uint middle = lower + phase/2;
uint lowG1 = lower, lowG2 = middle, topG1 = middle-1, topG2 = top;
while(true){
if(lowG1 > topG1 && lowG2 > topG2) break;
// --------------------- case 1 ---------------------
if(lowG1 <= topG1 && lowG2 <= topG2){
if(points[lowG1] > points[lowG2]){
swap(points,lowG1,lowG2);
lowG2++;
}
else lowG1++;
}
// --------------------- case 2 ---------------------
else if(lowG1 < topG1 && lowG2 > topG2){
uint next = lowG1 + 1;
if(points[lowG1] > points[next])
swap(points,lowG1,next);
lowG1++;
}
// --------------------- case 3 ---------------------
else if(lowG2 < topG2 && lowG1 > topG1){
uint next = lowG2 + 1;
if(points[lowG2] > points[next])
swap(points,lowG2,next);
lowG2++;
}
else if(lowG1 == topG1)
lowG1++;
else if(lowG2 == topG2)
lowG2++;
}
}
}
__host__ void fill(int *points,size_t n){
/* it will fill points array */
for(size_t i=0; i<n; i++)
points[i] = n-i;
}
__host__ void show(int* points,size_t n){
/* it will show points array */
for(size_t i=0; i<n; i++)
printf("%d ",points[i]);
printf("\n\n");
}
int main(int argc, char const *argv[]) {
size_t items = 2049;
size_t size = items*sizeof(int);
cudaError_t cudaState = cudaSuccess;
int *h_points = NULL, *d_points = NULL, *h_result = NULL;
h_points = (int*)malloc(size);
h_result = (int*)malloc(size);
fill(h_points,items);
cudaState = cudaMalloc((void**)&d_points,size);
checkCudaState(cudaState,"Impossible allocate data\n");
if(d_points != NULL){
cudaState = cudaMemcpy(d_points,h_points,size,cudaMemcpyHostToDevice);
checkCudaState(cudaState,"Impossible copy data from host to device\n");
show(h_points,items);
dim3 blockSize(1024,1,1);
dim3 gridSize((int)(ceil(items/1024.0)),1,1);
uint i = 1;
while(pow(2,i) <= items){
sort<<<gridSize,blockSize>>>(d_points,pow(2,i),items);
cudaDeviceSynchronize();
i++;
}
cudaState = cudaMemcpy(h_result,d_points,size,cudaMemcpyDeviceToHost);
checkCudaState(cudaState,"Impossible copy data from device to host\n");
show(h_result,items);
}
if(h_points != NULL) free(h_points);
if(h_result != NULL) free(h_result);
if(d_points != NULL) cudaFree(d_points);
return 0;
}
|
code for sm_80
Function : _Z4sortPijj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.EQ.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0000702670 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ I2F.U32.RP R4, c[0x0][0x168] ; /* 0x00005a0000047b06 */
/* 0x000e220000209000 */
/*0080*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fce0003f25070 */
/*0090*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00a0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00d0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*00e0*/ IMAD R5, R5, c[0x0][0x168], RZ ; /* 0x00005a0005057a24 */
/* 0x000fc800078e02ff */
/*00f0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*0100*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*0110*/ IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a03 */
/*0120*/ IMAD R3, R3, c[0x0][0x168], R0 ; /* 0x00005a0003037a24 */
/* 0x000fca00078e0200 */
/*0130*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fda0003f06070 */
/*0140*/ @P0 IADD3 R3, R3, -c[0x0][0x168], RZ ; /* 0x80005a0003030a10 */
/* 0x000fc80007ffe0ff */
/*0150*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fda0003f06070 */
/*0160*/ @P0 IADD3 R3, R3, -c[0x0][0x168], RZ ; /* 0x80005a0003030a10 */
/* 0x000fe40007ffe0ff */
/*0170*/ @!P1 LOP3.LUT R3, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff039a12 */
/* 0x000fc800078e33ff */
/*0180*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0190*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01a0*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000800 */
/*01b0*/ IADD3 R2, R0, -c[0x0][0x168], RZ ; /* 0x80005a0000027a10 */
/* 0x000fe20007ffe0ff */
/*01c0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc60008011604 */
/*01d0*/ IADD3 R7, R2, 0x1, RZ ; /* 0x0000000102077810 */
/* 0x000fc60007ffe0ff */
/*01e0*/ IADD3 R6, R2, UR4, RZ ; /* 0x0000000402067c10 */
/* 0x000fe4000fffe0ff */
/*01f0*/ IADD3 R9, R7.reuse, UR4, RZ ; /* 0x0000000407097c10 */
/* 0x040fe2000fffe0ff */
/*0200*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0210*/ ISETP.GT.U32.AND P2, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x000fe40003f44070 */
/*0220*/ ISETP.GT.U32.AND P0, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fe40003f04070 */
/*0230*/ ISETP.GT.U32.AND P1, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x000fd60003f24070 */
/*0240*/ @P0 EXIT P2 ; /* 0x000000000000094d */
/* 0x000fea0001000000 */
/*0250*/ ISETP.GT.U32.AND P2, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fe20003f44070 */
/*0260*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x001fe200078e00ff */
/*0270*/ ISETP.LE.U32.AND P3, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x000fe20003f63070 */
/*0280*/ BSSY B0, 0x540 ; /* 0x000002b000007945 */
/* 0x000fe40003800000 */
/*0290*/ IMAD.WIDE.U32 R2, R9, R8, c[0x0][0x160] ; /* 0x0000580009027625 */
/* 0x000fc800078e0008 */
/*02a0*/ IMAD.WIDE.U32 R4, R7, R8, c[0x0][0x160] ; /* 0x0000580007047625 */
/* 0x000fcc00078e0008 */
/*02b0*/ @!P2 BRA P3, 0x4c0 ; /* 0x000002000000a947 */
/* 0x000fea0001800000 */
/*02c0*/ ISETP.LT.U32.AND P2, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x000fda0003f41070 */
/*02d0*/ @P0 BRA P2, 0x430 ; /* 0x0000015000000947 */
/* 0x000fea0001000000 */
/*02e0*/ ISETP.LT.U32.AND P0, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fda0003f01070 */
/*02f0*/ @P1 BRA P0, 0x3a0 ; /* 0x000000a000001947 */
/* 0x000fea0000000000 */
/*0300*/ ISETP.NE.AND P0, PT, R7.reuse, R6.reuse, PT ; /* 0x000000060700720c */
/* 0x0c0fe40003f05270 */
/*0310*/ ISETP.NE.AND P1, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x000fe40003f25270 */
/*0320*/ ISETP.EQ.AND P0, PT, R9, R0, P0 ; /* 0x000000000900720c */
/* 0x000fe40000702270 */
/*0330*/ IADD3 R2, R7, 0x1, RZ ; /* 0x0000000107027810 */
/* 0x000fe40007ffe0ff */
/*0340*/ IADD3 R3, R9, 0x1, RZ ; /* 0x0000000109037810 */
/* 0x000fce0007ffe0ff */
/*0350*/ @P1 IMAD.MOV R2, RZ, RZ, R7 ; /* 0x000000ffff021224 */
/* 0x000fe400078e0207 */
/*0360*/ @!P0 IMAD.MOV R3, RZ, RZ, R9 ; /* 0x000000ffff038224 */
/* 0x000fe400078e0209 */
/*0370*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0002 */
/*0380*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0003 */
/*0390*/ BRA 0x530 ; /* 0x0000019000007947 */
/* 0x000fea0003800000 */
/*03a0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fca0007ffe0ff */
/*03b0*/ IMAD.WIDE.U32 R4, R8, R9, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x000fe400078e0009 */
/*03c0*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea4000c1e1900 */
/*03e0*/ ISETP.GT.AND P0, PT, R8, R11, PT ; /* 0x0000000b0800720c */
/* 0x004fda0003f04270 */
/*03f0*/ @!P0 BRA 0x530 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0400*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*0410*/ STG.E [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0001e2000c101904 */
/*0420*/ BRA 0x530 ; /* 0x0000010000007947 */
/* 0x000fea0003800000 */
/*0430*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fca0007ffe0ff */
/*0440*/ IMAD.WIDE.U32 R2, R8, R7, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x000fe400078e0007 */
/*0450*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1900 */
/*0460*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea4000c1e1900 */
/*0470*/ ISETP.GT.AND P0, PT, R8, R11, PT ; /* 0x0000000b0800720c */
/* 0x004fda0003f04270 */
/*0480*/ @!P0 BRA 0x530 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*0490*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e8000c101904 */
/*04a0*/ STG.E [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0001e2000c101904 */
/*04b0*/ BRA 0x530 ; /* 0x0000007000007947 */
/* 0x000fea0003800000 */
/*04c0*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea8000c1e1900 */
/*04d0*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea4000c1e1900 */
/*04e0*/ ISETP.GT.AND P0, PT, R11, R8, PT ; /* 0x000000080b00720c */
/* 0x004fda0003f04270 */
/*04f0*/ @P0 STG.E [R4.64], R8 ; /* 0x0000000804000986 */
/* 0x0001e2000c101904 */
/*0500*/ @!P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107078810 */
/* 0x000fe40007ffe0ff */
/*0510*/ @P0 IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109090810 */
/* 0x000fe20007ffe0ff */
/*0520*/ @P0 STG.E [R2.64], R11 ; /* 0x0000000b02000986 */
/* 0x0001e8000c101904 */
/*0530*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0540*/ ISETP.GT.U32.AND P0, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fe40003f04070 */
/*0550*/ ISETP.GT.U32.AND P1, PT, R7.reuse, R6.reuse, PT ; /* 0x000000060700720c */
/* 0x0c0fe40003f24070 */
/*0560*/ ISETP.GT.U32.AND P2, PT, R7, R6, P0 ; /* 0x000000060700720c */
/* 0x000fda0000744070 */
/*0570*/ @!P2 BRA 0x250 ; /* 0xfffffcd00000a947 */
/* 0x000fea000383ffff */
/*0580*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0590*/ BRA 0x590; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <math.h>
#include <cuda.h>
__host__ void checkCudaState(cudaError_t& cudaState,const char *message){
/* it will print an error message if there is */
if(cudaState != cudaSuccess) printf("%s",message);
}
__device__ void swap(int *points,uint lowIndex,uint upIndex){
/* it will swap two points */
int aux = points[lowIndex];
points[lowIndex] = points[upIndex];
points[upIndex] = aux;
}
__global__ void sort(int *points,uint phase,uint n){
/* it will sort with points array with respect to phase*/
uint ti = blockIdx.x*blockDim.x+threadIdx.x;
if(ti >= n || ti == 0) return;
if(ti%phase == 0){ // multiplier phase
uint top = ti, lower = (top - phase) + 1;
uint middle = lower + phase/2;
uint lowG1 = lower, lowG2 = middle, topG1 = middle-1, topG2 = top;
while(true){
if(lowG1 > topG1 && lowG2 > topG2) break;
// --------------------- case 1 ---------------------
if(lowG1 <= topG1 && lowG2 <= topG2){
if(points[lowG1] > points[lowG2]){
swap(points,lowG1,lowG2);
lowG2++;
}
else lowG1++;
}
// --------------------- case 2 ---------------------
else if(lowG1 < topG1 && lowG2 > topG2){
uint next = lowG1 + 1;
if(points[lowG1] > points[next])
swap(points,lowG1,next);
lowG1++;
}
// --------------------- case 3 ---------------------
else if(lowG2 < topG2 && lowG1 > topG1){
uint next = lowG2 + 1;
if(points[lowG2] > points[next])
swap(points,lowG2,next);
lowG2++;
}
else if(lowG1 == topG1)
lowG1++;
else if(lowG2 == topG2)
lowG2++;
}
}
}
__host__ void fill(int *points,size_t n){
/* it will fill points array */
for(size_t i=0; i<n; i++)
points[i] = n-i;
}
__host__ void show(int* points,size_t n){
/* it will show points array */
for(size_t i=0; i<n; i++)
printf("%d ",points[i]);
printf("\n\n");
}
int main(int argc, char const *argv[]) {
size_t items = 2049;
size_t size = items*sizeof(int);
cudaError_t cudaState = cudaSuccess;
int *h_points = NULL, *d_points = NULL, *h_result = NULL;
h_points = (int*)malloc(size);
h_result = (int*)malloc(size);
fill(h_points,items);
cudaState = cudaMalloc((void**)&d_points,size);
checkCudaState(cudaState,"Impossible allocate data\n");
if(d_points != NULL){
cudaState = cudaMemcpy(d_points,h_points,size,cudaMemcpyHostToDevice);
checkCudaState(cudaState,"Impossible copy data from host to device\n");
show(h_points,items);
dim3 blockSize(1024,1,1);
dim3 gridSize((int)(ceil(items/1024.0)),1,1);
uint i = 1;
while(pow(2,i) <= items){
sort<<<gridSize,blockSize>>>(d_points,pow(2,i),items);
cudaDeviceSynchronize();
i++;
}
cudaState = cudaMemcpy(h_result,d_points,size,cudaMemcpyDeviceToHost);
checkCudaState(cudaState,"Impossible copy data from device to host\n");
show(h_result,items);
}
if(h_points != NULL) free(h_points);
if(h_result != NULL) free(h_result);
if(d_points != NULL) cudaFree(d_points);
return 0;
}
|
.file "tmpxft_000fb3e3_00000000-6_mergesort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s"
.text
.globl _Z14checkCudaStateR9cudaErrorPKc
.type _Z14checkCudaStateR9cudaErrorPKc, @function
_Z14checkCudaStateR9cudaErrorPKc:
.LFB2057:
.cfi_startproc
endbr64
cmpl $0, (%rdi)
jne .L9
ret
.L9:
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rsi, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z14checkCudaStateR9cudaErrorPKc, .-_Z14checkCudaStateR9cudaErrorPKc
.globl _Z4swapPijj
.type _Z4swapPijj, @function
_Z4swapPijj:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z4swapPijj, .-_Z4swapPijj
.globl _Z4fillPim
.type _Z4fillPim, @function
_Z4fillPim:
.LFB2059:
.cfi_startproc
endbr64
testq %rsi, %rsi
je .L12
movl $0, %eax
.L14:
movl %esi, %edx
subl %eax, %edx
movl %edx, (%rdi,%rax,4)
addq $1, %rax
cmpq %rax, %rsi
jne .L14
.L12:
ret
.cfi_endproc
.LFE2059:
.size _Z4fillPim, .-_Z4fillPim
.section .rodata.str1.1
.LC1:
.string "%d "
.LC2:
.string "\n\n"
.text
.globl _Z4showPim
.type _Z4showPim, @function
_Z4showPim:
.LFB2060:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
testq %rsi, %rsi
je .L17
movq %rdi, %r12
movq %rsi, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r13
.L18:
movl (%r12,%rbx,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbx, %rbp
jne .L18
.L17:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z4showPim, .-_Z4showPim
.globl _Z25__device_stub__Z4sortPijjPijj
.type _Z25__device_stub__Z4sortPijjPijj, @function
_Z25__device_stub__Z4sortPijjPijj:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4sortPijj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z25__device_stub__Z4sortPijjPijj, .-_Z25__device_stub__Z4sortPijjPijj
.globl _Z4sortPijj
.type _Z4sortPijj, @function
_Z4sortPijj:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z4sortPijjPijj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z4sortPijj, .-_Z4sortPijj
.section .rodata.str1.1
.LC3:
.string "Impossible allocate data\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Impossible copy data from host to device\n"
.align 8
.LC7:
.string "Impossible copy data from device to host\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movl $8196, %edi
call malloc@PLT
movq %rax, %rbp
movl $8196, %edi
call malloc@PLT
movq %rax, %r12
movl $2049, %esi
movq %rbp, %rdi
call _Z4fillPim
leaq 8(%rsp), %rdi
movl $8196, %esi
call cudaMalloc@PLT
movl %eax, 4(%rsp)
leaq 4(%rsp), %rdi
leaq .LC3(%rip), %rsi
call _Z14checkCudaStateR9cudaErrorPKc
movq 8(%rsp), %rdi
testq %rdi, %rdi
je .L30
movl $1, %ecx
movl $8196, %edx
movq %rbp, %rsi
call cudaMemcpy@PLT
movl %eax, 4(%rsp)
leaq 4(%rsp), %rdi
leaq .LC4(%rip), %rsi
call _Z14checkCudaStateR9cudaErrorPKc
movl $2049, %esi
movq %rbp, %rdi
call _Z4showPim
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $3, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, %ebx
jmp .L31
.L32:
call cudaDeviceSynchronize@PLT
addl $1, %ebx
.L31:
movl %ebx, %eax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
movapd %xmm2, %xmm1
movq %xmm2, %r14
movsd .LC5(%rip), %xmm0
call pow@PLT
movsd .LC6(%rip), %xmm3
comisd %xmm0, %xmm3
jb .L41
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl 36(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L32
movq %r14, %xmm1
movsd .LC5(%rip), %xmm0
call pow@PLT
cvttsd2siq %xmm0, %rsi
movl $2049, %edx
movq 8(%rsp), %rdi
call _Z25__device_stub__Z4sortPijjPijj
jmp .L32
.L41:
movl $2, %ecx
movl $8196, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, 4(%rsp)
leaq 4(%rsp), %rdi
leaq .LC7(%rip), %rsi
call _Z14checkCudaStateR9cudaErrorPKc
movl $2049, %esi
movq %r12, %rdi
call _Z4showPim
.L30:
testq %rbp, %rbp
je .L36
movq %rbp, %rdi
call free@PLT
.L36:
testq %r12, %r12
je .L37
movq %r12, %rdi
call free@PLT
.L37:
movq 8(%rsp), %rdi
testq %rdi, %rdi
je .L38
call cudaFree@PLT
.L38:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z4sortPijj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z4sortPijj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1073741824
.align 8
.LC6:
.long 0
.long 1084228096
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <math.h>
#include <cuda.h>
__host__ void checkCudaState(cudaError_t& cudaState,const char *message){
/* it will print an error message if there is */
if(cudaState != cudaSuccess) printf("%s",message);
}
__device__ void swap(int *points,uint lowIndex,uint upIndex){
/* it will swap two points */
int aux = points[lowIndex];
points[lowIndex] = points[upIndex];
points[upIndex] = aux;
}
__global__ void sort(int *points,uint phase,uint n){
/* it will sort with points array with respect to phase*/
uint ti = blockIdx.x*blockDim.x+threadIdx.x;
if(ti >= n || ti == 0) return;
if(ti%phase == 0){ // multiplier phase
uint top = ti, lower = (top - phase) + 1;
uint middle = lower + phase/2;
uint lowG1 = lower, lowG2 = middle, topG1 = middle-1, topG2 = top;
while(true){
if(lowG1 > topG1 && lowG2 > topG2) break;
// --------------------- case 1 ---------------------
if(lowG1 <= topG1 && lowG2 <= topG2){
if(points[lowG1] > points[lowG2]){
swap(points,lowG1,lowG2);
lowG2++;
}
else lowG1++;
}
// --------------------- case 2 ---------------------
else if(lowG1 < topG1 && lowG2 > topG2){
uint next = lowG1 + 1;
if(points[lowG1] > points[next])
swap(points,lowG1,next);
lowG1++;
}
// --------------------- case 3 ---------------------
else if(lowG2 < topG2 && lowG1 > topG1){
uint next = lowG2 + 1;
if(points[lowG2] > points[next])
swap(points,lowG2,next);
lowG2++;
}
else if(lowG1 == topG1)
lowG1++;
else if(lowG2 == topG2)
lowG2++;
}
}
}
__host__ void fill(int *points,size_t n){
/* it will fill points array */
for(size_t i=0; i<n; i++)
points[i] = n-i;
}
__host__ void show(int* points,size_t n){
/* it will show points array */
for(size_t i=0; i<n; i++)
printf("%d ",points[i]);
printf("\n\n");
}
int main(int argc, char const *argv[]) {
size_t items = 2049;
size_t size = items*sizeof(int);
cudaError_t cudaState = cudaSuccess;
int *h_points = NULL, *d_points = NULL, *h_result = NULL;
h_points = (int*)malloc(size);
h_result = (int*)malloc(size);
fill(h_points,items);
cudaState = cudaMalloc((void**)&d_points,size);
checkCudaState(cudaState,"Impossible allocate data\n");
if(d_points != NULL){
cudaState = cudaMemcpy(d_points,h_points,size,cudaMemcpyHostToDevice);
checkCudaState(cudaState,"Impossible copy data from host to device\n");
show(h_points,items);
dim3 blockSize(1024,1,1);
dim3 gridSize((int)(ceil(items/1024.0)),1,1);
uint i = 1;
while(pow(2,i) <= items){
sort<<<gridSize,blockSize>>>(d_points,pow(2,i),items);
cudaDeviceSynchronize();
i++;
}
cudaState = cudaMemcpy(h_result,d_points,size,cudaMemcpyDeviceToHost);
checkCudaState(cudaState,"Impossible copy data from device to host\n");
show(h_result,items);
}
if(h_points != NULL) free(h_points);
if(h_result != NULL) free(h_result);
if(d_points != NULL) cudaFree(d_points);
return 0;
}
|
#include <stdio.h>
#include <math.h>
#include <hip/hip_runtime.h>
__host__ void checkCudaState(hipError_t& cudaState,const char *message){
/* it will print an error message if there is */
if(cudaState != hipSuccess) printf("%s",message);
}
__device__ void swap(int *points,uint lowIndex,uint upIndex){
/* it will swap two points */
int aux = points[lowIndex];
points[lowIndex] = points[upIndex];
points[upIndex] = aux;
}
__global__ void sort(int *points,uint phase,uint n){
/* it will sort with points array with respect to phase*/
uint ti = blockIdx.x*blockDim.x+threadIdx.x;
if(ti >= n || ti == 0) return;
if(ti%phase == 0){ // multiplier phase
uint top = ti, lower = (top - phase) + 1;
uint middle = lower + phase/2;
uint lowG1 = lower, lowG2 = middle, topG1 = middle-1, topG2 = top;
while(true){
if(lowG1 > topG1 && lowG2 > topG2) break;
// --------------------- case 1 ---------------------
if(lowG1 <= topG1 && lowG2 <= topG2){
if(points[lowG1] > points[lowG2]){
swap(points,lowG1,lowG2);
lowG2++;
}
else lowG1++;
}
// --------------------- case 2 ---------------------
else if(lowG1 < topG1 && lowG2 > topG2){
uint next = lowG1 + 1;
if(points[lowG1] > points[next])
swap(points,lowG1,next);
lowG1++;
}
// --------------------- case 3 ---------------------
else if(lowG2 < topG2 && lowG1 > topG1){
uint next = lowG2 + 1;
if(points[lowG2] > points[next])
swap(points,lowG2,next);
lowG2++;
}
else if(lowG1 == topG1)
lowG1++;
else if(lowG2 == topG2)
lowG2++;
}
}
}
__host__ void fill(int *points,size_t n){
/* it will fill points array */
for(size_t i=0; i<n; i++)
points[i] = n-i;
}
__host__ void show(int* points,size_t n){
/* it will show points array */
for(size_t i=0; i<n; i++)
printf("%d ",points[i]);
printf("\n\n");
}
int main(int argc, char const *argv[]) {
size_t items = 2049;
size_t size = items*sizeof(int);
hipError_t cudaState = hipSuccess;
int *h_points = NULL, *d_points = NULL, *h_result = NULL;
h_points = (int*)malloc(size);
h_result = (int*)malloc(size);
fill(h_points,items);
cudaState = hipMalloc((void**)&d_points,size);
checkCudaState(cudaState,"Impossible allocate data\n");
if(d_points != NULL){
cudaState = hipMemcpy(d_points,h_points,size,hipMemcpyHostToDevice);
checkCudaState(cudaState,"Impossible copy data from host to device\n");
show(h_points,items);
dim3 blockSize(1024,1,1);
dim3 gridSize((int)(ceil(items/1024.0)),1,1);
uint i = 1;
while(pow(2,i) <= items){
sort<<<gridSize,blockSize>>>(d_points,pow(2,i),items);
hipDeviceSynchronize();
i++;
}
cudaState = hipMemcpy(h_result,d_points,size,hipMemcpyDeviceToHost);
checkCudaState(cudaState,"Impossible copy data from device to host\n");
show(h_result,items);
}
if(h_points != NULL) free(h_points);
if(h_result != NULL) free(h_result);
if(d_points != NULL) hipFree(d_points);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <stdio.h>
#include <math.h>
#include <hip/hip_runtime.h>
__host__ void checkCudaState(hipError_t& cudaState,const char *message){
/* it will print an error message if there is */
if(cudaState != hipSuccess) printf("%s",message);
}
__device__ void swap(int *points,uint lowIndex,uint upIndex){
/* it will swap two points */
int aux = points[lowIndex];
points[lowIndex] = points[upIndex];
points[upIndex] = aux;
}
__global__ void sort(int *points,uint phase,uint n){
/* it will sort with points array with respect to phase*/
uint ti = blockIdx.x*blockDim.x+threadIdx.x;
if(ti >= n || ti == 0) return;
if(ti%phase == 0){ // multiplier phase
uint top = ti, lower = (top - phase) + 1;
uint middle = lower + phase/2;
uint lowG1 = lower, lowG2 = middle, topG1 = middle-1, topG2 = top;
while(true){
if(lowG1 > topG1 && lowG2 > topG2) break;
// --------------------- case 1 ---------------------
if(lowG1 <= topG1 && lowG2 <= topG2){
if(points[lowG1] > points[lowG2]){
swap(points,lowG1,lowG2);
lowG2++;
}
else lowG1++;
}
// --------------------- case 2 ---------------------
else if(lowG1 < topG1 && lowG2 > topG2){
uint next = lowG1 + 1;
if(points[lowG1] > points[next])
swap(points,lowG1,next);
lowG1++;
}
// --------------------- case 3 ---------------------
else if(lowG2 < topG2 && lowG1 > topG1){
uint next = lowG2 + 1;
if(points[lowG2] > points[next])
swap(points,lowG2,next);
lowG2++;
}
else if(lowG1 == topG1)
lowG1++;
else if(lowG2 == topG2)
lowG2++;
}
}
}
__host__ void fill(int *points,size_t n){
/* it will fill points array */
for(size_t i=0; i<n; i++)
points[i] = n-i;
}
__host__ void show(int* points,size_t n){
/* it will show points array */
for(size_t i=0; i<n; i++)
printf("%d ",points[i]);
printf("\n\n");
}
int main(int argc, char const *argv[]) {
size_t items = 2049;
size_t size = items*sizeof(int);
hipError_t cudaState = hipSuccess;
int *h_points = NULL, *d_points = NULL, *h_result = NULL;
h_points = (int*)malloc(size);
h_result = (int*)malloc(size);
fill(h_points,items);
cudaState = hipMalloc((void**)&d_points,size);
checkCudaState(cudaState,"Impossible allocate data\n");
if(d_points != NULL){
cudaState = hipMemcpy(d_points,h_points,size,hipMemcpyHostToDevice);
checkCudaState(cudaState,"Impossible copy data from host to device\n");
show(h_points,items);
dim3 blockSize(1024,1,1);
dim3 gridSize((int)(ceil(items/1024.0)),1,1);
uint i = 1;
while(pow(2,i) <= items){
sort<<<gridSize,blockSize>>>(d_points,pow(2,i),items);
hipDeviceSynchronize();
i++;
}
cudaState = hipMemcpy(h_result,d_points,size,hipMemcpyDeviceToHost);
checkCudaState(cudaState,"Impossible copy data from device to host\n");
show(h_result,items);
}
if(h_points != NULL) free(h_points);
if(h_result != NULL) free(h_result);
if(d_points != NULL) hipFree(d_points);
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4sortPijj
.globl _Z4sortPijj
.p2align 8
.type _Z4sortPijj,@function
_Z4sortPijj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmp_gt_u32_e32 vcc_lo, s3, v1
v_cmp_ne_u32_e64 s2, 0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_29
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v0, s2
s_sub_i32 s3, 0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s3, v0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mul_hi_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s2
v_sub_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_29
v_subrev_nc_u32_e32 v0, s2, v1
s_lshr_b32 s2, s2, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, 1, v0
v_add_nc_u32_e32 v0, s2, v0
v_add_nc_u32_e32 v4, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e64 s4, v2, v0
v_cmp_gt_u32_e64 s5, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s4, s5
s_xor_b32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_29
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s2, 0
s_branch .LBB0_7
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
v_mov_b32_e32 v6, v4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v4, v6
v_mov_b32_e32 v2, v5
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_u32_e64 s4, v2, v0
v_cmp_gt_u32_e64 s5, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s4, s5
s_and_b32 s3, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, s3, s2
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_29
.LBB0_7:
s_or_b32 s3, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s3, -1
s_and_saveexec_b32 s6, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s6
s_cbranch_execz .LBB0_13
v_mov_b32_e32 v3, 0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mov_b32_e32 v5, v3
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_lshlrev_b64 v[8:9], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v9, vcc_lo
s_clause 0x1
global_load_b32 v3, v[5:6], off
global_load_b32 v9, v[7:8], off
s_waitcnt vmcnt(0)
v_cmpx_le_i32_e64 v3, v9
s_xor_b32 s6, exec_lo, s6
v_add_nc_u32_e32 v2, 1, v2
s_and_not1_saveexec_b32 s6, s6
v_add_nc_u32_e32 v4, 1, v4
s_clause 0x1
global_store_b32 v[5:6], v9, off
global_store_b32 v[7:8], v3, off
s_or_b32 exec_lo, exec_lo, s6
.LBB0_13:
s_and_not1_saveexec_b32 s3, s3
s_cbranch_execz .LBB0_6
v_cmp_ge_u32_e32 vcc_lo, v2, v0
s_xor_b32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s5, vcc_lo, s5
s_and_saveexec_b32 s6, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s5, exec_lo, s6
s_cbranch_execz .LBB0_26
v_cmp_ge_u32_e32 vcc_lo, v4, v1
s_xor_b32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s4, vcc_lo, s4
s_and_saveexec_b32 s6, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s6
s_cbranch_execz .LBB0_21
s_mov_b32 s6, exec_lo
v_cmpx_ne_u32_e64 v2, v0
s_xor_b32 s6, exec_lo, s6
v_cmp_eq_u32_e32 vcc_lo, v4, v1
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v4, vcc_lo
s_and_not1_saveexec_b32 s6, s6
v_add_nc_u32_e32 v2, 1, v2
v_mov_b32_e32 v6, v4
s_or_b32 exec_lo, exec_lo, s6
.LBB0_21:
s_and_not1_saveexec_b32 s4, s4
s_cbranch_execz .LBB0_25
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v6, 1, v4
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mov_b32_e32 v7, v5
v_lshlrev_b64 v[3:4], 2, v[4:5]
v_lshlrev_b64 v[7:8], 2, v[6:7]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
s_clause 0x1
global_load_b32 v5, v[3:4], off
global_load_b32 v9, v[7:8], off
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 v5, v9
s_clause 0x1
global_store_b32 v[3:4], v9, off
global_store_b32 v[7:8], v5, off
s_or_b32 exec_lo, exec_lo, s6
.LBB0_25:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
v_mov_b32_e32 v5, v2
.LBB0_26:
s_and_not1_saveexec_b32 s4, s5
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v3, 0
v_add_nc_u32_e32 v5, 1, v2
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mov_b32_e32 v6, v3
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[6:7], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
s_clause 0x1
global_load_b32 v8, v[2:3], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 v8, v9
s_cbranch_execz .LBB0_4
s_clause 0x1
global_store_b32 v[2:3], v9, off
global_store_b32 v[6:7], v8, off
s_branch .LBB0_4
.LBB0_29:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4sortPijj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4sortPijj, .Lfunc_end0-_Z4sortPijj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4sortPijj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4sortPijj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <stdio.h>
#include <math.h>
#include <hip/hip_runtime.h>
__host__ void checkCudaState(hipError_t& cudaState,const char *message){
/* it will print an error message if there is */
if(cudaState != hipSuccess) printf("%s",message);
}
__device__ void swap(int *points,uint lowIndex,uint upIndex){
/* it will swap two points */
int aux = points[lowIndex];
points[lowIndex] = points[upIndex];
points[upIndex] = aux;
}
__global__ void sort(int *points,uint phase,uint n){
/* it will sort with points array with respect to phase*/
uint ti = blockIdx.x*blockDim.x+threadIdx.x;
if(ti >= n || ti == 0) return;
if(ti%phase == 0){ // multiplier phase
uint top = ti, lower = (top - phase) + 1;
uint middle = lower + phase/2;
uint lowG1 = lower, lowG2 = middle, topG1 = middle-1, topG2 = top;
while(true){
if(lowG1 > topG1 && lowG2 > topG2) break;
// --------------------- case 1 ---------------------
if(lowG1 <= topG1 && lowG2 <= topG2){
if(points[lowG1] > points[lowG2]){
swap(points,lowG1,lowG2);
lowG2++;
}
else lowG1++;
}
// --------------------- case 2 ---------------------
else if(lowG1 < topG1 && lowG2 > topG2){
uint next = lowG1 + 1;
if(points[lowG1] > points[next])
swap(points,lowG1,next);
lowG1++;
}
// --------------------- case 3 ---------------------
else if(lowG2 < topG2 && lowG1 > topG1){
uint next = lowG2 + 1;
if(points[lowG2] > points[next])
swap(points,lowG2,next);
lowG2++;
}
else if(lowG1 == topG1)
lowG1++;
else if(lowG2 == topG2)
lowG2++;
}
}
}
__host__ void fill(int *points,size_t n){
/* it will fill points array */
for(size_t i=0; i<n; i++)
points[i] = n-i;
}
__host__ void show(int* points,size_t n){
/* it will show points array */
for(size_t i=0; i<n; i++)
printf("%d ",points[i]);
printf("\n\n");
}
int main(int argc, char const *argv[]) {
size_t items = 2049;
size_t size = items*sizeof(int);
hipError_t cudaState = hipSuccess;
int *h_points = NULL, *d_points = NULL, *h_result = NULL;
h_points = (int*)malloc(size);
h_result = (int*)malloc(size);
fill(h_points,items);
cudaState = hipMalloc((void**)&d_points,size);
checkCudaState(cudaState,"Impossible allocate data\n");
if(d_points != NULL){
cudaState = hipMemcpy(d_points,h_points,size,hipMemcpyHostToDevice);
checkCudaState(cudaState,"Impossible copy data from host to device\n");
show(h_points,items);
dim3 blockSize(1024,1,1);
dim3 gridSize((int)(ceil(items/1024.0)),1,1);
uint i = 1;
while(pow(2,i) <= items){
sort<<<gridSize,blockSize>>>(d_points,pow(2,i),items);
hipDeviceSynchronize();
i++;
}
cudaState = hipMemcpy(h_result,d_points,size,hipMemcpyDeviceToHost);
checkCudaState(cudaState,"Impossible copy data from device to host\n");
show(h_result,items);
}
if(h_points != NULL) free(h_points);
if(h_result != NULL) free(h_result);
if(d_points != NULL) hipFree(d_points);
return 0;
}
|
.text
.file "mergesort.hip"
.globl _Z14checkCudaStateR10hipError_tPKc # -- Begin function _Z14checkCudaStateR10hipError_tPKc
.p2align 4, 0x90
.type _Z14checkCudaStateR10hipError_tPKc,@function
_Z14checkCudaStateR10hipError_tPKc: # @_Z14checkCudaStateR10hipError_tPKc
.cfi_startproc
# %bb.0:
cmpl $0, (%rdi)
je .LBB0_1
# %bb.2:
movl $.L.str, %edi
xorl %eax, %eax
jmp printf # TAILCALL
.LBB0_1:
retq
.Lfunc_end0:
.size _Z14checkCudaStateR10hipError_tPKc, .Lfunc_end0-_Z14checkCudaStateR10hipError_tPKc
.cfi_endproc
# -- End function
.globl _Z19__device_stub__sortPijj # -- Begin function _Z19__device_stub__sortPijj
.p2align 4, 0x90
.type _Z19__device_stub__sortPijj,@function
_Z19__device_stub__sortPijj: # @_Z19__device_stub__sortPijj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4sortPijj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z19__device_stub__sortPijj, .Lfunc_end1-_Z19__device_stub__sortPijj
.cfi_endproc
# -- End function
.globl _Z4fillPim # -- Begin function _Z4fillPim
.p2align 4, 0x90
.type _Z4fillPim,@function
_Z4fillPim: # @_Z4fillPim
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB2_2
.p2align 4, 0x90
.LBB2_1: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %esi, (%rdi)
addq $4, %rdi
decq %rsi
jne .LBB2_1
.LBB2_2: # %._crit_edge
retq
.Lfunc_end2:
.size _Z4fillPim, .Lfunc_end2-_Z4fillPim
.cfi_endproc
# -- End function
.globl _Z4showPim # -- Begin function _Z4showPim
.p2align 4, 0x90
.type _Z4showPim,@function
_Z4showPim: # @_Z4showPim
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB3_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%r14,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %rbx
jne .LBB3_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB3_4: # %._crit_edge
movl $.Lstr, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end3:
.size _Z4showPim, .Lfunc_end3-_Z4showPim
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq $0, (%rsp)
movl $8196, %edi # imm = 0x2004
callq malloc
movq %rax, %r14
movl $8196, %edi # imm = 0x2004
callq malloc
movq %rax, %rbx
movl $2049, %eax # imm = 0x801
movq %r14, %rcx
.p2align 4, 0x90
.LBB4_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl %eax, (%rcx)
addq $4, %rcx
decq %rax
jne .LBB4_1
# %bb.2: # %_Z4fillPim.exit
movq %rsp, %rdi
movl $8196, %esi # imm = 0x2004
callq hipMalloc
testl %eax, %eax
je .LBB4_4
# %bb.3:
movl $.Lstr.1, %edi
callq puts@PLT
.LBB4_4: # %_Z14checkCudaStateR10hipError_tPKc.exit
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB4_18
# %bb.5:
movl $8196, %edx # imm = 0x2004
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB4_7
# %bb.6:
movl $.Lstr.2, %edi
callq puts@PLT
.LBB4_7: # %.lr.ph.i39.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_8: # %.lr.ph.i39
# =>This Inner Loop Header: Depth=1
movl (%r14,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $2049, %r15 # imm = 0x801
jne .LBB4_8
# %bb.9: # %_Z4showPim.exit
movabsq $4294967299, %r15 # imm = 0x100000003
movl $.Lstr, %edi
callq puts@PLT
movsd .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 16(%rsp) # 8-byte Spill
callq exp2@PLT
movl $2, %ebp
leaq 1021(%r15), %r12
jmp .LBB4_10
.p2align 4, 0x90
.LBB4_12: # in Loop: Header=BB4_10 Depth=1
callq hipDeviceSynchronize
movl %ebp, %eax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
callq exp2@PLT
incl %ebp
cmpl $13, %ebp
je .LBB4_13
.LBB4_10: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_12
# %bb.11: # in Loop: Header=BB4_10 Depth=1
movq (%rsp), %r13
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq exp2@PLT
cvttsd2si %xmm0, %rax
movq %r13, 72(%rsp)
movl %eax, 12(%rsp)
movl $2049, 8(%rsp) # imm = 0x801
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z4sortPijj, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_12
.LBB4_13:
movq (%rsp), %rsi
movl $8196, %edx # imm = 0x2004
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB4_15
# %bb.14:
movl $.Lstr.3, %edi
callq puts@PLT
.LBB4_15: # %.lr.ph.i43.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_16: # %.lr.ph.i43
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $2049, %r15 # imm = 0x801
jne .LBB4_16
# %bb.17: # %_Z4showPim.exit47
movl $.Lstr, %edi
callq puts@PLT
.LBB4_18:
testq %r14, %r14
je .LBB4_20
# %bb.19:
movq %r14, %rdi
callq free
.LBB4_20:
testq %rbx, %rbx
je .LBB4_22
# %bb.21:
movq %rbx, %rdi
callq free
.LBB4_22:
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB4_24
# %bb.23:
callq hipFree
.LBB4_24:
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4sortPijj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s"
.size .L.str, 3
.type _Z4sortPijj,@object # @_Z4sortPijj
.section .rodata,"a",@progbits
.globl _Z4sortPijj
.p2align 3, 0x0
_Z4sortPijj:
.quad _Z19__device_stub__sortPijj
.size _Z4sortPijj, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4sortPijj"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n"
.size .Lstr, 2
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Impossible allocate data"
.size .Lstr.1, 25
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Impossible copy data from host to device"
.size .Lstr.2, 41
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Impossible copy data from device to host"
.size .Lstr.3, 41
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__sortPijj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4sortPijj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z4sortPijj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.EQ.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0000702670 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ I2F.U32.RP R4, c[0x0][0x168] ; /* 0x00005a0000047b06 */
/* 0x000e220000209000 */
/*0080*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fce0003f25070 */
/*0090*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00a0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00d0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*00e0*/ IMAD R5, R5, c[0x0][0x168], RZ ; /* 0x00005a0005057a24 */
/* 0x000fc800078e02ff */
/*00f0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*0100*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*0110*/ IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a03 */
/*0120*/ IMAD R3, R3, c[0x0][0x168], R0 ; /* 0x00005a0003037a24 */
/* 0x000fca00078e0200 */
/*0130*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fda0003f06070 */
/*0140*/ @P0 IADD3 R3, R3, -c[0x0][0x168], RZ ; /* 0x80005a0003030a10 */
/* 0x000fc80007ffe0ff */
/*0150*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fda0003f06070 */
/*0160*/ @P0 IADD3 R3, R3, -c[0x0][0x168], RZ ; /* 0x80005a0003030a10 */
/* 0x000fe40007ffe0ff */
/*0170*/ @!P1 LOP3.LUT R3, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff039a12 */
/* 0x000fc800078e33ff */
/*0180*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0190*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01a0*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000800 */
/*01b0*/ IADD3 R2, R0, -c[0x0][0x168], RZ ; /* 0x80005a0000027a10 */
/* 0x000fe20007ffe0ff */
/*01c0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc60008011604 */
/*01d0*/ IADD3 R7, R2, 0x1, RZ ; /* 0x0000000102077810 */
/* 0x000fc60007ffe0ff */
/*01e0*/ IADD3 R6, R2, UR4, RZ ; /* 0x0000000402067c10 */
/* 0x000fe4000fffe0ff */
/*01f0*/ IADD3 R9, R7.reuse, UR4, RZ ; /* 0x0000000407097c10 */
/* 0x040fe2000fffe0ff */
/*0200*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0210*/ ISETP.GT.U32.AND P2, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x000fe40003f44070 */
/*0220*/ ISETP.GT.U32.AND P0, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fe40003f04070 */
/*0230*/ ISETP.GT.U32.AND P1, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x000fd60003f24070 */
/*0240*/ @P0 EXIT P2 ; /* 0x000000000000094d */
/* 0x000fea0001000000 */
/*0250*/ ISETP.GT.U32.AND P2, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fe20003f44070 */
/*0260*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x001fe200078e00ff */
/*0270*/ ISETP.LE.U32.AND P3, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x000fe20003f63070 */
/*0280*/ BSSY B0, 0x540 ; /* 0x000002b000007945 */
/* 0x000fe40003800000 */
/*0290*/ IMAD.WIDE.U32 R2, R9, R8, c[0x0][0x160] ; /* 0x0000580009027625 */
/* 0x000fc800078e0008 */
/*02a0*/ IMAD.WIDE.U32 R4, R7, R8, c[0x0][0x160] ; /* 0x0000580007047625 */
/* 0x000fcc00078e0008 */
/*02b0*/ @!P2 BRA P3, 0x4c0 ; /* 0x000002000000a947 */
/* 0x000fea0001800000 */
/*02c0*/ ISETP.LT.U32.AND P2, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x000fda0003f41070 */
/*02d0*/ @P0 BRA P2, 0x430 ; /* 0x0000015000000947 */
/* 0x000fea0001000000 */
/*02e0*/ ISETP.LT.U32.AND P0, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fda0003f01070 */
/*02f0*/ @P1 BRA P0, 0x3a0 ; /* 0x000000a000001947 */
/* 0x000fea0000000000 */
/*0300*/ ISETP.NE.AND P0, PT, R7.reuse, R6.reuse, PT ; /* 0x000000060700720c */
/* 0x0c0fe40003f05270 */
/*0310*/ ISETP.NE.AND P1, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x000fe40003f25270 */
/*0320*/ ISETP.EQ.AND P0, PT, R9, R0, P0 ; /* 0x000000000900720c */
/* 0x000fe40000702270 */
/*0330*/ IADD3 R2, R7, 0x1, RZ ; /* 0x0000000107027810 */
/* 0x000fe40007ffe0ff */
/*0340*/ IADD3 R3, R9, 0x1, RZ ; /* 0x0000000109037810 */
/* 0x000fce0007ffe0ff */
/*0350*/ @P1 IMAD.MOV R2, RZ, RZ, R7 ; /* 0x000000ffff021224 */
/* 0x000fe400078e0207 */
/*0360*/ @!P0 IMAD.MOV R3, RZ, RZ, R9 ; /* 0x000000ffff038224 */
/* 0x000fe400078e0209 */
/*0370*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0002 */
/*0380*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0003 */
/*0390*/ BRA 0x530 ; /* 0x0000019000007947 */
/* 0x000fea0003800000 */
/*03a0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fca0007ffe0ff */
/*03b0*/ IMAD.WIDE.U32 R4, R8, R9, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x000fe400078e0009 */
/*03c0*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea4000c1e1900 */
/*03e0*/ ISETP.GT.AND P0, PT, R8, R11, PT ; /* 0x0000000b0800720c */
/* 0x004fda0003f04270 */
/*03f0*/ @!P0 BRA 0x530 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0400*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*0410*/ STG.E [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0001e2000c101904 */
/*0420*/ BRA 0x530 ; /* 0x0000010000007947 */
/* 0x000fea0003800000 */
/*0430*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fca0007ffe0ff */
/*0440*/ IMAD.WIDE.U32 R2, R8, R7, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x000fe400078e0007 */
/*0450*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1900 */
/*0460*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea4000c1e1900 */
/*0470*/ ISETP.GT.AND P0, PT, R8, R11, PT ; /* 0x0000000b0800720c */
/* 0x004fda0003f04270 */
/*0480*/ @!P0 BRA 0x530 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*0490*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e8000c101904 */
/*04a0*/ STG.E [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0001e2000c101904 */
/*04b0*/ BRA 0x530 ; /* 0x0000007000007947 */
/* 0x000fea0003800000 */
/*04c0*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea8000c1e1900 */
/*04d0*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea4000c1e1900 */
/*04e0*/ ISETP.GT.AND P0, PT, R11, R8, PT ; /* 0x000000080b00720c */
/* 0x004fda0003f04270 */
/*04f0*/ @P0 STG.E [R4.64], R8 ; /* 0x0000000804000986 */
/* 0x0001e2000c101904 */
/*0500*/ @!P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107078810 */
/* 0x000fe40007ffe0ff */
/*0510*/ @P0 IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109090810 */
/* 0x000fe20007ffe0ff */
/*0520*/ @P0 STG.E [R2.64], R11 ; /* 0x0000000b02000986 */
/* 0x0001e8000c101904 */
/*0530*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0540*/ ISETP.GT.U32.AND P0, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fe40003f04070 */
/*0550*/ ISETP.GT.U32.AND P1, PT, R7.reuse, R6.reuse, PT ; /* 0x000000060700720c */
/* 0x0c0fe40003f24070 */
/*0560*/ ISETP.GT.U32.AND P2, PT, R7, R6, P0 ; /* 0x000000060700720c */
/* 0x000fda0000744070 */
/*0570*/ @!P2 BRA 0x250 ; /* 0xfffffcd00000a947 */
/* 0x000fea000383ffff */
/*0580*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0590*/ BRA 0x590; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4sortPijj
.globl _Z4sortPijj
.p2align 8
.type _Z4sortPijj,@function
_Z4sortPijj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmp_gt_u32_e32 vcc_lo, s3, v1
v_cmp_ne_u32_e64 s2, 0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_29
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v0, s2
s_sub_i32 s3, 0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s3, v0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mul_hi_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s2
v_sub_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_29
v_subrev_nc_u32_e32 v0, s2, v1
s_lshr_b32 s2, s2, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, 1, v0
v_add_nc_u32_e32 v0, s2, v0
v_add_nc_u32_e32 v4, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e64 s4, v2, v0
v_cmp_gt_u32_e64 s5, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s4, s5
s_xor_b32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_29
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s2, 0
s_branch .LBB0_7
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
v_mov_b32_e32 v6, v4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v4, v6
v_mov_b32_e32 v2, v5
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_u32_e64 s4, v2, v0
v_cmp_gt_u32_e64 s5, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s4, s5
s_and_b32 s3, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, s3, s2
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_29
.LBB0_7:
s_or_b32 s3, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s3, -1
s_and_saveexec_b32 s6, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s6
s_cbranch_execz .LBB0_13
v_mov_b32_e32 v3, 0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mov_b32_e32 v5, v3
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_lshlrev_b64 v[8:9], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v9, vcc_lo
s_clause 0x1
global_load_b32 v3, v[5:6], off
global_load_b32 v9, v[7:8], off
s_waitcnt vmcnt(0)
v_cmpx_le_i32_e64 v3, v9
s_xor_b32 s6, exec_lo, s6
v_add_nc_u32_e32 v2, 1, v2
s_and_not1_saveexec_b32 s6, s6
v_add_nc_u32_e32 v4, 1, v4
s_clause 0x1
global_store_b32 v[5:6], v9, off
global_store_b32 v[7:8], v3, off
s_or_b32 exec_lo, exec_lo, s6
.LBB0_13:
s_and_not1_saveexec_b32 s3, s3
s_cbranch_execz .LBB0_6
v_cmp_ge_u32_e32 vcc_lo, v2, v0
s_xor_b32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s5, vcc_lo, s5
s_and_saveexec_b32 s6, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s5, exec_lo, s6
s_cbranch_execz .LBB0_26
v_cmp_ge_u32_e32 vcc_lo, v4, v1
s_xor_b32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s4, vcc_lo, s4
s_and_saveexec_b32 s6, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s6
s_cbranch_execz .LBB0_21
s_mov_b32 s6, exec_lo
v_cmpx_ne_u32_e64 v2, v0
s_xor_b32 s6, exec_lo, s6
v_cmp_eq_u32_e32 vcc_lo, v4, v1
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v4, vcc_lo
s_and_not1_saveexec_b32 s6, s6
v_add_nc_u32_e32 v2, 1, v2
v_mov_b32_e32 v6, v4
s_or_b32 exec_lo, exec_lo, s6
.LBB0_21:
s_and_not1_saveexec_b32 s4, s4
s_cbranch_execz .LBB0_25
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v6, 1, v4
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mov_b32_e32 v7, v5
v_lshlrev_b64 v[3:4], 2, v[4:5]
v_lshlrev_b64 v[7:8], 2, v[6:7]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
s_clause 0x1
global_load_b32 v5, v[3:4], off
global_load_b32 v9, v[7:8], off
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 v5, v9
s_clause 0x1
global_store_b32 v[3:4], v9, off
global_store_b32 v[7:8], v5, off
s_or_b32 exec_lo, exec_lo, s6
.LBB0_25:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
v_mov_b32_e32 v5, v2
.LBB0_26:
s_and_not1_saveexec_b32 s4, s5
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v3, 0
v_add_nc_u32_e32 v5, 1, v2
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mov_b32_e32 v6, v3
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[6:7], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
s_clause 0x1
global_load_b32 v8, v[2:3], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 v8, v9
s_cbranch_execz .LBB0_4
s_clause 0x1
global_store_b32 v[2:3], v9, off
global_store_b32 v[6:7], v8, off
s_branch .LBB0_4
.LBB0_29:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4sortPijj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4sortPijj, .Lfunc_end0-_Z4sortPijj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4sortPijj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4sortPijj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000fb3e3_00000000-6_mergesort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s"
.text
.globl _Z14checkCudaStateR9cudaErrorPKc
.type _Z14checkCudaStateR9cudaErrorPKc, @function
_Z14checkCudaStateR9cudaErrorPKc:
.LFB2057:
.cfi_startproc
endbr64
cmpl $0, (%rdi)
jne .L9
ret
.L9:
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rsi, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z14checkCudaStateR9cudaErrorPKc, .-_Z14checkCudaStateR9cudaErrorPKc
.globl _Z4swapPijj
.type _Z4swapPijj, @function
_Z4swapPijj:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z4swapPijj, .-_Z4swapPijj
.globl _Z4fillPim
.type _Z4fillPim, @function
_Z4fillPim:
.LFB2059:
.cfi_startproc
endbr64
testq %rsi, %rsi
je .L12
movl $0, %eax
.L14:
movl %esi, %edx
subl %eax, %edx
movl %edx, (%rdi,%rax,4)
addq $1, %rax
cmpq %rax, %rsi
jne .L14
.L12:
ret
.cfi_endproc
.LFE2059:
.size _Z4fillPim, .-_Z4fillPim
.section .rodata.str1.1
.LC1:
.string "%d "
.LC2:
.string "\n\n"
.text
.globl _Z4showPim
.type _Z4showPim, @function
_Z4showPim:
.LFB2060:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
testq %rsi, %rsi
je .L17
movq %rdi, %r12
movq %rsi, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r13
.L18:
movl (%r12,%rbx,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbx, %rbp
jne .L18
.L17:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z4showPim, .-_Z4showPim
.globl _Z25__device_stub__Z4sortPijjPijj
.type _Z25__device_stub__Z4sortPijjPijj, @function
_Z25__device_stub__Z4sortPijjPijj:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4sortPijj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z25__device_stub__Z4sortPijjPijj, .-_Z25__device_stub__Z4sortPijjPijj
.globl _Z4sortPijj
.type _Z4sortPijj, @function
_Z4sortPijj:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z4sortPijjPijj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z4sortPijj, .-_Z4sortPijj
.section .rodata.str1.1
.LC3:
.string "Impossible allocate data\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Impossible copy data from host to device\n"
.align 8
.LC7:
.string "Impossible copy data from device to host\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movl $8196, %edi
call malloc@PLT
movq %rax, %rbp
movl $8196, %edi
call malloc@PLT
movq %rax, %r12
movl $2049, %esi
movq %rbp, %rdi
call _Z4fillPim
leaq 8(%rsp), %rdi
movl $8196, %esi
call cudaMalloc@PLT
movl %eax, 4(%rsp)
leaq 4(%rsp), %rdi
leaq .LC3(%rip), %rsi
call _Z14checkCudaStateR9cudaErrorPKc
movq 8(%rsp), %rdi
testq %rdi, %rdi
je .L30
movl $1, %ecx
movl $8196, %edx
movq %rbp, %rsi
call cudaMemcpy@PLT
movl %eax, 4(%rsp)
leaq 4(%rsp), %rdi
leaq .LC4(%rip), %rsi
call _Z14checkCudaStateR9cudaErrorPKc
movl $2049, %esi
movq %rbp, %rdi
call _Z4showPim
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $3, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, %ebx
jmp .L31
.L32:
call cudaDeviceSynchronize@PLT
addl $1, %ebx
.L31:
movl %ebx, %eax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
movapd %xmm2, %xmm1
movq %xmm2, %r14
movsd .LC5(%rip), %xmm0
call pow@PLT
movsd .LC6(%rip), %xmm3
comisd %xmm0, %xmm3
jb .L41
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl 36(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L32
movq %r14, %xmm1
movsd .LC5(%rip), %xmm0
call pow@PLT
cvttsd2siq %xmm0, %rsi
movl $2049, %edx
movq 8(%rsp), %rdi
call _Z25__device_stub__Z4sortPijjPijj
jmp .L32
.L41:
movl $2, %ecx
movl $8196, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, 4(%rsp)
leaq 4(%rsp), %rdi
leaq .LC7(%rip), %rsi
call _Z14checkCudaStateR9cudaErrorPKc
movl $2049, %esi
movq %r12, %rdi
call _Z4showPim
.L30:
testq %rbp, %rbp
je .L36
movq %rbp, %rdi
call free@PLT
.L36:
testq %r12, %r12
je .L37
movq %r12, %rdi
call free@PLT
.L37:
movq 8(%rsp), %rdi
testq %rdi, %rdi
je .L38
call cudaFree@PLT
.L38:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z4sortPijj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z4sortPijj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1073741824
.align 8
.LC6:
.long 0
.long 1084228096
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "mergesort.hip"
.globl _Z14checkCudaStateR10hipError_tPKc # -- Begin function _Z14checkCudaStateR10hipError_tPKc
.p2align 4, 0x90
.type _Z14checkCudaStateR10hipError_tPKc,@function
_Z14checkCudaStateR10hipError_tPKc: # @_Z14checkCudaStateR10hipError_tPKc
.cfi_startproc
# %bb.0:
cmpl $0, (%rdi)
je .LBB0_1
# %bb.2:
movl $.L.str, %edi
xorl %eax, %eax
jmp printf # TAILCALL
.LBB0_1:
retq
.Lfunc_end0:
.size _Z14checkCudaStateR10hipError_tPKc, .Lfunc_end0-_Z14checkCudaStateR10hipError_tPKc
.cfi_endproc
# -- End function
.globl _Z19__device_stub__sortPijj # -- Begin function _Z19__device_stub__sortPijj
.p2align 4, 0x90
.type _Z19__device_stub__sortPijj,@function
_Z19__device_stub__sortPijj: # @_Z19__device_stub__sortPijj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4sortPijj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z19__device_stub__sortPijj, .Lfunc_end1-_Z19__device_stub__sortPijj
.cfi_endproc
# -- End function
.globl _Z4fillPim # -- Begin function _Z4fillPim
.p2align 4, 0x90
.type _Z4fillPim,@function
_Z4fillPim: # @_Z4fillPim
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB2_2
.p2align 4, 0x90
.LBB2_1: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %esi, (%rdi)
addq $4, %rdi
decq %rsi
jne .LBB2_1
.LBB2_2: # %._crit_edge
retq
.Lfunc_end2:
.size _Z4fillPim, .Lfunc_end2-_Z4fillPim
.cfi_endproc
# -- End function
.globl _Z4showPim # -- Begin function _Z4showPim
.p2align 4, 0x90
.type _Z4showPim,@function
_Z4showPim: # @_Z4showPim
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB3_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%r14,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %rbx
jne .LBB3_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB3_4: # %._crit_edge
movl $.Lstr, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end3:
.size _Z4showPim, .Lfunc_end3-_Z4showPim
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq $0, (%rsp)
movl $8196, %edi # imm = 0x2004
callq malloc
movq %rax, %r14
movl $8196, %edi # imm = 0x2004
callq malloc
movq %rax, %rbx
movl $2049, %eax # imm = 0x801
movq %r14, %rcx
.p2align 4, 0x90
.LBB4_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl %eax, (%rcx)
addq $4, %rcx
decq %rax
jne .LBB4_1
# %bb.2: # %_Z4fillPim.exit
movq %rsp, %rdi
movl $8196, %esi # imm = 0x2004
callq hipMalloc
testl %eax, %eax
je .LBB4_4
# %bb.3:
movl $.Lstr.1, %edi
callq puts@PLT
.LBB4_4: # %_Z14checkCudaStateR10hipError_tPKc.exit
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB4_18
# %bb.5:
movl $8196, %edx # imm = 0x2004
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB4_7
# %bb.6:
movl $.Lstr.2, %edi
callq puts@PLT
.LBB4_7: # %.lr.ph.i39.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_8: # %.lr.ph.i39
# =>This Inner Loop Header: Depth=1
movl (%r14,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $2049, %r15 # imm = 0x801
jne .LBB4_8
# %bb.9: # %_Z4showPim.exit
movabsq $4294967299, %r15 # imm = 0x100000003
movl $.Lstr, %edi
callq puts@PLT
movsd .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 16(%rsp) # 8-byte Spill
callq exp2@PLT
movl $2, %ebp
leaq 1021(%r15), %r12
jmp .LBB4_10
.p2align 4, 0x90
.LBB4_12: # in Loop: Header=BB4_10 Depth=1
callq hipDeviceSynchronize
movl %ebp, %eax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
callq exp2@PLT
incl %ebp
cmpl $13, %ebp
je .LBB4_13
.LBB4_10: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_12
# %bb.11: # in Loop: Header=BB4_10 Depth=1
movq (%rsp), %r13
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq exp2@PLT
cvttsd2si %xmm0, %rax
movq %r13, 72(%rsp)
movl %eax, 12(%rsp)
movl $2049, 8(%rsp) # imm = 0x801
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z4sortPijj, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_12
.LBB4_13:
movq (%rsp), %rsi
movl $8196, %edx # imm = 0x2004
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB4_15
# %bb.14:
movl $.Lstr.3, %edi
callq puts@PLT
.LBB4_15: # %.lr.ph.i43.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_16: # %.lr.ph.i43
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $2049, %r15 # imm = 0x801
jne .LBB4_16
# %bb.17: # %_Z4showPim.exit47
movl $.Lstr, %edi
callq puts@PLT
.LBB4_18:
testq %r14, %r14
je .LBB4_20
# %bb.19:
movq %r14, %rdi
callq free
.LBB4_20:
testq %rbx, %rbx
je .LBB4_22
# %bb.21:
movq %rbx, %rdi
callq free
.LBB4_22:
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB4_24
# %bb.23:
callq hipFree
.LBB4_24:
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4sortPijj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s"
.size .L.str, 3
.type _Z4sortPijj,@object # @_Z4sortPijj
.section .rodata,"a",@progbits
.globl _Z4sortPijj
.p2align 3, 0x0
_Z4sortPijj:
.quad _Z19__device_stub__sortPijj
.size _Z4sortPijj, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4sortPijj"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n"
.size .Lstr, 2
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Impossible allocate data"
.size .Lstr.1, 25
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Impossible copy data from host to device"
.size .Lstr.2, 41
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Impossible copy data from device to host"
.size .Lstr.3, 41
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__sortPijj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4sortPijj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
/*
* Device code
*/
__global__
void GaussSolve(
int const Nsize,
double* d_Aug,
double* d_Piv)
{
// Assign matrix elements to blocks and threads
int i = blockDim.x*blockIdx.x + threadIdx.x;
// Parallel forward elimination
for (int k = 0; k < Nsize-1; k++)
{
d_Piv[i] = d_Aug[i%Nsize+k*Nsize]/d_Aug[k*(Nsize+1)];
__syncthreads();
if (((i%Nsize)>k) && ((i/Nsize/*+1*/)>=k) && ((i/Nsize/*+1*/)<=Nsize))
d_Aug[i] -= d_Piv[i]*d_Aug[i-(i%Nsize)+k];
__syncthreads();
}
}
|
.file "tmpxft_001111aa_00000000-6_GaussSolve.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10GaussSolveiPdS_iPdS_
.type _Z33__device_stub__Z10GaussSolveiPdS_iPdS_, @function
_Z33__device_stub__Z10GaussSolveiPdS_iPdS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10GaussSolveiPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z10GaussSolveiPdS_iPdS_, .-_Z33__device_stub__Z10GaussSolveiPdS_iPdS_
.globl _Z10GaussSolveiPdS_
.type _Z10GaussSolveiPdS_, @function
_Z10GaussSolveiPdS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10GaussSolveiPdS_iPdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10GaussSolveiPdS_, .-_Z10GaussSolveiPdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10GaussSolveiPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10GaussSolveiPdS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/*
* Device code
*/
__global__
void GaussSolve(
int const Nsize,
double* d_Aug,
double* d_Piv)
{
// Assign matrix elements to blocks and threads
int i = blockDim.x*blockIdx.x + threadIdx.x;
// Parallel forward elimination
for (int k = 0; k < Nsize-1; k++)
{
d_Piv[i] = d_Aug[i%Nsize+k*Nsize]/d_Aug[k*(Nsize+1)];
__syncthreads();
if (((i%Nsize)>k) && ((i/Nsize/*+1*/)>=k) && ((i/Nsize/*+1*/)<=Nsize))
d_Aug[i] -= d_Piv[i]*d_Aug[i-(i%Nsize)+k];
__syncthreads();
}
}
|
#include <hip/hip_runtime.h>
/*
* Device code
*/
__global__
void GaussSolve(
int const Nsize,
double* d_Aug,
double* d_Piv)
{
// Assign matrix elements to blocks and threads
int i = blockDim.x*blockIdx.x + threadIdx.x;
// Parallel forward elimination
for (int k = 0; k < Nsize-1; k++)
{
d_Piv[i] = d_Aug[i%Nsize+k*Nsize]/d_Aug[k*(Nsize+1)];
__syncthreads();
if (((i%Nsize)>k) && ((i/Nsize/*+1*/)>=k) && ((i/Nsize/*+1*/)<=Nsize))
d_Aug[i] -= d_Piv[i]*d_Aug[i-(i%Nsize)+k];
__syncthreads();
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
/*
* Device code
*/
__global__
void GaussSolve(
int const Nsize,
double* d_Aug,
double* d_Piv)
{
// Assign matrix elements to blocks and threads
int i = blockDim.x*blockIdx.x + threadIdx.x;
// Parallel forward elimination
for (int k = 0; k < Nsize-1; k++)
{
d_Piv[i] = d_Aug[i%Nsize+k*Nsize]/d_Aug[k*(Nsize+1)];
__syncthreads();
if (((i%Nsize)>k) && ((i/Nsize/*+1*/)>=k) && ((i/Nsize/*+1*/)<=Nsize))
d_Aug[i] -= d_Piv[i]*d_Aug[i-(i%Nsize)+k];
__syncthreads();
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10GaussSolveiPdS_
.globl _Z10GaussSolveiPdS_
.p2align 8
.type _Z10GaussSolveiPdS_,@function
_Z10GaussSolveiPdS_:
s_load_b32 s8, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s8, 2
s_cbranch_scc1 .LBB0_6
s_load_b32 s4, s[0:1], 0x24
s_ashr_i32 s2, s8, 31
v_mov_b32_e32 v8, 0
s_add_i32 s3, s8, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s3, s2
v_cvt_f32_u32_e32 v1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s15, s15, s4
s_sub_i32 s4, 0, s3
v_add_nc_u32_e32 v5, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v5
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v1, 0x4f7ffffe, v1 :: v_dual_add_nc_u32 v4, v5, v3
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v3
v_mul_lo_u32 v2, s4, v1
v_xor_b32_e32 v3, s2, v3
s_load_b128 s[4:7], s[0:1], 0x8
s_add_i32 s1, s8, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v1, v2
v_add_nc_u32_e32 v1, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v4, v1
v_mul_lo_u32 v2, v1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v1
v_subrev_nc_u32_e32 v6, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v1, v1, v4 :: v_dual_cndmask_b32 v2, v2, v6
v_ashrrev_i32_e32 v6, 31, v5
v_add_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_mov_b32 s3, 0
s_mov_b32 s2, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v4, vcc_lo
v_xor_b32_e32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v7, v1, v3
v_lshlrev_b64 v[3:4], 3, v[5:6]
v_mul_lo_u32 v6, v7, s8
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v9, v5, v6
v_add3_u32 v0, v0, v6, s15
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_add_i32 s6, s8, -1
s_mov_b32 s7, s3
v_sub_nc_u32_e32 v0, v0, v5
v_mov_b32_e32 v5, v9
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s9
v_add_nc_u32_e32 v5, s8, v5
s_add_i32 s7, s7, 1
s_add_i32 s2, s2, s1
s_cmp_eq_u32 s6, s7
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
s_lshl_b64 s[10:11], s[2:3], 3
s_mov_b32 s9, exec_lo
s_add_u32 s10, s4, s10
s_addc_u32 s11, s5, s11
v_lshlrev_b64 v[10:11], 3, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s4, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
s_clause 0x1
global_load_b64 v[10:11], v[10:11], off
global_load_b64 v[12:13], v8, s[10:11]
s_waitcnt vmcnt(0)
v_div_scale_f64 v[14:15], null, v[12:13], v[12:13], v[10:11]
v_div_scale_f64 v[20:21], vcc_lo, v[10:11], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[16:17], v[14:15]
s_waitcnt_depctr 0xfff
v_fma_f64 v[18:19], -v[14:15], v[16:17], 1.0
v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[18:19], -v[14:15], v[16:17], 1.0
v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[18:19], v[20:21], v[16:17]
v_fma_f64 v[14:15], -v[14:15], v[18:19], v[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[14:15], v[14:15], v[16:17], v[18:19]
v_div_fixup_f64 v[10:11], v[14:15], v[12:13], v[10:11]
global_store_b64 v[1:2], v[10:11], off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_lt_i32_e64 s7, v9
s_cbranch_execz .LBB0_2
v_cmp_le_i32_e32 vcc_lo, s7, v7
v_cmp_ge_i32_e64 s0, s8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v10, s7, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[10:11], 3, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s4, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
global_load_b64 v[12:13], v[1:2], off
s_clause 0x1
global_load_b64 v[10:11], v[10:11], off
global_load_b64 v[14:15], v[3:4], off
s_waitcnt vmcnt(0)
v_fma_f64 v[10:11], -v[12:13], v[10:11], v[14:15]
global_store_b64 v[3:4], v[10:11], off
s_branch .LBB0_2
.LBB0_6:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10GaussSolveiPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 22
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10GaussSolveiPdS_, .Lfunc_end0-_Z10GaussSolveiPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10GaussSolveiPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10GaussSolveiPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 22
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
/*
* Device code
*/
__global__
void GaussSolve(
int const Nsize,
double* d_Aug,
double* d_Piv)
{
// Assign matrix elements to blocks and threads
int i = blockDim.x*blockIdx.x + threadIdx.x;
// Parallel forward elimination
for (int k = 0; k < Nsize-1; k++)
{
d_Piv[i] = d_Aug[i%Nsize+k*Nsize]/d_Aug[k*(Nsize+1)];
__syncthreads();
if (((i%Nsize)>k) && ((i/Nsize/*+1*/)>=k) && ((i/Nsize/*+1*/)<=Nsize))
d_Aug[i] -= d_Piv[i]*d_Aug[i-(i%Nsize)+k];
__syncthreads();
}
}
|
.text
.file "GaussSolve.hip"
.globl _Z25__device_stub__GaussSolveiPdS_ # -- Begin function _Z25__device_stub__GaussSolveiPdS_
.p2align 4, 0x90
.type _Z25__device_stub__GaussSolveiPdS_,@function
_Z25__device_stub__GaussSolveiPdS_: # @_Z25__device_stub__GaussSolveiPdS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10GaussSolveiPdS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__GaussSolveiPdS_, .Lfunc_end0-_Z25__device_stub__GaussSolveiPdS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10GaussSolveiPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10GaussSolveiPdS_,@object # @_Z10GaussSolveiPdS_
.section .rodata,"a",@progbits
.globl _Z10GaussSolveiPdS_
.p2align 3, 0x0
_Z10GaussSolveiPdS_:
.quad _Z25__device_stub__GaussSolveiPdS_
.size _Z10GaussSolveiPdS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10GaussSolveiPdS_"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__GaussSolveiPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10GaussSolveiPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001111aa_00000000-6_GaussSolve.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10GaussSolveiPdS_iPdS_
.type _Z33__device_stub__Z10GaussSolveiPdS_iPdS_, @function
_Z33__device_stub__Z10GaussSolveiPdS_iPdS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10GaussSolveiPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z10GaussSolveiPdS_iPdS_, .-_Z33__device_stub__Z10GaussSolveiPdS_iPdS_
.globl _Z10GaussSolveiPdS_
.type _Z10GaussSolveiPdS_, @function
_Z10GaussSolveiPdS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10GaussSolveiPdS_iPdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10GaussSolveiPdS_, .-_Z10GaussSolveiPdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10GaussSolveiPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10GaussSolveiPdS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "GaussSolve.hip"
.globl _Z25__device_stub__GaussSolveiPdS_ # -- Begin function _Z25__device_stub__GaussSolveiPdS_
.p2align 4, 0x90
.type _Z25__device_stub__GaussSolveiPdS_,@function
_Z25__device_stub__GaussSolveiPdS_: # @_Z25__device_stub__GaussSolveiPdS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10GaussSolveiPdS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__GaussSolveiPdS_, .Lfunc_end0-_Z25__device_stub__GaussSolveiPdS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10GaussSolveiPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10GaussSolveiPdS_,@object # @_Z10GaussSolveiPdS_
.section .rodata,"a",@progbits
.globl _Z10GaussSolveiPdS_
.p2align 3, 0x0
_Z10GaussSolveiPdS_:
.quad _Z25__device_stub__GaussSolveiPdS_
.size _Z10GaussSolveiPdS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10GaussSolveiPdS_"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__GaussSolveiPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10GaussSolveiPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void rMD_ED_D(float *S, float *T, int window_size, int dimensions, float *data_out, int trainSize, int gm) {
long long int i, j, p;
float sumErr = 0, dd = 0;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (gm == 0) {
extern __shared__ float T2[];
// offset training set
int s = dimensions * 2 * window_size * (idx / window_size);
int t = s + idx % window_size;
if (idx >= (trainSize * window_size)) //
return;
if (threadIdx.x == 0) {
for (i = 0; i < dimensions; i++)
for (j = 0; j < window_size; j++)
T2[window_size * i + j] = T[window_size * i + j];
}
__syncthreads();
for (j = 0; j < window_size; j++) {
dd = 0;
for (p = 0; p < dimensions; p++)
dd += (S[(t + p * 2 * window_size) + j] - T2[(p * window_size) + j]) *
(S[(t + p * 2 * window_size) + j] - T2[(p * window_size) + j]);
sumErr += dd;
}
data_out[idx] = sqrt(sumErr);
} else {
int s = dimensions * 2 * window_size * (idx / window_size);
int t = s + idx % window_size;
if (idx >= (trainSize * window_size))
return;
for (j = 0; j < window_size; j++) {
dd = 0;
for (p = 0; p < dimensions; p++)
dd += (S[(t + p * 2 * window_size) + j] - T[(p * window_size) + j]) *
(S[(t + p * 2 * window_size) + j] - T[(p * window_size) + j]);
sumErr += dd;
}
data_out[idx] = sqrt(sumErr);
}
}
|
.file "tmpxft_00085cae_00000000-6_rMD_ED_D.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z8rMD_ED_DPfS_iiS_iiPfS_iiS_ii
.type _Z35__device_stub__Z8rMD_ED_DPfS_iiS_iiPfS_iiS_ii, @function
_Z35__device_stub__Z8rMD_ED_DPfS_iiS_iiPfS_iiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8rMD_ED_DPfS_iiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z8rMD_ED_DPfS_iiS_iiPfS_iiS_ii, .-_Z35__device_stub__Z8rMD_ED_DPfS_iiS_iiPfS_iiS_ii
.globl _Z8rMD_ED_DPfS_iiS_ii
.type _Z8rMD_ED_DPfS_iiS_ii, @function
_Z8rMD_ED_DPfS_iiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z35__device_stub__Z8rMD_ED_DPfS_iiS_iiPfS_iiS_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8rMD_ED_DPfS_iiS_ii, .-_Z8rMD_ED_DPfS_iiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8rMD_ED_DPfS_iiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8rMD_ED_DPfS_iiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void rMD_ED_D(float *S, float *T, int window_size, int dimensions, float *data_out, int trainSize, int gm) {
long long int i, j, p;
float sumErr = 0, dd = 0;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (gm == 0) {
extern __shared__ float T2[];
// offset training set
int s = dimensions * 2 * window_size * (idx / window_size);
int t = s + idx % window_size;
if (idx >= (trainSize * window_size)) //
return;
if (threadIdx.x == 0) {
for (i = 0; i < dimensions; i++)
for (j = 0; j < window_size; j++)
T2[window_size * i + j] = T[window_size * i + j];
}
__syncthreads();
for (j = 0; j < window_size; j++) {
dd = 0;
for (p = 0; p < dimensions; p++)
dd += (S[(t + p * 2 * window_size) + j] - T2[(p * window_size) + j]) *
(S[(t + p * 2 * window_size) + j] - T2[(p * window_size) + j]);
sumErr += dd;
}
data_out[idx] = sqrt(sumErr);
} else {
int s = dimensions * 2 * window_size * (idx / window_size);
int t = s + idx % window_size;
if (idx >= (trainSize * window_size))
return;
for (j = 0; j < window_size; j++) {
dd = 0;
for (p = 0; p < dimensions; p++)
dd += (S[(t + p * 2 * window_size) + j] - T[(p * window_size) + j]) *
(S[(t + p * 2 * window_size) + j] - T[(p * window_size) + j]);
sumErr += dd;
}
data_out[idx] = sqrt(sumErr);
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void rMD_ED_D(float *S, float *T, int window_size, int dimensions, float *data_out, int trainSize, int gm) {
long long int i, j, p;
float sumErr = 0, dd = 0;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (gm == 0) {
extern __shared__ float T2[];
// offset training set
int s = dimensions * 2 * window_size * (idx / window_size);
int t = s + idx % window_size;
if (idx >= (trainSize * window_size)) //
return;
if (threadIdx.x == 0) {
for (i = 0; i < dimensions; i++)
for (j = 0; j < window_size; j++)
T2[window_size * i + j] = T[window_size * i + j];
}
__syncthreads();
for (j = 0; j < window_size; j++) {
dd = 0;
for (p = 0; p < dimensions; p++)
dd += (S[(t + p * 2 * window_size) + j] - T2[(p * window_size) + j]) *
(S[(t + p * 2 * window_size) + j] - T2[(p * window_size) + j]);
sumErr += dd;
}
data_out[idx] = sqrt(sumErr);
} else {
int s = dimensions * 2 * window_size * (idx / window_size);
int t = s + idx % window_size;
if (idx >= (trainSize * window_size))
return;
for (j = 0; j < window_size; j++) {
dd = 0;
for (p = 0; p < dimensions; p++)
dd += (S[(t + p * 2 * window_size) + j] - T[(p * window_size) + j]) *
(S[(t + p * 2 * window_size) + j] - T[(p * window_size) + j]);
sumErr += dd;
}
data_out[idx] = sqrt(sumErr);
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void rMD_ED_D(float *S, float *T, int window_size, int dimensions, float *data_out, int trainSize, int gm) {
long long int i, j, p;
float sumErr = 0, dd = 0;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (gm == 0) {
extern __shared__ float T2[];
// offset training set
int s = dimensions * 2 * window_size * (idx / window_size);
int t = s + idx % window_size;
if (idx >= (trainSize * window_size)) //
return;
if (threadIdx.x == 0) {
for (i = 0; i < dimensions; i++)
for (j = 0; j < window_size; j++)
T2[window_size * i + j] = T[window_size * i + j];
}
__syncthreads();
for (j = 0; j < window_size; j++) {
dd = 0;
for (p = 0; p < dimensions; p++)
dd += (S[(t + p * 2 * window_size) + j] - T2[(p * window_size) + j]) *
(S[(t + p * 2 * window_size) + j] - T2[(p * window_size) + j]);
sumErr += dd;
}
data_out[idx] = sqrt(sumErr);
} else {
int s = dimensions * 2 * window_size * (idx / window_size);
int t = s + idx % window_size;
if (idx >= (trainSize * window_size))
return;
for (j = 0; j < window_size; j++) {
dd = 0;
for (p = 0; p < dimensions; p++)
dd += (S[(t + p * 2 * window_size) + j] - T[(p * window_size) + j]) *
(S[(t + p * 2 * window_size) + j] - T[(p * window_size) + j]);
sumErr += dd;
}
data_out[idx] = sqrt(sumErr);
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8rMD_ED_DPfS_iiS_ii
.globl _Z8rMD_ED_DPfS_iiS_ii
.p2align 8
.type _Z8rMD_ED_DPfS_iiS_ii,@function
_Z8rMD_ED_DPfS_iiS_ii:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b32 s4, s[0:1], 0x34
s_mov_b32 s18, 0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s2, s8, 31
s_and_b32 s4, s4, 0xffff
s_add_i32 s3, s8, s2
s_mov_b32 s10, s9
s_xor_b32 s3, s3, s2
s_mul_i32 s9, s8, s9
v_cvt_f32_u32_e32 v1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_sub_i32 s4, 0, s3
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v2, s4, v3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v1
v_mul_hi_u32 v2, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v1, v4
v_xor_b32_e32 v5, v5, v4
v_xor_b32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v3, v2
v_mul_hi_u32 v2, v5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v2, s3
v_sub_nc_u32_e32 v3, v5, v3
v_add_nc_u32_e32 v5, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s3, v3
v_cmp_le_u32_e32 vcc_lo, s3, v3
v_dual_cndmask_b32 v2, v2, v5 :: v_dual_cndmask_b32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, 1, v2
v_cmp_le_u32_e32 vcc_lo, s3, v3
s_load_b64 s[2:3], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
v_xor_b32_e32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v4
v_mul_lo_u32 v3, v2, s8
v_mul_lo_u32 v2, s9, v2
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_cmp_lg_u32 s3, 0
v_cmp_gt_i32_e64 s2, s2, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v1, v3
v_lshl_add_u32 v2, v2, 1, v3
s_cbranch_scc0 .LBB0_8
s_mov_b32 s3, 0
s_and_saveexec_b32 s9, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s24, exec_lo, s9
s_cbranch_execz .LBB0_11
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_9
v_ashrrev_i32_e32 v3, 31, v2
s_ashr_i32 s9, s8, 31
s_ashr_i32 s11, s10, 31
v_mov_b32_e32 v7, 0
s_cmp_gt_i32 s10, 0
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_cselect_b32 s25, -1, 0
s_lshl_b64 s[12:13], s[8:9], 2
s_lshl_b64 s[14:15], s[8:9], 3
s_mov_b64 s[16:17], 0
s_mov_b64 s[18:19], s[6:7]
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
v_add_co_u32 v3, vcc_lo, v3, 4
s_add_u32 s16, s16, 1
v_add_f32_e32 v7, v7, v8
s_addc_u32 s17, s17, 0
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_add_u32 s18, s18, 4
s_addc_u32 s19, s19, 0
s_cmp_lg_u64 s[16:17], s[8:9]
s_cbranch_scc0 .LBB0_10
.LBB0_5:
v_mov_b32_e32 v8, 0
s_and_not1_b32 vcc_lo, exec_lo, s25
s_cbranch_vccnz .LBB0_4
v_mov_b32_e32 v6, v4
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v5, v3
s_mov_b64 s[20:21], s[18:19]
s_mov_b64 s[22:23], s[10:11]
.LBB0_7:
global_load_b32 v9, v[5:6], off
s_load_b32 s26, s[20:21], 0x0
v_add_co_u32 v5, vcc_lo, v5, s14
s_add_u32 s22, s22, -1
v_add_co_ci_u32_e32 v6, vcc_lo, s15, v6, vcc_lo
s_addc_u32 s23, s23, -1
s_add_u32 s20, s20, s12
s_addc_u32 s21, s21, s13
s_cmp_lg_u64 s[22:23], 0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_subrev_f32_e32 v9, s26, v9
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v8, v9, v9
s_cbranch_scc1 .LBB0_7
s_branch .LBB0_4
.LBB0_8:
s_mov_b32 s3, -1
s_branch .LBB0_12
.LBB0_9:
v_mov_b32_e32 v7, 0
.LBB0_10:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s18, exec_lo
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s24
.LBB0_12:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccz .LBB0_29
s_and_saveexec_b32 s19, s2
s_cbranch_execz .LBB0_28
s_mov_b32 s20, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_20
s_cmp_lt_i32 s10, 1
s_cbranch_scc1 .LBB0_20
s_ashr_i32 s11, s10, 31
s_ashr_i32 s9, s8, 31
s_cmp_gt_i32 s8, 0
s_mov_b32 s21, 0
s_cselect_b32 s22, -1, 0
s_lshl_b32 s23, s8, 2
s_lshl_b64 s[2:3], s[8:9], 2
s_mov_b64 s[12:13], 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_18
.p2align 6
.LBB0_17:
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_add_i32 s21, s21, s23
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_cmp_lg_u64 s[12:13], s[10:11]
s_cbranch_scc0 .LBB0_20
.LBB0_18:
s_mov_b64 s[14:15], s[6:7]
s_and_not1_b32 vcc_lo, exec_lo, s22
s_mov_b32 s24, s21
s_mov_b64 s[16:17], s[8:9]
s_cbranch_vccnz .LBB0_17
.LBB0_19:
s_load_b32 s25, s[14:15], 0x0
s_add_u32 s16, s16, -1
v_mov_b32_e32 v0, s24
s_addc_u32 s17, s17, -1
s_add_i32 s24, s24, 4
s_add_u32 s14, s14, 4
s_addc_u32 s15, s15, 0
s_cmp_lg_u64 s[16:17], 0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v3, s25
ds_store_b32 v0, v3
s_cbranch_scc1 .LBB0_19
s_branch .LBB0_17
.LBB0_20:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s20
s_cmp_lt_i32 s8, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_26
v_ashrrev_i32_e32 v3, 31, v2
s_ashr_i32 s9, s8, 31
s_ashr_i32 s11, s10, 31
v_mov_b32_e32 v7, 0
s_cmp_gt_i32 s10, 0
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_mov_b32 s12, 0
s_cselect_b32 s13, -1, 0
s_lshl_b32 s14, s8, 2
s_lshl_b64 s[2:3], s[8:9], 3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_mov_b64 s[4:5], 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_23
.p2align 6
.LBB0_22:
v_add_co_u32 v2, vcc_lo, v2, 4
s_delay_alu instid0(VALU_DEP_2)
v_add_f32_e32 v7, v7, v0
s_add_u32 s4, s4, 1
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_addc_u32 s5, s5, 0
s_add_i32 s12, s12, 4
s_cmp_eq_u64 s[4:5], s[8:9]
s_cbranch_scc1 .LBB0_27
.LBB0_23:
v_mov_b32_e32 v0, 0
s_and_not1_b32 vcc_lo, exec_lo, s13
s_cbranch_vccnz .LBB0_22
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v5, v3
v_mov_b32_e32 v4, v2
s_mov_b32 s15, s12
s_mov_b64 s[6:7], s[10:11]
.LBB0_25:
global_load_b32 v6, v[4:5], off
v_mov_b32_e32 v8, s15
v_add_co_u32 v4, vcc_lo, v4, s2
s_add_u32 s6, s6, -1
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
ds_load_b32 v8, v8
s_addc_u32 s7, s7, -1
s_add_i32 s15, s15, s14
s_cmp_lg_u64 s[6:7], 0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_sub_f32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v0, v6, v6
s_cbranch_scc1 .LBB0_25
s_branch .LBB0_22
.LBB0_26:
v_mov_b32_e32 v7, 0
.LBB0_27:
s_set_inst_prefetch_distance 0x2
s_or_b32 s18, s18, exec_lo
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s19
.LBB0_29:
s_and_saveexec_b32 s2, s18
s_cbranch_execz .LBB0_31
v_mul_f32_e32 v0, 0x4f800000, v7
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v7, v0, vcc_lo
v_sqrt_f32_e32 v0, v3
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v2, -1, v0
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, -v2, v0, v3
v_fma_f32 v6, -v4, v0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v5
v_cndmask_b32_e64 v0, v0, v2, s2
s_load_b64 s[2:3], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_lt_f32_e64 s0, 0, v6
v_ashrrev_i32_e32 v2, 31, v1
v_cndmask_b32_e64 v0, v0, v4, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, 0x37800000, v0
v_cndmask_b32_e32 v4, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_cmp_class_f32_e64 vcc_lo, v3, 0x260
v_cndmask_b32_e32 v2, v4, v3, vcc_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_31:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8rMD_ED_DPfS_iiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 27
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8rMD_ED_DPfS_iiS_ii, .Lfunc_end0-_Z8rMD_ED_DPfS_iiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
- .offset: 160
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8rMD_ED_DPfS_iiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 29
.sgpr_spill_count: 0
.symbol: _Z8rMD_ED_DPfS_iiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void rMD_ED_D(float *S, float *T, int window_size, int dimensions, float *data_out, int trainSize, int gm) {
long long int i, j, p;
float sumErr = 0, dd = 0;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (gm == 0) {
extern __shared__ float T2[];
// offset training set
int s = dimensions * 2 * window_size * (idx / window_size);
int t = s + idx % window_size;
if (idx >= (trainSize * window_size)) //
return;
if (threadIdx.x == 0) {
for (i = 0; i < dimensions; i++)
for (j = 0; j < window_size; j++)
T2[window_size * i + j] = T[window_size * i + j];
}
__syncthreads();
for (j = 0; j < window_size; j++) {
dd = 0;
for (p = 0; p < dimensions; p++)
dd += (S[(t + p * 2 * window_size) + j] - T2[(p * window_size) + j]) *
(S[(t + p * 2 * window_size) + j] - T2[(p * window_size) + j]);
sumErr += dd;
}
data_out[idx] = sqrt(sumErr);
} else {
int s = dimensions * 2 * window_size * (idx / window_size);
int t = s + idx % window_size;
if (idx >= (trainSize * window_size))
return;
for (j = 0; j < window_size; j++) {
dd = 0;
for (p = 0; p < dimensions; p++)
dd += (S[(t + p * 2 * window_size) + j] - T[(p * window_size) + j]) *
(S[(t + p * 2 * window_size) + j] - T[(p * window_size) + j]);
sumErr += dd;
}
data_out[idx] = sqrt(sumErr);
}
}
|
.text
.file "rMD_ED_D.hip"
.globl _Z23__device_stub__rMD_ED_DPfS_iiS_ii # -- Begin function _Z23__device_stub__rMD_ED_DPfS_iiS_ii
.p2align 4, 0x90
.type _Z23__device_stub__rMD_ED_DPfS_iiS_ii,@function
_Z23__device_stub__rMD_ED_DPfS_iiS_ii: # @_Z23__device_stub__rMD_ED_DPfS_iiS_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8rMD_ED_DPfS_iiS_ii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z23__device_stub__rMD_ED_DPfS_iiS_ii, .Lfunc_end0-_Z23__device_stub__rMD_ED_DPfS_iiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8rMD_ED_DPfS_iiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8rMD_ED_DPfS_iiS_ii,@object # @_Z8rMD_ED_DPfS_iiS_ii
.section .rodata,"a",@progbits
.globl _Z8rMD_ED_DPfS_iiS_ii
.p2align 3, 0x0
_Z8rMD_ED_DPfS_iiS_ii:
.quad _Z23__device_stub__rMD_ED_DPfS_iiS_ii
.size _Z8rMD_ED_DPfS_iiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8rMD_ED_DPfS_iiS_ii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__rMD_ED_DPfS_iiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8rMD_ED_DPfS_iiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00085cae_00000000-6_rMD_ED_D.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z8rMD_ED_DPfS_iiS_iiPfS_iiS_ii
.type _Z35__device_stub__Z8rMD_ED_DPfS_iiS_iiPfS_iiS_ii, @function
_Z35__device_stub__Z8rMD_ED_DPfS_iiS_iiPfS_iiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8rMD_ED_DPfS_iiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z8rMD_ED_DPfS_iiS_iiPfS_iiS_ii, .-_Z35__device_stub__Z8rMD_ED_DPfS_iiS_iiPfS_iiS_ii
.globl _Z8rMD_ED_DPfS_iiS_ii
.type _Z8rMD_ED_DPfS_iiS_ii, @function
_Z8rMD_ED_DPfS_iiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z35__device_stub__Z8rMD_ED_DPfS_iiS_iiPfS_iiS_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8rMD_ED_DPfS_iiS_ii, .-_Z8rMD_ED_DPfS_iiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8rMD_ED_DPfS_iiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8rMD_ED_DPfS_iiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "rMD_ED_D.hip"
.globl _Z23__device_stub__rMD_ED_DPfS_iiS_ii # -- Begin function _Z23__device_stub__rMD_ED_DPfS_iiS_ii
.p2align 4, 0x90
.type _Z23__device_stub__rMD_ED_DPfS_iiS_ii,@function
_Z23__device_stub__rMD_ED_DPfS_iiS_ii: # @_Z23__device_stub__rMD_ED_DPfS_iiS_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8rMD_ED_DPfS_iiS_ii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z23__device_stub__rMD_ED_DPfS_iiS_ii, .Lfunc_end0-_Z23__device_stub__rMD_ED_DPfS_iiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8rMD_ED_DPfS_iiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8rMD_ED_DPfS_iiS_ii,@object # @_Z8rMD_ED_DPfS_iiS_ii
.section .rodata,"a",@progbits
.globl _Z8rMD_ED_DPfS_iiS_ii
.p2align 3, 0x0
_Z8rMD_ED_DPfS_iiS_ii:
.quad _Z23__device_stub__rMD_ED_DPfS_iiS_ii
.size _Z8rMD_ED_DPfS_iiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8rMD_ED_DPfS_iiS_ii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__rMD_ED_DPfS_iiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8rMD_ED_DPfS_iiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
//
// Created by kindr on 2021/5/12.
//
#include "graphConcurrent.cuh"
#include "multiKernelConcurrent.cuh"
const int N = 1 << 25;
void graphConcurrent() {
cudaStream_t s1, s2;
cudaStreamCreate(&s1);
cudaStreamCreate(&s2);
// 开始捕获流操作
cudaStreamBeginCapture(s1, cudaStreamCaptureModeGlobal);
math_kernel1<<<1, 1, 0, s1>>>(N);
cudaEvent_t e1, e2;
cudaEventCreate(&e1);
cudaEventCreate(&e2);
cudaEventRecord(e1, s1);
cudaStreamWaitEvent(s2, e1);
math_kernel2<<<1, 1, 0, s1>>>(N);
math_kernel2<<<1, 1, 0, s2>>>(N);
cudaEventRecord(e2, s2);
cudaStreamWaitEvent(s1, e2);
math_kernel1<<<1, 1, 0, s1>>>(N);
// 捕获结束
cudaGraph_t graph;
cudaStreamEndCapture(s1, &graph);
cudaGraphExec_t graphExec;
cudaGraphInstantiate(&graphExec, graph, nullptr, nullptr, 0);
for (int i = 0; i < 2; i++) {
cudaGraphLaunch(graphExec, nullptr);
}
cudaDeviceSynchronize();
}
|
code for sm_80
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
//
// Created by kindr on 2021/5/12.
//
#include "graphConcurrent.cuh"
#include "multiKernelConcurrent.cuh"
const int N = 1 << 25;
void graphConcurrent() {
cudaStream_t s1, s2;
cudaStreamCreate(&s1);
cudaStreamCreate(&s2);
// 开始捕获流操作
cudaStreamBeginCapture(s1, cudaStreamCaptureModeGlobal);
math_kernel1<<<1, 1, 0, s1>>>(N);
cudaEvent_t e1, e2;
cudaEventCreate(&e1);
cudaEventCreate(&e2);
cudaEventRecord(e1, s1);
cudaStreamWaitEvent(s2, e1);
math_kernel2<<<1, 1, 0, s1>>>(N);
math_kernel2<<<1, 1, 0, s2>>>(N);
cudaEventRecord(e2, s2);
cudaStreamWaitEvent(s1, e2);
math_kernel1<<<1, 1, 0, s1>>>(N);
// 捕获结束
cudaGraph_t graph;
cudaStreamEndCapture(s1, &graph);
cudaGraphExec_t graphExec;
cudaGraphInstantiate(&graphExec, graph, nullptr, nullptr, 0);
for (int i = 0; i < 2; i++) {
cudaGraphLaunch(graphExec, nullptr);
}
cudaDeviceSynchronize();
}
|
.file "tmpxft_000b0b9c_00000000-6_graphConcurrent.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15graphConcurrentv
.type _Z15graphConcurrentv, @function
_Z15graphConcurrentv:
.LFB2027:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 16(%rsp), %rdi
call cudaStreamCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaStreamBeginCapture@PLT
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movq 8(%rsp), %r9
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L10
.L4:
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaStreamWaitEvent@PLT
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movq 8(%rsp), %r9
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L11
.L5:
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movq 16(%rsp), %r9
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L12
.L6:
movq 16(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %edx
movq 32(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaStreamWaitEvent@PLT
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movq 8(%rsp), %r9
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L13
.L7:
leaq 40(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaStreamEndCapture@PLT
leaq 56(%rsp), %rdi
movl $0, %edx
movq 40(%rsp), %rsi
call cudaGraphInstantiate@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaGraphLaunch@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaGraphLaunch@PLT
call cudaDeviceSynchronize@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl $33554432, %edi
call _Z12math_kernel1i@PLT
jmp .L4
.L11:
movl $33554432, %edi
call _Z12math_kernel2i@PLT
jmp .L5
.L12:
movl $33554432, %edi
call _Z12math_kernel2i@PLT
jmp .L6
.L13:
movl $33554432, %edi
call _Z12math_kernel1i@PLT
jmp .L7
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size _Z15graphConcurrentv, .-_Z15graphConcurrentv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
//
// Created by kindr on 2021/5/12.
//
#include "graphConcurrent.cuh"
#include "multiKernelConcurrent.cuh"
const int N = 1 << 25;
void graphConcurrent() {
cudaStream_t s1, s2;
cudaStreamCreate(&s1);
cudaStreamCreate(&s2);
// 开始捕获流操作
cudaStreamBeginCapture(s1, cudaStreamCaptureModeGlobal);
math_kernel1<<<1, 1, 0, s1>>>(N);
cudaEvent_t e1, e2;
cudaEventCreate(&e1);
cudaEventCreate(&e2);
cudaEventRecord(e1, s1);
cudaStreamWaitEvent(s2, e1);
math_kernel2<<<1, 1, 0, s1>>>(N);
math_kernel2<<<1, 1, 0, s2>>>(N);
cudaEventRecord(e2, s2);
cudaStreamWaitEvent(s1, e2);
math_kernel1<<<1, 1, 0, s1>>>(N);
// 捕获结束
cudaGraph_t graph;
cudaStreamEndCapture(s1, &graph);
cudaGraphExec_t graphExec;
cudaGraphInstantiate(&graphExec, graph, nullptr, nullptr, 0);
for (int i = 0; i < 2; i++) {
cudaGraphLaunch(graphExec, nullptr);
}
cudaDeviceSynchronize();
}
|
//
// Created by kindr on 2021/5/12.
//
#ifndef LEARNCUDA_GRAPHCONCURRENT_CUH
#define LEARNCUDA_GRAPHCONCURRENT_CUH
void graphConcurrent();
#endif //LEARNCUDA_GRAPHCONCURRENT_CUH
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
//
// Created by kindr on 2021/5/12.
//
#ifndef LEARNCUDA_GRAPHCONCURRENT_CUH
#define LEARNCUDA_GRAPHCONCURRENT_CUH
void graphConcurrent();
#endif //LEARNCUDA_GRAPHCONCURRENT_CUH
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
//
// Created by kindr on 2021/5/12.
//
#ifndef LEARNCUDA_GRAPHCONCURRENT_CUH
#define LEARNCUDA_GRAPHCONCURRENT_CUH
void graphConcurrent();
#endif //LEARNCUDA_GRAPHCONCURRENT_CUH
|
.text
.file "graphConcurrent.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000b0b9c_00000000-6_graphConcurrent.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15graphConcurrentv
.type _Z15graphConcurrentv, @function
_Z15graphConcurrentv:
.LFB2027:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 16(%rsp), %rdi
call cudaStreamCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaStreamBeginCapture@PLT
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movq 8(%rsp), %r9
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L10
.L4:
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaStreamWaitEvent@PLT
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movq 8(%rsp), %r9
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L11
.L5:
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movq 16(%rsp), %r9
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L12
.L6:
movq 16(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %edx
movq 32(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaStreamWaitEvent@PLT
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movq 8(%rsp), %r9
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L13
.L7:
leaq 40(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaStreamEndCapture@PLT
leaq 56(%rsp), %rdi
movl $0, %edx
movq 40(%rsp), %rsi
call cudaGraphInstantiate@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaGraphLaunch@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaGraphLaunch@PLT
call cudaDeviceSynchronize@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl $33554432, %edi
call _Z12math_kernel1i@PLT
jmp .L4
.L11:
movl $33554432, %edi
call _Z12math_kernel2i@PLT
jmp .L5
.L12:
movl $33554432, %edi
call _Z12math_kernel2i@PLT
jmp .L6
.L13:
movl $33554432, %edi
call _Z12math_kernel1i@PLT
jmp .L7
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size _Z15graphConcurrentv, .-_Z15graphConcurrentv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "graphConcurrent.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
// For the CUDA runtime routines (prefixed with "cuda_")
#include <cuda_runtime.h>
#include <cuda.h>
// Device global variables
__device__ double c_x_min;
__device__ double c_x_max;
__device__ double c_y_min;
__device__ double c_y_max;
__device__ double pixel_width;
__device__ double pixel_height;
__device__ int iteration_max = 200;
__device__ int image_size;
__device__ int image_buffer_size;
__device__ int num_threads;
__device__ int th_per_block;
__device__ int pixels_per_thread;
__device__ int gradient_size = 16;
__device__ int colors[17][3] = {
{66, 30, 15},
{25, 7, 26},
{9, 1, 47},
{4, 4, 73},
{0, 7, 100},
{12, 44, 138},
{24, 82, 177},
{57, 125, 209},
{134, 181, 229},
{211, 236, 248},
{241, 233, 191},
{248, 201, 95},
{255, 170, 0},
{204, 128, 0},
{153, 87, 0},
{106, 52, 3},
{16, 16, 16},
};
// Host global variables
dim3 num_blocks, threads_per_block;
int num_blocks_x, th_per_block_x;
int num_blocks_y, th_per_block_y;
int host_image_buffer_size;
unsigned char* image_buffer_host;
int i_x_max;
int i_y_max;
int check (cudaError_t& err, const char* msg) {
if (err != cudaSuccess) {
printf ("%s", msg);
printf (" | Error: %s\n", cudaGetErrorString(err));
return 1;
}
return 0;
}
void print_bad_arguments () {
printf("usage: ./mandelbrot_seq c_x_min c_x_max c_y_min c_y_max"
" image_size NUM_BLOCKS TH_PER_BLOCK \n");
printf("examples with image_size = 11500:\n");
printf(" Full Picture: ./mandelbrot_cuda -2.5 1.5 -2.0 2.0 11500 4 64 \n");
printf(" Seahorse Valley: ./mandelbrot_cuda -0.8 -0.7 0.05 0.15 11500 4 64 \n");
printf(" Elephant Valley: ./mandelbrot_cuda 0.175 0.375 -0.1 0.1 11500 4 64 \n");
printf(" Triple Spiral Valley: ./mandelbrot_cuda -0.188 -0.012 0.554 0.754 11500 4 64 \n");
}
// Get global variables from command line args
void init (int argc, char* argv[]) {
// host variables
double host_c_x_min, host_c_x_max;
double host_c_y_min, host_c_y_max;
int host_image_size;
if (argc < 8) {
print_bad_arguments();
exit(0);
}
else {
num_blocks_y = th_per_block_y = 1;
sscanf(argv[1], "%lf", &host_c_x_min);
sscanf(argv[2], "%lf", &host_c_x_max);
sscanf(argv[3], "%lf", &host_c_y_min);
sscanf(argv[4], "%lf", &host_c_y_max);
sscanf(argv[5], "%d", &host_image_size);
sscanf(argv[6], "%d", &num_blocks_x);
if (argc == 8) {
sscanf(argv[7], "%d", &th_per_block_x);
}
else if (argc == 10) {
sscanf(argv[7], "%d", &num_blocks_y);
sscanf(argv[8], "%d", &th_per_block_x);
sscanf(argv[9], "%d", &th_per_block_y);
}
else {
print_bad_arguments();
exit(0);
}
host_image_buffer_size = host_image_size * host_image_size;
int host_th_per_block = th_per_block_x * th_per_block_y;
int host_num_threads = host_th_per_block * num_blocks_x * num_blocks_y;
int host_pixels_per_thread = host_image_buffer_size / host_num_threads;
i_x_max = host_image_size;
i_y_max = host_image_size;
double host_pixel_width = (host_c_x_max - host_c_x_min) / i_x_max;
double host_pixel_height = (host_c_y_max - host_c_y_min) / i_y_max;
// copy host variables to device
cudaError_t err = cudaSuccess;
cudaMemcpyToSymbol(c_x_min, &host_c_x_min, sizeof(double));
cudaMemcpyToSymbol(c_x_max, &host_c_x_max, sizeof(double));
cudaMemcpyToSymbol(c_y_min, &host_c_y_min, sizeof(double));
cudaMemcpyToSymbol(c_y_max, &host_c_y_max, sizeof(double));
cudaMemcpyToSymbol(image_size, &host_image_size, sizeof(int));
cudaMemcpyToSymbol(num_threads, &host_num_threads, sizeof(int));
cudaMemcpyToSymbol(th_per_block, &host_th_per_block, sizeof(int));
cudaMemcpyToSymbol(pixel_width, &host_pixel_width, sizeof(double));
cudaMemcpyToSymbol(pixel_height, &host_pixel_height, sizeof(double));
cudaMemcpyToSymbol(pixels_per_thread, &host_pixels_per_thread, sizeof(int));
cudaMemcpyToSymbol(image_buffer_size, &host_image_buffer_size, sizeof(int));
err = cudaGetLastError();
if (check(err, "Failed to copy command line args to device"))
exit(EXIT_FAILURE);
};
};
__device__
void update_rgb_buffer(unsigned char* image_buffer_device, int iteration, int pix) {
int color;
if (iteration == iteration_max) {
image_buffer_device[pix * 3 + 0] = colors[gradient_size][0];
image_buffer_device[pix * 3 + 1] = colors[gradient_size][1];
image_buffer_device[pix * 3 + 2] = colors[gradient_size][2];
} else {
color = iteration % gradient_size;
image_buffer_device[pix * 3 + 0] = colors[color][0];
image_buffer_device[pix * 3 + 1] = colors[color][1];
image_buffer_device[pix * 3 + 2] = colors[color][2];
};
};
__global__
void compute_mandelbrot(unsigned char* image_buffer_device) {
double z_x;
double z_y;
double z_x_squared;
double z_y_squared;
double escape_radius_squared = 4;
int iteration;
int i_x;
int i_y;
double c_x;
double c_y;
// Calculates pixel where current thread will start its work
int my_block = blockIdx.x + gridDim.x * blockIdx.y;
int my_thread_in_block = threadIdx.x + blockDim.x * threadIdx.y;
int my_thread = my_block * th_per_block + my_thread_in_block;
/* what thread will process each pixel ?
*
* Example: image 5x5 -> buffer_size = 25
* 3 blocks of 3 threads -> 9 threads
*
* 2 4 7 - -
* 1 4 6 - -
* 1 3 6 8 -
* 0 3 5 8 -
* 0 2 5 7 -
*
* and the remaining pixels we process separetedly,
* each thread process its remaining pixel in the end
*
* 2 4 7 5 0
* 1 4 6 6 1
* 1 3 6 8 2
* 0 3 5 8 3
* 0 2 5 7 4
*/
// Its easier to process by pixels instead of by row-collunm
int pix = my_thread * pixels_per_thread;
int end_pixel = pix + pixels_per_thread;
int my_rem_pixel = image_buffer_size - my_thread - 1;
while (pix <= my_rem_pixel) {
i_y = pix / image_size;
i_x = pix % image_size;
c_y = c_y_min + i_y * pixel_height;
if (fabs(c_y) < pixel_height / 2) {
c_y = 0.0;
};
c_x = c_x_min + i_x * pixel_width;
z_x = 0.0;
z_y = 0.0;
z_x_squared = 0.0;
z_y_squared = 0.0;
for (iteration = 0;
iteration < iteration_max && \
((z_x_squared + z_y_squared) < escape_radius_squared);
iteration++) {
z_y = 2 * z_x * z_y + c_y;
z_x = z_x_squared - z_y_squared + c_x;
z_x_squared = z_x * z_x;
z_y_squared = z_y * z_y;
};
update_rgb_buffer(image_buffer_device, iteration, pix);
pix++;
// Treat remaining pixel
if (pix == end_pixel) {
if (my_rem_pixel >= pix) pix = my_rem_pixel;
else break;
}
}
}
void allocate_image_buffer(unsigned char** image_buffer_device, size_t size) {
// Our buffer, instead of a matrix, will be a continuous array
// Allocate host memory
image_buffer_host = (unsigned char*)malloc(sizeof(unsigned char) * size);
// Allocate device memory
cudaError_t err = cudaSuccess;
err = cudaMalloc((void**)(image_buffer_device), size);
// Test alloc success
if (image_buffer_host == NULL) {
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
if (check(err, "Failed to allocate device image buffer"))
exit(EXIT_FAILURE);
};
void write_to_file() {
FILE* file;
const char* filename = "output.ppm";
const char* comment = "# ";
int max_color_component_value = 255;
file = fopen(filename, "wb");
fprintf(file, "P6\n %s\n %d\n %d\n %d\n", comment,
i_x_max, i_y_max, max_color_component_value);
for (int i = 0; i < host_image_buffer_size; i++) {
fwrite(image_buffer_host + 3*i, 1, 3, file);
};
fclose(file);
};
int main(int argc, char* argv[]) {
init(argc, argv);
cudaError_t err;
int rgb_size = 3;
size_t size = host_image_buffer_size * rgb_size;
unsigned char* image_buffer_device;
allocate_image_buffer(&image_buffer_device, size);
// Launch compute_mandelbrot CUDA Kernel
num_blocks = dim3(num_blocks_x, num_blocks_y);
threads_per_block = dim3(th_per_block_x, th_per_block_y);
compute_mandelbrot<<<num_blocks, threads_per_block>>>(image_buffer_device);
cudaDeviceSynchronize();
err = cudaGetLastError();
if (check(err, "Failed to launch compute_mandelbrot kernel"))
exit(EXIT_FAILURE);
// Copy the device result vector in device memory to the host result vector
// in host memory.
err = cudaMemcpy(image_buffer_host, image_buffer_device, size,
cudaMemcpyDeviceToHost);
if (check(err, "Failed to copy vector from device to host"))
exit(EXIT_FAILURE);
// Free device global memory
err = cudaFree(image_buffer_device);
if (check(err, "Failed to free device vector"))
exit(EXIT_FAILURE);
write_to_file();
// Free host memory
free(image_buffer_host);
return 0;
}
|
code for sm_80
Function : _Z18compute_mandelbrotPh
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x4][0x54] ; /* 0x01001500ff037624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x4][0x50] ; /* 0x01001400ff027624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R4, c[0x4][0x58] ; /* 0x0100160000047a02 */
/* 0x000fc80000000f00 */
/*0050*/ LDG.E R3, [R2.64] ; /* 0x0000000802037981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x5c] ; /* 0x01001700ff057624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R7, c[0x4][0x44] ; /* 0x0100110000077a02 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x4][0x40] ; /* 0x01001000ff067624 */
/* 0x000fc600078e00ff */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000804047981 */
/* 0x000ee8000c1e1900 */
/*00a0*/ LDG.E R7, [R6.64] ; /* 0x0000000806077981 */
/* 0x000f22000c1e1900 */
/*00b0*/ S2UR UR4, SR_CTAID.Y ; /* 0x00000000000479c3 */
/* 0x000e220000002600 */
/*00c0*/ ULDC UR6, c[0x0][0xc] ; /* 0x0000030000067ab9 */
/* 0x000fe40000000800 */
/*00d0*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002200 */
/*00e0*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*00f0*/ S2UR UR5, SR_CTAID.X ; /* 0x00000000000579c3 */
/* 0x000e220000002500 */
/*0100*/ IMAD R0, R0, c[0x0][0x0], R9 ; /* 0x0000000000007a24 */
/* 0x002fe200078e0209 */
/*0110*/ UIMAD UR4, UR4, UR6, UR5 ; /* 0x00000006040472a4 */
/* 0x001fcc000f8e0205 */
/*0120*/ IMAD R0, R3, UR4, R0 ; /* 0x0000000403007c24 */
/* 0x004fca000f8e0200 */
/*0130*/ LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff027212 */
/* 0x000fe200078e33ff */
/*0140*/ IMAD R19, R0, R4, RZ ; /* 0x0000000400137224 */
/* 0x008fc800078e02ff */
/*0150*/ IMAD.IADD R0, R2, 0x1, R7 ; /* 0x0000000102007824 */
/* 0x010fca00078e0207 */
/*0160*/ ISETP.GT.AND P0, PT, R19, R0, PT ; /* 0x000000001300720c */
/* 0x000fda0003f04270 */
/*0170*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0180*/ IMAD.IADD R18, R4, 0x1, R19 ; /* 0x0000000104127824 */
/* 0x000fe400078e0213 */
/*0190*/ MOV R2, c[0x4][0x38] ; /* 0x01000e0000027a02 */
/* 0x000fe20000000f00 */
/*01a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x4][0x3c] ; /* 0x01000f00ff037624 */
/* 0x000fca00078e00ff */
/*01b0*/ LDG.E R4, [R2.64] ; /* 0x0000000802047981 */
/* 0x0010a2000c1e1900 */
/*01c0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x4][0x28] ; /* 0x01000a00ff067624 */
/* 0x000fe200078e00ff */
/*01d0*/ MOV R7, c[0x4][0x2c] ; /* 0x01000b0000077a02 */
/* 0x000fe20000000f00 */
/*01e0*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff0c7624 */
/* 0x000fe400078e00ff */
/*01f0*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff0d7624 */
/* 0x000fe200078e00ff */
/*0200*/ MOV R14, c[0x4][0x30] ; /* 0x01000c00000e7a02 */
/* 0x000fe20000000f00 */
/*0210*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x4][0x34] ; /* 0x01000d00ff0f7624 */
/* 0x000fe200078e00ff */
/*0220*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000806067981 */
/* 0x000ee8000c1e1b00 */
/*0230*/ LDG.E.64 R12, [R12.64] ; /* 0x000000080c0c7981 */
/* 0x000ee8000c1e1b00 */
/*0240*/ LDG.E R5, [R14.64] ; /* 0x000000080e057981 */
/* 0x000322000c1e1900 */
/*0250*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x4][0x20] ; /* 0x01000800ff087624 */
/* 0x000fe200078e00ff */
/*0260*/ MOV R9, c[0x4][0x24] ; /* 0x0100090000097a02 */
/* 0x000fe20000000f00 */
/*0270*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x4][0x0] ; /* 0x01000000ff0a7624 */
/* 0x000fc400078e00ff */
/*0280*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x4][0x4] ; /* 0x01000100ff0b7624 */
/* 0x000fe200078e00ff */
/*0290*/ MOV R2, c[0x4][0x60] ; /* 0x0100180000027a02 */
/* 0x001fe20000000f00 */
/*02a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x4][0x64] ; /* 0x01001900ff037624 */
/* 0x000fe200078e00ff */
/*02b0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000808087981 */
/* 0x000ee8000c1e1b00 */
/*02c0*/ LDG.E.64 R10, [R10.64] ; /* 0x000000080a0a7981 */
/* 0x000ee8000c1e1b00 */
/*02d0*/ LDG.E R20, [R2.64] ; /* 0x0000000802147981 */
/* 0x000162000c1e1900 */
/*02e0*/ IABS R22, R19 ; /* 0x0000001300167213 */
/* 0x000fc40000000000 */
/*02f0*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0300*/ IABS R16, R4.reuse ; /* 0x0000000400107213 */
/* 0x084fe40000000000 */
/*0310*/ IABS R23, R4 ; /* 0x0000000400177213 */
/* 0x000fe40000000000 */
/*0320*/ I2F.RP R17, R16 ; /* 0x0000001000117306 */
/* 0x000eb00000209400 */
/*0330*/ MUFU.RCP R17, R17 ; /* 0x0000001100117308 */
/* 0x004e640000001000 */
/*0340*/ IADD3 R14, R17, 0xffffffe, RZ ; /* 0x0ffffffe110e7810 */
/* 0x002fe20007ffe0ff */
/*0350*/ IMAD.MOV R17, RZ, RZ, -R23 ; /* 0x000000ffff117224 */
/* 0x000fca00078e0a17 */
/*0360*/ F2I.FTZ.U32.TRUNC.NTZ R15, R14 ; /* 0x0000000e000f7305 */
/* 0x0002a4000021f000 */
/*0370*/ HFMA2.MMA R14, -RZ, RZ, 0, 0 ; /* 0x00000000ff0e7435 */
/* 0x002fe200000001ff */
/*0380*/ IMAD.MOV R21, RZ, RZ, -R15 ; /* 0x000000ffff157224 */
/* 0x004fc800078e0a0f */
/*0390*/ IMAD R21, R21, R16, RZ ; /* 0x0000001015157224 */
/* 0x000fca00078e02ff */
/*03a0*/ IMAD.HI.U32 R15, R15, R21, R14 ; /* 0x000000150f0f7227 */
/* 0x000fe200078e000e */
/*03b0*/ LOP3.LUT R14, R19, R4, RZ, 0x3c, !PT ; /* 0x00000004130e7212 */
/* 0x000fc600078e3cff */
/*03c0*/ IMAD R21, R19, 0x3, RZ ; /* 0x0000000313157824 */
/* 0x000fe200078e02ff */
/*03d0*/ ISETP.GE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe20003f26270 */
/*03e0*/ IMAD.HI.U32 R15, R15, R22, RZ ; /* 0x000000160f0f7227 */
/* 0x000fc800078e00ff */
/*03f0*/ IMAD R17, R15, R17, R22 ; /* 0x000000110f117224 */
/* 0x000fca00078e0216 */
/*0400*/ ISETP.GT.U32.AND P2, PT, R16, R17, PT ; /* 0x000000111000720c */
/* 0x000fda0003f44070 */
/*0410*/ @!P2 IMAD.IADD R17, R17, 0x1, -R16 ; /* 0x000000011111a824 */
/* 0x000fe200078e0a10 */
/*0420*/ @!P2 IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0fa810 */
/* 0x000fe40007ffe0ff */
/*0430*/ ISETP.NE.AND P2, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f45270 */
/*0440*/ ISETP.GE.U32.AND P0, PT, R17, R16, PT ; /* 0x000000101100720c */
/* 0x000fda0003f06070 */
/*0450*/ @P0 IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f0810 */
/* 0x000fc80007ffe0ff */
/*0460*/ MOV R16, R15 ; /* 0x0000000f00107202 */
/* 0x000fca0000000f00 */
/*0470*/ @!P1 IMAD.MOV R16, RZ, RZ, -R16 ; /* 0x000000ffff109224 */
/* 0x000fe200078e0a10 */
/*0480*/ @!P2 LOP3.LUT R16, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff10a212 */
/* 0x000fe400078e33ff */
/*0490*/ ISETP.GE.AND P2, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x010fe40003f46270 */
/*04a0*/ I2F.F64 R14, R16 ; /* 0x00000010000e7312 */
/* 0x000ee20000201c00 */
/*04b0*/ IMAD.MOV R17, RZ, RZ, -R16 ; /* 0x000000ffff117224 */
/* 0x000fc800078e0a10 */
/*04c0*/ IMAD R17, R4, R17, R19 ; /* 0x0000001104117224 */
/* 0x000fe200078e0213 */
/*04d0*/ IADD3 R4, P0, R21, c[0x0][0x160], RZ ; /* 0x0000580015047a10 */
/* 0x000fe20007f1e0ff */
/*04e0*/ DFMA R14, R14, R6, R12 ; /* 0x000000060e0e722b */
/* 0x0083e4000000000c */
/*04f0*/ I2F.F64 R12, R17 ; /* 0x00000011000c7312 */
/* 0x002e640000201c00 */
/*0500*/ DMUL R6, R6, 0.5 ; /* 0x3fe0000006067828 */
/* 0x000e8c0000000000 */
/*0510*/ DSETP.GEU.AND P1, PT, |R14|, R6, PT ; /* 0x000000060e00722a */
/* 0x004e8c0003f2e200 */
/*0520*/ FSEL R6, R14, RZ, P1 ; /* 0x000000ff0e067208 */
/* 0x004fe20000800000 */
/*0530*/ DFMA R8, R12, R8, R10 ; /* 0x000000080c08722b */
/* 0x002062000000000a */
/*0540*/ FSEL R7, R15, RZ, P1 ; /* 0x000000ff0f077208 */
/* 0x000fe20000800000 */
/*0550*/ @!P2 BRA 0x680 ; /* 0x000001200000a947 */
/* 0x000fea0003800000 */
/*0560*/ BSSY B0, 0x680 ; /* 0x0000011000007945 */
/* 0x003fe20003800000 */
/*0570*/ IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff187224 */
/* 0x000fe200078e00ff */
/*0580*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fe2000001ff00 */
/*0590*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe2000001ff00 */
/*05a0*/ CS2R R14, SRZ ; /* 0x00000000000e7805 */
/* 0x000fe2000001ff00 */
/*05b0*/ CS2R R16, SRZ ; /* 0x0000000000107805 */
/* 0x000fcc000001ff00 */
/*05c0*/ DADD R14, -R16, R14 ; /* 0x00000000100e7229 */
/* 0x000e22000000010e */
/*05d0*/ IADD3 R24, R24, 0x1, RZ ; /* 0x0000000118187810 */
/* 0x000fc60007ffe0ff */
/*05e0*/ DADD R16, R10, R10 ; /* 0x000000000a107229 */
/* 0x000e62000000000a */
/*05f0*/ ISETP.GE.AND P1, PT, R24, R5, PT ; /* 0x000000051800720c */
/* 0x000fc60003f26270 */
/*0600*/ DADD R10, R8, R14 ; /* 0x00000000080a7229 */
/* 0x001e08000000000e */
/*0610*/ DFMA R12, R16, R12, R6 ; /* 0x0000000c100c722b */
/* 0x002e480000000006 */
/*0620*/ DMUL R14, R10, R10 ; /* 0x0000000a0a0e7228 */
/* 0x001fc80000000000 */
/*0630*/ DMUL R16, R12, R12 ; /* 0x0000000c0c107228 */
/* 0x002e0c0000000000 */
/*0640*/ DADD R22, R14, R16 ; /* 0x000000000e167229 */
/* 0x001e0c0000000010 */
/*0650*/ DSETP.LT.AND P2, PT, R22, 4, PT ; /* 0x401000001600742a */
/* 0x001e1c0003f41000 */
/*0660*/ @!P1 BRA P2, 0x5c0 ; /* 0xffffff5000009947 */
/* 0x001fea000103ffff */
/*0670*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0680*/ ISETP.NE.AND P1, PT, R5, R24, PT ; /* 0x000000180500720c */
/* 0x003fe20003f25270 */
/*0690*/ BSSY B0, 0x9c0 ; /* 0x0000032000007945 */
/* 0x000fe20003800000 */
/*06a0*/ LEA.HI.X.SX32 R5, R21, c[0x0][0x164], 0x1, P0 ; /* 0x0000590015057a11 */
/* 0x000fe400000f0eff */
/*06b0*/ SHF.R.S32.HI R6, RZ, 0x1f, R20 ; /* 0x0000001fff067819 */
/* 0x020fd20000011414 */
/*06c0*/ @!P1 BRA 0x8d0 ; /* 0x0000020000009947 */
/* 0x000fea0003800000 */
/*06d0*/ IABS R8, R20.reuse ; /* 0x0000001400087213 */
/* 0x080fe40000000000 */
/*06e0*/ IABS R9, R20 ; /* 0x0000001400097213 */
/* 0x000fe40000000000 */
/*06f0*/ I2F.U32.RP R6, R8 ; /* 0x0000000800067306 */
/* 0x000e220000209000 */
/*0700*/ ISETP.GE.AND P2, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x000fe40003f46270 */
/*0710*/ IADD3 R9, RZ, -R9, RZ ; /* 0x80000009ff097210 */
/* 0x000fca0007ffe0ff */
/*0720*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0730*/ IADD3 R2, R6, 0xffffffe, RZ ; /* 0x0ffffffe06027810 */
/* 0x001fe40007ffe0ff */
/*0740*/ IABS R6, R24 ; /* 0x0000001800067213 */
/* 0x000fc80000000000 */
/*0750*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0760*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0770*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*0780*/ IMAD R7, R7, R8, RZ ; /* 0x0000000807077224 */
/* 0x000fc800078e02ff */
/*0790*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*07a0*/ MOV R2, 0xc ; /* 0x0000000c00027802 */
/* 0x000fc60000000f00 */
/*07b0*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0009 */
/*07c0*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fc800078e00ff */
/*07d0*/ IMAD R3, R3, R7, R6 ; /* 0x0000000703037224 */
/* 0x000fca00078e0206 */
/*07e0*/ ISETP.GT.U32.AND P0, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f04070 */
/*07f0*/ @!P0 IADD3 R3, R3, -R8, RZ ; /* 0x8000000803038210 */
/* 0x000fe40007ffe0ff */
/*0800*/ ISETP.NE.AND P0, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe40003f05270 */
/*0810*/ ISETP.GT.U32.AND P1, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f24070 */
/*0820*/ @!P1 IMAD.IADD R3, R3, 0x1, -R8 ; /* 0x0000000103039824 */
/* 0x000fc800078e0a08 */
/*0830*/ @!P2 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff03a224 */
/* 0x000fe200078e0a03 */
/*0840*/ @!P0 LOP3.LUT R3, RZ, R20, RZ, 0x33, !PT ; /* 0x00000014ff038212 */
/* 0x000fca00078e33ff */
/*0850*/ IMAD.WIDE R2, R3, R2, c[0x4][0x68] ; /* 0x01001a0003027625 */
/* 0x000fca00078e0202 */
/*0860*/ LDG.E R7, [R2.64] ; /* 0x0000000802077981 */
/* 0x000ea8000c1e1900 */
/*0870*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0041e8000c101108 */
/*0880*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040802097981 */
/* 0x000ea8000c1e1900 */
/*0890*/ STG.E.U8 [R4.64+0x1], R9 ; /* 0x0000010904007986 */
/* 0x0041e8000c101108 */
/*08a0*/ LDG.E R11, [R2.64+0x8] ; /* 0x00000808020b7981 */
/* 0x000ea8000c1e1900 */
/*08b0*/ STG.E.U8 [R4.64+0x2], R11 ; /* 0x0000020b04007986 */
/* 0x0041e2000c101108 */
/*08c0*/ BRA 0x9b0 ; /* 0x000000e000007947 */
/* 0x000fea0003800000 */
/*08d0*/ IMAD.MOV.U32 R9, RZ, RZ, 0xc ; /* 0x0000000cff097424 */
/* 0x000fe400078e00ff */
/*08e0*/ IMAD R7, R6, 0xc, RZ ; /* 0x0000000c06077824 */
/* 0x000fc400078e02ff */
/*08f0*/ IMAD.WIDE.U32 R20, R20, R9, c[0x4][0x68] ; /* 0x01001a0014147625 */
/* 0x000fc800078e0009 */
/*0900*/ IMAD.IADD R21, R21, 0x1, R7 ; /* 0x0000000115157824 */
/* 0x000fcc00078e0207 */
/*0910*/ LDG.E R21, [R20.64] ; /* 0x0000000814157981 */
/* 0x000ea8000c1e1900 */
/*0920*/ STG.E.U8 [R4.64], R21 ; /* 0x0000001504007986 */
/* 0x0041e8000c101108 */
/*0930*/ LDG.E R6, [R2.64] ; /* 0x0000000802067981 */
/* 0x000ea4000c1e1900 */
/*0940*/ IMAD.WIDE R6, R6, R9, c[0x4][0x68] ; /* 0x01001a0006067625 */
/* 0x004fcc00078e0209 */
/*0950*/ LDG.E R7, [R6.64+0x4] ; /* 0x0000040806077981 */
/* 0x000ea8000c1e1900 */
/*0960*/ STG.E.U8 [R4.64+0x1], R7 ; /* 0x0000010704007986 */
/* 0x0041e8000c101108 */
/*0970*/ LDG.E R8, [R2.64] ; /* 0x0000000802087981 */
/* 0x000ea4000c1e1900 */
/*0980*/ IMAD.WIDE R8, R8, R9, c[0x4][0x68] ; /* 0x01001a0008087625 */
/* 0x004fcc00078e0209 */
/*0990*/ LDG.E R9, [R8.64+0x8] ; /* 0x0000080808097981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ STG.E.U8 [R4.64+0x2], R9 ; /* 0x0000020904007986 */
/* 0x0041e4000c101108 */
/*09b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*09c0*/ IADD3 R3, R19, 0x1, RZ ; /* 0x0000000113037810 */
/* 0x000fe20007ffe0ff */
/*09d0*/ BSSY B0, 0xa40 ; /* 0x0000006000007945 */
/* 0x000fe60003800000 */
/*09e0*/ ISETP.NE.AND P0, PT, R3, R18, PT ; /* 0x000000120300720c */
/* 0x000fda0003f05270 */
/*09f0*/ @P0 BRA 0xa30 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0a00*/ ISETP.GT.AND P0, PT, R0, R19, PT ; /* 0x000000130000720c */
/* 0x000fda0003f04270 */
/*0a10*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0a20*/ MOV R3, R0 ; /* 0x0000000000037202 */
/* 0x000fe40000000f00 */
/*0a30*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a40*/ ISETP.GT.AND P0, PT, R3, R0, PT ; /* 0x000000000300720c */
/* 0x000fe20003f04270 */
/*0a50*/ IMAD.MOV.U32 R19, RZ, RZ, R3 ; /* 0x000000ffff137224 */
/* 0x000fd800078e0003 */
/*0a60*/ @!P0 BRA 0x190 ; /* 0xfffff72000008947 */
/* 0x000fea000383ffff */
/*0a70*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a80*/ BRA 0xa80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
// For the CUDA runtime routines (prefixed with "cuda_")
#include <cuda_runtime.h>
#include <cuda.h>
// Device global variables
__device__ double c_x_min;
__device__ double c_x_max;
__device__ double c_y_min;
__device__ double c_y_max;
__device__ double pixel_width;
__device__ double pixel_height;
__device__ int iteration_max = 200;
__device__ int image_size;
__device__ int image_buffer_size;
__device__ int num_threads;
__device__ int th_per_block;
__device__ int pixels_per_thread;
__device__ int gradient_size = 16;
__device__ int colors[17][3] = {
{66, 30, 15},
{25, 7, 26},
{9, 1, 47},
{4, 4, 73},
{0, 7, 100},
{12, 44, 138},
{24, 82, 177},
{57, 125, 209},
{134, 181, 229},
{211, 236, 248},
{241, 233, 191},
{248, 201, 95},
{255, 170, 0},
{204, 128, 0},
{153, 87, 0},
{106, 52, 3},
{16, 16, 16},
};
// Host global variables
dim3 num_blocks, threads_per_block;
int num_blocks_x, th_per_block_x;
int num_blocks_y, th_per_block_y;
int host_image_buffer_size;
unsigned char* image_buffer_host;
int i_x_max;
int i_y_max;
int check (cudaError_t& err, const char* msg) {
if (err != cudaSuccess) {
printf ("%s", msg);
printf (" | Error: %s\n", cudaGetErrorString(err));
return 1;
}
return 0;
}
void print_bad_arguments () {
printf("usage: ./mandelbrot_seq c_x_min c_x_max c_y_min c_y_max"
" image_size NUM_BLOCKS TH_PER_BLOCK \n");
printf("examples with image_size = 11500:\n");
printf(" Full Picture: ./mandelbrot_cuda -2.5 1.5 -2.0 2.0 11500 4 64 \n");
printf(" Seahorse Valley: ./mandelbrot_cuda -0.8 -0.7 0.05 0.15 11500 4 64 \n");
printf(" Elephant Valley: ./mandelbrot_cuda 0.175 0.375 -0.1 0.1 11500 4 64 \n");
printf(" Triple Spiral Valley: ./mandelbrot_cuda -0.188 -0.012 0.554 0.754 11500 4 64 \n");
}
// Get global variables from command line args
void init (int argc, char* argv[]) {
// host variables
double host_c_x_min, host_c_x_max;
double host_c_y_min, host_c_y_max;
int host_image_size;
if (argc < 8) {
print_bad_arguments();
exit(0);
}
else {
num_blocks_y = th_per_block_y = 1;
sscanf(argv[1], "%lf", &host_c_x_min);
sscanf(argv[2], "%lf", &host_c_x_max);
sscanf(argv[3], "%lf", &host_c_y_min);
sscanf(argv[4], "%lf", &host_c_y_max);
sscanf(argv[5], "%d", &host_image_size);
sscanf(argv[6], "%d", &num_blocks_x);
if (argc == 8) {
sscanf(argv[7], "%d", &th_per_block_x);
}
else if (argc == 10) {
sscanf(argv[7], "%d", &num_blocks_y);
sscanf(argv[8], "%d", &th_per_block_x);
sscanf(argv[9], "%d", &th_per_block_y);
}
else {
print_bad_arguments();
exit(0);
}
host_image_buffer_size = host_image_size * host_image_size;
int host_th_per_block = th_per_block_x * th_per_block_y;
int host_num_threads = host_th_per_block * num_blocks_x * num_blocks_y;
int host_pixels_per_thread = host_image_buffer_size / host_num_threads;
i_x_max = host_image_size;
i_y_max = host_image_size;
double host_pixel_width = (host_c_x_max - host_c_x_min) / i_x_max;
double host_pixel_height = (host_c_y_max - host_c_y_min) / i_y_max;
// copy host variables to device
cudaError_t err = cudaSuccess;
cudaMemcpyToSymbol(c_x_min, &host_c_x_min, sizeof(double));
cudaMemcpyToSymbol(c_x_max, &host_c_x_max, sizeof(double));
cudaMemcpyToSymbol(c_y_min, &host_c_y_min, sizeof(double));
cudaMemcpyToSymbol(c_y_max, &host_c_y_max, sizeof(double));
cudaMemcpyToSymbol(image_size, &host_image_size, sizeof(int));
cudaMemcpyToSymbol(num_threads, &host_num_threads, sizeof(int));
cudaMemcpyToSymbol(th_per_block, &host_th_per_block, sizeof(int));
cudaMemcpyToSymbol(pixel_width, &host_pixel_width, sizeof(double));
cudaMemcpyToSymbol(pixel_height, &host_pixel_height, sizeof(double));
cudaMemcpyToSymbol(pixels_per_thread, &host_pixels_per_thread, sizeof(int));
cudaMemcpyToSymbol(image_buffer_size, &host_image_buffer_size, sizeof(int));
err = cudaGetLastError();
if (check(err, "Failed to copy command line args to device"))
exit(EXIT_FAILURE);
};
};
__device__
void update_rgb_buffer(unsigned char* image_buffer_device, int iteration, int pix) {
int color;
if (iteration == iteration_max) {
image_buffer_device[pix * 3 + 0] = colors[gradient_size][0];
image_buffer_device[pix * 3 + 1] = colors[gradient_size][1];
image_buffer_device[pix * 3 + 2] = colors[gradient_size][2];
} else {
color = iteration % gradient_size;
image_buffer_device[pix * 3 + 0] = colors[color][0];
image_buffer_device[pix * 3 + 1] = colors[color][1];
image_buffer_device[pix * 3 + 2] = colors[color][2];
};
};
__global__
void compute_mandelbrot(unsigned char* image_buffer_device) {
double z_x;
double z_y;
double z_x_squared;
double z_y_squared;
double escape_radius_squared = 4;
int iteration;
int i_x;
int i_y;
double c_x;
double c_y;
// Calculates pixel where current thread will start its work
int my_block = blockIdx.x + gridDim.x * blockIdx.y;
int my_thread_in_block = threadIdx.x + blockDim.x * threadIdx.y;
int my_thread = my_block * th_per_block + my_thread_in_block;
/* what thread will process each pixel ?
*
* Example: image 5x5 -> buffer_size = 25
* 3 blocks of 3 threads -> 9 threads
*
* 2 4 7 - -
* 1 4 6 - -
* 1 3 6 8 -
* 0 3 5 8 -
* 0 2 5 7 -
*
* and the remaining pixels we process separetedly,
* each thread process its remaining pixel in the end
*
* 2 4 7 5 0
* 1 4 6 6 1
* 1 3 6 8 2
* 0 3 5 8 3
* 0 2 5 7 4
*/
// Its easier to process by pixels instead of by row-collunm
int pix = my_thread * pixels_per_thread;
int end_pixel = pix + pixels_per_thread;
int my_rem_pixel = image_buffer_size - my_thread - 1;
while (pix <= my_rem_pixel) {
i_y = pix / image_size;
i_x = pix % image_size;
c_y = c_y_min + i_y * pixel_height;
if (fabs(c_y) < pixel_height / 2) {
c_y = 0.0;
};
c_x = c_x_min + i_x * pixel_width;
z_x = 0.0;
z_y = 0.0;
z_x_squared = 0.0;
z_y_squared = 0.0;
for (iteration = 0;
iteration < iteration_max && \
((z_x_squared + z_y_squared) < escape_radius_squared);
iteration++) {
z_y = 2 * z_x * z_y + c_y;
z_x = z_x_squared - z_y_squared + c_x;
z_x_squared = z_x * z_x;
z_y_squared = z_y * z_y;
};
update_rgb_buffer(image_buffer_device, iteration, pix);
pix++;
// Treat remaining pixel
if (pix == end_pixel) {
if (my_rem_pixel >= pix) pix = my_rem_pixel;
else break;
}
}
}
void allocate_image_buffer(unsigned char** image_buffer_device, size_t size) {
// Our buffer, instead of a matrix, will be a continuous array
// Allocate host memory
image_buffer_host = (unsigned char*)malloc(sizeof(unsigned char) * size);
// Allocate device memory
cudaError_t err = cudaSuccess;
err = cudaMalloc((void**)(image_buffer_device), size);
// Test alloc success
if (image_buffer_host == NULL) {
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
if (check(err, "Failed to allocate device image buffer"))
exit(EXIT_FAILURE);
};
void write_to_file() {
FILE* file;
const char* filename = "output.ppm";
const char* comment = "# ";
int max_color_component_value = 255;
file = fopen(filename, "wb");
fprintf(file, "P6\n %s\n %d\n %d\n %d\n", comment,
i_x_max, i_y_max, max_color_component_value);
for (int i = 0; i < host_image_buffer_size; i++) {
fwrite(image_buffer_host + 3*i, 1, 3, file);
};
fclose(file);
};
int main(int argc, char* argv[]) {
init(argc, argv);
cudaError_t err;
int rgb_size = 3;
size_t size = host_image_buffer_size * rgb_size;
unsigned char* image_buffer_device;
allocate_image_buffer(&image_buffer_device, size);
// Launch compute_mandelbrot CUDA Kernel
num_blocks = dim3(num_blocks_x, num_blocks_y);
threads_per_block = dim3(th_per_block_x, th_per_block_y);
compute_mandelbrot<<<num_blocks, threads_per_block>>>(image_buffer_device);
cudaDeviceSynchronize();
err = cudaGetLastError();
if (check(err, "Failed to launch compute_mandelbrot kernel"))
exit(EXIT_FAILURE);
// Copy the device result vector in device memory to the host result vector
// in host memory.
err = cudaMemcpy(image_buffer_host, image_buffer_device, size,
cudaMemcpyDeviceToHost);
if (check(err, "Failed to copy vector from device to host"))
exit(EXIT_FAILURE);
// Free device global memory
err = cudaFree(image_buffer_device);
if (check(err, "Failed to free device vector"))
exit(EXIT_FAILURE);
write_to_file();
// Free host memory
free(image_buffer_host);
return 0;
}
|
.file "tmpxft_000b2ca1_00000000-6_mandelbrot_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s"
.LC1:
.string " | Error: %s\n"
.text
.globl _Z5checkR9cudaErrorPKc
.type _Z5checkR9cudaErrorPKc, @function
_Z5checkR9cudaErrorPKc:
.LFB2057:
.cfi_startproc
endbr64
movl $0, %eax
cmpl $0, (%rdi)
jne .L10
ret
.L10:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq %rsi, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl (%rbx), %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z5checkR9cudaErrorPKc, .-_Z5checkR9cudaErrorPKc
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "usage: ./mandelbrot_seq c_x_min c_x_max c_y_min c_y_max image_size NUM_BLOCKS TH_PER_BLOCK \n"
.align 8
.LC3:
.string "examples with image_size = 11500:\n"
.align 8
.LC4:
.string " Full Picture: ./mandelbrot_cuda -2.5 1.5 -2.0 2.0 11500 4 64 \n"
.align 8
.LC5:
.string " Seahorse Valley: ./mandelbrot_cuda -0.8 -0.7 0.05 0.15 11500 4 64 \n"
.align 8
.LC6:
.string " Elephant Valley: ./mandelbrot_cuda 0.175 0.375 -0.1 0.1 11500 4 64 \n"
.align 8
.LC7:
.string " Triple Spiral Valley: ./mandelbrot_cuda -0.188 -0.012 0.554 0.754 11500 4 64 \n"
.text
.globl _Z19print_bad_argumentsv
.type _Z19print_bad_argumentsv, @function
_Z19print_bad_argumentsv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z19print_bad_argumentsv, .-_Z19print_bad_argumentsv
.section .rodata.str1.1
.LC8:
.string "%lf"
.LC9:
.string "%d"
.section .rodata.str1.8
.align 8
.LC10:
.string "Failed to copy command line args to device"
.text
.globl _Z4initiPPc
.type _Z4initiPPc, @function
_Z4initiPPc:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $7, %edi
jg .L14
call _Z19print_bad_argumentsv
movl $0, %edi
call exit@PLT
.L14:
movl %edi, %r12d
movq %rsi, %rbx
movl $1, th_per_block_y(%rip)
movl $1, num_blocks_y(%rip)
leaq 24(%rsp), %rdx
movq 8(%rsi), %rdi
leaq .LC8(%rip), %rbp
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
leaq 32(%rsp), %rdx
movq 16(%rbx), %rdi
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
leaq 40(%rsp), %rdx
movq 24(%rbx), %rdi
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
leaq 48(%rsp), %rdx
movq 32(%rbx), %rdi
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
leaq 4(%rsp), %rdx
movq 40(%rbx), %rdi
leaq .LC9(%rip), %rbp
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
movq 48(%rbx), %rdi
leaq num_blocks_x(%rip), %rdx
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
cmpl $8, %r12d
je .L21
cmpl $10, %r12d
je .L22
call _Z19print_bad_argumentsv
movl $0, %edi
call exit@PLT
.L21:
movq 56(%rbx), %rdi
leaq th_per_block_x(%rip), %rdx
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
jmp .L16
.L22:
movq 56(%rbx), %rdi
leaq num_blocks_y(%rip), %rdx
leaq .LC9(%rip), %rbp
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
movq 64(%rbx), %rdi
leaq th_per_block_x(%rip), %rdx
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
movq 72(%rbx), %rdi
leaq th_per_block_y(%rip), %rdx
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
.L16:
movl 4(%rsp), %esi
movl %esi, %eax
imull %esi, %eax
movl %eax, host_image_buffer_size(%rip)
movl th_per_block_x(%rip), %ecx
imull th_per_block_y(%rip), %ecx
movl %ecx, 8(%rsp)
imull num_blocks_x(%rip), %ecx
imull num_blocks_y(%rip), %ecx
movl %ecx, 12(%rsp)
cltd
idivl %ecx
movl %eax, 16(%rsp)
movl %esi, i_x_max(%rip)
movl %esi, i_y_max(%rip)
pxor %xmm1, %xmm1
cvtsi2sdl %esi, %xmm1
movsd 32(%rsp), %xmm0
subsd 24(%rsp), %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, 56(%rsp)
movsd 48(%rsp), %xmm0
subsd 40(%rsp), %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, 64(%rsp)
leaq 24(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $8, %edx
leaq _ZL7c_x_min(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 32(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $8, %edx
leaq _ZL7c_x_max(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 40(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $8, %edx
leaq _ZL7c_y_min(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 48(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $8, %edx
leaq _ZL7c_y_max(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 4(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL10image_size(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 12(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL11num_threads(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 8(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL12th_per_block(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 56(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $8, %edx
leaq _ZL11pixel_width(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 64(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $8, %edx
leaq _ZL12pixel_height(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 16(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL17pixels_per_thread(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq host_image_buffer_size(%rip), %rsi
leaq _ZL17image_buffer_size(%rip), %rdi
call cudaMemcpyToSymbol@PLT
call cudaGetLastError@PLT
movl %eax, 20(%rsp)
leaq 20(%rsp), %rdi
leaq .LC10(%rip), %rsi
call _Z5checkR9cudaErrorPKc
testl %eax, %eax
jne .L23
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $1, %edi
call exit@PLT
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z4initiPPc, .-_Z4initiPPc
.globl _Z17update_rgb_bufferPhii
.type _Z17update_rgb_bufferPhii, @function
_Z17update_rgb_bufferPhii:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z17update_rgb_bufferPhii, .-_Z17update_rgb_bufferPhii
.section .rodata.str1.8
.align 8
.LC11:
.string "Failed to allocate host vectors!\n"
.align 8
.LC12:
.string "Failed to allocate device image buffer"
.text
.globl _Z21allocate_image_bufferPPhm
.type _Z21allocate_image_bufferPPhm, @function
_Z21allocate_image_bufferPPhm:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsi, %rdi
call malloc@PLT
movq %rax, image_buffer_host(%rip)
movq %rbx, %rsi
movq %rbp, %rdi
call cudaMalloc@PLT
movl %eax, 4(%rsp)
cmpq $0, image_buffer_host(%rip)
je .L32
leaq 4(%rsp), %rdi
leaq .LC12(%rip), %rsi
call _Z5checkR9cudaErrorPKc
testl %eax, %eax
jne .L33
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
movl $1, %edi
call exit@PLT
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z21allocate_image_bufferPPhm, .-_Z21allocate_image_bufferPPhm
.section .rodata.str1.1
.LC13:
.string "wb"
.LC14:
.string "output.ppm"
.LC15:
.string "# "
.LC16:
.string "P6\n %s\n %d\n %d\n %d\n"
.text
.globl _Z13write_to_filev
.type _Z13write_to_filev, @function
_Z13write_to_filev:
.LFB2062:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
leaq .LC13(%rip), %rsi
leaq .LC14(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
subq $8, %rsp
.cfi_def_cfa_offset 40
pushq $255
.cfi_def_cfa_offset 48
movl i_y_max(%rip), %r9d
movl i_x_max(%rip), %r8d
leaq .LC15(%rip), %rcx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 32
cmpl $0, host_image_buffer_size(%rip)
jle .L36
movl $0, %ebx
.L37:
leaq (%rbx,%rbx,2), %rdi
addq image_buffer_host(%rip), %rdi
movq %rbp, %rcx
movl $3, %edx
movl $1, %esi
call fwrite@PLT
addq $1, %rbx
cmpl %ebx, host_image_buffer_size(%rip)
jg .L37
.L36:
movq %rbp, %rdi
call fclose@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z13write_to_filev, .-_Z13write_to_filev
.globl _Z38__device_stub__Z18compute_mandelbrotPhPh
.type _Z38__device_stub__Z18compute_mandelbrotPhPh, @function
_Z38__device_stub__Z18compute_mandelbrotPhPh:
.LFB2088:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L44
.L40:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L45
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18compute_mandelbrotPh(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L40
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z38__device_stub__Z18compute_mandelbrotPhPh, .-_Z38__device_stub__Z18compute_mandelbrotPhPh
.globl _Z18compute_mandelbrotPh
.type _Z18compute_mandelbrotPh, @function
_Z18compute_mandelbrotPh:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z18compute_mandelbrotPhPh
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z18compute_mandelbrotPh, .-_Z18compute_mandelbrotPh
.section .rodata.str1.8
.align 8
.LC17:
.string "Failed to launch compute_mandelbrot kernel"
.align 8
.LC18:
.string "Failed to copy vector from device to host"
.section .rodata.str1.1
.LC19:
.string "Failed to free device vector"
.text
.globl main
.type main, @function
main:
.LFB2063:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
call _Z4initiPPc
movl host_image_buffer_size(%rip), %eax
leal (%rax,%rax,2), %ebx
movslq %ebx, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call _Z21allocate_image_bufferPPhm
movl num_blocks_x(%rip), %eax
movl %eax, num_blocks(%rip)
movl num_blocks_y(%rip), %eax
movl %eax, 4+num_blocks(%rip)
movl $1, 8+num_blocks(%rip)
movl th_per_block_x(%rip), %eax
movl %eax, threads_per_block(%rip)
movl th_per_block_y(%rip), %eax
movl %eax, 4+threads_per_block(%rip)
movl $1, 8+threads_per_block(%rip)
movl $0, %r9d
movl $0, %r8d
movq threads_per_block(%rip), %rdx
movl $1, %ecx
movq num_blocks(%rip), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L49:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
movl %eax, 12(%rsp)
leaq 12(%rsp), %rdi
leaq .LC17(%rip), %rsi
call _Z5checkR9cudaErrorPKc
testl %eax, %eax
jne .L56
movl $2, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq image_buffer_host(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, 12(%rsp)
leaq 12(%rsp), %rdi
leaq .LC18(%rip), %rsi
call _Z5checkR9cudaErrorPKc
testl %eax, %eax
jne .L57
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, 12(%rsp)
leaq 12(%rsp), %rdi
leaq .LC19(%rip), %rsi
call _Z5checkR9cudaErrorPKc
testl %eax, %eax
jne .L58
call _Z13write_to_filev
movq image_buffer_host(%rip), %rdi
call free@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L59
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
movq 16(%rsp), %rdi
call _Z38__device_stub__Z18compute_mandelbrotPhPh
jmp .L49
.L56:
movl $1, %edi
call exit@PLT
.L57:
movl $1, %edi
call exit@PLT
.L58:
movl $1, %edi
call exit@PLT
.L59:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size main, .-main
.section .rodata.str1.1
.LC20:
.string "_Z18compute_mandelbrotPh"
.LC21:
.string "c_x_min"
.LC22:
.string "c_x_max"
.LC23:
.string "c_y_min"
.LC24:
.string "c_y_max"
.LC25:
.string "pixel_width"
.LC26:
.string "pixel_height"
.LC27:
.string "iteration_max"
.LC28:
.string "image_size"
.LC29:
.string "image_buffer_size"
.LC30:
.string "num_threads"
.LC31:
.string "th_per_block"
.LC32:
.string "pixels_per_thread"
.LC33:
.string "gradient_size"
.LC34:
.string "colors"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z18compute_mandelbrotPh(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7c_x_min(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7c_x_max(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC23(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7c_y_min(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC24(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7c_y_max(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC25(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11pixel_width(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC26(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12pixel_height(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC27(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13iteration_max(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC28(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10image_size(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC29(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17image_buffer_size(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC30(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11num_threads(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC31(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12th_per_block(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC32(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17pixels_per_thread(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC33(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13gradient_size(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $204, %r9d
movl $0, %r8d
leaq .LC34(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6colors(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl i_y_max
.bss
.align 4
.type i_y_max, @object
.size i_y_max, 4
i_y_max:
.zero 4
.globl i_x_max
.align 4
.type i_x_max, @object
.size i_x_max, 4
i_x_max:
.zero 4
.globl image_buffer_host
.align 8
.type image_buffer_host, @object
.size image_buffer_host, 8
image_buffer_host:
.zero 8
.globl host_image_buffer_size
.align 4
.type host_image_buffer_size, @object
.size host_image_buffer_size, 4
host_image_buffer_size:
.zero 4
.globl th_per_block_y
.align 4
.type th_per_block_y, @object
.size th_per_block_y, 4
th_per_block_y:
.zero 4
.globl num_blocks_y
.align 4
.type num_blocks_y, @object
.size num_blocks_y, 4
num_blocks_y:
.zero 4
.globl th_per_block_x
.align 4
.type th_per_block_x, @object
.size th_per_block_x, 4
th_per_block_x:
.zero 4
.globl num_blocks_x
.align 4
.type num_blocks_x, @object
.size num_blocks_x, 4
num_blocks_x:
.zero 4
.globl threads_per_block
.data
.align 8
.type threads_per_block, @object
.size threads_per_block, 12
threads_per_block:
.long 1
.long 1
.long 1
.globl num_blocks
.align 8
.type num_blocks, @object
.size num_blocks, 12
num_blocks:
.long 1
.long 1
.long 1
.local _ZL6colors
.comm _ZL6colors,204,32
.local _ZL13gradient_size
.comm _ZL13gradient_size,4,4
.local _ZL17pixels_per_thread
.comm _ZL17pixels_per_thread,4,4
.local _ZL12th_per_block
.comm _ZL12th_per_block,4,4
.local _ZL11num_threads
.comm _ZL11num_threads,4,4
.local _ZL17image_buffer_size
.comm _ZL17image_buffer_size,4,4
.local _ZL10image_size
.comm _ZL10image_size,4,4
.local _ZL13iteration_max
.comm _ZL13iteration_max,4,4
.local _ZL12pixel_height
.comm _ZL12pixel_height,8,8
.local _ZL11pixel_width
.comm _ZL11pixel_width,8,8
.local _ZL7c_y_max
.comm _ZL7c_y_max,8,8
.local _ZL7c_y_min
.comm _ZL7c_y_min,8,8
.local _ZL7c_x_max
.comm _ZL7c_x_max,8,8
.local _ZL7c_x_min
.comm _ZL7c_x_min,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
// For the CUDA runtime routines (prefixed with "cuda_")
#include <cuda_runtime.h>
#include <cuda.h>
// Device global variables
__device__ double c_x_min;
__device__ double c_x_max;
__device__ double c_y_min;
__device__ double c_y_max;
__device__ double pixel_width;
__device__ double pixel_height;
__device__ int iteration_max = 200;
__device__ int image_size;
__device__ int image_buffer_size;
__device__ int num_threads;
__device__ int th_per_block;
__device__ int pixels_per_thread;
__device__ int gradient_size = 16;
__device__ int colors[17][3] = {
{66, 30, 15},
{25, 7, 26},
{9, 1, 47},
{4, 4, 73},
{0, 7, 100},
{12, 44, 138},
{24, 82, 177},
{57, 125, 209},
{134, 181, 229},
{211, 236, 248},
{241, 233, 191},
{248, 201, 95},
{255, 170, 0},
{204, 128, 0},
{153, 87, 0},
{106, 52, 3},
{16, 16, 16},
};
// Host global variables
dim3 num_blocks, threads_per_block;
int num_blocks_x, th_per_block_x;
int num_blocks_y, th_per_block_y;
int host_image_buffer_size;
unsigned char* image_buffer_host;
int i_x_max;
int i_y_max;
int check (cudaError_t& err, const char* msg) {
if (err != cudaSuccess) {
printf ("%s", msg);
printf (" | Error: %s\n", cudaGetErrorString(err));
return 1;
}
return 0;
}
void print_bad_arguments () {
printf("usage: ./mandelbrot_seq c_x_min c_x_max c_y_min c_y_max"
" image_size NUM_BLOCKS TH_PER_BLOCK \n");
printf("examples with image_size = 11500:\n");
printf(" Full Picture: ./mandelbrot_cuda -2.5 1.5 -2.0 2.0 11500 4 64 \n");
printf(" Seahorse Valley: ./mandelbrot_cuda -0.8 -0.7 0.05 0.15 11500 4 64 \n");
printf(" Elephant Valley: ./mandelbrot_cuda 0.175 0.375 -0.1 0.1 11500 4 64 \n");
printf(" Triple Spiral Valley: ./mandelbrot_cuda -0.188 -0.012 0.554 0.754 11500 4 64 \n");
}
// Get global variables from command line args
void init (int argc, char* argv[]) {
// host variables
double host_c_x_min, host_c_x_max;
double host_c_y_min, host_c_y_max;
int host_image_size;
if (argc < 8) {
print_bad_arguments();
exit(0);
}
else {
num_blocks_y = th_per_block_y = 1;
sscanf(argv[1], "%lf", &host_c_x_min);
sscanf(argv[2], "%lf", &host_c_x_max);
sscanf(argv[3], "%lf", &host_c_y_min);
sscanf(argv[4], "%lf", &host_c_y_max);
sscanf(argv[5], "%d", &host_image_size);
sscanf(argv[6], "%d", &num_blocks_x);
if (argc == 8) {
sscanf(argv[7], "%d", &th_per_block_x);
}
else if (argc == 10) {
sscanf(argv[7], "%d", &num_blocks_y);
sscanf(argv[8], "%d", &th_per_block_x);
sscanf(argv[9], "%d", &th_per_block_y);
}
else {
print_bad_arguments();
exit(0);
}
host_image_buffer_size = host_image_size * host_image_size;
int host_th_per_block = th_per_block_x * th_per_block_y;
int host_num_threads = host_th_per_block * num_blocks_x * num_blocks_y;
int host_pixels_per_thread = host_image_buffer_size / host_num_threads;
i_x_max = host_image_size;
i_y_max = host_image_size;
double host_pixel_width = (host_c_x_max - host_c_x_min) / i_x_max;
double host_pixel_height = (host_c_y_max - host_c_y_min) / i_y_max;
// copy host variables to device
cudaError_t err = cudaSuccess;
cudaMemcpyToSymbol(c_x_min, &host_c_x_min, sizeof(double));
cudaMemcpyToSymbol(c_x_max, &host_c_x_max, sizeof(double));
cudaMemcpyToSymbol(c_y_min, &host_c_y_min, sizeof(double));
cudaMemcpyToSymbol(c_y_max, &host_c_y_max, sizeof(double));
cudaMemcpyToSymbol(image_size, &host_image_size, sizeof(int));
cudaMemcpyToSymbol(num_threads, &host_num_threads, sizeof(int));
cudaMemcpyToSymbol(th_per_block, &host_th_per_block, sizeof(int));
cudaMemcpyToSymbol(pixel_width, &host_pixel_width, sizeof(double));
cudaMemcpyToSymbol(pixel_height, &host_pixel_height, sizeof(double));
cudaMemcpyToSymbol(pixels_per_thread, &host_pixels_per_thread, sizeof(int));
cudaMemcpyToSymbol(image_buffer_size, &host_image_buffer_size, sizeof(int));
err = cudaGetLastError();
if (check(err, "Failed to copy command line args to device"))
exit(EXIT_FAILURE);
};
};
__device__
void update_rgb_buffer(unsigned char* image_buffer_device, int iteration, int pix) {
int color;
if (iteration == iteration_max) {
image_buffer_device[pix * 3 + 0] = colors[gradient_size][0];
image_buffer_device[pix * 3 + 1] = colors[gradient_size][1];
image_buffer_device[pix * 3 + 2] = colors[gradient_size][2];
} else {
color = iteration % gradient_size;
image_buffer_device[pix * 3 + 0] = colors[color][0];
image_buffer_device[pix * 3 + 1] = colors[color][1];
image_buffer_device[pix * 3 + 2] = colors[color][2];
};
};
__global__
void compute_mandelbrot(unsigned char* image_buffer_device) {
double z_x;
double z_y;
double z_x_squared;
double z_y_squared;
double escape_radius_squared = 4;
int iteration;
int i_x;
int i_y;
double c_x;
double c_y;
// Calculates pixel where current thread will start its work
int my_block = blockIdx.x + gridDim.x * blockIdx.y;
int my_thread_in_block = threadIdx.x + blockDim.x * threadIdx.y;
int my_thread = my_block * th_per_block + my_thread_in_block;
/* what thread will process each pixel ?
*
* Example: image 5x5 -> buffer_size = 25
* 3 blocks of 3 threads -> 9 threads
*
* 2 4 7 - -
* 1 4 6 - -
* 1 3 6 8 -
* 0 3 5 8 -
* 0 2 5 7 -
*
* and the remaining pixels we process separetedly,
* each thread process its remaining pixel in the end
*
* 2 4 7 5 0
* 1 4 6 6 1
* 1 3 6 8 2
* 0 3 5 8 3
* 0 2 5 7 4
*/
// Its easier to process by pixels instead of by row-collunm
int pix = my_thread * pixels_per_thread;
int end_pixel = pix + pixels_per_thread;
int my_rem_pixel = image_buffer_size - my_thread - 1;
while (pix <= my_rem_pixel) {
i_y = pix / image_size;
i_x = pix % image_size;
c_y = c_y_min + i_y * pixel_height;
if (fabs(c_y) < pixel_height / 2) {
c_y = 0.0;
};
c_x = c_x_min + i_x * pixel_width;
z_x = 0.0;
z_y = 0.0;
z_x_squared = 0.0;
z_y_squared = 0.0;
for (iteration = 0;
iteration < iteration_max && \
((z_x_squared + z_y_squared) < escape_radius_squared);
iteration++) {
z_y = 2 * z_x * z_y + c_y;
z_x = z_x_squared - z_y_squared + c_x;
z_x_squared = z_x * z_x;
z_y_squared = z_y * z_y;
};
update_rgb_buffer(image_buffer_device, iteration, pix);
pix++;
// Treat remaining pixel
if (pix == end_pixel) {
if (my_rem_pixel >= pix) pix = my_rem_pixel;
else break;
}
}
}
void allocate_image_buffer(unsigned char** image_buffer_device, size_t size) {
// Our buffer, instead of a matrix, will be a continuous array
// Allocate host memory
image_buffer_host = (unsigned char*)malloc(sizeof(unsigned char) * size);
// Allocate device memory
cudaError_t err = cudaSuccess;
err = cudaMalloc((void**)(image_buffer_device), size);
// Test alloc success
if (image_buffer_host == NULL) {
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
if (check(err, "Failed to allocate device image buffer"))
exit(EXIT_FAILURE);
};
void write_to_file() {
FILE* file;
const char* filename = "output.ppm";
const char* comment = "# ";
int max_color_component_value = 255;
file = fopen(filename, "wb");
fprintf(file, "P6\n %s\n %d\n %d\n %d\n", comment,
i_x_max, i_y_max, max_color_component_value);
for (int i = 0; i < host_image_buffer_size; i++) {
fwrite(image_buffer_host + 3*i, 1, 3, file);
};
fclose(file);
};
int main(int argc, char* argv[]) {
init(argc, argv);
cudaError_t err;
int rgb_size = 3;
size_t size = host_image_buffer_size * rgb_size;
unsigned char* image_buffer_device;
allocate_image_buffer(&image_buffer_device, size);
// Launch compute_mandelbrot CUDA Kernel
num_blocks = dim3(num_blocks_x, num_blocks_y);
threads_per_block = dim3(th_per_block_x, th_per_block_y);
compute_mandelbrot<<<num_blocks, threads_per_block>>>(image_buffer_device);
cudaDeviceSynchronize();
err = cudaGetLastError();
if (check(err, "Failed to launch compute_mandelbrot kernel"))
exit(EXIT_FAILURE);
// Copy the device result vector in device memory to the host result vector
// in host memory.
err = cudaMemcpy(image_buffer_host, image_buffer_device, size,
cudaMemcpyDeviceToHost);
if (check(err, "Failed to copy vector from device to host"))
exit(EXIT_FAILURE);
// Free device global memory
err = cudaFree(image_buffer_device);
if (check(err, "Failed to free device vector"))
exit(EXIT_FAILURE);
write_to_file();
// Free host memory
free(image_buffer_host);
return 0;
}
|
#include <stdio.h>
// For the CUDA runtime routines (prefixed with "cuda_")
#include <hip/hip_runtime.h>
// Device global variables
__device__ double c_x_min;
__device__ double c_x_max;
__device__ double c_y_min;
__device__ double c_y_max;
__device__ double pixel_width;
__device__ double pixel_height;
__device__ int iteration_max = 200;
__device__ int image_size;
__device__ int image_buffer_size;
__device__ int num_threads;
__device__ int th_per_block;
__device__ int pixels_per_thread;
__device__ int gradient_size = 16;
__device__ int colors[17][3] = {
{66, 30, 15},
{25, 7, 26},
{9, 1, 47},
{4, 4, 73},
{0, 7, 100},
{12, 44, 138},
{24, 82, 177},
{57, 125, 209},
{134, 181, 229},
{211, 236, 248},
{241, 233, 191},
{248, 201, 95},
{255, 170, 0},
{204, 128, 0},
{153, 87, 0},
{106, 52, 3},
{16, 16, 16},
};
// Host global variables
dim3 num_blocks, threads_per_block;
int num_blocks_x, th_per_block_x;
int num_blocks_y, th_per_block_y;
int host_image_buffer_size;
unsigned char* image_buffer_host;
int i_x_max;
int i_y_max;
int check (hipError_t& err, const char* msg) {
if (err != hipSuccess) {
printf ("%s", msg);
printf (" | Error: %s\n", hipGetErrorString(err));
return 1;
}
return 0;
}
void print_bad_arguments () {
printf("usage: ./mandelbrot_seq c_x_min c_x_max c_y_min c_y_max"
" image_size NUM_BLOCKS TH_PER_BLOCK \n");
printf("examples with image_size = 11500:\n");
printf(" Full Picture: ./mandelbrot_cuda -2.5 1.5 -2.0 2.0 11500 4 64 \n");
printf(" Seahorse Valley: ./mandelbrot_cuda -0.8 -0.7 0.05 0.15 11500 4 64 \n");
printf(" Elephant Valley: ./mandelbrot_cuda 0.175 0.375 -0.1 0.1 11500 4 64 \n");
printf(" Triple Spiral Valley: ./mandelbrot_cuda -0.188 -0.012 0.554 0.754 11500 4 64 \n");
}
// Get global variables from command line args
void init (int argc, char* argv[]) {
// host variables
double host_c_x_min, host_c_x_max;
double host_c_y_min, host_c_y_max;
int host_image_size;
if (argc < 8) {
print_bad_arguments();
exit(0);
}
else {
num_blocks_y = th_per_block_y = 1;
sscanf(argv[1], "%lf", &host_c_x_min);
sscanf(argv[2], "%lf", &host_c_x_max);
sscanf(argv[3], "%lf", &host_c_y_min);
sscanf(argv[4], "%lf", &host_c_y_max);
sscanf(argv[5], "%d", &host_image_size);
sscanf(argv[6], "%d", &num_blocks_x);
if (argc == 8) {
sscanf(argv[7], "%d", &th_per_block_x);
}
else if (argc == 10) {
sscanf(argv[7], "%d", &num_blocks_y);
sscanf(argv[8], "%d", &th_per_block_x);
sscanf(argv[9], "%d", &th_per_block_y);
}
else {
print_bad_arguments();
exit(0);
}
host_image_buffer_size = host_image_size * host_image_size;
int host_th_per_block = th_per_block_x * th_per_block_y;
int host_num_threads = host_th_per_block * num_blocks_x * num_blocks_y;
int host_pixels_per_thread = host_image_buffer_size / host_num_threads;
i_x_max = host_image_size;
i_y_max = host_image_size;
double host_pixel_width = (host_c_x_max - host_c_x_min) / i_x_max;
double host_pixel_height = (host_c_y_max - host_c_y_min) / i_y_max;
// copy host variables to device
hipError_t err = hipSuccess;
hipMemcpyToSymbol(HIP_SYMBOL(c_x_min), &host_c_x_min, sizeof(double));
hipMemcpyToSymbol(HIP_SYMBOL(c_x_max), &host_c_x_max, sizeof(double));
hipMemcpyToSymbol(HIP_SYMBOL(c_y_min), &host_c_y_min, sizeof(double));
hipMemcpyToSymbol(HIP_SYMBOL(c_y_max), &host_c_y_max, sizeof(double));
hipMemcpyToSymbol(HIP_SYMBOL(image_size), &host_image_size, sizeof(int));
hipMemcpyToSymbol(HIP_SYMBOL(num_threads), &host_num_threads, sizeof(int));
hipMemcpyToSymbol(HIP_SYMBOL(th_per_block), &host_th_per_block, sizeof(int));
hipMemcpyToSymbol(HIP_SYMBOL(pixel_width), &host_pixel_width, sizeof(double));
hipMemcpyToSymbol(HIP_SYMBOL(pixel_height), &host_pixel_height, sizeof(double));
hipMemcpyToSymbol(HIP_SYMBOL(pixels_per_thread), &host_pixels_per_thread, sizeof(int));
hipMemcpyToSymbol(HIP_SYMBOL(image_buffer_size), &host_image_buffer_size, sizeof(int));
err = hipGetLastError();
if (check(err, "Failed to copy command line args to device"))
exit(EXIT_FAILURE);
};
};
__device__
void update_rgb_buffer(unsigned char* image_buffer_device, int iteration, int pix) {
int color;
if (iteration == iteration_max) {
image_buffer_device[pix * 3 + 0] = colors[gradient_size][0];
image_buffer_device[pix * 3 + 1] = colors[gradient_size][1];
image_buffer_device[pix * 3 + 2] = colors[gradient_size][2];
} else {
color = iteration % gradient_size;
image_buffer_device[pix * 3 + 0] = colors[color][0];
image_buffer_device[pix * 3 + 1] = colors[color][1];
image_buffer_device[pix * 3 + 2] = colors[color][2];
};
};
__global__
void compute_mandelbrot(unsigned char* image_buffer_device) {
double z_x;
double z_y;
double z_x_squared;
double z_y_squared;
double escape_radius_squared = 4;
int iteration;
int i_x;
int i_y;
double c_x;
double c_y;
// Calculates pixel where current thread will start its work
int my_block = blockIdx.x + gridDim.x * blockIdx.y;
int my_thread_in_block = threadIdx.x + blockDim.x * threadIdx.y;
int my_thread = my_block * th_per_block + my_thread_in_block;
/* what thread will process each pixel ?
*
* Example: image 5x5 -> buffer_size = 25
* 3 blocks of 3 threads -> 9 threads
*
* 2 4 7 - -
* 1 4 6 - -
* 1 3 6 8 -
* 0 3 5 8 -
* 0 2 5 7 -
*
* and the remaining pixels we process separetedly,
* each thread process its remaining pixel in the end
*
* 2 4 7 5 0
* 1 4 6 6 1
* 1 3 6 8 2
* 0 3 5 8 3
* 0 2 5 7 4
*/
// Its easier to process by pixels instead of by row-collunm
int pix = my_thread * pixels_per_thread;
int end_pixel = pix + pixels_per_thread;
int my_rem_pixel = image_buffer_size - my_thread - 1;
while (pix <= my_rem_pixel) {
i_y = pix / image_size;
i_x = pix % image_size;
c_y = c_y_min + i_y * pixel_height;
if (fabs(c_y) < pixel_height / 2) {
c_y = 0.0;
};
c_x = c_x_min + i_x * pixel_width;
z_x = 0.0;
z_y = 0.0;
z_x_squared = 0.0;
z_y_squared = 0.0;
for (iteration = 0;
iteration < iteration_max && \
((z_x_squared + z_y_squared) < escape_radius_squared);
iteration++) {
z_y = 2 * z_x * z_y + c_y;
z_x = z_x_squared - z_y_squared + c_x;
z_x_squared = z_x * z_x;
z_y_squared = z_y * z_y;
};
update_rgb_buffer(image_buffer_device, iteration, pix);
pix++;
// Treat remaining pixel
if (pix == end_pixel) {
if (my_rem_pixel >= pix) pix = my_rem_pixel;
else break;
}
}
}
void allocate_image_buffer(unsigned char** image_buffer_device, size_t size) {
// Our buffer, instead of a matrix, will be a continuous array
// Allocate host memory
image_buffer_host = (unsigned char*)malloc(sizeof(unsigned char) * size);
// Allocate device memory
hipError_t err = hipSuccess;
err = hipMalloc((void**)(image_buffer_device), size);
// Test alloc success
if (image_buffer_host == NULL) {
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
if (check(err, "Failed to allocate device image buffer"))
exit(EXIT_FAILURE);
};
void write_to_file() {
FILE* file;
const char* filename = "output.ppm";
const char* comment = "# ";
int max_color_component_value = 255;
file = fopen(filename, "wb");
fprintf(file, "P6\n %s\n %d\n %d\n %d\n", comment,
i_x_max, i_y_max, max_color_component_value);
for (int i = 0; i < host_image_buffer_size; i++) {
fwrite(image_buffer_host + 3*i, 1, 3, file);
};
fclose(file);
};
int main(int argc, char* argv[]) {
init(argc, argv);
hipError_t err;
int rgb_size = 3;
size_t size = host_image_buffer_size * rgb_size;
unsigned char* image_buffer_device;
allocate_image_buffer(&image_buffer_device, size);
// Launch compute_mandelbrot CUDA Kernel
num_blocks = dim3(num_blocks_x, num_blocks_y);
threads_per_block = dim3(th_per_block_x, th_per_block_y);
compute_mandelbrot<<<num_blocks, threads_per_block>>>(image_buffer_device);
hipDeviceSynchronize();
err = hipGetLastError();
if (check(err, "Failed to launch compute_mandelbrot kernel"))
exit(EXIT_FAILURE);
// Copy the device result vector in device memory to the host result vector
// in host memory.
err = hipMemcpy(image_buffer_host, image_buffer_device, size,
hipMemcpyDeviceToHost);
if (check(err, "Failed to copy vector from device to host"))
exit(EXIT_FAILURE);
// Free device global memory
err = hipFree(image_buffer_device);
if (check(err, "Failed to free device vector"))
exit(EXIT_FAILURE);
write_to_file();
// Free host memory
free(image_buffer_host);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <stdio.h>
// For the CUDA runtime routines (prefixed with "cuda_")
#include <hip/hip_runtime.h>
// Device global variables
__device__ double c_x_min;
__device__ double c_x_max;
__device__ double c_y_min;
__device__ double c_y_max;
__device__ double pixel_width;
__device__ double pixel_height;
__device__ int iteration_max = 200;
__device__ int image_size;
__device__ int image_buffer_size;
__device__ int num_threads;
__device__ int th_per_block;
__device__ int pixels_per_thread;
__device__ int gradient_size = 16;
__device__ int colors[17][3] = {
{66, 30, 15},
{25, 7, 26},
{9, 1, 47},
{4, 4, 73},
{0, 7, 100},
{12, 44, 138},
{24, 82, 177},
{57, 125, 209},
{134, 181, 229},
{211, 236, 248},
{241, 233, 191},
{248, 201, 95},
{255, 170, 0},
{204, 128, 0},
{153, 87, 0},
{106, 52, 3},
{16, 16, 16},
};
// Host global variables
dim3 num_blocks, threads_per_block;
int num_blocks_x, th_per_block_x;
int num_blocks_y, th_per_block_y;
int host_image_buffer_size;
unsigned char* image_buffer_host;
int i_x_max;
int i_y_max;
int check (hipError_t& err, const char* msg) {
if (err != hipSuccess) {
printf ("%s", msg);
printf (" | Error: %s\n", hipGetErrorString(err));
return 1;
}
return 0;
}
void print_bad_arguments () {
printf("usage: ./mandelbrot_seq c_x_min c_x_max c_y_min c_y_max"
" image_size NUM_BLOCKS TH_PER_BLOCK \n");
printf("examples with image_size = 11500:\n");
printf(" Full Picture: ./mandelbrot_cuda -2.5 1.5 -2.0 2.0 11500 4 64 \n");
printf(" Seahorse Valley: ./mandelbrot_cuda -0.8 -0.7 0.05 0.15 11500 4 64 \n");
printf(" Elephant Valley: ./mandelbrot_cuda 0.175 0.375 -0.1 0.1 11500 4 64 \n");
printf(" Triple Spiral Valley: ./mandelbrot_cuda -0.188 -0.012 0.554 0.754 11500 4 64 \n");
}
// Get global variables from command line args
void init (int argc, char* argv[]) {
// host variables
double host_c_x_min, host_c_x_max;
double host_c_y_min, host_c_y_max;
int host_image_size;
if (argc < 8) {
print_bad_arguments();
exit(0);
}
else {
num_blocks_y = th_per_block_y = 1;
sscanf(argv[1], "%lf", &host_c_x_min);
sscanf(argv[2], "%lf", &host_c_x_max);
sscanf(argv[3], "%lf", &host_c_y_min);
sscanf(argv[4], "%lf", &host_c_y_max);
sscanf(argv[5], "%d", &host_image_size);
sscanf(argv[6], "%d", &num_blocks_x);
if (argc == 8) {
sscanf(argv[7], "%d", &th_per_block_x);
}
else if (argc == 10) {
sscanf(argv[7], "%d", &num_blocks_y);
sscanf(argv[8], "%d", &th_per_block_x);
sscanf(argv[9], "%d", &th_per_block_y);
}
else {
print_bad_arguments();
exit(0);
}
host_image_buffer_size = host_image_size * host_image_size;
int host_th_per_block = th_per_block_x * th_per_block_y;
int host_num_threads = host_th_per_block * num_blocks_x * num_blocks_y;
int host_pixels_per_thread = host_image_buffer_size / host_num_threads;
i_x_max = host_image_size;
i_y_max = host_image_size;
double host_pixel_width = (host_c_x_max - host_c_x_min) / i_x_max;
double host_pixel_height = (host_c_y_max - host_c_y_min) / i_y_max;
// copy host variables to device
hipError_t err = hipSuccess;
hipMemcpyToSymbol(HIP_SYMBOL(c_x_min), &host_c_x_min, sizeof(double));
hipMemcpyToSymbol(HIP_SYMBOL(c_x_max), &host_c_x_max, sizeof(double));
hipMemcpyToSymbol(HIP_SYMBOL(c_y_min), &host_c_y_min, sizeof(double));
hipMemcpyToSymbol(HIP_SYMBOL(c_y_max), &host_c_y_max, sizeof(double));
hipMemcpyToSymbol(HIP_SYMBOL(image_size), &host_image_size, sizeof(int));
hipMemcpyToSymbol(HIP_SYMBOL(num_threads), &host_num_threads, sizeof(int));
hipMemcpyToSymbol(HIP_SYMBOL(th_per_block), &host_th_per_block, sizeof(int));
hipMemcpyToSymbol(HIP_SYMBOL(pixel_width), &host_pixel_width, sizeof(double));
hipMemcpyToSymbol(HIP_SYMBOL(pixel_height), &host_pixel_height, sizeof(double));
hipMemcpyToSymbol(HIP_SYMBOL(pixels_per_thread), &host_pixels_per_thread, sizeof(int));
hipMemcpyToSymbol(HIP_SYMBOL(image_buffer_size), &host_image_buffer_size, sizeof(int));
err = hipGetLastError();
if (check(err, "Failed to copy command line args to device"))
exit(EXIT_FAILURE);
};
};
__device__
void update_rgb_buffer(unsigned char* image_buffer_device, int iteration, int pix) {
int color;
if (iteration == iteration_max) {
image_buffer_device[pix * 3 + 0] = colors[gradient_size][0];
image_buffer_device[pix * 3 + 1] = colors[gradient_size][1];
image_buffer_device[pix * 3 + 2] = colors[gradient_size][2];
} else {
color = iteration % gradient_size;
image_buffer_device[pix * 3 + 0] = colors[color][0];
image_buffer_device[pix * 3 + 1] = colors[color][1];
image_buffer_device[pix * 3 + 2] = colors[color][2];
};
};
__global__
void compute_mandelbrot(unsigned char* image_buffer_device) {
double z_x;
double z_y;
double z_x_squared;
double z_y_squared;
double escape_radius_squared = 4;
int iteration;
int i_x;
int i_y;
double c_x;
double c_y;
// Calculates pixel where current thread will start its work
int my_block = blockIdx.x + gridDim.x * blockIdx.y;
int my_thread_in_block = threadIdx.x + blockDim.x * threadIdx.y;
int my_thread = my_block * th_per_block + my_thread_in_block;
/* what thread will process each pixel ?
*
* Example: image 5x5 -> buffer_size = 25
* 3 blocks of 3 threads -> 9 threads
*
* 2 4 7 - -
* 1 4 6 - -
* 1 3 6 8 -
* 0 3 5 8 -
* 0 2 5 7 -
*
* and the remaining pixels we process separetedly,
* each thread process its remaining pixel in the end
*
* 2 4 7 5 0
* 1 4 6 6 1
* 1 3 6 8 2
* 0 3 5 8 3
* 0 2 5 7 4
*/
// Its easier to process by pixels instead of by row-collunm
int pix = my_thread * pixels_per_thread;
int end_pixel = pix + pixels_per_thread;
int my_rem_pixel = image_buffer_size - my_thread - 1;
while (pix <= my_rem_pixel) {
i_y = pix / image_size;
i_x = pix % image_size;
c_y = c_y_min + i_y * pixel_height;
if (fabs(c_y) < pixel_height / 2) {
c_y = 0.0;
};
c_x = c_x_min + i_x * pixel_width;
z_x = 0.0;
z_y = 0.0;
z_x_squared = 0.0;
z_y_squared = 0.0;
for (iteration = 0;
iteration < iteration_max && \
((z_x_squared + z_y_squared) < escape_radius_squared);
iteration++) {
z_y = 2 * z_x * z_y + c_y;
z_x = z_x_squared - z_y_squared + c_x;
z_x_squared = z_x * z_x;
z_y_squared = z_y * z_y;
};
update_rgb_buffer(image_buffer_device, iteration, pix);
pix++;
// Treat remaining pixel
if (pix == end_pixel) {
if (my_rem_pixel >= pix) pix = my_rem_pixel;
else break;
}
}
}
void allocate_image_buffer(unsigned char** image_buffer_device, size_t size) {
// Our buffer, instead of a matrix, will be a continuous array
// Allocate host memory
image_buffer_host = (unsigned char*)malloc(sizeof(unsigned char) * size);
// Allocate device memory
hipError_t err = hipSuccess;
err = hipMalloc((void**)(image_buffer_device), size);
// Test alloc success
if (image_buffer_host == NULL) {
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
if (check(err, "Failed to allocate device image buffer"))
exit(EXIT_FAILURE);
};
void write_to_file() {
FILE* file;
const char* filename = "output.ppm";
const char* comment = "# ";
int max_color_component_value = 255;
file = fopen(filename, "wb");
fprintf(file, "P6\n %s\n %d\n %d\n %d\n", comment,
i_x_max, i_y_max, max_color_component_value);
for (int i = 0; i < host_image_buffer_size; i++) {
fwrite(image_buffer_host + 3*i, 1, 3, file);
};
fclose(file);
};
int main(int argc, char* argv[]) {
init(argc, argv);
hipError_t err;
int rgb_size = 3;
size_t size = host_image_buffer_size * rgb_size;
unsigned char* image_buffer_device;
allocate_image_buffer(&image_buffer_device, size);
// Launch compute_mandelbrot CUDA Kernel
num_blocks = dim3(num_blocks_x, num_blocks_y);
threads_per_block = dim3(th_per_block_x, th_per_block_y);
compute_mandelbrot<<<num_blocks, threads_per_block>>>(image_buffer_device);
hipDeviceSynchronize();
err = hipGetLastError();
if (check(err, "Failed to launch compute_mandelbrot kernel"))
exit(EXIT_FAILURE);
// Copy the device result vector in device memory to the host result vector
// in host memory.
err = hipMemcpy(image_buffer_host, image_buffer_device, size,
hipMemcpyDeviceToHost);
if (check(err, "Failed to copy vector from device to host"))
exit(EXIT_FAILURE);
// Free device global memory
err = hipFree(image_buffer_device);
if (check(err, "Failed to free device vector"))
exit(EXIT_FAILURE);
write_to_file();
// Free host memory
free(image_buffer_host);
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18compute_mandelbrotPh
.globl _Z18compute_mandelbrotPh
.p2align 8
.type _Z18compute_mandelbrotPh,@function
_Z18compute_mandelbrotPh:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x8
s_load_b32 s7, s[0:1], 0x14
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, th_per_block@rel32@lo+4
s_addc_u32 s3, s3, th_per_block@rel32@hi+12
v_bfe_u32 v1, v0, 10, 10
s_load_b32 s8, s[2:3], 0x0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, pixels_per_thread@rel32@lo+4
s_addc_u32 s3, s3, pixels_per_thread@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, image_buffer_size@rel32@lo+4
s_addc_u32 s5, s5, image_buffer_size@rel32@hi+12
s_load_b32 s2, s[2:3], 0x0
s_load_b32 s3, s[4:5], 0x0
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s5, s6, s15
s_and_b32 s4, s7, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_u32_u24_e32 v1, s4, v1
s_add_i32 s4, s5, s14
s_mul_i32 s4, s4, s8
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v0, v1, v0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mul_lo_u32 v16, v0, s2
v_xad_u32 v14, v0, -1, s3
s_mov_b32 s3, exec_lo
v_cmpx_le_i32_e64 v16, v14
s_cbranch_execz .LBB0_15
s_load_b64 s[0:1], s[0:1], 0x0
v_add_nc_u32_e32 v15, s2, v16
v_mov_b32_e32 v1, 0
s_mov_b32 s4, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s0, 2
s_addc_u32 s3, s1, 0
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s7
v_mov_b32_e32 v16, v0
s_and_b32 s5, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s4, s5, s4
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_15
.LBB0_3:
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, iteration_max@rel32@lo+4
s_addc_u32 s7, s7, iteration_max@rel32@hi+12
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, image_size@rel32@lo+4
s_addc_u32 s9, s9, image_size@rel32@hi+12
s_clause 0x1
global_load_b32 v0, v1, s[6:7]
global_load_b32 v2, v1, s[8:9]
s_waitcnt vmcnt(1)
v_cmp_gt_i32_e32 vcc_lo, 1, v0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s6, v2
v_readfirstlane_b32 s5, v0
v_mov_b32_e32 v0, 0
s_cbranch_vccnz .LBB0_7
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, c_y_min@rel32@lo+4
s_addc_u32 s9, s9, c_y_min@rel32@hi+12
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, pixel_height@rel32@lo+4
s_addc_u32 s11, s11, pixel_height@rel32@hi+12
v_ashrrev_i32_e32 v12, 31, v16
s_clause 0x1
global_load_b64 v[2:3], v1, s[8:9]
global_load_b64 v[4:5], v1, s[10:11]
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, c_x_min@rel32@lo+4
s_addc_u32 s9, s9, c_x_min@rel32@hi+12
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, pixel_width@rel32@lo+4
s_addc_u32 s11, s11, pixel_width@rel32@hi+12
s_clause 0x1
global_load_b64 v[6:7], v1, s[8:9]
global_load_b64 v[8:9], v1, s[10:11]
s_ashr_i32 s7, s6, 31
v_add_nc_u32_e32 v11, v16, v12
s_add_i32 s8, s6, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s8, s8, s7
v_cvt_f32_u32_e32 v0, s8
s_sub_i32 s9, 0, s8
v_xor_b32_e32 v13, v11, v12
v_xor_b32_e32 v12, s7, v12
s_mov_b32 s7, 0
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v10, s9, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v10, v0, v10
v_add_nc_u32_e32 v0, v0, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[10:11], null, v13, v0, 0
v_mul_lo_u32 v0, v11, s8
v_add_nc_u32_e32 v10, 1, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v13, v0
v_subrev_nc_u32_e32 v13, s8, v0
v_cmp_le_u32_e32 vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v10, v11, v10, vcc_lo
v_dual_cndmask_b32 v0, v0, v13 :: v_dual_add_nc_u32 v11, 1, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s8, v0
v_cndmask_b32_e32 v0, v10, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v12
v_sub_nc_u32_e32 v0, v0, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cvt_f64_i32_e32 v[10:11], v0
v_mul_lo_u32 v0, v0, s6
s_mov_b32 s6, 0
v_sub_nc_u32_e32 v0, v16, v0
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[12:13], v[4:5], v[10:11], v[2:3]
v_mul_f64 v[2:3], v[4:5], 0.5
v_cvt_f64_i32_e32 v[4:5], v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_nlt_f64_e64 vcc_lo, |v[12:13]|, v[2:3]
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[8:9], v[4:5], v[6:7]
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v7, v5
v_dual_mov_b32 v11, v5 :: v_dual_mov_b32 v6, v4
v_dual_mov_b32 v10, v4 :: v_dual_cndmask_b32 v9, 0, v13
v_dual_cndmask_b32 v8, 0, v12 :: v_dual_mov_b32 v13, v5
v_mov_b32_e32 v12, v4
.p2align 6
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_f64 v[10:11], v[10:11], -v[12:13]
v_add_f64 v[12:13], v[4:5], v[4:5]
s_add_i32 s7, s7, 1
s_cmp_ge_i32 s7, s5
v_mov_b32_e32 v0, s7
s_cselect_b32 s8, -1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[4:5], v[2:3], v[10:11]
v_fma_f64 v[6:7], v[6:7], v[12:13], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[4:5], v[4:5]
v_fma_f64 v[12:13], v[6:7], v[6:7], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_ngt_f64_e32 vcc_lo, 4.0, v[12:13]
v_mul_f64 v[12:13], v[6:7], v[6:7]
s_or_b32 s8, s8, vcc_lo
s_and_b32 s8, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s6, s8, s6
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_5
s_or_b32 exec_lo, exec_lo, s6
.LBB0_7:
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, gradient_size@rel32@lo+4
s_addc_u32 s7, s7, gradient_size@rel32@hi+12
v_cmp_ne_u32_e32 vcc_lo, s5, v0
global_load_b32 v2, v1, s[6:7]
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s5, v2
s_and_saveexec_b32 s6, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB0_9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_ashr_i32 s7, s5, 31
v_ashrrev_i32_e32 v4, 31, v0
s_add_i32 s8, s5, s7
s_xor_b32 s7, s8, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, v0, v4
v_cvt_f32_u32_e32 v2, s7
s_sub_i32 s8, 0, s7
v_xor_b32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s8, v2
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, colors@rel32@lo+4
s_addc_u32 s9, s9, colors@rel32@hi+12
v_mul_hi_u32 v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v3
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s7
v_sub_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s7, v0
v_cmp_le_u32_e32 vcc_lo, s7, v0
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s7, v0
v_cmp_le_u32_e32 vcc_lo, s7, v0
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v4
v_sub_nc_u32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, v0, 12, s[8:9]
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, colors@rel32@lo+8
s_addc_u32 s9, s9, colors@rel32@hi+16
v_mad_u64_u32 v[4:5], null, v0, 12, s[8:9]
global_load_b32 v8, v[2:3], off
v_lshl_add_u32 v2, v16, 1, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v6, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b8 v[6:7], v8, off
global_load_b32 v8, v[4:5], off
v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
s_waitcnt vmcnt(0)
global_store_b8 v[6:7], v8, off offset:1
.LBB0_9:
s_and_not1_saveexec_b32 s6, s6
s_cbranch_execz .LBB0_11
s_mul_i32 s7, s5, 12
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, colors@rel32@lo+4
s_addc_u32 s9, s9, colors@rel32@hi+12
s_mul_hi_i32 s5, s5, 12
s_add_u32 s8, s7, s8
s_addc_u32 s9, s5, s9
v_lshl_add_u32 v2, v16, 1, v16
global_load_b32 v0, v1, s[8:9]
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, gradient_size@rel32@lo+4
s_addc_u32 s9, s9, gradient_size@rel32@hi+12
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, colors@rel32@lo+8
s_addc_u32 s11, s11, colors@rel32@hi+16
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v4, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b8 v[4:5], v0, off
global_load_b32 v0, v1, s[8:9]
s_waitcnt vmcnt(0)
v_mul_lo_u32 v6, v0, 12
v_mul_hi_i32 v0, v0, 12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v6, s10
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v0, vcc_lo
global_load_b32 v0, v[6:7], off
s_waitcnt vmcnt(0)
global_store_b8 v[4:5], v0, off offset:1
global_load_b32 v4, v1, s[8:9]
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v5, 31, v4
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s6
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, colors@rel32@lo+12
s_addc_u32 s7, s7, colors@rel32@hi+20
v_add_co_u32 v2, vcc_lo, s2, v2
v_mad_u64_u32 v[6:7], null, v4, 12, s[6:7]
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v0, v7
v_mad_u64_u32 v[7:8], null, v5, 12, v[0:1]
v_add_nc_u32_e32 v0, 1, v16
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e64 s5, v0, v15
global_load_b32 v4, v[6:7], off
s_waitcnt vmcnt(0)
global_store_b8 v[2:3], v4, off
v_cmpx_eq_u32_e64 v0, v15
v_cmp_gt_i32_e32 vcc_lo, v14, v16
v_mov_b32_e32 v0, v14
s_and_not1_b32 s5, s5, exec_lo
s_and_b32 s7, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s5, s5, s7
s_or_b32 exec_lo, exec_lo, s6
s_mov_b32 s6, -1
s_and_saveexec_b32 s7, s5
s_cbranch_execz .LBB0_2
v_cmp_gt_i32_e32 vcc_lo, v0, v14
s_or_not1_b32 s6, vcc_lo, exec_lo
s_branch .LBB0_2
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18compute_mandelbrotPh
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18compute_mandelbrotPh, .Lfunc_end0-_Z18compute_mandelbrotPh
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected c_x_min
.type c_x_min,@object
.section .bss,"aw",@nobits
.globl c_x_min
.p2align 3, 0x0
c_x_min:
.quad 0x0000000000000000
.size c_x_min, 8
.protected c_x_max
.type c_x_max,@object
.globl c_x_max
.p2align 3, 0x0
c_x_max:
.quad 0x0000000000000000
.size c_x_max, 8
.protected c_y_min
.type c_y_min,@object
.globl c_y_min
.p2align 3, 0x0
c_y_min:
.quad 0x0000000000000000
.size c_y_min, 8
.protected c_y_max
.type c_y_max,@object
.globl c_y_max
.p2align 3, 0x0
c_y_max:
.quad 0x0000000000000000
.size c_y_max, 8
.protected pixel_width
.type pixel_width,@object
.globl pixel_width
.p2align 3, 0x0
pixel_width:
.quad 0x0000000000000000
.size pixel_width, 8
.protected pixel_height
.type pixel_height,@object
.globl pixel_height
.p2align 3, 0x0
pixel_height:
.quad 0x0000000000000000
.size pixel_height, 8
.protected iteration_max
.type iteration_max,@object
.data
.globl iteration_max
.p2align 2, 0x0
iteration_max:
.long 200
.size iteration_max, 4
.protected image_size
.type image_size,@object
.section .bss,"aw",@nobits
.globl image_size
.p2align 2, 0x0
image_size:
.long 0
.size image_size, 4
.protected image_buffer_size
.type image_buffer_size,@object
.globl image_buffer_size
.p2align 2, 0x0
image_buffer_size:
.long 0
.size image_buffer_size, 4
.protected num_threads
.type num_threads,@object
.globl num_threads
.p2align 2, 0x0
num_threads:
.long 0
.size num_threads, 4
.protected th_per_block
.type th_per_block,@object
.globl th_per_block
.p2align 2, 0x0
th_per_block:
.long 0
.size th_per_block, 4
.protected pixels_per_thread
.type pixels_per_thread,@object
.globl pixels_per_thread
.p2align 2, 0x0
pixels_per_thread:
.long 0
.size pixels_per_thread, 4
.protected gradient_size
.type gradient_size,@object
.data
.globl gradient_size
.p2align 2, 0x0
gradient_size:
.long 16
.size gradient_size, 4
.protected colors
.type colors,@object
.globl colors
.p2align 4, 0x0
colors:
.long 66
.long 30
.long 15
.long 25
.long 7
.long 26
.long 9
.long 1
.long 47
.long 4
.long 4
.long 73
.long 0
.long 7
.long 100
.long 12
.long 44
.long 138
.long 24
.long 82
.long 177
.long 57
.long 125
.long 209
.long 134
.long 181
.long 229
.long 211
.long 236
.long 248
.long 241
.long 233
.long 191
.long 248
.long 201
.long 95
.long 255
.long 170
.long 0
.long 204
.long 128
.long 0
.long 153
.long 87
.long 0
.long 106
.long 52
.long 3
.long 16
.long 16
.long 16
.size colors, 204
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym c_x_min
.addrsig_sym c_x_max
.addrsig_sym c_y_min
.addrsig_sym c_y_max
.addrsig_sym pixel_width
.addrsig_sym pixel_height
.addrsig_sym iteration_max
.addrsig_sym image_size
.addrsig_sym image_buffer_size
.addrsig_sym num_threads
.addrsig_sym th_per_block
.addrsig_sym pixels_per_thread
.addrsig_sym gradient_size
.addrsig_sym colors
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18compute_mandelbrotPh
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18compute_mandelbrotPh.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <stdio.h>
// For the CUDA runtime routines (prefixed with "cuda_")
#include <hip/hip_runtime.h>
// Device global variables
__device__ double c_x_min;
__device__ double c_x_max;
__device__ double c_y_min;
__device__ double c_y_max;
__device__ double pixel_width;
__device__ double pixel_height;
__device__ int iteration_max = 200;
__device__ int image_size;
__device__ int image_buffer_size;
__device__ int num_threads;
__device__ int th_per_block;
__device__ int pixels_per_thread;
__device__ int gradient_size = 16;
__device__ int colors[17][3] = {
{66, 30, 15},
{25, 7, 26},
{9, 1, 47},
{4, 4, 73},
{0, 7, 100},
{12, 44, 138},
{24, 82, 177},
{57, 125, 209},
{134, 181, 229},
{211, 236, 248},
{241, 233, 191},
{248, 201, 95},
{255, 170, 0},
{204, 128, 0},
{153, 87, 0},
{106, 52, 3},
{16, 16, 16},
};
// Host global variables
dim3 num_blocks, threads_per_block;
int num_blocks_x, th_per_block_x;
int num_blocks_y, th_per_block_y;
int host_image_buffer_size;
unsigned char* image_buffer_host;
int i_x_max;
int i_y_max;
int check (hipError_t& err, const char* msg) {
if (err != hipSuccess) {
printf ("%s", msg);
printf (" | Error: %s\n", hipGetErrorString(err));
return 1;
}
return 0;
}
void print_bad_arguments () {
printf("usage: ./mandelbrot_seq c_x_min c_x_max c_y_min c_y_max"
" image_size NUM_BLOCKS TH_PER_BLOCK \n");
printf("examples with image_size = 11500:\n");
printf(" Full Picture: ./mandelbrot_cuda -2.5 1.5 -2.0 2.0 11500 4 64 \n");
printf(" Seahorse Valley: ./mandelbrot_cuda -0.8 -0.7 0.05 0.15 11500 4 64 \n");
printf(" Elephant Valley: ./mandelbrot_cuda 0.175 0.375 -0.1 0.1 11500 4 64 \n");
printf(" Triple Spiral Valley: ./mandelbrot_cuda -0.188 -0.012 0.554 0.754 11500 4 64 \n");
}
// Get global variables from command line args
void init (int argc, char* argv[]) {
// host variables
double host_c_x_min, host_c_x_max;
double host_c_y_min, host_c_y_max;
int host_image_size;
if (argc < 8) {
print_bad_arguments();
exit(0);
}
else {
num_blocks_y = th_per_block_y = 1;
sscanf(argv[1], "%lf", &host_c_x_min);
sscanf(argv[2], "%lf", &host_c_x_max);
sscanf(argv[3], "%lf", &host_c_y_min);
sscanf(argv[4], "%lf", &host_c_y_max);
sscanf(argv[5], "%d", &host_image_size);
sscanf(argv[6], "%d", &num_blocks_x);
if (argc == 8) {
sscanf(argv[7], "%d", &th_per_block_x);
}
else if (argc == 10) {
sscanf(argv[7], "%d", &num_blocks_y);
sscanf(argv[8], "%d", &th_per_block_x);
sscanf(argv[9], "%d", &th_per_block_y);
}
else {
print_bad_arguments();
exit(0);
}
host_image_buffer_size = host_image_size * host_image_size;
int host_th_per_block = th_per_block_x * th_per_block_y;
int host_num_threads = host_th_per_block * num_blocks_x * num_blocks_y;
int host_pixels_per_thread = host_image_buffer_size / host_num_threads;
i_x_max = host_image_size;
i_y_max = host_image_size;
double host_pixel_width = (host_c_x_max - host_c_x_min) / i_x_max;
double host_pixel_height = (host_c_y_max - host_c_y_min) / i_y_max;
// copy host variables to device
hipError_t err = hipSuccess;
hipMemcpyToSymbol(HIP_SYMBOL(c_x_min), &host_c_x_min, sizeof(double));
hipMemcpyToSymbol(HIP_SYMBOL(c_x_max), &host_c_x_max, sizeof(double));
hipMemcpyToSymbol(HIP_SYMBOL(c_y_min), &host_c_y_min, sizeof(double));
hipMemcpyToSymbol(HIP_SYMBOL(c_y_max), &host_c_y_max, sizeof(double));
hipMemcpyToSymbol(HIP_SYMBOL(image_size), &host_image_size, sizeof(int));
hipMemcpyToSymbol(HIP_SYMBOL(num_threads), &host_num_threads, sizeof(int));
hipMemcpyToSymbol(HIP_SYMBOL(th_per_block), &host_th_per_block, sizeof(int));
hipMemcpyToSymbol(HIP_SYMBOL(pixel_width), &host_pixel_width, sizeof(double));
hipMemcpyToSymbol(HIP_SYMBOL(pixel_height), &host_pixel_height, sizeof(double));
hipMemcpyToSymbol(HIP_SYMBOL(pixels_per_thread), &host_pixels_per_thread, sizeof(int));
hipMemcpyToSymbol(HIP_SYMBOL(image_buffer_size), &host_image_buffer_size, sizeof(int));
err = hipGetLastError();
if (check(err, "Failed to copy command line args to device"))
exit(EXIT_FAILURE);
};
};
__device__
void update_rgb_buffer(unsigned char* image_buffer_device, int iteration, int pix) {
int color;
if (iteration == iteration_max) {
image_buffer_device[pix * 3 + 0] = colors[gradient_size][0];
image_buffer_device[pix * 3 + 1] = colors[gradient_size][1];
image_buffer_device[pix * 3 + 2] = colors[gradient_size][2];
} else {
color = iteration % gradient_size;
image_buffer_device[pix * 3 + 0] = colors[color][0];
image_buffer_device[pix * 3 + 1] = colors[color][1];
image_buffer_device[pix * 3 + 2] = colors[color][2];
};
};
__global__
void compute_mandelbrot(unsigned char* image_buffer_device) {
double z_x;
double z_y;
double z_x_squared;
double z_y_squared;
double escape_radius_squared = 4;
int iteration;
int i_x;
int i_y;
double c_x;
double c_y;
// Calculates pixel where current thread will start its work
int my_block = blockIdx.x + gridDim.x * blockIdx.y;
int my_thread_in_block = threadIdx.x + blockDim.x * threadIdx.y;
int my_thread = my_block * th_per_block + my_thread_in_block;
/* what thread will process each pixel ?
*
* Example: image 5x5 -> buffer_size = 25
* 3 blocks of 3 threads -> 9 threads
*
* 2 4 7 - -
* 1 4 6 - -
* 1 3 6 8 -
* 0 3 5 8 -
* 0 2 5 7 -
*
* and the remaining pixels we process separetedly,
* each thread process its remaining pixel in the end
*
* 2 4 7 5 0
* 1 4 6 6 1
* 1 3 6 8 2
* 0 3 5 8 3
* 0 2 5 7 4
*/
// Its easier to process by pixels instead of by row-collunm
int pix = my_thread * pixels_per_thread;
int end_pixel = pix + pixels_per_thread;
int my_rem_pixel = image_buffer_size - my_thread - 1;
while (pix <= my_rem_pixel) {
i_y = pix / image_size;
i_x = pix % image_size;
c_y = c_y_min + i_y * pixel_height;
if (fabs(c_y) < pixel_height / 2) {
c_y = 0.0;
};
c_x = c_x_min + i_x * pixel_width;
z_x = 0.0;
z_y = 0.0;
z_x_squared = 0.0;
z_y_squared = 0.0;
for (iteration = 0;
iteration < iteration_max && \
((z_x_squared + z_y_squared) < escape_radius_squared);
iteration++) {
z_y = 2 * z_x * z_y + c_y;
z_x = z_x_squared - z_y_squared + c_x;
z_x_squared = z_x * z_x;
z_y_squared = z_y * z_y;
};
update_rgb_buffer(image_buffer_device, iteration, pix);
pix++;
// Treat remaining pixel
if (pix == end_pixel) {
if (my_rem_pixel >= pix) pix = my_rem_pixel;
else break;
}
}
}
void allocate_image_buffer(unsigned char** image_buffer_device, size_t size) {
// Our buffer, instead of a matrix, will be a continuous array
// Allocate host memory
image_buffer_host = (unsigned char*)malloc(sizeof(unsigned char) * size);
// Allocate device memory
hipError_t err = hipSuccess;
err = hipMalloc((void**)(image_buffer_device), size);
// Test alloc success
if (image_buffer_host == NULL) {
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
if (check(err, "Failed to allocate device image buffer"))
exit(EXIT_FAILURE);
};
void write_to_file() {
FILE* file;
const char* filename = "output.ppm";
const char* comment = "# ";
int max_color_component_value = 255;
file = fopen(filename, "wb");
fprintf(file, "P6\n %s\n %d\n %d\n %d\n", comment,
i_x_max, i_y_max, max_color_component_value);
for (int i = 0; i < host_image_buffer_size; i++) {
fwrite(image_buffer_host + 3*i, 1, 3, file);
};
fclose(file);
};
int main(int argc, char* argv[]) {
init(argc, argv);
hipError_t err;
int rgb_size = 3;
size_t size = host_image_buffer_size * rgb_size;
unsigned char* image_buffer_device;
allocate_image_buffer(&image_buffer_device, size);
// Launch compute_mandelbrot CUDA Kernel
num_blocks = dim3(num_blocks_x, num_blocks_y);
threads_per_block = dim3(th_per_block_x, th_per_block_y);
compute_mandelbrot<<<num_blocks, threads_per_block>>>(image_buffer_device);
hipDeviceSynchronize();
err = hipGetLastError();
if (check(err, "Failed to launch compute_mandelbrot kernel"))
exit(EXIT_FAILURE);
// Copy the device result vector in device memory to the host result vector
// in host memory.
err = hipMemcpy(image_buffer_host, image_buffer_device, size,
hipMemcpyDeviceToHost);
if (check(err, "Failed to copy vector from device to host"))
exit(EXIT_FAILURE);
// Free device global memory
err = hipFree(image_buffer_device);
if (check(err, "Failed to free device vector"))
exit(EXIT_FAILURE);
write_to_file();
// Free host memory
free(image_buffer_host);
return 0;
}
|
.text
.file "mandelbrot_cuda.hip"
.globl _Z5checkR10hipError_tPKc # -- Begin function _Z5checkR10hipError_tPKc
.p2align 4, 0x90
.type _Z5checkR10hipError_tPKc,@function
_Z5checkR10hipError_tPKc: # @_Z5checkR10hipError_tPKc
.cfi_startproc
# %bb.0:
cmpl $0, (%rdi)
je .LBB0_1
# %bb.2:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl (%rbx), %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %eax
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
retq
.LBB0_1:
xorl %eax, %eax
retq
.Lfunc_end0:
.size _Z5checkR10hipError_tPKc, .Lfunc_end0-_Z5checkR10hipError_tPKc
.cfi_endproc
# -- End function
.globl _Z19print_bad_argumentsv # -- Begin function _Z19print_bad_argumentsv
.p2align 4, 0x90
.type _Z19print_bad_argumentsv,@function
_Z19print_bad_argumentsv: # @_Z19print_bad_argumentsv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
movl $.Lstr.4, %edi
callq puts@PLT
movl $.Lstr.5, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end1:
.size _Z19print_bad_argumentsv, .Lfunc_end1-_Z19print_bad_argumentsv
.cfi_endproc
# -- End function
.globl _Z4initiPPc # -- Begin function _Z4initiPPc
.p2align 4, 0x90
.type _Z4initiPPc,@function
_Z4initiPPc: # @_Z4initiPPc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $72, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
cmpl $7, %edi
jle .LBB2_7
# %bb.1:
movq %rsi, %rbx
movl %edi, %ebp
movl $1, th_per_block_y(%rip)
movl $1, num_blocks_y(%rip)
movq 8(%rsi), %rdi
leaq 48(%rsp), %rdx
movl $.L.str.8, %esi
xorl %eax, %eax
callq __isoc23_sscanf
movq 16(%rbx), %rdi
leaq 40(%rsp), %rdx
movl $.L.str.8, %esi
xorl %eax, %eax
callq __isoc23_sscanf
movq 24(%rbx), %rdi
leaq 32(%rsp), %rdx
movl $.L.str.8, %esi
xorl %eax, %eax
callq __isoc23_sscanf
movq 32(%rbx), %rdi
leaq 24(%rsp), %rdx
movl $.L.str.8, %esi
xorl %eax, %eax
callq __isoc23_sscanf
movq 40(%rbx), %rdi
leaq 8(%rsp), %rdx
movl $.L.str.9, %esi
xorl %eax, %eax
callq __isoc23_sscanf
movq 48(%rbx), %rdi
movl $.L.str.9, %esi
movl $num_blocks_x, %edx
xorl %eax, %eax
callq __isoc23_sscanf
cmpl $8, %ebp
je .LBB2_2
# %bb.3:
cmpl $10, %ebp
jne .LBB2_7
# %bb.4:
movq 56(%rbx), %rdi
movl $.L.str.9, %esi
movl $num_blocks_y, %edx
xorl %eax, %eax
callq __isoc23_sscanf
movq 64(%rbx), %rdi
movl $.L.str.9, %esi
movl $th_per_block_x, %edx
xorl %eax, %eax
callq __isoc23_sscanf
movl $th_per_block_y, %edx
movl $9, %eax
jmp .LBB2_5
.LBB2_2:
movl $th_per_block_x, %edx
movl $7, %eax
.LBB2_5:
movq (%rbx,%rax,8), %rdi
movl $.L.str.9, %esi
xorl %eax, %eax
callq __isoc23_sscanf
movl 8(%rsp), %ecx
movl %ecx, %eax
imull %ecx, %eax
movl %eax, host_image_buffer_size(%rip)
movl th_per_block_y(%rip), %esi
imull th_per_block_x(%rip), %esi
movl %esi, 20(%rsp)
imull num_blocks_x(%rip), %esi
imull num_blocks_y(%rip), %esi
movl %esi, 16(%rsp)
xorl %edx, %edx
idivl %esi
movl %eax, 12(%rsp)
movl %ecx, i_x_max(%rip)
movsd 40(%rsp), %xmm0 # xmm0 = mem[0],zero
subsd 48(%rsp), %xmm0
cvtsi2sd %ecx, %xmm1
movl %ecx, i_y_max(%rip)
divsd %xmm1, %xmm0
movsd %xmm0, 64(%rsp)
movsd 24(%rsp), %xmm0 # xmm0 = mem[0],zero
subsd 32(%rsp), %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, 56(%rsp)
leaq 48(%rsp), %rsi
movl $c_x_min, %edi
movl $8, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 40(%rsp), %rsi
movl $c_x_max, %edi
movl $8, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 32(%rsp), %rsi
movl $c_y_min, %edi
movl $8, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 24(%rsp), %rsi
movl $c_y_max, %edi
movl $8, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 8(%rsp), %rsi
movl $image_size, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 16(%rsp), %rsi
movl $num_threads, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 20(%rsp), %rsi
movl $th_per_block, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 64(%rsp), %rsi
movl $pixel_width, %edi
movl $8, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 56(%rsp), %rsi
movl $pixel_height, %edi
movl $8, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 12(%rsp), %rsi
movl $pixels_per_thread, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movl $image_buffer_size, %edi
movl $host_image_buffer_size, %esi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
callq hipGetLastError
testl %eax, %eax
jne .LBB2_8
# %bb.6: # %.critedge
addq $72, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_7:
.cfi_def_cfa_offset 96
callq _Z19print_bad_argumentsv
xorl %edi, %edi
callq exit
.LBB2_8: # %_Z5checkR10hipError_tPKc.exit
movl $.L.str, %edi
movl $.L.str.10, %esi
movl %eax, %ebx
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z4initiPPc, .Lfunc_end2-_Z4initiPPc
.cfi_endproc
# -- End function
.globl _Z33__device_stub__compute_mandelbrotPh # -- Begin function _Z33__device_stub__compute_mandelbrotPh
.p2align 4, 0x90
.type _Z33__device_stub__compute_mandelbrotPh,@function
_Z33__device_stub__compute_mandelbrotPh: # @_Z33__device_stub__compute_mandelbrotPh
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z18compute_mandelbrotPh, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z33__device_stub__compute_mandelbrotPh, .Lfunc_end3-_Z33__device_stub__compute_mandelbrotPh
.cfi_endproc
# -- End function
.globl _Z21allocate_image_bufferPPhm # -- Begin function _Z21allocate_image_bufferPPhm
.p2align 4, 0x90
.type _Z21allocate_image_bufferPPhm,@function
_Z21allocate_image_bufferPPhm: # @_Z21allocate_image_bufferPPhm
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
movq %rsi, %rdi
callq malloc
movq %rax, image_buffer_host(%rip)
movq %r14, %rdi
movq %rbx, %rsi
callq hipMalloc
cmpq $0, image_buffer_host(%rip)
je .LBB4_3
# %bb.1:
testl %eax, %eax
jne .LBB4_4
# %bb.2: # %.critedge
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB4_3:
.cfi_def_cfa_offset 32
movq stderr(%rip), %rcx
movl $.L.str.11, %edi
movl $33, %esi
movl $1, %edx
callq fwrite
movl $1, %edi
callq exit
.LBB4_4: # %_Z5checkR10hipError_tPKc.exit
movl $.L.str, %edi
movl $.L.str.12, %esi
movl %eax, %ebx
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end4:
.size _Z21allocate_image_bufferPPhm, .Lfunc_end4-_Z21allocate_image_bufferPPhm
.cfi_endproc
# -- End function
.globl _Z13write_to_filev # -- Begin function _Z13write_to_filev
.p2align 4, 0x90
.type _Z13write_to_filev,@function
_Z13write_to_filev: # @_Z13write_to_filev
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.L.str.13, %edi
movl $.L.str.15, %esi
callq fopen
movq %rax, %rbx
movl i_x_max(%rip), %ecx
movl i_y_max(%rip), %r8d
movl $.L.str.16, %esi
movl $.L.str.14, %edx
movq %rax, %rdi
movl $255, %r9d
xorl %eax, %eax
callq fprintf
cmpl $0, host_image_buffer_size(%rip)
jle .LBB5_3
# %bb.1: # %.lr.ph.preheader
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq image_buffer_host(%rip), %rdi
addq %r14, %rdi
movl $1, %esi
movl $3, %edx
movq %rbx, %rcx
callq fwrite
incq %r15
movslq host_image_buffer_size(%rip), %rax
addq $3, %r14
cmpq %rax, %r15
jl .LBB5_2
.LBB5_3: # %._crit_edge
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end5:
.size _Z13write_to_filev, .Lfunc_end5-_Z13write_to_filev
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $80, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
callq _Z4initiPPc
movslq host_image_buffer_size(%rip), %rax
leaq (%rax,%rax,2), %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq _Z21allocate_image_bufferPPhm
movl num_blocks_x(%rip), %eax
movl num_blocks_y(%rip), %ecx
movl %eax, num_blocks(%rip)
movl %ecx, num_blocks+4(%rip)
movl $1, num_blocks+8(%rip)
movl th_per_block_x(%rip), %eax
movl th_per_block_y(%rip), %ecx
movl %eax, threads_per_block(%rip)
movl %ecx, threads_per_block+4(%rip)
movl $1, threads_per_block+8(%rip)
movq num_blocks(%rip), %rdi
movq threads_per_block(%rip), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z18compute_mandelbrotPh, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_2:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB6_3
# %bb.5: # %.critedge
movq image_buffer_host(%rip), %rdi
movq 8(%rsp), %rsi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB6_6
# %bb.7: # %.critedge27
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB6_8
# %bb.9: # %.critedge28
movl $.L.str.13, %edi
movl $.L.str.15, %esi
callq fopen
movq %rax, %rbx
movl i_x_max(%rip), %ecx
movl i_y_max(%rip), %r8d
movl $.L.str.16, %esi
movl $.L.str.14, %edx
movq %rax, %rdi
movl $255, %r9d
xorl %eax, %eax
callq fprintf
cmpl $0, host_image_buffer_size(%rip)
jle .LBB6_12
# %bb.10: # %.lr.ph.i.preheader
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB6_11: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq image_buffer_host(%rip), %rdi
addq %r14, %rdi
movl $1, %esi
movl $3, %edx
movq %rbx, %rcx
callq fwrite
incq %r15
movslq host_image_buffer_size(%rip), %rax
addq $3, %r14
cmpq %rax, %r15
jl .LBB6_11
.LBB6_12: # %_Z13write_to_filev.exit
movq %rbx, %rdi
callq fclose
movq image_buffer_host(%rip), %rdi
callq free
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB6_3: # %_Z5checkR10hipError_tPKc.exit
.cfi_def_cfa_offset 112
movl $.L.str, %edi
movl $.L.str.17, %esi
jmp .LBB6_4
.LBB6_6: # %_Z5checkR10hipError_tPKc.exit15
movl $.L.str, %edi
movl $.L.str.18, %esi
jmp .LBB6_4
.LBB6_8: # %_Z5checkR10hipError_tPKc.exit18
movl $.L.str, %edi
movl $.L.str.19, %esi
.LBB6_4: # %_Z5checkR10hipError_tPKc.exit
movl %eax, %ebx
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18compute_mandelbrotPh, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $c_x_min, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $c_x_max, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $c_y_min, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $c_y_max, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $pixel_width, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $pixel_height, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $iteration_max, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $image_size, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $image_buffer_size, %esi
movl $.L__unnamed_10, %edx
movl $.L__unnamed_10, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $num_threads, %esi
movl $.L__unnamed_11, %edx
movl $.L__unnamed_11, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $th_per_block, %esi
movl $.L__unnamed_12, %edx
movl $.L__unnamed_12, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $pixels_per_thread, %esi
movl $.L__unnamed_13, %edx
movl $.L__unnamed_13, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $gradient_size, %esi
movl $.L__unnamed_14, %edx
movl $.L__unnamed_14, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $colors, %esi
movl $.L__unnamed_15, %edx
movl $.L__unnamed_15, %ecx
movl $204, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type c_x_min,@object # @c_x_min
.local c_x_min
.comm c_x_min,8,8
.type c_x_max,@object # @c_x_max
.local c_x_max
.comm c_x_max,8,8
.type c_y_min,@object # @c_y_min
.local c_y_min
.comm c_y_min,8,8
.type c_y_max,@object # @c_y_max
.local c_y_max
.comm c_y_max,8,8
.type pixel_width,@object # @pixel_width
.local pixel_width
.comm pixel_width,8,8
.type pixel_height,@object # @pixel_height
.local pixel_height
.comm pixel_height,8,8
.type iteration_max,@object # @iteration_max
.local iteration_max
.comm iteration_max,4,4
.type image_size,@object # @image_size
.local image_size
.comm image_size,4,4
.type image_buffer_size,@object # @image_buffer_size
.local image_buffer_size
.comm image_buffer_size,4,4
.type num_threads,@object # @num_threads
.local num_threads
.comm num_threads,4,4
.type th_per_block,@object # @th_per_block
.local th_per_block
.comm th_per_block,4,4
.type pixels_per_thread,@object # @pixels_per_thread
.local pixels_per_thread
.comm pixels_per_thread,4,4
.type gradient_size,@object # @gradient_size
.local gradient_size
.comm gradient_size,4,4
.type colors,@object # @colors
.local colors
.comm colors,204,16
.type num_blocks,@object # @num_blocks
.data
.globl num_blocks
.p2align 3, 0x0
num_blocks:
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.size num_blocks, 12
.type threads_per_block,@object # @threads_per_block
.globl threads_per_block
.p2align 3, 0x0
threads_per_block:
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.size threads_per_block, 12
.type num_blocks_x,@object # @num_blocks_x
.bss
.globl num_blocks_x
.p2align 2, 0x0
num_blocks_x:
.long 0 # 0x0
.size num_blocks_x, 4
.type th_per_block_x,@object # @th_per_block_x
.globl th_per_block_x
.p2align 2, 0x0
th_per_block_x:
.long 0 # 0x0
.size th_per_block_x, 4
.type num_blocks_y,@object # @num_blocks_y
.globl num_blocks_y
.p2align 2, 0x0
num_blocks_y:
.long 0 # 0x0
.size num_blocks_y, 4
.type th_per_block_y,@object # @th_per_block_y
.globl th_per_block_y
.p2align 2, 0x0
th_per_block_y:
.long 0 # 0x0
.size th_per_block_y, 4
.type host_image_buffer_size,@object # @host_image_buffer_size
.globl host_image_buffer_size
.p2align 2, 0x0
host_image_buffer_size:
.long 0 # 0x0
.size host_image_buffer_size, 4
.type image_buffer_host,@object # @image_buffer_host
.globl image_buffer_host
.p2align 3, 0x0
image_buffer_host:
.quad 0
.size image_buffer_host, 8
.type i_x_max,@object # @i_x_max
.globl i_x_max
.p2align 2, 0x0
i_x_max:
.long 0 # 0x0
.size i_x_max, 4
.type i_y_max,@object # @i_y_max
.globl i_y_max
.p2align 2, 0x0
i_y_max:
.long 0 # 0x0
.size i_y_max, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " | Error: %s\n"
.size .L.str.1, 14
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%lf"
.size .L.str.8, 4
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d"
.size .L.str.9, 3
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Failed to copy command line args to device"
.size .L.str.10, 43
.type _Z18compute_mandelbrotPh,@object # @_Z18compute_mandelbrotPh
.section .rodata,"a",@progbits
.globl _Z18compute_mandelbrotPh
.p2align 3, 0x0
_Z18compute_mandelbrotPh:
.quad _Z33__device_stub__compute_mandelbrotPh
.size _Z18compute_mandelbrotPh, 8
.type .L.str.11,@object # @.str.11
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.11:
.asciz "Failed to allocate host vectors!\n"
.size .L.str.11, 34
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Failed to allocate device image buffer"
.size .L.str.12, 39
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "output.ppm"
.size .L.str.13, 11
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "# "
.size .L.str.14, 3
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "wb"
.size .L.str.15, 3
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "P6\n %s\n %d\n %d\n %d\n"
.size .L.str.16, 20
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Failed to launch compute_mandelbrot kernel"
.size .L.str.17, 43
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "Failed to copy vector from device to host"
.size .L.str.18, 42
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "Failed to free device vector"
.size .L.str.19, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18compute_mandelbrotPh"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "c_x_min"
.size .L__unnamed_2, 8
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "c_x_max"
.size .L__unnamed_3, 8
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "c_y_min"
.size .L__unnamed_4, 8
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "c_y_max"
.size .L__unnamed_5, 8
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "pixel_width"
.size .L__unnamed_6, 12
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "pixel_height"
.size .L__unnamed_7, 13
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "iteration_max"
.size .L__unnamed_8, 14
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "image_size"
.size .L__unnamed_9, 11
.type .L__unnamed_10,@object # @9
.L__unnamed_10:
.asciz "image_buffer_size"
.size .L__unnamed_10, 18
.type .L__unnamed_11,@object # @10
.L__unnamed_11:
.asciz "num_threads"
.size .L__unnamed_11, 12
.type .L__unnamed_12,@object # @11
.L__unnamed_12:
.asciz "th_per_block"
.size .L__unnamed_12, 13
.type .L__unnamed_13,@object # @12
.L__unnamed_13:
.asciz "pixels_per_thread"
.size .L__unnamed_13, 18
.type .L__unnamed_14,@object # @13
.L__unnamed_14:
.asciz "gradient_size"
.size .L__unnamed_14, 14
.type .L__unnamed_15,@object # @14
.L__unnamed_15:
.asciz "colors"
.size .L__unnamed_15, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "usage: ./mandelbrot_seq c_x_min c_x_max c_y_min c_y_max image_size NUM_BLOCKS TH_PER_BLOCK "
.size .Lstr, 92
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "examples with image_size = 11500:"
.size .Lstr.1, 34
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz " Full Picture: ./mandelbrot_cuda -2.5 1.5 -2.0 2.0 11500 4 64 "
.size .Lstr.2, 74
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz " Seahorse Valley: ./mandelbrot_cuda -0.8 -0.7 0.05 0.15 11500 4 64 "
.size .Lstr.3, 76
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz " Elephant Valley: ./mandelbrot_cuda 0.175 0.375 -0.1 0.1 11500 4 64 "
.size .Lstr.4, 77
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz " Triple Spiral Valley: ./mandelbrot_cuda -0.188 -0.012 0.554 0.754 11500 4 64 "
.size .Lstr.5, 82
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__compute_mandelbrotPh
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym c_x_min
.addrsig_sym c_x_max
.addrsig_sym c_y_min
.addrsig_sym c_y_max
.addrsig_sym pixel_width
.addrsig_sym pixel_height
.addrsig_sym iteration_max
.addrsig_sym image_size
.addrsig_sym image_buffer_size
.addrsig_sym num_threads
.addrsig_sym th_per_block
.addrsig_sym pixels_per_thread
.addrsig_sym gradient_size
.addrsig_sym colors
.addrsig_sym num_blocks_x
.addrsig_sym th_per_block_x
.addrsig_sym num_blocks_y
.addrsig_sym th_per_block_y
.addrsig_sym host_image_buffer_size
.addrsig_sym _Z18compute_mandelbrotPh
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z18compute_mandelbrotPh
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x4][0x54] ; /* 0x01001500ff037624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x4][0x50] ; /* 0x01001400ff027624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R4, c[0x4][0x58] ; /* 0x0100160000047a02 */
/* 0x000fc80000000f00 */
/*0050*/ LDG.E R3, [R2.64] ; /* 0x0000000802037981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x5c] ; /* 0x01001700ff057624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R7, c[0x4][0x44] ; /* 0x0100110000077a02 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x4][0x40] ; /* 0x01001000ff067624 */
/* 0x000fc600078e00ff */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000804047981 */
/* 0x000ee8000c1e1900 */
/*00a0*/ LDG.E R7, [R6.64] ; /* 0x0000000806077981 */
/* 0x000f22000c1e1900 */
/*00b0*/ S2UR UR4, SR_CTAID.Y ; /* 0x00000000000479c3 */
/* 0x000e220000002600 */
/*00c0*/ ULDC UR6, c[0x0][0xc] ; /* 0x0000030000067ab9 */
/* 0x000fe40000000800 */
/*00d0*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002200 */
/*00e0*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*00f0*/ S2UR UR5, SR_CTAID.X ; /* 0x00000000000579c3 */
/* 0x000e220000002500 */
/*0100*/ IMAD R0, R0, c[0x0][0x0], R9 ; /* 0x0000000000007a24 */
/* 0x002fe200078e0209 */
/*0110*/ UIMAD UR4, UR4, UR6, UR5 ; /* 0x00000006040472a4 */
/* 0x001fcc000f8e0205 */
/*0120*/ IMAD R0, R3, UR4, R0 ; /* 0x0000000403007c24 */
/* 0x004fca000f8e0200 */
/*0130*/ LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff027212 */
/* 0x000fe200078e33ff */
/*0140*/ IMAD R19, R0, R4, RZ ; /* 0x0000000400137224 */
/* 0x008fc800078e02ff */
/*0150*/ IMAD.IADD R0, R2, 0x1, R7 ; /* 0x0000000102007824 */
/* 0x010fca00078e0207 */
/*0160*/ ISETP.GT.AND P0, PT, R19, R0, PT ; /* 0x000000001300720c */
/* 0x000fda0003f04270 */
/*0170*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0180*/ IMAD.IADD R18, R4, 0x1, R19 ; /* 0x0000000104127824 */
/* 0x000fe400078e0213 */
/*0190*/ MOV R2, c[0x4][0x38] ; /* 0x01000e0000027a02 */
/* 0x000fe20000000f00 */
/*01a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x4][0x3c] ; /* 0x01000f00ff037624 */
/* 0x000fca00078e00ff */
/*01b0*/ LDG.E R4, [R2.64] ; /* 0x0000000802047981 */
/* 0x0010a2000c1e1900 */
/*01c0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x4][0x28] ; /* 0x01000a00ff067624 */
/* 0x000fe200078e00ff */
/*01d0*/ MOV R7, c[0x4][0x2c] ; /* 0x01000b0000077a02 */
/* 0x000fe20000000f00 */
/*01e0*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff0c7624 */
/* 0x000fe400078e00ff */
/*01f0*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff0d7624 */
/* 0x000fe200078e00ff */
/*0200*/ MOV R14, c[0x4][0x30] ; /* 0x01000c00000e7a02 */
/* 0x000fe20000000f00 */
/*0210*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x4][0x34] ; /* 0x01000d00ff0f7624 */
/* 0x000fe200078e00ff */
/*0220*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000806067981 */
/* 0x000ee8000c1e1b00 */
/*0230*/ LDG.E.64 R12, [R12.64] ; /* 0x000000080c0c7981 */
/* 0x000ee8000c1e1b00 */
/*0240*/ LDG.E R5, [R14.64] ; /* 0x000000080e057981 */
/* 0x000322000c1e1900 */
/*0250*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x4][0x20] ; /* 0x01000800ff087624 */
/* 0x000fe200078e00ff */
/*0260*/ MOV R9, c[0x4][0x24] ; /* 0x0100090000097a02 */
/* 0x000fe20000000f00 */
/*0270*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x4][0x0] ; /* 0x01000000ff0a7624 */
/* 0x000fc400078e00ff */
/*0280*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x4][0x4] ; /* 0x01000100ff0b7624 */
/* 0x000fe200078e00ff */
/*0290*/ MOV R2, c[0x4][0x60] ; /* 0x0100180000027a02 */
/* 0x001fe20000000f00 */
/*02a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x4][0x64] ; /* 0x01001900ff037624 */
/* 0x000fe200078e00ff */
/*02b0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000808087981 */
/* 0x000ee8000c1e1b00 */
/*02c0*/ LDG.E.64 R10, [R10.64] ; /* 0x000000080a0a7981 */
/* 0x000ee8000c1e1b00 */
/*02d0*/ LDG.E R20, [R2.64] ; /* 0x0000000802147981 */
/* 0x000162000c1e1900 */
/*02e0*/ IABS R22, R19 ; /* 0x0000001300167213 */
/* 0x000fc40000000000 */
/*02f0*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0300*/ IABS R16, R4.reuse ; /* 0x0000000400107213 */
/* 0x084fe40000000000 */
/*0310*/ IABS R23, R4 ; /* 0x0000000400177213 */
/* 0x000fe40000000000 */
/*0320*/ I2F.RP R17, R16 ; /* 0x0000001000117306 */
/* 0x000eb00000209400 */
/*0330*/ MUFU.RCP R17, R17 ; /* 0x0000001100117308 */
/* 0x004e640000001000 */
/*0340*/ IADD3 R14, R17, 0xffffffe, RZ ; /* 0x0ffffffe110e7810 */
/* 0x002fe20007ffe0ff */
/*0350*/ IMAD.MOV R17, RZ, RZ, -R23 ; /* 0x000000ffff117224 */
/* 0x000fca00078e0a17 */
/*0360*/ F2I.FTZ.U32.TRUNC.NTZ R15, R14 ; /* 0x0000000e000f7305 */
/* 0x0002a4000021f000 */
/*0370*/ HFMA2.MMA R14, -RZ, RZ, 0, 0 ; /* 0x00000000ff0e7435 */
/* 0x002fe200000001ff */
/*0380*/ IMAD.MOV R21, RZ, RZ, -R15 ; /* 0x000000ffff157224 */
/* 0x004fc800078e0a0f */
/*0390*/ IMAD R21, R21, R16, RZ ; /* 0x0000001015157224 */
/* 0x000fca00078e02ff */
/*03a0*/ IMAD.HI.U32 R15, R15, R21, R14 ; /* 0x000000150f0f7227 */
/* 0x000fe200078e000e */
/*03b0*/ LOP3.LUT R14, R19, R4, RZ, 0x3c, !PT ; /* 0x00000004130e7212 */
/* 0x000fc600078e3cff */
/*03c0*/ IMAD R21, R19, 0x3, RZ ; /* 0x0000000313157824 */
/* 0x000fe200078e02ff */
/*03d0*/ ISETP.GE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe20003f26270 */
/*03e0*/ IMAD.HI.U32 R15, R15, R22, RZ ; /* 0x000000160f0f7227 */
/* 0x000fc800078e00ff */
/*03f0*/ IMAD R17, R15, R17, R22 ; /* 0x000000110f117224 */
/* 0x000fca00078e0216 */
/*0400*/ ISETP.GT.U32.AND P2, PT, R16, R17, PT ; /* 0x000000111000720c */
/* 0x000fda0003f44070 */
/*0410*/ @!P2 IMAD.IADD R17, R17, 0x1, -R16 ; /* 0x000000011111a824 */
/* 0x000fe200078e0a10 */
/*0420*/ @!P2 IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0fa810 */
/* 0x000fe40007ffe0ff */
/*0430*/ ISETP.NE.AND P2, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f45270 */
/*0440*/ ISETP.GE.U32.AND P0, PT, R17, R16, PT ; /* 0x000000101100720c */
/* 0x000fda0003f06070 */
/*0450*/ @P0 IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f0810 */
/* 0x000fc80007ffe0ff */
/*0460*/ MOV R16, R15 ; /* 0x0000000f00107202 */
/* 0x000fca0000000f00 */
/*0470*/ @!P1 IMAD.MOV R16, RZ, RZ, -R16 ; /* 0x000000ffff109224 */
/* 0x000fe200078e0a10 */
/*0480*/ @!P2 LOP3.LUT R16, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff10a212 */
/* 0x000fe400078e33ff */
/*0490*/ ISETP.GE.AND P2, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x010fe40003f46270 */
/*04a0*/ I2F.F64 R14, R16 ; /* 0x00000010000e7312 */
/* 0x000ee20000201c00 */
/*04b0*/ IMAD.MOV R17, RZ, RZ, -R16 ; /* 0x000000ffff117224 */
/* 0x000fc800078e0a10 */
/*04c0*/ IMAD R17, R4, R17, R19 ; /* 0x0000001104117224 */
/* 0x000fe200078e0213 */
/*04d0*/ IADD3 R4, P0, R21, c[0x0][0x160], RZ ; /* 0x0000580015047a10 */
/* 0x000fe20007f1e0ff */
/*04e0*/ DFMA R14, R14, R6, R12 ; /* 0x000000060e0e722b */
/* 0x0083e4000000000c */
/*04f0*/ I2F.F64 R12, R17 ; /* 0x00000011000c7312 */
/* 0x002e640000201c00 */
/*0500*/ DMUL R6, R6, 0.5 ; /* 0x3fe0000006067828 */
/* 0x000e8c0000000000 */
/*0510*/ DSETP.GEU.AND P1, PT, |R14|, R6, PT ; /* 0x000000060e00722a */
/* 0x004e8c0003f2e200 */
/*0520*/ FSEL R6, R14, RZ, P1 ; /* 0x000000ff0e067208 */
/* 0x004fe20000800000 */
/*0530*/ DFMA R8, R12, R8, R10 ; /* 0x000000080c08722b */
/* 0x002062000000000a */
/*0540*/ FSEL R7, R15, RZ, P1 ; /* 0x000000ff0f077208 */
/* 0x000fe20000800000 */
/*0550*/ @!P2 BRA 0x680 ; /* 0x000001200000a947 */
/* 0x000fea0003800000 */
/*0560*/ BSSY B0, 0x680 ; /* 0x0000011000007945 */
/* 0x003fe20003800000 */
/*0570*/ IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff187224 */
/* 0x000fe200078e00ff */
/*0580*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fe2000001ff00 */
/*0590*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe2000001ff00 */
/*05a0*/ CS2R R14, SRZ ; /* 0x00000000000e7805 */
/* 0x000fe2000001ff00 */
/*05b0*/ CS2R R16, SRZ ; /* 0x0000000000107805 */
/* 0x000fcc000001ff00 */
/*05c0*/ DADD R14, -R16, R14 ; /* 0x00000000100e7229 */
/* 0x000e22000000010e */
/*05d0*/ IADD3 R24, R24, 0x1, RZ ; /* 0x0000000118187810 */
/* 0x000fc60007ffe0ff */
/*05e0*/ DADD R16, R10, R10 ; /* 0x000000000a107229 */
/* 0x000e62000000000a */
/*05f0*/ ISETP.GE.AND P1, PT, R24, R5, PT ; /* 0x000000051800720c */
/* 0x000fc60003f26270 */
/*0600*/ DADD R10, R8, R14 ; /* 0x00000000080a7229 */
/* 0x001e08000000000e */
/*0610*/ DFMA R12, R16, R12, R6 ; /* 0x0000000c100c722b */
/* 0x002e480000000006 */
/*0620*/ DMUL R14, R10, R10 ; /* 0x0000000a0a0e7228 */
/* 0x001fc80000000000 */
/*0630*/ DMUL R16, R12, R12 ; /* 0x0000000c0c107228 */
/* 0x002e0c0000000000 */
/*0640*/ DADD R22, R14, R16 ; /* 0x000000000e167229 */
/* 0x001e0c0000000010 */
/*0650*/ DSETP.LT.AND P2, PT, R22, 4, PT ; /* 0x401000001600742a */
/* 0x001e1c0003f41000 */
/*0660*/ @!P1 BRA P2, 0x5c0 ; /* 0xffffff5000009947 */
/* 0x001fea000103ffff */
/*0670*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0680*/ ISETP.NE.AND P1, PT, R5, R24, PT ; /* 0x000000180500720c */
/* 0x003fe20003f25270 */
/*0690*/ BSSY B0, 0x9c0 ; /* 0x0000032000007945 */
/* 0x000fe20003800000 */
/*06a0*/ LEA.HI.X.SX32 R5, R21, c[0x0][0x164], 0x1, P0 ; /* 0x0000590015057a11 */
/* 0x000fe400000f0eff */
/*06b0*/ SHF.R.S32.HI R6, RZ, 0x1f, R20 ; /* 0x0000001fff067819 */
/* 0x020fd20000011414 */
/*06c0*/ @!P1 BRA 0x8d0 ; /* 0x0000020000009947 */
/* 0x000fea0003800000 */
/*06d0*/ IABS R8, R20.reuse ; /* 0x0000001400087213 */
/* 0x080fe40000000000 */
/*06e0*/ IABS R9, R20 ; /* 0x0000001400097213 */
/* 0x000fe40000000000 */
/*06f0*/ I2F.U32.RP R6, R8 ; /* 0x0000000800067306 */
/* 0x000e220000209000 */
/*0700*/ ISETP.GE.AND P2, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x000fe40003f46270 */
/*0710*/ IADD3 R9, RZ, -R9, RZ ; /* 0x80000009ff097210 */
/* 0x000fca0007ffe0ff */
/*0720*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0730*/ IADD3 R2, R6, 0xffffffe, RZ ; /* 0x0ffffffe06027810 */
/* 0x001fe40007ffe0ff */
/*0740*/ IABS R6, R24 ; /* 0x0000001800067213 */
/* 0x000fc80000000000 */
/*0750*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0760*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0770*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*0780*/ IMAD R7, R7, R8, RZ ; /* 0x0000000807077224 */
/* 0x000fc800078e02ff */
/*0790*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*07a0*/ MOV R2, 0xc ; /* 0x0000000c00027802 */
/* 0x000fc60000000f00 */
/*07b0*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0009 */
/*07c0*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fc800078e00ff */
/*07d0*/ IMAD R3, R3, R7, R6 ; /* 0x0000000703037224 */
/* 0x000fca00078e0206 */
/*07e0*/ ISETP.GT.U32.AND P0, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f04070 */
/*07f0*/ @!P0 IADD3 R3, R3, -R8, RZ ; /* 0x8000000803038210 */
/* 0x000fe40007ffe0ff */
/*0800*/ ISETP.NE.AND P0, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe40003f05270 */
/*0810*/ ISETP.GT.U32.AND P1, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f24070 */
/*0820*/ @!P1 IMAD.IADD R3, R3, 0x1, -R8 ; /* 0x0000000103039824 */
/* 0x000fc800078e0a08 */
/*0830*/ @!P2 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff03a224 */
/* 0x000fe200078e0a03 */
/*0840*/ @!P0 LOP3.LUT R3, RZ, R20, RZ, 0x33, !PT ; /* 0x00000014ff038212 */
/* 0x000fca00078e33ff */
/*0850*/ IMAD.WIDE R2, R3, R2, c[0x4][0x68] ; /* 0x01001a0003027625 */
/* 0x000fca00078e0202 */
/*0860*/ LDG.E R7, [R2.64] ; /* 0x0000000802077981 */
/* 0x000ea8000c1e1900 */
/*0870*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0041e8000c101108 */
/*0880*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040802097981 */
/* 0x000ea8000c1e1900 */
/*0890*/ STG.E.U8 [R4.64+0x1], R9 ; /* 0x0000010904007986 */
/* 0x0041e8000c101108 */
/*08a0*/ LDG.E R11, [R2.64+0x8] ; /* 0x00000808020b7981 */
/* 0x000ea8000c1e1900 */
/*08b0*/ STG.E.U8 [R4.64+0x2], R11 ; /* 0x0000020b04007986 */
/* 0x0041e2000c101108 */
/*08c0*/ BRA 0x9b0 ; /* 0x000000e000007947 */
/* 0x000fea0003800000 */
/*08d0*/ IMAD.MOV.U32 R9, RZ, RZ, 0xc ; /* 0x0000000cff097424 */
/* 0x000fe400078e00ff */
/*08e0*/ IMAD R7, R6, 0xc, RZ ; /* 0x0000000c06077824 */
/* 0x000fc400078e02ff */
/*08f0*/ IMAD.WIDE.U32 R20, R20, R9, c[0x4][0x68] ; /* 0x01001a0014147625 */
/* 0x000fc800078e0009 */
/*0900*/ IMAD.IADD R21, R21, 0x1, R7 ; /* 0x0000000115157824 */
/* 0x000fcc00078e0207 */
/*0910*/ LDG.E R21, [R20.64] ; /* 0x0000000814157981 */
/* 0x000ea8000c1e1900 */
/*0920*/ STG.E.U8 [R4.64], R21 ; /* 0x0000001504007986 */
/* 0x0041e8000c101108 */
/*0930*/ LDG.E R6, [R2.64] ; /* 0x0000000802067981 */
/* 0x000ea4000c1e1900 */
/*0940*/ IMAD.WIDE R6, R6, R9, c[0x4][0x68] ; /* 0x01001a0006067625 */
/* 0x004fcc00078e0209 */
/*0950*/ LDG.E R7, [R6.64+0x4] ; /* 0x0000040806077981 */
/* 0x000ea8000c1e1900 */
/*0960*/ STG.E.U8 [R4.64+0x1], R7 ; /* 0x0000010704007986 */
/* 0x0041e8000c101108 */
/*0970*/ LDG.E R8, [R2.64] ; /* 0x0000000802087981 */
/* 0x000ea4000c1e1900 */
/*0980*/ IMAD.WIDE R8, R8, R9, c[0x4][0x68] ; /* 0x01001a0008087625 */
/* 0x004fcc00078e0209 */
/*0990*/ LDG.E R9, [R8.64+0x8] ; /* 0x0000080808097981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ STG.E.U8 [R4.64+0x2], R9 ; /* 0x0000020904007986 */
/* 0x0041e4000c101108 */
/*09b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*09c0*/ IADD3 R3, R19, 0x1, RZ ; /* 0x0000000113037810 */
/* 0x000fe20007ffe0ff */
/*09d0*/ BSSY B0, 0xa40 ; /* 0x0000006000007945 */
/* 0x000fe60003800000 */
/*09e0*/ ISETP.NE.AND P0, PT, R3, R18, PT ; /* 0x000000120300720c */
/* 0x000fda0003f05270 */
/*09f0*/ @P0 BRA 0xa30 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0a00*/ ISETP.GT.AND P0, PT, R0, R19, PT ; /* 0x000000130000720c */
/* 0x000fda0003f04270 */
/*0a10*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0a20*/ MOV R3, R0 ; /* 0x0000000000037202 */
/* 0x000fe40000000f00 */
/*0a30*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a40*/ ISETP.GT.AND P0, PT, R3, R0, PT ; /* 0x000000000300720c */
/* 0x000fe20003f04270 */
/*0a50*/ IMAD.MOV.U32 R19, RZ, RZ, R3 ; /* 0x000000ffff137224 */
/* 0x000fd800078e0003 */
/*0a60*/ @!P0 BRA 0x190 ; /* 0xfffff72000008947 */
/* 0x000fea000383ffff */
/*0a70*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a80*/ BRA 0xa80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18compute_mandelbrotPh
.globl _Z18compute_mandelbrotPh
.p2align 8
.type _Z18compute_mandelbrotPh,@function
_Z18compute_mandelbrotPh:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x8
s_load_b32 s7, s[0:1], 0x14
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, th_per_block@rel32@lo+4
s_addc_u32 s3, s3, th_per_block@rel32@hi+12
v_bfe_u32 v1, v0, 10, 10
s_load_b32 s8, s[2:3], 0x0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, pixels_per_thread@rel32@lo+4
s_addc_u32 s3, s3, pixels_per_thread@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, image_buffer_size@rel32@lo+4
s_addc_u32 s5, s5, image_buffer_size@rel32@hi+12
s_load_b32 s2, s[2:3], 0x0
s_load_b32 s3, s[4:5], 0x0
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s5, s6, s15
s_and_b32 s4, s7, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_u32_u24_e32 v1, s4, v1
s_add_i32 s4, s5, s14
s_mul_i32 s4, s4, s8
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v0, v1, v0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mul_lo_u32 v16, v0, s2
v_xad_u32 v14, v0, -1, s3
s_mov_b32 s3, exec_lo
v_cmpx_le_i32_e64 v16, v14
s_cbranch_execz .LBB0_15
s_load_b64 s[0:1], s[0:1], 0x0
v_add_nc_u32_e32 v15, s2, v16
v_mov_b32_e32 v1, 0
s_mov_b32 s4, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s0, 2
s_addc_u32 s3, s1, 0
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s7
v_mov_b32_e32 v16, v0
s_and_b32 s5, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s4, s5, s4
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_15
.LBB0_3:
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, iteration_max@rel32@lo+4
s_addc_u32 s7, s7, iteration_max@rel32@hi+12
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, image_size@rel32@lo+4
s_addc_u32 s9, s9, image_size@rel32@hi+12
s_clause 0x1
global_load_b32 v0, v1, s[6:7]
global_load_b32 v2, v1, s[8:9]
s_waitcnt vmcnt(1)
v_cmp_gt_i32_e32 vcc_lo, 1, v0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s6, v2
v_readfirstlane_b32 s5, v0
v_mov_b32_e32 v0, 0
s_cbranch_vccnz .LBB0_7
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, c_y_min@rel32@lo+4
s_addc_u32 s9, s9, c_y_min@rel32@hi+12
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, pixel_height@rel32@lo+4
s_addc_u32 s11, s11, pixel_height@rel32@hi+12
v_ashrrev_i32_e32 v12, 31, v16
s_clause 0x1
global_load_b64 v[2:3], v1, s[8:9]
global_load_b64 v[4:5], v1, s[10:11]
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, c_x_min@rel32@lo+4
s_addc_u32 s9, s9, c_x_min@rel32@hi+12
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, pixel_width@rel32@lo+4
s_addc_u32 s11, s11, pixel_width@rel32@hi+12
s_clause 0x1
global_load_b64 v[6:7], v1, s[8:9]
global_load_b64 v[8:9], v1, s[10:11]
s_ashr_i32 s7, s6, 31
v_add_nc_u32_e32 v11, v16, v12
s_add_i32 s8, s6, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s8, s8, s7
v_cvt_f32_u32_e32 v0, s8
s_sub_i32 s9, 0, s8
v_xor_b32_e32 v13, v11, v12
v_xor_b32_e32 v12, s7, v12
s_mov_b32 s7, 0
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v10, s9, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v10, v0, v10
v_add_nc_u32_e32 v0, v0, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[10:11], null, v13, v0, 0
v_mul_lo_u32 v0, v11, s8
v_add_nc_u32_e32 v10, 1, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v13, v0
v_subrev_nc_u32_e32 v13, s8, v0
v_cmp_le_u32_e32 vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v10, v11, v10, vcc_lo
v_dual_cndmask_b32 v0, v0, v13 :: v_dual_add_nc_u32 v11, 1, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s8, v0
v_cndmask_b32_e32 v0, v10, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v12
v_sub_nc_u32_e32 v0, v0, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cvt_f64_i32_e32 v[10:11], v0
v_mul_lo_u32 v0, v0, s6
s_mov_b32 s6, 0
v_sub_nc_u32_e32 v0, v16, v0
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[12:13], v[4:5], v[10:11], v[2:3]
v_mul_f64 v[2:3], v[4:5], 0.5
v_cvt_f64_i32_e32 v[4:5], v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_nlt_f64_e64 vcc_lo, |v[12:13]|, v[2:3]
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[8:9], v[4:5], v[6:7]
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v7, v5
v_dual_mov_b32 v11, v5 :: v_dual_mov_b32 v6, v4
v_dual_mov_b32 v10, v4 :: v_dual_cndmask_b32 v9, 0, v13
v_dual_cndmask_b32 v8, 0, v12 :: v_dual_mov_b32 v13, v5
v_mov_b32_e32 v12, v4
.p2align 6
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_f64 v[10:11], v[10:11], -v[12:13]
v_add_f64 v[12:13], v[4:5], v[4:5]
s_add_i32 s7, s7, 1
s_cmp_ge_i32 s7, s5
v_mov_b32_e32 v0, s7
s_cselect_b32 s8, -1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[4:5], v[2:3], v[10:11]
v_fma_f64 v[6:7], v[6:7], v[12:13], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[4:5], v[4:5]
v_fma_f64 v[12:13], v[6:7], v[6:7], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_ngt_f64_e32 vcc_lo, 4.0, v[12:13]
v_mul_f64 v[12:13], v[6:7], v[6:7]
s_or_b32 s8, s8, vcc_lo
s_and_b32 s8, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s6, s8, s6
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_5
s_or_b32 exec_lo, exec_lo, s6
.LBB0_7:
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, gradient_size@rel32@lo+4
s_addc_u32 s7, s7, gradient_size@rel32@hi+12
v_cmp_ne_u32_e32 vcc_lo, s5, v0
global_load_b32 v2, v1, s[6:7]
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s5, v2
s_and_saveexec_b32 s6, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB0_9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_ashr_i32 s7, s5, 31
v_ashrrev_i32_e32 v4, 31, v0
s_add_i32 s8, s5, s7
s_xor_b32 s7, s8, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, v0, v4
v_cvt_f32_u32_e32 v2, s7
s_sub_i32 s8, 0, s7
v_xor_b32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s8, v2
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, colors@rel32@lo+4
s_addc_u32 s9, s9, colors@rel32@hi+12
v_mul_hi_u32 v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v3
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s7
v_sub_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s7, v0
v_cmp_le_u32_e32 vcc_lo, s7, v0
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s7, v0
v_cmp_le_u32_e32 vcc_lo, s7, v0
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v4
v_sub_nc_u32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, v0, 12, s[8:9]
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, colors@rel32@lo+8
s_addc_u32 s9, s9, colors@rel32@hi+16
v_mad_u64_u32 v[4:5], null, v0, 12, s[8:9]
global_load_b32 v8, v[2:3], off
v_lshl_add_u32 v2, v16, 1, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v6, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b8 v[6:7], v8, off
global_load_b32 v8, v[4:5], off
v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
s_waitcnt vmcnt(0)
global_store_b8 v[6:7], v8, off offset:1
.LBB0_9:
s_and_not1_saveexec_b32 s6, s6
s_cbranch_execz .LBB0_11
s_mul_i32 s7, s5, 12
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, colors@rel32@lo+4
s_addc_u32 s9, s9, colors@rel32@hi+12
s_mul_hi_i32 s5, s5, 12
s_add_u32 s8, s7, s8
s_addc_u32 s9, s5, s9
v_lshl_add_u32 v2, v16, 1, v16
global_load_b32 v0, v1, s[8:9]
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, gradient_size@rel32@lo+4
s_addc_u32 s9, s9, gradient_size@rel32@hi+12
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, colors@rel32@lo+8
s_addc_u32 s11, s11, colors@rel32@hi+16
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v4, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b8 v[4:5], v0, off
global_load_b32 v0, v1, s[8:9]
s_waitcnt vmcnt(0)
v_mul_lo_u32 v6, v0, 12
v_mul_hi_i32 v0, v0, 12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v6, s10
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v0, vcc_lo
global_load_b32 v0, v[6:7], off
s_waitcnt vmcnt(0)
global_store_b8 v[4:5], v0, off offset:1
global_load_b32 v4, v1, s[8:9]
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v5, 31, v4
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s6
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, colors@rel32@lo+12
s_addc_u32 s7, s7, colors@rel32@hi+20
v_add_co_u32 v2, vcc_lo, s2, v2
v_mad_u64_u32 v[6:7], null, v4, 12, s[6:7]
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v0, v7
v_mad_u64_u32 v[7:8], null, v5, 12, v[0:1]
v_add_nc_u32_e32 v0, 1, v16
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e64 s5, v0, v15
global_load_b32 v4, v[6:7], off
s_waitcnt vmcnt(0)
global_store_b8 v[2:3], v4, off
v_cmpx_eq_u32_e64 v0, v15
v_cmp_gt_i32_e32 vcc_lo, v14, v16
v_mov_b32_e32 v0, v14
s_and_not1_b32 s5, s5, exec_lo
s_and_b32 s7, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s5, s5, s7
s_or_b32 exec_lo, exec_lo, s6
s_mov_b32 s6, -1
s_and_saveexec_b32 s7, s5
s_cbranch_execz .LBB0_2
v_cmp_gt_i32_e32 vcc_lo, v0, v14
s_or_not1_b32 s6, vcc_lo, exec_lo
s_branch .LBB0_2
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18compute_mandelbrotPh
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18compute_mandelbrotPh, .Lfunc_end0-_Z18compute_mandelbrotPh
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected c_x_min
.type c_x_min,@object
.section .bss,"aw",@nobits
.globl c_x_min
.p2align 3, 0x0
c_x_min:
.quad 0x0000000000000000
.size c_x_min, 8
.protected c_x_max
.type c_x_max,@object
.globl c_x_max
.p2align 3, 0x0
c_x_max:
.quad 0x0000000000000000
.size c_x_max, 8
.protected c_y_min
.type c_y_min,@object
.globl c_y_min
.p2align 3, 0x0
c_y_min:
.quad 0x0000000000000000
.size c_y_min, 8
.protected c_y_max
.type c_y_max,@object
.globl c_y_max
.p2align 3, 0x0
c_y_max:
.quad 0x0000000000000000
.size c_y_max, 8
.protected pixel_width
.type pixel_width,@object
.globl pixel_width
.p2align 3, 0x0
pixel_width:
.quad 0x0000000000000000
.size pixel_width, 8
.protected pixel_height
.type pixel_height,@object
.globl pixel_height
.p2align 3, 0x0
pixel_height:
.quad 0x0000000000000000
.size pixel_height, 8
.protected iteration_max
.type iteration_max,@object
.data
.globl iteration_max
.p2align 2, 0x0
iteration_max:
.long 200
.size iteration_max, 4
.protected image_size
.type image_size,@object
.section .bss,"aw",@nobits
.globl image_size
.p2align 2, 0x0
image_size:
.long 0
.size image_size, 4
.protected image_buffer_size
.type image_buffer_size,@object
.globl image_buffer_size
.p2align 2, 0x0
image_buffer_size:
.long 0
.size image_buffer_size, 4
.protected num_threads
.type num_threads,@object
.globl num_threads
.p2align 2, 0x0
num_threads:
.long 0
.size num_threads, 4
.protected th_per_block
.type th_per_block,@object
.globl th_per_block
.p2align 2, 0x0
th_per_block:
.long 0
.size th_per_block, 4
.protected pixels_per_thread
.type pixels_per_thread,@object
.globl pixels_per_thread
.p2align 2, 0x0
pixels_per_thread:
.long 0
.size pixels_per_thread, 4
.protected gradient_size
.type gradient_size,@object
.data
.globl gradient_size
.p2align 2, 0x0
gradient_size:
.long 16
.size gradient_size, 4
.protected colors
.type colors,@object
.globl colors
.p2align 4, 0x0
colors:
.long 66
.long 30
.long 15
.long 25
.long 7
.long 26
.long 9
.long 1
.long 47
.long 4
.long 4
.long 73
.long 0
.long 7
.long 100
.long 12
.long 44
.long 138
.long 24
.long 82
.long 177
.long 57
.long 125
.long 209
.long 134
.long 181
.long 229
.long 211
.long 236
.long 248
.long 241
.long 233
.long 191
.long 248
.long 201
.long 95
.long 255
.long 170
.long 0
.long 204
.long 128
.long 0
.long 153
.long 87
.long 0
.long 106
.long 52
.long 3
.long 16
.long 16
.long 16
.size colors, 204
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym c_x_min
.addrsig_sym c_x_max
.addrsig_sym c_y_min
.addrsig_sym c_y_max
.addrsig_sym pixel_width
.addrsig_sym pixel_height
.addrsig_sym iteration_max
.addrsig_sym image_size
.addrsig_sym image_buffer_size
.addrsig_sym num_threads
.addrsig_sym th_per_block
.addrsig_sym pixels_per_thread
.addrsig_sym gradient_size
.addrsig_sym colors
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18compute_mandelbrotPh
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18compute_mandelbrotPh.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000b2ca1_00000000-6_mandelbrot_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s"
.LC1:
.string " | Error: %s\n"
.text
.globl _Z5checkR9cudaErrorPKc
.type _Z5checkR9cudaErrorPKc, @function
_Z5checkR9cudaErrorPKc:
.LFB2057:
.cfi_startproc
endbr64
movl $0, %eax
cmpl $0, (%rdi)
jne .L10
ret
.L10:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq %rsi, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl (%rbx), %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z5checkR9cudaErrorPKc, .-_Z5checkR9cudaErrorPKc
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "usage: ./mandelbrot_seq c_x_min c_x_max c_y_min c_y_max image_size NUM_BLOCKS TH_PER_BLOCK \n"
.align 8
.LC3:
.string "examples with image_size = 11500:\n"
.align 8
.LC4:
.string " Full Picture: ./mandelbrot_cuda -2.5 1.5 -2.0 2.0 11500 4 64 \n"
.align 8
.LC5:
.string " Seahorse Valley: ./mandelbrot_cuda -0.8 -0.7 0.05 0.15 11500 4 64 \n"
.align 8
.LC6:
.string " Elephant Valley: ./mandelbrot_cuda 0.175 0.375 -0.1 0.1 11500 4 64 \n"
.align 8
.LC7:
.string " Triple Spiral Valley: ./mandelbrot_cuda -0.188 -0.012 0.554 0.754 11500 4 64 \n"
.text
.globl _Z19print_bad_argumentsv
.type _Z19print_bad_argumentsv, @function
_Z19print_bad_argumentsv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z19print_bad_argumentsv, .-_Z19print_bad_argumentsv
.section .rodata.str1.1
.LC8:
.string "%lf"
.LC9:
.string "%d"
.section .rodata.str1.8
.align 8
.LC10:
.string "Failed to copy command line args to device"
.text
.globl _Z4initiPPc
.type _Z4initiPPc, @function
_Z4initiPPc:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $7, %edi
jg .L14
call _Z19print_bad_argumentsv
movl $0, %edi
call exit@PLT
.L14:
movl %edi, %r12d
movq %rsi, %rbx
movl $1, th_per_block_y(%rip)
movl $1, num_blocks_y(%rip)
leaq 24(%rsp), %rdx
movq 8(%rsi), %rdi
leaq .LC8(%rip), %rbp
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
leaq 32(%rsp), %rdx
movq 16(%rbx), %rdi
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
leaq 40(%rsp), %rdx
movq 24(%rbx), %rdi
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
leaq 48(%rsp), %rdx
movq 32(%rbx), %rdi
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
leaq 4(%rsp), %rdx
movq 40(%rbx), %rdi
leaq .LC9(%rip), %rbp
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
movq 48(%rbx), %rdi
leaq num_blocks_x(%rip), %rdx
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
cmpl $8, %r12d
je .L21
cmpl $10, %r12d
je .L22
call _Z19print_bad_argumentsv
movl $0, %edi
call exit@PLT
.L21:
movq 56(%rbx), %rdi
leaq th_per_block_x(%rip), %rdx
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
jmp .L16
.L22:
movq 56(%rbx), %rdi
leaq num_blocks_y(%rip), %rdx
leaq .LC9(%rip), %rbp
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
movq 64(%rbx), %rdi
leaq th_per_block_x(%rip), %rdx
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
movq 72(%rbx), %rdi
leaq th_per_block_y(%rip), %rdx
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
.L16:
movl 4(%rsp), %esi
movl %esi, %eax
imull %esi, %eax
movl %eax, host_image_buffer_size(%rip)
movl th_per_block_x(%rip), %ecx
imull th_per_block_y(%rip), %ecx
movl %ecx, 8(%rsp)
imull num_blocks_x(%rip), %ecx
imull num_blocks_y(%rip), %ecx
movl %ecx, 12(%rsp)
cltd
idivl %ecx
movl %eax, 16(%rsp)
movl %esi, i_x_max(%rip)
movl %esi, i_y_max(%rip)
pxor %xmm1, %xmm1
cvtsi2sdl %esi, %xmm1
movsd 32(%rsp), %xmm0
subsd 24(%rsp), %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, 56(%rsp)
movsd 48(%rsp), %xmm0
subsd 40(%rsp), %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, 64(%rsp)
leaq 24(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $8, %edx
leaq _ZL7c_x_min(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 32(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $8, %edx
leaq _ZL7c_x_max(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 40(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $8, %edx
leaq _ZL7c_y_min(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 48(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $8, %edx
leaq _ZL7c_y_max(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 4(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL10image_size(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 12(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL11num_threads(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 8(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL12th_per_block(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 56(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $8, %edx
leaq _ZL11pixel_width(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 64(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $8, %edx
leaq _ZL12pixel_height(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 16(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL17pixels_per_thread(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq host_image_buffer_size(%rip), %rsi
leaq _ZL17image_buffer_size(%rip), %rdi
call cudaMemcpyToSymbol@PLT
call cudaGetLastError@PLT
movl %eax, 20(%rsp)
leaq 20(%rsp), %rdi
leaq .LC10(%rip), %rsi
call _Z5checkR9cudaErrorPKc
testl %eax, %eax
jne .L23
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $1, %edi
call exit@PLT
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z4initiPPc, .-_Z4initiPPc
.globl _Z17update_rgb_bufferPhii
.type _Z17update_rgb_bufferPhii, @function
_Z17update_rgb_bufferPhii:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z17update_rgb_bufferPhii, .-_Z17update_rgb_bufferPhii
.section .rodata.str1.8
.align 8
.LC11:
.string "Failed to allocate host vectors!\n"
.align 8
.LC12:
.string "Failed to allocate device image buffer"
.text
.globl _Z21allocate_image_bufferPPhm
.type _Z21allocate_image_bufferPPhm, @function
_Z21allocate_image_bufferPPhm:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsi, %rdi
call malloc@PLT
movq %rax, image_buffer_host(%rip)
movq %rbx, %rsi
movq %rbp, %rdi
call cudaMalloc@PLT
movl %eax, 4(%rsp)
cmpq $0, image_buffer_host(%rip)
je .L32
leaq 4(%rsp), %rdi
leaq .LC12(%rip), %rsi
call _Z5checkR9cudaErrorPKc
testl %eax, %eax
jne .L33
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
movl $1, %edi
call exit@PLT
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z21allocate_image_bufferPPhm, .-_Z21allocate_image_bufferPPhm
.section .rodata.str1.1
.LC13:
.string "wb"
.LC14:
.string "output.ppm"
.LC15:
.string "# "
.LC16:
.string "P6\n %s\n %d\n %d\n %d\n"
.text
.globl _Z13write_to_filev
.type _Z13write_to_filev, @function
_Z13write_to_filev:
.LFB2062:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
leaq .LC13(%rip), %rsi
leaq .LC14(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
subq $8, %rsp
.cfi_def_cfa_offset 40
pushq $255
.cfi_def_cfa_offset 48
movl i_y_max(%rip), %r9d
movl i_x_max(%rip), %r8d
leaq .LC15(%rip), %rcx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 32
cmpl $0, host_image_buffer_size(%rip)
jle .L36
movl $0, %ebx
.L37:
leaq (%rbx,%rbx,2), %rdi
addq image_buffer_host(%rip), %rdi
movq %rbp, %rcx
movl $3, %edx
movl $1, %esi
call fwrite@PLT
addq $1, %rbx
cmpl %ebx, host_image_buffer_size(%rip)
jg .L37
.L36:
movq %rbp, %rdi
call fclose@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z13write_to_filev, .-_Z13write_to_filev
.globl _Z38__device_stub__Z18compute_mandelbrotPhPh
.type _Z38__device_stub__Z18compute_mandelbrotPhPh, @function
_Z38__device_stub__Z18compute_mandelbrotPhPh:
.LFB2088:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L44
.L40:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L45
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18compute_mandelbrotPh(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L40
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z38__device_stub__Z18compute_mandelbrotPhPh, .-_Z38__device_stub__Z18compute_mandelbrotPhPh
.globl _Z18compute_mandelbrotPh
.type _Z18compute_mandelbrotPh, @function
_Z18compute_mandelbrotPh:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z18compute_mandelbrotPhPh
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z18compute_mandelbrotPh, .-_Z18compute_mandelbrotPh
.section .rodata.str1.8
.align 8
.LC17:
.string "Failed to launch compute_mandelbrot kernel"
.align 8
.LC18:
.string "Failed to copy vector from device to host"
.section .rodata.str1.1
.LC19:
.string "Failed to free device vector"
.text
.globl main
.type main, @function
main:
.LFB2063:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
call _Z4initiPPc
movl host_image_buffer_size(%rip), %eax
leal (%rax,%rax,2), %ebx
movslq %ebx, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call _Z21allocate_image_bufferPPhm
movl num_blocks_x(%rip), %eax
movl %eax, num_blocks(%rip)
movl num_blocks_y(%rip), %eax
movl %eax, 4+num_blocks(%rip)
movl $1, 8+num_blocks(%rip)
movl th_per_block_x(%rip), %eax
movl %eax, threads_per_block(%rip)
movl th_per_block_y(%rip), %eax
movl %eax, 4+threads_per_block(%rip)
movl $1, 8+threads_per_block(%rip)
movl $0, %r9d
movl $0, %r8d
movq threads_per_block(%rip), %rdx
movl $1, %ecx
movq num_blocks(%rip), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L49:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
movl %eax, 12(%rsp)
leaq 12(%rsp), %rdi
leaq .LC17(%rip), %rsi
call _Z5checkR9cudaErrorPKc
testl %eax, %eax
jne .L56
movl $2, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq image_buffer_host(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, 12(%rsp)
leaq 12(%rsp), %rdi
leaq .LC18(%rip), %rsi
call _Z5checkR9cudaErrorPKc
testl %eax, %eax
jne .L57
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, 12(%rsp)
leaq 12(%rsp), %rdi
leaq .LC19(%rip), %rsi
call _Z5checkR9cudaErrorPKc
testl %eax, %eax
jne .L58
call _Z13write_to_filev
movq image_buffer_host(%rip), %rdi
call free@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L59
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
movq 16(%rsp), %rdi
call _Z38__device_stub__Z18compute_mandelbrotPhPh
jmp .L49
.L56:
movl $1, %edi
call exit@PLT
.L57:
movl $1, %edi
call exit@PLT
.L58:
movl $1, %edi
call exit@PLT
.L59:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size main, .-main
.section .rodata.str1.1
.LC20:
.string "_Z18compute_mandelbrotPh"
.LC21:
.string "c_x_min"
.LC22:
.string "c_x_max"
.LC23:
.string "c_y_min"
.LC24:
.string "c_y_max"
.LC25:
.string "pixel_width"
.LC26:
.string "pixel_height"
.LC27:
.string "iteration_max"
.LC28:
.string "image_size"
.LC29:
.string "image_buffer_size"
.LC30:
.string "num_threads"
.LC31:
.string "th_per_block"
.LC32:
.string "pixels_per_thread"
.LC33:
.string "gradient_size"
.LC34:
.string "colors"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z18compute_mandelbrotPh(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7c_x_min(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7c_x_max(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC23(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7c_y_min(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC24(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7c_y_max(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC25(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11pixel_width(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC26(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12pixel_height(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC27(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13iteration_max(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC28(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10image_size(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC29(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17image_buffer_size(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC30(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11num_threads(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC31(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12th_per_block(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC32(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17pixels_per_thread(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC33(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13gradient_size(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $204, %r9d
movl $0, %r8d
leaq .LC34(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6colors(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl i_y_max
.bss
.align 4
.type i_y_max, @object
.size i_y_max, 4
i_y_max:
.zero 4
.globl i_x_max
.align 4
.type i_x_max, @object
.size i_x_max, 4
i_x_max:
.zero 4
.globl image_buffer_host
.align 8
.type image_buffer_host, @object
.size image_buffer_host, 8
image_buffer_host:
.zero 8
.globl host_image_buffer_size
.align 4
.type host_image_buffer_size, @object
.size host_image_buffer_size, 4
host_image_buffer_size:
.zero 4
.globl th_per_block_y
.align 4
.type th_per_block_y, @object
.size th_per_block_y, 4
th_per_block_y:
.zero 4
.globl num_blocks_y
.align 4
.type num_blocks_y, @object
.size num_blocks_y, 4
num_blocks_y:
.zero 4
.globl th_per_block_x
.align 4
.type th_per_block_x, @object
.size th_per_block_x, 4
th_per_block_x:
.zero 4
.globl num_blocks_x
.align 4
.type num_blocks_x, @object
.size num_blocks_x, 4
num_blocks_x:
.zero 4
.globl threads_per_block
.data
.align 8
.type threads_per_block, @object
.size threads_per_block, 12
threads_per_block:
.long 1
.long 1
.long 1
.globl num_blocks
.align 8
.type num_blocks, @object
.size num_blocks, 12
num_blocks:
.long 1
.long 1
.long 1
.local _ZL6colors
.comm _ZL6colors,204,32
.local _ZL13gradient_size
.comm _ZL13gradient_size,4,4
.local _ZL17pixels_per_thread
.comm _ZL17pixels_per_thread,4,4
.local _ZL12th_per_block
.comm _ZL12th_per_block,4,4
.local _ZL11num_threads
.comm _ZL11num_threads,4,4
.local _ZL17image_buffer_size
.comm _ZL17image_buffer_size,4,4
.local _ZL10image_size
.comm _ZL10image_size,4,4
.local _ZL13iteration_max
.comm _ZL13iteration_max,4,4
.local _ZL12pixel_height
.comm _ZL12pixel_height,8,8
.local _ZL11pixel_width
.comm _ZL11pixel_width,8,8
.local _ZL7c_y_max
.comm _ZL7c_y_max,8,8
.local _ZL7c_y_min
.comm _ZL7c_y_min,8,8
.local _ZL7c_x_max
.comm _ZL7c_x_max,8,8
.local _ZL7c_x_min
.comm _ZL7c_x_min,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "mandelbrot_cuda.hip"
.globl _Z5checkR10hipError_tPKc # -- Begin function _Z5checkR10hipError_tPKc
.p2align 4, 0x90
.type _Z5checkR10hipError_tPKc,@function
_Z5checkR10hipError_tPKc: # @_Z5checkR10hipError_tPKc
.cfi_startproc
# %bb.0:
cmpl $0, (%rdi)
je .LBB0_1
# %bb.2:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl (%rbx), %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %eax
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
retq
.LBB0_1:
xorl %eax, %eax
retq
.Lfunc_end0:
.size _Z5checkR10hipError_tPKc, .Lfunc_end0-_Z5checkR10hipError_tPKc
.cfi_endproc
# -- End function
.globl _Z19print_bad_argumentsv # -- Begin function _Z19print_bad_argumentsv
.p2align 4, 0x90
.type _Z19print_bad_argumentsv,@function
_Z19print_bad_argumentsv: # @_Z19print_bad_argumentsv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
movl $.Lstr.4, %edi
callq puts@PLT
movl $.Lstr.5, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end1:
.size _Z19print_bad_argumentsv, .Lfunc_end1-_Z19print_bad_argumentsv
.cfi_endproc
# -- End function
.globl _Z4initiPPc # -- Begin function _Z4initiPPc
.p2align 4, 0x90
.type _Z4initiPPc,@function
_Z4initiPPc: # @_Z4initiPPc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $72, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
cmpl $7, %edi
jle .LBB2_7
# %bb.1:
movq %rsi, %rbx
movl %edi, %ebp
movl $1, th_per_block_y(%rip)
movl $1, num_blocks_y(%rip)
movq 8(%rsi), %rdi
leaq 48(%rsp), %rdx
movl $.L.str.8, %esi
xorl %eax, %eax
callq __isoc23_sscanf
movq 16(%rbx), %rdi
leaq 40(%rsp), %rdx
movl $.L.str.8, %esi
xorl %eax, %eax
callq __isoc23_sscanf
movq 24(%rbx), %rdi
leaq 32(%rsp), %rdx
movl $.L.str.8, %esi
xorl %eax, %eax
callq __isoc23_sscanf
movq 32(%rbx), %rdi
leaq 24(%rsp), %rdx
movl $.L.str.8, %esi
xorl %eax, %eax
callq __isoc23_sscanf
movq 40(%rbx), %rdi
leaq 8(%rsp), %rdx
movl $.L.str.9, %esi
xorl %eax, %eax
callq __isoc23_sscanf
movq 48(%rbx), %rdi
movl $.L.str.9, %esi
movl $num_blocks_x, %edx
xorl %eax, %eax
callq __isoc23_sscanf
cmpl $8, %ebp
je .LBB2_2
# %bb.3:
cmpl $10, %ebp
jne .LBB2_7
# %bb.4:
movq 56(%rbx), %rdi
movl $.L.str.9, %esi
movl $num_blocks_y, %edx
xorl %eax, %eax
callq __isoc23_sscanf
movq 64(%rbx), %rdi
movl $.L.str.9, %esi
movl $th_per_block_x, %edx
xorl %eax, %eax
callq __isoc23_sscanf
movl $th_per_block_y, %edx
movl $9, %eax
jmp .LBB2_5
.LBB2_2:
movl $th_per_block_x, %edx
movl $7, %eax
.LBB2_5:
movq (%rbx,%rax,8), %rdi
movl $.L.str.9, %esi
xorl %eax, %eax
callq __isoc23_sscanf
movl 8(%rsp), %ecx
movl %ecx, %eax
imull %ecx, %eax
movl %eax, host_image_buffer_size(%rip)
movl th_per_block_y(%rip), %esi
imull th_per_block_x(%rip), %esi
movl %esi, 20(%rsp)
imull num_blocks_x(%rip), %esi
imull num_blocks_y(%rip), %esi
movl %esi, 16(%rsp)
xorl %edx, %edx
idivl %esi
movl %eax, 12(%rsp)
movl %ecx, i_x_max(%rip)
movsd 40(%rsp), %xmm0 # xmm0 = mem[0],zero
subsd 48(%rsp), %xmm0
cvtsi2sd %ecx, %xmm1
movl %ecx, i_y_max(%rip)
divsd %xmm1, %xmm0
movsd %xmm0, 64(%rsp)
movsd 24(%rsp), %xmm0 # xmm0 = mem[0],zero
subsd 32(%rsp), %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, 56(%rsp)
leaq 48(%rsp), %rsi
movl $c_x_min, %edi
movl $8, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 40(%rsp), %rsi
movl $c_x_max, %edi
movl $8, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 32(%rsp), %rsi
movl $c_y_min, %edi
movl $8, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 24(%rsp), %rsi
movl $c_y_max, %edi
movl $8, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 8(%rsp), %rsi
movl $image_size, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 16(%rsp), %rsi
movl $num_threads, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 20(%rsp), %rsi
movl $th_per_block, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 64(%rsp), %rsi
movl $pixel_width, %edi
movl $8, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 56(%rsp), %rsi
movl $pixel_height, %edi
movl $8, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 12(%rsp), %rsi
movl $pixels_per_thread, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movl $image_buffer_size, %edi
movl $host_image_buffer_size, %esi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
callq hipGetLastError
testl %eax, %eax
jne .LBB2_8
# %bb.6: # %.critedge
addq $72, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_7:
.cfi_def_cfa_offset 96
callq _Z19print_bad_argumentsv
xorl %edi, %edi
callq exit
.LBB2_8: # %_Z5checkR10hipError_tPKc.exit
movl $.L.str, %edi
movl $.L.str.10, %esi
movl %eax, %ebx
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z4initiPPc, .Lfunc_end2-_Z4initiPPc
.cfi_endproc
# -- End function
.globl _Z33__device_stub__compute_mandelbrotPh # -- Begin function _Z33__device_stub__compute_mandelbrotPh
.p2align 4, 0x90
.type _Z33__device_stub__compute_mandelbrotPh,@function
_Z33__device_stub__compute_mandelbrotPh: # @_Z33__device_stub__compute_mandelbrotPh
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z18compute_mandelbrotPh, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z33__device_stub__compute_mandelbrotPh, .Lfunc_end3-_Z33__device_stub__compute_mandelbrotPh
.cfi_endproc
# -- End function
.globl _Z21allocate_image_bufferPPhm # -- Begin function _Z21allocate_image_bufferPPhm
.p2align 4, 0x90
.type _Z21allocate_image_bufferPPhm,@function
_Z21allocate_image_bufferPPhm: # @_Z21allocate_image_bufferPPhm
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
movq %rsi, %rdi
callq malloc
movq %rax, image_buffer_host(%rip)
movq %r14, %rdi
movq %rbx, %rsi
callq hipMalloc
cmpq $0, image_buffer_host(%rip)
je .LBB4_3
# %bb.1:
testl %eax, %eax
jne .LBB4_4
# %bb.2: # %.critedge
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB4_3:
.cfi_def_cfa_offset 32
movq stderr(%rip), %rcx
movl $.L.str.11, %edi
movl $33, %esi
movl $1, %edx
callq fwrite
movl $1, %edi
callq exit
.LBB4_4: # %_Z5checkR10hipError_tPKc.exit
movl $.L.str, %edi
movl $.L.str.12, %esi
movl %eax, %ebx
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end4:
.size _Z21allocate_image_bufferPPhm, .Lfunc_end4-_Z21allocate_image_bufferPPhm
.cfi_endproc
# -- End function
.globl _Z13write_to_filev # -- Begin function _Z13write_to_filev
.p2align 4, 0x90
.type _Z13write_to_filev,@function
_Z13write_to_filev: # @_Z13write_to_filev
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.L.str.13, %edi
movl $.L.str.15, %esi
callq fopen
movq %rax, %rbx
movl i_x_max(%rip), %ecx
movl i_y_max(%rip), %r8d
movl $.L.str.16, %esi
movl $.L.str.14, %edx
movq %rax, %rdi
movl $255, %r9d
xorl %eax, %eax
callq fprintf
cmpl $0, host_image_buffer_size(%rip)
jle .LBB5_3
# %bb.1: # %.lr.ph.preheader
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq image_buffer_host(%rip), %rdi
addq %r14, %rdi
movl $1, %esi
movl $3, %edx
movq %rbx, %rcx
callq fwrite
incq %r15
movslq host_image_buffer_size(%rip), %rax
addq $3, %r14
cmpq %rax, %r15
jl .LBB5_2
.LBB5_3: # %._crit_edge
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end5:
.size _Z13write_to_filev, .Lfunc_end5-_Z13write_to_filev
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $80, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
callq _Z4initiPPc
movslq host_image_buffer_size(%rip), %rax
leaq (%rax,%rax,2), %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq _Z21allocate_image_bufferPPhm
movl num_blocks_x(%rip), %eax
movl num_blocks_y(%rip), %ecx
movl %eax, num_blocks(%rip)
movl %ecx, num_blocks+4(%rip)
movl $1, num_blocks+8(%rip)
movl th_per_block_x(%rip), %eax
movl th_per_block_y(%rip), %ecx
movl %eax, threads_per_block(%rip)
movl %ecx, threads_per_block+4(%rip)
movl $1, threads_per_block+8(%rip)
movq num_blocks(%rip), %rdi
movq threads_per_block(%rip), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z18compute_mandelbrotPh, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_2:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB6_3
# %bb.5: # %.critedge
movq image_buffer_host(%rip), %rdi
movq 8(%rsp), %rsi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB6_6
# %bb.7: # %.critedge27
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB6_8
# %bb.9: # %.critedge28
movl $.L.str.13, %edi
movl $.L.str.15, %esi
callq fopen
movq %rax, %rbx
movl i_x_max(%rip), %ecx
movl i_y_max(%rip), %r8d
movl $.L.str.16, %esi
movl $.L.str.14, %edx
movq %rax, %rdi
movl $255, %r9d
xorl %eax, %eax
callq fprintf
cmpl $0, host_image_buffer_size(%rip)
jle .LBB6_12
# %bb.10: # %.lr.ph.i.preheader
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB6_11: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq image_buffer_host(%rip), %rdi
addq %r14, %rdi
movl $1, %esi
movl $3, %edx
movq %rbx, %rcx
callq fwrite
incq %r15
movslq host_image_buffer_size(%rip), %rax
addq $3, %r14
cmpq %rax, %r15
jl .LBB6_11
.LBB6_12: # %_Z13write_to_filev.exit
movq %rbx, %rdi
callq fclose
movq image_buffer_host(%rip), %rdi
callq free
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB6_3: # %_Z5checkR10hipError_tPKc.exit
.cfi_def_cfa_offset 112
movl $.L.str, %edi
movl $.L.str.17, %esi
jmp .LBB6_4
.LBB6_6: # %_Z5checkR10hipError_tPKc.exit15
movl $.L.str, %edi
movl $.L.str.18, %esi
jmp .LBB6_4
.LBB6_8: # %_Z5checkR10hipError_tPKc.exit18
movl $.L.str, %edi
movl $.L.str.19, %esi
.LBB6_4: # %_Z5checkR10hipError_tPKc.exit
movl %eax, %ebx
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18compute_mandelbrotPh, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $c_x_min, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $c_x_max, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $c_y_min, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $c_y_max, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $pixel_width, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $pixel_height, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $iteration_max, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $image_size, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $image_buffer_size, %esi
movl $.L__unnamed_10, %edx
movl $.L__unnamed_10, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $num_threads, %esi
movl $.L__unnamed_11, %edx
movl $.L__unnamed_11, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $th_per_block, %esi
movl $.L__unnamed_12, %edx
movl $.L__unnamed_12, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $pixels_per_thread, %esi
movl $.L__unnamed_13, %edx
movl $.L__unnamed_13, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $gradient_size, %esi
movl $.L__unnamed_14, %edx
movl $.L__unnamed_14, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $colors, %esi
movl $.L__unnamed_15, %edx
movl $.L__unnamed_15, %ecx
movl $204, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type c_x_min,@object # @c_x_min
.local c_x_min
.comm c_x_min,8,8
.type c_x_max,@object # @c_x_max
.local c_x_max
.comm c_x_max,8,8
.type c_y_min,@object # @c_y_min
.local c_y_min
.comm c_y_min,8,8
.type c_y_max,@object # @c_y_max
.local c_y_max
.comm c_y_max,8,8
.type pixel_width,@object # @pixel_width
.local pixel_width
.comm pixel_width,8,8
.type pixel_height,@object # @pixel_height
.local pixel_height
.comm pixel_height,8,8
.type iteration_max,@object # @iteration_max
.local iteration_max
.comm iteration_max,4,4
.type image_size,@object # @image_size
.local image_size
.comm image_size,4,4
.type image_buffer_size,@object # @image_buffer_size
.local image_buffer_size
.comm image_buffer_size,4,4
.type num_threads,@object # @num_threads
.local num_threads
.comm num_threads,4,4
.type th_per_block,@object # @th_per_block
.local th_per_block
.comm th_per_block,4,4
.type pixels_per_thread,@object # @pixels_per_thread
.local pixels_per_thread
.comm pixels_per_thread,4,4
.type gradient_size,@object # @gradient_size
.local gradient_size
.comm gradient_size,4,4
.type colors,@object # @colors
.local colors
.comm colors,204,16
.type num_blocks,@object # @num_blocks
.data
.globl num_blocks
.p2align 3, 0x0
num_blocks:
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.size num_blocks, 12
.type threads_per_block,@object # @threads_per_block
.globl threads_per_block
.p2align 3, 0x0
threads_per_block:
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.size threads_per_block, 12
.type num_blocks_x,@object # @num_blocks_x
.bss
.globl num_blocks_x
.p2align 2, 0x0
num_blocks_x:
.long 0 # 0x0
.size num_blocks_x, 4
.type th_per_block_x,@object # @th_per_block_x
.globl th_per_block_x
.p2align 2, 0x0
th_per_block_x:
.long 0 # 0x0
.size th_per_block_x, 4
.type num_blocks_y,@object # @num_blocks_y
.globl num_blocks_y
.p2align 2, 0x0
num_blocks_y:
.long 0 # 0x0
.size num_blocks_y, 4
.type th_per_block_y,@object # @th_per_block_y
.globl th_per_block_y
.p2align 2, 0x0
th_per_block_y:
.long 0 # 0x0
.size th_per_block_y, 4
.type host_image_buffer_size,@object # @host_image_buffer_size
.globl host_image_buffer_size
.p2align 2, 0x0
host_image_buffer_size:
.long 0 # 0x0
.size host_image_buffer_size, 4
.type image_buffer_host,@object # @image_buffer_host
.globl image_buffer_host
.p2align 3, 0x0
image_buffer_host:
.quad 0
.size image_buffer_host, 8
.type i_x_max,@object # @i_x_max
.globl i_x_max
.p2align 2, 0x0
i_x_max:
.long 0 # 0x0
.size i_x_max, 4
.type i_y_max,@object # @i_y_max
.globl i_y_max
.p2align 2, 0x0
i_y_max:
.long 0 # 0x0
.size i_y_max, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " | Error: %s\n"
.size .L.str.1, 14
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%lf"
.size .L.str.8, 4
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d"
.size .L.str.9, 3
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Failed to copy command line args to device"
.size .L.str.10, 43
.type _Z18compute_mandelbrotPh,@object # @_Z18compute_mandelbrotPh
.section .rodata,"a",@progbits
.globl _Z18compute_mandelbrotPh
.p2align 3, 0x0
_Z18compute_mandelbrotPh:
.quad _Z33__device_stub__compute_mandelbrotPh
.size _Z18compute_mandelbrotPh, 8
.type .L.str.11,@object # @.str.11
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.11:
.asciz "Failed to allocate host vectors!\n"
.size .L.str.11, 34
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Failed to allocate device image buffer"
.size .L.str.12, 39
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "output.ppm"
.size .L.str.13, 11
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "# "
.size .L.str.14, 3
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "wb"
.size .L.str.15, 3
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "P6\n %s\n %d\n %d\n %d\n"
.size .L.str.16, 20
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Failed to launch compute_mandelbrot kernel"
.size .L.str.17, 43
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "Failed to copy vector from device to host"
.size .L.str.18, 42
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "Failed to free device vector"
.size .L.str.19, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18compute_mandelbrotPh"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "c_x_min"
.size .L__unnamed_2, 8
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "c_x_max"
.size .L__unnamed_3, 8
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "c_y_min"
.size .L__unnamed_4, 8
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "c_y_max"
.size .L__unnamed_5, 8
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "pixel_width"
.size .L__unnamed_6, 12
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "pixel_height"
.size .L__unnamed_7, 13
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "iteration_max"
.size .L__unnamed_8, 14
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "image_size"
.size .L__unnamed_9, 11
.type .L__unnamed_10,@object # @9
.L__unnamed_10:
.asciz "image_buffer_size"
.size .L__unnamed_10, 18
.type .L__unnamed_11,@object # @10
.L__unnamed_11:
.asciz "num_threads"
.size .L__unnamed_11, 12
.type .L__unnamed_12,@object # @11
.L__unnamed_12:
.asciz "th_per_block"
.size .L__unnamed_12, 13
.type .L__unnamed_13,@object # @12
.L__unnamed_13:
.asciz "pixels_per_thread"
.size .L__unnamed_13, 18
.type .L__unnamed_14,@object # @13
.L__unnamed_14:
.asciz "gradient_size"
.size .L__unnamed_14, 14
.type .L__unnamed_15,@object # @14
.L__unnamed_15:
.asciz "colors"
.size .L__unnamed_15, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "usage: ./mandelbrot_seq c_x_min c_x_max c_y_min c_y_max image_size NUM_BLOCKS TH_PER_BLOCK "
.size .Lstr, 92
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "examples with image_size = 11500:"
.size .Lstr.1, 34
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz " Full Picture: ./mandelbrot_cuda -2.5 1.5 -2.0 2.0 11500 4 64 "
.size .Lstr.2, 74
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz " Seahorse Valley: ./mandelbrot_cuda -0.8 -0.7 0.05 0.15 11500 4 64 "
.size .Lstr.3, 76
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz " Elephant Valley: ./mandelbrot_cuda 0.175 0.375 -0.1 0.1 11500 4 64 "
.size .Lstr.4, 77
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz " Triple Spiral Valley: ./mandelbrot_cuda -0.188 -0.012 0.554 0.754 11500 4 64 "
.size .Lstr.5, 82
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__compute_mandelbrotPh
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym c_x_min
.addrsig_sym c_x_max
.addrsig_sym c_y_min
.addrsig_sym c_y_max
.addrsig_sym pixel_width
.addrsig_sym pixel_height
.addrsig_sym iteration_max
.addrsig_sym image_size
.addrsig_sym image_buffer_size
.addrsig_sym num_threads
.addrsig_sym th_per_block
.addrsig_sym pixels_per_thread
.addrsig_sym gradient_size
.addrsig_sym colors
.addrsig_sym num_blocks_x
.addrsig_sym th_per_block_x
.addrsig_sym num_blocks_y
.addrsig_sym th_per_block_y
.addrsig_sym host_image_buffer_size
.addrsig_sym _Z18compute_mandelbrotPh
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void PolynomialFunctionKernel(float a3, float a2, float a1, float a0, float* input, float* output, int size)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
if(id < size)
{
float x = input[id];
output[id] = a3 * x * x * x + a2 * x * x + a1 * x + a0;
}
}
|
code for sm_80
Function : _Z24PolynomialFunctionKernelffffPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0207 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FMUL R5, R2.reuse, c[0x0][0x160] ; /* 0x0000580002057a20 */
/* 0x044fe40000400000 */
/*00d0*/ FMUL R4, R2.reuse, c[0x0][0x164] ; /* 0x0000590002047a20 */
/* 0x040fe40000400000 */
/*00e0*/ FMUL R5, R2, R5 ; /* 0x0000000502057220 */
/* 0x000fc80000400000 */
/*00f0*/ FMUL R5, R2, R5 ; /* 0x0000000502057220 */
/* 0x000fc80000400000 */
/*0100*/ FFMA R5, R2, R4, R5 ; /* 0x0000000402057223 */
/* 0x000fc80000000005 */
/*0110*/ FFMA R6, R2, c[0x0][0x168], R5 ; /* 0x00005a0002067a23 */
/* 0x000fe40000000005 */
/*0120*/ IMAD.WIDE R4, R0, R7, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fc800078e0207 */
/*0130*/ FADD R7, R6, c[0x0][0x16c] ; /* 0x00005b0006077621 */
/* 0x000fca0000000000 */
/*0140*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void PolynomialFunctionKernel(float a3, float a2, float a1, float a0, float* input, float* output, int size)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
if(id < size)
{
float x = input[id];
output[id] = a3 * x * x * x + a2 * x * x + a1 * x + a0;
}
}
|
.file "tmpxft_000720c9_00000000-6_PolynomialFunctionKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z24PolynomialFunctionKernelffffPfS_iffffPfS_i
.type _Z51__device_stub__Z24PolynomialFunctionKernelffffPfS_iffffPfS_i, @function
_Z51__device_stub__Z24PolynomialFunctionKernelffffPfS_iffffPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movss %xmm0, 44(%rsp)
movss %xmm1, 40(%rsp)
movss %xmm2, 36(%rsp)
movss %xmm3, 32(%rsp)
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z24PolynomialFunctionKernelffffPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z24PolynomialFunctionKernelffffPfS_iffffPfS_i, .-_Z51__device_stub__Z24PolynomialFunctionKernelffffPfS_iffffPfS_i
.globl _Z24PolynomialFunctionKernelffffPfS_i
.type _Z24PolynomialFunctionKernelffffPfS_i, @function
_Z24PolynomialFunctionKernelffffPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z24PolynomialFunctionKernelffffPfS_iffffPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24PolynomialFunctionKernelffffPfS_i, .-_Z24PolynomialFunctionKernelffffPfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24PolynomialFunctionKernelffffPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24PolynomialFunctionKernelffffPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void PolynomialFunctionKernel(float a3, float a2, float a1, float a0, float* input, float* output, int size)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
if(id < size)
{
float x = input[id];
output[id] = a3 * x * x * x + a2 * x * x + a1 * x + a0;
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void PolynomialFunctionKernel(float a3, float a2, float a1, float a0, float* input, float* output, int size)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
if(id < size)
{
float x = input[id];
output[id] = a3 * x * x * x + a2 * x * x + a1 * x + a0;
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void PolynomialFunctionKernel(float a3, float a2, float a1, float a0, float* input, float* output, int size)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
if(id < size)
{
float x = input[id];
output[id] = a3 * x * x * x + a2 * x * x + a1 * x + a0;
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24PolynomialFunctionKernelffffPfS_i
.globl _Z24PolynomialFunctionKernelffffPfS_i
.p2align 8
.type _Z24PolynomialFunctionKernelffffPfS_i,@function
_Z24PolynomialFunctionKernelffffPfS_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x28
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, s2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v4, s3, v2 :: v_dual_mul_f32 v3, v2, v3
v_mul_f32_e32 v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v2, v4
v_fmac_f32_e32 v3, s4, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v2, s5, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24PolynomialFunctionKernelffffPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24PolynomialFunctionKernelffffPfS_i, .Lfunc_end0-_Z24PolynomialFunctionKernelffffPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24PolynomialFunctionKernelffffPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24PolynomialFunctionKernelffffPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void PolynomialFunctionKernel(float a3, float a2, float a1, float a0, float* input, float* output, int size)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
if(id < size)
{
float x = input[id];
output[id] = a3 * x * x * x + a2 * x * x + a1 * x + a0;
}
}
|
.text
.file "PolynomialFunctionKernel.hip"
.globl _Z39__device_stub__PolynomialFunctionKernelffffPfS_i # -- Begin function _Z39__device_stub__PolynomialFunctionKernelffffPfS_i
.p2align 4, 0x90
.type _Z39__device_stub__PolynomialFunctionKernelffffPfS_i,@function
_Z39__device_stub__PolynomialFunctionKernelffffPfS_i: # @_Z39__device_stub__PolynomialFunctionKernelffffPfS_i
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 12(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24PolynomialFunctionKernelffffPfS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z39__device_stub__PolynomialFunctionKernelffffPfS_i, .Lfunc_end0-_Z39__device_stub__PolynomialFunctionKernelffffPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24PolynomialFunctionKernelffffPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24PolynomialFunctionKernelffffPfS_i,@object # @_Z24PolynomialFunctionKernelffffPfS_i
.section .rodata,"a",@progbits
.globl _Z24PolynomialFunctionKernelffffPfS_i
.p2align 3, 0x0
_Z24PolynomialFunctionKernelffffPfS_i:
.quad _Z39__device_stub__PolynomialFunctionKernelffffPfS_i
.size _Z24PolynomialFunctionKernelffffPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24PolynomialFunctionKernelffffPfS_i"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__PolynomialFunctionKernelffffPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24PolynomialFunctionKernelffffPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z24PolynomialFunctionKernelffffPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0207 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FMUL R5, R2.reuse, c[0x0][0x160] ; /* 0x0000580002057a20 */
/* 0x044fe40000400000 */
/*00d0*/ FMUL R4, R2.reuse, c[0x0][0x164] ; /* 0x0000590002047a20 */
/* 0x040fe40000400000 */
/*00e0*/ FMUL R5, R2, R5 ; /* 0x0000000502057220 */
/* 0x000fc80000400000 */
/*00f0*/ FMUL R5, R2, R5 ; /* 0x0000000502057220 */
/* 0x000fc80000400000 */
/*0100*/ FFMA R5, R2, R4, R5 ; /* 0x0000000402057223 */
/* 0x000fc80000000005 */
/*0110*/ FFMA R6, R2, c[0x0][0x168], R5 ; /* 0x00005a0002067a23 */
/* 0x000fe40000000005 */
/*0120*/ IMAD.WIDE R4, R0, R7, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fc800078e0207 */
/*0130*/ FADD R7, R6, c[0x0][0x16c] ; /* 0x00005b0006077621 */
/* 0x000fca0000000000 */
/*0140*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24PolynomialFunctionKernelffffPfS_i
.globl _Z24PolynomialFunctionKernelffffPfS_i
.p2align 8
.type _Z24PolynomialFunctionKernelffffPfS_i,@function
_Z24PolynomialFunctionKernelffffPfS_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x28
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, s2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v4, s3, v2 :: v_dual_mul_f32 v3, v2, v3
v_mul_f32_e32 v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v2, v4
v_fmac_f32_e32 v3, s4, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v2, s5, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24PolynomialFunctionKernelffffPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24PolynomialFunctionKernelffffPfS_i, .Lfunc_end0-_Z24PolynomialFunctionKernelffffPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24PolynomialFunctionKernelffffPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24PolynomialFunctionKernelffffPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000720c9_00000000-6_PolynomialFunctionKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z24PolynomialFunctionKernelffffPfS_iffffPfS_i
.type _Z51__device_stub__Z24PolynomialFunctionKernelffffPfS_iffffPfS_i, @function
_Z51__device_stub__Z24PolynomialFunctionKernelffffPfS_iffffPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movss %xmm0, 44(%rsp)
movss %xmm1, 40(%rsp)
movss %xmm2, 36(%rsp)
movss %xmm3, 32(%rsp)
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z24PolynomialFunctionKernelffffPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z24PolynomialFunctionKernelffffPfS_iffffPfS_i, .-_Z51__device_stub__Z24PolynomialFunctionKernelffffPfS_iffffPfS_i
.globl _Z24PolynomialFunctionKernelffffPfS_i
.type _Z24PolynomialFunctionKernelffffPfS_i, @function
_Z24PolynomialFunctionKernelffffPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z24PolynomialFunctionKernelffffPfS_iffffPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24PolynomialFunctionKernelffffPfS_i, .-_Z24PolynomialFunctionKernelffffPfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24PolynomialFunctionKernelffffPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24PolynomialFunctionKernelffffPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "PolynomialFunctionKernel.hip"
.globl _Z39__device_stub__PolynomialFunctionKernelffffPfS_i # -- Begin function _Z39__device_stub__PolynomialFunctionKernelffffPfS_i
.p2align 4, 0x90
.type _Z39__device_stub__PolynomialFunctionKernelffffPfS_i,@function
_Z39__device_stub__PolynomialFunctionKernelffffPfS_i: # @_Z39__device_stub__PolynomialFunctionKernelffffPfS_i
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 12(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24PolynomialFunctionKernelffffPfS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z39__device_stub__PolynomialFunctionKernelffffPfS_i, .Lfunc_end0-_Z39__device_stub__PolynomialFunctionKernelffffPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24PolynomialFunctionKernelffffPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24PolynomialFunctionKernelffffPfS_i,@object # @_Z24PolynomialFunctionKernelffffPfS_i
.section .rodata,"a",@progbits
.globl _Z24PolynomialFunctionKernelffffPfS_i
.p2align 3, 0x0
_Z24PolynomialFunctionKernelffffPfS_i:
.quad _Z39__device_stub__PolynomialFunctionKernelffffPfS_i
.size _Z24PolynomialFunctionKernelffffPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24PolynomialFunctionKernelffffPfS_i"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__PolynomialFunctionKernelffffPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24PolynomialFunctionKernelffffPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
// g++ -DTHRUST_DEVICE_SYSTEM=THRUST_DEVICE_SYSTEM_OMP -I../../../thrust/ -fopenmp -x c++ exemplo1.cu -o exemplo1 && ./exemplo1 < ../17-intro-gpu/stocks2.csv
// nvcc -arch=sm_70 -std=c++14 exemplo1.cu -o exemplo1 && ./exemplo1 < ../17-intro-gpu/stocks2.csv
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <iostream>
#include <math.h>
struct calcular_var
{
// essas marcações indicam que o código deve ser compilado para CPU (host)
// e GPU (device)
// IMPORTANTE: somente código com a marcação __device__ é compilado para GPU
double mean;
int N;
calcular_var(double a, int n): mean(a), N(n) {};
__device__
double operator()(const double& x) {
return ((x - mean) * (x - mean))/N;
}
};
int main()
{
int N = 0;
thrust::host_vector<double> hostMicrosoft;
thrust::host_vector<double> hostApple;
double a, m;
while (std::cin.fail() == false)
{
N += 1;
std::cin >> a;
std::cin >> m;
hostMicrosoft.push_back(m);
hostApple.push_back(a);
}
thrust::device_vector<double> diferenca(N);
thrust::device_vector<double> MSFT(hostMicrosoft);
thrust::device_vector<double> AAPL(hostApple);
thrust::device_vector<double> mean_vector(N);
thrust::device_vector<double> var(N);
thrust::device_vector<double> var_double(N);
// diference
thrust::transform(MSFT.begin(), MSFT.end(), AAPL.begin(), diferenca.begin(), thrust::minus<double>());
// mean
double mean = thrust::reduce(diferenca.begin(), diferenca.end(), 0.0, thrust::plus<double>()) / N;
// thrust::fill(mean_vector.begin(), mean_vector.end(), mean);
thrust::transform(diferenca.begin(), diferenca.end(), var.begin(), calcular_var(mean, N));
// for (auto i = var_double.begin(); i != var_double.end(); i++)
// {
// std::cout << *i / N << " "; // este acesso é rápido -- CPU
// }
double variancia = thrust::reduce(var.begin(), var.end(), 0.0, thrust::plus<double>());
std::cout << "variancia: " << variancia << "\n";
}
|
// g++ -DTHRUST_DEVICE_SYSTEM=THRUST_DEVICE_SYSTEM_OMP -I../../../thrust/ -fopenmp -x c++ exemplo1.cu -o exemplo1 && ./exemplo1 < ../17-intro-gpu/stocks2.csv
// nvcc -arch=sm_70 -std=c++14 exemplo1.cu -o exemplo1 && ./exemplo1 < ../17-intro-gpu/stocks2.csv
#include <hip/hip_runtime.h>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <iostream>
#include <math.h>
struct calcular_var
{
// essas marcações indicam que o código deve ser compilado para CPU (host)
// e GPU (device)
// IMPORTANTE: somente código com a marcação __device__ é compilado para GPU
double mean;
int N;
calcular_var(double a, int n): mean(a), N(n) {};
__device__
double operator()(const double& x) {
return ((x - mean) * (x - mean))/N;
}
};
int main()
{
int N = 0;
thrust::host_vector<double> hostMicrosoft;
thrust::host_vector<double> hostApple;
double a, m;
while (std::cin.fail() == false)
{
N += 1;
std::cin >> a;
std::cin >> m;
hostMicrosoft.push_back(m);
hostApple.push_back(a);
}
thrust::device_vector<double> diferenca(N);
thrust::device_vector<double> MSFT(hostMicrosoft);
thrust::device_vector<double> AAPL(hostApple);
thrust::device_vector<double> mean_vector(N);
thrust::device_vector<double> var(N);
thrust::device_vector<double> var_double(N);
// diference
thrust::transform(MSFT.begin(), MSFT.end(), AAPL.begin(), diferenca.begin(), thrust::minus<double>());
// mean
double mean = thrust::reduce(diferenca.begin(), diferenca.end(), 0.0, thrust::plus<double>()) / N;
// thrust::fill(mean_vector.begin(), mean_vector.end(), mean);
thrust::transform(diferenca.begin(), diferenca.end(), var.begin(), calcular_var(mean, N));
// for (auto i = var_double.begin(); i != var_double.end(); i++)
// {
// std::cout << *i / N << " "; // este acesso é rápido -- CPU
// }
double variancia = thrust::reduce(var.begin(), var.end(), 0.0, thrust::plus<double>());
std::cout << "variancia: " << variancia << "\n";
}
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void matMult(int* a, int* b, int* res,unsigned int rows, unsigned int k, unsigned int cols){
unsigned int r = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int c = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int sum = 0;
if(r< rows && c< cols){
for(int x=0; x<k; x++){
sum += a[r*k +x] + b[x*cols + c];
}
res[r*cols + c] = sum;
}
}
|
code for sm_80
Function : _Z7matMultPiS_S_jjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R26, SR_TID.X ; /* 0x00000000001a7919 */
/* 0x000e280000002100 */
/*0030*/ S2R R17, SR_CTAID.Y ; /* 0x0000000000117919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R26 ; /* 0x0000000003007a24 */
/* 0x001fca00078e021a */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R17, R17, c[0x0][0x4], R2 ; /* 0x0000010011117a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R17, c[0x0][0x178], P0 ; /* 0x00005e0011007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe20003f05270 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R25, RZ, RZ, RZ ; /* 0x000000ffff197224 */
/* 0x000fd600078e00ff */
/*00d0*/ @!P0 BRA 0x4e0 ; /* 0x0000040000008947 */
/* 0x000fea0003800000 */
/*00e0*/ MOV R2, c[0x0][0x17c] ; /* 0x00005f0000027a02 */
/* 0x000fe20000000f00 */
/*00f0*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R25, RZ, RZ, RZ ; /* 0x000000ffff197224 */
/* 0x000fe200078e00ff */
/*0110*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0120*/ LOP3.LUT R18, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302127812 */
/* 0x000fe400078ec0ff */
/*0130*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f26070 */
/*0140*/ ISETP.NE.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fd60003f05270 */
/*0150*/ @!P1 BRA 0x400 ; /* 0x000002a000009947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R26, R26, c[0x0][0x180], RZ ; /* 0x000060001a1a7a10 */
/* 0x000fe20007ffe0ff */
/*0170*/ IMAD R23, R17, R2, 0x3 ; /* 0x0000000311177424 */
/* 0x000fe200078e0202 */
/*0180*/ MOV R21, c[0x0][0x180] ; /* 0x0000600000157a02 */
/* 0x000fe20000000f00 */
/*0190*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe200078e00ff */
/*01a0*/ IADD3 R22, R18, -c[0x0][0x17c], RZ ; /* 0x80005f0012167a10 */
/* 0x000fe20007ffe0ff */
/*01b0*/ IMAD R26, R3, c[0x0][0x0], R26 ; /* 0x00000000031a7a24 */
/* 0x000fe200078e021a */
/*01c0*/ LEA R16, R21.reuse, R0, 0x1 ; /* 0x0000000015107211 */
/* 0x040fe200078e08ff */
/*01d0*/ IMAD.MOV.U32 R24, RZ, RZ, R0.reuse ; /* 0x000000ffff187224 */
/* 0x100fe400078e0000 */
/*01e0*/ IMAD R20, R21, 0x3, R0 ; /* 0x0000000315147824 */
/* 0x000fe400078e0200 */
/*01f0*/ IADD3 R28, R23.reuse, -0x3, RZ ; /* 0xfffffffd171c7810 */
/* 0x040fe20007ffe0ff */
/*0200*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe200078e00ff */
/*0210*/ IADD3 R4, R23, -0x2, RZ ; /* 0xfffffffe17047810 */
/* 0x000fc40007ffe0ff */
/*0220*/ IADD3 R8, R23, -0x1, RZ ; /* 0xffffffff17087810 */
/* 0x000fe20007ffe0ff */
/*0230*/ IMAD.WIDE.U32 R28, R28, R13, c[0x0][0x160] ; /* 0x000058001c1c7625 */
/* 0x000fc800078e000d */
/*0240*/ IMAD.WIDE.U32 R14, R24, R13.reuse, c[0x0][0x168] ; /* 0x00005a00180e7625 */
/* 0x080fe400078e000d */
/*0250*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000ea4000c1e1900 */
/*0260*/ IMAD.WIDE.U32 R4, R4, R13.reuse, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x080fe400078e000d */
/*0270*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1900 */
/*0280*/ IMAD.WIDE.U32 R6, R26, R13.reuse, c[0x0][0x168] ; /* 0x00005a001a067625 */
/* 0x080fe400078e000d */
/*0290*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee4000c1e1900 */
/*02a0*/ IMAD.WIDE.U32 R8, R8, R13, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fc400078e000d */
/*02b0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee4000c1e1900 */
/*02c0*/ IMAD.WIDE.U32 R2, R16, R13.reuse, c[0x0][0x168] ; /* 0x00005a0010027625 */
/* 0x080fe400078e000d */
/*02d0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f24000c1e1900 */
/*02e0*/ IMAD.WIDE.U32 R10, R23, R13.reuse, c[0x0][0x160] ; /* 0x00005800170a7625 */
/* 0x080fe400078e000d */
/*02f0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000f24000c1e1900 */
/*0300*/ IMAD.WIDE.U32 R12, R20, R13, c[0x0][0x168] ; /* 0x00005a00140c7625 */
/* 0x000fc400078e000d */
/*0310*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f68000c1e1900 */
/*0320*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f62000c1e1900 */
/*0330*/ IADD3 R19, R19, 0x4, RZ ; /* 0x0000000413137810 */
/* 0x000fe20007ffe0ff */
/*0340*/ IMAD R26, R21.reuse, 0x4, R26 ; /* 0x00000004151a7824 */
/* 0x040fe200078e021a */
/*0350*/ LEA R16, R21.reuse, R16, 0x2 ; /* 0x0000001015107211 */
/* 0x040fe200078e10ff */
/*0360*/ IMAD R24, R21, 0x4, R24 ; /* 0x0000000415187824 */
/* 0x000fe200078e0218 */
/*0370*/ IADD3 R23, R23, 0x4, RZ ; /* 0x0000000417177810 */
/* 0x000fe40007ffe0ff */
/*0380*/ LEA R20, R21, R20, 0x2 ; /* 0x0000001415147211 */
/* 0x000fc400078e10ff */
/*0390*/ IADD3 R14, R14, R28, R25 ; /* 0x0000001c0e0e7210 */
/* 0x004fc80007ffe019 */
/*03a0*/ IADD3 R5, R7, R4, R14 ; /* 0x0000000407057210 */
/* 0x008fe40007ffe00e */
/*03b0*/ IADD3 R4, R22, R19, RZ ; /* 0x0000001316047210 */
/* 0x000fc80007ffe0ff */
/*03c0*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f25270 */
/*03d0*/ IADD3 R5, R2, R8, R5 ; /* 0x0000000802057210 */
/* 0x010fc80007ffe005 */
/*03e0*/ IADD3 R25, R12, R10, R5 ; /* 0x0000000a0c197210 */
/* 0x020fce0007ffe005 */
/*03f0*/ @P1 BRA 0x1f0 ; /* 0xfffffdf000001947 */
/* 0x000fea000383ffff */
/*0400*/ @!P0 BRA 0x4e0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0410*/ IMAD R6, R19, c[0x0][0x180], R0 ; /* 0x0000600013067a24 */
/* 0x000fe400078e0200 */
/*0420*/ IMAD R19, R17, c[0x0][0x17c], R19 ; /* 0x00005f0011137a24 */
/* 0x000fe400078e0213 */
/*0430*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0440*/ IMAD.WIDE.U32 R2, R19, R4, c[0x0][0x160] ; /* 0x0000580013027625 */
/* 0x000fc800078e0004 */
/*0450*/ IMAD.WIDE.U32 R4, R6, R4, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fe400078e0004 */
/*0460*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IADD3 R18, R18, -0x1, RZ ; /* 0xffffffff12127810 */
/* 0x000fe40007ffe0ff */
/*0490*/ IADD3 R19, R19, 0x1, RZ ; /* 0x0000000113137810 */
/* 0x000fe40007ffe0ff */
/*04a0*/ ISETP.NE.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fc40003f05270 */
/*04b0*/ IADD3 R6, R6, c[0x0][0x180], RZ ; /* 0x0000600006067a10 */
/* 0x000fe40007ffe0ff */
/*04c0*/ IADD3 R25, R4, R2, R25 ; /* 0x0000000204197210 */
/* 0x004fd20007ffe019 */
/*04d0*/ @P0 BRA 0x430 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*04e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*04f0*/ IMAD R2, R17, c[0x0][0x180], R0 ; /* 0x0000600011027a24 */
/* 0x000fd200078e0200 */
/*0500*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0003 */
/*0510*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x000fe2000c101904 */
/*0520*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0530*/ BRA 0x530; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void matMult(int* a, int* b, int* res,unsigned int rows, unsigned int k, unsigned int cols){
unsigned int r = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int c = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int sum = 0;
if(r< rows && c< cols){
for(int x=0; x<k; x++){
sum += a[r*k +x] + b[x*cols + c];
}
res[r*cols + c] = sum;
}
}
|
.file "tmpxft_000bd391_00000000-6_matMult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z7matMultPiS_S_jjjPiS_S_jjj
.type _Z33__device_stub__Z7matMultPiS_S_jjjPiS_S_jjj, @function
_Z33__device_stub__Z7matMultPiS_S_jjjPiS_S_jjj:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7matMultPiS_S_jjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z7matMultPiS_S_jjjPiS_S_jjj, .-_Z33__device_stub__Z7matMultPiS_S_jjjPiS_S_jjj
.globl _Z7matMultPiS_S_jjj
.type _Z7matMultPiS_S_jjj, @function
_Z7matMultPiS_S_jjj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z7matMultPiS_S_jjjPiS_S_jjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7matMultPiS_S_jjj, .-_Z7matMultPiS_S_jjj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7matMultPiS_S_jjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7matMultPiS_S_jjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void matMult(int* a, int* b, int* res,unsigned int rows, unsigned int k, unsigned int cols){
unsigned int r = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int c = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int sum = 0;
if(r< rows && c< cols){
for(int x=0; x<k; x++){
sum += a[r*k +x] + b[x*cols + c];
}
res[r*cols + c] = sum;
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matMult(int* a, int* b, int* res,unsigned int rows, unsigned int k, unsigned int cols){
unsigned int r = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int c = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int sum = 0;
if(r< rows && c< cols){
for(int x=0; x<k; x++){
sum += a[r*k +x] + b[x*cols + c];
}
res[r*cols + c] = sum;
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matMult(int* a, int* b, int* res,unsigned int rows, unsigned int k, unsigned int cols){
unsigned int r = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int c = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int sum = 0;
if(r< rows && c< cols){
for(int x=0; x<k; x++){
sum += a[r*k +x] + b[x*cols + c];
}
res[r*cols + c] = sum;
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7matMultPiS_S_jjj
.globl _Z7matMultPiS_S_jjj
.p2align 8
.type _Z7matMultPiS_S_jjj,@function
_Z7matMultPiS_S_jjj:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x20
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_5
s_load_b32 s2, s[0:1], 0x1c
v_mov_b32_e32 v6, 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
.p2align 6
.LBB0_3:
v_mov_b32_e32 v3, 0
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_mov_b32_e32 v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[4:5]
v_add_nc_u32_e32 v4, s3, v4
v_lshlrev_b64 v[7:8], 2, v[2:3]
v_add_nc_u32_e32 v2, 1, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s4, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v3, v[7:8], off
global_load_b32 v5, v[9:10], off
s_waitcnt vmcnt(0)
v_add3_u32 v6, v3, v6, v5
s_cbranch_scc0 .LBB0_3
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7matMultPiS_S_jjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7matMultPiS_S_jjj, .Lfunc_end0-_Z7matMultPiS_S_jjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7matMultPiS_S_jjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7matMultPiS_S_jjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matMult(int* a, int* b, int* res,unsigned int rows, unsigned int k, unsigned int cols){
unsigned int r = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int c = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int sum = 0;
if(r< rows && c< cols){
for(int x=0; x<k; x++){
sum += a[r*k +x] + b[x*cols + c];
}
res[r*cols + c] = sum;
}
}
|
.text
.file "matMult.hip"
.globl _Z22__device_stub__matMultPiS_S_jjj # -- Begin function _Z22__device_stub__matMultPiS_S_jjj
.p2align 4, 0x90
.type _Z22__device_stub__matMultPiS_S_jjj,@function
_Z22__device_stub__matMultPiS_S_jjj: # @_Z22__device_stub__matMultPiS_S_jjj
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7matMultPiS_S_jjj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__matMultPiS_S_jjj, .Lfunc_end0-_Z22__device_stub__matMultPiS_S_jjj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7matMultPiS_S_jjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7matMultPiS_S_jjj,@object # @_Z7matMultPiS_S_jjj
.section .rodata,"a",@progbits
.globl _Z7matMultPiS_S_jjj
.p2align 3, 0x0
_Z7matMultPiS_S_jjj:
.quad _Z22__device_stub__matMultPiS_S_jjj
.size _Z7matMultPiS_S_jjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7matMultPiS_S_jjj"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__matMultPiS_S_jjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7matMultPiS_S_jjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z7matMultPiS_S_jjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R26, SR_TID.X ; /* 0x00000000001a7919 */
/* 0x000e280000002100 */
/*0030*/ S2R R17, SR_CTAID.Y ; /* 0x0000000000117919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R26 ; /* 0x0000000003007a24 */
/* 0x001fca00078e021a */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R17, R17, c[0x0][0x4], R2 ; /* 0x0000010011117a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R17, c[0x0][0x178], P0 ; /* 0x00005e0011007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe20003f05270 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R25, RZ, RZ, RZ ; /* 0x000000ffff197224 */
/* 0x000fd600078e00ff */
/*00d0*/ @!P0 BRA 0x4e0 ; /* 0x0000040000008947 */
/* 0x000fea0003800000 */
/*00e0*/ MOV R2, c[0x0][0x17c] ; /* 0x00005f0000027a02 */
/* 0x000fe20000000f00 */
/*00f0*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R25, RZ, RZ, RZ ; /* 0x000000ffff197224 */
/* 0x000fe200078e00ff */
/*0110*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0120*/ LOP3.LUT R18, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302127812 */
/* 0x000fe400078ec0ff */
/*0130*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f26070 */
/*0140*/ ISETP.NE.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fd60003f05270 */
/*0150*/ @!P1 BRA 0x400 ; /* 0x000002a000009947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R26, R26, c[0x0][0x180], RZ ; /* 0x000060001a1a7a10 */
/* 0x000fe20007ffe0ff */
/*0170*/ IMAD R23, R17, R2, 0x3 ; /* 0x0000000311177424 */
/* 0x000fe200078e0202 */
/*0180*/ MOV R21, c[0x0][0x180] ; /* 0x0000600000157a02 */
/* 0x000fe20000000f00 */
/*0190*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe200078e00ff */
/*01a0*/ IADD3 R22, R18, -c[0x0][0x17c], RZ ; /* 0x80005f0012167a10 */
/* 0x000fe20007ffe0ff */
/*01b0*/ IMAD R26, R3, c[0x0][0x0], R26 ; /* 0x00000000031a7a24 */
/* 0x000fe200078e021a */
/*01c0*/ LEA R16, R21.reuse, R0, 0x1 ; /* 0x0000000015107211 */
/* 0x040fe200078e08ff */
/*01d0*/ IMAD.MOV.U32 R24, RZ, RZ, R0.reuse ; /* 0x000000ffff187224 */
/* 0x100fe400078e0000 */
/*01e0*/ IMAD R20, R21, 0x3, R0 ; /* 0x0000000315147824 */
/* 0x000fe400078e0200 */
/*01f0*/ IADD3 R28, R23.reuse, -0x3, RZ ; /* 0xfffffffd171c7810 */
/* 0x040fe20007ffe0ff */
/*0200*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe200078e00ff */
/*0210*/ IADD3 R4, R23, -0x2, RZ ; /* 0xfffffffe17047810 */
/* 0x000fc40007ffe0ff */
/*0220*/ IADD3 R8, R23, -0x1, RZ ; /* 0xffffffff17087810 */
/* 0x000fe20007ffe0ff */
/*0230*/ IMAD.WIDE.U32 R28, R28, R13, c[0x0][0x160] ; /* 0x000058001c1c7625 */
/* 0x000fc800078e000d */
/*0240*/ IMAD.WIDE.U32 R14, R24, R13.reuse, c[0x0][0x168] ; /* 0x00005a00180e7625 */
/* 0x080fe400078e000d */
/*0250*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000ea4000c1e1900 */
/*0260*/ IMAD.WIDE.U32 R4, R4, R13.reuse, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x080fe400078e000d */
/*0270*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1900 */
/*0280*/ IMAD.WIDE.U32 R6, R26, R13.reuse, c[0x0][0x168] ; /* 0x00005a001a067625 */
/* 0x080fe400078e000d */
/*0290*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee4000c1e1900 */
/*02a0*/ IMAD.WIDE.U32 R8, R8, R13, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fc400078e000d */
/*02b0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee4000c1e1900 */
/*02c0*/ IMAD.WIDE.U32 R2, R16, R13.reuse, c[0x0][0x168] ; /* 0x00005a0010027625 */
/* 0x080fe400078e000d */
/*02d0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f24000c1e1900 */
/*02e0*/ IMAD.WIDE.U32 R10, R23, R13.reuse, c[0x0][0x160] ; /* 0x00005800170a7625 */
/* 0x080fe400078e000d */
/*02f0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000f24000c1e1900 */
/*0300*/ IMAD.WIDE.U32 R12, R20, R13, c[0x0][0x168] ; /* 0x00005a00140c7625 */
/* 0x000fc400078e000d */
/*0310*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f68000c1e1900 */
/*0320*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f62000c1e1900 */
/*0330*/ IADD3 R19, R19, 0x4, RZ ; /* 0x0000000413137810 */
/* 0x000fe20007ffe0ff */
/*0340*/ IMAD R26, R21.reuse, 0x4, R26 ; /* 0x00000004151a7824 */
/* 0x040fe200078e021a */
/*0350*/ LEA R16, R21.reuse, R16, 0x2 ; /* 0x0000001015107211 */
/* 0x040fe200078e10ff */
/*0360*/ IMAD R24, R21, 0x4, R24 ; /* 0x0000000415187824 */
/* 0x000fe200078e0218 */
/*0370*/ IADD3 R23, R23, 0x4, RZ ; /* 0x0000000417177810 */
/* 0x000fe40007ffe0ff */
/*0380*/ LEA R20, R21, R20, 0x2 ; /* 0x0000001415147211 */
/* 0x000fc400078e10ff */
/*0390*/ IADD3 R14, R14, R28, R25 ; /* 0x0000001c0e0e7210 */
/* 0x004fc80007ffe019 */
/*03a0*/ IADD3 R5, R7, R4, R14 ; /* 0x0000000407057210 */
/* 0x008fe40007ffe00e */
/*03b0*/ IADD3 R4, R22, R19, RZ ; /* 0x0000001316047210 */
/* 0x000fc80007ffe0ff */
/*03c0*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f25270 */
/*03d0*/ IADD3 R5, R2, R8, R5 ; /* 0x0000000802057210 */
/* 0x010fc80007ffe005 */
/*03e0*/ IADD3 R25, R12, R10, R5 ; /* 0x0000000a0c197210 */
/* 0x020fce0007ffe005 */
/*03f0*/ @P1 BRA 0x1f0 ; /* 0xfffffdf000001947 */
/* 0x000fea000383ffff */
/*0400*/ @!P0 BRA 0x4e0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0410*/ IMAD R6, R19, c[0x0][0x180], R0 ; /* 0x0000600013067a24 */
/* 0x000fe400078e0200 */
/*0420*/ IMAD R19, R17, c[0x0][0x17c], R19 ; /* 0x00005f0011137a24 */
/* 0x000fe400078e0213 */
/*0430*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0440*/ IMAD.WIDE.U32 R2, R19, R4, c[0x0][0x160] ; /* 0x0000580013027625 */
/* 0x000fc800078e0004 */
/*0450*/ IMAD.WIDE.U32 R4, R6, R4, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fe400078e0004 */
/*0460*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IADD3 R18, R18, -0x1, RZ ; /* 0xffffffff12127810 */
/* 0x000fe40007ffe0ff */
/*0490*/ IADD3 R19, R19, 0x1, RZ ; /* 0x0000000113137810 */
/* 0x000fe40007ffe0ff */
/*04a0*/ ISETP.NE.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fc40003f05270 */
/*04b0*/ IADD3 R6, R6, c[0x0][0x180], RZ ; /* 0x0000600006067a10 */
/* 0x000fe40007ffe0ff */
/*04c0*/ IADD3 R25, R4, R2, R25 ; /* 0x0000000204197210 */
/* 0x004fd20007ffe019 */
/*04d0*/ @P0 BRA 0x430 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*04e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*04f0*/ IMAD R2, R17, c[0x0][0x180], R0 ; /* 0x0000600011027a24 */
/* 0x000fd200078e0200 */
/*0500*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0003 */
/*0510*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x000fe2000c101904 */
/*0520*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0530*/ BRA 0x530; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7matMultPiS_S_jjj
.globl _Z7matMultPiS_S_jjj
.p2align 8
.type _Z7matMultPiS_S_jjj,@function
_Z7matMultPiS_S_jjj:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x20
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_5
s_load_b32 s2, s[0:1], 0x1c
v_mov_b32_e32 v6, 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
.p2align 6
.LBB0_3:
v_mov_b32_e32 v3, 0
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_mov_b32_e32 v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[4:5]
v_add_nc_u32_e32 v4, s3, v4
v_lshlrev_b64 v[7:8], 2, v[2:3]
v_add_nc_u32_e32 v2, 1, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s4, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v3, v[7:8], off
global_load_b32 v5, v[9:10], off
s_waitcnt vmcnt(0)
v_add3_u32 v6, v3, v6, v5
s_cbranch_scc0 .LBB0_3
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7matMultPiS_S_jjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7matMultPiS_S_jjj, .Lfunc_end0-_Z7matMultPiS_S_jjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7matMultPiS_S_jjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7matMultPiS_S_jjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000bd391_00000000-6_matMult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z7matMultPiS_S_jjjPiS_S_jjj
.type _Z33__device_stub__Z7matMultPiS_S_jjjPiS_S_jjj, @function
_Z33__device_stub__Z7matMultPiS_S_jjjPiS_S_jjj:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7matMultPiS_S_jjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z7matMultPiS_S_jjjPiS_S_jjj, .-_Z33__device_stub__Z7matMultPiS_S_jjjPiS_S_jjj
.globl _Z7matMultPiS_S_jjj
.type _Z7matMultPiS_S_jjj, @function
_Z7matMultPiS_S_jjj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z7matMultPiS_S_jjjPiS_S_jjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7matMultPiS_S_jjj, .-_Z7matMultPiS_S_jjj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7matMultPiS_S_jjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7matMultPiS_S_jjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "matMult.hip"
.globl _Z22__device_stub__matMultPiS_S_jjj # -- Begin function _Z22__device_stub__matMultPiS_S_jjj
.p2align 4, 0x90
.type _Z22__device_stub__matMultPiS_S_jjj,@function
_Z22__device_stub__matMultPiS_S_jjj: # @_Z22__device_stub__matMultPiS_S_jjj
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7matMultPiS_S_jjj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__matMultPiS_S_jjj, .Lfunc_end0-_Z22__device_stub__matMultPiS_S_jjj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7matMultPiS_S_jjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7matMultPiS_S_jjj,@object # @_Z7matMultPiS_S_jjj
.section .rodata,"a",@progbits
.globl _Z7matMultPiS_S_jjj
.p2align 3, 0x0
_Z7matMultPiS_S_jjj:
.quad _Z22__device_stub__matMultPiS_S_jjj
.size _Z7matMultPiS_S_jjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7matMultPiS_S_jjj"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__matMultPiS_S_jjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7matMultPiS_S_jjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <cuda.h>
#include <float.h>
const float MAX_EXP = 80. ;
__global__ void kCumulativeSum(
float *probabilities,
float *sumProbabilities,
int softMaxWidth,
int signalLength
)
{
extern __shared__ float sData[] ;
float *dataPrev = (float *) &sData[0] ;
float *dataNext = (float *) &sData[softMaxWidth] ;
// first copy data for current softMax
int signalIndex = signalLength * blockIdx.x ;
int dataIndex = blockIdx.y * softMaxWidth + threadIdx.x ;
int maxLength = min(softMaxWidth, signalLength-dataIndex+threadIdx.x) ;
for (int index = threadIdx.x ; index < maxLength && dataIndex < signalLength ;
index+= blockDim.x, dataIndex += blockDim.x)
{
dataPrev[index] = probabilities[signalIndex+dataIndex] ;
}
__syncthreads() ;
// Now compute cumulative sum
dataIndex = blockIdx.y * softMaxWidth + threadIdx.x ;
for (int round = 1 ; round < maxLength ; round = round<<1)
{
for (int index = threadIdx.x ; index < maxLength ; index+= blockDim.x)
{
float val = dataPrev[index] ;
if (index >= round)
val += dataPrev[index-round] ;
dataNext[index] = val ;
}
float *temp = dataPrev ;
dataPrev = dataNext ;
dataNext = temp ;
__syncthreads() ;
}
// Write out the data.
for (int index = threadIdx.x ; index < maxLength && dataIndex < signalLength ;
index+= blockDim.x, dataIndex += blockDim.x)
{
sumProbabilities[signalIndex+dataIndex] = dataPrev[index] ;
}
}
__global__ void kMultinomialSample(
float *unifRandNums,
float *probabilities,
float *samples,
int softMaxWidth,
int startShift,
int signalLength
)
{
extern __shared__ float sData[] ;
float *dataPrev = (float *) &sData[0] ;
float *dataNext = (float *) &sData[softMaxWidth] ;
// first copy data for current softMax
int signalIndex = signalLength * blockIdx.x ;
int dataIndex = blockIdx.y * softMaxWidth + threadIdx.x + startShift ;
float randNum = unifRandNums[blockIdx.x*gridDim.y + blockIdx.y] ;
int maxLength = min(softMaxWidth, signalLength-dataIndex+threadIdx.x) ;
for (int index = threadIdx.x ; index < maxLength && dataIndex < signalLength ;
index+= blockDim.x, dataIndex += blockDim.x)
{
dataPrev[index] = probabilities[signalIndex+dataIndex] ;
}
__syncthreads() ;
// Now compute cumulative sum
dataIndex = blockIdx.y * softMaxWidth + threadIdx.x + startShift ;
for (int round = 1 ; round < maxLength ; round = round<<1)
{
for (int index = threadIdx.x ; index < maxLength ; index+= blockDim.x)
{
float val = dataPrev[index] ;
if (index >= round)
val += dataPrev[index-round] ;
dataNext[index] = val ;
}
float *temp = dataPrev ;
dataPrev = dataNext ;
dataNext = temp ;
__syncthreads() ;
}
// Find the appropriate index where cumulative[i-1]<= r < cumulative[i]
for (int index = threadIdx.x ; index < maxLength && dataIndex < signalLength ;
index+= blockDim.x, dataIndex += blockDim.x)
{
if (index == 0)
{
if (randNum < dataPrev[index])
samples[signalIndex+dataIndex] = 1 ;
else
samples[signalIndex+dataIndex] = 0 ;
}
else
{
if (randNum >= dataPrev[index-1] && randNum < dataPrev[index])
samples[signalIndex+dataIndex] = 1 ;
else
samples[signalIndex+dataIndex] = 0 ;
}
}
}
__global__ void kSoftMaxStackApproxWithPositionBiases(
float *activations,
float *probabilities,
float *stdevs,
float *featureBiases,
float *positionBiases,
int softMaxWidth,
int signalLength
)
{
extern __shared__ float sData[] ;
float *arrData = (float *) &sData[0] ;
float *threadStores = (float *) &sData[softMaxWidth] ;
int signalIndex = blockIdx.x*signalLength ;
int dataIndex = blockIdx.y*softMaxWidth + threadIdx.x ;
float maxVal = -FLT_MAX ;
for (int index = threadIdx.x ; index < softMaxWidth && dataIndex < signalLength ;
index += blockDim.x, dataIndex += blockDim.x)
{
arrData[index] = activations[signalIndex+dataIndex] + positionBiases[index] ;
if (maxVal < arrData[index])
maxVal = arrData[index] ;
}
threadStores[threadIdx.x] = maxVal ;
__syncthreads() ;
// do a reduction to find the max of all maxes.
for (unsigned int s=blockDim.x/2; s>0; s>>=1)
{
if (threadIdx.x < s)
{
threadStores[threadIdx.x] =
threadStores[threadIdx.x+s]*(threadStores[threadIdx.x + s] >=threadStores[threadIdx.x]) +
threadStores[threadIdx.x] * (threadStores[threadIdx.x] > threadStores[threadIdx.x+s]) ;
}
__syncthreads();
}
// now we have max. Lets subract it from all elements, and compute intermediate logSumExp over all elements
// a thread is responsible for
float bias = featureBiases[blockIdx.x] ;
maxVal = threadStores[0] ;
__syncthreads();
float sumExp = 0. ;
dataIndex = blockIdx.y*softMaxWidth + threadIdx.x ;
for (int index = threadIdx.x ; index < softMaxWidth && dataIndex < signalLength ;
index += blockDim.x, dataIndex += blockDim.x)
{
arrData[index] = arrData[index] - maxVal ;
sumExp += __expf(arrData[index]) ;
}
threadStores[threadIdx.x] = sumExp ;
__syncthreads() ;
// compute normalization constant over sumExp by summing together all the intermediate values.
for (unsigned int s=blockDim.x/2; s>0; s>>=1)
{
if (threadIdx.x < s)
threadStores[threadIdx.x] += threadStores[threadIdx.x + s];
__syncthreads();
}
__syncthreads() ;
sumExp = threadStores[0] ;
float maxValNew = fmaxf(maxVal, bias) ;
bias = bias - maxValNew ;
float reluSumExp = sumExp * __expf(maxVal-maxValNew) + __expf(bias) ;
// notice, reusing maxValNew and maxVal variables for new causes.
// maxValNew is the negative delta from the previous one.
maxValNew = maxVal-maxValNew ;
// maxVal is -log(exp(biases)/(exp(biases)+sum(exp(x_i))))
maxVal = -bias + __logf(reluSumExp) ;
// write out probabilities and standard deviations
dataIndex = blockIdx.y*softMaxWidth + threadIdx.x ;
for (int index = threadIdx.x ; index < softMaxWidth && dataIndex < signalLength ;
index += blockDim.x, dataIndex += blockDim.x)
{
float r_x_i = __expf(arrData[index])/ sumExp ;
float relu_r_x_i = __expf(arrData[index]+maxValNew)/ reluSumExp ;
probabilities[signalIndex+dataIndex] = r_x_i * maxVal ;
float variance = r_x_i * ((1-r_x_i)*maxVal + relu_r_x_i) ;
if (variance < 0) // stupid overflows, underflows etc, causing a perfectly reasonable calculation to look negative..
variance = 0.0 ;
stdevs[signalIndex+dataIndex] = sqrtf(variance) ;
}
__syncthreads() ;
}
__global__ void kSoftMaxReluWithPositionBiases(
float *activations,
float *probabilities,
float *meanValues,
float *featureStdevs,
float *featureBiases,
float *positionBiases,
int softMaxWidth,
int shift,
int signalLength,
float minExpForSum
)
{
extern __shared__ float sData[] ;
float *arrData = (float *) &sData[0] ;
float *arrActivation = (float *) &sData[softMaxWidth] ;
float *threadStores = (float *) &sData[2*softMaxWidth] ;
int signalIndex = blockIdx.x*signalLength ;
int dataIndex = blockIdx.y*softMaxWidth + threadIdx.x + shift ;
float maxVal = -FLT_MAX ;
for (int index = threadIdx.x ; index < softMaxWidth && dataIndex < signalLength ;
index += blockDim.x, dataIndex += blockDim.x)
{
float x_i = activations[signalIndex+dataIndex] + positionBiases[index] ;
arrActivation[index] = x_i ;
float val = x_i ;
x_i = x_i - .5 ;
while (x_i >= minExpForSum)
{
if (x_i > MAX_EXP)
val = val + x_i ;
else
val = val + __logf(1. + __expf(x_i)) ;
x_i = x_i - 1.0 ;
}
arrData[index] = val ;
if (maxVal < arrData[index])
maxVal = arrData[index] ;
}
threadStores[threadIdx.x] = maxVal ;
__syncthreads() ;
// do a reduction to find the max of all maxes.
for (unsigned int s=blockDim.x/2; s>0; s>>=1)
{
if (threadIdx.x < s)
{
threadStores[threadIdx.x] =
threadStores[threadIdx.x+s]*(threadStores[threadIdx.x + s] >=threadStores[threadIdx.x]) +
threadStores[threadIdx.x] * (threadStores[threadIdx.x] > threadStores[threadIdx.x+s]) ;
}
__syncthreads();
}
// now we have max. Lets subract it from all elements, and compute intermediate logSumExp over all elements
// a thread is responsible for
float bias = featureBiases[blockIdx.x] ;
maxVal = fmaxf(threadStores[0], bias) ;
__syncthreads();
float sumExp = 0. ;
dataIndex = blockIdx.y*softMaxWidth + threadIdx.x + shift ;
for (int index = threadIdx.x ; index < softMaxWidth && dataIndex < signalLength ;
index += blockDim.x, dataIndex += blockDim.x)
{
arrData[index] = arrData[index] - maxVal ;
arrActivation[index] = arrActivation[index] - bias ;
sumExp += __expf(arrData[index]) ;
}
threadStores[threadIdx.x] = sumExp ;
__syncthreads() ;
// compute normalization constant over sumExp by summing together all the intermediate values.
for (unsigned int s=blockDim.x/2; s>0; s>>=1)
{
if (threadIdx.x < s)
threadStores[threadIdx.x] += threadStores[threadIdx.x + s];
__syncthreads();
}
__syncthreads() ;
sumExp = threadStores[0] + __expf(bias-maxVal) ;
// write out probabilities.
dataIndex = blockIdx.y*softMaxWidth + threadIdx.x + shift ;
for (int index = threadIdx.x ; index < softMaxWidth && dataIndex < signalLength ;
index += blockDim.x, dataIndex += blockDim.x)
{
float prob = __expf(arrData[index])/ sumExp ;
probabilities[signalIndex+dataIndex] = prob ;
// using the relu approximation. Remember to threshold
meanValues[signalIndex+dataIndex] = arrActivation[index] ;
featureStdevs[signalIndex+dataIndex] = sqrtf(1. / (1 + __expf(-arrActivation[index])));
}
__syncthreads() ;
}
__global__ void kSoftMaxWithOffAndPositionBiases(
float *activations,
float *probabilities,
float *featureBiases,
float *positionBiases,
int softMaxWidth,
int signalLength
)
{
extern __shared__ float sData[] ;
float *arrData = (float *) &sData[0] ;
float *threadStores = (float *) &sData[softMaxWidth] ;
int signalIndex = blockIdx.x*signalLength ;
int dataIndex = blockIdx.y*softMaxWidth + threadIdx.x ;
float maxVal = -FLT_MAX ;
for (int index = threadIdx.x ; index < softMaxWidth && dataIndex < signalLength ;
index += blockDim.x, dataIndex += blockDim.x)
{
arrData[index] = activations[signalIndex+dataIndex] + positionBiases[index] ;
if (maxVal < arrData[index])
maxVal = arrData[index] ;
}
threadStores[threadIdx.x] = maxVal ;
__syncthreads() ;
// do a reduction to find the max of all maxes.
for (unsigned int s=blockDim.x/2; s>0; s>>=1)
{
if (threadIdx.x < s)
{
threadStores[threadIdx.x] =
threadStores[threadIdx.x+s]*(threadStores[threadIdx.x + s] >=threadStores[threadIdx.x]) +
threadStores[threadIdx.x] * (threadStores[threadIdx.x] > threadStores[threadIdx.x+s]) ;
}
__syncthreads();
}
// now we have max. Lets subract it from all elements, and compute intermediate logSumExp over all elements
// a thread is responsible for
float bias = featureBiases[blockIdx.x] ;
maxVal = fmaxf(threadStores[0], bias) ;
__syncthreads();
float sumExp = 0. ;
dataIndex = blockIdx.y*softMaxWidth + threadIdx.x ;
for (int index = threadIdx.x ; index < softMaxWidth && dataIndex < signalLength ;
index += blockDim.x, dataIndex += blockDim.x)
{
arrData[index] = arrData[index] - maxVal ;
sumExp += __expf(arrData[index]) ;
}
threadStores[threadIdx.x] = sumExp ;
__syncthreads() ;
// compute normalization constant over sumExp by summing together all the intermediate values.
for (unsigned int s=blockDim.x/2; s>0; s>>=1)
{
if (threadIdx.x < s)
threadStores[threadIdx.x] += threadStores[threadIdx.x + s];
__syncthreads();
}
__syncthreads() ;
sumExp = threadStores[0] + __expf(bias-maxVal) ;
// write out probabilities.
dataIndex = blockIdx.y*softMaxWidth + threadIdx.x ;
for (int index = threadIdx.x ; index < softMaxWidth && dataIndex < signalLength ;
index += blockDim.x, dataIndex += blockDim.x)
{
probabilities[signalIndex+dataIndex] = __expf(arrData[index])/ sumExp ;
}
__syncthreads() ;
}
__global__ void kSoftMaxWithOff(float *activations, float *probabilities, float *biases,
int softMaxWidth, int signalLength, int numPtsPerThread)
{
extern __shared__ float sData[] ;
float *arrData = (float *) &sData[0] ;
float *threadStores = (float *) &sData[softMaxWidth] ;
int signalIndex = blockIdx.x*signalLength ;
int blockIndex = blockIdx.y*softMaxWidth ;
int softMaxIndex = blockIndex + threadIdx.x*numPtsPerThread ;
// copy to local memory
int numToCopy = numPtsPerThread ;
if (softMaxIndex + numToCopy > signalLength)
numToCopy = signalLength - softMaxIndex ;
if (softMaxIndex + numToCopy > blockIndex + softMaxWidth)
numToCopy = blockIndex + softMaxWidth - softMaxIndex ;
float maxVal = -FLT_MAX ;
for (int index = 0 ; index < numToCopy ; index++)
{
arrData[softMaxIndex+index-blockIndex] = activations[signalIndex+softMaxIndex+index] ;
if (maxVal < arrData[softMaxIndex+index])
maxVal = arrData[softMaxIndex+index-blockIndex] ;
}
threadStores[threadIdx.x] = maxVal ;
__syncthreads() ;
// do a reduction to find the max of all maxes.
for (unsigned int s=blockDim.x/2; s>0; s>>=1)
{
if (threadIdx.x < s)
{
threadStores[threadIdx.x] =
threadStores[threadIdx.x+s]*(threadStores[threadIdx.x + s] >=threadStores[threadIdx.x]) +
threadStores[threadIdx.x] * (threadStores[threadIdx.x] > threadStores[threadIdx.x+s]) ;
}
__syncthreads();
}
// now we have max. Lets subract it from all elements, and compute intermediate logSumExp over all elements
// a thread is responsible for
float bias = biases[blockIdx.x] ;
maxVal = threadStores[0] * (threadStores[0] > bias) + bias * (bias >= threadStores[0]) ;
__syncthreads();
float sumExp = 0. ;
for (int index = 0 ; index < numToCopy ; index++)
{
arrData[softMaxIndex+index-blockIndex] = arrData[softMaxIndex+index-blockIndex] - maxVal ;
sumExp += __expf(arrData[softMaxIndex+index-blockIndex]) ;
}
threadStores[threadIdx.x] = sumExp ;
__syncthreads() ;
// compute normalization constant over sumExp by summing together all the intermediate values.
for (unsigned int s=blockDim.x/2; s>0; s>>=1)
{
if (threadIdx.x < s)
threadStores[threadIdx.x] += threadStores[threadIdx.x + s];
__syncthreads();
}
__syncthreads() ;
sumExp = threadStores[0] + __expf(bias-maxVal) ;
for (int index = 0 ; index < numToCopy ; index++)
{
probabilities[signalIndex+softMaxIndex+index] = __expf(arrData[softMaxIndex+index-blockIndex])/ sumExp ;
}
__syncthreads() ;
}
|
.file "tmpxft_000d4387_00000000-6_SoftMax_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14kCumulativeSumPfS_iiPfS_ii
.type _Z38__device_stub__Z14kCumulativeSumPfS_iiPfS_ii, @function
_Z38__device_stub__Z14kCumulativeSumPfS_iiPfS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14kCumulativeSumPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z14kCumulativeSumPfS_iiPfS_ii, .-_Z38__device_stub__Z14kCumulativeSumPfS_iiPfS_ii
.globl _Z14kCumulativeSumPfS_ii
.type _Z14kCumulativeSumPfS_ii, @function
_Z14kCumulativeSumPfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14kCumulativeSumPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14kCumulativeSumPfS_ii, .-_Z14kCumulativeSumPfS_ii
.globl _Z45__device_stub__Z18kMultinomialSamplePfS_S_iiiPfS_S_iii
.type _Z45__device_stub__Z18kMultinomialSamplePfS_S_iiiPfS_S_iii, @function
_Z45__device_stub__Z18kMultinomialSamplePfS_S_iiiPfS_S_iii:
.LFB2053:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18kMultinomialSamplePfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z45__device_stub__Z18kMultinomialSamplePfS_S_iiiPfS_S_iii, .-_Z45__device_stub__Z18kMultinomialSamplePfS_S_iiiPfS_S_iii
.globl _Z18kMultinomialSamplePfS_S_iii
.type _Z18kMultinomialSamplePfS_S_iii, @function
_Z18kMultinomialSamplePfS_S_iii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z18kMultinomialSamplePfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z18kMultinomialSamplePfS_S_iii, .-_Z18kMultinomialSamplePfS_S_iii
.globl _Z67__device_stub__Z37kSoftMaxStackApproxWithPositionBiasesPfS_S_S_S_iiPfS_S_S_S_ii
.type _Z67__device_stub__Z37kSoftMaxStackApproxWithPositionBiasesPfS_S_S_S_iiPfS_S_S_S_ii, @function
_Z67__device_stub__Z37kSoftMaxStackApproxWithPositionBiasesPfS_S_S_S_iiPfS_S_S_S_ii:
.LFB2055:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z37kSoftMaxStackApproxWithPositionBiasesPfS_S_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z67__device_stub__Z37kSoftMaxStackApproxWithPositionBiasesPfS_S_S_S_iiPfS_S_S_S_ii, .-_Z67__device_stub__Z37kSoftMaxStackApproxWithPositionBiasesPfS_S_S_S_iiPfS_S_S_S_ii
.globl _Z37kSoftMaxStackApproxWithPositionBiasesPfS_S_S_S_ii
.type _Z37kSoftMaxStackApproxWithPositionBiasesPfS_S_S_S_ii, @function
_Z37kSoftMaxStackApproxWithPositionBiasesPfS_S_S_S_ii:
.LFB2056:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z67__device_stub__Z37kSoftMaxStackApproxWithPositionBiasesPfS_S_S_S_iiPfS_S_S_S_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z37kSoftMaxStackApproxWithPositionBiasesPfS_S_S_S_ii, .-_Z37kSoftMaxStackApproxWithPositionBiasesPfS_S_S_S_ii
.globl _Z64__device_stub__Z30kSoftMaxReluWithPositionBiasesPfS_S_S_S_S_iiifPfS_S_S_S_S_iiif
.type _Z64__device_stub__Z30kSoftMaxReluWithPositionBiasesPfS_S_S_S_S_iiifPfS_S_S_S_S_iiif, @function
_Z64__device_stub__Z30kSoftMaxReluWithPositionBiasesPfS_S_S_S_S_iiifPfS_S_S_S_S_iiif:
.LFB2057:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 12(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z30kSoftMaxReluWithPositionBiasesPfS_S_S_S_S_iiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z64__device_stub__Z30kSoftMaxReluWithPositionBiasesPfS_S_S_S_S_iiifPfS_S_S_S_S_iiif, .-_Z64__device_stub__Z30kSoftMaxReluWithPositionBiasesPfS_S_S_S_S_iiifPfS_S_S_S_S_iiif
.globl _Z30kSoftMaxReluWithPositionBiasesPfS_S_S_S_S_iiif
.type _Z30kSoftMaxReluWithPositionBiasesPfS_S_S_S_S_iiif, @function
_Z30kSoftMaxReluWithPositionBiasesPfS_S_S_S_S_iiif:
.LFB2058:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z64__device_stub__Z30kSoftMaxReluWithPositionBiasesPfS_S_S_S_S_iiifPfS_S_S_S_S_iiif
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z30kSoftMaxReluWithPositionBiasesPfS_S_S_S_S_iiif, .-_Z30kSoftMaxReluWithPositionBiasesPfS_S_S_S_S_iiif
.globl _Z60__device_stub__Z32kSoftMaxWithOffAndPositionBiasesPfS_S_S_iiPfS_S_S_ii
.type _Z60__device_stub__Z32kSoftMaxWithOffAndPositionBiasesPfS_S_S_iiPfS_S_S_ii, @function
_Z60__device_stub__Z32kSoftMaxWithOffAndPositionBiasesPfS_S_S_iiPfS_S_S_ii:
.LFB2059:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z32kSoftMaxWithOffAndPositionBiasesPfS_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z60__device_stub__Z32kSoftMaxWithOffAndPositionBiasesPfS_S_S_iiPfS_S_S_ii, .-_Z60__device_stub__Z32kSoftMaxWithOffAndPositionBiasesPfS_S_S_iiPfS_S_S_ii
.globl _Z32kSoftMaxWithOffAndPositionBiasesPfS_S_S_ii
.type _Z32kSoftMaxWithOffAndPositionBiasesPfS_S_S_ii, @function
_Z32kSoftMaxWithOffAndPositionBiasesPfS_S_S_ii:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z60__device_stub__Z32kSoftMaxWithOffAndPositionBiasesPfS_S_S_iiPfS_S_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z32kSoftMaxWithOffAndPositionBiasesPfS_S_S_ii, .-_Z32kSoftMaxWithOffAndPositionBiasesPfS_S_S_ii
.globl _Z42__device_stub__Z15kSoftMaxWithOffPfS_S_iiiPfS_S_iii
.type _Z42__device_stub__Z15kSoftMaxWithOffPfS_S_iiiPfS_S_iii, @function
_Z42__device_stub__Z15kSoftMaxWithOffPfS_S_iiiPfS_S_iii:
.LFB2061:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15kSoftMaxWithOffPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z42__device_stub__Z15kSoftMaxWithOffPfS_S_iiiPfS_S_iii, .-_Z42__device_stub__Z15kSoftMaxWithOffPfS_S_iiiPfS_S_iii
.globl _Z15kSoftMaxWithOffPfS_S_iii
.type _Z15kSoftMaxWithOffPfS_S_iii, @function
_Z15kSoftMaxWithOffPfS_S_iii:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15kSoftMaxWithOffPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z15kSoftMaxWithOffPfS_S_iii, .-_Z15kSoftMaxWithOffPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15kSoftMaxWithOffPfS_S_iii"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z32kSoftMaxWithOffAndPositionBiasesPfS_S_S_ii"
.align 8
.LC2:
.string "_Z30kSoftMaxReluWithPositionBiasesPfS_S_S_S_S_iiif"
.align 8
.LC3:
.string "_Z37kSoftMaxStackApproxWithPositionBiasesPfS_S_S_S_ii"
.align 8
.LC4:
.string "_Z18kMultinomialSamplePfS_S_iii"
.section .rodata.str1.1
.LC5:
.string "_Z14kCumulativeSumPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2064:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15kSoftMaxWithOffPfS_S_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z32kSoftMaxWithOffAndPositionBiasesPfS_S_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z30kSoftMaxReluWithPositionBiasesPfS_S_S_S_S_iiif(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z37kSoftMaxStackApproxWithPositionBiasesPfS_S_S_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z18kMultinomialSamplePfS_S_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z14kCumulativeSumPfS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <cuda.h>
#include <float.h>
const float MAX_EXP = 80. ;
__global__ void kCumulativeSum(
float *probabilities,
float *sumProbabilities,
int softMaxWidth,
int signalLength
)
{
extern __shared__ float sData[] ;
float *dataPrev = (float *) &sData[0] ;
float *dataNext = (float *) &sData[softMaxWidth] ;
// first copy data for current softMax
int signalIndex = signalLength * blockIdx.x ;
int dataIndex = blockIdx.y * softMaxWidth + threadIdx.x ;
int maxLength = min(softMaxWidth, signalLength-dataIndex+threadIdx.x) ;
for (int index = threadIdx.x ; index < maxLength && dataIndex < signalLength ;
index+= blockDim.x, dataIndex += blockDim.x)
{
dataPrev[index] = probabilities[signalIndex+dataIndex] ;
}
__syncthreads() ;
// Now compute cumulative sum
dataIndex = blockIdx.y * softMaxWidth + threadIdx.x ;
for (int round = 1 ; round < maxLength ; round = round<<1)
{
for (int index = threadIdx.x ; index < maxLength ; index+= blockDim.x)
{
float val = dataPrev[index] ;
if (index >= round)
val += dataPrev[index-round] ;
dataNext[index] = val ;
}
float *temp = dataPrev ;
dataPrev = dataNext ;
dataNext = temp ;
__syncthreads() ;
}
// Write out the data.
for (int index = threadIdx.x ; index < maxLength && dataIndex < signalLength ;
index+= blockDim.x, dataIndex += blockDim.x)
{
sumProbabilities[signalIndex+dataIndex] = dataPrev[index] ;
}
}
__global__ void kMultinomialSample(
float *unifRandNums,
float *probabilities,
float *samples,
int softMaxWidth,
int startShift,
int signalLength
)
{
extern __shared__ float sData[] ;
float *dataPrev = (float *) &sData[0] ;
float *dataNext = (float *) &sData[softMaxWidth] ;
// first copy data for current softMax
int signalIndex = signalLength * blockIdx.x ;
int dataIndex = blockIdx.y * softMaxWidth + threadIdx.x + startShift ;
float randNum = unifRandNums[blockIdx.x*gridDim.y + blockIdx.y] ;
int maxLength = min(softMaxWidth, signalLength-dataIndex+threadIdx.x) ;
for (int index = threadIdx.x ; index < maxLength && dataIndex < signalLength ;
index+= blockDim.x, dataIndex += blockDim.x)
{
dataPrev[index] = probabilities[signalIndex+dataIndex] ;
}
__syncthreads() ;
// Now compute cumulative sum
dataIndex = blockIdx.y * softMaxWidth + threadIdx.x + startShift ;
for (int round = 1 ; round < maxLength ; round = round<<1)
{
for (int index = threadIdx.x ; index < maxLength ; index+= blockDim.x)
{
float val = dataPrev[index] ;
if (index >= round)
val += dataPrev[index-round] ;
dataNext[index] = val ;
}
float *temp = dataPrev ;
dataPrev = dataNext ;
dataNext = temp ;
__syncthreads() ;
}
// Find the appropriate index where cumulative[i-1]<= r < cumulative[i]
for (int index = threadIdx.x ; index < maxLength && dataIndex < signalLength ;
index+= blockDim.x, dataIndex += blockDim.x)
{
if (index == 0)
{
if (randNum < dataPrev[index])
samples[signalIndex+dataIndex] = 1 ;
else
samples[signalIndex+dataIndex] = 0 ;
}
else
{
if (randNum >= dataPrev[index-1] && randNum < dataPrev[index])
samples[signalIndex+dataIndex] = 1 ;
else
samples[signalIndex+dataIndex] = 0 ;
}
}
}
__global__ void kSoftMaxStackApproxWithPositionBiases(
float *activations,
float *probabilities,
float *stdevs,
float *featureBiases,
float *positionBiases,
int softMaxWidth,
int signalLength
)
{
extern __shared__ float sData[] ;
float *arrData = (float *) &sData[0] ;
float *threadStores = (float *) &sData[softMaxWidth] ;
int signalIndex = blockIdx.x*signalLength ;
int dataIndex = blockIdx.y*softMaxWidth + threadIdx.x ;
float maxVal = -FLT_MAX ;
for (int index = threadIdx.x ; index < softMaxWidth && dataIndex < signalLength ;
index += blockDim.x, dataIndex += blockDim.x)
{
arrData[index] = activations[signalIndex+dataIndex] + positionBiases[index] ;
if (maxVal < arrData[index])
maxVal = arrData[index] ;
}
threadStores[threadIdx.x] = maxVal ;
__syncthreads() ;
// do a reduction to find the max of all maxes.
for (unsigned int s=blockDim.x/2; s>0; s>>=1)
{
if (threadIdx.x < s)
{
threadStores[threadIdx.x] =
threadStores[threadIdx.x+s]*(threadStores[threadIdx.x + s] >=threadStores[threadIdx.x]) +
threadStores[threadIdx.x] * (threadStores[threadIdx.x] > threadStores[threadIdx.x+s]) ;
}
__syncthreads();
}
// now we have max. Lets subract it from all elements, and compute intermediate logSumExp over all elements
// a thread is responsible for
float bias = featureBiases[blockIdx.x] ;
maxVal = threadStores[0] ;
__syncthreads();
float sumExp = 0. ;
dataIndex = blockIdx.y*softMaxWidth + threadIdx.x ;
for (int index = threadIdx.x ; index < softMaxWidth && dataIndex < signalLength ;
index += blockDim.x, dataIndex += blockDim.x)
{
arrData[index] = arrData[index] - maxVal ;
sumExp += __expf(arrData[index]) ;
}
threadStores[threadIdx.x] = sumExp ;
__syncthreads() ;
// compute normalization constant over sumExp by summing together all the intermediate values.
for (unsigned int s=blockDim.x/2; s>0; s>>=1)
{
if (threadIdx.x < s)
threadStores[threadIdx.x] += threadStores[threadIdx.x + s];
__syncthreads();
}
__syncthreads() ;
sumExp = threadStores[0] ;
float maxValNew = fmaxf(maxVal, bias) ;
bias = bias - maxValNew ;
float reluSumExp = sumExp * __expf(maxVal-maxValNew) + __expf(bias) ;
// notice, reusing maxValNew and maxVal variables for new causes.
// maxValNew is the negative delta from the previous one.
maxValNew = maxVal-maxValNew ;
// maxVal is -log(exp(biases)/(exp(biases)+sum(exp(x_i))))
maxVal = -bias + __logf(reluSumExp) ;
// write out probabilities and standard deviations
dataIndex = blockIdx.y*softMaxWidth + threadIdx.x ;
for (int index = threadIdx.x ; index < softMaxWidth && dataIndex < signalLength ;
index += blockDim.x, dataIndex += blockDim.x)
{
float r_x_i = __expf(arrData[index])/ sumExp ;
float relu_r_x_i = __expf(arrData[index]+maxValNew)/ reluSumExp ;
probabilities[signalIndex+dataIndex] = r_x_i * maxVal ;
float variance = r_x_i * ((1-r_x_i)*maxVal + relu_r_x_i) ;
if (variance < 0) // stupid overflows, underflows etc, causing a perfectly reasonable calculation to look negative..
variance = 0.0 ;
stdevs[signalIndex+dataIndex] = sqrtf(variance) ;
}
__syncthreads() ;
}
__global__ void kSoftMaxReluWithPositionBiases(
float *activations,
float *probabilities,
float *meanValues,
float *featureStdevs,
float *featureBiases,
float *positionBiases,
int softMaxWidth,
int shift,
int signalLength,
float minExpForSum
)
{
extern __shared__ float sData[] ;
float *arrData = (float *) &sData[0] ;
float *arrActivation = (float *) &sData[softMaxWidth] ;
float *threadStores = (float *) &sData[2*softMaxWidth] ;
int signalIndex = blockIdx.x*signalLength ;
int dataIndex = blockIdx.y*softMaxWidth + threadIdx.x + shift ;
float maxVal = -FLT_MAX ;
for (int index = threadIdx.x ; index < softMaxWidth && dataIndex < signalLength ;
index += blockDim.x, dataIndex += blockDim.x)
{
float x_i = activations[signalIndex+dataIndex] + positionBiases[index] ;
arrActivation[index] = x_i ;
float val = x_i ;
x_i = x_i - .5 ;
while (x_i >= minExpForSum)
{
if (x_i > MAX_EXP)
val = val + x_i ;
else
val = val + __logf(1. + __expf(x_i)) ;
x_i = x_i - 1.0 ;
}
arrData[index] = val ;
if (maxVal < arrData[index])
maxVal = arrData[index] ;
}
threadStores[threadIdx.x] = maxVal ;
__syncthreads() ;
// do a reduction to find the max of all maxes.
for (unsigned int s=blockDim.x/2; s>0; s>>=1)
{
if (threadIdx.x < s)
{
threadStores[threadIdx.x] =
threadStores[threadIdx.x+s]*(threadStores[threadIdx.x + s] >=threadStores[threadIdx.x]) +
threadStores[threadIdx.x] * (threadStores[threadIdx.x] > threadStores[threadIdx.x+s]) ;
}
__syncthreads();
}
// now we have max. Lets subract it from all elements, and compute intermediate logSumExp over all elements
// a thread is responsible for
float bias = featureBiases[blockIdx.x] ;
maxVal = fmaxf(threadStores[0], bias) ;
__syncthreads();
float sumExp = 0. ;
dataIndex = blockIdx.y*softMaxWidth + threadIdx.x + shift ;
for (int index = threadIdx.x ; index < softMaxWidth && dataIndex < signalLength ;
index += blockDim.x, dataIndex += blockDim.x)
{
arrData[index] = arrData[index] - maxVal ;
arrActivation[index] = arrActivation[index] - bias ;
sumExp += __expf(arrData[index]) ;
}
threadStores[threadIdx.x] = sumExp ;
__syncthreads() ;
// compute normalization constant over sumExp by summing together all the intermediate values.
for (unsigned int s=blockDim.x/2; s>0; s>>=1)
{
if (threadIdx.x < s)
threadStores[threadIdx.x] += threadStores[threadIdx.x + s];
__syncthreads();
}
__syncthreads() ;
sumExp = threadStores[0] + __expf(bias-maxVal) ;
// write out probabilities.
dataIndex = blockIdx.y*softMaxWidth + threadIdx.x + shift ;
for (int index = threadIdx.x ; index < softMaxWidth && dataIndex < signalLength ;
index += blockDim.x, dataIndex += blockDim.x)
{
float prob = __expf(arrData[index])/ sumExp ;
probabilities[signalIndex+dataIndex] = prob ;
// using the relu approximation. Remember to threshold
meanValues[signalIndex+dataIndex] = arrActivation[index] ;
featureStdevs[signalIndex+dataIndex] = sqrtf(1. / (1 + __expf(-arrActivation[index])));
}
__syncthreads() ;
}
__global__ void kSoftMaxWithOffAndPositionBiases(
float *activations,
float *probabilities,
float *featureBiases,
float *positionBiases,
int softMaxWidth,
int signalLength
)
{
extern __shared__ float sData[] ;
float *arrData = (float *) &sData[0] ;
float *threadStores = (float *) &sData[softMaxWidth] ;
int signalIndex = blockIdx.x*signalLength ;
int dataIndex = blockIdx.y*softMaxWidth + threadIdx.x ;
float maxVal = -FLT_MAX ;
for (int index = threadIdx.x ; index < softMaxWidth && dataIndex < signalLength ;
index += blockDim.x, dataIndex += blockDim.x)
{
arrData[index] = activations[signalIndex+dataIndex] + positionBiases[index] ;
if (maxVal < arrData[index])
maxVal = arrData[index] ;
}
threadStores[threadIdx.x] = maxVal ;
__syncthreads() ;
// do a reduction to find the max of all maxes.
for (unsigned int s=blockDim.x/2; s>0; s>>=1)
{
if (threadIdx.x < s)
{
threadStores[threadIdx.x] =
threadStores[threadIdx.x+s]*(threadStores[threadIdx.x + s] >=threadStores[threadIdx.x]) +
threadStores[threadIdx.x] * (threadStores[threadIdx.x] > threadStores[threadIdx.x+s]) ;
}
__syncthreads();
}
// now we have max. Lets subract it from all elements, and compute intermediate logSumExp over all elements
// a thread is responsible for
float bias = featureBiases[blockIdx.x] ;
maxVal = fmaxf(threadStores[0], bias) ;
__syncthreads();
float sumExp = 0. ;
dataIndex = blockIdx.y*softMaxWidth + threadIdx.x ;
for (int index = threadIdx.x ; index < softMaxWidth && dataIndex < signalLength ;
index += blockDim.x, dataIndex += blockDim.x)
{
arrData[index] = arrData[index] - maxVal ;
sumExp += __expf(arrData[index]) ;
}
threadStores[threadIdx.x] = sumExp ;
__syncthreads() ;
// compute normalization constant over sumExp by summing together all the intermediate values.
for (unsigned int s=blockDim.x/2; s>0; s>>=1)
{
if (threadIdx.x < s)
threadStores[threadIdx.x] += threadStores[threadIdx.x + s];
__syncthreads();
}
__syncthreads() ;
sumExp = threadStores[0] + __expf(bias-maxVal) ;
// write out probabilities.
dataIndex = blockIdx.y*softMaxWidth + threadIdx.x ;
for (int index = threadIdx.x ; index < softMaxWidth && dataIndex < signalLength ;
index += blockDim.x, dataIndex += blockDim.x)
{
probabilities[signalIndex+dataIndex] = __expf(arrData[index])/ sumExp ;
}
__syncthreads() ;
}
__global__ void kSoftMaxWithOff(float *activations, float *probabilities, float *biases,
int softMaxWidth, int signalLength, int numPtsPerThread)
{
extern __shared__ float sData[] ;
float *arrData = (float *) &sData[0] ;
float *threadStores = (float *) &sData[softMaxWidth] ;
int signalIndex = blockIdx.x*signalLength ;
int blockIndex = blockIdx.y*softMaxWidth ;
int softMaxIndex = blockIndex + threadIdx.x*numPtsPerThread ;
// copy to local memory
int numToCopy = numPtsPerThread ;
if (softMaxIndex + numToCopy > signalLength)
numToCopy = signalLength - softMaxIndex ;
if (softMaxIndex + numToCopy > blockIndex + softMaxWidth)
numToCopy = blockIndex + softMaxWidth - softMaxIndex ;
float maxVal = -FLT_MAX ;
for (int index = 0 ; index < numToCopy ; index++)
{
arrData[softMaxIndex+index-blockIndex] = activations[signalIndex+softMaxIndex+index] ;
if (maxVal < arrData[softMaxIndex+index])
maxVal = arrData[softMaxIndex+index-blockIndex] ;
}
threadStores[threadIdx.x] = maxVal ;
__syncthreads() ;
// do a reduction to find the max of all maxes.
for (unsigned int s=blockDim.x/2; s>0; s>>=1)
{
if (threadIdx.x < s)
{
threadStores[threadIdx.x] =
threadStores[threadIdx.x+s]*(threadStores[threadIdx.x + s] >=threadStores[threadIdx.x]) +
threadStores[threadIdx.x] * (threadStores[threadIdx.x] > threadStores[threadIdx.x+s]) ;
}
__syncthreads();
}
// now we have max. Lets subract it from all elements, and compute intermediate logSumExp over all elements
// a thread is responsible for
float bias = biases[blockIdx.x] ;
maxVal = threadStores[0] * (threadStores[0] > bias) + bias * (bias >= threadStores[0]) ;
__syncthreads();
float sumExp = 0. ;
for (int index = 0 ; index < numToCopy ; index++)
{
arrData[softMaxIndex+index-blockIndex] = arrData[softMaxIndex+index-blockIndex] - maxVal ;
sumExp += __expf(arrData[softMaxIndex+index-blockIndex]) ;
}
threadStores[threadIdx.x] = sumExp ;
__syncthreads() ;
// compute normalization constant over sumExp by summing together all the intermediate values.
for (unsigned int s=blockDim.x/2; s>0; s>>=1)
{
if (threadIdx.x < s)
threadStores[threadIdx.x] += threadStores[threadIdx.x + s];
__syncthreads();
}
__syncthreads() ;
sumExp = threadStores[0] + __expf(bias-maxVal) ;
for (int index = 0 ; index < numToCopy ; index++)
{
probabilities[signalIndex+softMaxIndex+index] = __expf(arrData[softMaxIndex+index-blockIndex])/ sumExp ;
}
__syncthreads() ;
}
|
#pragma once
#include <hip/hip_runtime.h>
__global__ void kMultinomialSample(
float *unifRandNums,
float *probabilities,
float *samples,
int softMaxWidth,
int startShift,
int signalLength
) ;
__global__ void kCumulativeSum(
float *probabilities,
float *sumProbabilities,
int softMaxWidth,
int signalLength
) ;
__global__ void kSoftMaxWithOff(
float *activations,
float *probabilities,
float *biases,
int softMaxWidth,
int signalLength,
int numPtsPerThread
) ;
__global__ void kSoftMaxWithOffAndPositionBiases(
float *activations,
float *probabilities,
float *featureBiases,
float *positionBiases,
int softMaxWidth,
int signalLength
) ;
__global__ void kSoftMaxStackApproxWithPositionBiases(
float *activations,
float *probabilities,
float *stdevs,
float *featureBiases,
float *positionBiases,
int softMaxWidth,
int signalLength
) ;
__global__ void kSoftMaxReluWithPositionBiases(
float *activations,
float *probabilities,
float *meanValues,
float *featureStdevs,
float *featureBiases,
float *positionBiases,
int softMaxWidth,
int shift,
int signalLength,
float minExpForSum
) ;
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#pragma once
#include <hip/hip_runtime.h>
__global__ void kMultinomialSample(
float *unifRandNums,
float *probabilities,
float *samples,
int softMaxWidth,
int startShift,
int signalLength
) ;
__global__ void kCumulativeSum(
float *probabilities,
float *sumProbabilities,
int softMaxWidth,
int signalLength
) ;
__global__ void kSoftMaxWithOff(
float *activations,
float *probabilities,
float *biases,
int softMaxWidth,
int signalLength,
int numPtsPerThread
) ;
__global__ void kSoftMaxWithOffAndPositionBiases(
float *activations,
float *probabilities,
float *featureBiases,
float *positionBiases,
int softMaxWidth,
int signalLength
) ;
__global__ void kSoftMaxStackApproxWithPositionBiases(
float *activations,
float *probabilities,
float *stdevs,
float *featureBiases,
float *positionBiases,
int softMaxWidth,
int signalLength
) ;
__global__ void kSoftMaxReluWithPositionBiases(
float *activations,
float *probabilities,
float *meanValues,
float *featureStdevs,
float *featureBiases,
float *positionBiases,
int softMaxWidth,
int shift,
int signalLength,
float minExpForSum
) ;
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#pragma once
#include <hip/hip_runtime.h>
__global__ void kMultinomialSample(
float *unifRandNums,
float *probabilities,
float *samples,
int softMaxWidth,
int startShift,
int signalLength
) ;
__global__ void kCumulativeSum(
float *probabilities,
float *sumProbabilities,
int softMaxWidth,
int signalLength
) ;
__global__ void kSoftMaxWithOff(
float *activations,
float *probabilities,
float *biases,
int softMaxWidth,
int signalLength,
int numPtsPerThread
) ;
__global__ void kSoftMaxWithOffAndPositionBiases(
float *activations,
float *probabilities,
float *featureBiases,
float *positionBiases,
int softMaxWidth,
int signalLength
) ;
__global__ void kSoftMaxStackApproxWithPositionBiases(
float *activations,
float *probabilities,
float *stdevs,
float *featureBiases,
float *positionBiases,
int softMaxWidth,
int signalLength
) ;
__global__ void kSoftMaxReluWithPositionBiases(
float *activations,
float *probabilities,
float *meanValues,
float *featureStdevs,
float *featureBiases,
float *positionBiases,
int softMaxWidth,
int shift,
int signalLength,
float minExpForSum
) ;
|
.text
.file "SoftMax_kernels.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000d4387_00000000-6_SoftMax_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14kCumulativeSumPfS_iiPfS_ii
.type _Z38__device_stub__Z14kCumulativeSumPfS_iiPfS_ii, @function
_Z38__device_stub__Z14kCumulativeSumPfS_iiPfS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14kCumulativeSumPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z14kCumulativeSumPfS_iiPfS_ii, .-_Z38__device_stub__Z14kCumulativeSumPfS_iiPfS_ii
.globl _Z14kCumulativeSumPfS_ii
.type _Z14kCumulativeSumPfS_ii, @function
_Z14kCumulativeSumPfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14kCumulativeSumPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14kCumulativeSumPfS_ii, .-_Z14kCumulativeSumPfS_ii
.globl _Z45__device_stub__Z18kMultinomialSamplePfS_S_iiiPfS_S_iii
.type _Z45__device_stub__Z18kMultinomialSamplePfS_S_iiiPfS_S_iii, @function
_Z45__device_stub__Z18kMultinomialSamplePfS_S_iiiPfS_S_iii:
.LFB2053:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18kMultinomialSamplePfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z45__device_stub__Z18kMultinomialSamplePfS_S_iiiPfS_S_iii, .-_Z45__device_stub__Z18kMultinomialSamplePfS_S_iiiPfS_S_iii
.globl _Z18kMultinomialSamplePfS_S_iii
.type _Z18kMultinomialSamplePfS_S_iii, @function
_Z18kMultinomialSamplePfS_S_iii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z18kMultinomialSamplePfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z18kMultinomialSamplePfS_S_iii, .-_Z18kMultinomialSamplePfS_S_iii
.globl _Z67__device_stub__Z37kSoftMaxStackApproxWithPositionBiasesPfS_S_S_S_iiPfS_S_S_S_ii
.type _Z67__device_stub__Z37kSoftMaxStackApproxWithPositionBiasesPfS_S_S_S_iiPfS_S_S_S_ii, @function
_Z67__device_stub__Z37kSoftMaxStackApproxWithPositionBiasesPfS_S_S_S_iiPfS_S_S_S_ii:
.LFB2055:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z37kSoftMaxStackApproxWithPositionBiasesPfS_S_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z67__device_stub__Z37kSoftMaxStackApproxWithPositionBiasesPfS_S_S_S_iiPfS_S_S_S_ii, .-_Z67__device_stub__Z37kSoftMaxStackApproxWithPositionBiasesPfS_S_S_S_iiPfS_S_S_S_ii
.globl _Z37kSoftMaxStackApproxWithPositionBiasesPfS_S_S_S_ii
.type _Z37kSoftMaxStackApproxWithPositionBiasesPfS_S_S_S_ii, @function
_Z37kSoftMaxStackApproxWithPositionBiasesPfS_S_S_S_ii:
.LFB2056:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z67__device_stub__Z37kSoftMaxStackApproxWithPositionBiasesPfS_S_S_S_iiPfS_S_S_S_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z37kSoftMaxStackApproxWithPositionBiasesPfS_S_S_S_ii, .-_Z37kSoftMaxStackApproxWithPositionBiasesPfS_S_S_S_ii
.globl _Z64__device_stub__Z30kSoftMaxReluWithPositionBiasesPfS_S_S_S_S_iiifPfS_S_S_S_S_iiif
.type _Z64__device_stub__Z30kSoftMaxReluWithPositionBiasesPfS_S_S_S_S_iiifPfS_S_S_S_S_iiif, @function
_Z64__device_stub__Z30kSoftMaxReluWithPositionBiasesPfS_S_S_S_S_iiifPfS_S_S_S_S_iiif:
.LFB2057:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 12(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z30kSoftMaxReluWithPositionBiasesPfS_S_S_S_S_iiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z64__device_stub__Z30kSoftMaxReluWithPositionBiasesPfS_S_S_S_S_iiifPfS_S_S_S_S_iiif, .-_Z64__device_stub__Z30kSoftMaxReluWithPositionBiasesPfS_S_S_S_S_iiifPfS_S_S_S_S_iiif
.globl _Z30kSoftMaxReluWithPositionBiasesPfS_S_S_S_S_iiif
.type _Z30kSoftMaxReluWithPositionBiasesPfS_S_S_S_S_iiif, @function
_Z30kSoftMaxReluWithPositionBiasesPfS_S_S_S_S_iiif:
.LFB2058:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z64__device_stub__Z30kSoftMaxReluWithPositionBiasesPfS_S_S_S_S_iiifPfS_S_S_S_S_iiif
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z30kSoftMaxReluWithPositionBiasesPfS_S_S_S_S_iiif, .-_Z30kSoftMaxReluWithPositionBiasesPfS_S_S_S_S_iiif
.globl _Z60__device_stub__Z32kSoftMaxWithOffAndPositionBiasesPfS_S_S_iiPfS_S_S_ii
.type _Z60__device_stub__Z32kSoftMaxWithOffAndPositionBiasesPfS_S_S_iiPfS_S_S_ii, @function
_Z60__device_stub__Z32kSoftMaxWithOffAndPositionBiasesPfS_S_S_iiPfS_S_S_ii:
.LFB2059:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z32kSoftMaxWithOffAndPositionBiasesPfS_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z60__device_stub__Z32kSoftMaxWithOffAndPositionBiasesPfS_S_S_iiPfS_S_S_ii, .-_Z60__device_stub__Z32kSoftMaxWithOffAndPositionBiasesPfS_S_S_iiPfS_S_S_ii
.globl _Z32kSoftMaxWithOffAndPositionBiasesPfS_S_S_ii
.type _Z32kSoftMaxWithOffAndPositionBiasesPfS_S_S_ii, @function
_Z32kSoftMaxWithOffAndPositionBiasesPfS_S_S_ii:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z60__device_stub__Z32kSoftMaxWithOffAndPositionBiasesPfS_S_S_iiPfS_S_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z32kSoftMaxWithOffAndPositionBiasesPfS_S_S_ii, .-_Z32kSoftMaxWithOffAndPositionBiasesPfS_S_S_ii
.globl _Z42__device_stub__Z15kSoftMaxWithOffPfS_S_iiiPfS_S_iii
.type _Z42__device_stub__Z15kSoftMaxWithOffPfS_S_iiiPfS_S_iii, @function
_Z42__device_stub__Z15kSoftMaxWithOffPfS_S_iiiPfS_S_iii:
.LFB2061:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15kSoftMaxWithOffPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z42__device_stub__Z15kSoftMaxWithOffPfS_S_iiiPfS_S_iii, .-_Z42__device_stub__Z15kSoftMaxWithOffPfS_S_iiiPfS_S_iii
.globl _Z15kSoftMaxWithOffPfS_S_iii
.type _Z15kSoftMaxWithOffPfS_S_iii, @function
_Z15kSoftMaxWithOffPfS_S_iii:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15kSoftMaxWithOffPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z15kSoftMaxWithOffPfS_S_iii, .-_Z15kSoftMaxWithOffPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15kSoftMaxWithOffPfS_S_iii"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z32kSoftMaxWithOffAndPositionBiasesPfS_S_S_ii"
.align 8
.LC2:
.string "_Z30kSoftMaxReluWithPositionBiasesPfS_S_S_S_S_iiif"
.align 8
.LC3:
.string "_Z37kSoftMaxStackApproxWithPositionBiasesPfS_S_S_S_ii"
.align 8
.LC4:
.string "_Z18kMultinomialSamplePfS_S_iii"
.section .rodata.str1.1
.LC5:
.string "_Z14kCumulativeSumPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2064:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15kSoftMaxWithOffPfS_S_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z32kSoftMaxWithOffAndPositionBiasesPfS_S_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z30kSoftMaxReluWithPositionBiasesPfS_S_S_S_S_iiif(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z37kSoftMaxStackApproxWithPositionBiasesPfS_S_S_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z18kMultinomialSamplePfS_S_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z14kCumulativeSumPfS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "SoftMax_kernels.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
// ERROR CHECKING MACROS //////////////////////////////////////////////////////
__global__ void createQueryPoints(int noPoints, int noDims, int dimRes, int control, int noControls, int year, float* xmins, float* xmaxes, float* regression, float* queryPts) {
// Global thread index
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx < noPoints) {
// First, deconstruct the index into the index along each dimension
int *dimIdx;
dimIdx = (int*)malloc(noDims*sizeof(int));
int rem = idx;
for (int ii = 0; ii < noDims; ii++) {
int div = (int)(rem/pow(dimRes,noDims-ii-1));
dimIdx[ii] = div;
rem = rem - div*pow(dimRes,noDims-ii-1);
}
// We use the highest and lowest x values for each dimension
// among ALL the controls, not just for this control
// Get the query point coordinates
for (int ii = 0; ii < noDims; ii++) {
// queryPts[idx + ii*noPoints] = ((float)dimIdx[ii])*(xmaxes[
// control*noDims + ii] - xmins[control*noDims + ii])/(
// float)(dimRes-1) + xmins[control*noDims + ii];
queryPts[idx + ii*noPoints] = ((float)dimIdx[ii])*(xmaxes[
noControls*noDims + ii] - xmins[noControls*noDims +
ii])/(float)(dimRes-1) + xmins[noControls*noDims +
ii];
// Save the X value for the query point
regression[year*noControls*(dimRes*noDims + (int)pow(dimRes,
noDims)*2) + control*(dimRes*noDims + (int)pow(dimRes,
noDims)*2) + ii*dimRes + dimIdx[ii]] = queryPts[idx + ii*
noPoints];
}
free(dimIdx);
}
}
|
.file "tmpxft_000bca89_00000000-6_createQueryPoints.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z17createQueryPointsiiiiiiPfS_S_S_iiiiiiPfS_S_S_
.type _Z49__device_stub__Z17createQueryPointsiiiiiiPfS_S_S_iiiiiiPfS_S_S_, @function
_Z49__device_stub__Z17createQueryPointsiiiiiiPfS_S_S_iiiiiiPfS_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movl %edx, 52(%rsp)
movl %ecx, 48(%rsp)
movl %r8d, 44(%rsp)
movl %r9d, 40(%rsp)
movq 240(%rsp), %rax
movq %rax, 32(%rsp)
movq 248(%rsp), %rax
movq %rax, 24(%rsp)
movq 256(%rsp), %rax
movq %rax, 16(%rsp)
movq 264(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rax
movq %rax, 176(%rsp)
leaq 24(%rsp), %rax
movq %rax, 184(%rsp)
leaq 16(%rsp), %rax
movq %rax, 192(%rsp)
leaq 8(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z17createQueryPointsiiiiiiPfS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z17createQueryPointsiiiiiiPfS_S_S_iiiiiiPfS_S_S_, .-_Z49__device_stub__Z17createQueryPointsiiiiiiPfS_S_S_iiiiiiPfS_S_S_
.globl _Z17createQueryPointsiiiiiiPfS_S_S_
.type _Z17createQueryPointsiiiiiiPfS_S_S_, @function
_Z17createQueryPointsiiiiiiPfS_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 40(%rsp)
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z49__device_stub__Z17createQueryPointsiiiiiiPfS_S_S_iiiiiiPfS_S_S_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17createQueryPointsiiiiiiPfS_S_S_, .-_Z17createQueryPointsiiiiiiPfS_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17createQueryPointsiiiiiiPfS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17createQueryPointsiiiiiiPfS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
// ERROR CHECKING MACROS //////////////////////////////////////////////////////
__global__ void createQueryPoints(int noPoints, int noDims, int dimRes, int control, int noControls, int year, float* xmins, float* xmaxes, float* regression, float* queryPts) {
// Global thread index
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx < noPoints) {
// First, deconstruct the index into the index along each dimension
int *dimIdx;
dimIdx = (int*)malloc(noDims*sizeof(int));
int rem = idx;
for (int ii = 0; ii < noDims; ii++) {
int div = (int)(rem/pow(dimRes,noDims-ii-1));
dimIdx[ii] = div;
rem = rem - div*pow(dimRes,noDims-ii-1);
}
// We use the highest and lowest x values for each dimension
// among ALL the controls, not just for this control
// Get the query point coordinates
for (int ii = 0; ii < noDims; ii++) {
// queryPts[idx + ii*noPoints] = ((float)dimIdx[ii])*(xmaxes[
// control*noDims + ii] - xmins[control*noDims + ii])/(
// float)(dimRes-1) + xmins[control*noDims + ii];
queryPts[idx + ii*noPoints] = ((float)dimIdx[ii])*(xmaxes[
noControls*noDims + ii] - xmins[noControls*noDims +
ii])/(float)(dimRes-1) + xmins[noControls*noDims +
ii];
// Save the X value for the query point
regression[year*noControls*(dimRes*noDims + (int)pow(dimRes,
noDims)*2) + control*(dimRes*noDims + (int)pow(dimRes,
noDims)*2) + ii*dimRes + dimIdx[ii]] = queryPts[idx + ii*
noPoints];
}
free(dimIdx);
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
// ERROR CHECKING MACROS //////////////////////////////////////////////////////
__global__ void createQueryPoints(int noPoints, int noDims, int dimRes, int control, int noControls, int year, float* xmins, float* xmaxes, float* regression, float* queryPts) {
// Global thread index
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx < noPoints) {
// First, deconstruct the index into the index along each dimension
int *dimIdx;
dimIdx = (int*)malloc(noDims*sizeof(int));
int rem = idx;
for (int ii = 0; ii < noDims; ii++) {
int div = (int)(rem/pow(dimRes,noDims-ii-1));
dimIdx[ii] = div;
rem = rem - div*pow(dimRes,noDims-ii-1);
}
// We use the highest and lowest x values for each dimension
// among ALL the controls, not just for this control
// Get the query point coordinates
for (int ii = 0; ii < noDims; ii++) {
// queryPts[idx + ii*noPoints] = ((float)dimIdx[ii])*(xmaxes[
// control*noDims + ii] - xmins[control*noDims + ii])/(
// float)(dimRes-1) + xmins[control*noDims + ii];
queryPts[idx + ii*noPoints] = ((float)dimIdx[ii])*(xmaxes[
noControls*noDims + ii] - xmins[noControls*noDims +
ii])/(float)(dimRes-1) + xmins[noControls*noDims +
ii];
// Save the X value for the query point
regression[year*noControls*(dimRes*noDims + (int)pow(dimRes,
noDims)*2) + control*(dimRes*noDims + (int)pow(dimRes,
noDims)*2) + ii*dimRes + dimIdx[ii]] = queryPts[idx + ii*
noPoints];
}
free(dimIdx);
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
// ERROR CHECKING MACROS //////////////////////////////////////////////////////
__global__ void createQueryPoints(int noPoints, int noDims, int dimRes, int control, int noControls, int year, float* xmins, float* xmaxes, float* regression, float* queryPts) {
// Global thread index
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx < noPoints) {
// First, deconstruct the index into the index along each dimension
int *dimIdx;
dimIdx = (int*)malloc(noDims*sizeof(int));
int rem = idx;
for (int ii = 0; ii < noDims; ii++) {
int div = (int)(rem/pow(dimRes,noDims-ii-1));
dimIdx[ii] = div;
rem = rem - div*pow(dimRes,noDims-ii-1);
}
// We use the highest and lowest x values for each dimension
// among ALL the controls, not just for this control
// Get the query point coordinates
for (int ii = 0; ii < noDims; ii++) {
// queryPts[idx + ii*noPoints] = ((float)dimIdx[ii])*(xmaxes[
// control*noDims + ii] - xmins[control*noDims + ii])/(
// float)(dimRes-1) + xmins[control*noDims + ii];
queryPts[idx + ii*noPoints] = ((float)dimIdx[ii])*(xmaxes[
noControls*noDims + ii] - xmins[noControls*noDims +
ii])/(float)(dimRes-1) + xmins[noControls*noDims +
ii];
// Save the X value for the query point
regression[year*noControls*(dimRes*noDims + (int)pow(dimRes,
noDims)*2) + control*(dimRes*noDims + (int)pow(dimRes,
noDims)*2) + ii*dimRes + dimIdx[ii]] = queryPts[idx + ii*
noPoints];
}
free(dimIdx);
}
}
|
.text
.file "createQueryPoints.hip"
.globl _Z32__device_stub__createQueryPointsiiiiiiPfS_S_S_ # -- Begin function _Z32__device_stub__createQueryPointsiiiiiiPfS_S_S_
.p2align 4, 0x90
.type _Z32__device_stub__createQueryPointsiiiiiiPfS_S_S_,@function
_Z32__device_stub__createQueryPointsiiiiiiPfS_S_S_: # @_Z32__device_stub__createQueryPointsiiiiiiPfS_S_S_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 28(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17createQueryPointsiiiiiiPfS_S_S_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z32__device_stub__createQueryPointsiiiiiiPfS_S_S_, .Lfunc_end0-_Z32__device_stub__createQueryPointsiiiiiiPfS_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17createQueryPointsiiiiiiPfS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17createQueryPointsiiiiiiPfS_S_S_,@object # @_Z17createQueryPointsiiiiiiPfS_S_S_
.section .rodata,"a",@progbits
.globl _Z17createQueryPointsiiiiiiPfS_S_S_
.p2align 3, 0x0
_Z17createQueryPointsiiiiiiPfS_S_S_:
.quad _Z32__device_stub__createQueryPointsiiiiiiPfS_S_S_
.size _Z17createQueryPointsiiiiiiPfS_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17createQueryPointsiiiiiiPfS_S_S_"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__createQueryPointsiiiiiiPfS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17createQueryPointsiiiiiiPfS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000bca89_00000000-6_createQueryPoints.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z17createQueryPointsiiiiiiPfS_S_S_iiiiiiPfS_S_S_
.type _Z49__device_stub__Z17createQueryPointsiiiiiiPfS_S_S_iiiiiiPfS_S_S_, @function
_Z49__device_stub__Z17createQueryPointsiiiiiiPfS_S_S_iiiiiiPfS_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movl %edx, 52(%rsp)
movl %ecx, 48(%rsp)
movl %r8d, 44(%rsp)
movl %r9d, 40(%rsp)
movq 240(%rsp), %rax
movq %rax, 32(%rsp)
movq 248(%rsp), %rax
movq %rax, 24(%rsp)
movq 256(%rsp), %rax
movq %rax, 16(%rsp)
movq 264(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rax
movq %rax, 176(%rsp)
leaq 24(%rsp), %rax
movq %rax, 184(%rsp)
leaq 16(%rsp), %rax
movq %rax, 192(%rsp)
leaq 8(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z17createQueryPointsiiiiiiPfS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z17createQueryPointsiiiiiiPfS_S_S_iiiiiiPfS_S_S_, .-_Z49__device_stub__Z17createQueryPointsiiiiiiPfS_S_S_iiiiiiPfS_S_S_
.globl _Z17createQueryPointsiiiiiiPfS_S_S_
.type _Z17createQueryPointsiiiiiiPfS_S_S_, @function
_Z17createQueryPointsiiiiiiPfS_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 40(%rsp)
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z49__device_stub__Z17createQueryPointsiiiiiiPfS_S_S_iiiiiiPfS_S_S_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17createQueryPointsiiiiiiPfS_S_S_, .-_Z17createQueryPointsiiiiiiPfS_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17createQueryPointsiiiiiiPfS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17createQueryPointsiiiiiiPfS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "createQueryPoints.hip"
.globl _Z32__device_stub__createQueryPointsiiiiiiPfS_S_S_ # -- Begin function _Z32__device_stub__createQueryPointsiiiiiiPfS_S_S_
.p2align 4, 0x90
.type _Z32__device_stub__createQueryPointsiiiiiiPfS_S_S_,@function
_Z32__device_stub__createQueryPointsiiiiiiPfS_S_S_: # @_Z32__device_stub__createQueryPointsiiiiiiPfS_S_S_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 28(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17createQueryPointsiiiiiiPfS_S_S_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z32__device_stub__createQueryPointsiiiiiiPfS_S_S_, .Lfunc_end0-_Z32__device_stub__createQueryPointsiiiiiiPfS_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17createQueryPointsiiiiiiPfS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17createQueryPointsiiiiiiPfS_S_S_,@object # @_Z17createQueryPointsiiiiiiPfS_S_S_
.section .rodata,"a",@progbits
.globl _Z17createQueryPointsiiiiiiPfS_S_S_
.p2align 3, 0x0
_Z17createQueryPointsiiiiiiPfS_S_S_:
.quad _Z32__device_stub__createQueryPointsiiiiiiPfS_S_S_
.size _Z17createQueryPointsiiiiiiPfS_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17createQueryPointsiiiiiiPfS_S_S_"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__createQueryPointsiiiiiiPfS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17createQueryPointsiiiiiiPfS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cmath>
|
code for sm_80
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cmath>
|
.file "tmpxft_00166f46_00000000-6_13_matmul.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3671:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3694:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3694:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cmath>
|
#include <stdio.h>
#include <iostream>
#include <hip/hip_runtime.h>
#include <cmath>
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <stdio.h>
#include <iostream>
#include <hip/hip_runtime.h>
#include <cmath>
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <stdio.h>
#include <iostream>
#include <hip/hip_runtime.h>
#include <cmath>
|
.text
.file "13_matmul.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00166f46_00000000-6_13_matmul.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3671:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3694:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3694:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "13_matmul.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void ind2ptr_kernel(const int64_t *ind_data, int64_t *out_data, int64_t M, int64_t numel) {
int64_t thread_idx = blockDim.x * blockIdx.x + threadIdx.x;
if (thread_idx == 0) {
for (int64_t i = 0; i <= ind_data[0]; i++)
out_data[i] = 0;
} else if (thread_idx < numel) {
for (int64_t i = ind_data[thread_idx - 1]; i < ind_data[thread_idx]; i++)
out_data[i + 1] = thread_idx;
} else if (thread_idx == numel) {
for (int64_t i = ind_data[numel - 1] + 1; i < M + 1; i++)
out_data[i] = numel;
}
}
|
code for sm_80
Function : _Z14ind2ptr_kernelPKlPlll
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fe400078e00ff */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff077624 */
/* 0x000fe400078e00ff */
/*0060*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0070*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0080*/ @!P0 BRA 0xa00 ; /* 0x0000097000008947 */
/* 0x000fea0003800000 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fc80003f06070 */
/*00a0*/ ISETP.GE.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f06300 */
/*00b0*/ @!P0 BRA 0x860 ; /* 0x000007a000008947 */
/* 0x000fea0003800000 */
/*00c0*/ ISETP.NE.U32.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fc80003f05070 */
/*00d0*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f05300 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ ULDC.64 UR6, c[0x0][0x178] ; /* 0x00005e0000067ab9 */
/* 0x000fe40000000a00 */
/*0100*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000a00 */
/*0110*/ ULEA UR4, UP0, UR6, UR4, 0x3 ; /* 0x0000000406047291 */
/* 0x000fc8000f80183f */
/*0120*/ ULEA.HI.X UR5, UR6, UR5, UR7, 0x3, UP0 ; /* 0x0000000506057291 */
/* 0x000fe400080f1c07 */
/*0130*/ IMAD.U32 R2, RZ, RZ, UR4 ; /* 0x00000004ff027e24 */
/* 0x000fc8000f8e00ff */
/*0140*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x000fca000f8e00ff */
/*0150*/ LDG.E.64 R4, [R2.64+-0x8] ; /* 0xfffff80802047981 */
/* 0x000ea4000c1e1b00 */
/*0160*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x004fc80003f06070 */
/*0170*/ ISETP.GE.AND.EX P0, PT, R5, c[0x0][0x174], PT, P0 ; /* 0x00005d0005007a0c */
/* 0x000fda0003f06300 */
/*0180*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0190*/ IADD3 R3, -R4, c[0x0][0x170], RZ ; /* 0x00005c0004037a10 */
/* 0x000fe20007ffe1ff */
/*01a0*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0004 */
/*01b0*/ LOP3.LUT R0, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff007212 */
/* 0x000fe200078e33ff */
/*01c0*/ IMAD.MOV.U32 R10, RZ, RZ, R5 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0005 */
/*01d0*/ LOP3.LUT R3, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303037812 */
/* 0x000fe400078ec0ff */
/*01e0*/ IADD3 R0, P2, R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a10 */
/* 0x000fe40007f5e0ff */
/*01f0*/ ISETP.NE.U32.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f25070 */
/*0200*/ LOP3.LUT R2, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff027212 */
/* 0x000fc400078e33ff */
/*0210*/ ISETP.NE.AND.EX P1, PT, RZ, RZ, PT, P1 ; /* 0x000000ffff00720c */
/* 0x000fe40003f25310 */
/*0220*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f06070 */
/*0230*/ IADD3.X R0, R2, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0002007a10 */
/* 0x000fc800017fe4ff */
/*0240*/ ISETP.GE.U32.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fca0003f06100 */
/*0250*/ @!P1 BRA 0x3c0 ; /* 0x0000016000009947 */
/* 0x000ff00003800000 */
/*0260*/ LEA R7, P1, R4.reuse, c[0x0][0x168], 0x3 ; /* 0x00005a0004077a11 */
/* 0x040fe200078218ff */
/*0270*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0004 */
/*0280*/ IADD3 R0, P3, RZ, -R3, RZ ; /* 0x80000003ff007210 */
/* 0x000fe20007f7e0ff */
/*0290*/ IMAD.MOV.U32 R10, RZ, RZ, R5.reuse ; /* 0x000000ffff0a7224 */
/* 0x100fe200078e0005 */
/*02a0*/ IADD3 R7, P2, R7, 0x8, RZ ; /* 0x0000000807077810 */
/* 0x000fe40007f5e0ff */
/*02b0*/ LEA.HI.X R8, R4, c[0x0][0x16c], R5, 0x3, P1 ; /* 0x00005b0004087a11 */
/* 0x000fe200008f1c05 */
/*02c0*/ IMAD.X R6, RZ, RZ, -0x1, P3 ; /* 0xffffffffff067424 */
/* 0x000fc800018e06ff */
/*02d0*/ IMAD.X R8, RZ, RZ, R8, P2 ; /* 0x000000ffff087224 */
/* 0x000fe400010e0608 */
/*02e0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe200078e00ff */
/*02f0*/ IADD3 R0, P1, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007f3e0ff */
/*0300*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fe200078e00ff */
/*0310*/ IADD3 R9, P2, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe20007f5e0ff */
/*0320*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0007 */
/*0330*/ IADD3 R7, P3, R7, 0x8, RZ ; /* 0x0000000807077810 */
/* 0x000fe20007f7e0ff */
/*0340*/ IMAD.MOV.U32 R3, RZ, RZ, R8 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0008 */
/*0350*/ IMAD.X R6, RZ, RZ, R6, P1 ; /* 0x000000ffff067224 */
/* 0x000fe200008e0606 */
/*0360*/ ISETP.NE.U32.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f25070 */
/*0370*/ IMAD.X R10, RZ, RZ, R10, P2 ; /* 0x000000ffff0a7224 */
/* 0x000fe200010e060a */
/*0380*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0001e2000c101b08 */
/*0390*/ IMAD.X R8, RZ, RZ, R8, P3 ; /* 0x000000ffff087224 */
/* 0x000fe200018e0608 */
/*03a0*/ ISETP.NE.AND.EX P1, PT, R6, RZ, PT, P1 ; /* 0x000000ff0600720c */
/* 0x000fda0003f25310 */
/*03b0*/ @P1 BRA 0x2e0 ; /* 0xffffff2000001947 */
/* 0x001fea000383ffff */
/*03c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*03d0*/ IADD3 R0, P2, -R9.reuse, c[0x0][0x170], RZ ; /* 0x00005c0009007a10 */
/* 0x040fe40007f5e1ff */
/*03e0*/ LEA R2, P0, R9, c[0x0][0x168], 0x3 ; /* 0x00005a0009027a11 */
/* 0x000fe400078018ff */
/*03f0*/ ISETP.GT.U32.AND P1, PT, R0, 0xc, PT ; /* 0x0000000c0000780c */
/* 0x000fe40003f24070 */
/*0400*/ IADD3.X R0, ~R10, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d000a007a10 */
/* 0x000fe400017fe5ff */
/*0410*/ IADD3 R2, P2, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x000fe40007f5e0ff */
/*0420*/ ISETP.GT.AND.EX P1, PT, R0, RZ, PT, P1 ; /* 0x000000ff0000720c */
/* 0x000fc40003f24310 */
/*0430*/ LEA.HI.X R3, R9, c[0x0][0x16c], R10, 0x3, P0 ; /* 0x00005b0009037a11 */
/* 0x000fe400000f1c0a */
/*0440*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fc60003f0f070 */
/*0450*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fcc00010e0603 */
/*0460*/ @!P1 BRA 0x660 ; /* 0x000001f000009947 */
/* 0x000fea0003800000 */
/*0470*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000a00 */
/*0480*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0490*/ UIADD3 UR4, UP0, UR4, -0xc, URZ ; /* 0xfffffff404047890 */
/* 0x000fc8000ff1e03f */
/*04a0*/ UIADD3.X UR5, UR5, -0x1, URZ, UP0, !UPT ; /* 0xffffffff05057890 */
/* 0x000fe400087fe43f */
/*04b0*/ IADD3 R9, P1, R9, 0x10, RZ ; /* 0x0000001009097810 */
/* 0x000fe20007f3e0ff */
/*04c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe200078e00ff */
/*04d0*/ IADD3 R0, P2, R2, 0x80, RZ ; /* 0x0000008002007810 */
/* 0x000fe20007f5e0ff */
/*04e0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fe400078e00ff */
/*04f0*/ IMAD.X R10, RZ, RZ, R10, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fe200008e060a */
/*0500*/ ISETP.GE.U32.AND P1, PT, R9, UR4, PT ; /* 0x0000000409007c0c */
/* 0x000fe2000bf26070 */
/*0510*/ IMAD.X R7, RZ, RZ, R3, P2 ; /* 0x000000ffff077224 */
/* 0x000fe200010e0603 */
/*0520*/ STG.E.64 [R2.64+-0x18], R4 ; /* 0xffffe80402007986 */
/* 0x000fe4000c101b08 */
/*0530*/ ISETP.GE.AND.EX P1, PT, R10, UR5, PT, P1 ; /* 0x000000050a007c0c */
/* 0x000fc4000bf26310 */
/*0540*/ STG.E.64 [R2.64+-0x10], R4 ; /* 0xfffff00402007986 */
/* 0x000fe8000c101b08 */
/*0550*/ STG.E.64 [R2.64+-0x8], R4 ; /* 0xfffff80402007986 */
/* 0x000fe8000c101b08 */
/*0560*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe8000c101b08 */
/*0570*/ STG.E.64 [R2.64+0x8], R4 ; /* 0x0000080402007986 */
/* 0x000fe8000c101b08 */
/*0580*/ STG.E.64 [R2.64+0x10], R4 ; /* 0x0000100402007986 */
/* 0x000fe8000c101b08 */
/*0590*/ STG.E.64 [R2.64+0x18], R4 ; /* 0x0000180402007986 */
/* 0x000fe8000c101b08 */
/*05a0*/ STG.E.64 [R2.64+0x20], R4 ; /* 0x0000200402007986 */
/* 0x000fe8000c101b08 */
/*05b0*/ STG.E.64 [R2.64+0x28], R4 ; /* 0x0000280402007986 */
/* 0x000fe8000c101b08 */
/*05c0*/ STG.E.64 [R2.64+0x30], R4 ; /* 0x0000300402007986 */
/* 0x000fe8000c101b08 */
/*05d0*/ STG.E.64 [R2.64+0x38], R4 ; /* 0x0000380402007986 */
/* 0x000fe8000c101b08 */
/*05e0*/ STG.E.64 [R2.64+0x40], R4 ; /* 0x0000400402007986 */
/* 0x000fe8000c101b08 */
/*05f0*/ STG.E.64 [R2.64+0x48], R4 ; /* 0x0000480402007986 */
/* 0x000fe8000c101b08 */
/*0600*/ STG.E.64 [R2.64+0x50], R4 ; /* 0x0000500402007986 */
/* 0x000fe8000c101b08 */
/*0610*/ STG.E.64 [R2.64+0x58], R4 ; /* 0x0000580402007986 */
/* 0x000fe8000c101b08 */
/*0620*/ STG.E.64 [R2.64+0x60], R4 ; /* 0x0000600402007986 */
/* 0x0001e4000c101b08 */
/*0630*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0000 */
/*0640*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0007 */
/*0650*/ @!P1 BRA 0x4b0 ; /* 0xfffffe5000009947 */
/* 0x000fea000383ffff */
/*0660*/ IADD3 R0, P2, -R9, c[0x0][0x170], RZ ; /* 0x00005c0009007a10 */
/* 0x000fc80007f5e1ff */
/*0670*/ ISETP.GT.U32.AND P1, PT, R0, 0x4, PT ; /* 0x000000040000780c */
/* 0x000fe40003f24070 */
/*0680*/ IADD3.X R0, ~R10, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d000a007a10 */
/* 0x000fc800017fe5ff */
/*0690*/ ISETP.GT.AND.EX P1, PT, R0, RZ, PT, P1 ; /* 0x000000ff0000720c */
/* 0x000fda0003f24310 */
/*06a0*/ @!P1 BRA 0x7c0 ; /* 0x0000011000009947 */
/* 0x000fea0003800000 */
/*06b0*/ IADD3 R0, P1, R2, 0x40, RZ ; /* 0x0000004002007810 */
/* 0x000fe20007f3e0ff */
/*06c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe200078e00ff */
/*06d0*/ IADD3 R9, P2, R9, 0x8, RZ ; /* 0x0000000809097810 */
/* 0x000fe20007f5e0ff */
/*06e0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fe200078e00ff */
/*06f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0700*/ IMAD.X R7, RZ, RZ, R3, P1 ; /* 0x000000ffff077224 */
/* 0x000fe400008e0603 */
/*0710*/ IMAD.X R10, RZ, RZ, R10, P2 ; /* 0x000000ffff0a7224 */
/* 0x000fe200010e060a */
/*0720*/ STG.E.64 [R2.64+-0x18], R4 ; /* 0xffffe80402007986 */
/* 0x000fe8000c101b08 */
/*0730*/ STG.E.64 [R2.64+-0x10], R4 ; /* 0xfffff00402007986 */
/* 0x000fe8000c101b08 */
/*0740*/ STG.E.64 [R2.64+-0x8], R4 ; /* 0xfffff80402007986 */
/* 0x000fe8000c101b08 */
/*0750*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe8000c101b08 */
/*0760*/ STG.E.64 [R2.64+0x8], R4 ; /* 0x0000080402007986 */
/* 0x000fe8000c101b08 */
/*0770*/ STG.E.64 [R2.64+0x10], R4 ; /* 0x0000100402007986 */
/* 0x000fe8000c101b08 */
/*0780*/ STG.E.64 [R2.64+0x18], R4 ; /* 0x0000180402007986 */
/* 0x000fe8000c101b08 */
/*0790*/ STG.E.64 [R2.64+0x20], R4 ; /* 0x0000200402007986 */
/* 0x0001e4000c101b08 */
/*07a0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0000 */
/*07b0*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0007 */
/*07c0*/ ISETP.LT.U32.AND P1, PT, R9, c[0x0][0x170], PT ; /* 0x00005c0009007a0c */
/* 0x000fc80003f21070 */
/*07d0*/ ISETP.LT.OR.EX P0, PT, R10, c[0x0][0x174], P0, P1 ; /* 0x00005d000a007a0c */
/* 0x000fda0000701710 */
/*07e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*07f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe400078e00ff */
/*0800*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fca00078e00ff */
/*0810*/ STG.E.64 [R2.64+-0x18], R4 ; /* 0xffffe80402007986 */
/* 0x000fe8000c101b08 */
/*0820*/ STG.E.64 [R2.64+-0x10], R4 ; /* 0xfffff00402007986 */
/* 0x000fe8000c101b08 */
/*0830*/ STG.E.64 [R2.64+-0x8], R4 ; /* 0xfffff80402007986 */
/* 0x000fe8000c101b08 */
/*0840*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b08 */
/*0850*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0860*/ LEA R2, P0, R6, c[0x0][0x160], 0x3 ; /* 0x0000580006027a11 */
/* 0x000fc800078018ff */
/*0870*/ LEA.HI.X R3, R6, c[0x0][0x164], RZ, 0x3, P0 ; /* 0x0000590006037a11 */
/* 0x000fca00000f1cff */
/*0880*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000802047981 */
/* 0x000ea8000c1e1b00 */
/*0890*/ LDG.E.64 R8, [R2.64+-0x8] ; /* 0xfffff80802087981 */
/* 0x000ea4000c1e1b00 */
/*08a0*/ ISETP.GE.U32.AND P0, PT, R8, R4, PT ; /* 0x000000040800720c */
/* 0x004fc80003f06070 */
/*08b0*/ ISETP.GE.AND.EX P0, PT, R9, R5, PT, P0 ; /* 0x000000050900720c */
/* 0x000fda0003f06300 */
/*08c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*08d0*/ IMAD.MOV.U32 R13, RZ, RZ, R8 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0008 */
/*08e0*/ IMAD.MOV.U32 R10, RZ, RZ, R9 ; /* 0x000000ffff0a7224 */
/* 0x000fc600078e0009 */
/*08f0*/ LEA R0, P0, R13, c[0x0][0x168], 0x3 ; /* 0x00005a000d007a11 */
/* 0x000fc800078018ff */
/*0900*/ IADD3 R0, P1, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fe40007f3e0ff */
/*0910*/ LEA.HI.X R11, R13, c[0x0][0x16c], R10, 0x3, P0 ; /* 0x00005b000d0b7a11 */
/* 0x000fca00000f1c0a */
/*0920*/ IMAD.X R11, RZ, RZ, R11, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fe400008e060b */
/*0930*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*0940*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0000 */
/*0950*/ IMAD.MOV.U32 R9, RZ, RZ, R11 ; /* 0x000000ffff097224 */
/* 0x000fca00078e000b */
/*0960*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x0001e8000c101b08 */
/*0970*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000802047981 */
/* 0x000ea2000c1e1b00 */
/*0980*/ IADD3 R13, P0, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fe40007f1e0ff */
/*0990*/ IADD3 R0, P1, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fc60007f3e0ff */
/*09a0*/ IMAD.X R10, RZ, RZ, R10, P0 ; /* 0x000000ffff0a7224 */
/* 0x000fe400000e060a */
/*09b0*/ IMAD.X R11, RZ, RZ, R11, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fe200008e060b */
/*09c0*/ ISETP.GE.U32.AND P0, PT, R13, R4, PT ; /* 0x000000040d00720c */
/* 0x004fc80003f06070 */
/*09d0*/ ISETP.GE.AND.EX P0, PT, R10, R5, PT, P0 ; /* 0x000000050a00720c */
/* 0x000fda0003f06300 */
/*09e0*/ @!P0 BRA 0x930 ; /* 0xffffff4000008947 */
/* 0x001fea000383ffff */
/*09f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a00*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe400078e00ff */
/*0a10*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*0a20*/ LDG.E R4, [R2.64+0x4] ; /* 0x0000040802047981 */
/* 0x000ea4000c1e1900 */
/*0a30*/ ISETP.GE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x004fda0003f06270 */
/*0a40*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0a50*/ UMOV UR4, 0xffffffff ; /* 0xffffffff00047882 */
/* 0x000fe40000000000 */
/*0a60*/ UMOV UR5, 0xffffffff ; /* 0xffffffff00057882 */
/* 0x000fe40000000000 */
/*0a70*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fca00078e0000 */
/*0a80*/ STG.E.64 [R6.64], RZ ; /* 0x000000ff06007986 */
/* 0x0001e8000c101b08 */
/*0a90*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000802047981 */
/* 0x000ea2000c1e1b00 */
/*0aa0*/ UIADD3 UR4, UP0, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000ff1e03f */
/*0ab0*/ IADD3 R0, P1, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fc60007f3e0ff */
/*0ac0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*0ad0*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x001fc800008e0607 */
/*0ae0*/ IMAD.U32 R9, RZ, RZ, UR5 ; /* 0x00000005ff097e24 */
/* 0x000fe2000f8e00ff */
/*0af0*/ ISETP.LE.U32.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x004fc8000bf03070 */
/*0b00*/ ISETP.GE.AND.EX P0, PT, R9, R5, PT, P0 ; /* 0x000000050900720c */
/* 0x000fda0003f06300 */
/*0b10*/ @!P0 BRA 0xa70 ; /* 0xffffff5000008947 */
/* 0x000fea000383ffff */
/*0b20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b30*/ BRA 0xb30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void ind2ptr_kernel(const int64_t *ind_data, int64_t *out_data, int64_t M, int64_t numel) {
int64_t thread_idx = blockDim.x * blockIdx.x + threadIdx.x;
if (thread_idx == 0) {
for (int64_t i = 0; i <= ind_data[0]; i++)
out_data[i] = 0;
} else if (thread_idx < numel) {
for (int64_t i = ind_data[thread_idx - 1]; i < ind_data[thread_idx]; i++)
out_data[i + 1] = thread_idx;
} else if (thread_idx == numel) {
for (int64_t i = ind_data[numel - 1] + 1; i < M + 1; i++)
out_data[i] = numel;
}
}
|
.file "tmpxft_0012ca29_00000000-6_ind2ptr_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z14ind2ptr_kernelPKlPlllPKlPlll
.type _Z39__device_stub__Z14ind2ptr_kernelPKlPlllPKlPlll, @function
_Z39__device_stub__Z14ind2ptr_kernelPKlPlllPKlPlll:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14ind2ptr_kernelPKlPlll(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z14ind2ptr_kernelPKlPlllPKlPlll, .-_Z39__device_stub__Z14ind2ptr_kernelPKlPlllPKlPlll
.globl _Z14ind2ptr_kernelPKlPlll
.type _Z14ind2ptr_kernelPKlPlll, @function
_Z14ind2ptr_kernelPKlPlll:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14ind2ptr_kernelPKlPlllPKlPlll
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14ind2ptr_kernelPKlPlll, .-_Z14ind2ptr_kernelPKlPlll
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14ind2ptr_kernelPKlPlll"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14ind2ptr_kernelPKlPlll(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void ind2ptr_kernel(const int64_t *ind_data, int64_t *out_data, int64_t M, int64_t numel) {
int64_t thread_idx = blockDim.x * blockIdx.x + threadIdx.x;
if (thread_idx == 0) {
for (int64_t i = 0; i <= ind_data[0]; i++)
out_data[i] = 0;
} else if (thread_idx < numel) {
for (int64_t i = ind_data[thread_idx - 1]; i < ind_data[thread_idx]; i++)
out_data[i + 1] = thread_idx;
} else if (thread_idx == numel) {
for (int64_t i = ind_data[numel - 1] + 1; i < M + 1; i++)
out_data[i] = numel;
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ind2ptr_kernel(const int64_t *ind_data, int64_t *out_data, int64_t M, int64_t numel) {
int64_t thread_idx = blockDim.x * blockIdx.x + threadIdx.x;
if (thread_idx == 0) {
for (int64_t i = 0; i <= ind_data[0]; i++)
out_data[i] = 0;
} else if (thread_idx < numel) {
for (int64_t i = ind_data[thread_idx - 1]; i < ind_data[thread_idx]; i++)
out_data[i + 1] = thread_idx;
} else if (thread_idx == numel) {
for (int64_t i = ind_data[numel - 1] + 1; i < M + 1; i++)
out_data[i] = numel;
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ind2ptr_kernel(const int64_t *ind_data, int64_t *out_data, int64_t M, int64_t numel) {
int64_t thread_idx = blockDim.x * blockIdx.x + threadIdx.x;
if (thread_idx == 0) {
for (int64_t i = 0; i <= ind_data[0]; i++)
out_data[i] = 0;
} else if (thread_idx < numel) {
for (int64_t i = ind_data[thread_idx - 1]; i < ind_data[thread_idx]; i++)
out_data[i + 1] = thread_idx;
} else if (thread_idx == numel) {
for (int64_t i = ind_data[numel - 1] + 1; i < M + 1; i++)
out_data[i] = numel;
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14ind2ptr_kernelPKlPlll
.globl _Z14ind2ptr_kernelPKlPlll
.p2align 8
.type _Z14ind2ptr_kernelPKlPlll,@function
_Z14ind2ptr_kernelPKlPlll:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_xor_b32 s10, exec_lo, s2
s_cbranch_execz .LBB0_13
s_load_b64 s[2:3], s[0:1], 0x18
v_mov_b32_e32 v2, 0
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_le_i64_e64 s[2:3], v[1:2]
s_xor_b32 s11, exec_lo, s8
s_cbranch_execz .LBB0_7
s_mov_b32 s12, exec_lo
v_cmpx_eq_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_6
s_lshl_b64 s[8:9], s[2:3], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s8, s4, s8
s_addc_u32 s9, s5, s9
s_add_u32 s8, s8, -8
s_addc_u32 s9, s9, -1
s_load_b64 s[0:1], s[0:1], 0x10
s_load_b64 s[8:9], s[8:9], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_ge_i64_e64 s13, s[8:9], s[0:1]
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s13
s_cbranch_vccnz .LBB0_6
s_lshl_b64 s[14:15], s[8:9], 3
v_mov_b32_e32 v0, s2
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
s_add_u32 s13, s14, s6
s_addc_u32 s3, s15, s7
s_add_u32 s2, s13, 8
s_addc_u32 s3, s3, 0
.LBB0_5:
s_add_u32 s8, s8, 1
s_addc_u32 s9, s9, 0
global_store_b64 v2, v[0:1], s[2:3]
v_cmp_lt_i64_e64 s13, s[8:9], s[0:1]
s_add_u32 s2, s2, 8
s_addc_u32 s3, s3, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s13
s_cbranch_vccnz .LBB0_5
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s12
.LBB0_7:
s_and_not1_saveexec_b32 s1, s11
s_cbranch_execz .LBB0_12
v_lshlrev_b64 v[3:4], 3, v[1:2]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_clause 0x1
global_load_b64 v[5:6], v[3:4], off offset:-8
global_load_b64 v[7:8], v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i64_e64 v[5:6], v[7:8]
s_cbranch_execz .LBB0_11
v_lshlrev_b64 v[7:8], 3, v[5:6]
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v7, s6
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v0, 8
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB0_10:
global_store_b64 v[7:8], v[1:2], off
global_load_b64 v[9:10], v[3:4], off
v_add_co_u32 v5, vcc_lo, v5, 1
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_add_co_u32 v7, s0, v7, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v8, s0, 0, v8, s0
s_waitcnt vmcnt(0)
v_cmp_ge_i64_e32 vcc_lo, v[5:6], v[9:10]
s_or_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_10
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_12:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
.LBB0_13:
s_and_not1_saveexec_b32 s0, s10
s_cbranch_execz .LBB0_17
v_mov_b32_e32 v2, 0
global_load_b64 v[0:1], v2, s[4:5]
s_waitcnt vmcnt(0)
v_cmp_gt_i64_e32 vcc_lo, 0, v[0:1]
s_cbranch_vccnz .LBB0_17
v_mov_b32_e32 v0, 0
s_mov_b64 s[0:1], -1
.LBB0_16:
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v1, v0
s_add_u32 s0, s0, 1
s_addc_u32 s1, s1, 0
global_store_b64 v2, v[0:1], s[6:7]
global_load_b64 v[3:4], v2, s[4:5]
s_add_u32 s6, s6, 8
s_addc_u32 s7, s7, 0
s_waitcnt vmcnt(0)
v_cmp_ge_i64_e32 vcc_lo, s[0:1], v[3:4]
s_cbranch_vccz .LBB0_16
.LBB0_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14ind2ptr_kernelPKlPlll
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14ind2ptr_kernelPKlPlll, .Lfunc_end0-_Z14ind2ptr_kernelPKlPlll
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14ind2ptr_kernelPKlPlll
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14ind2ptr_kernelPKlPlll.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ind2ptr_kernel(const int64_t *ind_data, int64_t *out_data, int64_t M, int64_t numel) {
int64_t thread_idx = blockDim.x * blockIdx.x + threadIdx.x;
if (thread_idx == 0) {
for (int64_t i = 0; i <= ind_data[0]; i++)
out_data[i] = 0;
} else if (thread_idx < numel) {
for (int64_t i = ind_data[thread_idx - 1]; i < ind_data[thread_idx]; i++)
out_data[i + 1] = thread_idx;
} else if (thread_idx == numel) {
for (int64_t i = ind_data[numel - 1] + 1; i < M + 1; i++)
out_data[i] = numel;
}
}
|
.text
.file "ind2ptr_kernel.hip"
.globl _Z29__device_stub__ind2ptr_kernelPKlPlll # -- Begin function _Z29__device_stub__ind2ptr_kernelPKlPlll
.p2align 4, 0x90
.type _Z29__device_stub__ind2ptr_kernelPKlPlll,@function
_Z29__device_stub__ind2ptr_kernelPKlPlll: # @_Z29__device_stub__ind2ptr_kernelPKlPlll
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14ind2ptr_kernelPKlPlll, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__ind2ptr_kernelPKlPlll, .Lfunc_end0-_Z29__device_stub__ind2ptr_kernelPKlPlll
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14ind2ptr_kernelPKlPlll, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14ind2ptr_kernelPKlPlll,@object # @_Z14ind2ptr_kernelPKlPlll
.section .rodata,"a",@progbits
.globl _Z14ind2ptr_kernelPKlPlll
.p2align 3, 0x0
_Z14ind2ptr_kernelPKlPlll:
.quad _Z29__device_stub__ind2ptr_kernelPKlPlll
.size _Z14ind2ptr_kernelPKlPlll, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14ind2ptr_kernelPKlPlll"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__ind2ptr_kernelPKlPlll
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14ind2ptr_kernelPKlPlll
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z14ind2ptr_kernelPKlPlll
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fe400078e00ff */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff077624 */
/* 0x000fe400078e00ff */
/*0060*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0070*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0080*/ @!P0 BRA 0xa00 ; /* 0x0000097000008947 */
/* 0x000fea0003800000 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fc80003f06070 */
/*00a0*/ ISETP.GE.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f06300 */
/*00b0*/ @!P0 BRA 0x860 ; /* 0x000007a000008947 */
/* 0x000fea0003800000 */
/*00c0*/ ISETP.NE.U32.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fc80003f05070 */
/*00d0*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f05300 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ ULDC.64 UR6, c[0x0][0x178] ; /* 0x00005e0000067ab9 */
/* 0x000fe40000000a00 */
/*0100*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000a00 */
/*0110*/ ULEA UR4, UP0, UR6, UR4, 0x3 ; /* 0x0000000406047291 */
/* 0x000fc8000f80183f */
/*0120*/ ULEA.HI.X UR5, UR6, UR5, UR7, 0x3, UP0 ; /* 0x0000000506057291 */
/* 0x000fe400080f1c07 */
/*0130*/ IMAD.U32 R2, RZ, RZ, UR4 ; /* 0x00000004ff027e24 */
/* 0x000fc8000f8e00ff */
/*0140*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x000fca000f8e00ff */
/*0150*/ LDG.E.64 R4, [R2.64+-0x8] ; /* 0xfffff80802047981 */
/* 0x000ea4000c1e1b00 */
/*0160*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x004fc80003f06070 */
/*0170*/ ISETP.GE.AND.EX P0, PT, R5, c[0x0][0x174], PT, P0 ; /* 0x00005d0005007a0c */
/* 0x000fda0003f06300 */
/*0180*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0190*/ IADD3 R3, -R4, c[0x0][0x170], RZ ; /* 0x00005c0004037a10 */
/* 0x000fe20007ffe1ff */
/*01a0*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0004 */
/*01b0*/ LOP3.LUT R0, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff007212 */
/* 0x000fe200078e33ff */
/*01c0*/ IMAD.MOV.U32 R10, RZ, RZ, R5 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0005 */
/*01d0*/ LOP3.LUT R3, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303037812 */
/* 0x000fe400078ec0ff */
/*01e0*/ IADD3 R0, P2, R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a10 */
/* 0x000fe40007f5e0ff */
/*01f0*/ ISETP.NE.U32.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f25070 */
/*0200*/ LOP3.LUT R2, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff027212 */
/* 0x000fc400078e33ff */
/*0210*/ ISETP.NE.AND.EX P1, PT, RZ, RZ, PT, P1 ; /* 0x000000ffff00720c */
/* 0x000fe40003f25310 */
/*0220*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f06070 */
/*0230*/ IADD3.X R0, R2, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0002007a10 */
/* 0x000fc800017fe4ff */
/*0240*/ ISETP.GE.U32.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fca0003f06100 */
/*0250*/ @!P1 BRA 0x3c0 ; /* 0x0000016000009947 */
/* 0x000ff00003800000 */
/*0260*/ LEA R7, P1, R4.reuse, c[0x0][0x168], 0x3 ; /* 0x00005a0004077a11 */
/* 0x040fe200078218ff */
/*0270*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0004 */
/*0280*/ IADD3 R0, P3, RZ, -R3, RZ ; /* 0x80000003ff007210 */
/* 0x000fe20007f7e0ff */
/*0290*/ IMAD.MOV.U32 R10, RZ, RZ, R5.reuse ; /* 0x000000ffff0a7224 */
/* 0x100fe200078e0005 */
/*02a0*/ IADD3 R7, P2, R7, 0x8, RZ ; /* 0x0000000807077810 */
/* 0x000fe40007f5e0ff */
/*02b0*/ LEA.HI.X R8, R4, c[0x0][0x16c], R5, 0x3, P1 ; /* 0x00005b0004087a11 */
/* 0x000fe200008f1c05 */
/*02c0*/ IMAD.X R6, RZ, RZ, -0x1, P3 ; /* 0xffffffffff067424 */
/* 0x000fc800018e06ff */
/*02d0*/ IMAD.X R8, RZ, RZ, R8, P2 ; /* 0x000000ffff087224 */
/* 0x000fe400010e0608 */
/*02e0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe200078e00ff */
/*02f0*/ IADD3 R0, P1, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007f3e0ff */
/*0300*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fe200078e00ff */
/*0310*/ IADD3 R9, P2, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe20007f5e0ff */
/*0320*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0007 */
/*0330*/ IADD3 R7, P3, R7, 0x8, RZ ; /* 0x0000000807077810 */
/* 0x000fe20007f7e0ff */
/*0340*/ IMAD.MOV.U32 R3, RZ, RZ, R8 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0008 */
/*0350*/ IMAD.X R6, RZ, RZ, R6, P1 ; /* 0x000000ffff067224 */
/* 0x000fe200008e0606 */
/*0360*/ ISETP.NE.U32.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f25070 */
/*0370*/ IMAD.X R10, RZ, RZ, R10, P2 ; /* 0x000000ffff0a7224 */
/* 0x000fe200010e060a */
/*0380*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0001e2000c101b08 */
/*0390*/ IMAD.X R8, RZ, RZ, R8, P3 ; /* 0x000000ffff087224 */
/* 0x000fe200018e0608 */
/*03a0*/ ISETP.NE.AND.EX P1, PT, R6, RZ, PT, P1 ; /* 0x000000ff0600720c */
/* 0x000fda0003f25310 */
/*03b0*/ @P1 BRA 0x2e0 ; /* 0xffffff2000001947 */
/* 0x001fea000383ffff */
/*03c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*03d0*/ IADD3 R0, P2, -R9.reuse, c[0x0][0x170], RZ ; /* 0x00005c0009007a10 */
/* 0x040fe40007f5e1ff */
/*03e0*/ LEA R2, P0, R9, c[0x0][0x168], 0x3 ; /* 0x00005a0009027a11 */
/* 0x000fe400078018ff */
/*03f0*/ ISETP.GT.U32.AND P1, PT, R0, 0xc, PT ; /* 0x0000000c0000780c */
/* 0x000fe40003f24070 */
/*0400*/ IADD3.X R0, ~R10, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d000a007a10 */
/* 0x000fe400017fe5ff */
/*0410*/ IADD3 R2, P2, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x000fe40007f5e0ff */
/*0420*/ ISETP.GT.AND.EX P1, PT, R0, RZ, PT, P1 ; /* 0x000000ff0000720c */
/* 0x000fc40003f24310 */
/*0430*/ LEA.HI.X R3, R9, c[0x0][0x16c], R10, 0x3, P0 ; /* 0x00005b0009037a11 */
/* 0x000fe400000f1c0a */
/*0440*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fc60003f0f070 */
/*0450*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fcc00010e0603 */
/*0460*/ @!P1 BRA 0x660 ; /* 0x000001f000009947 */
/* 0x000fea0003800000 */
/*0470*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000a00 */
/*0480*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0490*/ UIADD3 UR4, UP0, UR4, -0xc, URZ ; /* 0xfffffff404047890 */
/* 0x000fc8000ff1e03f */
/*04a0*/ UIADD3.X UR5, UR5, -0x1, URZ, UP0, !UPT ; /* 0xffffffff05057890 */
/* 0x000fe400087fe43f */
/*04b0*/ IADD3 R9, P1, R9, 0x10, RZ ; /* 0x0000001009097810 */
/* 0x000fe20007f3e0ff */
/*04c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe200078e00ff */
/*04d0*/ IADD3 R0, P2, R2, 0x80, RZ ; /* 0x0000008002007810 */
/* 0x000fe20007f5e0ff */
/*04e0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fe400078e00ff */
/*04f0*/ IMAD.X R10, RZ, RZ, R10, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fe200008e060a */
/*0500*/ ISETP.GE.U32.AND P1, PT, R9, UR4, PT ; /* 0x0000000409007c0c */
/* 0x000fe2000bf26070 */
/*0510*/ IMAD.X R7, RZ, RZ, R3, P2 ; /* 0x000000ffff077224 */
/* 0x000fe200010e0603 */
/*0520*/ STG.E.64 [R2.64+-0x18], R4 ; /* 0xffffe80402007986 */
/* 0x000fe4000c101b08 */
/*0530*/ ISETP.GE.AND.EX P1, PT, R10, UR5, PT, P1 ; /* 0x000000050a007c0c */
/* 0x000fc4000bf26310 */
/*0540*/ STG.E.64 [R2.64+-0x10], R4 ; /* 0xfffff00402007986 */
/* 0x000fe8000c101b08 */
/*0550*/ STG.E.64 [R2.64+-0x8], R4 ; /* 0xfffff80402007986 */
/* 0x000fe8000c101b08 */
/*0560*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe8000c101b08 */
/*0570*/ STG.E.64 [R2.64+0x8], R4 ; /* 0x0000080402007986 */
/* 0x000fe8000c101b08 */
/*0580*/ STG.E.64 [R2.64+0x10], R4 ; /* 0x0000100402007986 */
/* 0x000fe8000c101b08 */
/*0590*/ STG.E.64 [R2.64+0x18], R4 ; /* 0x0000180402007986 */
/* 0x000fe8000c101b08 */
/*05a0*/ STG.E.64 [R2.64+0x20], R4 ; /* 0x0000200402007986 */
/* 0x000fe8000c101b08 */
/*05b0*/ STG.E.64 [R2.64+0x28], R4 ; /* 0x0000280402007986 */
/* 0x000fe8000c101b08 */
/*05c0*/ STG.E.64 [R2.64+0x30], R4 ; /* 0x0000300402007986 */
/* 0x000fe8000c101b08 */
/*05d0*/ STG.E.64 [R2.64+0x38], R4 ; /* 0x0000380402007986 */
/* 0x000fe8000c101b08 */
/*05e0*/ STG.E.64 [R2.64+0x40], R4 ; /* 0x0000400402007986 */
/* 0x000fe8000c101b08 */
/*05f0*/ STG.E.64 [R2.64+0x48], R4 ; /* 0x0000480402007986 */
/* 0x000fe8000c101b08 */
/*0600*/ STG.E.64 [R2.64+0x50], R4 ; /* 0x0000500402007986 */
/* 0x000fe8000c101b08 */
/*0610*/ STG.E.64 [R2.64+0x58], R4 ; /* 0x0000580402007986 */
/* 0x000fe8000c101b08 */
/*0620*/ STG.E.64 [R2.64+0x60], R4 ; /* 0x0000600402007986 */
/* 0x0001e4000c101b08 */
/*0630*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0000 */
/*0640*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0007 */
/*0650*/ @!P1 BRA 0x4b0 ; /* 0xfffffe5000009947 */
/* 0x000fea000383ffff */
/*0660*/ IADD3 R0, P2, -R9, c[0x0][0x170], RZ ; /* 0x00005c0009007a10 */
/* 0x000fc80007f5e1ff */
/*0670*/ ISETP.GT.U32.AND P1, PT, R0, 0x4, PT ; /* 0x000000040000780c */
/* 0x000fe40003f24070 */
/*0680*/ IADD3.X R0, ~R10, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d000a007a10 */
/* 0x000fc800017fe5ff */
/*0690*/ ISETP.GT.AND.EX P1, PT, R0, RZ, PT, P1 ; /* 0x000000ff0000720c */
/* 0x000fda0003f24310 */
/*06a0*/ @!P1 BRA 0x7c0 ; /* 0x0000011000009947 */
/* 0x000fea0003800000 */
/*06b0*/ IADD3 R0, P1, R2, 0x40, RZ ; /* 0x0000004002007810 */
/* 0x000fe20007f3e0ff */
/*06c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe200078e00ff */
/*06d0*/ IADD3 R9, P2, R9, 0x8, RZ ; /* 0x0000000809097810 */
/* 0x000fe20007f5e0ff */
/*06e0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fe200078e00ff */
/*06f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0700*/ IMAD.X R7, RZ, RZ, R3, P1 ; /* 0x000000ffff077224 */
/* 0x000fe400008e0603 */
/*0710*/ IMAD.X R10, RZ, RZ, R10, P2 ; /* 0x000000ffff0a7224 */
/* 0x000fe200010e060a */
/*0720*/ STG.E.64 [R2.64+-0x18], R4 ; /* 0xffffe80402007986 */
/* 0x000fe8000c101b08 */
/*0730*/ STG.E.64 [R2.64+-0x10], R4 ; /* 0xfffff00402007986 */
/* 0x000fe8000c101b08 */
/*0740*/ STG.E.64 [R2.64+-0x8], R4 ; /* 0xfffff80402007986 */
/* 0x000fe8000c101b08 */
/*0750*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe8000c101b08 */
/*0760*/ STG.E.64 [R2.64+0x8], R4 ; /* 0x0000080402007986 */
/* 0x000fe8000c101b08 */
/*0770*/ STG.E.64 [R2.64+0x10], R4 ; /* 0x0000100402007986 */
/* 0x000fe8000c101b08 */
/*0780*/ STG.E.64 [R2.64+0x18], R4 ; /* 0x0000180402007986 */
/* 0x000fe8000c101b08 */
/*0790*/ STG.E.64 [R2.64+0x20], R4 ; /* 0x0000200402007986 */
/* 0x0001e4000c101b08 */
/*07a0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0000 */
/*07b0*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0007 */
/*07c0*/ ISETP.LT.U32.AND P1, PT, R9, c[0x0][0x170], PT ; /* 0x00005c0009007a0c */
/* 0x000fc80003f21070 */
/*07d0*/ ISETP.LT.OR.EX P0, PT, R10, c[0x0][0x174], P0, P1 ; /* 0x00005d000a007a0c */
/* 0x000fda0000701710 */
/*07e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*07f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe400078e00ff */
/*0800*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fca00078e00ff */
/*0810*/ STG.E.64 [R2.64+-0x18], R4 ; /* 0xffffe80402007986 */
/* 0x000fe8000c101b08 */
/*0820*/ STG.E.64 [R2.64+-0x10], R4 ; /* 0xfffff00402007986 */
/* 0x000fe8000c101b08 */
/*0830*/ STG.E.64 [R2.64+-0x8], R4 ; /* 0xfffff80402007986 */
/* 0x000fe8000c101b08 */
/*0840*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b08 */
/*0850*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0860*/ LEA R2, P0, R6, c[0x0][0x160], 0x3 ; /* 0x0000580006027a11 */
/* 0x000fc800078018ff */
/*0870*/ LEA.HI.X R3, R6, c[0x0][0x164], RZ, 0x3, P0 ; /* 0x0000590006037a11 */
/* 0x000fca00000f1cff */
/*0880*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000802047981 */
/* 0x000ea8000c1e1b00 */
/*0890*/ LDG.E.64 R8, [R2.64+-0x8] ; /* 0xfffff80802087981 */
/* 0x000ea4000c1e1b00 */
/*08a0*/ ISETP.GE.U32.AND P0, PT, R8, R4, PT ; /* 0x000000040800720c */
/* 0x004fc80003f06070 */
/*08b0*/ ISETP.GE.AND.EX P0, PT, R9, R5, PT, P0 ; /* 0x000000050900720c */
/* 0x000fda0003f06300 */
/*08c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*08d0*/ IMAD.MOV.U32 R13, RZ, RZ, R8 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0008 */
/*08e0*/ IMAD.MOV.U32 R10, RZ, RZ, R9 ; /* 0x000000ffff0a7224 */
/* 0x000fc600078e0009 */
/*08f0*/ LEA R0, P0, R13, c[0x0][0x168], 0x3 ; /* 0x00005a000d007a11 */
/* 0x000fc800078018ff */
/*0900*/ IADD3 R0, P1, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fe40007f3e0ff */
/*0910*/ LEA.HI.X R11, R13, c[0x0][0x16c], R10, 0x3, P0 ; /* 0x00005b000d0b7a11 */
/* 0x000fca00000f1c0a */
/*0920*/ IMAD.X R11, RZ, RZ, R11, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fe400008e060b */
/*0930*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*0940*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0000 */
/*0950*/ IMAD.MOV.U32 R9, RZ, RZ, R11 ; /* 0x000000ffff097224 */
/* 0x000fca00078e000b */
/*0960*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x0001e8000c101b08 */
/*0970*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000802047981 */
/* 0x000ea2000c1e1b00 */
/*0980*/ IADD3 R13, P0, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fe40007f1e0ff */
/*0990*/ IADD3 R0, P1, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fc60007f3e0ff */
/*09a0*/ IMAD.X R10, RZ, RZ, R10, P0 ; /* 0x000000ffff0a7224 */
/* 0x000fe400000e060a */
/*09b0*/ IMAD.X R11, RZ, RZ, R11, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fe200008e060b */
/*09c0*/ ISETP.GE.U32.AND P0, PT, R13, R4, PT ; /* 0x000000040d00720c */
/* 0x004fc80003f06070 */
/*09d0*/ ISETP.GE.AND.EX P0, PT, R10, R5, PT, P0 ; /* 0x000000050a00720c */
/* 0x000fda0003f06300 */
/*09e0*/ @!P0 BRA 0x930 ; /* 0xffffff4000008947 */
/* 0x001fea000383ffff */
/*09f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a00*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe400078e00ff */
/*0a10*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*0a20*/ LDG.E R4, [R2.64+0x4] ; /* 0x0000040802047981 */
/* 0x000ea4000c1e1900 */
/*0a30*/ ISETP.GE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x004fda0003f06270 */
/*0a40*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0a50*/ UMOV UR4, 0xffffffff ; /* 0xffffffff00047882 */
/* 0x000fe40000000000 */
/*0a60*/ UMOV UR5, 0xffffffff ; /* 0xffffffff00057882 */
/* 0x000fe40000000000 */
/*0a70*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fca00078e0000 */
/*0a80*/ STG.E.64 [R6.64], RZ ; /* 0x000000ff06007986 */
/* 0x0001e8000c101b08 */
/*0a90*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000802047981 */
/* 0x000ea2000c1e1b00 */
/*0aa0*/ UIADD3 UR4, UP0, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000ff1e03f */
/*0ab0*/ IADD3 R0, P1, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fc60007f3e0ff */
/*0ac0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*0ad0*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x001fc800008e0607 */
/*0ae0*/ IMAD.U32 R9, RZ, RZ, UR5 ; /* 0x00000005ff097e24 */
/* 0x000fe2000f8e00ff */
/*0af0*/ ISETP.LE.U32.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x004fc8000bf03070 */
/*0b00*/ ISETP.GE.AND.EX P0, PT, R9, R5, PT, P0 ; /* 0x000000050900720c */
/* 0x000fda0003f06300 */
/*0b10*/ @!P0 BRA 0xa70 ; /* 0xffffff5000008947 */
/* 0x000fea000383ffff */
/*0b20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b30*/ BRA 0xb30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14ind2ptr_kernelPKlPlll
.globl _Z14ind2ptr_kernelPKlPlll
.p2align 8
.type _Z14ind2ptr_kernelPKlPlll,@function
_Z14ind2ptr_kernelPKlPlll:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_xor_b32 s10, exec_lo, s2
s_cbranch_execz .LBB0_13
s_load_b64 s[2:3], s[0:1], 0x18
v_mov_b32_e32 v2, 0
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_le_i64_e64 s[2:3], v[1:2]
s_xor_b32 s11, exec_lo, s8
s_cbranch_execz .LBB0_7
s_mov_b32 s12, exec_lo
v_cmpx_eq_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_6
s_lshl_b64 s[8:9], s[2:3], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s8, s4, s8
s_addc_u32 s9, s5, s9
s_add_u32 s8, s8, -8
s_addc_u32 s9, s9, -1
s_load_b64 s[0:1], s[0:1], 0x10
s_load_b64 s[8:9], s[8:9], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_ge_i64_e64 s13, s[8:9], s[0:1]
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s13
s_cbranch_vccnz .LBB0_6
s_lshl_b64 s[14:15], s[8:9], 3
v_mov_b32_e32 v0, s2
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
s_add_u32 s13, s14, s6
s_addc_u32 s3, s15, s7
s_add_u32 s2, s13, 8
s_addc_u32 s3, s3, 0
.LBB0_5:
s_add_u32 s8, s8, 1
s_addc_u32 s9, s9, 0
global_store_b64 v2, v[0:1], s[2:3]
v_cmp_lt_i64_e64 s13, s[8:9], s[0:1]
s_add_u32 s2, s2, 8
s_addc_u32 s3, s3, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s13
s_cbranch_vccnz .LBB0_5
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s12
.LBB0_7:
s_and_not1_saveexec_b32 s1, s11
s_cbranch_execz .LBB0_12
v_lshlrev_b64 v[3:4], 3, v[1:2]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_clause 0x1
global_load_b64 v[5:6], v[3:4], off offset:-8
global_load_b64 v[7:8], v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i64_e64 v[5:6], v[7:8]
s_cbranch_execz .LBB0_11
v_lshlrev_b64 v[7:8], 3, v[5:6]
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v7, s6
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v0, 8
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB0_10:
global_store_b64 v[7:8], v[1:2], off
global_load_b64 v[9:10], v[3:4], off
v_add_co_u32 v5, vcc_lo, v5, 1
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_add_co_u32 v7, s0, v7, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v8, s0, 0, v8, s0
s_waitcnt vmcnt(0)
v_cmp_ge_i64_e32 vcc_lo, v[5:6], v[9:10]
s_or_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_10
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_12:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
.LBB0_13:
s_and_not1_saveexec_b32 s0, s10
s_cbranch_execz .LBB0_17
v_mov_b32_e32 v2, 0
global_load_b64 v[0:1], v2, s[4:5]
s_waitcnt vmcnt(0)
v_cmp_gt_i64_e32 vcc_lo, 0, v[0:1]
s_cbranch_vccnz .LBB0_17
v_mov_b32_e32 v0, 0
s_mov_b64 s[0:1], -1
.LBB0_16:
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v1, v0
s_add_u32 s0, s0, 1
s_addc_u32 s1, s1, 0
global_store_b64 v2, v[0:1], s[6:7]
global_load_b64 v[3:4], v2, s[4:5]
s_add_u32 s6, s6, 8
s_addc_u32 s7, s7, 0
s_waitcnt vmcnt(0)
v_cmp_ge_i64_e32 vcc_lo, s[0:1], v[3:4]
s_cbranch_vccz .LBB0_16
.LBB0_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14ind2ptr_kernelPKlPlll
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14ind2ptr_kernelPKlPlll, .Lfunc_end0-_Z14ind2ptr_kernelPKlPlll
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14ind2ptr_kernelPKlPlll
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14ind2ptr_kernelPKlPlll.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0012ca29_00000000-6_ind2ptr_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z14ind2ptr_kernelPKlPlllPKlPlll
.type _Z39__device_stub__Z14ind2ptr_kernelPKlPlllPKlPlll, @function
_Z39__device_stub__Z14ind2ptr_kernelPKlPlllPKlPlll:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14ind2ptr_kernelPKlPlll(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z14ind2ptr_kernelPKlPlllPKlPlll, .-_Z39__device_stub__Z14ind2ptr_kernelPKlPlllPKlPlll
.globl _Z14ind2ptr_kernelPKlPlll
.type _Z14ind2ptr_kernelPKlPlll, @function
_Z14ind2ptr_kernelPKlPlll:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14ind2ptr_kernelPKlPlllPKlPlll
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14ind2ptr_kernelPKlPlll, .-_Z14ind2ptr_kernelPKlPlll
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14ind2ptr_kernelPKlPlll"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14ind2ptr_kernelPKlPlll(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "ind2ptr_kernel.hip"
.globl _Z29__device_stub__ind2ptr_kernelPKlPlll # -- Begin function _Z29__device_stub__ind2ptr_kernelPKlPlll
.p2align 4, 0x90
.type _Z29__device_stub__ind2ptr_kernelPKlPlll,@function
_Z29__device_stub__ind2ptr_kernelPKlPlll: # @_Z29__device_stub__ind2ptr_kernelPKlPlll
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14ind2ptr_kernelPKlPlll, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__ind2ptr_kernelPKlPlll, .Lfunc_end0-_Z29__device_stub__ind2ptr_kernelPKlPlll
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14ind2ptr_kernelPKlPlll, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14ind2ptr_kernelPKlPlll,@object # @_Z14ind2ptr_kernelPKlPlll
.section .rodata,"a",@progbits
.globl _Z14ind2ptr_kernelPKlPlll
.p2align 3, 0x0
_Z14ind2ptr_kernelPKlPlll:
.quad _Z29__device_stub__ind2ptr_kernelPKlPlll
.size _Z14ind2ptr_kernelPKlPlll, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14ind2ptr_kernelPKlPlll"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__ind2ptr_kernelPKlPlll
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14ind2ptr_kernelPKlPlll
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
/*
*
* Carlos Roman Rivera - A01700820
*
* Programming Languages - Cuda Lab 1
*
*/
#include <stdio.h>
#include <stdlib.h>
#define BLOCKS 1000
#define THREADS_PER_BLOCK 512
#define RECTANGLES 1000000
__global__ void gpuPi(double *r, double width, int n) {
int idx = threadIdx.x + (blockIdx.x * blockDim.x); // Index to calculate.
int id = idx; // My array position.
double mid, height; // Auxiliary variables.
while (idx < n) { // Dont overflow array.
mid = (idx + 0.6) * width; // Formula.
height = 4.0 / (1.0 + mid * mid); // Formula.
r[id] += height; // Store result.
idx += (blockDim.x * gridDim.x); // Update index.
}
}
int main() {
double *pi;
double *d_pi;
double width;
double result = 0;
width = 1.0 / (double) RECTANGLES;
int results = (BLOCKS * THREADS_PER_BLOCK); // Total threads.
int size = results * sizeof(double); // Size in bytes.
pi = (double*) malloc(size); // Memory on host.
cudaMalloc((void**)&d_pi, size); // Memory on device.
cudaMemcpy(d_pi, pi, size, cudaMemcpyHostToDevice); // Host to device.
gpuPi<<<BLOCKS, THREADS_PER_BLOCK>>>(d_pi, width, RECTANGLES);
cudaMemcpy(pi, d_pi, size, cudaMemcpyDeviceToHost); // Device to host.
for(int i = 0 ; i < results ; i++) { // Sum results.
result += pi[i];
}
result *= width; // Formula.
printf("PI: %lf\n", result); // Display result.
free(pi); // Free host memory.
cudaFree(d_pi); // Free device memory.
return 0;
}
|
code for sm_80
Function : _Z5gpuPiPddi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000162000c1e1b00 */
/*00a0*/ BSSY B0, 0x260 ; /* 0x000001b000007945 */
/* 0x000fe40003800000 */
/*00b0*/ I2F.F64 R6, R0 ; /* 0x0000000000067312 */
/* 0x006e620000201c00 */
/*00c0*/ BSSY B1, 0x230 ; /* 0x0000016000017945 */
/* 0x000fe20003800000 */
/*00d0*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*00e0*/ DMUL R6, R6, c[0x0][0x168] ; /* 0x00005a0006067a28 */
/* 0x002e4c0000000000 */
/*00f0*/ DFMA R8, R6, R6, 1 ; /* 0x3ff000000608742b */
/* 0x0022a40000000006 */
/*0100*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x002fc800078e00ff */
/*0110*/ MUFU.RCP64H R7, R9 ; /* 0x0000000900077308 */
/* 0x004e640000001800 */
/*0120*/ DFMA R10, -R8, R6, 1 ; /* 0x3ff00000080a742b */
/* 0x002e4c0000000106 */
/*0130*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x002e4c000000000a */
/*0140*/ DFMA R10, R6, R10, R6 ; /* 0x0000000a060a722b */
/* 0x002e4c0000000006 */
/*0150*/ DFMA R6, -R8, R10, 1 ; /* 0x3ff000000806742b */
/* 0x002e4c000000010a */
/*0160*/ DFMA R6, R10, R6, R10 ; /* 0x000000060a06722b */
/* 0x002e4c000000000a */
/*0170*/ DMUL R10, R6, 4 ; /* 0x40100000060a7828 */
/* 0x002e4c0000000000 */
/*0180*/ DFMA R12, -R8, R10, 4 ; /* 0x40100000080c742b */
/* 0x002e4c000000010a */
/*0190*/ DFMA R6, R6, R12, R10 ; /* 0x0000000c0606722b */
/* 0x0022a4000000000a */
/*01a0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0b7624 */
/* 0x002fc800078e00ff */
/*01b0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fc800078e0200 */
/*01c0*/ FFMA R10, RZ, R9, R7 ; /* 0x00000009ff0a7223 */
/* 0x004fe20000000007 */
/*01d0*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f26270 */
/*01e0*/ FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ; /* 0x001000000a00780b */
/* 0x000fda0003f04200 */
/*01f0*/ @P0 BRA 0x220 ; /* 0x0000002000000947 */
/* 0x009fea0003800000 */
/*0200*/ MOV R10, 0x220 ; /* 0x00000220000a7802 */
/* 0x000fe40000000f00 */
/*0210*/ CALL.REL.NOINC 0x280 ; /* 0x0000006000007944 */
/* 0x021fea0003c00000 */
/*0220*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0230*/ DADD R4, R6, R4 ; /* 0x0000000006047229 */
/* 0x0204e20000000004 */
/*0240*/ @!P1 BRA 0xb0 ; /* 0xfffffe6000009947 */
/* 0x000fea000383ffff */
/*0250*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0260*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x008fe2000c101b04 */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ FSETP.GEU.AND P0, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f0e200 */
/*0290*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; /* 0x00000001ff0c7424 */
/* 0x000fe200078e00ff */
/*02a0*/ LOP3.LUT R6, R9.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff09067812 */
/* 0x040fe200078ec0ff */
/*02b0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x40100000 ; /* 0x40100000ff0b7424 */
/* 0x000fe200078e00ff */
/*02c0*/ LOP3.LUT R22, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009167812 */
/* 0x000fe200078ec0ff */
/*02d0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff107424 */
/* 0x000fe200078e00ff */
/*02e0*/ LOP3.LUT R7, R6, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000006077812 */
/* 0x000fe200078efcff */
/*02f0*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0008 */
/*0300*/ ISETP.LE.U32.AND P2, PT, R22, 0x40100000, PT ; /* 0x401000001600780c */
/* 0x000fe20003f43070 */
/*0310*/ BSSY B2, 0x720 ; /* 0x0000040000027945 */
/* 0x000fe20003800000 */
/*0320*/ IADD3 R17, R11, -0x1, RZ ; /* 0xffffffff0b117810 */
/* 0x000fc60007ffe0ff */
/*0330*/ @!P0 DMUL R6, R8, 8.98846567431157953865e+307 ; /* 0x7fe0000008068828 */
/* 0x000e0c0000000000 */
/*0340*/ MUFU.RCP64H R13, R7 ; /* 0x00000007000d7308 */
/* 0x001e280000001800 */
/*0350*/ @!P0 LOP3.LUT R22, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007168812 */
/* 0x000fe400078ec0ff */
/*0360*/ ISETP.GT.U32.AND P0, PT, R17, 0x7feffffe, PT ; /* 0x7feffffe1100780c */
/* 0x000fe40003f04070 */
/*0370*/ IADD3 R17, R22, -0x1, RZ ; /* 0xffffffff16117810 */
/* 0x000fc80007ffe0ff */
/*0380*/ ISETP.GT.U32.OR P0, PT, R17, 0x7feffffe, P0 ; /* 0x7feffffe1100780c */
/* 0x000fe20000704470 */
/*0390*/ DFMA R14, R12, -R6, 1 ; /* 0x3ff000000c0e742b */
/* 0x001e0c0000000806 */
/*03a0*/ DFMA R14, R14, R14, R14 ; /* 0x0000000e0e0e722b */
/* 0x001e0c000000000e */
/*03b0*/ DFMA R14, R12, R14, R12 ; /* 0x0000000e0c0e722b */
/* 0x001064000000000c */
/*03c0*/ SEL R13, R16, 0x63400000, !P2 ; /* 0x63400000100d7807 */
/* 0x001fe20005000000 */
/*03d0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fc600078e00ff */
/*03e0*/ DFMA R18, R14, -R6, 1 ; /* 0x3ff000000e12742b */
/* 0x002e0c0000000806 */
/*03f0*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e0c000000000e */
/*0400*/ DMUL R18, R14, R12 ; /* 0x0000000c0e127228 */
/* 0x001e0c0000000000 */
/*0410*/ DFMA R20, R18, -R6, R12 ; /* 0x800000061214722b */
/* 0x001e0c000000000c */
/*0420*/ DFMA R14, R14, R20, R18 ; /* 0x000000140e0e722b */
/* 0x0010620000000012 */
/*0430*/ @P0 BRA 0x600 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0440*/ LOP3.LUT R17, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009117812 */
/* 0x000fe200078ec0ff */
/*0450*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x001fc600078e00ff */
/*0460*/ IADD3 R11, -R17.reuse, 0x40100000, RZ ; /* 0x40100000110b7810 */
/* 0x040fe40007ffe1ff */
/*0470*/ ISETP.LE.U32.AND P0, PT, R17, 0x40100000, PT ; /* 0x401000001100780c */
/* 0x000fe40003f03070 */
/*0480*/ IMNMX R11, R11, -0x46a00000, !PT ; /* 0xb96000000b0b7817 */
/* 0x000fe40007800200 */
/*0490*/ SEL R16, R16, 0x63400000, !P0 ; /* 0x6340000010107807 */
/* 0x000fe40004000000 */
/*04a0*/ IMNMX R11, R11, 0x46a00000, PT ; /* 0x46a000000b0b7817 */
/* 0x000fca0003800200 */
/*04b0*/ IMAD.IADD R11, R11, 0x1, -R16 ; /* 0x000000010b0b7824 */
/* 0x000fca00078e0a10 */
/*04c0*/ IADD3 R19, R11, 0x7fe00000, RZ ; /* 0x7fe000000b137810 */
/* 0x000fcc0007ffe0ff */
/*04d0*/ DMUL R16, R14, R18 ; /* 0x000000120e107228 */
/* 0x002e140000000000 */
/*04e0*/ FSETP.GTU.AND P0, PT, |R17|, 1.469367938527859385e-39, PT ; /* 0x001000001100780b */
/* 0x001fda0003f0c200 */
/*04f0*/ @P0 BRA 0x710 ; /* 0x0000021000000947 */
/* 0x000fea0003800000 */
/*0500*/ DFMA R6, R14, -R6, R12 ; /* 0x800000060e06722b */
/* 0x000e22000000000c */
/*0510*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fd200078e00ff */
/*0520*/ FSETP.NEU.AND P0, PT, R7.reuse, RZ, PT ; /* 0x000000ff0700720b */
/* 0x041fe40003f0d000 */
/*0530*/ LOP3.LUT R9, R7, 0x80000000, R9, 0x48, !PT ; /* 0x8000000007097812 */
/* 0x000fc800078e4809 */
/*0540*/ LOP3.LUT R19, R9, R19, RZ, 0xfc, !PT ; /* 0x0000001309137212 */
/* 0x000fce00078efcff */
/*0550*/ @!P0 BRA 0x710 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0560*/ IMAD.MOV R7, RZ, RZ, -R11 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a0b */
/*0570*/ IADD3 R11, -R11, -0x43300000, RZ ; /* 0xbcd000000b0b7810 */
/* 0x000fe20007ffe1ff */
/*0580*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fcc00078e00ff */
/*0590*/ DFMA R6, R16, -R6, R14 ; /* 0x800000061006722b */
/* 0x000e08000000000e */
/*05a0*/ DMUL.RP R14, R14, R18 ; /* 0x000000120e0e7228 */
/* 0x000e4c0000008000 */
/*05b0*/ FSETP.NEU.AND P0, PT, |R7|, R11, PT ; /* 0x0000000b0700720b */
/* 0x001fc80003f0d200 */
/*05c0*/ LOP3.LUT R9, R15, R9, RZ, 0x3c, !PT ; /* 0x000000090f097212 */
/* 0x002fe400078e3cff */
/*05d0*/ FSEL R16, R14, R16, !P0 ; /* 0x000000100e107208 */
/* 0x000fe40004000000 */
/*05e0*/ FSEL R17, R9, R17, !P0 ; /* 0x0000001109117208 */
/* 0x000fe20004000000 */
/*05f0*/ BRA 0x710 ; /* 0x0000011000007947 */
/* 0x000fea0003800000 */
/*0600*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e9c0003f08000 */
/*0610*/ @P0 BRA 0x6f0 ; /* 0x000000d000000947 */
/* 0x004fea0003800000 */
/*0620*/ ISETP.NE.AND P0, PT, R11, R22, PT ; /* 0x000000160b00720c */
/* 0x000fe20003f05270 */
/*0630*/ IMAD.MOV.U32 R16, RZ, RZ, 0x0 ; /* 0x00000000ff107424 */
/* 0x000fe400078e00ff */
/*0640*/ IMAD.MOV.U32 R17, RZ, RZ, -0x80000 ; /* 0xfff80000ff117424 */
/* 0x000fd400078e00ff */
/*0650*/ @!P0 BRA 0x710 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0660*/ ISETP.NE.AND P0, PT, R11, 0x7ff00000, PT ; /* 0x7ff000000b00780c */
/* 0x000fe40003f05270 */
/*0670*/ LOP3.LUT R8, R9, 0x40100000, RZ, 0x3c, !PT ; /* 0x4010000009087812 */
/* 0x000fe400078e3cff */
/*0680*/ ISETP.EQ.OR P0, PT, R22, RZ, !P0 ; /* 0x000000ff1600720c */
/* 0x000fe40004702670 */
/*0690*/ LOP3.LUT R17, R8, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000008117812 */
/* 0x000fd600078ec0ff */
/*06a0*/ @P0 LOP3.LUT R6, R17, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000011060812 */
/* 0x000fe200078efcff */
/*06b0*/ @!P0 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff108224 */
/* 0x000fe400078e00ff */
/*06c0*/ @P0 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff100224 */
/* 0x000fe400078e00ff */
/*06d0*/ @P0 IMAD.MOV.U32 R17, RZ, RZ, R6 ; /* 0x000000ffff110224 */
/* 0x000fe200078e0006 */
/*06e0*/ BRA 0x710 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*06f0*/ LOP3.LUT R17, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000009117812 */
/* 0x000fe200078efcff */
/*0700*/ IMAD.MOV.U32 R16, RZ, RZ, R8 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0008 */
/*0710*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0720*/ IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; /* 0x00000000ff0b7424 */
/* 0x000fe400078e00ff */
/*0730*/ IMAD.MOV.U32 R6, RZ, RZ, R16 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0010 */
/*0740*/ IMAD.MOV.U32 R7, RZ, RZ, R17 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0011 */
/*0750*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff8a00a007950 */
/* 0x000fec0003c3ffff */
/*0760*/ BRA 0x760; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
/*
*
* Carlos Roman Rivera - A01700820
*
* Programming Languages - Cuda Lab 1
*
*/
#include <stdio.h>
#include <stdlib.h>
#define BLOCKS 1000
#define THREADS_PER_BLOCK 512
#define RECTANGLES 1000000
__global__ void gpuPi(double *r, double width, int n) {
int idx = threadIdx.x + (blockIdx.x * blockDim.x); // Index to calculate.
int id = idx; // My array position.
double mid, height; // Auxiliary variables.
while (idx < n) { // Dont overflow array.
mid = (idx + 0.6) * width; // Formula.
height = 4.0 / (1.0 + mid * mid); // Formula.
r[id] += height; // Store result.
idx += (blockDim.x * gridDim.x); // Update index.
}
}
int main() {
double *pi;
double *d_pi;
double width;
double result = 0;
width = 1.0 / (double) RECTANGLES;
int results = (BLOCKS * THREADS_PER_BLOCK); // Total threads.
int size = results * sizeof(double); // Size in bytes.
pi = (double*) malloc(size); // Memory on host.
cudaMalloc((void**)&d_pi, size); // Memory on device.
cudaMemcpy(d_pi, pi, size, cudaMemcpyHostToDevice); // Host to device.
gpuPi<<<BLOCKS, THREADS_PER_BLOCK>>>(d_pi, width, RECTANGLES);
cudaMemcpy(pi, d_pi, size, cudaMemcpyDeviceToHost); // Device to host.
for(int i = 0 ; i < results ; i++) { // Sum results.
result += pi[i];
}
result *= width; // Formula.
printf("PI: %lf\n", result); // Display result.
free(pi); // Free host memory.
cudaFree(d_pi); // Free device memory.
return 0;
}
|
.file "tmpxft_00025ad9_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z5gpuPiPddiPddi
.type _Z26__device_stub__Z5gpuPiPddiPddi, @function
_Z26__device_stub__Z5gpuPiPddiPddi:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movsd %xmm0, 16(%rsp)
movl %esi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5gpuPiPddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z5gpuPiPddiPddi, .-_Z26__device_stub__Z5gpuPiPddiPddi
.globl _Z5gpuPiPddi
.type _Z5gpuPiPddi, @function
_Z5gpuPiPddi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z5gpuPiPddiPddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5gpuPiPddi, .-_Z5gpuPiPddi
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "PI: %lf\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4096000, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4096000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4096000, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 28(%rsp)
movl $1, 32(%rsp)
movl $1000, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
movl $2, %ecx
movl $4096000, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 4096000(%rbx), %rdx
pxor %xmm0, %xmm0
.L13:
addsd (%rax), %xmm0
addq $8, %rax
cmpq %rdx, %rax
jne .L13
mulsd .LC1(%rip), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $1000000, %esi
movsd .LC1(%rip), %xmm0
movq 8(%rsp), %rdi
call _Z26__device_stub__Z5gpuPiPddiPddi
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z5gpuPiPddi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z5gpuPiPddi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/*
*
* Carlos Roman Rivera - A01700820
*
* Programming Languages - Cuda Lab 1
*
*/
#include <stdio.h>
#include <stdlib.h>
#define BLOCKS 1000
#define THREADS_PER_BLOCK 512
#define RECTANGLES 1000000
__global__ void gpuPi(double *r, double width, int n) {
int idx = threadIdx.x + (blockIdx.x * blockDim.x); // Index to calculate.
int id = idx; // My array position.
double mid, height; // Auxiliary variables.
while (idx < n) { // Dont overflow array.
mid = (idx + 0.6) * width; // Formula.
height = 4.0 / (1.0 + mid * mid); // Formula.
r[id] += height; // Store result.
idx += (blockDim.x * gridDim.x); // Update index.
}
}
int main() {
double *pi;
double *d_pi;
double width;
double result = 0;
width = 1.0 / (double) RECTANGLES;
int results = (BLOCKS * THREADS_PER_BLOCK); // Total threads.
int size = results * sizeof(double); // Size in bytes.
pi = (double*) malloc(size); // Memory on host.
cudaMalloc((void**)&d_pi, size); // Memory on device.
cudaMemcpy(d_pi, pi, size, cudaMemcpyHostToDevice); // Host to device.
gpuPi<<<BLOCKS, THREADS_PER_BLOCK>>>(d_pi, width, RECTANGLES);
cudaMemcpy(pi, d_pi, size, cudaMemcpyDeviceToHost); // Device to host.
for(int i = 0 ; i < results ; i++) { // Sum results.
result += pi[i];
}
result *= width; // Formula.
printf("PI: %lf\n", result); // Display result.
free(pi); // Free host memory.
cudaFree(d_pi); // Free device memory.
return 0;
}
|
/*
*
* Carlos Roman Rivera - A01700820
*
* Programming Languages - Cuda Lab 1
*
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCKS 1000
#define THREADS_PER_BLOCK 512
#define RECTANGLES 1000000
__global__ void gpuPi(double *r, double width, int n) {
int idx = threadIdx.x + (blockIdx.x * blockDim.x); // Index to calculate.
int id = idx; // My array position.
double mid, height; // Auxiliary variables.
while (idx < n) { // Dont overflow array.
mid = (idx + 0.6) * width; // Formula.
height = 4.0 / (1.0 + mid * mid); // Formula.
r[id] += height; // Store result.
idx += (blockDim.x * gridDim.x); // Update index.
}
}
int main() {
double *pi;
double *d_pi;
double width;
double result = 0;
width = 1.0 / (double) RECTANGLES;
int results = (BLOCKS * THREADS_PER_BLOCK); // Total threads.
int size = results * sizeof(double); // Size in bytes.
pi = (double*) malloc(size); // Memory on host.
hipMalloc((void**)&d_pi, size); // Memory on device.
hipMemcpy(d_pi, pi, size, hipMemcpyHostToDevice); // Host to device.
gpuPi<<<BLOCKS, THREADS_PER_BLOCK>>>(d_pi, width, RECTANGLES);
hipMemcpy(pi, d_pi, size, hipMemcpyDeviceToHost); // Device to host.
for(int i = 0 ; i < results ; i++) { // Sum results.
result += pi[i];
}
result *= width; // Formula.
printf("PI: %lf\n", result); // Display result.
free(pi); // Free host memory.
hipFree(d_pi); // Free device memory.
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
/*
*
* Carlos Roman Rivera - A01700820
*
* Programming Languages - Cuda Lab 1
*
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCKS 1000
#define THREADS_PER_BLOCK 512
#define RECTANGLES 1000000
__global__ void gpuPi(double *r, double width, int n) {
int idx = threadIdx.x + (blockIdx.x * blockDim.x); // Index to calculate.
int id = idx; // My array position.
double mid, height; // Auxiliary variables.
while (idx < n) { // Dont overflow array.
mid = (idx + 0.6) * width; // Formula.
height = 4.0 / (1.0 + mid * mid); // Formula.
r[id] += height; // Store result.
idx += (blockDim.x * gridDim.x); // Update index.
}
}
int main() {
double *pi;
double *d_pi;
double width;
double result = 0;
width = 1.0 / (double) RECTANGLES;
int results = (BLOCKS * THREADS_PER_BLOCK); // Total threads.
int size = results * sizeof(double); // Size in bytes.
pi = (double*) malloc(size); // Memory on host.
hipMalloc((void**)&d_pi, size); // Memory on device.
hipMemcpy(d_pi, pi, size, hipMemcpyHostToDevice); // Host to device.
gpuPi<<<BLOCKS, THREADS_PER_BLOCK>>>(d_pi, width, RECTANGLES);
hipMemcpy(pi, d_pi, size, hipMemcpyDeviceToHost); // Device to host.
for(int i = 0 ; i < results ; i++) { // Sum results.
result += pi[i];
}
result *= width; // Formula.
printf("PI: %lf\n", result); // Display result.
free(pi); // Free host memory.
hipFree(d_pi); // Free device memory.
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5gpuPiPddi
.globl _Z5gpuPiPddi
.p2align 8
.type _Z5gpuPiPddi,@function
_Z5gpuPiPddi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x10
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s7, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s6, v1
s_cbranch_execz .LBB0_4
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s5, s[4:5], 0x0
s_mov_b32 s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_mul_i32 s5, s5, s7
s_mov_b32 s1, 0x3fe33333
s_mov_b32 s0, 0x33333333
global_load_b64 v[4:5], v[2:3], off
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_cvt_f64_i32_e32 v[6:7], v1
v_add_nc_u32_e32 v1, s5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[6:7], s[0:1]
v_mul_f64 v[6:7], v[6:7], s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[6:7], 1.0
v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], 4.0
v_div_scale_f64 v[14:15], vcc_lo, 4.0, v[6:7], 4.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[10:11], v[8:9]
s_waitcnt_depctr 0xfff
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[14:15], v[10:11]
v_fma_f64 v[8:9], -v[8:9], v[12:13], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[12:13]
v_cmp_le_i32_e32 vcc_lo, s6, v1
s_or_b32 s4, vcc_lo, s4
v_div_fixup_f64 v[6:7], v[8:9], v[6:7], 4.0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[4:5], v[6:7], v[4:5]
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_2
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s4
global_store_b64 v[2:3], v[4:5], off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5gpuPiPddi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5gpuPiPddi, .Lfunc_end0-_Z5gpuPiPddi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5gpuPiPddi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5gpuPiPddi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
/*
*
* Carlos Roman Rivera - A01700820
*
* Programming Languages - Cuda Lab 1
*
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCKS 1000
#define THREADS_PER_BLOCK 512
#define RECTANGLES 1000000
__global__ void gpuPi(double *r, double width, int n) {
int idx = threadIdx.x + (blockIdx.x * blockDim.x); // Index to calculate.
int id = idx; // My array position.
double mid, height; // Auxiliary variables.
while (idx < n) { // Dont overflow array.
mid = (idx + 0.6) * width; // Formula.
height = 4.0 / (1.0 + mid * mid); // Formula.
r[id] += height; // Store result.
idx += (blockDim.x * gridDim.x); // Update index.
}
}
int main() {
double *pi;
double *d_pi;
double width;
double result = 0;
width = 1.0 / (double) RECTANGLES;
int results = (BLOCKS * THREADS_PER_BLOCK); // Total threads.
int size = results * sizeof(double); // Size in bytes.
pi = (double*) malloc(size); // Memory on host.
hipMalloc((void**)&d_pi, size); // Memory on device.
hipMemcpy(d_pi, pi, size, hipMemcpyHostToDevice); // Host to device.
gpuPi<<<BLOCKS, THREADS_PER_BLOCK>>>(d_pi, width, RECTANGLES);
hipMemcpy(pi, d_pi, size, hipMemcpyDeviceToHost); // Device to host.
for(int i = 0 ; i < results ; i++) { // Sum results.
result += pi[i];
}
result *= width; // Formula.
printf("PI: %lf\n", result); // Display result.
free(pi); // Free host memory.
hipFree(d_pi); // Free device memory.
return 0;
}
|
.text
.file "main.hip"
.globl _Z20__device_stub__gpuPiPddi # -- Begin function _Z20__device_stub__gpuPiPddi
.p2align 4, 0x90
.type _Z20__device_stub__gpuPiPddi,@function
_Z20__device_stub__gpuPiPddi: # @_Z20__device_stub__gpuPiPddi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movsd %xmm0, 64(%rsp)
movl %esi, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5gpuPiPddi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z20__device_stub__gpuPiPddi, .Lfunc_end0-_Z20__device_stub__gpuPiPddi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
movl $4096000, %edi # imm = 0x3E8000
callq malloc
movq %rax, %rbx
movq %rsp, %rdi
movl $4096000, %esi # imm = 0x3E8000
callq hipMalloc
movq (%rsp), %rdi
movl $4096000, %edx # imm = 0x3E8000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967808, %rdx # imm = 0x100000200
leaq 488(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movq %rax, 72(%rsp)
movabsq $4517329193108106637, %rax # imm = 0x3EB0C6F7A0B5ED8D
movq %rax, 64(%rsp)
movl $1000000, 12(%rsp) # imm = 0xF4240
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5gpuPiPddi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movl $4096000, %edx # imm = 0x3E8000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorpd %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
addsd (%rbx,%rax,8), %xmm0
incq %rax
cmpq $512000, %rax # imm = 0x7D000
jne .LBB1_3
# %bb.4:
mulsd .LCPI1_0(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5gpuPiPddi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5gpuPiPddi,@object # @_Z5gpuPiPddi
.section .rodata,"a",@progbits
.globl _Z5gpuPiPddi
.p2align 3, 0x0
_Z5gpuPiPddi:
.quad _Z20__device_stub__gpuPiPddi
.size _Z5gpuPiPddi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "PI: %lf\n"
.size .L.str, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5gpuPiPddi"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__gpuPiPddi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5gpuPiPddi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z5gpuPiPddi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000162000c1e1b00 */
/*00a0*/ BSSY B0, 0x260 ; /* 0x000001b000007945 */
/* 0x000fe40003800000 */
/*00b0*/ I2F.F64 R6, R0 ; /* 0x0000000000067312 */
/* 0x006e620000201c00 */
/*00c0*/ BSSY B1, 0x230 ; /* 0x0000016000017945 */
/* 0x000fe20003800000 */
/*00d0*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*00e0*/ DMUL R6, R6, c[0x0][0x168] ; /* 0x00005a0006067a28 */
/* 0x002e4c0000000000 */
/*00f0*/ DFMA R8, R6, R6, 1 ; /* 0x3ff000000608742b */
/* 0x0022a40000000006 */
/*0100*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x002fc800078e00ff */
/*0110*/ MUFU.RCP64H R7, R9 ; /* 0x0000000900077308 */
/* 0x004e640000001800 */
/*0120*/ DFMA R10, -R8, R6, 1 ; /* 0x3ff00000080a742b */
/* 0x002e4c0000000106 */
/*0130*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x002e4c000000000a */
/*0140*/ DFMA R10, R6, R10, R6 ; /* 0x0000000a060a722b */
/* 0x002e4c0000000006 */
/*0150*/ DFMA R6, -R8, R10, 1 ; /* 0x3ff000000806742b */
/* 0x002e4c000000010a */
/*0160*/ DFMA R6, R10, R6, R10 ; /* 0x000000060a06722b */
/* 0x002e4c000000000a */
/*0170*/ DMUL R10, R6, 4 ; /* 0x40100000060a7828 */
/* 0x002e4c0000000000 */
/*0180*/ DFMA R12, -R8, R10, 4 ; /* 0x40100000080c742b */
/* 0x002e4c000000010a */
/*0190*/ DFMA R6, R6, R12, R10 ; /* 0x0000000c0606722b */
/* 0x0022a4000000000a */
/*01a0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0b7624 */
/* 0x002fc800078e00ff */
/*01b0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fc800078e0200 */
/*01c0*/ FFMA R10, RZ, R9, R7 ; /* 0x00000009ff0a7223 */
/* 0x004fe20000000007 */
/*01d0*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f26270 */
/*01e0*/ FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ; /* 0x001000000a00780b */
/* 0x000fda0003f04200 */
/*01f0*/ @P0 BRA 0x220 ; /* 0x0000002000000947 */
/* 0x009fea0003800000 */
/*0200*/ MOV R10, 0x220 ; /* 0x00000220000a7802 */
/* 0x000fe40000000f00 */
/*0210*/ CALL.REL.NOINC 0x280 ; /* 0x0000006000007944 */
/* 0x021fea0003c00000 */
/*0220*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0230*/ DADD R4, R6, R4 ; /* 0x0000000006047229 */
/* 0x0204e20000000004 */
/*0240*/ @!P1 BRA 0xb0 ; /* 0xfffffe6000009947 */
/* 0x000fea000383ffff */
/*0250*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0260*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x008fe2000c101b04 */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ FSETP.GEU.AND P0, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f0e200 */
/*0290*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; /* 0x00000001ff0c7424 */
/* 0x000fe200078e00ff */
/*02a0*/ LOP3.LUT R6, R9.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff09067812 */
/* 0x040fe200078ec0ff */
/*02b0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x40100000 ; /* 0x40100000ff0b7424 */
/* 0x000fe200078e00ff */
/*02c0*/ LOP3.LUT R22, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009167812 */
/* 0x000fe200078ec0ff */
/*02d0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff107424 */
/* 0x000fe200078e00ff */
/*02e0*/ LOP3.LUT R7, R6, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000006077812 */
/* 0x000fe200078efcff */
/*02f0*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0008 */
/*0300*/ ISETP.LE.U32.AND P2, PT, R22, 0x40100000, PT ; /* 0x401000001600780c */
/* 0x000fe20003f43070 */
/*0310*/ BSSY B2, 0x720 ; /* 0x0000040000027945 */
/* 0x000fe20003800000 */
/*0320*/ IADD3 R17, R11, -0x1, RZ ; /* 0xffffffff0b117810 */
/* 0x000fc60007ffe0ff */
/*0330*/ @!P0 DMUL R6, R8, 8.98846567431157953865e+307 ; /* 0x7fe0000008068828 */
/* 0x000e0c0000000000 */
/*0340*/ MUFU.RCP64H R13, R7 ; /* 0x00000007000d7308 */
/* 0x001e280000001800 */
/*0350*/ @!P0 LOP3.LUT R22, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007168812 */
/* 0x000fe400078ec0ff */
/*0360*/ ISETP.GT.U32.AND P0, PT, R17, 0x7feffffe, PT ; /* 0x7feffffe1100780c */
/* 0x000fe40003f04070 */
/*0370*/ IADD3 R17, R22, -0x1, RZ ; /* 0xffffffff16117810 */
/* 0x000fc80007ffe0ff */
/*0380*/ ISETP.GT.U32.OR P0, PT, R17, 0x7feffffe, P0 ; /* 0x7feffffe1100780c */
/* 0x000fe20000704470 */
/*0390*/ DFMA R14, R12, -R6, 1 ; /* 0x3ff000000c0e742b */
/* 0x001e0c0000000806 */
/*03a0*/ DFMA R14, R14, R14, R14 ; /* 0x0000000e0e0e722b */
/* 0x001e0c000000000e */
/*03b0*/ DFMA R14, R12, R14, R12 ; /* 0x0000000e0c0e722b */
/* 0x001064000000000c */
/*03c0*/ SEL R13, R16, 0x63400000, !P2 ; /* 0x63400000100d7807 */
/* 0x001fe20005000000 */
/*03d0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fc600078e00ff */
/*03e0*/ DFMA R18, R14, -R6, 1 ; /* 0x3ff000000e12742b */
/* 0x002e0c0000000806 */
/*03f0*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e0c000000000e */
/*0400*/ DMUL R18, R14, R12 ; /* 0x0000000c0e127228 */
/* 0x001e0c0000000000 */
/*0410*/ DFMA R20, R18, -R6, R12 ; /* 0x800000061214722b */
/* 0x001e0c000000000c */
/*0420*/ DFMA R14, R14, R20, R18 ; /* 0x000000140e0e722b */
/* 0x0010620000000012 */
/*0430*/ @P0 BRA 0x600 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0440*/ LOP3.LUT R17, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009117812 */
/* 0x000fe200078ec0ff */
/*0450*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x001fc600078e00ff */
/*0460*/ IADD3 R11, -R17.reuse, 0x40100000, RZ ; /* 0x40100000110b7810 */
/* 0x040fe40007ffe1ff */
/*0470*/ ISETP.LE.U32.AND P0, PT, R17, 0x40100000, PT ; /* 0x401000001100780c */
/* 0x000fe40003f03070 */
/*0480*/ IMNMX R11, R11, -0x46a00000, !PT ; /* 0xb96000000b0b7817 */
/* 0x000fe40007800200 */
/*0490*/ SEL R16, R16, 0x63400000, !P0 ; /* 0x6340000010107807 */
/* 0x000fe40004000000 */
/*04a0*/ IMNMX R11, R11, 0x46a00000, PT ; /* 0x46a000000b0b7817 */
/* 0x000fca0003800200 */
/*04b0*/ IMAD.IADD R11, R11, 0x1, -R16 ; /* 0x000000010b0b7824 */
/* 0x000fca00078e0a10 */
/*04c0*/ IADD3 R19, R11, 0x7fe00000, RZ ; /* 0x7fe000000b137810 */
/* 0x000fcc0007ffe0ff */
/*04d0*/ DMUL R16, R14, R18 ; /* 0x000000120e107228 */
/* 0x002e140000000000 */
/*04e0*/ FSETP.GTU.AND P0, PT, |R17|, 1.469367938527859385e-39, PT ; /* 0x001000001100780b */
/* 0x001fda0003f0c200 */
/*04f0*/ @P0 BRA 0x710 ; /* 0x0000021000000947 */
/* 0x000fea0003800000 */
/*0500*/ DFMA R6, R14, -R6, R12 ; /* 0x800000060e06722b */
/* 0x000e22000000000c */
/*0510*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fd200078e00ff */
/*0520*/ FSETP.NEU.AND P0, PT, R7.reuse, RZ, PT ; /* 0x000000ff0700720b */
/* 0x041fe40003f0d000 */
/*0530*/ LOP3.LUT R9, R7, 0x80000000, R9, 0x48, !PT ; /* 0x8000000007097812 */
/* 0x000fc800078e4809 */
/*0540*/ LOP3.LUT R19, R9, R19, RZ, 0xfc, !PT ; /* 0x0000001309137212 */
/* 0x000fce00078efcff */
/*0550*/ @!P0 BRA 0x710 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0560*/ IMAD.MOV R7, RZ, RZ, -R11 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a0b */
/*0570*/ IADD3 R11, -R11, -0x43300000, RZ ; /* 0xbcd000000b0b7810 */
/* 0x000fe20007ffe1ff */
/*0580*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fcc00078e00ff */
/*0590*/ DFMA R6, R16, -R6, R14 ; /* 0x800000061006722b */
/* 0x000e08000000000e */
/*05a0*/ DMUL.RP R14, R14, R18 ; /* 0x000000120e0e7228 */
/* 0x000e4c0000008000 */
/*05b0*/ FSETP.NEU.AND P0, PT, |R7|, R11, PT ; /* 0x0000000b0700720b */
/* 0x001fc80003f0d200 */
/*05c0*/ LOP3.LUT R9, R15, R9, RZ, 0x3c, !PT ; /* 0x000000090f097212 */
/* 0x002fe400078e3cff */
/*05d0*/ FSEL R16, R14, R16, !P0 ; /* 0x000000100e107208 */
/* 0x000fe40004000000 */
/*05e0*/ FSEL R17, R9, R17, !P0 ; /* 0x0000001109117208 */
/* 0x000fe20004000000 */
/*05f0*/ BRA 0x710 ; /* 0x0000011000007947 */
/* 0x000fea0003800000 */
/*0600*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e9c0003f08000 */
/*0610*/ @P0 BRA 0x6f0 ; /* 0x000000d000000947 */
/* 0x004fea0003800000 */
/*0620*/ ISETP.NE.AND P0, PT, R11, R22, PT ; /* 0x000000160b00720c */
/* 0x000fe20003f05270 */
/*0630*/ IMAD.MOV.U32 R16, RZ, RZ, 0x0 ; /* 0x00000000ff107424 */
/* 0x000fe400078e00ff */
/*0640*/ IMAD.MOV.U32 R17, RZ, RZ, -0x80000 ; /* 0xfff80000ff117424 */
/* 0x000fd400078e00ff */
/*0650*/ @!P0 BRA 0x710 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0660*/ ISETP.NE.AND P0, PT, R11, 0x7ff00000, PT ; /* 0x7ff000000b00780c */
/* 0x000fe40003f05270 */
/*0670*/ LOP3.LUT R8, R9, 0x40100000, RZ, 0x3c, !PT ; /* 0x4010000009087812 */
/* 0x000fe400078e3cff */
/*0680*/ ISETP.EQ.OR P0, PT, R22, RZ, !P0 ; /* 0x000000ff1600720c */
/* 0x000fe40004702670 */
/*0690*/ LOP3.LUT R17, R8, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000008117812 */
/* 0x000fd600078ec0ff */
/*06a0*/ @P0 LOP3.LUT R6, R17, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000011060812 */
/* 0x000fe200078efcff */
/*06b0*/ @!P0 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff108224 */
/* 0x000fe400078e00ff */
/*06c0*/ @P0 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff100224 */
/* 0x000fe400078e00ff */
/*06d0*/ @P0 IMAD.MOV.U32 R17, RZ, RZ, R6 ; /* 0x000000ffff110224 */
/* 0x000fe200078e0006 */
/*06e0*/ BRA 0x710 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*06f0*/ LOP3.LUT R17, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000009117812 */
/* 0x000fe200078efcff */
/*0700*/ IMAD.MOV.U32 R16, RZ, RZ, R8 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0008 */
/*0710*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0720*/ IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; /* 0x00000000ff0b7424 */
/* 0x000fe400078e00ff */
/*0730*/ IMAD.MOV.U32 R6, RZ, RZ, R16 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0010 */
/*0740*/ IMAD.MOV.U32 R7, RZ, RZ, R17 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0011 */
/*0750*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff8a00a007950 */
/* 0x000fec0003c3ffff */
/*0760*/ BRA 0x760; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5gpuPiPddi
.globl _Z5gpuPiPddi
.p2align 8
.type _Z5gpuPiPddi,@function
_Z5gpuPiPddi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x10
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s7, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s6, v1
s_cbranch_execz .LBB0_4
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s5, s[4:5], 0x0
s_mov_b32 s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_mul_i32 s5, s5, s7
s_mov_b32 s1, 0x3fe33333
s_mov_b32 s0, 0x33333333
global_load_b64 v[4:5], v[2:3], off
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_cvt_f64_i32_e32 v[6:7], v1
v_add_nc_u32_e32 v1, s5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[6:7], s[0:1]
v_mul_f64 v[6:7], v[6:7], s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[6:7], 1.0
v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], 4.0
v_div_scale_f64 v[14:15], vcc_lo, 4.0, v[6:7], 4.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[10:11], v[8:9]
s_waitcnt_depctr 0xfff
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[14:15], v[10:11]
v_fma_f64 v[8:9], -v[8:9], v[12:13], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[12:13]
v_cmp_le_i32_e32 vcc_lo, s6, v1
s_or_b32 s4, vcc_lo, s4
v_div_fixup_f64 v[6:7], v[8:9], v[6:7], 4.0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[4:5], v[6:7], v[4:5]
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_2
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s4
global_store_b64 v[2:3], v[4:5], off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5gpuPiPddi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5gpuPiPddi, .Lfunc_end0-_Z5gpuPiPddi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5gpuPiPddi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5gpuPiPddi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00025ad9_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z5gpuPiPddiPddi
.type _Z26__device_stub__Z5gpuPiPddiPddi, @function
_Z26__device_stub__Z5gpuPiPddiPddi:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movsd %xmm0, 16(%rsp)
movl %esi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5gpuPiPddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z5gpuPiPddiPddi, .-_Z26__device_stub__Z5gpuPiPddiPddi
.globl _Z5gpuPiPddi
.type _Z5gpuPiPddi, @function
_Z5gpuPiPddi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z5gpuPiPddiPddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5gpuPiPddi, .-_Z5gpuPiPddi
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "PI: %lf\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4096000, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4096000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4096000, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 28(%rsp)
movl $1, 32(%rsp)
movl $1000, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
movl $2, %ecx
movl $4096000, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 4096000(%rbx), %rdx
pxor %xmm0, %xmm0
.L13:
addsd (%rax), %xmm0
addq $8, %rax
cmpq %rdx, %rax
jne .L13
mulsd .LC1(%rip), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $1000000, %esi
movsd .LC1(%rip), %xmm0
movq 8(%rsp), %rdi
call _Z26__device_stub__Z5gpuPiPddiPddi
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z5gpuPiPddi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z5gpuPiPddi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "main.hip"
.globl _Z20__device_stub__gpuPiPddi # -- Begin function _Z20__device_stub__gpuPiPddi
.p2align 4, 0x90
.type _Z20__device_stub__gpuPiPddi,@function
_Z20__device_stub__gpuPiPddi: # @_Z20__device_stub__gpuPiPddi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movsd %xmm0, 64(%rsp)
movl %esi, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5gpuPiPddi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z20__device_stub__gpuPiPddi, .Lfunc_end0-_Z20__device_stub__gpuPiPddi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
movl $4096000, %edi # imm = 0x3E8000
callq malloc
movq %rax, %rbx
movq %rsp, %rdi
movl $4096000, %esi # imm = 0x3E8000
callq hipMalloc
movq (%rsp), %rdi
movl $4096000, %edx # imm = 0x3E8000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967808, %rdx # imm = 0x100000200
leaq 488(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movq %rax, 72(%rsp)
movabsq $4517329193108106637, %rax # imm = 0x3EB0C6F7A0B5ED8D
movq %rax, 64(%rsp)
movl $1000000, 12(%rsp) # imm = 0xF4240
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5gpuPiPddi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movl $4096000, %edx # imm = 0x3E8000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorpd %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
addsd (%rbx,%rax,8), %xmm0
incq %rax
cmpq $512000, %rax # imm = 0x7D000
jne .LBB1_3
# %bb.4:
mulsd .LCPI1_0(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5gpuPiPddi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5gpuPiPddi,@object # @_Z5gpuPiPddi
.section .rodata,"a",@progbits
.globl _Z5gpuPiPddi
.p2align 3, 0x0
_Z5gpuPiPddi:
.quad _Z20__device_stub__gpuPiPddi
.size _Z5gpuPiPddi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "PI: %lf\n"
.size .L.str, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5gpuPiPddi"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__gpuPiPddi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5gpuPiPddi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__device__ bool checkBoundary(int blockIdx, int blockDim, int threadIdx){
int x = threadIdx;
int y = blockIdx;
return (x == 0 || x == (blockDim-1) || y == 0 || y == 479);
}
__global__ void mSetFieldBoundary(float *field, float scalar) {
if(checkBoundary(blockIdx.x, blockDim.x, threadIdx.x)) {
int Idx = blockIdx.x * blockDim.x + threadIdx.x;
int x = threadIdx.x;
int y = blockIdx.x;
if(x == 0 && y == 0) {
field[Idx] = field[Idx+blockDim.x+1]*scalar;
} else if(x == 0 && y == blockDim.x-1) {
field[Idx] = field[Idx-blockDim.x+1]*scalar;
} else if (x == blockDim.x-1 && y == 0) {
field[Idx] = field[Idx+blockDim.x-1]*scalar;
} else if (x == blockDim.x-1 && y == blockDim.x-1) {
field[Idx] = field[Idx-blockDim.x-1]*scalar;
} else if (x == 0) {
field[Idx] = field[Idx+1]*scalar;
} else if(x == blockDim.x-1) {
field[Idx] = field[Idx-1]*scalar;
} else if(y == 0) {
field[Idx] = field[Idx+blockDim.x]*scalar;
} else field[Idx] = field[Idx-blockDim.x]*scalar;
} else return;
}
|
code for sm_80
Function : _Z17mSetFieldBoundaryPff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e6a0000002500 */
/*0050*/ ISETP.NE.AND P0, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x001fc8000bf05270 */
/*0060*/ ISETP.NE.AND P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fe40000705270 */
/*0070*/ ISETP.NE.AND P1, PT, R4.reuse, 0x1df, PT ; /* 0x000001df0400780c */
/* 0x042fe40003f25270 */
/*0080*/ ISETP.NE.AND P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705270 */
/*0090*/ @P0 EXIT P1 ; /* 0x000000000000094d */
/* 0x000fea0000800000 */
/*00a0*/ LOP3.LUT P0, RZ, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405ff7212 */
/* 0x000fe2000780fcff */
/*00b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*00c0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ IMAD R0, R4, c[0x0][0x0], R5 ; /* 0x0000000004007a24 */
/* 0x000fc800078e0205 */
/*00e0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0207 */
/*00f0*/ @!P0 BRA 0x460 ; /* 0x0000036000008947 */
/* 0x000fea0003800000 */
/*0100*/ ISETP.NE.AND P1, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fe4000bf25270 */
/*0110*/ ISETP.EQ.AND P2, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720c */
/* 0x040fe40003f42270 */
/*0120*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fd60003f05270 */
/*0130*/ @!P1 BRA P2, 0x3f0 ; /* 0x000002b000009947 */
/* 0x000fea0001000000 */
/*0140*/ ISETP.EQ.AND P4, PT, R4.reuse, RZ, PT ; /* 0x000000ff0400720c */
/* 0x040fe40003f82270 */
/*0150*/ ISETP.NE.AND P3, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fe4000bf65270 */
/*0160*/ ISETP.NE.AND P2, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fd60003f45270 */
/*0170*/ @!P3 BRA P4, 0x390 ; /* 0x000002100000b947 */
/* 0x000fea0002000000 */
/*0180*/ ISETP.EQ.AND P4, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fda000bf82270 */
/*0190*/ @!P1 BRA P4, 0x310 ; /* 0x0000017000009947 */
/* 0x000fea0002000000 */
/*01a0*/ @!P0 BRA 0x2d0 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*01b0*/ @!P3 BRA 0x290 ; /* 0x000000d00000b947 */
/* 0x000fea0003800000 */
/*01c0*/ @!P2 BRA 0x230 ; /* 0x000000600000a947 */
/* 0x000fea0003800000 */
/*01d0*/ IADD3 R4, R0, -c[0x0][0x0], RZ ; /* 0x8000000000047a10 */
/* 0x000fca0007ffe0ff */
/*01e0*/ IMAD.WIDE.U32 R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0007 */
/*01f0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea4000c1e1900 */
/*0200*/ FMUL R7, R4, c[0x0][0x168] ; /* 0x00005a0004077a20 */
/* 0x004fca0000400000 */
/*0210*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ IADD3 R4, R0, c[0x0][0x0], RZ ; /* 0x0000000000047a10 */
/* 0x000fca0007ffe0ff */
/*0240*/ IMAD.WIDE.U32 R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0007 */
/*0250*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea4000c1e1900 */
/*0260*/ FMUL R7, R4, c[0x0][0x168] ; /* 0x00005a0004077a20 */
/* 0x004fca0000400000 */
/*0270*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ LDG.E R0, [R2.64+-0x4] ; /* 0xfffffc0602007981 */
/* 0x000ea4000c1e1900 */
/*02a0*/ FMUL R5, R0, c[0x0][0x168] ; /* 0x00005a0000057a20 */
/* 0x004fca0000400000 */
/*02b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*02c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02d0*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040602007981 */
/* 0x000ea4000c1e1900 */
/*02e0*/ FMUL R5, R0, c[0x0][0x168] ; /* 0x00005a0000057a20 */
/* 0x004fca0000400000 */
/*02f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*0300*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0310*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe40000000800 */
/*0320*/ ULOP3.LUT UR5, URZ, UR5, URZ, 0x33, !UPT ; /* 0x000000053f057292 */
/* 0x000fcc000f8e333f */
/*0330*/ IADD3 R4, R0, UR5, RZ ; /* 0x0000000500047c10 */
/* 0x000fca000fffe0ff */
/*0340*/ IMAD.WIDE.U32 R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0007 */
/*0350*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea4000c1e1900 */
/*0360*/ FMUL R7, R4, c[0x0][0x168] ; /* 0x00005a0004077a20 */
/* 0x004fca0000400000 */
/*0370*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*0380*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0390*/ IADD3 R4, R0, R5, RZ ; /* 0x0000000500047210 */
/* 0x000fca0007ffe0ff */
/*03a0*/ IMAD.WIDE.U32 R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0007 */
/*03b0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea4000c1e1900 */
/*03c0*/ FMUL R7, R4, c[0x0][0x168] ; /* 0x00005a0004077a20 */
/* 0x004fca0000400000 */
/*03d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*03e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03f0*/ HFMA2.MMA R5, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff057435 */
/* 0x000fd400000001ff */
/*0400*/ IADD3 R4, R0, -c[0x0][0x0], R5 ; /* 0x8000000000047a10 */
/* 0x000fca0007ffe005 */
/*0410*/ IMAD.WIDE.U32 R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0007 */
/*0420*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea4000c1e1900 */
/*0430*/ FMUL R7, R4, c[0x0][0x168] ; /* 0x00005a0004077a20 */
/* 0x004fca0000400000 */
/*0440*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*0450*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0460*/ IADD3.X R4, R0, c[0x0][0x0], RZ, PT, !PT ; /* 0x0000000000047a10 */
/* 0x000fca0003ffe4ff */
/*0470*/ IMAD.WIDE.U32 R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0007 */
/*0480*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea4000c1e1900 */
/*0490*/ FMUL R7, R4, c[0x0][0x168] ; /* 0x00005a0004077a20 */
/* 0x004fca0000400000 */
/*04a0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*04b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04c0*/ BRA 0x4c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
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