system
stringclasses 7
values | input
stringlengths 10
94.5k
| output
stringlengths 14
55.5k
|
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <random>
int getRandom(int n) {
std::random_device rd;
std::mt19937 gen(rd());
std::uniform_int_distribution<> dis(0, n);
return dis(gen);
}
__global__
void check(int *fDictX, int *fDictY, int sizeOfFDict, int *currInjective) {
int idxInit = blockIdx.x * blockDim.x + threadIdx.x; // this is the initial global index
if (idxInit < sizeOfFDict) { // make sure we're not out of bounds
// grid-stride loop
for (int idx = idxInit; idx <= sizeOfFDict; idx += blockDim.x * gridDim.x) {
// this inner loop will do the work for a thread in each grid
for (int i=idx; i < sizeOfFDict; i++) {
if (fDictY[idx] == fDictY[i] && fDictX[idx] != fDictX[i]) {
currInjective[idx] = 0; // this will insert a zero into INJECTIVE
break;
}
}
}
}
}
extern "C" {
int injective(int maxDomain, int maxCodomain) {
// declare the arrays
int *domainX, *domainY, *INJECTIVE;
// allocated Unified Memory
hipMallocManaged(&domainX, maxDomain*sizeof(int));
hipMallocManaged(&domainY, maxDomain*sizeof(int));
hipMallocManaged(&INJECTIVE, maxDomain*sizeof(int));
// initialize function
for (int i = 0; i < maxDomain; i++) {
domainX[i] = i;
domainY[i] = getRandom(maxCodomain);
INJECTIVE[i] = 1; // here we assume that the function is injective
}
// actually make the kernel call
// this is currently running with thread blocks of size 256. I may find a better number
// to tune that too. It's <<< numBlocks, numThreads >>>
check<<<(maxDomain+255)/256, 256>>>(domainX, domainY, maxDomain, INJECTIVE);
hipDeviceSynchronize(); // sync the host and device
// error checking
if (hipSuccess != hipGetLastError()) {
hipFree(domainX);
hipFree(domainY);
hipFree(INJECTIVE);
return -1; // this will be used to raise a RuntimeError
}
// free the unified memory
hipFree(domainX);
hipFree(domainY);
for (int i = 0; i < maxDomain; i++) {
if (INJECTIVE[i] == 0) { // 0 => false so the function is not injective
hipFree(INJECTIVE);
return 0;
}
}
hipFree(INJECTIVE);
return 1; // the function is injective
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5checkPiS_iS_
.globl _Z5checkPiS_iS_
.p2align 8
.type _Z5checkPiS_iS_,@function
_Z5checkPiS_iS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_12
s_load_b32 s10, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x18
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s10, s9
s_mov_b32 s9, 0
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s10
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_lt_i32_e32 vcc_lo, s8, v1
s_or_b32 s9, vcc_lo, s9
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execz .LBB0_12
.LBB0_3:
s_mov_b32 s10, exec_lo
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v11, v1
s_mov_b32 s11, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
global_load_b32 v10, v[4:5], off
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, exec_lo, s0
s_or_b32 s11, s0, s11
s_and_not1_b32 s0, s12, exec_lo
s_and_b32 s12, s13, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s12, s0, s12
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB0_10
.LBB0_6:
global_load_b32 v12, v[4:5], off
s_mov_b32 s0, -1
s_mov_b32 s15, -1
s_mov_b32 s16, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 v10, v12
s_cbranch_execz .LBB0_8
global_load_b32 v12, v[6:7], off
global_load_b32 v13, v[8:9], off
s_mov_b32 s14, -1
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v12, v13
s_or_not1_b32 s15, vcc_lo, exec_lo
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s13, s13, exec_lo
s_and_b32 s14, s14, exec_lo
s_or_b32 s13, s13, s14
s_and_saveexec_b32 s14, s15
s_cbranch_execz .LBB0_5
v_add_nc_u32_e32 v11, 1, v11
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, s8, v11
v_add_co_u32 v8, s0, v8, 4
v_add_co_ci_u32_e64 v9, s0, 0, v9, s0
s_and_not1_b32 s13, s13, exec_lo
s_or_not1_b32 s0, vcc_lo, exec_lo
s_branch .LBB0_5
.LBB0_10:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s11
s_and_saveexec_b32 s0, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_2
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[2:3], v0, off
s_branch .LBB0_2
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5checkPiS_iS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5checkPiS_iS_, .Lfunc_end0-_Z5checkPiS_iS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5checkPiS_iS_
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z5checkPiS_iS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <random>
int getRandom(int n) {
std::random_device rd;
std::mt19937 gen(rd());
std::uniform_int_distribution<> dis(0, n);
return dis(gen);
}
__global__
void check(int *fDictX, int *fDictY, int sizeOfFDict, int *currInjective) {
int idxInit = blockIdx.x * blockDim.x + threadIdx.x; // this is the initial global index
if (idxInit < sizeOfFDict) { // make sure we're not out of bounds
// grid-stride loop
for (int idx = idxInit; idx <= sizeOfFDict; idx += blockDim.x * gridDim.x) {
// this inner loop will do the work for a thread in each grid
for (int i=idx; i < sizeOfFDict; i++) {
if (fDictY[idx] == fDictY[i] && fDictX[idx] != fDictX[i]) {
currInjective[idx] = 0; // this will insert a zero into INJECTIVE
break;
}
}
}
}
}
extern "C" {
int injective(int maxDomain, int maxCodomain) {
// declare the arrays
int *domainX, *domainY, *INJECTIVE;
// allocated Unified Memory
hipMallocManaged(&domainX, maxDomain*sizeof(int));
hipMallocManaged(&domainY, maxDomain*sizeof(int));
hipMallocManaged(&INJECTIVE, maxDomain*sizeof(int));
// initialize function
for (int i = 0; i < maxDomain; i++) {
domainX[i] = i;
domainY[i] = getRandom(maxCodomain);
INJECTIVE[i] = 1; // here we assume that the function is injective
}
// actually make the kernel call
// this is currently running with thread blocks of size 256. I may find a better number
// to tune that too. It's <<< numBlocks, numThreads >>>
check<<<(maxDomain+255)/256, 256>>>(domainX, domainY, maxDomain, INJECTIVE);
hipDeviceSynchronize(); // sync the host and device
// error checking
if (hipSuccess != hipGetLastError()) {
hipFree(domainX);
hipFree(domainY);
hipFree(INJECTIVE);
return -1; // this will be used to raise a RuntimeError
}
// free the unified memory
hipFree(domainX);
hipFree(domainY);
for (int i = 0; i < maxDomain; i++) {
if (INJECTIVE[i] == 0) { // 0 => false so the function is not injective
hipFree(INJECTIVE);
return 0;
}
}
hipFree(INJECTIVE);
return 1; // the function is injective
}
}
|
.text
.file "checkInjective.hip"
.globl _Z9getRandomi # -- Begin function _Z9getRandomi
.p2align 4, 0x90
.type _Z9getRandomi,@function
_Z9getRandomi: # @_Z9getRandomi
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $10008, %rsp # imm = 0x2718
.cfi_def_cfa_offset 10032
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edi, %ebx
leaq 24(%rsp), %r14
movq %r14, 8(%rsp)
movl $1634100580, 24(%rsp) # imm = 0x61666564
movl $1953264993, 27(%rsp) # imm = 0x746C7561
movq $7, 16(%rsp)
movb $0, 31(%rsp)
.Ltmp0:
leaq 5008(%rsp), %rdi
leaq 8(%rsp), %rsi
callq _ZNSt13random_device7_M_initERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp1:
# %bb.1:
movq 8(%rsp), %rdi
cmpq %r14, %rdi
je .LBB0_3
# %bb.2: # %.critedge.i.i.i
callq _ZdlPv
.LBB0_3: # %_ZNSt13random_deviceC2Ev.exit
.Ltmp3:
leaq 5008(%rsp), %rdi
callq _ZNSt13random_device9_M_getvalEv
.Ltmp4:
# %bb.4: # %_ZNSt13random_deviceclEv.exit
movl %eax, %eax
movq %rax, 8(%rsp)
movl $1, %ecx
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
movq %rax, %rdx
shrq $30, %rdx
xorl %eax, %edx
imull $1812433253, %edx, %eax # imm = 0x6C078965
addl %ecx, %eax
movq %rax, 8(%rsp,%rcx,8)
incq %rcx
cmpq $624, %rcx # imm = 0x270
jne .LBB0_5
# %bb.6: # %_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEC2Em.exit
movq $624, 5000(%rsp) # imm = 0x270
movl $0, (%rsp)
movl %ebx, 4(%rsp)
.Ltmp6:
leaq 8(%rsp), %rsi
movq %rsp, %rdi
movq %rdi, %rdx
callq _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.Ltmp7:
# %bb.7: # %_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_.exit
.Ltmp12:
movl %eax, %ebx
leaq 5008(%rsp), %rdi
callq _ZNSt13random_device7_M_finiEv
.Ltmp13:
# %bb.8: # %_ZNSt13random_deviceD2Ev.exit
movl %ebx, %eax
addq $10008, %rsp # imm = 0x2718
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_12:
.cfi_def_cfa_offset 10032
.Ltmp14:
movq %rax, %rdi
callq __clang_call_terminate
.LBB0_14:
.Ltmp8:
jmp .LBB0_15
.LBB0_13:
.Ltmp5:
.LBB0_15:
movq %rax, %rbx
.Ltmp9:
leaq 5008(%rsp), %rdi
callq _ZNSt13random_device7_M_finiEv
.Ltmp10:
jmp .LBB0_11
.LBB0_16:
.Ltmp11:
movq %rax, %rdi
callq __clang_call_terminate
.LBB0_9:
.Ltmp2:
movq %rax, %rbx
movq 8(%rsp), %rdi
cmpq %r14, %rdi
je .LBB0_11
# %bb.10: # %.critedge.i.i6.i
callq _ZdlPv
.LBB0_11: # %common.resume
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size _Z9getRandomi, .Lfunc_end0-_Z9getRandomi
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14
.byte 1 # On action: 1
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 1 # On action: 1
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Lfunc_end0-.Ltmp10 # Call between .Ltmp10 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.text
.globl _Z20__device_stub__checkPiS_iS_ # -- Begin function _Z20__device_stub__checkPiS_iS_
.p2align 4, 0x90
.type _Z20__device_stub__checkPiS_iS_,@function
_Z20__device_stub__checkPiS_iS_: # @_Z20__device_stub__checkPiS_iS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5checkPiS_iS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z20__device_stub__checkPiS_iS_, .Lfunc_end1-_Z20__device_stub__checkPiS_iS_
.cfi_endproc
# -- End function
.globl injective # -- Begin function injective
.p2align 4, 0x90
.type injective,@function
injective: # @injective
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movl %edi, %ebx
movslq %edi, %r15
leaq (,%r15,4), %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movq %r14, %rsi
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movq %r14, %rsi
movl $1, %edx
callq hipMallocManaged
testl %r15d, %r15d
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %ebx, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq 24(%rsp), %rax
movl %r15d, (%rax,%r15,4)
movl %ebp, %edi
callq _Z9getRandomi
movq 16(%rsp), %rcx
movl %eax, (%rcx,%r15,4)
movq 8(%rsp), %rax
movl $1, (%rax,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB2_2
.LBB2_3: # %._crit_edge
leal 255(%rbx), %eax
leal 510(%rbx), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $8, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl %ebx, 36(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z5checkPiS_iS_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
callq hipDeviceSynchronize
callq hipGetLastError
movl %eax, %ebp
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
testl %ebp, %ebp
je .LBB2_7
# %bb.6:
movl $-1, %ebx
jmp .LBB2_12
.LBB2_7:
testl %ebx, %ebx
jle .LBB2_11
# %bb.8: # %.lr.ph34
movq 8(%rsp), %rdi
movl %ebx, %eax
xorl %ebx, %ebx
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_10: # =>This Inner Loop Header: Depth=1
cmpl $0, (%rdi,%rcx,4)
je .LBB2_13
# %bb.9: # in Loop: Header=BB2_10 Depth=1
incq %rcx
cmpq %rcx, %rax
jne .LBB2_10
.LBB2_11: # %.critedge
movl $1, %ebx
.LBB2_12: # %.loopexit
movq 8(%rsp), %rdi
.LBB2_13: # %.loopexit
callq hipFree
movl %ebx, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size injective, .Lfunc_end2-injective
.cfi_endproc
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end3:
.size __clang_call_terminate, .Lfunc_end3-__clang_call_terminate
.cfi_endproc
# -- End function
.section .text._ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,"axG",@progbits,_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,comdat
.weak _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE # -- Begin function _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.p2align 4, 0x90
.type _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,@function
_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE: # @_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movslq 4(%rdx), %r15
movq %rdx, 8(%rsp) # 8-byte Spill
movslq (%rdx), %rax
subq %rax, %r15
movl $4294967294, %eax # imm = 0xFFFFFFFE
cmpq %rax, %r15
ja .LBB4_6
# %bb.1:
leal 1(%r15), %r12d
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %r12, %rax
cmpl %eax, %r12d
jbe .LBB4_5
# %bb.2:
notl %r15d
movq %rax, %rcx
movl %r15d, %eax
xorl %edx, %edx
divl %r12d
movq %rcx, %rax
cmpl %eax, %edx
jbe .LBB4_5
# %bb.3: # %.lr.ph.i.preheader
movl %edx, %ebp
.p2align 4, 0x90
.LBB4_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %r12, %rax
cmpl %eax, %ebp
ja .LBB4_4
.LBB4_5: # %_ZNSt24uniform_int_distributionIiE5_S_ndImSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEjEET1_RT0_S4_.exit
shrq $32, %rax
jmp .LBB4_11
.LBB4_6:
movl $4294967295, %eax # imm = 0xFFFFFFFF
cmpq %rax, %r15
jne .LBB4_7
# %bb.10:
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
jmp .LBB4_11
.LBB4_7: # %.preheader
movq %rdi, %r12
movabsq $-4294967296, %rbx # imm = 0xFFFFFFFF00000000
leaq 16(%rsp), %r13
.p2align 4, 0x90
.LBB4_8: # =>This Inner Loop Header: Depth=1
movq %rbx, 16(%rsp)
movq %r12, %rdi
movq %r14, %rsi
movq %r13, %rdx
callq _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
movl %eax, %ebp
shlq $32, %rbp
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
addq %rbp, %rax
setb %cl
cmpq %r15, %rax
ja .LBB4_8
# %bb.9: # in Loop: Header=BB4_8 Depth=1
testb %cl, %cl
jne .LBB4_8
.LBB4_11: # %.loopexit
movq 8(%rsp), %rcx # 8-byte Reload
addl (%rcx), %eax
# kill: def $eax killed $eax killed $rax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE, .Lfunc_end4-_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.cfi_endproc
# -- End function
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,comdat
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv # -- Begin function _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.p2align 4, 0x90
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,@function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv: # @_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.cfi_startproc
# %bb.0:
cmpq $624, 4992(%rdi) # imm = 0x270
jb .LBB5_6
# %bb.1: # %.preheader.preheader
movl $2567483615, %eax # imm = 0x9908B0DF
xorl %edx, %edx
movq $-2147483648, %rcx # imm = 0x80000000
.p2align 4, 0x90
.LBB5_2: # %.preheader
# =>This Inner Loop Header: Depth=1
movq (%rdi,%rdx,8), %rsi
andq %rcx, %rsi
movq 8(%rdi,%rdx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq 3176(%rdi,%rdx,8), %r9
andl $1, %r8d
negl %r8d
andl %eax, %r8d
xorq %r9, %r8
movq %r8, (%rdi,%rdx,8)
leaq 1(%rdx), %rsi
movq %rsi, %rdx
cmpq $227, %rsi
jne .LBB5_2
# %bb.3: # %.preheader.i.preheader
movl $228, %ecx
movq $-2147483648, %rdx # imm = 0x80000000
.p2align 4, 0x90
.LBB5_4: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movq -8(%rdi,%rcx,8), %rsi
andq %rdx, %rsi
movq (%rdi,%rcx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq -1824(%rdi,%rcx,8), %r9
andl $1, %r8d
negl %r8d
andl %eax, %r8d
xorq %r9, %r8
movq %r8, -8(%rdi,%rcx,8)
incq %rcx
cmpq $624, %rcx # imm = 0x270
jne .LBB5_4
# %bb.5: # %_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv.exit
movq $-2147483648, %rcx # imm = 0x80000000
andq 4984(%rdi), %rcx
movq (%rdi), %rdx
movl %edx, %esi
andl $2147483646, %esi # imm = 0x7FFFFFFE
orq %rcx, %rsi
shrq %rsi
xorq 3168(%rdi), %rsi
andl $1, %edx
negl %edx
andl %eax, %edx
xorq %rsi, %rdx
movq %rdx, 4984(%rdi)
movq $0, 4992(%rdi)
.LBB5_6:
movq 4992(%rdi), %rax
leaq 1(%rax), %rcx
movq %rcx, 4992(%rdi)
movq (%rdi,%rax,8), %rax
movq %rax, %rcx
shrq $11, %rcx
movl %ecx, %ecx
xorq %rax, %rcx
movl %ecx, %eax
shll $7, %eax
andl $-1658038656, %eax # imm = 0x9D2C5680
xorq %rcx, %rax
movl %eax, %ecx
shll $15, %ecx
andl $-272236544, %ecx # imm = 0xEFC60000
xorq %rax, %rcx
movq %rcx, %rax
shrq $18, %rax
xorq %rcx, %rax
retq
.Lfunc_end5:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, .Lfunc_end5-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5checkPiS_iS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5checkPiS_iS_,@object # @_Z5checkPiS_iS_
.section .rodata,"a",@progbits
.globl _Z5checkPiS_iS_
.p2align 3, 0x0
_Z5checkPiS_iS_:
.quad _Z20__device_stub__checkPiS_iS_
.size _Z5checkPiS_iS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "default"
.size .L.str, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5checkPiS_iS_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Z20__device_stub__checkPiS_iS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z5checkPiS_iS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z5checkPiS_iS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06270 */
/*0080*/ BSSY B0, 0x270 ; /* 0x000001e000007945 */
/* 0x000fd80003800000 */
/*0090*/ @P0 BRA 0x260 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*00b0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0205 */
/*00c0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000162000c1e1900 */
/*00d0*/ SHF.R.S32.HI R9, RZ, 0x1f, R0.reuse ; /* 0x0000001fff097819 */
/* 0x100fe20000011400 */
/*00e0*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0000 */
/*00f0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0205 */
/*0100*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x001fc800078e00ff */
/*0110*/ IMAD.WIDE R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fcc00078e0203 */
/*0120*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0130*/ BSSY B1, 0x1f0 ; /* 0x000000b000017945 */
/* 0x000fe20003800000 */
/*0140*/ ISETP.NE.AND P0, PT, R11, R2, PT ; /* 0x000000020b00720c */
/* 0x024fda0003f05270 */
/*0150*/ @P0 BRA 0x1e0 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0160*/ SHF.R.S32.HI R3, RZ, 0x1f, R6 ; /* 0x0000001fff037819 */
/* 0x000fe20000011406 */
/*0170*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea2000c1e1900 */
/*0180*/ LEA R2, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006027a11 */
/* 0x000fc800078010ff */
/*0190*/ LEA.HI.X R3, R6, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590006037a11 */
/* 0x000fca00000f1403 */
/*01a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*01b0*/ ISETP.NE.AND P0, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x004fda0003f05270 */
/*01c0*/ @P0 BREAK B1 ; /* 0x0000000000010942 */
/* 0x000fe20003800000 */
/*01d0*/ @P0 BRA 0x230 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*01e0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*01f0*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fc80007ffe0ff */
/*0200*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fda0003f06270 */
/*0210*/ @!P0 BRA 0x100 ; /* 0xfffffee000008947 */
/* 0x000fea000383ffff */
/*0220*/ BRA 0x260 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0230*/ LEA R2, P0, R0, c[0x0][0x178], 0x2 ; /* 0x00005e0000027a11 */
/* 0x000fc800078010ff */
/*0240*/ LEA.HI.X R3, R0, c[0x0][0x17c], R9, 0x2, P0 ; /* 0x00005f0000037a11 */
/* 0x000fca00000f1409 */
/*0250*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e8000c101904 */
/*0260*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0270*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x001fc800078e00ff */
/*0280*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x000fca00078e0200 */
/*0290*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f04270 */
/*02a0*/ @!P0 BRA 0x70 ; /* 0xfffffdc000008947 */
/* 0x000fea000383ffff */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5checkPiS_iS_
.globl _Z5checkPiS_iS_
.p2align 8
.type _Z5checkPiS_iS_,@function
_Z5checkPiS_iS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_12
s_load_b32 s10, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x18
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s10, s9
s_mov_b32 s9, 0
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s10
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_lt_i32_e32 vcc_lo, s8, v1
s_or_b32 s9, vcc_lo, s9
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execz .LBB0_12
.LBB0_3:
s_mov_b32 s10, exec_lo
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v11, v1
s_mov_b32 s11, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
global_load_b32 v10, v[4:5], off
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, exec_lo, s0
s_or_b32 s11, s0, s11
s_and_not1_b32 s0, s12, exec_lo
s_and_b32 s12, s13, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s12, s0, s12
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB0_10
.LBB0_6:
global_load_b32 v12, v[4:5], off
s_mov_b32 s0, -1
s_mov_b32 s15, -1
s_mov_b32 s16, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 v10, v12
s_cbranch_execz .LBB0_8
global_load_b32 v12, v[6:7], off
global_load_b32 v13, v[8:9], off
s_mov_b32 s14, -1
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v12, v13
s_or_not1_b32 s15, vcc_lo, exec_lo
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s13, s13, exec_lo
s_and_b32 s14, s14, exec_lo
s_or_b32 s13, s13, s14
s_and_saveexec_b32 s14, s15
s_cbranch_execz .LBB0_5
v_add_nc_u32_e32 v11, 1, v11
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, s8, v11
v_add_co_u32 v8, s0, v8, 4
v_add_co_ci_u32_e64 v9, s0, 0, v9, s0
s_and_not1_b32 s13, s13, exec_lo
s_or_not1_b32 s0, vcc_lo, exec_lo
s_branch .LBB0_5
.LBB0_10:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s11
s_and_saveexec_b32 s0, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_2
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[2:3], v0, off
s_branch .LBB0_2
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5checkPiS_iS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5checkPiS_iS_, .Lfunc_end0-_Z5checkPiS_iS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5checkPiS_iS_
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z5checkPiS_iS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001723c8_00000000-6_checkInjective.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4145:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4145:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z5checkPiS_iS_PiS_iS_
.type _Z29__device_stub__Z5checkPiS_iS_PiS_iS_, @function
_Z29__device_stub__Z5checkPiS_iS_PiS_iS_:
.LFB4167:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5checkPiS_iS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4167:
.size _Z29__device_stub__Z5checkPiS_iS_PiS_iS_, .-_Z29__device_stub__Z5checkPiS_iS_PiS_iS_
.globl _Z5checkPiS_iS_
.type _Z5checkPiS_iS_, @function
_Z5checkPiS_iS_:
.LFB4168:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5checkPiS_iS_PiS_iS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4168:
.size _Z5checkPiS_iS_, .-_Z5checkPiS_iS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5checkPiS_iS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4170:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5checkPiS_iS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4170:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv,comdat
.align 2
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv, @function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv:
.LFB4804:
.cfi_startproc
endbr64
movq %rdi, %rdx
leaq 1816(%rdi), %r9
movq %rdi, %rcx
movl $2567483615, %r8d
.L15:
movq (%rcx), %rax
andq $-2147483648, %rax
movq 8(%rcx), %rsi
andl $2147483647, %esi
orq %rsi, %rax
movq %rax, %rsi
shrq %rsi
xorq 3176(%rcx), %rsi
andl $1, %eax
cmovne %r8, %rax
xorq %rsi, %rax
movq %rax, (%rcx)
addq $8, %rcx
cmpq %r9, %rcx
jne .L15
leaq 3168(%rdi), %r8
movl $2567483615, %esi
.L17:
movq 1816(%rdx), %rax
andq $-2147483648, %rax
movq 1824(%rdx), %rcx
andl $2147483647, %ecx
orq %rcx, %rax
movq %rax, %rcx
shrq %rcx
xorq (%rdx), %rcx
andl $1, %eax
cmovne %rsi, %rax
xorq %rcx, %rax
movq %rax, 1816(%rdx)
addq $8, %rdx
cmpq %r8, %rdx
jne .L17
movq 4984(%rdi), %rax
andq $-2147483648, %rax
movq (%rdi), %rdx
andl $2147483647, %edx
orq %rdx, %rax
movq %rax, %rdx
shrq %rdx
xorq 3168(%rdi), %rdx
andl $1, %eax
movl $2567483615, %ecx
cmovne %rcx, %rax
xorq %rdx, %rax
movq %rax, 4984(%rdi)
movq $0, 4992(%rdi)
ret
.cfi_endproc
.LFE4804:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv, .-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,comdat
.align 2
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, @function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv:
.LFB4743:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
cmpq $623, 4992(%rdi)
ja .L24
.L22:
movq 4992(%rbx), %rax
leaq 1(%rax), %rdx
movq %rdx, 4992(%rbx)
movq (%rbx,%rax,8), %rax
movq %rax, %rdx
shrq $11, %rdx
movl %edx, %edx
xorq %rax, %rdx
movq %rdx, %rax
salq $7, %rax
andl $2636928640, %eax
xorq %rdx, %rax
movq %rax, %rdx
salq $15, %rdx
andl $4022730752, %edx
xorq %rax, %rdx
movq %rdx, %rax
shrq $18, %rax
xorq %rdx, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
jmp .L22
.cfi_endproc
.LFE4743:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, .-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.section .text._ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,"axG",@progbits,_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,comdat
.align 2
.weak _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.type _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE, @function
_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE:
.LFB4642:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbp
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movslq 4(%rdx), %rbx
movslq (%rdx), %rax
subq %rax, %rbx
movl $4294967294, %eax
cmpq %rbx, %rax
jnb .L36
movq %rdi, %r14
movq %rbx, %rax
shrq $32, %rax
je .L30
movq %rsp, %r15
.L34:
movl $0, (%rsp)
movl $-1, 4(%rsp)
movq %r15, %rdx
movq %rbp, %rsi
movq %r14, %rdi
call _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
movq %rax, %r13
salq $32, %r13
movq %rbp, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
addq %r13, %rax
cmpq %rax, %rbx
jb .L34
cmpq %r13, %rax
jb .L34
jmp .L29
.L36:
addq $1, %rbx
movq %rsi, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %rbx, %rax
movq %rax, %rcx
cmpl %ebx, %eax
jnb .L27
movl %ebx, %eax
negl %eax
movl $0, %edx
divl %ebx
movl %edx, %r13d
cmpl %edx, %ecx
jnb .L27
.L28:
movq %rbp, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %rbx, %rax
movq %rax, %rcx
cmpl %r13d, %eax
jb .L28
.L27:
movq %rcx, %rax
shrq $32, %rax
.L29:
addl (%r12), %eax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L37
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movq %rsi, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
jmp .L29
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4642:
.size _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE, .-_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.text
.globl _Z9getRandomi
.type _Z9getRandomi, @function
_Z9getRandomi:
.LFB4141:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4141
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $4096, %rsp
.cfi_def_cfa_offset 4112
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 8208
orq $0, (%rsp)
subq $1840, %rsp
.cfi_def_cfa_offset 10048
movl %edi, %ebx
movq %fs:40, %rax
movq %rax, 10024(%rsp)
xorl %eax, %eax
leaq 5024(%rsp), %rsi
leaq 5040(%rsp), %rax
movq %rax, 5024(%rsp)
movl $1634100580, 5040(%rsp)
movl $1953264993, 5043(%rsp)
movq $7, 5032(%rsp)
movb $0, 5047(%rsp)
leaq 16(%rsp), %rdi
.LEHB0:
call _ZNSt13random_device7_M_initERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@PLT
.LEHE0:
movq 5024(%rsp), %rdi
leaq 5040(%rsp), %rax
cmpq %rax, %rdi
je .L39
movq 5040(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L39:
leaq 16(%rsp), %rdi
.LEHB1:
call _ZNSt13random_device9_M_getvalEv@PLT
.LEHE1:
movl %eax, %eax
movq %rax, 5024(%rsp)
movl $1, %ecx
movabsq $945986875574848801, %rdi
.L43:
movq 5016(%rsp,%rcx,8), %rax
movq %rax, %rdx
shrq $30, %rdx
xorq %rdx, %rax
imulq $1812433253, %rax, %rsi
movq %rcx, %rdx
shrq $4, %rdx
movq %rdx, %rax
mulq %rdi
shrq %rdx
imulq $624, %rdx, %rdx
movq %rcx, %rax
subq %rdx, %rax
addl %esi, %eax
movq %rax, 5024(%rsp,%rcx,8)
addq $1, %rcx
cmpq $624, %rcx
jne .L43
movq $624, 10016(%rsp)
movl $0, 8(%rsp)
movl %ebx, 12(%rsp)
leaq 8(%rsp), %rdi
leaq 5024(%rsp), %rsi
movq %rdi, %rdx
call _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
movl %eax, %ebx
leaq 16(%rsp), %rdi
call _ZNSt13random_device7_M_finiEv@PLT
movq 10024(%rsp), %rax
subq %fs:40, %rax
jne .L52
movl %ebx, %eax
addq $10032, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 5024(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 10024(%rsp), %rax
subq %fs:40, %rax
je .L42
call __stack_chk_fail@PLT
.L42:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L47:
endbr64
movq %rax, %rbx
leaq 16(%rsp), %rdi
call _ZNSt13random_device7_M_finiEv@PLT
movq 10024(%rsp), %rax
subq %fs:40, %rax
je .L45
call __stack_chk_fail@PLT
.L45:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4141:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4141:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4141-.LLSDACSB4141
.LLSDACSB4141:
.uleb128 .LEHB0-.LFB4141
.uleb128 .LEHE0-.LEHB0
.uleb128 .L48-.LFB4141
.uleb128 0
.uleb128 .LEHB1-.LFB4141
.uleb128 .LEHE1-.LEHB1
.uleb128 .L47-.LFB4141
.uleb128 0
.uleb128 .LEHB2-.LFB4141
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB4141
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE4141:
.text
.size _Z9getRandomi, .-_Z9getRandomi
.globl injective
.type injective, @function
injective:
.LFB4142:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %r14d
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movslq %edi, %r13
leaq 0(,%r13,4), %r12
leaq 8(%rsp), %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
testl %r14d, %r14d
jle .L54
movl $0, %ebx
.L55:
movq 8(%rsp), %rax
movl %ebx, (%rax,%rbx,4)
movq 16(%rsp), %rax
leaq (%rax,%rbx,4), %r15
movl %ebp, %edi
call _Z9getRandomi
movl %eax, (%r15)
movq 24(%rsp), %rax
movl $1, (%rax,%rbx,4)
addq $1, %rbx
cmpq %rbx, %r13
jne .L55
.L54:
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leal 510(%r14), %eax
movl %r14d, %edx
addl $255, %edx
cmovns %edx, %eax
sarl $8, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L66
.L56:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L67
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
testl %r14d, %r14d
jle .L59
movq 24(%rsp), %rdi
movq %rdi, %rax
addq %rdi, %r12
.L61:
movl (%rax), %ebx
testl %ebx, %ebx
je .L68
addq $4, %rax
cmpq %r12, %rax
jne .L61
.L59:
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $1, %ebx
jmp .L53
.L66:
movq 24(%rsp), %rcx
movl %r14d, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z5checkPiS_iS_PiS_iS_
jmp .L56
.L67:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $-1, %ebx
.L53:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L69
movl %ebx, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
call cudaFree@PLT
jmp .L53
.L69:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4142:
.size injective, .-injective
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "checkInjective.hip"
.globl _Z9getRandomi # -- Begin function _Z9getRandomi
.p2align 4, 0x90
.type _Z9getRandomi,@function
_Z9getRandomi: # @_Z9getRandomi
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $10008, %rsp # imm = 0x2718
.cfi_def_cfa_offset 10032
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edi, %ebx
leaq 24(%rsp), %r14
movq %r14, 8(%rsp)
movl $1634100580, 24(%rsp) # imm = 0x61666564
movl $1953264993, 27(%rsp) # imm = 0x746C7561
movq $7, 16(%rsp)
movb $0, 31(%rsp)
.Ltmp0:
leaq 5008(%rsp), %rdi
leaq 8(%rsp), %rsi
callq _ZNSt13random_device7_M_initERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp1:
# %bb.1:
movq 8(%rsp), %rdi
cmpq %r14, %rdi
je .LBB0_3
# %bb.2: # %.critedge.i.i.i
callq _ZdlPv
.LBB0_3: # %_ZNSt13random_deviceC2Ev.exit
.Ltmp3:
leaq 5008(%rsp), %rdi
callq _ZNSt13random_device9_M_getvalEv
.Ltmp4:
# %bb.4: # %_ZNSt13random_deviceclEv.exit
movl %eax, %eax
movq %rax, 8(%rsp)
movl $1, %ecx
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
movq %rax, %rdx
shrq $30, %rdx
xorl %eax, %edx
imull $1812433253, %edx, %eax # imm = 0x6C078965
addl %ecx, %eax
movq %rax, 8(%rsp,%rcx,8)
incq %rcx
cmpq $624, %rcx # imm = 0x270
jne .LBB0_5
# %bb.6: # %_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEC2Em.exit
movq $624, 5000(%rsp) # imm = 0x270
movl $0, (%rsp)
movl %ebx, 4(%rsp)
.Ltmp6:
leaq 8(%rsp), %rsi
movq %rsp, %rdi
movq %rdi, %rdx
callq _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.Ltmp7:
# %bb.7: # %_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_.exit
.Ltmp12:
movl %eax, %ebx
leaq 5008(%rsp), %rdi
callq _ZNSt13random_device7_M_finiEv
.Ltmp13:
# %bb.8: # %_ZNSt13random_deviceD2Ev.exit
movl %ebx, %eax
addq $10008, %rsp # imm = 0x2718
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_12:
.cfi_def_cfa_offset 10032
.Ltmp14:
movq %rax, %rdi
callq __clang_call_terminate
.LBB0_14:
.Ltmp8:
jmp .LBB0_15
.LBB0_13:
.Ltmp5:
.LBB0_15:
movq %rax, %rbx
.Ltmp9:
leaq 5008(%rsp), %rdi
callq _ZNSt13random_device7_M_finiEv
.Ltmp10:
jmp .LBB0_11
.LBB0_16:
.Ltmp11:
movq %rax, %rdi
callq __clang_call_terminate
.LBB0_9:
.Ltmp2:
movq %rax, %rbx
movq 8(%rsp), %rdi
cmpq %r14, %rdi
je .LBB0_11
# %bb.10: # %.critedge.i.i6.i
callq _ZdlPv
.LBB0_11: # %common.resume
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size _Z9getRandomi, .Lfunc_end0-_Z9getRandomi
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14
.byte 1 # On action: 1
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 1 # On action: 1
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Lfunc_end0-.Ltmp10 # Call between .Ltmp10 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.text
.globl _Z20__device_stub__checkPiS_iS_ # -- Begin function _Z20__device_stub__checkPiS_iS_
.p2align 4, 0x90
.type _Z20__device_stub__checkPiS_iS_,@function
_Z20__device_stub__checkPiS_iS_: # @_Z20__device_stub__checkPiS_iS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5checkPiS_iS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z20__device_stub__checkPiS_iS_, .Lfunc_end1-_Z20__device_stub__checkPiS_iS_
.cfi_endproc
# -- End function
.globl injective # -- Begin function injective
.p2align 4, 0x90
.type injective,@function
injective: # @injective
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movl %edi, %ebx
movslq %edi, %r15
leaq (,%r15,4), %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movq %r14, %rsi
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movq %r14, %rsi
movl $1, %edx
callq hipMallocManaged
testl %r15d, %r15d
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %ebx, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq 24(%rsp), %rax
movl %r15d, (%rax,%r15,4)
movl %ebp, %edi
callq _Z9getRandomi
movq 16(%rsp), %rcx
movl %eax, (%rcx,%r15,4)
movq 8(%rsp), %rax
movl $1, (%rax,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB2_2
.LBB2_3: # %._crit_edge
leal 255(%rbx), %eax
leal 510(%rbx), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $8, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl %ebx, 36(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z5checkPiS_iS_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
callq hipDeviceSynchronize
callq hipGetLastError
movl %eax, %ebp
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
testl %ebp, %ebp
je .LBB2_7
# %bb.6:
movl $-1, %ebx
jmp .LBB2_12
.LBB2_7:
testl %ebx, %ebx
jle .LBB2_11
# %bb.8: # %.lr.ph34
movq 8(%rsp), %rdi
movl %ebx, %eax
xorl %ebx, %ebx
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_10: # =>This Inner Loop Header: Depth=1
cmpl $0, (%rdi,%rcx,4)
je .LBB2_13
# %bb.9: # in Loop: Header=BB2_10 Depth=1
incq %rcx
cmpq %rcx, %rax
jne .LBB2_10
.LBB2_11: # %.critedge
movl $1, %ebx
.LBB2_12: # %.loopexit
movq 8(%rsp), %rdi
.LBB2_13: # %.loopexit
callq hipFree
movl %ebx, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size injective, .Lfunc_end2-injective
.cfi_endproc
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end3:
.size __clang_call_terminate, .Lfunc_end3-__clang_call_terminate
.cfi_endproc
# -- End function
.section .text._ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,"axG",@progbits,_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,comdat
.weak _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE # -- Begin function _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.p2align 4, 0x90
.type _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,@function
_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE: # @_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movslq 4(%rdx), %r15
movq %rdx, 8(%rsp) # 8-byte Spill
movslq (%rdx), %rax
subq %rax, %r15
movl $4294967294, %eax # imm = 0xFFFFFFFE
cmpq %rax, %r15
ja .LBB4_6
# %bb.1:
leal 1(%r15), %r12d
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %r12, %rax
cmpl %eax, %r12d
jbe .LBB4_5
# %bb.2:
notl %r15d
movq %rax, %rcx
movl %r15d, %eax
xorl %edx, %edx
divl %r12d
movq %rcx, %rax
cmpl %eax, %edx
jbe .LBB4_5
# %bb.3: # %.lr.ph.i.preheader
movl %edx, %ebp
.p2align 4, 0x90
.LBB4_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %r12, %rax
cmpl %eax, %ebp
ja .LBB4_4
.LBB4_5: # %_ZNSt24uniform_int_distributionIiE5_S_ndImSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEjEET1_RT0_S4_.exit
shrq $32, %rax
jmp .LBB4_11
.LBB4_6:
movl $4294967295, %eax # imm = 0xFFFFFFFF
cmpq %rax, %r15
jne .LBB4_7
# %bb.10:
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
jmp .LBB4_11
.LBB4_7: # %.preheader
movq %rdi, %r12
movabsq $-4294967296, %rbx # imm = 0xFFFFFFFF00000000
leaq 16(%rsp), %r13
.p2align 4, 0x90
.LBB4_8: # =>This Inner Loop Header: Depth=1
movq %rbx, 16(%rsp)
movq %r12, %rdi
movq %r14, %rsi
movq %r13, %rdx
callq _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
movl %eax, %ebp
shlq $32, %rbp
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
addq %rbp, %rax
setb %cl
cmpq %r15, %rax
ja .LBB4_8
# %bb.9: # in Loop: Header=BB4_8 Depth=1
testb %cl, %cl
jne .LBB4_8
.LBB4_11: # %.loopexit
movq 8(%rsp), %rcx # 8-byte Reload
addl (%rcx), %eax
# kill: def $eax killed $eax killed $rax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE, .Lfunc_end4-_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.cfi_endproc
# -- End function
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,comdat
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv # -- Begin function _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.p2align 4, 0x90
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,@function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv: # @_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.cfi_startproc
# %bb.0:
cmpq $624, 4992(%rdi) # imm = 0x270
jb .LBB5_6
# %bb.1: # %.preheader.preheader
movl $2567483615, %eax # imm = 0x9908B0DF
xorl %edx, %edx
movq $-2147483648, %rcx # imm = 0x80000000
.p2align 4, 0x90
.LBB5_2: # %.preheader
# =>This Inner Loop Header: Depth=1
movq (%rdi,%rdx,8), %rsi
andq %rcx, %rsi
movq 8(%rdi,%rdx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq 3176(%rdi,%rdx,8), %r9
andl $1, %r8d
negl %r8d
andl %eax, %r8d
xorq %r9, %r8
movq %r8, (%rdi,%rdx,8)
leaq 1(%rdx), %rsi
movq %rsi, %rdx
cmpq $227, %rsi
jne .LBB5_2
# %bb.3: # %.preheader.i.preheader
movl $228, %ecx
movq $-2147483648, %rdx # imm = 0x80000000
.p2align 4, 0x90
.LBB5_4: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movq -8(%rdi,%rcx,8), %rsi
andq %rdx, %rsi
movq (%rdi,%rcx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq -1824(%rdi,%rcx,8), %r9
andl $1, %r8d
negl %r8d
andl %eax, %r8d
xorq %r9, %r8
movq %r8, -8(%rdi,%rcx,8)
incq %rcx
cmpq $624, %rcx # imm = 0x270
jne .LBB5_4
# %bb.5: # %_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv.exit
movq $-2147483648, %rcx # imm = 0x80000000
andq 4984(%rdi), %rcx
movq (%rdi), %rdx
movl %edx, %esi
andl $2147483646, %esi # imm = 0x7FFFFFFE
orq %rcx, %rsi
shrq %rsi
xorq 3168(%rdi), %rsi
andl $1, %edx
negl %edx
andl %eax, %edx
xorq %rsi, %rdx
movq %rdx, 4984(%rdi)
movq $0, 4992(%rdi)
.LBB5_6:
movq 4992(%rdi), %rax
leaq 1(%rax), %rcx
movq %rcx, 4992(%rdi)
movq (%rdi,%rax,8), %rax
movq %rax, %rcx
shrq $11, %rcx
movl %ecx, %ecx
xorq %rax, %rcx
movl %ecx, %eax
shll $7, %eax
andl $-1658038656, %eax # imm = 0x9D2C5680
xorq %rcx, %rax
movl %eax, %ecx
shll $15, %ecx
andl $-272236544, %ecx # imm = 0xEFC60000
xorq %rax, %rcx
movq %rcx, %rax
shrq $18, %rax
xorq %rcx, %rax
retq
.Lfunc_end5:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, .Lfunc_end5-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5checkPiS_iS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5checkPiS_iS_,@object # @_Z5checkPiS_iS_
.section .rodata,"a",@progbits
.globl _Z5checkPiS_iS_
.p2align 3, 0x0
_Z5checkPiS_iS_:
.quad _Z20__device_stub__checkPiS_iS_
.size _Z5checkPiS_iS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "default"
.size .L.str, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5checkPiS_iS_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Z20__device_stub__checkPiS_iS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z5checkPiS_iS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <cuda.h>
#define THREADS_PER_BLOCK 1024
void matrixAdd(int *a, int *b, int *c, int N) {
int index;
for (int col = 0; col < N; col++) {
for (int row = 0; row < N; row++) {
c[index] = a[index] + b[index];
}
}
}
__global__ void matrixAddKernel(int *a, int *b, int *c, int N) {
int col = threadIdx.x + blockIdx.x * blockDim.x;
int row = threadIdx.y + blockIdx.y * blockDim.y;
int index = row * N + col;
c[index] = a[index] + b[index];
}
int main() {
int N = 4096; // Define size of 1 side of square matrix
// Initialise grid and block variables
dim3 grid(N / THREADS_PER_BLOCK, 1, 1);
dim3 block(THREADS_PER_BLOCK, 1, 1);
// Initialise host pointers (dynamically allocated memory) and device pointers
int *a_h;
int *b_h;
int *c_h; // GPU results
int *d_h; // CPU results
int *a_d;
int *b_d;
int *c_d;
int size; // Number of bytes required by arrays
// Create timer
cudaEvent_t start;
cudaEvent_t stop;
float elapsedTime;
// Print out information about blocks and threads
printf("Number of threads: %i (%ix%i)\n", block.x*block.y, block.x, block.y);
printf("Number of blocks: %i (%ix%i)\n", grid.x*grid.y, grid.x, grid.y);
// Dynamically allocate host memory
size = N * N * sizeof(int);
a_h = (int*) malloc(size);
b_h = (int*) malloc(size);
c_h = (int*) malloc(size);
d_h = (int*) malloc(size);
// Load host arrays with data
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
a_h[i * N + j] = i;
b_h[i * N + j] = i;
}
}
// Allocate device memory
cudaMalloc((void**)&a_d, size);
cudaMalloc((void**)&b_d, size);
cudaMalloc((void**)&c_d, size);
// Copy host memory to device memory
cudaMemcpy(a_d, a_h, size, cudaMemcpyHostToDevice);
cudaMemcpy(b_d, b_h, size, cudaMemcpyHostToDevice);
cudaMemcpy(c_d, c_h, size, cudaMemcpyHostToDevice);
// Start timer for GPU
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
// Launch kernel
matrixAddKernel<<<grid, block>>>(a_d, b_d, c_d, N);
// Stop timer
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
// Print execution time
printf("Time to calculate results on GPU: %f ms\n", elapsedTime);
// Copy results to device
cudaMemcpy(c_h, c_d, size, cudaMemcpyDeviceToHost);
// Start timer for CPU
cudaEventRecord(start, 0);
// Launch CPU code
matrixAdd(a_h, b_h, d_h, N);
// Stop timer
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
// Print execution time
printf("Time to calculate results on CPU: %f ms\n", elapsedTime);
// Compare results
for (int i = 0; i < N*N; i++) {
if (c_h[i] != d_h[i]) {
printf("Error: CPU and GPU results do not match\n");
break;
}
}
// Free memory
free(a_h);
free(b_h);
free(c_h);
free(d_h);
cudaFree(a_d);
cudaFree(b_d);
cudaFree(c_d);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
}
|
code for sm_80
Function : _Z15matrixAddKernelPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002200 */
/*0060*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002600 */
/*0070*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc400078e0200 */
/*0080*/ IMAD R3, R5, c[0x0][0x4], R2 ; /* 0x0000010005037a24 */
/* 0x002fc800078e0202 */
/*0090*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */
/* 0x000fc800078e0200 */
/*00a0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*00f0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <cuda.h>
#define THREADS_PER_BLOCK 1024
void matrixAdd(int *a, int *b, int *c, int N) {
int index;
for (int col = 0; col < N; col++) {
for (int row = 0; row < N; row++) {
c[index] = a[index] + b[index];
}
}
}
__global__ void matrixAddKernel(int *a, int *b, int *c, int N) {
int col = threadIdx.x + blockIdx.x * blockDim.x;
int row = threadIdx.y + blockIdx.y * blockDim.y;
int index = row * N + col;
c[index] = a[index] + b[index];
}
int main() {
int N = 4096; // Define size of 1 side of square matrix
// Initialise grid and block variables
dim3 grid(N / THREADS_PER_BLOCK, 1, 1);
dim3 block(THREADS_PER_BLOCK, 1, 1);
// Initialise host pointers (dynamically allocated memory) and device pointers
int *a_h;
int *b_h;
int *c_h; // GPU results
int *d_h; // CPU results
int *a_d;
int *b_d;
int *c_d;
int size; // Number of bytes required by arrays
// Create timer
cudaEvent_t start;
cudaEvent_t stop;
float elapsedTime;
// Print out information about blocks and threads
printf("Number of threads: %i (%ix%i)\n", block.x*block.y, block.x, block.y);
printf("Number of blocks: %i (%ix%i)\n", grid.x*grid.y, grid.x, grid.y);
// Dynamically allocate host memory
size = N * N * sizeof(int);
a_h = (int*) malloc(size);
b_h = (int*) malloc(size);
c_h = (int*) malloc(size);
d_h = (int*) malloc(size);
// Load host arrays with data
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
a_h[i * N + j] = i;
b_h[i * N + j] = i;
}
}
// Allocate device memory
cudaMalloc((void**)&a_d, size);
cudaMalloc((void**)&b_d, size);
cudaMalloc((void**)&c_d, size);
// Copy host memory to device memory
cudaMemcpy(a_d, a_h, size, cudaMemcpyHostToDevice);
cudaMemcpy(b_d, b_h, size, cudaMemcpyHostToDevice);
cudaMemcpy(c_d, c_h, size, cudaMemcpyHostToDevice);
// Start timer for GPU
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
// Launch kernel
matrixAddKernel<<<grid, block>>>(a_d, b_d, c_d, N);
// Stop timer
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
// Print execution time
printf("Time to calculate results on GPU: %f ms\n", elapsedTime);
// Copy results to device
cudaMemcpy(c_h, c_d, size, cudaMemcpyDeviceToHost);
// Start timer for CPU
cudaEventRecord(start, 0);
// Launch CPU code
matrixAdd(a_h, b_h, d_h, N);
// Stop timer
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
// Print execution time
printf("Time to calculate results on CPU: %f ms\n", elapsedTime);
// Compare results
for (int i = 0; i < N*N; i++) {
if (c_h[i] != d_h[i]) {
printf("Error: CPU and GPU results do not match\n");
break;
}
}
// Free memory
free(a_h);
free(b_h);
free(c_h);
free(d_h);
cudaFree(a_d);
cudaFree(b_d);
cudaFree(c_d);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
}
|
.file "tmpxft_001b557f_00000000-6_matrixAddition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9matrixAddPiS_S_i
.type _Z9matrixAddPiS_S_i, @function
_Z9matrixAddPiS_S_i:
.LFB2057:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L3
movl $0, %eax
leaq (%rdi,%rax), %r8
leaq (%rsi,%rax), %rdi
leaq (%rdx,%rax), %rsi
movl $0, %r9d
.L5:
movl $0, %eax
.L6:
movl (%rdi), %edx
addl (%r8), %edx
movl %edx, (%rsi)
movl %eax, %edx
addl $1, %eax
cmpl %eax, %ecx
jne .L6
leal 1(%r9), %eax
cmpl %edx, %r9d
je .L3
movl %eax, %r9d
jmp .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z9matrixAddPiS_S_i, .-_Z9matrixAddPiS_S_i
.globl _Z40__device_stub__Z15matrixAddKernelPiS_S_iPiS_S_i
.type _Z40__device_stub__Z15matrixAddKernelPiS_S_iPiS_S_i, @function
_Z40__device_stub__Z15matrixAddKernelPiS_S_iPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrixAddKernelPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z40__device_stub__Z15matrixAddKernelPiS_S_iPiS_S_i, .-_Z40__device_stub__Z15matrixAddKernelPiS_S_iPiS_S_i
.globl _Z15matrixAddKernelPiS_S_i
.type _Z15matrixAddKernelPiS_S_i, @function
_Z15matrixAddKernelPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15matrixAddKernelPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z15matrixAddKernelPiS_S_i, .-_Z15matrixAddKernelPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Number of threads: %i (%ix%i)\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Number of blocks: %i (%ix%i)\n"
.section .rodata.str1.8
.align 8
.LC2:
.string "Time to calculate results on GPU: %f ms\n"
.align 8
.LC3:
.string "Time to calculate results on CPU: %f ms\n"
.align 8
.LC4:
.string "Error: CPU and GPU results do not match\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 56(%rsp)
movl $1, 68(%rsp)
movl $1, %r8d
movl $1024, %ecx
movl $1024, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %r8d
movl $4, %ecx
movl $4, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbp
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbx
movl $67108864, %edi
call malloc@PLT
movq %rax, %r12
movl $67108864, %edi
call malloc@PLT
movq %rax, %r13
movl $16384, %ecx
movl $0, %edx
.L17:
leaq -16384(%rcx), %rax
.L18:
movl %edx, 0(%rbp,%rax)
movl %edx, (%rbx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L18
addl $1, %edx
addq $16384, %rcx
cmpl $4096, %edx
jne .L17
leaq 8(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $67108864, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $67108864, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $67108864, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $4, 48(%rsp)
movl $1, 52(%rsp)
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L20:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %r14
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq %r14, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $67108864, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $4096, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z9matrixAddPiS_S_i
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq %r14, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
.L23:
movl 0(%r13,%rax), %esi
cmpl %esi, (%r12,%rax)
jne .L29
addq $4, %rax
cmpq $67108864, %rax
jne .L23
jmp .L22
.L28:
movl $4096, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z40__device_stub__Z15matrixAddKernelPiS_S_iPiS_S_i
jmp .L20
.L29:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L22:
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z15matrixAddKernelPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixAddKernelPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <cuda.h>
#define THREADS_PER_BLOCK 1024
void matrixAdd(int *a, int *b, int *c, int N) {
int index;
for (int col = 0; col < N; col++) {
for (int row = 0; row < N; row++) {
c[index] = a[index] + b[index];
}
}
}
__global__ void matrixAddKernel(int *a, int *b, int *c, int N) {
int col = threadIdx.x + blockIdx.x * blockDim.x;
int row = threadIdx.y + blockIdx.y * blockDim.y;
int index = row * N + col;
c[index] = a[index] + b[index];
}
int main() {
int N = 4096; // Define size of 1 side of square matrix
// Initialise grid and block variables
dim3 grid(N / THREADS_PER_BLOCK, 1, 1);
dim3 block(THREADS_PER_BLOCK, 1, 1);
// Initialise host pointers (dynamically allocated memory) and device pointers
int *a_h;
int *b_h;
int *c_h; // GPU results
int *d_h; // CPU results
int *a_d;
int *b_d;
int *c_d;
int size; // Number of bytes required by arrays
// Create timer
cudaEvent_t start;
cudaEvent_t stop;
float elapsedTime;
// Print out information about blocks and threads
printf("Number of threads: %i (%ix%i)\n", block.x*block.y, block.x, block.y);
printf("Number of blocks: %i (%ix%i)\n", grid.x*grid.y, grid.x, grid.y);
// Dynamically allocate host memory
size = N * N * sizeof(int);
a_h = (int*) malloc(size);
b_h = (int*) malloc(size);
c_h = (int*) malloc(size);
d_h = (int*) malloc(size);
// Load host arrays with data
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
a_h[i * N + j] = i;
b_h[i * N + j] = i;
}
}
// Allocate device memory
cudaMalloc((void**)&a_d, size);
cudaMalloc((void**)&b_d, size);
cudaMalloc((void**)&c_d, size);
// Copy host memory to device memory
cudaMemcpy(a_d, a_h, size, cudaMemcpyHostToDevice);
cudaMemcpy(b_d, b_h, size, cudaMemcpyHostToDevice);
cudaMemcpy(c_d, c_h, size, cudaMemcpyHostToDevice);
// Start timer for GPU
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
// Launch kernel
matrixAddKernel<<<grid, block>>>(a_d, b_d, c_d, N);
// Stop timer
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
// Print execution time
printf("Time to calculate results on GPU: %f ms\n", elapsedTime);
// Copy results to device
cudaMemcpy(c_h, c_d, size, cudaMemcpyDeviceToHost);
// Start timer for CPU
cudaEventRecord(start, 0);
// Launch CPU code
matrixAdd(a_h, b_h, d_h, N);
// Stop timer
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
// Print execution time
printf("Time to calculate results on CPU: %f ms\n", elapsedTime);
// Compare results
for (int i = 0; i < N*N; i++) {
if (c_h[i] != d_h[i]) {
printf("Error: CPU and GPU results do not match\n");
break;
}
}
// Free memory
free(a_h);
free(b_h);
free(c_h);
free(d_h);
cudaFree(a_d);
cudaFree(b_d);
cudaFree(c_d);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
}
|
#include <stdio.h>
#include <hip/hip_runtime.h>
#define THREADS_PER_BLOCK 1024
void matrixAdd(int *a, int *b, int *c, int N) {
int index;
for (int col = 0; col < N; col++) {
for (int row = 0; row < N; row++) {
c[index] = a[index] + b[index];
}
}
}
__global__ void matrixAddKernel(int *a, int *b, int *c, int N) {
int col = threadIdx.x + blockIdx.x * blockDim.x;
int row = threadIdx.y + blockIdx.y * blockDim.y;
int index = row * N + col;
c[index] = a[index] + b[index];
}
int main() {
int N = 4096; // Define size of 1 side of square matrix
// Initialise grid and block variables
dim3 grid(N / THREADS_PER_BLOCK, 1, 1);
dim3 block(THREADS_PER_BLOCK, 1, 1);
// Initialise host pointers (dynamically allocated memory) and device pointers
int *a_h;
int *b_h;
int *c_h; // GPU results
int *d_h; // CPU results
int *a_d;
int *b_d;
int *c_d;
int size; // Number of bytes required by arrays
// Create timer
hipEvent_t start;
hipEvent_t stop;
float elapsedTime;
// Print out information about blocks and threads
printf("Number of threads: %i (%ix%i)\n", block.x*block.y, block.x, block.y);
printf("Number of blocks: %i (%ix%i)\n", grid.x*grid.y, grid.x, grid.y);
// Dynamically allocate host memory
size = N * N * sizeof(int);
a_h = (int*) malloc(size);
b_h = (int*) malloc(size);
c_h = (int*) malloc(size);
d_h = (int*) malloc(size);
// Load host arrays with data
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
a_h[i * N + j] = i;
b_h[i * N + j] = i;
}
}
// Allocate device memory
hipMalloc((void**)&a_d, size);
hipMalloc((void**)&b_d, size);
hipMalloc((void**)&c_d, size);
// Copy host memory to device memory
hipMemcpy(a_d, a_h, size, hipMemcpyHostToDevice);
hipMemcpy(b_d, b_h, size, hipMemcpyHostToDevice);
hipMemcpy(c_d, c_h, size, hipMemcpyHostToDevice);
// Start timer for GPU
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
// Launch kernel
matrixAddKernel<<<grid, block>>>(a_d, b_d, c_d, N);
// Stop timer
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
// Print execution time
printf("Time to calculate results on GPU: %f ms\n", elapsedTime);
// Copy results to device
hipMemcpy(c_h, c_d, size, hipMemcpyDeviceToHost);
// Start timer for CPU
hipEventRecord(start, 0);
// Launch CPU code
matrixAdd(a_h, b_h, d_h, N);
// Stop timer
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
// Print execution time
printf("Time to calculate results on CPU: %f ms\n", elapsedTime);
// Compare results
for (int i = 0; i < N*N; i++) {
if (c_h[i] != d_h[i]) {
printf("Error: CPU and GPU results do not match\n");
break;
}
}
// Free memory
free(a_h);
free(b_h);
free(c_h);
free(d_h);
hipFree(a_d);
hipFree(b_d);
hipFree(c_d);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <stdio.h>
#include <hip/hip_runtime.h>
#define THREADS_PER_BLOCK 1024
void matrixAdd(int *a, int *b, int *c, int N) {
int index;
for (int col = 0; col < N; col++) {
for (int row = 0; row < N; row++) {
c[index] = a[index] + b[index];
}
}
}
__global__ void matrixAddKernel(int *a, int *b, int *c, int N) {
int col = threadIdx.x + blockIdx.x * blockDim.x;
int row = threadIdx.y + blockIdx.y * blockDim.y;
int index = row * N + col;
c[index] = a[index] + b[index];
}
int main() {
int N = 4096; // Define size of 1 side of square matrix
// Initialise grid and block variables
dim3 grid(N / THREADS_PER_BLOCK, 1, 1);
dim3 block(THREADS_PER_BLOCK, 1, 1);
// Initialise host pointers (dynamically allocated memory) and device pointers
int *a_h;
int *b_h;
int *c_h; // GPU results
int *d_h; // CPU results
int *a_d;
int *b_d;
int *c_d;
int size; // Number of bytes required by arrays
// Create timer
hipEvent_t start;
hipEvent_t stop;
float elapsedTime;
// Print out information about blocks and threads
printf("Number of threads: %i (%ix%i)\n", block.x*block.y, block.x, block.y);
printf("Number of blocks: %i (%ix%i)\n", grid.x*grid.y, grid.x, grid.y);
// Dynamically allocate host memory
size = N * N * sizeof(int);
a_h = (int*) malloc(size);
b_h = (int*) malloc(size);
c_h = (int*) malloc(size);
d_h = (int*) malloc(size);
// Load host arrays with data
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
a_h[i * N + j] = i;
b_h[i * N + j] = i;
}
}
// Allocate device memory
hipMalloc((void**)&a_d, size);
hipMalloc((void**)&b_d, size);
hipMalloc((void**)&c_d, size);
// Copy host memory to device memory
hipMemcpy(a_d, a_h, size, hipMemcpyHostToDevice);
hipMemcpy(b_d, b_h, size, hipMemcpyHostToDevice);
hipMemcpy(c_d, c_h, size, hipMemcpyHostToDevice);
// Start timer for GPU
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
// Launch kernel
matrixAddKernel<<<grid, block>>>(a_d, b_d, c_d, N);
// Stop timer
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
// Print execution time
printf("Time to calculate results on GPU: %f ms\n", elapsedTime);
// Copy results to device
hipMemcpy(c_h, c_d, size, hipMemcpyDeviceToHost);
// Start timer for CPU
hipEventRecord(start, 0);
// Launch CPU code
matrixAdd(a_h, b_h, d_h, N);
// Stop timer
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
// Print execution time
printf("Time to calculate results on CPU: %f ms\n", elapsedTime);
// Compare results
for (int i = 0; i < N*N; i++) {
if (c_h[i] != d_h[i]) {
printf("Error: CPU and GPU results do not match\n");
break;
}
}
// Free memory
free(a_h);
free(b_h);
free(c_h);
free(d_h);
hipFree(a_d);
hipFree(b_d);
hipFree(c_d);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15matrixAddKernelPiS_S_i
.globl _Z15matrixAddKernelPiS_S_i
.p2align 8
.type _Z15matrixAddKernelPiS_S_i,@function
_Z15matrixAddKernelPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s14, s14, s2
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s3
v_add3_u32 v0, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matrixAddKernelPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15matrixAddKernelPiS_S_i, .Lfunc_end0-_Z15matrixAddKernelPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matrixAddKernelPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15matrixAddKernelPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <stdio.h>
#include <hip/hip_runtime.h>
#define THREADS_PER_BLOCK 1024
void matrixAdd(int *a, int *b, int *c, int N) {
int index;
for (int col = 0; col < N; col++) {
for (int row = 0; row < N; row++) {
c[index] = a[index] + b[index];
}
}
}
__global__ void matrixAddKernel(int *a, int *b, int *c, int N) {
int col = threadIdx.x + blockIdx.x * blockDim.x;
int row = threadIdx.y + blockIdx.y * blockDim.y;
int index = row * N + col;
c[index] = a[index] + b[index];
}
int main() {
int N = 4096; // Define size of 1 side of square matrix
// Initialise grid and block variables
dim3 grid(N / THREADS_PER_BLOCK, 1, 1);
dim3 block(THREADS_PER_BLOCK, 1, 1);
// Initialise host pointers (dynamically allocated memory) and device pointers
int *a_h;
int *b_h;
int *c_h; // GPU results
int *d_h; // CPU results
int *a_d;
int *b_d;
int *c_d;
int size; // Number of bytes required by arrays
// Create timer
hipEvent_t start;
hipEvent_t stop;
float elapsedTime;
// Print out information about blocks and threads
printf("Number of threads: %i (%ix%i)\n", block.x*block.y, block.x, block.y);
printf("Number of blocks: %i (%ix%i)\n", grid.x*grid.y, grid.x, grid.y);
// Dynamically allocate host memory
size = N * N * sizeof(int);
a_h = (int*) malloc(size);
b_h = (int*) malloc(size);
c_h = (int*) malloc(size);
d_h = (int*) malloc(size);
// Load host arrays with data
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
a_h[i * N + j] = i;
b_h[i * N + j] = i;
}
}
// Allocate device memory
hipMalloc((void**)&a_d, size);
hipMalloc((void**)&b_d, size);
hipMalloc((void**)&c_d, size);
// Copy host memory to device memory
hipMemcpy(a_d, a_h, size, hipMemcpyHostToDevice);
hipMemcpy(b_d, b_h, size, hipMemcpyHostToDevice);
hipMemcpy(c_d, c_h, size, hipMemcpyHostToDevice);
// Start timer for GPU
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
// Launch kernel
matrixAddKernel<<<grid, block>>>(a_d, b_d, c_d, N);
// Stop timer
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
// Print execution time
printf("Time to calculate results on GPU: %f ms\n", elapsedTime);
// Copy results to device
hipMemcpy(c_h, c_d, size, hipMemcpyDeviceToHost);
// Start timer for CPU
hipEventRecord(start, 0);
// Launch CPU code
matrixAdd(a_h, b_h, d_h, N);
// Stop timer
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
// Print execution time
printf("Time to calculate results on CPU: %f ms\n", elapsedTime);
// Compare results
for (int i = 0; i < N*N; i++) {
if (c_h[i] != d_h[i]) {
printf("Error: CPU and GPU results do not match\n");
break;
}
}
// Free memory
free(a_h);
free(b_h);
free(c_h);
free(d_h);
hipFree(a_d);
hipFree(b_d);
hipFree(c_d);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
}
|
.text
.file "matrixAddition.hip"
.globl _Z9matrixAddPiS_S_i # -- Begin function _Z9matrixAddPiS_S_i
.p2align 4, 0x90
.type _Z9matrixAddPiS_S_i,@function
_Z9matrixAddPiS_S_i: # @_Z9matrixAddPiS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB0_5
# %bb.1: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
movl %ecx, %r8d
.p2align 4, 0x90
.LBB0_3: # %.lr.ph
# Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rsi), %r9d
addl (%rdi), %r9d
movl %r9d, (%rdx)
decl %r8d
jne .LBB0_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incl %eax
cmpl %ecx, %eax
jne .LBB0_2
.LBB0_5: # %._crit_edge15
retq
.Lfunc_end0:
.size _Z9matrixAddPiS_S_i, .Lfunc_end0-_Z9matrixAddPiS_S_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__matrixAddKernelPiS_S_i # -- Begin function _Z30__device_stub__matrixAddKernelPiS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__matrixAddKernelPiS_S_i,@function
_Z30__device_stub__matrixAddKernelPiS_S_i: # @_Z30__device_stub__matrixAddKernelPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrixAddKernelPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z30__device_stub__matrixAddKernelPiS_S_i, .Lfunc_end1-_Z30__device_stub__matrixAddKernelPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %r13d, %r13d
movl $.L.str, %edi
movl $1024, %esi # imm = 0x400
movl $1024, %edx # imm = 0x400
movl $1, %ecx
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $4, %esi
movl $4, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %rbx
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r14
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r15
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r12
movq %rbx, %rax
movq %r14, %rcx
.p2align 4, 0x90
.LBB2_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %r13d, (%rax,%rdx,4)
movl %r13d, (%rcx,%rdx,4)
incq %rdx
cmpq $4096, %rdx # imm = 0x1000
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
incq %r13
addq $16384, %rcx # imm = 0x4000
addq $16384, %rax # imm = 0x4000
cmpq $4096, %r13 # imm = 0x1000
jne .LBB2_1
# %bb.4:
leaq 32(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
movq 32(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 1020(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movl $4096, 44(%rsp) # imm = 0x1000
leaq 144(%rsp), %rax
movq %rax, 48(%rsp)
leaq 136(%rsp), %rax
movq %rax, 56(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 44(%rsp), %rax
movq %rax, 72(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z15matrixAddKernelPiS_S_i, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6: # %_Z9matrixAddPiS_S_i.exit
movq (%rsp), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
leaq 48(%rsp), %r13
movq %r13, %rdi
callq hipEventElapsedTime
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rsi
movl $67108864, %edx # imm = 0x4000000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl (%r14), %eax
addl (%rbx), %eax
movl %eax, (%r12)
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
movq %r13, %rdi
callq hipEventElapsedTime
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
.p2align 4, 0x90
.LBB2_8: # =>This Inner Loop Header: Depth=1
movl (%r15,%rbp,4), %eax
cmpl (%r12,%rbp,4), %eax
jne .LBB2_9
# %bb.7: # in Loop: Header=BB2_8 Depth=1
incq %rbp
cmpq $16777216, %rbp # imm = 0x1000000
jne .LBB2_8
jmp .LBB2_10
.LBB2_9:
movl $.Lstr, %edi
callq puts@PLT
.LBB2_10: # %.loopexit
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixAddKernelPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15matrixAddKernelPiS_S_i,@object # @_Z15matrixAddKernelPiS_S_i
.section .rodata,"a",@progbits
.globl _Z15matrixAddKernelPiS_S_i
.p2align 3, 0x0
_Z15matrixAddKernelPiS_S_i:
.quad _Z30__device_stub__matrixAddKernelPiS_S_i
.size _Z15matrixAddKernelPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Number of threads: %i (%ix%i)\n"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Number of blocks: %i (%ix%i)\n"
.size .L.str.1, 30
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Time to calculate results on GPU: %f ms\n"
.size .L.str.2, 41
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Time to calculate results on CPU: %f ms\n"
.size .L.str.3, 41
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15matrixAddKernelPiS_S_i"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error: CPU and GPU results do not match"
.size .Lstr, 40
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__matrixAddKernelPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15matrixAddKernelPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z15matrixAddKernelPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002200 */
/*0060*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002600 */
/*0070*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc400078e0200 */
/*0080*/ IMAD R3, R5, c[0x0][0x4], R2 ; /* 0x0000010005037a24 */
/* 0x002fc800078e0202 */
/*0090*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */
/* 0x000fc800078e0200 */
/*00a0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*00f0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15matrixAddKernelPiS_S_i
.globl _Z15matrixAddKernelPiS_S_i
.p2align 8
.type _Z15matrixAddKernelPiS_S_i,@function
_Z15matrixAddKernelPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s14, s14, s2
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s3
v_add3_u32 v0, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matrixAddKernelPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15matrixAddKernelPiS_S_i, .Lfunc_end0-_Z15matrixAddKernelPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matrixAddKernelPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15matrixAddKernelPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001b557f_00000000-6_matrixAddition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9matrixAddPiS_S_i
.type _Z9matrixAddPiS_S_i, @function
_Z9matrixAddPiS_S_i:
.LFB2057:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L3
movl $0, %eax
leaq (%rdi,%rax), %r8
leaq (%rsi,%rax), %rdi
leaq (%rdx,%rax), %rsi
movl $0, %r9d
.L5:
movl $0, %eax
.L6:
movl (%rdi), %edx
addl (%r8), %edx
movl %edx, (%rsi)
movl %eax, %edx
addl $1, %eax
cmpl %eax, %ecx
jne .L6
leal 1(%r9), %eax
cmpl %edx, %r9d
je .L3
movl %eax, %r9d
jmp .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z9matrixAddPiS_S_i, .-_Z9matrixAddPiS_S_i
.globl _Z40__device_stub__Z15matrixAddKernelPiS_S_iPiS_S_i
.type _Z40__device_stub__Z15matrixAddKernelPiS_S_iPiS_S_i, @function
_Z40__device_stub__Z15matrixAddKernelPiS_S_iPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrixAddKernelPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z40__device_stub__Z15matrixAddKernelPiS_S_iPiS_S_i, .-_Z40__device_stub__Z15matrixAddKernelPiS_S_iPiS_S_i
.globl _Z15matrixAddKernelPiS_S_i
.type _Z15matrixAddKernelPiS_S_i, @function
_Z15matrixAddKernelPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15matrixAddKernelPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z15matrixAddKernelPiS_S_i, .-_Z15matrixAddKernelPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Number of threads: %i (%ix%i)\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Number of blocks: %i (%ix%i)\n"
.section .rodata.str1.8
.align 8
.LC2:
.string "Time to calculate results on GPU: %f ms\n"
.align 8
.LC3:
.string "Time to calculate results on CPU: %f ms\n"
.align 8
.LC4:
.string "Error: CPU and GPU results do not match\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 56(%rsp)
movl $1, 68(%rsp)
movl $1, %r8d
movl $1024, %ecx
movl $1024, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %r8d
movl $4, %ecx
movl $4, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbp
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbx
movl $67108864, %edi
call malloc@PLT
movq %rax, %r12
movl $67108864, %edi
call malloc@PLT
movq %rax, %r13
movl $16384, %ecx
movl $0, %edx
.L17:
leaq -16384(%rcx), %rax
.L18:
movl %edx, 0(%rbp,%rax)
movl %edx, (%rbx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L18
addl $1, %edx
addq $16384, %rcx
cmpl $4096, %edx
jne .L17
leaq 8(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $67108864, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $67108864, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $67108864, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $4, 48(%rsp)
movl $1, 52(%rsp)
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L20:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %r14
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq %r14, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $67108864, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $4096, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z9matrixAddPiS_S_i
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq %r14, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
.L23:
movl 0(%r13,%rax), %esi
cmpl %esi, (%r12,%rax)
jne .L29
addq $4, %rax
cmpq $67108864, %rax
jne .L23
jmp .L22
.L28:
movl $4096, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z40__device_stub__Z15matrixAddKernelPiS_S_iPiS_S_i
jmp .L20
.L29:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L22:
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z15matrixAddKernelPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixAddKernelPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "matrixAddition.hip"
.globl _Z9matrixAddPiS_S_i # -- Begin function _Z9matrixAddPiS_S_i
.p2align 4, 0x90
.type _Z9matrixAddPiS_S_i,@function
_Z9matrixAddPiS_S_i: # @_Z9matrixAddPiS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB0_5
# %bb.1: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
movl %ecx, %r8d
.p2align 4, 0x90
.LBB0_3: # %.lr.ph
# Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rsi), %r9d
addl (%rdi), %r9d
movl %r9d, (%rdx)
decl %r8d
jne .LBB0_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incl %eax
cmpl %ecx, %eax
jne .LBB0_2
.LBB0_5: # %._crit_edge15
retq
.Lfunc_end0:
.size _Z9matrixAddPiS_S_i, .Lfunc_end0-_Z9matrixAddPiS_S_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__matrixAddKernelPiS_S_i # -- Begin function _Z30__device_stub__matrixAddKernelPiS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__matrixAddKernelPiS_S_i,@function
_Z30__device_stub__matrixAddKernelPiS_S_i: # @_Z30__device_stub__matrixAddKernelPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrixAddKernelPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z30__device_stub__matrixAddKernelPiS_S_i, .Lfunc_end1-_Z30__device_stub__matrixAddKernelPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %r13d, %r13d
movl $.L.str, %edi
movl $1024, %esi # imm = 0x400
movl $1024, %edx # imm = 0x400
movl $1, %ecx
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $4, %esi
movl $4, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %rbx
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r14
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r15
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r12
movq %rbx, %rax
movq %r14, %rcx
.p2align 4, 0x90
.LBB2_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %r13d, (%rax,%rdx,4)
movl %r13d, (%rcx,%rdx,4)
incq %rdx
cmpq $4096, %rdx # imm = 0x1000
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
incq %r13
addq $16384, %rcx # imm = 0x4000
addq $16384, %rax # imm = 0x4000
cmpq $4096, %r13 # imm = 0x1000
jne .LBB2_1
# %bb.4:
leaq 32(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
movq 32(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 1020(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movl $4096, 44(%rsp) # imm = 0x1000
leaq 144(%rsp), %rax
movq %rax, 48(%rsp)
leaq 136(%rsp), %rax
movq %rax, 56(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 44(%rsp), %rax
movq %rax, 72(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z15matrixAddKernelPiS_S_i, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6: # %_Z9matrixAddPiS_S_i.exit
movq (%rsp), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
leaq 48(%rsp), %r13
movq %r13, %rdi
callq hipEventElapsedTime
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rsi
movl $67108864, %edx # imm = 0x4000000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl (%r14), %eax
addl (%rbx), %eax
movl %eax, (%r12)
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
movq %r13, %rdi
callq hipEventElapsedTime
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
.p2align 4, 0x90
.LBB2_8: # =>This Inner Loop Header: Depth=1
movl (%r15,%rbp,4), %eax
cmpl (%r12,%rbp,4), %eax
jne .LBB2_9
# %bb.7: # in Loop: Header=BB2_8 Depth=1
incq %rbp
cmpq $16777216, %rbp # imm = 0x1000000
jne .LBB2_8
jmp .LBB2_10
.LBB2_9:
movl $.Lstr, %edi
callq puts@PLT
.LBB2_10: # %.loopexit
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixAddKernelPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15matrixAddKernelPiS_S_i,@object # @_Z15matrixAddKernelPiS_S_i
.section .rodata,"a",@progbits
.globl _Z15matrixAddKernelPiS_S_i
.p2align 3, 0x0
_Z15matrixAddKernelPiS_S_i:
.quad _Z30__device_stub__matrixAddKernelPiS_S_i
.size _Z15matrixAddKernelPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Number of threads: %i (%ix%i)\n"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Number of blocks: %i (%ix%i)\n"
.size .L.str.1, 30
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Time to calculate results on GPU: %f ms\n"
.size .L.str.2, 41
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Time to calculate results on CPU: %f ms\n"
.size .L.str.3, 41
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15matrixAddKernelPiS_S_i"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error: CPU and GPU results do not match"
.size .Lstr, 40
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__matrixAddKernelPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15matrixAddKernelPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void matrixTranspose(double *a, double *c, int cr, int cc){
int x = blockIdx.x * blockDim.x + threadIdx.x; // col
int y = blockIdx.y * blockDim.y + threadIdx.y; // row
if(x < cc && y < cr){
for(int i = 0; i<cc; i++) {
c[y * cc + x+i] = a[x * cc + y + i];
}
}
}
|
code for sm_80
Function : _Z15matrixTransposePdS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff007624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e280000002100 */
/*0040*/ S2R R8, SR_CTAID.Y ; /* 0x0000000000087919 */
/* 0x000e680000002600 */
/*0050*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R10, R6, c[0x0][0x0], R7 ; /* 0x00000000060a7a24 */
/* 0x001fca00078e0207 */
/*0070*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x174], PT ; /* 0x00005d000a007a0c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD R11, R8, c[0x0][0x4], R9 ; /* 0x00000100080b7a24 */
/* 0x002fca00078e0209 */
/*0090*/ ISETP.GE.OR P0, PT, R11, c[0x0][0x170], P0 ; /* 0x00005c000b007a0c */
/* 0x000fc80000706670 */
/*00a0*/ ISETP.LT.OR P0, PT, R0, 0x1, P0 ; /* 0x000000010000780c */
/* 0x000fda0000701670 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00e0*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*00f0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0100*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0110*/ @!P0 BRA 0x810 ; /* 0x000006f000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R13, -R0, c[0x0][0x174], RZ ; /* 0x00005d00000d7a10 */
/* 0x000fe20007ffe1ff */
/*0130*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe200078e00ff */
/*0140*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0150*/ IMAD R2, R10, c[0x0][0x174], R11 ; /* 0x00005d000a027a24 */
/* 0x000fe200078e020b */
/*0160*/ ISETP.GT.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f04270 */
/*0170*/ ULDC.64 UR8, c[0x0][0x168] ; /* 0x00005a0000087ab9 */
/* 0x000fe20000000a00 */
/*0180*/ IMAD R12, R11, c[0x0][0x174], R10 ; /* 0x00005d000b0c7a24 */
/* 0x000fe400078e020a */
/*0190*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fd200078e0203 */
/*01a0*/ @!P0 BRA 0x6c0 ; /* 0x0000051000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R13, 0xc, PT ; /* 0x0000000c0d00780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x4c0 ; /* 0x000002e000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ LDG.E.64 R14, [R2.64] ; /* 0x00000006020e7981 */
/* 0x001ea2000c1e1b00 */
/*0200*/ MOV R4, UR8 ; /* 0x0000000800047c02 */
/* 0x000fe20008000f00 */
/*0210*/ IMAD.U32 R5, RZ, RZ, UR9 ; /* 0x00000009ff057e24 */
/* 0x000fc8000f8e00ff */
/*0220*/ IMAD.WIDE R4, R12, 0x8, R4 ; /* 0x000000080c047825 */
/* 0x000fca00078e0204 */
/*0230*/ STG.E.64 [R4.64], R14 ; /* 0x0000000e04007986 */
/* 0x0041e8000c101b06 */
/*0240*/ LDG.E.64 R16, [R2.64+0x8] ; /* 0x0000080602107981 */
/* 0x000ea8000c1e1b00 */
/*0250*/ STG.E.64 [R4.64+0x8], R16 ; /* 0x0000081004007986 */
/* 0x0043e8000c101b06 */
/*0260*/ LDG.E.64 R18, [R2.64+0x10] ; /* 0x0000100602127981 */
/* 0x000ea8000c1e1b00 */
/*0270*/ STG.E.64 [R4.64+0x10], R18 ; /* 0x0000101204007986 */
/* 0x0045e8000c101b06 */
/*0280*/ LDG.E.64 R20, [R2.64+0x18] ; /* 0x0000180602147981 */
/* 0x000ee8000c1e1b00 */
/*0290*/ STG.E.64 [R4.64+0x18], R20 ; /* 0x0000181404007986 */
/* 0x0087e8000c101b06 */
/*02a0*/ LDG.E.64 R22, [R2.64+0x20] ; /* 0x0000200602167981 */
/* 0x000f28000c1e1b00 */
/*02b0*/ STG.E.64 [R4.64+0x20], R22 ; /* 0x0000201604007986 */
/* 0x0109e8000c101b06 */
/*02c0*/ LDG.E.64 R24, [R2.64+0x28] ; /* 0x0000280602187981 */
/* 0x000f68000c1e1b00 */
/*02d0*/ STG.E.64 [R4.64+0x28], R24 ; /* 0x0000281804007986 */
/* 0x020be8000c101b06 */
/*02e0*/ LDG.E.64 R14, [R2.64+0x30] ; /* 0x00003006020e7981 */
/* 0x001ea8000c1e1b00 */
/*02f0*/ STG.E.64 [R4.64+0x30], R14 ; /* 0x0000300e04007986 */
/* 0x0041e8000c101b06 */
/*0300*/ LDG.E.64 R16, [R2.64+0x38] ; /* 0x0000380602107981 */
/* 0x002ea8000c1e1b00 */
/*0310*/ STG.E.64 [R4.64+0x38], R16 ; /* 0x0000381004007986 */
/* 0x0043e8000c101b06 */
/*0320*/ LDG.E.64 R18, [R2.64+0x40] ; /* 0x0000400602127981 */
/* 0x000ea8000c1e1b00 */
/*0330*/ STG.E.64 [R4.64+0x40], R18 ; /* 0x0000401204007986 */
/* 0x0045e8000c101b06 */
/*0340*/ LDG.E.64 R20, [R2.64+0x48] ; /* 0x0000480602147981 */
/* 0x008ee8000c1e1b00 */
/*0350*/ STG.E.64 [R4.64+0x48], R20 ; /* 0x0000481404007986 */
/* 0x0087e8000c101b06 */
/*0360*/ LDG.E.64 R22, [R2.64+0x50] ; /* 0x0000500602167981 */
/* 0x010f28000c1e1b00 */
/*0370*/ STG.E.64 [R4.64+0x50], R22 ; /* 0x0000501604007986 */
/* 0x0109e8000c101b06 */
/*0380*/ LDG.E.64 R24, [R2.64+0x58] ; /* 0x0000580602187981 */
/* 0x020f68000c1e1b00 */
/*0390*/ STG.E.64 [R4.64+0x58], R24 ; /* 0x0000581804007986 */
/* 0x0203e8000c101b06 */
/*03a0*/ LDG.E.64 R14, [R2.64+0x60] ; /* 0x00006006020e7981 */
/* 0x001f68000c1e1b00 */
/*03b0*/ STG.E.64 [R4.64+0x60], R14 ; /* 0x0000600e04007986 */
/* 0x0201e8000c101b06 */
/*03c0*/ LDG.E.64 R16, [R2.64+0x68] ; /* 0x0000680602107981 */
/* 0x002f68000c1e1b00 */
/*03d0*/ STG.E.64 [R4.64+0x68], R16 ; /* 0x0000681004007986 */
/* 0x0201e8000c101b06 */
/*03e0*/ LDG.E.64 R18, [R2.64+0x70] ; /* 0x0000700602127981 */
/* 0x004ea2000c1e1b00 */
/*03f0*/ IADD3 R13, R13, -0x10, RZ ; /* 0xfffffff00d0d7810 */
/* 0x000fc80007ffe0ff */
/*0400*/ ISETP.GT.AND P1, PT, R13, 0xc, PT ; /* 0x0000000c0d00780c */
/* 0x000fe20003f24270 */
/*0410*/ STG.E.64 [R4.64+0x70], R18 ; /* 0x0000701204007986 */
/* 0x0041e8000c101b06 */
/*0420*/ LDG.E.64 R20, [R2.64+0x78] ; /* 0x0000780602147981 */
/* 0x0082a2000c1e1b00 */
/*0430*/ IADD3 R22, P2, R2, 0x80, RZ ; /* 0x0000008002167810 */
/* 0x010fe20007f5e0ff */
/*0440*/ UIADD3 UR8, UP0, UR8, 0x80, URZ ; /* 0x0000008008087890 */
/* 0x000fe4000ff1e03f */
/*0450*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe4000fffe03f */
/*0460*/ IMAD.X R23, RZ, RZ, R3, P2 ; /* 0x000000ffff177224 */
/* 0x000fe200010e0603 */
/*0470*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0480*/ IMAD.MOV.U32 R2, RZ, RZ, R22 ; /* 0x000000ffff027224 */
/* 0x002fc600078e0016 */
/*0490*/ MOV R3, R23 ; /* 0x0000001700037202 */
/* 0x000fe20000000f00 */
/*04a0*/ STG.E.64 [R4.64+0x78], R20 ; /* 0x0000781404007986 */
/* 0x0041e2000c101b06 */
/*04b0*/ @P1 BRA 0x1f0 ; /* 0xfffffd3000001947 */
/* 0x000fea000383ffff */
/*04c0*/ ISETP.GT.AND P1, PT, R13, 0x4, PT ; /* 0x000000040d00780c */
/* 0x000fda0003f24270 */
/*04d0*/ @!P1 BRA 0x6a0 ; /* 0x000001c000009947 */
/* 0x000fea0003800000 */
/*04e0*/ LDG.E.64 R14, [R2.64] ; /* 0x00000006020e7981 */
/* 0x001ea2000c1e1b00 */
/*04f0*/ IMAD.U32 R4, RZ, RZ, UR8 ; /* 0x00000008ff047e24 */
/* 0x000fe4000f8e00ff */
/*0500*/ IMAD.U32 R5, RZ, RZ, UR9 ; /* 0x00000009ff057e24 */
/* 0x000fc8000f8e00ff */
/*0510*/ IMAD.WIDE R4, R12, 0x8, R4 ; /* 0x000000080c047825 */
/* 0x000fca00078e0204 */
/*0520*/ STG.E.64 [R4.64], R14 ; /* 0x0000000e04007986 */
/* 0x0041e8000c101b06 */
/*0530*/ LDG.E.64 R16, [R2.64+0x8] ; /* 0x0000080602107981 */
/* 0x000ea8000c1e1b00 */
/*0540*/ STG.E.64 [R4.64+0x8], R16 ; /* 0x0000081004007986 */
/* 0x0043e8000c101b06 */
/*0550*/ LDG.E.64 R18, [R2.64+0x10] ; /* 0x0000100602127981 */
/* 0x000ea8000c1e1b00 */
/*0560*/ STG.E.64 [R4.64+0x10], R18 ; /* 0x0000101204007986 */
/* 0x0045e8000c101b06 */
/*0570*/ LDG.E.64 R20, [R2.64+0x18] ; /* 0x0000180602147981 */
/* 0x000ee8000c1e1b00 */
/*0580*/ STG.E.64 [R4.64+0x18], R20 ; /* 0x0000181404007986 */
/* 0x0087e8000c101b06 */
/*0590*/ LDG.E.64 R22, [R2.64+0x20] ; /* 0x0000200602167981 */
/* 0x000f28000c1e1b00 */
/*05a0*/ STG.E.64 [R4.64+0x20], R22 ; /* 0x0000201604007986 */
/* 0x0107e8000c101b06 */
/*05b0*/ LDG.E.64 R24, [R2.64+0x28] ; /* 0x0000280602187981 */
/* 0x000f28000c1e1b00 */
/*05c0*/ STG.E.64 [R4.64+0x28], R24 ; /* 0x0000281804007986 */
/* 0x0107e8000c101b06 */
/*05d0*/ LDG.E.64 R14, [R2.64+0x30] ; /* 0x00003006020e7981 */
/* 0x001f28000c1e1b00 */
/*05e0*/ STG.E.64 [R4.64+0x30], R14 ; /* 0x0000300e04007986 */
/* 0x0107e8000c101b06 */
/*05f0*/ LDG.E.64 R16, [R2.64+0x38] ; /* 0x0000380602107981 */
/* 0x002122000c1e1b00 */
/*0600*/ IADD3 R18, P1, R2, 0x40, RZ ; /* 0x0000004002127810 */
/* 0x004fe20007f3e0ff */
/*0610*/ UIADD3 UR8, UP0, UR8, 0x40, URZ ; /* 0x0000004008087890 */
/* 0x000fe2000ff1e03f */
/*0620*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0630*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0640*/ IADD3 R13, R13, -0x8, RZ ; /* 0xfffffff80d0d7810 */
/* 0x000fe20007ffe0ff */
/*0650*/ IMAD.X R19, RZ, RZ, R3, P1 ; /* 0x000000ffff137224 */
/* 0x000fe200008e0603 */
/*0660*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0670*/ MOV R2, R18 ; /* 0x0000001200027202 */
/* 0x001fc40000000f00 */
/*0680*/ IMAD.MOV.U32 R3, RZ, RZ, R19 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0013 */
/*0690*/ STG.E.64 [R4.64+0x38], R16 ; /* 0x0000381004007986 */
/* 0x0107e8000c101b06 */
/*06a0*/ ISETP.NE.OR P0, PT, R13, RZ, P0 ; /* 0x000000ff0d00720c */
/* 0x000fda0000705670 */
/*06b0*/ @!P0 BRA 0x810 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*06c0*/ LDG.E.64 R14, [R2.64] ; /* 0x00000006020e7981 */
/* 0x009ea2000c1e1b00 */
/*06d0*/ IMAD.U32 R4, RZ, RZ, UR8 ; /* 0x00000008ff047e24 */
/* 0x000fe4000f8e00ff */
/*06e0*/ IMAD.U32 R5, RZ, RZ, UR9 ; /* 0x00000009ff057e24 */
/* 0x000fc8000f8e00ff */
/*06f0*/ IMAD.WIDE R4, R12, 0x8, R4 ; /* 0x000000080c047825 */
/* 0x000fca00078e0204 */
/*0700*/ STG.E.64 [R4.64], R14 ; /* 0x0000000e04007986 */
/* 0x0041e8000c101b06 */
/*0710*/ LDG.E.64 R16, [R2.64+0x8] ; /* 0x0000080602107981 */
/* 0x000ea8000c1e1b00 */
/*0720*/ STG.E.64 [R4.64+0x8], R16 ; /* 0x0000081004007986 */
/* 0x0041e8000c101b06 */
/*0730*/ LDG.E.64 R18, [R2.64+0x10] ; /* 0x0000100602127981 */
/* 0x000ea2000c1e1b00 */
/*0740*/ IADD3 R13, R13, -0x4, RZ ; /* 0xfffffffc0d0d7810 */
/* 0x000fc80007ffe0ff */
/*0750*/ ISETP.NE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f05270 */
/*0760*/ STG.E.64 [R4.64+0x10], R18 ; /* 0x0000101204007986 */
/* 0x0041e8000c101b06 */
/*0770*/ LDG.E.64 R20, [R2.64+0x18] ; /* 0x0000180602147981 */
/* 0x0002a2000c1e1b00 */
/*0780*/ IADD3 R22, P1, R2, 0x20, RZ ; /* 0x0000002002167810 */
/* 0x000fe20007f3e0ff */
/*0790*/ UIADD3 UR8, UP0, UR8, 0x20, URZ ; /* 0x0000002008087890 */
/* 0x000fe4000ff1e03f */
/*07a0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*07b0*/ IADD3.X R23, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff177210 */
/* 0x000fe20000ffe4ff */
/*07c0*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*07d0*/ IMAD.MOV.U32 R2, RZ, RZ, R22 ; /* 0x000000ffff027224 */
/* 0x002fc600078e0016 */
/*07e0*/ IMAD.MOV.U32 R3, RZ, RZ, R23 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0017 */
/*07f0*/ STG.E.64 [R4.64+0x18], R20 ; /* 0x0000181404007986 */
/* 0x0041e4000c101b06 */
/*0800*/ @P0 BRA 0x6c0 ; /* 0xfffffeb000000947 */
/* 0x001fea000383ffff */
/*0810*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0820*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0830*/ IADD3 R7, R7, UR4, RZ ; /* 0x0000000407077c10 */
/* 0x000fe2000fffe0ff */
/*0840*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x009fe200000001ff */
/*0850*/ IADD3 R9, R9, UR4, RZ ; /* 0x0000000409097c10 */
/* 0x000fc6000fffe0ff */
/*0860*/ IMAD R6, R6, c[0x0][0x0], R7 ; /* 0x0000000006067a24 */
/* 0x000fe400078e0207 */
/*0870*/ IMAD R9, R8, c[0x0][0x4], R9 ; /* 0x0000010008097a24 */
/* 0x000fe400078e0209 */
/*0880*/ IMAD R2, R11, c[0x0][0x174], R6 ; /* 0x00005d000b027a24 */
/* 0x000fe400078e0206 */
/*0890*/ IMAD R4, R10, c[0x0][0x174], R9 ; /* 0x00005d000a047a24 */
/* 0x000fe400078e0209 */
/*08a0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0205 */
/*08b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*08c0*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0002 */
/*08d0*/ MOV R6, R4 ; /* 0x0000000400067202 */
/* 0x000fe20000000f00 */
/*08e0*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0003 */
/*08f0*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0005 */
/*0900*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x001fe200078e0006 */
/*0910*/ MOV R3, R7 ; /* 0x0000000700037202 */
/* 0x000fcc0000000f00 */
/*0920*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1b00 */
/*0930*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0940*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0008 */
/*0950*/ IADD3 R6, P2, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe20007f5e0ff */
/*0960*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*0970*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0980*/ IADD3 R8, P1, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x000fe20007f3e0ff */
/*0990*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x000fc600010e0607 */
/*09a0*/ IADD3.X R9, RZ, R9, RZ, P1, !PT ; /* 0x00000009ff097210 */
/* 0x000fe20000ffe4ff */
/*09b0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x0041ec000c101b06 */
/*09c0*/ @P0 BRA 0x900 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*09d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09e0*/ BRA 0x9e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void matrixTranspose(double *a, double *c, int cr, int cc){
int x = blockIdx.x * blockDim.x + threadIdx.x; // col
int y = blockIdx.y * blockDim.y + threadIdx.y; // row
if(x < cc && y < cr){
for(int i = 0; i<cc; i++) {
c[y * cc + x+i] = a[x * cc + y + i];
}
}
}
|
.file "tmpxft_001136b5_00000000-6_matrixTranspose.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15matrixTransposePdS_iiPdS_ii
.type _Z39__device_stub__Z15matrixTransposePdS_iiPdS_ii, @function
_Z39__device_stub__Z15matrixTransposePdS_iiPdS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrixTransposePdS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z15matrixTransposePdS_iiPdS_ii, .-_Z39__device_stub__Z15matrixTransposePdS_iiPdS_ii
.globl _Z15matrixTransposePdS_ii
.type _Z15matrixTransposePdS_ii, @function
_Z15matrixTransposePdS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15matrixTransposePdS_iiPdS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15matrixTransposePdS_ii, .-_Z15matrixTransposePdS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15matrixTransposePdS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixTransposePdS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void matrixTranspose(double *a, double *c, int cr, int cc){
int x = blockIdx.x * blockDim.x + threadIdx.x; // col
int y = blockIdx.y * blockDim.y + threadIdx.y; // row
if(x < cc && y < cr){
for(int i = 0; i<cc; i++) {
c[y * cc + x+i] = a[x * cc + y + i];
}
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixTranspose(double *a, double *c, int cr, int cc){
int x = blockIdx.x * blockDim.x + threadIdx.x; // col
int y = blockIdx.y * blockDim.y + threadIdx.y; // row
if(x < cc && y < cr){
for(int i = 0; i<cc; i++) {
c[y * cc + x+i] = a[x * cc + y + i];
}
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixTranspose(double *a, double *c, int cr, int cc){
int x = blockIdx.x * blockDim.x + threadIdx.x; // col
int y = blockIdx.y * blockDim.y + threadIdx.y; // row
if(x < cc && y < cr){
for(int i = 0; i<cc; i++) {
c[y * cc + x+i] = a[x * cc + y + i];
}
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15matrixTransposePdS_ii
.globl _Z15matrixTransposePdS_ii
.p2align 8
.type _Z15matrixTransposePdS_ii,@function
_Z15matrixTransposePdS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[4:5], null, s14, s3, v[1:2]
v_mad_u64_u32 v[5:6], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s5, v4
v_cmp_gt_i32_e64 s2, s4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_cmp_gt_i32 s5, 0
s_cselect_b32 s3, -1, 0
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[0:1], null, v4, s5, v[5:6]
v_mad_u64_u32 v[2:3], null, v5, s5, v[4:5]
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s5, s5, -1
s_cmp_lg_u32 s5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 3, v[0:1]
v_add_nc_u32_e32 v0, 1, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_load_b64 v[4:5], v[3:4], off
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[6:7], 3, v[2:3]
v_add_nc_u32_e32 v2, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[6:7], v[4:5], off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matrixTransposePdS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15matrixTransposePdS_ii, .Lfunc_end0-_Z15matrixTransposePdS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matrixTransposePdS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15matrixTransposePdS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixTranspose(double *a, double *c, int cr, int cc){
int x = blockIdx.x * blockDim.x + threadIdx.x; // col
int y = blockIdx.y * blockDim.y + threadIdx.y; // row
if(x < cc && y < cr){
for(int i = 0; i<cc; i++) {
c[y * cc + x+i] = a[x * cc + y + i];
}
}
}
|
.text
.file "matrixTranspose.hip"
.globl _Z30__device_stub__matrixTransposePdS_ii # -- Begin function _Z30__device_stub__matrixTransposePdS_ii
.p2align 4, 0x90
.type _Z30__device_stub__matrixTransposePdS_ii,@function
_Z30__device_stub__matrixTransposePdS_ii: # @_Z30__device_stub__matrixTransposePdS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrixTransposePdS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__matrixTransposePdS_ii, .Lfunc_end0-_Z30__device_stub__matrixTransposePdS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixTransposePdS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15matrixTransposePdS_ii,@object # @_Z15matrixTransposePdS_ii
.section .rodata,"a",@progbits
.globl _Z15matrixTransposePdS_ii
.p2align 3, 0x0
_Z15matrixTransposePdS_ii:
.quad _Z30__device_stub__matrixTransposePdS_ii
.size _Z15matrixTransposePdS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15matrixTransposePdS_ii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__matrixTransposePdS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15matrixTransposePdS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z15matrixTransposePdS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff007624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e280000002100 */
/*0040*/ S2R R8, SR_CTAID.Y ; /* 0x0000000000087919 */
/* 0x000e680000002600 */
/*0050*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R10, R6, c[0x0][0x0], R7 ; /* 0x00000000060a7a24 */
/* 0x001fca00078e0207 */
/*0070*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x174], PT ; /* 0x00005d000a007a0c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD R11, R8, c[0x0][0x4], R9 ; /* 0x00000100080b7a24 */
/* 0x002fca00078e0209 */
/*0090*/ ISETP.GE.OR P0, PT, R11, c[0x0][0x170], P0 ; /* 0x00005c000b007a0c */
/* 0x000fc80000706670 */
/*00a0*/ ISETP.LT.OR P0, PT, R0, 0x1, P0 ; /* 0x000000010000780c */
/* 0x000fda0000701670 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00e0*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*00f0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0100*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0110*/ @!P0 BRA 0x810 ; /* 0x000006f000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R13, -R0, c[0x0][0x174], RZ ; /* 0x00005d00000d7a10 */
/* 0x000fe20007ffe1ff */
/*0130*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe200078e00ff */
/*0140*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0150*/ IMAD R2, R10, c[0x0][0x174], R11 ; /* 0x00005d000a027a24 */
/* 0x000fe200078e020b */
/*0160*/ ISETP.GT.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f04270 */
/*0170*/ ULDC.64 UR8, c[0x0][0x168] ; /* 0x00005a0000087ab9 */
/* 0x000fe20000000a00 */
/*0180*/ IMAD R12, R11, c[0x0][0x174], R10 ; /* 0x00005d000b0c7a24 */
/* 0x000fe400078e020a */
/*0190*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fd200078e0203 */
/*01a0*/ @!P0 BRA 0x6c0 ; /* 0x0000051000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R13, 0xc, PT ; /* 0x0000000c0d00780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x4c0 ; /* 0x000002e000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ LDG.E.64 R14, [R2.64] ; /* 0x00000006020e7981 */
/* 0x001ea2000c1e1b00 */
/*0200*/ MOV R4, UR8 ; /* 0x0000000800047c02 */
/* 0x000fe20008000f00 */
/*0210*/ IMAD.U32 R5, RZ, RZ, UR9 ; /* 0x00000009ff057e24 */
/* 0x000fc8000f8e00ff */
/*0220*/ IMAD.WIDE R4, R12, 0x8, R4 ; /* 0x000000080c047825 */
/* 0x000fca00078e0204 */
/*0230*/ STG.E.64 [R4.64], R14 ; /* 0x0000000e04007986 */
/* 0x0041e8000c101b06 */
/*0240*/ LDG.E.64 R16, [R2.64+0x8] ; /* 0x0000080602107981 */
/* 0x000ea8000c1e1b00 */
/*0250*/ STG.E.64 [R4.64+0x8], R16 ; /* 0x0000081004007986 */
/* 0x0043e8000c101b06 */
/*0260*/ LDG.E.64 R18, [R2.64+0x10] ; /* 0x0000100602127981 */
/* 0x000ea8000c1e1b00 */
/*0270*/ STG.E.64 [R4.64+0x10], R18 ; /* 0x0000101204007986 */
/* 0x0045e8000c101b06 */
/*0280*/ LDG.E.64 R20, [R2.64+0x18] ; /* 0x0000180602147981 */
/* 0x000ee8000c1e1b00 */
/*0290*/ STG.E.64 [R4.64+0x18], R20 ; /* 0x0000181404007986 */
/* 0x0087e8000c101b06 */
/*02a0*/ LDG.E.64 R22, [R2.64+0x20] ; /* 0x0000200602167981 */
/* 0x000f28000c1e1b00 */
/*02b0*/ STG.E.64 [R4.64+0x20], R22 ; /* 0x0000201604007986 */
/* 0x0109e8000c101b06 */
/*02c0*/ LDG.E.64 R24, [R2.64+0x28] ; /* 0x0000280602187981 */
/* 0x000f68000c1e1b00 */
/*02d0*/ STG.E.64 [R4.64+0x28], R24 ; /* 0x0000281804007986 */
/* 0x020be8000c101b06 */
/*02e0*/ LDG.E.64 R14, [R2.64+0x30] ; /* 0x00003006020e7981 */
/* 0x001ea8000c1e1b00 */
/*02f0*/ STG.E.64 [R4.64+0x30], R14 ; /* 0x0000300e04007986 */
/* 0x0041e8000c101b06 */
/*0300*/ LDG.E.64 R16, [R2.64+0x38] ; /* 0x0000380602107981 */
/* 0x002ea8000c1e1b00 */
/*0310*/ STG.E.64 [R4.64+0x38], R16 ; /* 0x0000381004007986 */
/* 0x0043e8000c101b06 */
/*0320*/ LDG.E.64 R18, [R2.64+0x40] ; /* 0x0000400602127981 */
/* 0x000ea8000c1e1b00 */
/*0330*/ STG.E.64 [R4.64+0x40], R18 ; /* 0x0000401204007986 */
/* 0x0045e8000c101b06 */
/*0340*/ LDG.E.64 R20, [R2.64+0x48] ; /* 0x0000480602147981 */
/* 0x008ee8000c1e1b00 */
/*0350*/ STG.E.64 [R4.64+0x48], R20 ; /* 0x0000481404007986 */
/* 0x0087e8000c101b06 */
/*0360*/ LDG.E.64 R22, [R2.64+0x50] ; /* 0x0000500602167981 */
/* 0x010f28000c1e1b00 */
/*0370*/ STG.E.64 [R4.64+0x50], R22 ; /* 0x0000501604007986 */
/* 0x0109e8000c101b06 */
/*0380*/ LDG.E.64 R24, [R2.64+0x58] ; /* 0x0000580602187981 */
/* 0x020f68000c1e1b00 */
/*0390*/ STG.E.64 [R4.64+0x58], R24 ; /* 0x0000581804007986 */
/* 0x0203e8000c101b06 */
/*03a0*/ LDG.E.64 R14, [R2.64+0x60] ; /* 0x00006006020e7981 */
/* 0x001f68000c1e1b00 */
/*03b0*/ STG.E.64 [R4.64+0x60], R14 ; /* 0x0000600e04007986 */
/* 0x0201e8000c101b06 */
/*03c0*/ LDG.E.64 R16, [R2.64+0x68] ; /* 0x0000680602107981 */
/* 0x002f68000c1e1b00 */
/*03d0*/ STG.E.64 [R4.64+0x68], R16 ; /* 0x0000681004007986 */
/* 0x0201e8000c101b06 */
/*03e0*/ LDG.E.64 R18, [R2.64+0x70] ; /* 0x0000700602127981 */
/* 0x004ea2000c1e1b00 */
/*03f0*/ IADD3 R13, R13, -0x10, RZ ; /* 0xfffffff00d0d7810 */
/* 0x000fc80007ffe0ff */
/*0400*/ ISETP.GT.AND P1, PT, R13, 0xc, PT ; /* 0x0000000c0d00780c */
/* 0x000fe20003f24270 */
/*0410*/ STG.E.64 [R4.64+0x70], R18 ; /* 0x0000701204007986 */
/* 0x0041e8000c101b06 */
/*0420*/ LDG.E.64 R20, [R2.64+0x78] ; /* 0x0000780602147981 */
/* 0x0082a2000c1e1b00 */
/*0430*/ IADD3 R22, P2, R2, 0x80, RZ ; /* 0x0000008002167810 */
/* 0x010fe20007f5e0ff */
/*0440*/ UIADD3 UR8, UP0, UR8, 0x80, URZ ; /* 0x0000008008087890 */
/* 0x000fe4000ff1e03f */
/*0450*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe4000fffe03f */
/*0460*/ IMAD.X R23, RZ, RZ, R3, P2 ; /* 0x000000ffff177224 */
/* 0x000fe200010e0603 */
/*0470*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0480*/ IMAD.MOV.U32 R2, RZ, RZ, R22 ; /* 0x000000ffff027224 */
/* 0x002fc600078e0016 */
/*0490*/ MOV R3, R23 ; /* 0x0000001700037202 */
/* 0x000fe20000000f00 */
/*04a0*/ STG.E.64 [R4.64+0x78], R20 ; /* 0x0000781404007986 */
/* 0x0041e2000c101b06 */
/*04b0*/ @P1 BRA 0x1f0 ; /* 0xfffffd3000001947 */
/* 0x000fea000383ffff */
/*04c0*/ ISETP.GT.AND P1, PT, R13, 0x4, PT ; /* 0x000000040d00780c */
/* 0x000fda0003f24270 */
/*04d0*/ @!P1 BRA 0x6a0 ; /* 0x000001c000009947 */
/* 0x000fea0003800000 */
/*04e0*/ LDG.E.64 R14, [R2.64] ; /* 0x00000006020e7981 */
/* 0x001ea2000c1e1b00 */
/*04f0*/ IMAD.U32 R4, RZ, RZ, UR8 ; /* 0x00000008ff047e24 */
/* 0x000fe4000f8e00ff */
/*0500*/ IMAD.U32 R5, RZ, RZ, UR9 ; /* 0x00000009ff057e24 */
/* 0x000fc8000f8e00ff */
/*0510*/ IMAD.WIDE R4, R12, 0x8, R4 ; /* 0x000000080c047825 */
/* 0x000fca00078e0204 */
/*0520*/ STG.E.64 [R4.64], R14 ; /* 0x0000000e04007986 */
/* 0x0041e8000c101b06 */
/*0530*/ LDG.E.64 R16, [R2.64+0x8] ; /* 0x0000080602107981 */
/* 0x000ea8000c1e1b00 */
/*0540*/ STG.E.64 [R4.64+0x8], R16 ; /* 0x0000081004007986 */
/* 0x0043e8000c101b06 */
/*0550*/ LDG.E.64 R18, [R2.64+0x10] ; /* 0x0000100602127981 */
/* 0x000ea8000c1e1b00 */
/*0560*/ STG.E.64 [R4.64+0x10], R18 ; /* 0x0000101204007986 */
/* 0x0045e8000c101b06 */
/*0570*/ LDG.E.64 R20, [R2.64+0x18] ; /* 0x0000180602147981 */
/* 0x000ee8000c1e1b00 */
/*0580*/ STG.E.64 [R4.64+0x18], R20 ; /* 0x0000181404007986 */
/* 0x0087e8000c101b06 */
/*0590*/ LDG.E.64 R22, [R2.64+0x20] ; /* 0x0000200602167981 */
/* 0x000f28000c1e1b00 */
/*05a0*/ STG.E.64 [R4.64+0x20], R22 ; /* 0x0000201604007986 */
/* 0x0107e8000c101b06 */
/*05b0*/ LDG.E.64 R24, [R2.64+0x28] ; /* 0x0000280602187981 */
/* 0x000f28000c1e1b00 */
/*05c0*/ STG.E.64 [R4.64+0x28], R24 ; /* 0x0000281804007986 */
/* 0x0107e8000c101b06 */
/*05d0*/ LDG.E.64 R14, [R2.64+0x30] ; /* 0x00003006020e7981 */
/* 0x001f28000c1e1b00 */
/*05e0*/ STG.E.64 [R4.64+0x30], R14 ; /* 0x0000300e04007986 */
/* 0x0107e8000c101b06 */
/*05f0*/ LDG.E.64 R16, [R2.64+0x38] ; /* 0x0000380602107981 */
/* 0x002122000c1e1b00 */
/*0600*/ IADD3 R18, P1, R2, 0x40, RZ ; /* 0x0000004002127810 */
/* 0x004fe20007f3e0ff */
/*0610*/ UIADD3 UR8, UP0, UR8, 0x40, URZ ; /* 0x0000004008087890 */
/* 0x000fe2000ff1e03f */
/*0620*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0630*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0640*/ IADD3 R13, R13, -0x8, RZ ; /* 0xfffffff80d0d7810 */
/* 0x000fe20007ffe0ff */
/*0650*/ IMAD.X R19, RZ, RZ, R3, P1 ; /* 0x000000ffff137224 */
/* 0x000fe200008e0603 */
/*0660*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0670*/ MOV R2, R18 ; /* 0x0000001200027202 */
/* 0x001fc40000000f00 */
/*0680*/ IMAD.MOV.U32 R3, RZ, RZ, R19 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0013 */
/*0690*/ STG.E.64 [R4.64+0x38], R16 ; /* 0x0000381004007986 */
/* 0x0107e8000c101b06 */
/*06a0*/ ISETP.NE.OR P0, PT, R13, RZ, P0 ; /* 0x000000ff0d00720c */
/* 0x000fda0000705670 */
/*06b0*/ @!P0 BRA 0x810 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*06c0*/ LDG.E.64 R14, [R2.64] ; /* 0x00000006020e7981 */
/* 0x009ea2000c1e1b00 */
/*06d0*/ IMAD.U32 R4, RZ, RZ, UR8 ; /* 0x00000008ff047e24 */
/* 0x000fe4000f8e00ff */
/*06e0*/ IMAD.U32 R5, RZ, RZ, UR9 ; /* 0x00000009ff057e24 */
/* 0x000fc8000f8e00ff */
/*06f0*/ IMAD.WIDE R4, R12, 0x8, R4 ; /* 0x000000080c047825 */
/* 0x000fca00078e0204 */
/*0700*/ STG.E.64 [R4.64], R14 ; /* 0x0000000e04007986 */
/* 0x0041e8000c101b06 */
/*0710*/ LDG.E.64 R16, [R2.64+0x8] ; /* 0x0000080602107981 */
/* 0x000ea8000c1e1b00 */
/*0720*/ STG.E.64 [R4.64+0x8], R16 ; /* 0x0000081004007986 */
/* 0x0041e8000c101b06 */
/*0730*/ LDG.E.64 R18, [R2.64+0x10] ; /* 0x0000100602127981 */
/* 0x000ea2000c1e1b00 */
/*0740*/ IADD3 R13, R13, -0x4, RZ ; /* 0xfffffffc0d0d7810 */
/* 0x000fc80007ffe0ff */
/*0750*/ ISETP.NE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f05270 */
/*0760*/ STG.E.64 [R4.64+0x10], R18 ; /* 0x0000101204007986 */
/* 0x0041e8000c101b06 */
/*0770*/ LDG.E.64 R20, [R2.64+0x18] ; /* 0x0000180602147981 */
/* 0x0002a2000c1e1b00 */
/*0780*/ IADD3 R22, P1, R2, 0x20, RZ ; /* 0x0000002002167810 */
/* 0x000fe20007f3e0ff */
/*0790*/ UIADD3 UR8, UP0, UR8, 0x20, URZ ; /* 0x0000002008087890 */
/* 0x000fe4000ff1e03f */
/*07a0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*07b0*/ IADD3.X R23, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff177210 */
/* 0x000fe20000ffe4ff */
/*07c0*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*07d0*/ IMAD.MOV.U32 R2, RZ, RZ, R22 ; /* 0x000000ffff027224 */
/* 0x002fc600078e0016 */
/*07e0*/ IMAD.MOV.U32 R3, RZ, RZ, R23 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0017 */
/*07f0*/ STG.E.64 [R4.64+0x18], R20 ; /* 0x0000181404007986 */
/* 0x0041e4000c101b06 */
/*0800*/ @P0 BRA 0x6c0 ; /* 0xfffffeb000000947 */
/* 0x001fea000383ffff */
/*0810*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0820*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0830*/ IADD3 R7, R7, UR4, RZ ; /* 0x0000000407077c10 */
/* 0x000fe2000fffe0ff */
/*0840*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x009fe200000001ff */
/*0850*/ IADD3 R9, R9, UR4, RZ ; /* 0x0000000409097c10 */
/* 0x000fc6000fffe0ff */
/*0860*/ IMAD R6, R6, c[0x0][0x0], R7 ; /* 0x0000000006067a24 */
/* 0x000fe400078e0207 */
/*0870*/ IMAD R9, R8, c[0x0][0x4], R9 ; /* 0x0000010008097a24 */
/* 0x000fe400078e0209 */
/*0880*/ IMAD R2, R11, c[0x0][0x174], R6 ; /* 0x00005d000b027a24 */
/* 0x000fe400078e0206 */
/*0890*/ IMAD R4, R10, c[0x0][0x174], R9 ; /* 0x00005d000a047a24 */
/* 0x000fe400078e0209 */
/*08a0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0205 */
/*08b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*08c0*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0002 */
/*08d0*/ MOV R6, R4 ; /* 0x0000000400067202 */
/* 0x000fe20000000f00 */
/*08e0*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0003 */
/*08f0*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0005 */
/*0900*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x001fe200078e0006 */
/*0910*/ MOV R3, R7 ; /* 0x0000000700037202 */
/* 0x000fcc0000000f00 */
/*0920*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1b00 */
/*0930*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0940*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0008 */
/*0950*/ IADD3 R6, P2, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe20007f5e0ff */
/*0960*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*0970*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0980*/ IADD3 R8, P1, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x000fe20007f3e0ff */
/*0990*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x000fc600010e0607 */
/*09a0*/ IADD3.X R9, RZ, R9, RZ, P1, !PT ; /* 0x00000009ff097210 */
/* 0x000fe20000ffe4ff */
/*09b0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x0041ec000c101b06 */
/*09c0*/ @P0 BRA 0x900 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*09d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09e0*/ BRA 0x9e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15matrixTransposePdS_ii
.globl _Z15matrixTransposePdS_ii
.p2align 8
.type _Z15matrixTransposePdS_ii,@function
_Z15matrixTransposePdS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[4:5], null, s14, s3, v[1:2]
v_mad_u64_u32 v[5:6], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s5, v4
v_cmp_gt_i32_e64 s2, s4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_cmp_gt_i32 s5, 0
s_cselect_b32 s3, -1, 0
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[0:1], null, v4, s5, v[5:6]
v_mad_u64_u32 v[2:3], null, v5, s5, v[4:5]
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s5, s5, -1
s_cmp_lg_u32 s5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 3, v[0:1]
v_add_nc_u32_e32 v0, 1, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_load_b64 v[4:5], v[3:4], off
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[6:7], 3, v[2:3]
v_add_nc_u32_e32 v2, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[6:7], v[4:5], off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matrixTransposePdS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15matrixTransposePdS_ii, .Lfunc_end0-_Z15matrixTransposePdS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matrixTransposePdS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15matrixTransposePdS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001136b5_00000000-6_matrixTranspose.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15matrixTransposePdS_iiPdS_ii
.type _Z39__device_stub__Z15matrixTransposePdS_iiPdS_ii, @function
_Z39__device_stub__Z15matrixTransposePdS_iiPdS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrixTransposePdS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z15matrixTransposePdS_iiPdS_ii, .-_Z39__device_stub__Z15matrixTransposePdS_iiPdS_ii
.globl _Z15matrixTransposePdS_ii
.type _Z15matrixTransposePdS_ii, @function
_Z15matrixTransposePdS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15matrixTransposePdS_iiPdS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15matrixTransposePdS_ii, .-_Z15matrixTransposePdS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15matrixTransposePdS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixTransposePdS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "matrixTranspose.hip"
.globl _Z30__device_stub__matrixTransposePdS_ii # -- Begin function _Z30__device_stub__matrixTransposePdS_ii
.p2align 4, 0x90
.type _Z30__device_stub__matrixTransposePdS_ii,@function
_Z30__device_stub__matrixTransposePdS_ii: # @_Z30__device_stub__matrixTransposePdS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrixTransposePdS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__matrixTransposePdS_ii, .Lfunc_end0-_Z30__device_stub__matrixTransposePdS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixTransposePdS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15matrixTransposePdS_ii,@object # @_Z15matrixTransposePdS_ii
.section .rodata,"a",@progbits
.globl _Z15matrixTransposePdS_ii
.p2align 3, 0x0
_Z15matrixTransposePdS_ii:
.quad _Z30__device_stub__matrixTransposePdS_ii
.size _Z15matrixTransposePdS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15matrixTransposePdS_ii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__matrixTransposePdS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15matrixTransposePdS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include<stdio.h>
#include<cuda.h>
#include<time.h>
__global__ void zad2(float *a,float *b,float *c, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx<N) c[idx] = a[idx] + b[idx];
}
int main(void)
{
clock_t t1,t2,t5,t6,t7,t8;
float *a_h,*b_h,*c_h;
float *a_d,*b_d,*c_d;
const int N = 50000000;
size_t size = N * sizeof(float);
t1=clock();
a_h = (float *)malloc(size);
b_h = (float *)malloc(size);
c_h = (float *)malloc(size);
cudaMalloc((void **) &a_d,size);
cudaMalloc((void **) &b_d,size);
cudaMalloc((void **) &c_d,size);
t2=clock();
for(int i=0;i<N;i++)
{
a_h[i]=(float)(i+1);
b_h[i]=(float)(i+1);
c_h[i]=(float)(i+1);
}
cudaEvent_t start, stop;
float time;
cudaEventCreate(&start);
cudaEventCreate(&stop);
t5=clock();
cudaMemcpy(a_d,a_h,size,cudaMemcpyHostToDevice);
cudaMemcpy(b_d,b_h,size,cudaMemcpyHostToDevice);
cudaMemcpy(c_d,c_h,size,cudaMemcpyHostToDevice);
t6=clock();
int block_size = 1024;
int n_blocks = N/block_size + (N%block_size == 0 ? 0:1);
cudaEventRecord(start, 0);
zad2<<<n_blocks,block_size>>>(a_d,b_d,c_d,N);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
t7=clock();
cudaMemcpy(a_h,a_d,size,cudaMemcpyDeviceToHost);
cudaMemcpy(b_h,b_d,size,cudaMemcpyDeviceToHost);
cudaMemcpy(c_h,c_d,size,cudaMemcpyDeviceToHost);
t8=clock();
//for(int i=0;i<N;i++)
//{
//printf("%d rekord to: %f\n",i,c_h[i]);
//}
printf("Czas alokowania danych: %f s\n",(float)(t2-t1)/CLOCKS_PER_SEC);
printf("Czas przesyłu danych: %f s\n",(float)((t6-t5)+(t8-t7))/CLOCKS_PER_SEC);
free(a_h);
free(b_h);
free(c_h);
cudaFree(a_d);
cudaFree(b_d);
cudaFree(c_d);
cudaEventElapsedTime(&time, start, stop);
printf ("Czas wykonania dodawania wektorów: %f ms\n", time);
}
|
code for sm_80
Function : _Z4zad2PfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include<stdio.h>
#include<cuda.h>
#include<time.h>
__global__ void zad2(float *a,float *b,float *c, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx<N) c[idx] = a[idx] + b[idx];
}
int main(void)
{
clock_t t1,t2,t5,t6,t7,t8;
float *a_h,*b_h,*c_h;
float *a_d,*b_d,*c_d;
const int N = 50000000;
size_t size = N * sizeof(float);
t1=clock();
a_h = (float *)malloc(size);
b_h = (float *)malloc(size);
c_h = (float *)malloc(size);
cudaMalloc((void **) &a_d,size);
cudaMalloc((void **) &b_d,size);
cudaMalloc((void **) &c_d,size);
t2=clock();
for(int i=0;i<N;i++)
{
a_h[i]=(float)(i+1);
b_h[i]=(float)(i+1);
c_h[i]=(float)(i+1);
}
cudaEvent_t start, stop;
float time;
cudaEventCreate(&start);
cudaEventCreate(&stop);
t5=clock();
cudaMemcpy(a_d,a_h,size,cudaMemcpyHostToDevice);
cudaMemcpy(b_d,b_h,size,cudaMemcpyHostToDevice);
cudaMemcpy(c_d,c_h,size,cudaMemcpyHostToDevice);
t6=clock();
int block_size = 1024;
int n_blocks = N/block_size + (N%block_size == 0 ? 0:1);
cudaEventRecord(start, 0);
zad2<<<n_blocks,block_size>>>(a_d,b_d,c_d,N);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
t7=clock();
cudaMemcpy(a_h,a_d,size,cudaMemcpyDeviceToHost);
cudaMemcpy(b_h,b_d,size,cudaMemcpyDeviceToHost);
cudaMemcpy(c_h,c_d,size,cudaMemcpyDeviceToHost);
t8=clock();
//for(int i=0;i<N;i++)
//{
//printf("%d rekord to: %f\n",i,c_h[i]);
//}
printf("Czas alokowania danych: %f s\n",(float)(t2-t1)/CLOCKS_PER_SEC);
printf("Czas przesyłu danych: %f s\n",(float)((t6-t5)+(t8-t7))/CLOCKS_PER_SEC);
free(a_h);
free(b_h);
free(c_h);
cudaFree(a_d);
cudaFree(b_d);
cudaFree(c_d);
cudaEventElapsedTime(&time, start, stop);
printf ("Czas wykonania dodawania wektorów: %f ms\n", time);
}
|
.file "tmpxft_000d25af_00000000-6_z2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z4zad2PfS_S_iPfS_S_i
.type _Z28__device_stub__Z4zad2PfS_S_iPfS_S_i, @function
_Z28__device_stub__Z4zad2PfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4zad2PfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z4zad2PfS_S_iPfS_S_i, .-_Z28__device_stub__Z4zad2PfS_S_iPfS_S_i
.globl _Z4zad2PfS_S_i
.type _Z4zad2PfS_S_i, @function
_Z4zad2PfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z4zad2PfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4zad2PfS_S_i, .-_Z4zad2PfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Czas alokowania danych: %f s\n"
.LC2:
.string "Czas przesy\305\202u danych: %f s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Czas wykonania dodawania wektor\303\263w: %f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
call clock@PLT
movq %rax, %r15
movl $200000000, %edi
call malloc@PLT
movq %rax, %r12
movl $200000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $200000000, %edi
call malloc@PLT
movq %rax, %rbx
leaq 40(%rsp), %rdi
movl $200000000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $200000000, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $200000000, %esi
call cudaMalloc@PLT
call clock@PLT
movq %rax, 8(%rsp)
movl $1, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, -4(%r12,%rax,4)
movss %xmm0, -4(%rbp,%rax,4)
movss %xmm0, -4(%rbx,%rax,4)
addq $1, %rax
cmpq $50000001, %rax
jne .L12
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
call clock@PLT
movq %rax, %r14
movl $1, %ecx
movl $200000000, %edx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $200000000, %edx
movq %rbp, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $200000000, %edx
movq %rbx, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
movq %rax, 16(%rsp)
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $48829, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
call clock@PLT
movq %rax, %r13
movl $2, %ecx
movl $200000000, %edx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $200000000, %edx
movq 48(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $200000000, %edx
movq 56(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
call clock@PLT
movq %rax, 24(%rsp)
movq 8(%rsp), %rax
subq %r15, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rsp), %rax
subq %r14, %rax
movq 24(%rsp), %rdx
subq %r13, %rdx
addq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
leaq 92(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 92(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $50000000, %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z28__device_stub__Z4zad2PfS_S_iPfS_S_i
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z4zad2PfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z4zad2PfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include<stdio.h>
#include<cuda.h>
#include<time.h>
__global__ void zad2(float *a,float *b,float *c, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx<N) c[idx] = a[idx] + b[idx];
}
int main(void)
{
clock_t t1,t2,t5,t6,t7,t8;
float *a_h,*b_h,*c_h;
float *a_d,*b_d,*c_d;
const int N = 50000000;
size_t size = N * sizeof(float);
t1=clock();
a_h = (float *)malloc(size);
b_h = (float *)malloc(size);
c_h = (float *)malloc(size);
cudaMalloc((void **) &a_d,size);
cudaMalloc((void **) &b_d,size);
cudaMalloc((void **) &c_d,size);
t2=clock();
for(int i=0;i<N;i++)
{
a_h[i]=(float)(i+1);
b_h[i]=(float)(i+1);
c_h[i]=(float)(i+1);
}
cudaEvent_t start, stop;
float time;
cudaEventCreate(&start);
cudaEventCreate(&stop);
t5=clock();
cudaMemcpy(a_d,a_h,size,cudaMemcpyHostToDevice);
cudaMemcpy(b_d,b_h,size,cudaMemcpyHostToDevice);
cudaMemcpy(c_d,c_h,size,cudaMemcpyHostToDevice);
t6=clock();
int block_size = 1024;
int n_blocks = N/block_size + (N%block_size == 0 ? 0:1);
cudaEventRecord(start, 0);
zad2<<<n_blocks,block_size>>>(a_d,b_d,c_d,N);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
t7=clock();
cudaMemcpy(a_h,a_d,size,cudaMemcpyDeviceToHost);
cudaMemcpy(b_h,b_d,size,cudaMemcpyDeviceToHost);
cudaMemcpy(c_h,c_d,size,cudaMemcpyDeviceToHost);
t8=clock();
//for(int i=0;i<N;i++)
//{
//printf("%d rekord to: %f\n",i,c_h[i]);
//}
printf("Czas alokowania danych: %f s\n",(float)(t2-t1)/CLOCKS_PER_SEC);
printf("Czas przesyłu danych: %f s\n",(float)((t6-t5)+(t8-t7))/CLOCKS_PER_SEC);
free(a_h);
free(b_h);
free(c_h);
cudaFree(a_d);
cudaFree(b_d);
cudaFree(c_d);
cudaEventElapsedTime(&time, start, stop);
printf ("Czas wykonania dodawania wektorów: %f ms\n", time);
}
|
#include<stdio.h>
#include<hip/hip_runtime.h>
#include<time.h>
__global__ void zad2(float *a,float *b,float *c, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx<N) c[idx] = a[idx] + b[idx];
}
int main(void)
{
clock_t t1,t2,t5,t6,t7,t8;
float *a_h,*b_h,*c_h;
float *a_d,*b_d,*c_d;
const int N = 50000000;
size_t size = N * sizeof(float);
t1=clock();
a_h = (float *)malloc(size);
b_h = (float *)malloc(size);
c_h = (float *)malloc(size);
hipMalloc((void **) &a_d,size);
hipMalloc((void **) &b_d,size);
hipMalloc((void **) &c_d,size);
t2=clock();
for(int i=0;i<N;i++)
{
a_h[i]=(float)(i+1);
b_h[i]=(float)(i+1);
c_h[i]=(float)(i+1);
}
hipEvent_t start, stop;
float time;
hipEventCreate(&start);
hipEventCreate(&stop);
t5=clock();
hipMemcpy(a_d,a_h,size,hipMemcpyHostToDevice);
hipMemcpy(b_d,b_h,size,hipMemcpyHostToDevice);
hipMemcpy(c_d,c_h,size,hipMemcpyHostToDevice);
t6=clock();
int block_size = 1024;
int n_blocks = N/block_size + (N%block_size == 0 ? 0:1);
hipEventRecord(start, 0);
zad2<<<n_blocks,block_size>>>(a_d,b_d,c_d,N);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
t7=clock();
hipMemcpy(a_h,a_d,size,hipMemcpyDeviceToHost);
hipMemcpy(b_h,b_d,size,hipMemcpyDeviceToHost);
hipMemcpy(c_h,c_d,size,hipMemcpyDeviceToHost);
t8=clock();
//for(int i=0;i<N;i++)
//{
//printf("%d rekord to: %f\n",i,c_h[i]);
//}
printf("Czas alokowania danych: %f s\n",(float)(t2-t1)/CLOCKS_PER_SEC);
printf("Czas przesyłu danych: %f s\n",(float)((t6-t5)+(t8-t7))/CLOCKS_PER_SEC);
free(a_h);
free(b_h);
free(c_h);
hipFree(a_d);
hipFree(b_d);
hipFree(c_d);
hipEventElapsedTime(&time, start, stop);
printf ("Czas wykonania dodawania wektorów: %f ms\n", time);
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include<stdio.h>
#include<hip/hip_runtime.h>
#include<time.h>
__global__ void zad2(float *a,float *b,float *c, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx<N) c[idx] = a[idx] + b[idx];
}
int main(void)
{
clock_t t1,t2,t5,t6,t7,t8;
float *a_h,*b_h,*c_h;
float *a_d,*b_d,*c_d;
const int N = 50000000;
size_t size = N * sizeof(float);
t1=clock();
a_h = (float *)malloc(size);
b_h = (float *)malloc(size);
c_h = (float *)malloc(size);
hipMalloc((void **) &a_d,size);
hipMalloc((void **) &b_d,size);
hipMalloc((void **) &c_d,size);
t2=clock();
for(int i=0;i<N;i++)
{
a_h[i]=(float)(i+1);
b_h[i]=(float)(i+1);
c_h[i]=(float)(i+1);
}
hipEvent_t start, stop;
float time;
hipEventCreate(&start);
hipEventCreate(&stop);
t5=clock();
hipMemcpy(a_d,a_h,size,hipMemcpyHostToDevice);
hipMemcpy(b_d,b_h,size,hipMemcpyHostToDevice);
hipMemcpy(c_d,c_h,size,hipMemcpyHostToDevice);
t6=clock();
int block_size = 1024;
int n_blocks = N/block_size + (N%block_size == 0 ? 0:1);
hipEventRecord(start, 0);
zad2<<<n_blocks,block_size>>>(a_d,b_d,c_d,N);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
t7=clock();
hipMemcpy(a_h,a_d,size,hipMemcpyDeviceToHost);
hipMemcpy(b_h,b_d,size,hipMemcpyDeviceToHost);
hipMemcpy(c_h,c_d,size,hipMemcpyDeviceToHost);
t8=clock();
//for(int i=0;i<N;i++)
//{
//printf("%d rekord to: %f\n",i,c_h[i]);
//}
printf("Czas alokowania danych: %f s\n",(float)(t2-t1)/CLOCKS_PER_SEC);
printf("Czas przesyłu danych: %f s\n",(float)((t6-t5)+(t8-t7))/CLOCKS_PER_SEC);
free(a_h);
free(b_h);
free(c_h);
hipFree(a_d);
hipFree(b_d);
hipFree(c_d);
hipEventElapsedTime(&time, start, stop);
printf ("Czas wykonania dodawania wektorów: %f ms\n", time);
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4zad2PfS_S_i
.globl _Z4zad2PfS_S_i
.p2align 8
.type _Z4zad2PfS_S_i,@function
_Z4zad2PfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4zad2PfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4zad2PfS_S_i, .Lfunc_end0-_Z4zad2PfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4zad2PfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4zad2PfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include<stdio.h>
#include<hip/hip_runtime.h>
#include<time.h>
__global__ void zad2(float *a,float *b,float *c, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx<N) c[idx] = a[idx] + b[idx];
}
int main(void)
{
clock_t t1,t2,t5,t6,t7,t8;
float *a_h,*b_h,*c_h;
float *a_d,*b_d,*c_d;
const int N = 50000000;
size_t size = N * sizeof(float);
t1=clock();
a_h = (float *)malloc(size);
b_h = (float *)malloc(size);
c_h = (float *)malloc(size);
hipMalloc((void **) &a_d,size);
hipMalloc((void **) &b_d,size);
hipMalloc((void **) &c_d,size);
t2=clock();
for(int i=0;i<N;i++)
{
a_h[i]=(float)(i+1);
b_h[i]=(float)(i+1);
c_h[i]=(float)(i+1);
}
hipEvent_t start, stop;
float time;
hipEventCreate(&start);
hipEventCreate(&stop);
t5=clock();
hipMemcpy(a_d,a_h,size,hipMemcpyHostToDevice);
hipMemcpy(b_d,b_h,size,hipMemcpyHostToDevice);
hipMemcpy(c_d,c_h,size,hipMemcpyHostToDevice);
t6=clock();
int block_size = 1024;
int n_blocks = N/block_size + (N%block_size == 0 ? 0:1);
hipEventRecord(start, 0);
zad2<<<n_blocks,block_size>>>(a_d,b_d,c_d,N);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
t7=clock();
hipMemcpy(a_h,a_d,size,hipMemcpyDeviceToHost);
hipMemcpy(b_h,b_d,size,hipMemcpyDeviceToHost);
hipMemcpy(c_h,c_d,size,hipMemcpyDeviceToHost);
t8=clock();
//for(int i=0;i<N;i++)
//{
//printf("%d rekord to: %f\n",i,c_h[i]);
//}
printf("Czas alokowania danych: %f s\n",(float)(t2-t1)/CLOCKS_PER_SEC);
printf("Czas przesyłu danych: %f s\n",(float)((t6-t5)+(t8-t7))/CLOCKS_PER_SEC);
free(a_h);
free(b_h);
free(c_h);
hipFree(a_d);
hipFree(b_d);
hipFree(c_d);
hipEventElapsedTime(&time, start, stop);
printf ("Czas wykonania dodawania wektorów: %f ms\n", time);
}
|
.text
.file "z2.hip"
.globl _Z19__device_stub__zad2PfS_S_i # -- Begin function _Z19__device_stub__zad2PfS_S_i
.p2align 4, 0x90
.type _Z19__device_stub__zad2PfS_S_i,@function
_Z19__device_stub__zad2PfS_S_i: # @_Z19__device_stub__zad2PfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4zad2PfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__zad2PfS_S_i, .Lfunc_end0-_Z19__device_stub__zad2PfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
callq clock
movq %rax, 64(%rsp) # 8-byte Spill
movl $200000000, %edi # imm = 0xBEBC200
callq malloc
movq %rax, %rbx
movl $200000000, %edi # imm = 0xBEBC200
callq malloc
movq %rax, %r14
movl $200000000, %edi # imm = 0xBEBC200
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $200000000, %esi # imm = 0xBEBC200
callq hipMalloc
leaq 16(%rsp), %rdi
movl $200000000, %esi # imm = 0xBEBC200
callq hipMalloc
leaq 8(%rsp), %rdi
movl $200000000, %esi # imm = 0xBEBC200
callq hipMalloc
xorl %r12d, %r12d
callq clock
movq %rax, %rbp
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%r12), %rax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r12,4)
movss %xmm0, (%r14,%r12,4)
movss %xmm0, (%r15,%r12,4)
movq %rax, %r12
cmpq $50000000, %rax # imm = 0x2FAF080
jne .LBB1_1
# %bb.2:
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
callq clock
movq %rax, 56(%rsp) # 8-byte Spill
movq 24(%rsp), %rdi
movl $200000000, %edx # imm = 0xBEBC200
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $200000000, %edx # imm = 0xBEBC200
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $200000000, %edx # imm = 0xBEBC200
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
callq clock
movq %rax, %r12
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 47805(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl $50000000, 44(%rsp) # imm = 0x2FAF080
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 44(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z4zad2PfS_S_i, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
callq clock
movq %rax, %r13
movq 24(%rsp), %rsi
movl $200000000, %edx # imm = 0xBEBC200
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
movl $200000000, %edx # imm = 0xBEBC200
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movl $200000000, %edx # imm = 0xBEBC200
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
callq clock
subq 64(%rsp), %rbp # 8-byte Folded Reload
cvtsi2ss %rbp, %xmm0
movq %rax, %rbp
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 56(%rsp), %rax # 8-byte Reload
addq %r13, %rax
subq %rax, %r12
addq %rbp, %r12
xorps %xmm0, %xmm0
cvtsi2ss %r12, %xmm0
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 144(%rsp), %rdi
callq hipEventElapsedTime
movss 144(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4zad2PfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4zad2PfS_S_i,@object # @_Z4zad2PfS_S_i
.section .rodata,"a",@progbits
.globl _Z4zad2PfS_S_i
.p2align 3, 0x0
_Z4zad2PfS_S_i:
.quad _Z19__device_stub__zad2PfS_S_i
.size _Z4zad2PfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Czas alokowania danych: %f s\n"
.size .L.str, 30
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Czas przesy\305\202u danych: %f s\n"
.size .L.str.1, 29
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Czas wykonania dodawania wektor\303\263w: %f ms\n"
.size .L.str.2, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4zad2PfS_S_i"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__zad2PfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4zad2PfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z4zad2PfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4zad2PfS_S_i
.globl _Z4zad2PfS_S_i
.p2align 8
.type _Z4zad2PfS_S_i,@function
_Z4zad2PfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4zad2PfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4zad2PfS_S_i, .Lfunc_end0-_Z4zad2PfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4zad2PfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4zad2PfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000d25af_00000000-6_z2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z4zad2PfS_S_iPfS_S_i
.type _Z28__device_stub__Z4zad2PfS_S_iPfS_S_i, @function
_Z28__device_stub__Z4zad2PfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4zad2PfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z4zad2PfS_S_iPfS_S_i, .-_Z28__device_stub__Z4zad2PfS_S_iPfS_S_i
.globl _Z4zad2PfS_S_i
.type _Z4zad2PfS_S_i, @function
_Z4zad2PfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z4zad2PfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4zad2PfS_S_i, .-_Z4zad2PfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Czas alokowania danych: %f s\n"
.LC2:
.string "Czas przesy\305\202u danych: %f s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Czas wykonania dodawania wektor\303\263w: %f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
call clock@PLT
movq %rax, %r15
movl $200000000, %edi
call malloc@PLT
movq %rax, %r12
movl $200000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $200000000, %edi
call malloc@PLT
movq %rax, %rbx
leaq 40(%rsp), %rdi
movl $200000000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $200000000, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $200000000, %esi
call cudaMalloc@PLT
call clock@PLT
movq %rax, 8(%rsp)
movl $1, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, -4(%r12,%rax,4)
movss %xmm0, -4(%rbp,%rax,4)
movss %xmm0, -4(%rbx,%rax,4)
addq $1, %rax
cmpq $50000001, %rax
jne .L12
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
call clock@PLT
movq %rax, %r14
movl $1, %ecx
movl $200000000, %edx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $200000000, %edx
movq %rbp, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $200000000, %edx
movq %rbx, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
movq %rax, 16(%rsp)
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $48829, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
call clock@PLT
movq %rax, %r13
movl $2, %ecx
movl $200000000, %edx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $200000000, %edx
movq 48(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $200000000, %edx
movq 56(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
call clock@PLT
movq %rax, 24(%rsp)
movq 8(%rsp), %rax
subq %r15, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rsp), %rax
subq %r14, %rax
movq 24(%rsp), %rdx
subq %r13, %rdx
addq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
leaq 92(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 92(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $50000000, %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z28__device_stub__Z4zad2PfS_S_iPfS_S_i
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z4zad2PfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z4zad2PfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "z2.hip"
.globl _Z19__device_stub__zad2PfS_S_i # -- Begin function _Z19__device_stub__zad2PfS_S_i
.p2align 4, 0x90
.type _Z19__device_stub__zad2PfS_S_i,@function
_Z19__device_stub__zad2PfS_S_i: # @_Z19__device_stub__zad2PfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4zad2PfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__zad2PfS_S_i, .Lfunc_end0-_Z19__device_stub__zad2PfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
callq clock
movq %rax, 64(%rsp) # 8-byte Spill
movl $200000000, %edi # imm = 0xBEBC200
callq malloc
movq %rax, %rbx
movl $200000000, %edi # imm = 0xBEBC200
callq malloc
movq %rax, %r14
movl $200000000, %edi # imm = 0xBEBC200
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $200000000, %esi # imm = 0xBEBC200
callq hipMalloc
leaq 16(%rsp), %rdi
movl $200000000, %esi # imm = 0xBEBC200
callq hipMalloc
leaq 8(%rsp), %rdi
movl $200000000, %esi # imm = 0xBEBC200
callq hipMalloc
xorl %r12d, %r12d
callq clock
movq %rax, %rbp
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%r12), %rax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r12,4)
movss %xmm0, (%r14,%r12,4)
movss %xmm0, (%r15,%r12,4)
movq %rax, %r12
cmpq $50000000, %rax # imm = 0x2FAF080
jne .LBB1_1
# %bb.2:
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
callq clock
movq %rax, 56(%rsp) # 8-byte Spill
movq 24(%rsp), %rdi
movl $200000000, %edx # imm = 0xBEBC200
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $200000000, %edx # imm = 0xBEBC200
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $200000000, %edx # imm = 0xBEBC200
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
callq clock
movq %rax, %r12
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 47805(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl $50000000, 44(%rsp) # imm = 0x2FAF080
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 44(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z4zad2PfS_S_i, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
callq clock
movq %rax, %r13
movq 24(%rsp), %rsi
movl $200000000, %edx # imm = 0xBEBC200
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
movl $200000000, %edx # imm = 0xBEBC200
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movl $200000000, %edx # imm = 0xBEBC200
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
callq clock
subq 64(%rsp), %rbp # 8-byte Folded Reload
cvtsi2ss %rbp, %xmm0
movq %rax, %rbp
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 56(%rsp), %rax # 8-byte Reload
addq %r13, %rax
subq %rax, %r12
addq %rbp, %r12
xorps %xmm0, %xmm0
cvtsi2ss %r12, %xmm0
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 144(%rsp), %rdi
callq hipEventElapsedTime
movss 144(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4zad2PfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4zad2PfS_S_i,@object # @_Z4zad2PfS_S_i
.section .rodata,"a",@progbits
.globl _Z4zad2PfS_S_i
.p2align 3, 0x0
_Z4zad2PfS_S_i:
.quad _Z19__device_stub__zad2PfS_S_i
.size _Z4zad2PfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Czas alokowania danych: %f s\n"
.size .L.str, 30
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Czas przesy\305\202u danych: %f s\n"
.size .L.str.1, 29
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Czas wykonania dodawania wektor\303\263w: %f ms\n"
.size .L.str.2, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4zad2PfS_S_i"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__zad2PfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4zad2PfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
inline void create_beta_h(int *h_beta, int *h_left, int *h_rows, int *h_cols, int m, int nnz){
// Note: Index in h_rows and h_cols starts at 1
int *h_visited = (int*)malloc( sizeof(int) * m );
for(int i=0; i<m; i++) h_left[i] = -1;
for(int i=0; i<m; i++) h_visited[i] = 0;
for(int i=0; i<m; i++) h_beta[i] = -1;
for(int l=0; l<nnz; l++)
if (h_visited[h_rows[l]-1] == 0){
h_beta[h_cols[l]-1] = h_beta[h_cols[l]-1] > h_rows[l]-1 ? h_beta[h_cols[l]-1] : h_rows[l]-1;
h_visited[h_rows[l]-1] = 1;
h_left[h_rows[l]-1] = h_cols[l]-1;
}
free(h_visited);
}
inline void create_beta(int *d_beta, int *d_left, int *h_rows, int *h_cols, int m, int nnz){
int *h_beta = (int*)malloc( sizeof(int) * m );
int *h_left = (int*)malloc( sizeof(int) * m );
create_beta_h(h_beta, h_left, h_rows, h_cols, m, nnz);
cudaMemcpy(d_beta, h_beta, m*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_left, h_left, m*sizeof(int), cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
free(h_beta);
free(h_left);
}
|
code for sm_80
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
inline void create_beta_h(int *h_beta, int *h_left, int *h_rows, int *h_cols, int m, int nnz){
// Note: Index in h_rows and h_cols starts at 1
int *h_visited = (int*)malloc( sizeof(int) * m );
for(int i=0; i<m; i++) h_left[i] = -1;
for(int i=0; i<m; i++) h_visited[i] = 0;
for(int i=0; i<m; i++) h_beta[i] = -1;
for(int l=0; l<nnz; l++)
if (h_visited[h_rows[l]-1] == 0){
h_beta[h_cols[l]-1] = h_beta[h_cols[l]-1] > h_rows[l]-1 ? h_beta[h_cols[l]-1] : h_rows[l]-1;
h_visited[h_rows[l]-1] = 1;
h_left[h_rows[l]-1] = h_cols[l]-1;
}
free(h_visited);
}
inline void create_beta(int *d_beta, int *d_left, int *h_rows, int *h_cols, int m, int nnz){
int *h_beta = (int*)malloc( sizeof(int) * m );
int *h_left = (int*)malloc( sizeof(int) * m );
create_beta_h(h_beta, h_left, h_rows, h_cols, m, nnz);
cudaMemcpy(d_beta, h_beta, m*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_left, h_left, m*sizeof(int), cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
free(h_beta);
free(h_left);
}
|
.file "tmpxft_0004561d_00000000-6_beta.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
inline void create_beta_h(int *h_beta, int *h_left, int *h_rows, int *h_cols, int m, int nnz){
// Note: Index in h_rows and h_cols starts at 1
int *h_visited = (int*)malloc( sizeof(int) * m );
for(int i=0; i<m; i++) h_left[i] = -1;
for(int i=0; i<m; i++) h_visited[i] = 0;
for(int i=0; i<m; i++) h_beta[i] = -1;
for(int l=0; l<nnz; l++)
if (h_visited[h_rows[l]-1] == 0){
h_beta[h_cols[l]-1] = h_beta[h_cols[l]-1] > h_rows[l]-1 ? h_beta[h_cols[l]-1] : h_rows[l]-1;
h_visited[h_rows[l]-1] = 1;
h_left[h_rows[l]-1] = h_cols[l]-1;
}
free(h_visited);
}
inline void create_beta(int *d_beta, int *d_left, int *h_rows, int *h_cols, int m, int nnz){
int *h_beta = (int*)malloc( sizeof(int) * m );
int *h_left = (int*)malloc( sizeof(int) * m );
create_beta_h(h_beta, h_left, h_rows, h_cols, m, nnz);
cudaMemcpy(d_beta, h_beta, m*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_left, h_left, m*sizeof(int), cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
free(h_beta);
free(h_left);
}
|
#include <hip/hip_runtime.h>
inline void create_beta_h(int *h_beta, int *h_left, int *h_rows, int *h_cols, int m, int nnz){
// Note: Index in h_rows and h_cols starts at 1
int *h_visited = (int*)malloc( sizeof(int) * m );
for(int i=0; i<m; i++) h_left[i] = -1;
for(int i=0; i<m; i++) h_visited[i] = 0;
for(int i=0; i<m; i++) h_beta[i] = -1;
for(int l=0; l<nnz; l++)
if (h_visited[h_rows[l]-1] == 0){
h_beta[h_cols[l]-1] = h_beta[h_cols[l]-1] > h_rows[l]-1 ? h_beta[h_cols[l]-1] : h_rows[l]-1;
h_visited[h_rows[l]-1] = 1;
h_left[h_rows[l]-1] = h_cols[l]-1;
}
free(h_visited);
}
inline void create_beta(int *d_beta, int *d_left, int *h_rows, int *h_cols, int m, int nnz){
int *h_beta = (int*)malloc( sizeof(int) * m );
int *h_left = (int*)malloc( sizeof(int) * m );
create_beta_h(h_beta, h_left, h_rows, h_cols, m, nnz);
hipMemcpy(d_beta, h_beta, m*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_left, h_left, m*sizeof(int), hipMemcpyHostToDevice);
hipDeviceSynchronize();
free(h_beta);
free(h_left);
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
inline void create_beta_h(int *h_beta, int *h_left, int *h_rows, int *h_cols, int m, int nnz){
// Note: Index in h_rows and h_cols starts at 1
int *h_visited = (int*)malloc( sizeof(int) * m );
for(int i=0; i<m; i++) h_left[i] = -1;
for(int i=0; i<m; i++) h_visited[i] = 0;
for(int i=0; i<m; i++) h_beta[i] = -1;
for(int l=0; l<nnz; l++)
if (h_visited[h_rows[l]-1] == 0){
h_beta[h_cols[l]-1] = h_beta[h_cols[l]-1] > h_rows[l]-1 ? h_beta[h_cols[l]-1] : h_rows[l]-1;
h_visited[h_rows[l]-1] = 1;
h_left[h_rows[l]-1] = h_cols[l]-1;
}
free(h_visited);
}
inline void create_beta(int *d_beta, int *d_left, int *h_rows, int *h_cols, int m, int nnz){
int *h_beta = (int*)malloc( sizeof(int) * m );
int *h_left = (int*)malloc( sizeof(int) * m );
create_beta_h(h_beta, h_left, h_rows, h_cols, m, nnz);
hipMemcpy(d_beta, h_beta, m*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_left, h_left, m*sizeof(int), hipMemcpyHostToDevice);
hipDeviceSynchronize();
free(h_beta);
free(h_left);
}
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
inline void create_beta_h(int *h_beta, int *h_left, int *h_rows, int *h_cols, int m, int nnz){
// Note: Index in h_rows and h_cols starts at 1
int *h_visited = (int*)malloc( sizeof(int) * m );
for(int i=0; i<m; i++) h_left[i] = -1;
for(int i=0; i<m; i++) h_visited[i] = 0;
for(int i=0; i<m; i++) h_beta[i] = -1;
for(int l=0; l<nnz; l++)
if (h_visited[h_rows[l]-1] == 0){
h_beta[h_cols[l]-1] = h_beta[h_cols[l]-1] > h_rows[l]-1 ? h_beta[h_cols[l]-1] : h_rows[l]-1;
h_visited[h_rows[l]-1] = 1;
h_left[h_rows[l]-1] = h_cols[l]-1;
}
free(h_visited);
}
inline void create_beta(int *d_beta, int *d_left, int *h_rows, int *h_cols, int m, int nnz){
int *h_beta = (int*)malloc( sizeof(int) * m );
int *h_left = (int*)malloc( sizeof(int) * m );
create_beta_h(h_beta, h_left, h_rows, h_cols, m, nnz);
hipMemcpy(d_beta, h_beta, m*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_left, h_left, m*sizeof(int), hipMemcpyHostToDevice);
hipDeviceSynchronize();
free(h_beta);
free(h_left);
}
|
.text
.file "beta.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0004561d_00000000-6_beta.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "beta.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#include <time.h>
#include <driver_types.h>
//Performs inner product of vectors on CPU
void multiply_cpu(int *a, int *b, int* c, int N)
{
int d[N];
for (int i = 0; i < N; ++i)
{
d[i] = a[i]*b[i];
}
for (int i = 0; i < N; ++i)
{
*c += d[i];
}
}
//Performs inner product of vectors on device
__global__ void multiply_kernel(int *a,int *b, int *c, int N)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
int val;
if(id < N)
{
val = a[id]*b[id];
atomicAdd(c, val);
}
}
//Inner Product of vectors a = (a1,...,an), b = (b1,...,bn) can be written as a1b1+...+anbn
//This computes the vector {a1b1,...,anbn} where the sum is carried out on the CPU
__global__ void multiply_kernel_add_cpu(int *a, int* b, int* c, int N)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N)
{
c[id] = a[id] * b[id];
}
}
//Inner Product of vectors a = (a1,...,an), b = (b1,...,bn) can be written as a1b1+...+anbn
//This computes the sum, where a is assumed to contain {a1b1,...,anbn} where the product has already
//been computed on the CPU
__global__ void multiply_cpu_add_kernel(int* a, int* b, int N)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N)
{
int val = a[id];
atomicAdd(b, val);
}
}
int main(int argc, char *argv[]) {
int N = 4096;
int T = 10, B = 1; // threads per block and blocks per grid
int c[1];
int *dev_a, *dev_b, *dev_c, *dev_d;
cudaDeviceProp device;
cudaGetDeviceProperties(&device, 0);
int maxthreadsperblock = device.maxThreadsPerBlock;
long memory = device.totalGlobalMem;
size_t shared_mem = device.sharedMemPerBlock;
int major = device.major;
int minor = device.minor;
printf("Max Threads per Block: %d\n", maxthreadsperblock);
printf("Total Global Memory: %d\n", (int)memory);
printf("Shared Memory: %d\n", (int)shared_mem);
printf("Major Compute Capability: %d\n", major);
printf("Minor Compute Capability: %d\n", minor);
do {
printf("Enter size of array: ");
scanf("%d", &N);
long memory_required = 3*(long)N + 1;
if (memory_required > memory)
{
printf("Too big to fit on Device!\n");
continue;
}
printf("Enter number of threads per block: ");
scanf("%d",&T);
if (T > maxthreadsperblock)
{
printf("Max threads per block exceeded\n");
continue;
}
printf("\nEnter number of blocks per grid: ");
scanf("%d",&B);
if (T * B < N) printf("Error T x B < N, try again\n");
} while (T * B < N);
int a[N],b[N], d[N];
cudaEvent_t start, stop; // using cuda events to measure time
float elapsed_time_ms; // which is applicable for asynchronous code also
//allocate memory on device and check for errors
if (cudaMalloc((void**)&dev_a,N * sizeof(int)) != cudaSuccess) {
puts("Not enough Space on Device!");
return 0;
}
if (cudaMalloc((void**)&dev_b,N * sizeof(int)) != cudaSuccess) {
puts("Not enough Space on Device!");
goto cleanup_a;
}
if (cudaMalloc((void**)&dev_c,sizeof(int)) != cudaSuccess) {
puts("Not enough Space on Device!");
goto cleanup_b;
}
if (cudaMalloc((void**)&dev_d, N * sizeof(int)) != cudaSuccess) {
puts("Not enough Space on Device!");
goto cleanup_c;
}
for(int i=0;i<N;i++) { // load arrays with some numbers
a[i] = i;
b[i] = i*1;
}
*c = 0;
cudaMemcpy(dev_a, a , N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b , N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_c, c , sizeof(int),cudaMemcpyHostToDevice);
cudaEventCreate( &start ); // instrument code to measure start time
cudaEventCreate( &stop );
// Do Inner product on the Device
cudaEventRecord( start, 0 );
multiply_kernel<<<B,T>>>(dev_a,dev_b,dev_c, N);
cudaMemcpy(c,dev_c,sizeof(int),cudaMemcpyDeviceToHost);
cudaEventRecord( stop, 0 ); // instrument code to measue end time
cudaEventSynchronize( stop );
cudaEventElapsedTime( &elapsed_time_ms, start, stop );
printf("Device Inner Product: %d ", *c);
printf("Time: %f ms.\n", elapsed_time_ms); // print out execution time
*c = 0;
//Do Inner product on the CPU
cudaEventRecord( start, 0 );
multiply_cpu(a,b,c, N);
cudaEventRecord( stop, 0 ); // instrument code to measue end time
cudaEventSynchronize( stop );
cudaEventElapsedTime( &elapsed_time_ms, start, stop );
printf("CPU Inner Product: %d ", *c);
printf("Time: %f ms.\n", elapsed_time_ms); // print out execution time
*c = 0;
//Do Multiplication on the Device, and addition on the CPU
cudaEventRecord( start, 0 );
multiply_kernel_add_cpu<<<B,T>>>(dev_a,dev_b,dev_d, N);
cudaMemcpy(d, dev_d, sizeof(int)*N, cudaMemcpyDeviceToHost);
for (int i = 0; i < N; ++i)
{
*c += d[i];
}
cudaEventRecord( stop, 0 ); // instrument code to measue end time
cudaEventSynchronize( stop );
cudaEventElapsedTime( &elapsed_time_ms, start, stop );
printf("Multiplication on Device. Addition on CPU. Inner product: %d ", *c);
printf("Time: %f ms.\n", elapsed_time_ms); // print out execution time
*c = 0;
//Do Multiplication on the CPU and addition on the Device
cudaEventRecord( start, 0 );
for (int i = 0; i < N; ++i)
{
d[i] = a[i] * b[i];
}
cudaMemcpy(dev_d, d, sizeof(int)*N, cudaMemcpyHostToDevice);
cudaMemcpy(dev_c, c, sizeof(int), cudaMemcpyHostToDevice);
multiply_cpu_add_kernel<<<B,T>>>(dev_d, dev_c, N);
cudaMemcpy(c, dev_c, sizeof(int), cudaMemcpyDeviceToHost);
cudaEventRecord( stop, 0 ); // instrument code to measue end time
cudaEventSynchronize( stop );
cudaEventElapsedTime( &elapsed_time_ms, start, stop );
printf("Multiplication on CPU. Addition on Device. Inner Product: %d ", *c);
printf("Time: %f ms.\n", elapsed_time_ms); // print out execution time
// clean up
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaFree(dev_d);
cleanup_c:
cudaFree(dev_c);
cleanup_b:
cudaFree(dev_b);
cleanup_a:
cudaFree(dev_a);
return 0;
}
|
code for sm_80
Function : _Z23multiply_cpu_add_kernelPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*00b0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*00c0*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*00d0*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*00e0*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fc80000000f00 */
/*00f0*/ ISETP.EQ.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x001fe2000bf02070 */
/*0100*/ REDUX.SUM UR5, R2 ; /* 0x00000000020573c4 */
/* 0x004e24000000c000 */
/*0110*/ IMAD.U32 R7, RZ, RZ, UR5 ; /* 0x00000005ff077e24 */
/* 0x001fd4000f8e00ff */
/*0120*/ @P0 RED.E.ADD.STRONG.GPU [R4.64], R7 ; /* 0x000000070400098e */
/* 0x000fe2000c10e186 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z23multiply_kernel_add_cpuPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ IMAD R9, R4, R3, RZ ; /* 0x0000000304097224 */
/* 0x004fca00078e02ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15multiply_kernelPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R2, R3, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x000fc800078e0203 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe400078e0203 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*00d0*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fe20000000f00 */
/*00e0*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*00f0*/ S2R R6, SR_LANEID ; /* 0x0000000000067919 */
/* 0x000e2a0000000000 */
/*0100*/ ISETP.EQ.U32.AND P0, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x001fc4000bf02070 */
/*0110*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fe20000000f00 */
/*0120*/ IMAD R0, R4, R3, RZ ; /* 0x0000000304007224 */
/* 0x004fc800078e02ff */
/*0130*/ REDUX.SUM UR5, R0 ; /* 0x00000000000573c4 */
/* 0x000e24000000c000 */
/*0140*/ MOV R9, UR5 ; /* 0x0000000500097c02 */
/* 0x001fca0008000f00 */
/*0150*/ @P0 RED.E.ADD.STRONG.GPU [R6.64], R9 ; /* 0x000000090600098e */
/* 0x000fe2000c10e186 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#include <time.h>
#include <driver_types.h>
//Performs inner product of vectors on CPU
void multiply_cpu(int *a, int *b, int* c, int N)
{
int d[N];
for (int i = 0; i < N; ++i)
{
d[i] = a[i]*b[i];
}
for (int i = 0; i < N; ++i)
{
*c += d[i];
}
}
//Performs inner product of vectors on device
__global__ void multiply_kernel(int *a,int *b, int *c, int N)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
int val;
if(id < N)
{
val = a[id]*b[id];
atomicAdd(c, val);
}
}
//Inner Product of vectors a = (a1,...,an), b = (b1,...,bn) can be written as a1b1+...+anbn
//This computes the vector {a1b1,...,anbn} where the sum is carried out on the CPU
__global__ void multiply_kernel_add_cpu(int *a, int* b, int* c, int N)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N)
{
c[id] = a[id] * b[id];
}
}
//Inner Product of vectors a = (a1,...,an), b = (b1,...,bn) can be written as a1b1+...+anbn
//This computes the sum, where a is assumed to contain {a1b1,...,anbn} where the product has already
//been computed on the CPU
__global__ void multiply_cpu_add_kernel(int* a, int* b, int N)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N)
{
int val = a[id];
atomicAdd(b, val);
}
}
int main(int argc, char *argv[]) {
int N = 4096;
int T = 10, B = 1; // threads per block and blocks per grid
int c[1];
int *dev_a, *dev_b, *dev_c, *dev_d;
cudaDeviceProp device;
cudaGetDeviceProperties(&device, 0);
int maxthreadsperblock = device.maxThreadsPerBlock;
long memory = device.totalGlobalMem;
size_t shared_mem = device.sharedMemPerBlock;
int major = device.major;
int minor = device.minor;
printf("Max Threads per Block: %d\n", maxthreadsperblock);
printf("Total Global Memory: %d\n", (int)memory);
printf("Shared Memory: %d\n", (int)shared_mem);
printf("Major Compute Capability: %d\n", major);
printf("Minor Compute Capability: %d\n", minor);
do {
printf("Enter size of array: ");
scanf("%d", &N);
long memory_required = 3*(long)N + 1;
if (memory_required > memory)
{
printf("Too big to fit on Device!\n");
continue;
}
printf("Enter number of threads per block: ");
scanf("%d",&T);
if (T > maxthreadsperblock)
{
printf("Max threads per block exceeded\n");
continue;
}
printf("\nEnter number of blocks per grid: ");
scanf("%d",&B);
if (T * B < N) printf("Error T x B < N, try again\n");
} while (T * B < N);
int a[N],b[N], d[N];
cudaEvent_t start, stop; // using cuda events to measure time
float elapsed_time_ms; // which is applicable for asynchronous code also
//allocate memory on device and check for errors
if (cudaMalloc((void**)&dev_a,N * sizeof(int)) != cudaSuccess) {
puts("Not enough Space on Device!");
return 0;
}
if (cudaMalloc((void**)&dev_b,N * sizeof(int)) != cudaSuccess) {
puts("Not enough Space on Device!");
goto cleanup_a;
}
if (cudaMalloc((void**)&dev_c,sizeof(int)) != cudaSuccess) {
puts("Not enough Space on Device!");
goto cleanup_b;
}
if (cudaMalloc((void**)&dev_d, N * sizeof(int)) != cudaSuccess) {
puts("Not enough Space on Device!");
goto cleanup_c;
}
for(int i=0;i<N;i++) { // load arrays with some numbers
a[i] = i;
b[i] = i*1;
}
*c = 0;
cudaMemcpy(dev_a, a , N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b , N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_c, c , sizeof(int),cudaMemcpyHostToDevice);
cudaEventCreate( &start ); // instrument code to measure start time
cudaEventCreate( &stop );
// Do Inner product on the Device
cudaEventRecord( start, 0 );
multiply_kernel<<<B,T>>>(dev_a,dev_b,dev_c, N);
cudaMemcpy(c,dev_c,sizeof(int),cudaMemcpyDeviceToHost);
cudaEventRecord( stop, 0 ); // instrument code to measue end time
cudaEventSynchronize( stop );
cudaEventElapsedTime( &elapsed_time_ms, start, stop );
printf("Device Inner Product: %d ", *c);
printf("Time: %f ms.\n", elapsed_time_ms); // print out execution time
*c = 0;
//Do Inner product on the CPU
cudaEventRecord( start, 0 );
multiply_cpu(a,b,c, N);
cudaEventRecord( stop, 0 ); // instrument code to measue end time
cudaEventSynchronize( stop );
cudaEventElapsedTime( &elapsed_time_ms, start, stop );
printf("CPU Inner Product: %d ", *c);
printf("Time: %f ms.\n", elapsed_time_ms); // print out execution time
*c = 0;
//Do Multiplication on the Device, and addition on the CPU
cudaEventRecord( start, 0 );
multiply_kernel_add_cpu<<<B,T>>>(dev_a,dev_b,dev_d, N);
cudaMemcpy(d, dev_d, sizeof(int)*N, cudaMemcpyDeviceToHost);
for (int i = 0; i < N; ++i)
{
*c += d[i];
}
cudaEventRecord( stop, 0 ); // instrument code to measue end time
cudaEventSynchronize( stop );
cudaEventElapsedTime( &elapsed_time_ms, start, stop );
printf("Multiplication on Device. Addition on CPU. Inner product: %d ", *c);
printf("Time: %f ms.\n", elapsed_time_ms); // print out execution time
*c = 0;
//Do Multiplication on the CPU and addition on the Device
cudaEventRecord( start, 0 );
for (int i = 0; i < N; ++i)
{
d[i] = a[i] * b[i];
}
cudaMemcpy(dev_d, d, sizeof(int)*N, cudaMemcpyHostToDevice);
cudaMemcpy(dev_c, c, sizeof(int), cudaMemcpyHostToDevice);
multiply_cpu_add_kernel<<<B,T>>>(dev_d, dev_c, N);
cudaMemcpy(c, dev_c, sizeof(int), cudaMemcpyDeviceToHost);
cudaEventRecord( stop, 0 ); // instrument code to measue end time
cudaEventSynchronize( stop );
cudaEventElapsedTime( &elapsed_time_ms, start, stop );
printf("Multiplication on CPU. Addition on Device. Inner Product: %d ", *c);
printf("Time: %f ms.\n", elapsed_time_ms); // print out execution time
// clean up
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaFree(dev_d);
cleanup_c:
cudaFree(dev_c);
cleanup_b:
cudaFree(dev_b);
cleanup_a:
cudaFree(dev_a);
return 0;
}
|
.file "tmpxft_001648e1_00000000-6_innerproduct.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12multiply_cpuPiS_S_i
.type _Z12multiply_cpuPiS_S_i, @function
_Z12multiply_cpuPiS_S_i:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
subq $16, %rsp
movq %rdi, %r8
movq %rsi, %r9
movq %rdx, %r10
movq %fs:40, %rax
movq %rax, -8(%rbp)
xorl %eax, %eax
movslq %ecx, %rdi
salq $2, %rdi
leaq 15(%rdi), %rax
movq %rax, %rsi
andq $-16, %rsi
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L4:
cmpq %rdx, %rsp
je .L5
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L4
.L5:
movq %rsi, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L6
orq $0, -8(%rsp,%rax)
.L6:
movq %rsp, %rsi
testl %ecx, %ecx
jle .L3
movl $0, %eax
.L8:
movl (%r8,%rax), %edx
imull (%r9,%rax), %edx
movl %edx, (%rsi,%rax)
addq $4, %rax
cmpq %rax, %rdi
jne .L8
movl (%r10), %ecx
movq %rsi, %rax
addq %rdi, %rsi
.L9:
addl (%rax), %ecx
addq $4, %rax
cmpq %rsi, %rax
jne .L9
movl %ecx, (%r10)
.L3:
movq -8(%rbp), %rax
subq %fs:40, %rax
jne .L14
leave
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L14:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z12multiply_cpuPiS_S_i, .-_Z12multiply_cpuPiS_S_i
.globl _Z40__device_stub__Z15multiply_kernelPiS_S_iPiS_S_i
.type _Z40__device_stub__Z15multiply_kernelPiS_S_iPiS_S_i, @function
_Z40__device_stub__Z15multiply_kernelPiS_S_iPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15multiply_kernelPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z40__device_stub__Z15multiply_kernelPiS_S_iPiS_S_i, .-_Z40__device_stub__Z15multiply_kernelPiS_S_iPiS_S_i
.globl _Z15multiply_kernelPiS_S_i
.type _Z15multiply_kernelPiS_S_i, @function
_Z15multiply_kernelPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15multiply_kernelPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z15multiply_kernelPiS_S_i, .-_Z15multiply_kernelPiS_S_i
.globl _Z48__device_stub__Z23multiply_kernel_add_cpuPiS_S_iPiS_S_i
.type _Z48__device_stub__Z23multiply_kernel_add_cpuPiS_S_iPiS_S_i, @function
_Z48__device_stub__Z23multiply_kernel_add_cpuPiS_S_iPiS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23multiply_kernel_add_cpuPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z48__device_stub__Z23multiply_kernel_add_cpuPiS_S_iPiS_S_i, .-_Z48__device_stub__Z23multiply_kernel_add_cpuPiS_S_iPiS_S_i
.globl _Z23multiply_kernel_add_cpuPiS_S_i
.type _Z23multiply_kernel_add_cpuPiS_S_i, @function
_Z23multiply_kernel_add_cpuPiS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z23multiply_kernel_add_cpuPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z23multiply_kernel_add_cpuPiS_S_i, .-_Z23multiply_kernel_add_cpuPiS_S_i
.globl _Z46__device_stub__Z23multiply_cpu_add_kernelPiS_iPiS_i
.type _Z46__device_stub__Z23multiply_cpu_add_kernelPiS_iPiS_i, @function
_Z46__device_stub__Z23multiply_cpu_add_kernelPiS_iPiS_i:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23multiply_cpu_add_kernelPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z46__device_stub__Z23multiply_cpu_add_kernelPiS_iPiS_i, .-_Z46__device_stub__Z23multiply_cpu_add_kernelPiS_iPiS_i
.globl _Z23multiply_cpu_add_kernelPiS_i
.type _Z23multiply_cpu_add_kernelPiS_i, @function
_Z23multiply_cpu_add_kernelPiS_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z23multiply_cpu_add_kernelPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z23multiply_cpu_add_kernelPiS_i, .-_Z23multiply_cpu_add_kernelPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Max Threads per Block: %d\n"
.LC1:
.string "Total Global Memory: %d\n"
.LC2:
.string "Shared Memory: %d\n"
.LC3:
.string "Major Compute Capability: %d\n"
.LC4:
.string "Minor Compute Capability: %d\n"
.LC5:
.string "Enter size of array: "
.LC6:
.string "%d"
.LC7:
.string "Too big to fit on Device!\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "Enter number of threads per block: "
.align 8
.LC9:
.string "Max threads per block exceeded\n"
.align 8
.LC10:
.string "\nEnter number of blocks per grid: "
.section .rodata.str1.1
.LC11:
.string "Error T x B < N, try again\n"
.LC12:
.string "Not enough Space on Device!"
.LC13:
.string "Device Inner Product: %d "
.LC14:
.string "Time: %f ms.\n"
.LC15:
.string "CPU Inner Product: %d "
.section .rodata.str1.8
.align 8
.LC16:
.string "Multiplication on Device. Addition on CPU. Inner product: %d "
.align 8
.LC17:
.string "Multiplication on CPU. Addition on Device. Inner Product: %d "
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $1144, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movl $4096, -1184(%rbp)
movl $10, -1180(%rbp)
movl $1, -1176(%rbp)
leaq -1088(%rbp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl -768(%rbp), %r14d
movq -800(%rbp), %r12
movq -792(%rbp), %rbx
movl -728(%rbp), %r15d
movl -724(%rbp), %r13d
movl %r14d, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %r13
leaq .LC6(%rip), %rbx
leaq .LC8(%rip), %r15
jmp .L44
.L78:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L41:
movl -1184(%rbp), %edx
movl -1180(%rbp), %eax
imull -1176(%rbp), %eax
cmpl %edx, %eax
jge .L43
.L44:
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq -1184(%rbp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movslq -1184(%rbp), %rax
leaq (%rax,%rax,2), %rax
cmpq %r12, %rax
jge .L78
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq -1180(%rbp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
cmpl %r14d, -1180(%rbp)
jg .L79
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq -1176(%rbp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl -1184(%rbp), %edx
movl -1180(%rbp), %eax
imull -1176(%rbp), %eax
cmpl %edx, %eax
jl .L80
.L43:
movslq %edx, %rdx
leaq 0(,%rdx,4), %rsi
leaq 15(%rsi), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L45:
cmpq %rdx, %rsp
je .L46
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L45
.L79:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L41
.L80:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L41
.L46:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L47
orq $0, -8(%rsp,%rax)
.L47:
movq %rsp, %rbx
leaq 15(%rsi), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L48:
cmpq %rdx, %rsp
je .L49
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L48
.L49:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L50
orq $0, -8(%rsp,%rax)
.L50:
movq %rsp, %r12
leaq 15(%rsi), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L51:
cmpq %rdx, %rsp
je .L52
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L51
.L52:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L53
orq $0, -8(%rsp,%rax)
.L53:
movq %rsp, %r13
leaq -1168(%rbp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L81
movslq -1184(%rbp), %rsi
salq $2, %rsi
leaq -1160(%rbp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L82
leaq -1152(%rbp), %rdi
movl $4, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L83
movslq -1184(%rbp), %rsi
salq $2, %rsi
leaq -1144(%rbp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L60
movl -1184(%rbp), %ecx
testl %ecx, %ecx
jle .L62
movslq %ecx, %rdx
movl $0, %eax
.L64:
movl %eax, (%rbx,%rax,4)
movl %eax, (%r12,%rax,4)
addq $1, %rax
cmpq %rdx, %rax
jne .L64
.L62:
movl $0, -1092(%rbp)
movslq %ecx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq -1168(%rbp), %rdi
call cudaMemcpy@PLT
movslq -1184(%rbp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r12, %rsi
movq -1160(%rbp), %rdi
call cudaMemcpy@PLT
leaq -1092(%rbp), %rsi
movl $1, %ecx
movl $4, %edx
movq -1152(%rbp), %rdi
call cudaMemcpy@PLT
leaq -1136(%rbp), %rdi
call cudaEventCreate@PLT
leaq -1128(%rbp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq -1136(%rbp), %rdi
call cudaEventRecord@PLT
movl -1180(%rbp), %eax
movl %eax, -1104(%rbp)
movl $1, -1100(%rbp)
movl $1, -1096(%rbp)
movl -1176(%rbp), %eax
movl %eax, -1116(%rbp)
movl $1, -1112(%rbp)
movl $1, -1108(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -1104(%rbp), %rdx
movl $1, %ecx
movq -1116(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L84
.L65:
leaq -1092(%rbp), %r15
movl $2, %ecx
movl $4, %edx
movq -1152(%rbp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq -1128(%rbp), %rdi
call cudaEventRecord@PLT
movq -1128(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -1172(%rbp), %r14
movq -1128(%rbp), %rdx
movq -1136(%rbp), %rsi
movq %r14, %rdi
call cudaEventElapsedTime@PLT
movl -1092(%rbp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd -1172(%rbp), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, -1092(%rbp)
movl $0, %esi
movq -1136(%rbp), %rdi
call cudaEventRecord@PLT
movl -1184(%rbp), %ecx
movq %r15, %rdx
movq %r12, %rsi
movq %rbx, %rdi
call _Z12multiply_cpuPiS_S_i
movl $0, %esi
movq -1128(%rbp), %rdi
call cudaEventRecord@PLT
movq -1128(%rbp), %rdi
call cudaEventSynchronize@PLT
movq -1128(%rbp), %rdx
movq -1136(%rbp), %rsi
movq %r14, %rdi
call cudaEventElapsedTime@PLT
movl -1092(%rbp), %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd -1172(%rbp), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, -1092(%rbp)
movl $0, %esi
movq -1136(%rbp), %rdi
call cudaEventRecord@PLT
movl -1180(%rbp), %eax
movl %eax, -1104(%rbp)
movl $1, -1100(%rbp)
movl $1, -1096(%rbp)
movl -1176(%rbp), %eax
movl %eax, -1116(%rbp)
movl $1, -1112(%rbp)
movl $1, -1108(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -1104(%rbp), %rdx
movl $1, %ecx
movq -1116(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L85
.L66:
movslq -1184(%rbp), %rdx
salq $2, %rdx
movl $2, %ecx
movq -1144(%rbp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl -1184(%rbp), %edx
testl %edx, %edx
jle .L67
movl -1092(%rbp), %ecx
movq %r13, %rax
movslq %edx, %rdx
leaq 0(%r13,%rdx,4), %rsi
.L68:
addl (%rax), %ecx
addq $4, %rax
cmpq %rsi, %rax
jne .L68
movl %ecx, -1092(%rbp)
.L67:
movl $0, %esi
movq -1128(%rbp), %rdi
call cudaEventRecord@PLT
movq -1128(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -1172(%rbp), %rdi
movq -1128(%rbp), %rdx
movq -1136(%rbp), %rsi
call cudaEventElapsedTime@PLT
movl -1092(%rbp), %edx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd -1172(%rbp), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, -1092(%rbp)
movl $0, %esi
movq -1136(%rbp), %rdi
call cudaEventRecord@PLT
movl -1184(%rbp), %esi
testl %esi, %esi
jle .L69
movslq %esi, %rcx
salq $2, %rcx
movl $0, %eax
.L70:
movl (%rbx,%rax), %edx
imull (%r12,%rax), %edx
movl %edx, 0(%r13,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L70
.L69:
movslq %esi, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r13, %rsi
movq -1144(%rbp), %rdi
call cudaMemcpy@PLT
leaq -1092(%rbp), %rsi
movl $1, %ecx
movl $4, %edx
movq -1152(%rbp), %rdi
call cudaMemcpy@PLT
movl -1180(%rbp), %eax
movl %eax, -1104(%rbp)
movl $1, -1100(%rbp)
movl $1, -1096(%rbp)
movl -1176(%rbp), %eax
movl %eax, -1116(%rbp)
movl $1, -1112(%rbp)
movl $1, -1108(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -1104(%rbp), %rdx
movl $1, %ecx
movq -1116(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L86
.L71:
leaq -1092(%rbp), %rdi
movl $2, %ecx
movl $4, %edx
movq -1152(%rbp), %rsi
call cudaMemcpy@PLT
movl $0, %esi
movq -1128(%rbp), %rdi
call cudaEventRecord@PLT
movq -1128(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -1172(%rbp), %rdi
movq -1128(%rbp), %rdx
movq -1136(%rbp), %rsi
call cudaEventElapsedTime@PLT
movl -1092(%rbp), %edx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd -1172(%rbp), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq -1136(%rbp), %rdi
call cudaEventDestroy@PLT
movq -1128(%rbp), %rdi
call cudaEventDestroy@PLT
movq -1144(%rbp), %rdi
call cudaFree@PLT
.L63:
movq -1152(%rbp), %rdi
call cudaFree@PLT
.L59:
movq -1160(%rbp), %rdi
call cudaFree@PLT
.L57:
movq -1168(%rbp), %rdi
call cudaFree@PLT
.L55:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L87
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L81:
.cfi_restore_state
leaq .LC12(%rip), %rdi
call puts@PLT
jmp .L55
.L82:
leaq .LC12(%rip), %rdi
call puts@PLT
jmp .L57
.L83:
leaq .LC12(%rip), %rdi
call puts@PLT
jmp .L59
.L60:
leaq .LC12(%rip), %rdi
call puts@PLT
jmp .L63
.L84:
movl -1184(%rbp), %ecx
movq -1152(%rbp), %rdx
movq -1160(%rbp), %rsi
movq -1168(%rbp), %rdi
call _Z40__device_stub__Z15multiply_kernelPiS_S_iPiS_S_i
jmp .L65
.L85:
movl -1184(%rbp), %ecx
movq -1144(%rbp), %rdx
movq -1160(%rbp), %rsi
movq -1168(%rbp), %rdi
call _Z48__device_stub__Z23multiply_kernel_add_cpuPiS_S_iPiS_S_i
jmp .L66
.L86:
movl -1184(%rbp), %edx
movq -1152(%rbp), %rsi
movq -1144(%rbp), %rdi
call _Z46__device_stub__Z23multiply_cpu_add_kernelPiS_iPiS_i
jmp .L71
.L87:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC18:
.string "_Z23multiply_cpu_add_kernelPiS_i"
.align 8
.LC19:
.string "_Z23multiply_kernel_add_cpuPiS_S_i"
.section .rodata.str1.1
.LC20:
.string "_Z15multiply_kernelPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z23multiply_cpu_add_kernelPiS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z23multiply_kernel_add_cpuPiS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z15multiply_kernelPiS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#include <time.h>
#include <driver_types.h>
//Performs inner product of vectors on CPU
void multiply_cpu(int *a, int *b, int* c, int N)
{
int d[N];
for (int i = 0; i < N; ++i)
{
d[i] = a[i]*b[i];
}
for (int i = 0; i < N; ++i)
{
*c += d[i];
}
}
//Performs inner product of vectors on device
__global__ void multiply_kernel(int *a,int *b, int *c, int N)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
int val;
if(id < N)
{
val = a[id]*b[id];
atomicAdd(c, val);
}
}
//Inner Product of vectors a = (a1,...,an), b = (b1,...,bn) can be written as a1b1+...+anbn
//This computes the vector {a1b1,...,anbn} where the sum is carried out on the CPU
__global__ void multiply_kernel_add_cpu(int *a, int* b, int* c, int N)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N)
{
c[id] = a[id] * b[id];
}
}
//Inner Product of vectors a = (a1,...,an), b = (b1,...,bn) can be written as a1b1+...+anbn
//This computes the sum, where a is assumed to contain {a1b1,...,anbn} where the product has already
//been computed on the CPU
__global__ void multiply_cpu_add_kernel(int* a, int* b, int N)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N)
{
int val = a[id];
atomicAdd(b, val);
}
}
int main(int argc, char *argv[]) {
int N = 4096;
int T = 10, B = 1; // threads per block and blocks per grid
int c[1];
int *dev_a, *dev_b, *dev_c, *dev_d;
cudaDeviceProp device;
cudaGetDeviceProperties(&device, 0);
int maxthreadsperblock = device.maxThreadsPerBlock;
long memory = device.totalGlobalMem;
size_t shared_mem = device.sharedMemPerBlock;
int major = device.major;
int minor = device.minor;
printf("Max Threads per Block: %d\n", maxthreadsperblock);
printf("Total Global Memory: %d\n", (int)memory);
printf("Shared Memory: %d\n", (int)shared_mem);
printf("Major Compute Capability: %d\n", major);
printf("Minor Compute Capability: %d\n", minor);
do {
printf("Enter size of array: ");
scanf("%d", &N);
long memory_required = 3*(long)N + 1;
if (memory_required > memory)
{
printf("Too big to fit on Device!\n");
continue;
}
printf("Enter number of threads per block: ");
scanf("%d",&T);
if (T > maxthreadsperblock)
{
printf("Max threads per block exceeded\n");
continue;
}
printf("\nEnter number of blocks per grid: ");
scanf("%d",&B);
if (T * B < N) printf("Error T x B < N, try again\n");
} while (T * B < N);
int a[N],b[N], d[N];
cudaEvent_t start, stop; // using cuda events to measure time
float elapsed_time_ms; // which is applicable for asynchronous code also
//allocate memory on device and check for errors
if (cudaMalloc((void**)&dev_a,N * sizeof(int)) != cudaSuccess) {
puts("Not enough Space on Device!");
return 0;
}
if (cudaMalloc((void**)&dev_b,N * sizeof(int)) != cudaSuccess) {
puts("Not enough Space on Device!");
goto cleanup_a;
}
if (cudaMalloc((void**)&dev_c,sizeof(int)) != cudaSuccess) {
puts("Not enough Space on Device!");
goto cleanup_b;
}
if (cudaMalloc((void**)&dev_d, N * sizeof(int)) != cudaSuccess) {
puts("Not enough Space on Device!");
goto cleanup_c;
}
for(int i=0;i<N;i++) { // load arrays with some numbers
a[i] = i;
b[i] = i*1;
}
*c = 0;
cudaMemcpy(dev_a, a , N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b , N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_c, c , sizeof(int),cudaMemcpyHostToDevice);
cudaEventCreate( &start ); // instrument code to measure start time
cudaEventCreate( &stop );
// Do Inner product on the Device
cudaEventRecord( start, 0 );
multiply_kernel<<<B,T>>>(dev_a,dev_b,dev_c, N);
cudaMemcpy(c,dev_c,sizeof(int),cudaMemcpyDeviceToHost);
cudaEventRecord( stop, 0 ); // instrument code to measue end time
cudaEventSynchronize( stop );
cudaEventElapsedTime( &elapsed_time_ms, start, stop );
printf("Device Inner Product: %d ", *c);
printf("Time: %f ms.\n", elapsed_time_ms); // print out execution time
*c = 0;
//Do Inner product on the CPU
cudaEventRecord( start, 0 );
multiply_cpu(a,b,c, N);
cudaEventRecord( stop, 0 ); // instrument code to measue end time
cudaEventSynchronize( stop );
cudaEventElapsedTime( &elapsed_time_ms, start, stop );
printf("CPU Inner Product: %d ", *c);
printf("Time: %f ms.\n", elapsed_time_ms); // print out execution time
*c = 0;
//Do Multiplication on the Device, and addition on the CPU
cudaEventRecord( start, 0 );
multiply_kernel_add_cpu<<<B,T>>>(dev_a,dev_b,dev_d, N);
cudaMemcpy(d, dev_d, sizeof(int)*N, cudaMemcpyDeviceToHost);
for (int i = 0; i < N; ++i)
{
*c += d[i];
}
cudaEventRecord( stop, 0 ); // instrument code to measue end time
cudaEventSynchronize( stop );
cudaEventElapsedTime( &elapsed_time_ms, start, stop );
printf("Multiplication on Device. Addition on CPU. Inner product: %d ", *c);
printf("Time: %f ms.\n", elapsed_time_ms); // print out execution time
*c = 0;
//Do Multiplication on the CPU and addition on the Device
cudaEventRecord( start, 0 );
for (int i = 0; i < N; ++i)
{
d[i] = a[i] * b[i];
}
cudaMemcpy(dev_d, d, sizeof(int)*N, cudaMemcpyHostToDevice);
cudaMemcpy(dev_c, c, sizeof(int), cudaMemcpyHostToDevice);
multiply_cpu_add_kernel<<<B,T>>>(dev_d, dev_c, N);
cudaMemcpy(c, dev_c, sizeof(int), cudaMemcpyDeviceToHost);
cudaEventRecord( stop, 0 ); // instrument code to measue end time
cudaEventSynchronize( stop );
cudaEventElapsedTime( &elapsed_time_ms, start, stop );
printf("Multiplication on CPU. Addition on Device. Inner Product: %d ", *c);
printf("Time: %f ms.\n", elapsed_time_ms); // print out execution time
// clean up
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaFree(dev_d);
cleanup_c:
cudaFree(dev_c);
cleanup_b:
cudaFree(dev_b);
cleanup_a:
cudaFree(dev_a);
return 0;
}
|
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <time.h>
#include <hip/driver_types.h>
//Performs inner product of vectors on CPU
void multiply_cpu(int *a, int *b, int* c, int N)
{
int d[N];
for (int i = 0; i < N; ++i)
{
d[i] = a[i]*b[i];
}
for (int i = 0; i < N; ++i)
{
*c += d[i];
}
}
//Performs inner product of vectors on device
__global__ void multiply_kernel(int *a,int *b, int *c, int N)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
int val;
if(id < N)
{
val = a[id]*b[id];
atomicAdd(c, val);
}
}
//Inner Product of vectors a = (a1,...,an), b = (b1,...,bn) can be written as a1b1+...+anbn
//This computes the vector {a1b1,...,anbn} where the sum is carried out on the CPU
__global__ void multiply_kernel_add_cpu(int *a, int* b, int* c, int N)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N)
{
c[id] = a[id] * b[id];
}
}
//Inner Product of vectors a = (a1,...,an), b = (b1,...,bn) can be written as a1b1+...+anbn
//This computes the sum, where a is assumed to contain {a1b1,...,anbn} where the product has already
//been computed on the CPU
__global__ void multiply_cpu_add_kernel(int* a, int* b, int N)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N)
{
int val = a[id];
atomicAdd(b, val);
}
}
int main(int argc, char *argv[]) {
int N = 4096;
int T = 10, B = 1; // threads per block and blocks per grid
int c[1];
int *dev_a, *dev_b, *dev_c, *dev_d;
hipDeviceProp_t device;
hipGetDeviceProperties(&device, 0);
int maxthreadsperblock = device.maxThreadsPerBlock;
long memory = device.totalGlobalMem;
size_t shared_mem = device.sharedMemPerBlock;
int major = device.major;
int minor = device.minor;
printf("Max Threads per Block: %d\n", maxthreadsperblock);
printf("Total Global Memory: %d\n", (int)memory);
printf("Shared Memory: %d\n", (int)shared_mem);
printf("Major Compute Capability: %d\n", major);
printf("Minor Compute Capability: %d\n", minor);
do {
printf("Enter size of array: ");
scanf("%d", &N);
long memory_required = 3*(long)N + 1;
if (memory_required > memory)
{
printf("Too big to fit on Device!\n");
continue;
}
printf("Enter number of threads per block: ");
scanf("%d",&T);
if (T > maxthreadsperblock)
{
printf("Max threads per block exceeded\n");
continue;
}
printf("\nEnter number of blocks per grid: ");
scanf("%d",&B);
if (T * B < N) printf("Error T x B < N, try again\n");
} while (T * B < N);
int a[N],b[N], d[N];
hipEvent_t start, stop; // using cuda events to measure time
float elapsed_time_ms; // which is applicable for asynchronous code also
//allocate memory on device and check for errors
if (hipMalloc((void**)&dev_a,N * sizeof(int)) != hipSuccess) {
puts("Not enough Space on Device!");
return 0;
}
if (hipMalloc((void**)&dev_b,N * sizeof(int)) != hipSuccess) {
puts("Not enough Space on Device!");
goto cleanup_a;
}
if (hipMalloc((void**)&dev_c,sizeof(int)) != hipSuccess) {
puts("Not enough Space on Device!");
goto cleanup_b;
}
if (hipMalloc((void**)&dev_d, N * sizeof(int)) != hipSuccess) {
puts("Not enough Space on Device!");
goto cleanup_c;
}
for(int i=0;i<N;i++) { // load arrays with some numbers
a[i] = i;
b[i] = i*1;
}
*c = 0;
hipMemcpy(dev_a, a , N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_b, b , N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_c, c , sizeof(int),hipMemcpyHostToDevice);
hipEventCreate( &start ); // instrument code to measure start time
hipEventCreate( &stop );
// Do Inner product on the Device
hipEventRecord( start, 0 );
multiply_kernel<<<B,T>>>(dev_a,dev_b,dev_c, N);
hipMemcpy(c,dev_c,sizeof(int),hipMemcpyDeviceToHost);
hipEventRecord( stop, 0 ); // instrument code to measue end time
hipEventSynchronize( stop );
hipEventElapsedTime( &elapsed_time_ms, start, stop );
printf("Device Inner Product: %d ", *c);
printf("Time: %f ms.\n", elapsed_time_ms); // print out execution time
*c = 0;
//Do Inner product on the CPU
hipEventRecord( start, 0 );
multiply_cpu(a,b,c, N);
hipEventRecord( stop, 0 ); // instrument code to measue end time
hipEventSynchronize( stop );
hipEventElapsedTime( &elapsed_time_ms, start, stop );
printf("CPU Inner Product: %d ", *c);
printf("Time: %f ms.\n", elapsed_time_ms); // print out execution time
*c = 0;
//Do Multiplication on the Device, and addition on the CPU
hipEventRecord( start, 0 );
multiply_kernel_add_cpu<<<B,T>>>(dev_a,dev_b,dev_d, N);
hipMemcpy(d, dev_d, sizeof(int)*N, hipMemcpyDeviceToHost);
for (int i = 0; i < N; ++i)
{
*c += d[i];
}
hipEventRecord( stop, 0 ); // instrument code to measue end time
hipEventSynchronize( stop );
hipEventElapsedTime( &elapsed_time_ms, start, stop );
printf("Multiplication on Device. Addition on CPU. Inner product: %d ", *c);
printf("Time: %f ms.\n", elapsed_time_ms); // print out execution time
*c = 0;
//Do Multiplication on the CPU and addition on the Device
hipEventRecord( start, 0 );
for (int i = 0; i < N; ++i)
{
d[i] = a[i] * b[i];
}
hipMemcpy(dev_d, d, sizeof(int)*N, hipMemcpyHostToDevice);
hipMemcpy(dev_c, c, sizeof(int), hipMemcpyHostToDevice);
multiply_cpu_add_kernel<<<B,T>>>(dev_d, dev_c, N);
hipMemcpy(c, dev_c, sizeof(int), hipMemcpyDeviceToHost);
hipEventRecord( stop, 0 ); // instrument code to measue end time
hipEventSynchronize( stop );
hipEventElapsedTime( &elapsed_time_ms, start, stop );
printf("Multiplication on CPU. Addition on Device. Inner Product: %d ", *c);
printf("Time: %f ms.\n", elapsed_time_ms); // print out execution time
// clean up
hipEventDestroy(start);
hipEventDestroy(stop);
hipFree(dev_d);
cleanup_c:
hipFree(dev_c);
cleanup_b:
hipFree(dev_b);
cleanup_a:
hipFree(dev_a);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <time.h>
#include <hip/driver_types.h>
//Performs inner product of vectors on CPU
void multiply_cpu(int *a, int *b, int* c, int N)
{
int d[N];
for (int i = 0; i < N; ++i)
{
d[i] = a[i]*b[i];
}
for (int i = 0; i < N; ++i)
{
*c += d[i];
}
}
//Performs inner product of vectors on device
__global__ void multiply_kernel(int *a,int *b, int *c, int N)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
int val;
if(id < N)
{
val = a[id]*b[id];
atomicAdd(c, val);
}
}
//Inner Product of vectors a = (a1,...,an), b = (b1,...,bn) can be written as a1b1+...+anbn
//This computes the vector {a1b1,...,anbn} where the sum is carried out on the CPU
__global__ void multiply_kernel_add_cpu(int *a, int* b, int* c, int N)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N)
{
c[id] = a[id] * b[id];
}
}
//Inner Product of vectors a = (a1,...,an), b = (b1,...,bn) can be written as a1b1+...+anbn
//This computes the sum, where a is assumed to contain {a1b1,...,anbn} where the product has already
//been computed on the CPU
__global__ void multiply_cpu_add_kernel(int* a, int* b, int N)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N)
{
int val = a[id];
atomicAdd(b, val);
}
}
int main(int argc, char *argv[]) {
int N = 4096;
int T = 10, B = 1; // threads per block and blocks per grid
int c[1];
int *dev_a, *dev_b, *dev_c, *dev_d;
hipDeviceProp_t device;
hipGetDeviceProperties(&device, 0);
int maxthreadsperblock = device.maxThreadsPerBlock;
long memory = device.totalGlobalMem;
size_t shared_mem = device.sharedMemPerBlock;
int major = device.major;
int minor = device.minor;
printf("Max Threads per Block: %d\n", maxthreadsperblock);
printf("Total Global Memory: %d\n", (int)memory);
printf("Shared Memory: %d\n", (int)shared_mem);
printf("Major Compute Capability: %d\n", major);
printf("Minor Compute Capability: %d\n", minor);
do {
printf("Enter size of array: ");
scanf("%d", &N);
long memory_required = 3*(long)N + 1;
if (memory_required > memory)
{
printf("Too big to fit on Device!\n");
continue;
}
printf("Enter number of threads per block: ");
scanf("%d",&T);
if (T > maxthreadsperblock)
{
printf("Max threads per block exceeded\n");
continue;
}
printf("\nEnter number of blocks per grid: ");
scanf("%d",&B);
if (T * B < N) printf("Error T x B < N, try again\n");
} while (T * B < N);
int a[N],b[N], d[N];
hipEvent_t start, stop; // using cuda events to measure time
float elapsed_time_ms; // which is applicable for asynchronous code also
//allocate memory on device and check for errors
if (hipMalloc((void**)&dev_a,N * sizeof(int)) != hipSuccess) {
puts("Not enough Space on Device!");
return 0;
}
if (hipMalloc((void**)&dev_b,N * sizeof(int)) != hipSuccess) {
puts("Not enough Space on Device!");
goto cleanup_a;
}
if (hipMalloc((void**)&dev_c,sizeof(int)) != hipSuccess) {
puts("Not enough Space on Device!");
goto cleanup_b;
}
if (hipMalloc((void**)&dev_d, N * sizeof(int)) != hipSuccess) {
puts("Not enough Space on Device!");
goto cleanup_c;
}
for(int i=0;i<N;i++) { // load arrays with some numbers
a[i] = i;
b[i] = i*1;
}
*c = 0;
hipMemcpy(dev_a, a , N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_b, b , N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_c, c , sizeof(int),hipMemcpyHostToDevice);
hipEventCreate( &start ); // instrument code to measure start time
hipEventCreate( &stop );
// Do Inner product on the Device
hipEventRecord( start, 0 );
multiply_kernel<<<B,T>>>(dev_a,dev_b,dev_c, N);
hipMemcpy(c,dev_c,sizeof(int),hipMemcpyDeviceToHost);
hipEventRecord( stop, 0 ); // instrument code to measue end time
hipEventSynchronize( stop );
hipEventElapsedTime( &elapsed_time_ms, start, stop );
printf("Device Inner Product: %d ", *c);
printf("Time: %f ms.\n", elapsed_time_ms); // print out execution time
*c = 0;
//Do Inner product on the CPU
hipEventRecord( start, 0 );
multiply_cpu(a,b,c, N);
hipEventRecord( stop, 0 ); // instrument code to measue end time
hipEventSynchronize( stop );
hipEventElapsedTime( &elapsed_time_ms, start, stop );
printf("CPU Inner Product: %d ", *c);
printf("Time: %f ms.\n", elapsed_time_ms); // print out execution time
*c = 0;
//Do Multiplication on the Device, and addition on the CPU
hipEventRecord( start, 0 );
multiply_kernel_add_cpu<<<B,T>>>(dev_a,dev_b,dev_d, N);
hipMemcpy(d, dev_d, sizeof(int)*N, hipMemcpyDeviceToHost);
for (int i = 0; i < N; ++i)
{
*c += d[i];
}
hipEventRecord( stop, 0 ); // instrument code to measue end time
hipEventSynchronize( stop );
hipEventElapsedTime( &elapsed_time_ms, start, stop );
printf("Multiplication on Device. Addition on CPU. Inner product: %d ", *c);
printf("Time: %f ms.\n", elapsed_time_ms); // print out execution time
*c = 0;
//Do Multiplication on the CPU and addition on the Device
hipEventRecord( start, 0 );
for (int i = 0; i < N; ++i)
{
d[i] = a[i] * b[i];
}
hipMemcpy(dev_d, d, sizeof(int)*N, hipMemcpyHostToDevice);
hipMemcpy(dev_c, c, sizeof(int), hipMemcpyHostToDevice);
multiply_cpu_add_kernel<<<B,T>>>(dev_d, dev_c, N);
hipMemcpy(c, dev_c, sizeof(int), hipMemcpyDeviceToHost);
hipEventRecord( stop, 0 ); // instrument code to measue end time
hipEventSynchronize( stop );
hipEventElapsedTime( &elapsed_time_ms, start, stop );
printf("Multiplication on CPU. Addition on Device. Inner Product: %d ", *c);
printf("Time: %f ms.\n", elapsed_time_ms); // print out execution time
// clean up
hipEventDestroy(start);
hipEventDestroy(stop);
hipFree(dev_d);
cleanup_c:
hipFree(dev_c);
cleanup_b:
hipFree(dev_b);
cleanup_a:
hipFree(dev_a);
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15multiply_kernelPiS_S_i
.globl _Z15multiply_kernelPiS_S_i
.p2align 8
.type _Z15multiply_kernelPiS_S_i,@function
_Z15multiply_kernelPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s2, exec_lo
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v0, v0, v2
.LBB0_2:
s_ctz_i32_b32 s4, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s5, v0, s4
s_lshl_b32 s4, 1, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s2, s2, s4
s_add_i32 s3, s3, s5
s_cmp_lg_u32 s2, 0
s_cbranch_scc1 .LBB0_2
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x10
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s3
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15multiply_kernelPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15multiply_kernelPiS_S_i, .Lfunc_end0-_Z15multiply_kernelPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z23multiply_kernel_add_cpuPiS_S_i
.globl _Z23multiply_kernel_add_cpuPiS_S_i
.p2align 8
.type _Z23multiply_kernel_add_cpuPiS_S_i,@function
_Z23multiply_kernel_add_cpuPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23multiply_kernel_add_cpuPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z23multiply_kernel_add_cpuPiS_S_i, .Lfunc_end1-_Z23multiply_kernel_add_cpuPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z23multiply_cpu_add_kernelPiS_i
.globl _Z23multiply_cpu_add_kernelPiS_i
.p2align 8
.type _Z23multiply_cpu_add_kernelPiS_i,@function
_Z23multiply_cpu_add_kernelPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB2_5
s_load_b64 s[4:5], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s3, exec_lo
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v0, v[0:1], off
.LBB2_2:
s_ctz_i32_b32 s4, s3
s_waitcnt vmcnt(0)
v_readlane_b32 s5, v0, s4
s_lshl_b32 s4, 1, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s3, s3, s4
s_add_i32 s2, s2, s5
s_cmp_lg_u32 s3, 0
s_cbranch_scc1 .LBB2_2
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB2_5
s_load_b64 s[0:1], s[0:1], 0x8
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB2_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23multiply_cpu_add_kernelPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z23multiply_cpu_add_kernelPiS_i, .Lfunc_end2-_Z23multiply_cpu_add_kernelPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15multiply_kernelPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15multiply_kernelPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23multiply_kernel_add_cpuPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23multiply_kernel_add_cpuPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23multiply_cpu_add_kernelPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23multiply_cpu_add_kernelPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <time.h>
#include <hip/driver_types.h>
//Performs inner product of vectors on CPU
void multiply_cpu(int *a, int *b, int* c, int N)
{
int d[N];
for (int i = 0; i < N; ++i)
{
d[i] = a[i]*b[i];
}
for (int i = 0; i < N; ++i)
{
*c += d[i];
}
}
//Performs inner product of vectors on device
__global__ void multiply_kernel(int *a,int *b, int *c, int N)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
int val;
if(id < N)
{
val = a[id]*b[id];
atomicAdd(c, val);
}
}
//Inner Product of vectors a = (a1,...,an), b = (b1,...,bn) can be written as a1b1+...+anbn
//This computes the vector {a1b1,...,anbn} where the sum is carried out on the CPU
__global__ void multiply_kernel_add_cpu(int *a, int* b, int* c, int N)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N)
{
c[id] = a[id] * b[id];
}
}
//Inner Product of vectors a = (a1,...,an), b = (b1,...,bn) can be written as a1b1+...+anbn
//This computes the sum, where a is assumed to contain {a1b1,...,anbn} where the product has already
//been computed on the CPU
__global__ void multiply_cpu_add_kernel(int* a, int* b, int N)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N)
{
int val = a[id];
atomicAdd(b, val);
}
}
int main(int argc, char *argv[]) {
int N = 4096;
int T = 10, B = 1; // threads per block and blocks per grid
int c[1];
int *dev_a, *dev_b, *dev_c, *dev_d;
hipDeviceProp_t device;
hipGetDeviceProperties(&device, 0);
int maxthreadsperblock = device.maxThreadsPerBlock;
long memory = device.totalGlobalMem;
size_t shared_mem = device.sharedMemPerBlock;
int major = device.major;
int minor = device.minor;
printf("Max Threads per Block: %d\n", maxthreadsperblock);
printf("Total Global Memory: %d\n", (int)memory);
printf("Shared Memory: %d\n", (int)shared_mem);
printf("Major Compute Capability: %d\n", major);
printf("Minor Compute Capability: %d\n", minor);
do {
printf("Enter size of array: ");
scanf("%d", &N);
long memory_required = 3*(long)N + 1;
if (memory_required > memory)
{
printf("Too big to fit on Device!\n");
continue;
}
printf("Enter number of threads per block: ");
scanf("%d",&T);
if (T > maxthreadsperblock)
{
printf("Max threads per block exceeded\n");
continue;
}
printf("\nEnter number of blocks per grid: ");
scanf("%d",&B);
if (T * B < N) printf("Error T x B < N, try again\n");
} while (T * B < N);
int a[N],b[N], d[N];
hipEvent_t start, stop; // using cuda events to measure time
float elapsed_time_ms; // which is applicable for asynchronous code also
//allocate memory on device and check for errors
if (hipMalloc((void**)&dev_a,N * sizeof(int)) != hipSuccess) {
puts("Not enough Space on Device!");
return 0;
}
if (hipMalloc((void**)&dev_b,N * sizeof(int)) != hipSuccess) {
puts("Not enough Space on Device!");
goto cleanup_a;
}
if (hipMalloc((void**)&dev_c,sizeof(int)) != hipSuccess) {
puts("Not enough Space on Device!");
goto cleanup_b;
}
if (hipMalloc((void**)&dev_d, N * sizeof(int)) != hipSuccess) {
puts("Not enough Space on Device!");
goto cleanup_c;
}
for(int i=0;i<N;i++) { // load arrays with some numbers
a[i] = i;
b[i] = i*1;
}
*c = 0;
hipMemcpy(dev_a, a , N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_b, b , N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_c, c , sizeof(int),hipMemcpyHostToDevice);
hipEventCreate( &start ); // instrument code to measure start time
hipEventCreate( &stop );
// Do Inner product on the Device
hipEventRecord( start, 0 );
multiply_kernel<<<B,T>>>(dev_a,dev_b,dev_c, N);
hipMemcpy(c,dev_c,sizeof(int),hipMemcpyDeviceToHost);
hipEventRecord( stop, 0 ); // instrument code to measue end time
hipEventSynchronize( stop );
hipEventElapsedTime( &elapsed_time_ms, start, stop );
printf("Device Inner Product: %d ", *c);
printf("Time: %f ms.\n", elapsed_time_ms); // print out execution time
*c = 0;
//Do Inner product on the CPU
hipEventRecord( start, 0 );
multiply_cpu(a,b,c, N);
hipEventRecord( stop, 0 ); // instrument code to measue end time
hipEventSynchronize( stop );
hipEventElapsedTime( &elapsed_time_ms, start, stop );
printf("CPU Inner Product: %d ", *c);
printf("Time: %f ms.\n", elapsed_time_ms); // print out execution time
*c = 0;
//Do Multiplication on the Device, and addition on the CPU
hipEventRecord( start, 0 );
multiply_kernel_add_cpu<<<B,T>>>(dev_a,dev_b,dev_d, N);
hipMemcpy(d, dev_d, sizeof(int)*N, hipMemcpyDeviceToHost);
for (int i = 0; i < N; ++i)
{
*c += d[i];
}
hipEventRecord( stop, 0 ); // instrument code to measue end time
hipEventSynchronize( stop );
hipEventElapsedTime( &elapsed_time_ms, start, stop );
printf("Multiplication on Device. Addition on CPU. Inner product: %d ", *c);
printf("Time: %f ms.\n", elapsed_time_ms); // print out execution time
*c = 0;
//Do Multiplication on the CPU and addition on the Device
hipEventRecord( start, 0 );
for (int i = 0; i < N; ++i)
{
d[i] = a[i] * b[i];
}
hipMemcpy(dev_d, d, sizeof(int)*N, hipMemcpyHostToDevice);
hipMemcpy(dev_c, c, sizeof(int), hipMemcpyHostToDevice);
multiply_cpu_add_kernel<<<B,T>>>(dev_d, dev_c, N);
hipMemcpy(c, dev_c, sizeof(int), hipMemcpyDeviceToHost);
hipEventRecord( stop, 0 ); // instrument code to measue end time
hipEventSynchronize( stop );
hipEventElapsedTime( &elapsed_time_ms, start, stop );
printf("Multiplication on CPU. Addition on Device. Inner Product: %d ", *c);
printf("Time: %f ms.\n", elapsed_time_ms); // print out execution time
// clean up
hipEventDestroy(start);
hipEventDestroy(stop);
hipFree(dev_d);
cleanup_c:
hipFree(dev_c);
cleanup_b:
hipFree(dev_b);
cleanup_a:
hipFree(dev_a);
return 0;
}
|
.text
.file "innerproduct.hip"
.globl _Z12multiply_cpuPiS_S_i # -- Begin function _Z12multiply_cpuPiS_S_i
.p2align 4, 0x90
.type _Z12multiply_cpuPiS_S_i,@function
_Z12multiply_cpuPiS_S_i: # @_Z12multiply_cpuPiS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
movl %ecx, %eax
movq %rsp, %r8
leaq 15(,%rax,4), %r9
andq $-16, %r9
subq %r9, %r8
movq %r8, %rsp
testl %ecx, %ecx
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rsi,%r9,4), %r10d
imull (%rdi,%r9,4), %r10d
movl %r10d, (%r8,%r9,4)
incq %r9
cmpq %r9, %rax
jne .LBB0_2
.LBB0_3: # %.preheader
testl %ecx, %ecx
jle .LBB0_7
# %bb.4: # %.lr.ph18
movl (%rdx), %ecx
xorl %esi, %esi
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
addl (%r8,%rsi,4), %ecx
incq %rsi
cmpq %rsi, %rax
jne .LBB0_5
# %bb.6: # %._crit_edge
movl %ecx, (%rdx)
.LBB0_7:
movq %rbp, %rsp
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end0:
.size _Z12multiply_cpuPiS_S_i, .Lfunc_end0-_Z12multiply_cpuPiS_S_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__multiply_kernelPiS_S_i # -- Begin function _Z30__device_stub__multiply_kernelPiS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__multiply_kernelPiS_S_i,@function
_Z30__device_stub__multiply_kernelPiS_S_i: # @_Z30__device_stub__multiply_kernelPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15multiply_kernelPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z30__device_stub__multiply_kernelPiS_S_i, .Lfunc_end1-_Z30__device_stub__multiply_kernelPiS_S_i
.cfi_endproc
# -- End function
.globl _Z38__device_stub__multiply_kernel_add_cpuPiS_S_i # -- Begin function _Z38__device_stub__multiply_kernel_add_cpuPiS_S_i
.p2align 4, 0x90
.type _Z38__device_stub__multiply_kernel_add_cpuPiS_S_i,@function
_Z38__device_stub__multiply_kernel_add_cpuPiS_S_i: # @_Z38__device_stub__multiply_kernel_add_cpuPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23multiply_kernel_add_cpuPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z38__device_stub__multiply_kernel_add_cpuPiS_S_i, .Lfunc_end2-_Z38__device_stub__multiply_kernel_add_cpuPiS_S_i
.cfi_endproc
# -- End function
.globl _Z38__device_stub__multiply_cpu_add_kernelPiS_i # -- Begin function _Z38__device_stub__multiply_cpu_add_kernelPiS_i
.p2align 4, 0x90
.type _Z38__device_stub__multiply_cpu_add_kernelPiS_i,@function
_Z38__device_stub__multiply_cpu_add_kernelPiS_i: # @_Z38__device_stub__multiply_cpu_add_kernelPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23multiply_cpu_add_kernelPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z38__device_stub__multiply_cpu_add_kernelPiS_i, .Lfunc_end3-_Z38__device_stub__multiply_cpu_add_kernelPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $1544, %rsp # imm = 0x608
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movl $4096, -44(%rbp) # imm = 0x1000
movl $10, -52(%rbp)
movl $1, -72(%rbp)
leaq -1584(%rbp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl -1264(%rbp), %ebx
movq -1296(%rbp), %r14
movl -1288(%rbp), %r12d
movl -1224(%rbp), %r13d
movl -1220(%rbp), %r15d
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl %r13d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.4, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
leaq -44(%rbp), %r15
leaq -52(%rbp), %r12
leaq -72(%rbp), %r13
jmp .LBB4_1
.p2align 4, 0x90
.LBB4_4: # %.sink.split
# in Loop: Header=BB4_1 Depth=1
callq puts
.LBB4_5: # in Loop: Header=BB4_1 Depth=1
movl -72(%rbp), %ecx
imull -52(%rbp), %ecx
movl -44(%rbp), %eax
cmpl %eax, %ecx
jge .LBB4_6
.LBB4_1: # =>This Inner Loop Header: Depth=1
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl $.L.str.6, %edi
movq %r15, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movslq -44(%rbp), %rax
leaq (%rax,%rax,2), %rax
movl $.Lstr.2, %edi
cmpq %r14, %rax
jge .LBB4_4
# %bb.2: # in Loop: Header=BB4_1 Depth=1
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl $.L.str.6, %edi
movq %r12, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movl $.Lstr.1, %edi
cmpl %ebx, -52(%rbp)
jg .LBB4_4
# %bb.3: # in Loop: Header=BB4_1 Depth=1
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl $.L.str.6, %edi
movq %r13, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movl -72(%rbp), %eax
imull -52(%rbp), %eax
movl $.Lstr, %edi
cmpl -44(%rbp), %eax
jl .LBB4_4
jmp .LBB4_5
.LBB4_6:
movq %rsp, %r12
movq %rsp, %rbx
leaq 15(,%rax,4), %rax
andq $-16, %rax
subq %rax, %rbx
movq %rbx, %rsp
movslq -44(%rbp), %rsi
movl %esi, %eax
movq %rsp, %r15
leaq 15(,%rax,4), %rax
andq $-16, %rax
subq %rax, %r15
movq %r15, %rsp
movq %rsp, %r14
subq %rax, %r14
movq %r14, %rsp
shlq $2, %rsi
leaq -112(%rbp), %rdi
callq hipMalloc
testl %eax, %eax
je .LBB4_8
# %bb.7:
movl $.L.str.12, %edi
callq puts
jmp .LBB4_33
.LBB4_8:
movslq -44(%rbp), %rsi
shlq $2, %rsi
leaq -104(%rbp), %rdi
callq hipMalloc
testl %eax, %eax
je .LBB4_10
# %bb.9:
movl $.L.str.12, %edi
callq puts
jmp .LBB4_32
.LBB4_10:
leaq -88(%rbp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
je .LBB4_12
# %bb.11:
movl $.L.str.12, %edi
callq puts
jmp .LBB4_31
.LBB4_12:
movslq -44(%rbp), %rsi
shlq $2, %rsi
leaq -96(%rbp), %rdi
callq hipMalloc
testl %eax, %eax
je .LBB4_13
# %bb.34:
movl $.L.str.12, %edi
callq puts
jmp .LBB4_30
.LBB4_13: # %.preheader
movl -44(%rbp), %eax
testl %eax, %eax
jle .LBB4_16
# %bb.14: # %.lr.ph.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_15: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, (%rbx,%rcx,4)
movl %ecx, (%r15,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB4_15
.LBB4_16: # %._crit_edge
movabsq $4294967296, %r13 # imm = 0x100000000
movl $0, -48(%rbp)
movq -112(%rbp), %rdi
movslq %eax, %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq -104(%rbp), %rdi
movslq -44(%rbp), %rdx
shlq $2, %rdx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq -88(%rbp), %rdi
leaq -48(%rbp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
leaq -80(%rbp), %rdi
callq hipEventCreate
leaq -64(%rbp), %rdi
callq hipEventCreate
movq -80(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl -72(%rbp), %edi
movl -52(%rbp), %edx
orq %r13, %rdi
orq %r13, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_18
# %bb.17:
movq -112(%rbp), %rdi
movq -104(%rbp), %rsi
movq -88(%rbp), %rdx
movl -44(%rbp), %ecx
callq _Z30__device_stub__multiply_kernelPiS_S_i
.LBB4_18:
movq -88(%rbp), %rsi
leaq -48(%rbp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq -64(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -64(%rbp), %rdi
callq hipEventSynchronize
movq -80(%rbp), %rsi
movq -64(%rbp), %rdx
leaq -68(%rbp), %r13
movq %r13, %rdi
callq hipEventElapsedTime
movl -48(%rbp), %esi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movss -68(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.14, %edi
movb $1, %al
callq printf
movl $0, -48(%rbp)
movq -80(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl -44(%rbp), %ecx
movq %rbx, %rdi
movq %r15, %rsi
leaq -48(%rbp), %rdx
callq _Z12multiply_cpuPiS_S_i
movq -64(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -64(%rbp), %rdi
callq hipEventSynchronize
movq -80(%rbp), %rsi
movq -64(%rbp), %rdx
movq %r13, %rdi
callq hipEventElapsedTime
movl -48(%rbp), %esi
movl $.L.str.15, %edi
xorl %eax, %eax
callq printf
movss -68(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.14, %edi
movb $1, %al
callq printf
movl $0, -48(%rbp)
movq -80(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl -72(%rbp), %edi
movl -52(%rbp), %edx
movabsq $4294967296, %r13 # imm = 0x100000000
orq %r13, %rdi
orq %r13, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_20
# %bb.19:
movq -112(%rbp), %rdi
movq -104(%rbp), %rsi
movq -96(%rbp), %rdx
movl -44(%rbp), %ecx
callq _Z38__device_stub__multiply_kernel_add_cpuPiS_S_i
.LBB4_20:
movq -96(%rbp), %rsi
movslq -44(%rbp), %rdx
shlq $2, %rdx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl -44(%rbp), %eax
testl %eax, %eax
jle .LBB4_24
# %bb.21: # %.lr.ph66.preheader
movl -48(%rbp), %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_22: # %.lr.ph66
# =>This Inner Loop Header: Depth=1
addl (%r14,%rdx,4), %ecx
incq %rdx
cmpq %rdx, %rax
jne .LBB4_22
# %bb.23: # %._crit_edge67
movl %ecx, -48(%rbp)
.LBB4_24:
movq -64(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -64(%rbp), %rdi
callq hipEventSynchronize
movq -80(%rbp), %rsi
movq -64(%rbp), %rdx
leaq -68(%rbp), %rdi
callq hipEventElapsedTime
movl -48(%rbp), %esi
movl $.L.str.16, %edi
xorl %eax, %eax
callq printf
movss -68(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.14, %edi
movb $1, %al
callq printf
movl $0, -48(%rbp)
movq -80(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl -44(%rbp), %eax
testl %eax, %eax
jle .LBB4_27
# %bb.25: # %.lr.ph71.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_26: # %.lr.ph71
# =>This Inner Loop Header: Depth=1
movl (%r15,%rcx,4), %edx
imull (%rbx,%rcx,4), %edx
movl %edx, (%r14,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB4_26
.LBB4_27: # %._crit_edge72
movq -96(%rbp), %rdi
movslq %eax, %rdx
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq -88(%rbp), %rdi
leaq -48(%rbp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movl -72(%rbp), %edi
movl -52(%rbp), %edx
orq %r13, %rdi
orq %r13, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_29
# %bb.28:
movq -96(%rbp), %rdi
movq -88(%rbp), %rsi
movl -44(%rbp), %edx
callq _Z38__device_stub__multiply_cpu_add_kernelPiS_i
.LBB4_29:
movq -88(%rbp), %rsi
leaq -48(%rbp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq -64(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -64(%rbp), %rdi
callq hipEventSynchronize
movq -80(%rbp), %rsi
movq -64(%rbp), %rdx
leaq -68(%rbp), %rdi
callq hipEventElapsedTime
movl -48(%rbp), %esi
movl $.L.str.17, %edi
xorl %eax, %eax
callq printf
movss -68(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.14, %edi
movb $1, %al
callq printf
movq -80(%rbp), %rdi
callq hipEventDestroy
movq -64(%rbp), %rdi
callq hipEventDestroy
movq -96(%rbp), %rdi
callq hipFree
.LBB4_30:
movq -88(%rbp), %rdi
callq hipFree
.LBB4_31:
movq -104(%rbp), %rdi
callq hipFree
.LBB4_32:
movq -112(%rbp), %rdi
callq hipFree
.LBB4_33:
movq %r12, %rsp
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15multiply_kernelPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23multiply_kernel_add_cpuPiS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23multiply_cpu_add_kernelPiS_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15multiply_kernelPiS_S_i,@object # @_Z15multiply_kernelPiS_S_i
.section .rodata,"a",@progbits
.globl _Z15multiply_kernelPiS_S_i
.p2align 3, 0x0
_Z15multiply_kernelPiS_S_i:
.quad _Z30__device_stub__multiply_kernelPiS_S_i
.size _Z15multiply_kernelPiS_S_i, 8
.type _Z23multiply_kernel_add_cpuPiS_S_i,@object # @_Z23multiply_kernel_add_cpuPiS_S_i
.globl _Z23multiply_kernel_add_cpuPiS_S_i
.p2align 3, 0x0
_Z23multiply_kernel_add_cpuPiS_S_i:
.quad _Z38__device_stub__multiply_kernel_add_cpuPiS_S_i
.size _Z23multiply_kernel_add_cpuPiS_S_i, 8
.type _Z23multiply_cpu_add_kernelPiS_i,@object # @_Z23multiply_cpu_add_kernelPiS_i
.globl _Z23multiply_cpu_add_kernelPiS_i
.p2align 3, 0x0
_Z23multiply_cpu_add_kernelPiS_i:
.quad _Z38__device_stub__multiply_cpu_add_kernelPiS_i
.size _Z23multiply_cpu_add_kernelPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Max Threads per Block: %d\n"
.size .L.str, 27
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Total Global Memory: %d\n"
.size .L.str.1, 25
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Shared Memory: %d\n"
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Major Compute Capability: %d\n"
.size .L.str.3, 30
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Minor Compute Capability: %d\n"
.size .L.str.4, 30
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Enter size of array: "
.size .L.str.5, 22
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d"
.size .L.str.6, 3
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Enter number of threads per block: "
.size .L.str.8, 36
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\nEnter number of blocks per grid: "
.size .L.str.10, 35
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Not enough Space on Device!"
.size .L.str.12, 28
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Device Inner Product: %d "
.size .L.str.13, 26
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Time: %f ms.\n"
.size .L.str.14, 14
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "CPU Inner Product: %d "
.size .L.str.15, 23
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Multiplication on Device. Addition on CPU. Inner product: %d "
.size .L.str.16, 62
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Multiplication on CPU. Addition on Device. Inner Product: %d "
.size .L.str.17, 62
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15multiply_kernelPiS_S_i"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z23multiply_kernel_add_cpuPiS_S_i"
.size .L__unnamed_2, 35
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z23multiply_cpu_add_kernelPiS_i"
.size .L__unnamed_3, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error T x B < N, try again"
.size .Lstr, 27
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Max threads per block exceeded"
.size .Lstr.1, 31
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Too big to fit on Device!"
.size .Lstr.2, 26
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__multiply_kernelPiS_S_i
.addrsig_sym _Z38__device_stub__multiply_kernel_add_cpuPiS_S_i
.addrsig_sym _Z38__device_stub__multiply_cpu_add_kernelPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15multiply_kernelPiS_S_i
.addrsig_sym _Z23multiply_kernel_add_cpuPiS_S_i
.addrsig_sym _Z23multiply_cpu_add_kernelPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z23multiply_cpu_add_kernelPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*00b0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*00c0*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*00d0*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*00e0*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fc80000000f00 */
/*00f0*/ ISETP.EQ.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x001fe2000bf02070 */
/*0100*/ REDUX.SUM UR5, R2 ; /* 0x00000000020573c4 */
/* 0x004e24000000c000 */
/*0110*/ IMAD.U32 R7, RZ, RZ, UR5 ; /* 0x00000005ff077e24 */
/* 0x001fd4000f8e00ff */
/*0120*/ @P0 RED.E.ADD.STRONG.GPU [R4.64], R7 ; /* 0x000000070400098e */
/* 0x000fe2000c10e186 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z23multiply_kernel_add_cpuPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ IMAD R9, R4, R3, RZ ; /* 0x0000000304097224 */
/* 0x004fca00078e02ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15multiply_kernelPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R2, R3, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x000fc800078e0203 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe400078e0203 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*00d0*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fe20000000f00 */
/*00e0*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*00f0*/ S2R R6, SR_LANEID ; /* 0x0000000000067919 */
/* 0x000e2a0000000000 */
/*0100*/ ISETP.EQ.U32.AND P0, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x001fc4000bf02070 */
/*0110*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fe20000000f00 */
/*0120*/ IMAD R0, R4, R3, RZ ; /* 0x0000000304007224 */
/* 0x004fc800078e02ff */
/*0130*/ REDUX.SUM UR5, R0 ; /* 0x00000000000573c4 */
/* 0x000e24000000c000 */
/*0140*/ MOV R9, UR5 ; /* 0x0000000500097c02 */
/* 0x001fca0008000f00 */
/*0150*/ @P0 RED.E.ADD.STRONG.GPU [R6.64], R9 ; /* 0x000000090600098e */
/* 0x000fe2000c10e186 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15multiply_kernelPiS_S_i
.globl _Z15multiply_kernelPiS_S_i
.p2align 8
.type _Z15multiply_kernelPiS_S_i,@function
_Z15multiply_kernelPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s2, exec_lo
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v0, v0, v2
.LBB0_2:
s_ctz_i32_b32 s4, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s5, v0, s4
s_lshl_b32 s4, 1, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s2, s2, s4
s_add_i32 s3, s3, s5
s_cmp_lg_u32 s2, 0
s_cbranch_scc1 .LBB0_2
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x10
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s3
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15multiply_kernelPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15multiply_kernelPiS_S_i, .Lfunc_end0-_Z15multiply_kernelPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z23multiply_kernel_add_cpuPiS_S_i
.globl _Z23multiply_kernel_add_cpuPiS_S_i
.p2align 8
.type _Z23multiply_kernel_add_cpuPiS_S_i,@function
_Z23multiply_kernel_add_cpuPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23multiply_kernel_add_cpuPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z23multiply_kernel_add_cpuPiS_S_i, .Lfunc_end1-_Z23multiply_kernel_add_cpuPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z23multiply_cpu_add_kernelPiS_i
.globl _Z23multiply_cpu_add_kernelPiS_i
.p2align 8
.type _Z23multiply_cpu_add_kernelPiS_i,@function
_Z23multiply_cpu_add_kernelPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB2_5
s_load_b64 s[4:5], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s3, exec_lo
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v0, v[0:1], off
.LBB2_2:
s_ctz_i32_b32 s4, s3
s_waitcnt vmcnt(0)
v_readlane_b32 s5, v0, s4
s_lshl_b32 s4, 1, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s3, s3, s4
s_add_i32 s2, s2, s5
s_cmp_lg_u32 s3, 0
s_cbranch_scc1 .LBB2_2
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB2_5
s_load_b64 s[0:1], s[0:1], 0x8
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB2_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23multiply_cpu_add_kernelPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z23multiply_cpu_add_kernelPiS_i, .Lfunc_end2-_Z23multiply_cpu_add_kernelPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15multiply_kernelPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15multiply_kernelPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23multiply_kernel_add_cpuPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23multiply_kernel_add_cpuPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23multiply_cpu_add_kernelPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23multiply_cpu_add_kernelPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001648e1_00000000-6_innerproduct.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12multiply_cpuPiS_S_i
.type _Z12multiply_cpuPiS_S_i, @function
_Z12multiply_cpuPiS_S_i:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
subq $16, %rsp
movq %rdi, %r8
movq %rsi, %r9
movq %rdx, %r10
movq %fs:40, %rax
movq %rax, -8(%rbp)
xorl %eax, %eax
movslq %ecx, %rdi
salq $2, %rdi
leaq 15(%rdi), %rax
movq %rax, %rsi
andq $-16, %rsi
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L4:
cmpq %rdx, %rsp
je .L5
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L4
.L5:
movq %rsi, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L6
orq $0, -8(%rsp,%rax)
.L6:
movq %rsp, %rsi
testl %ecx, %ecx
jle .L3
movl $0, %eax
.L8:
movl (%r8,%rax), %edx
imull (%r9,%rax), %edx
movl %edx, (%rsi,%rax)
addq $4, %rax
cmpq %rax, %rdi
jne .L8
movl (%r10), %ecx
movq %rsi, %rax
addq %rdi, %rsi
.L9:
addl (%rax), %ecx
addq $4, %rax
cmpq %rsi, %rax
jne .L9
movl %ecx, (%r10)
.L3:
movq -8(%rbp), %rax
subq %fs:40, %rax
jne .L14
leave
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L14:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z12multiply_cpuPiS_S_i, .-_Z12multiply_cpuPiS_S_i
.globl _Z40__device_stub__Z15multiply_kernelPiS_S_iPiS_S_i
.type _Z40__device_stub__Z15multiply_kernelPiS_S_iPiS_S_i, @function
_Z40__device_stub__Z15multiply_kernelPiS_S_iPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15multiply_kernelPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z40__device_stub__Z15multiply_kernelPiS_S_iPiS_S_i, .-_Z40__device_stub__Z15multiply_kernelPiS_S_iPiS_S_i
.globl _Z15multiply_kernelPiS_S_i
.type _Z15multiply_kernelPiS_S_i, @function
_Z15multiply_kernelPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15multiply_kernelPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z15multiply_kernelPiS_S_i, .-_Z15multiply_kernelPiS_S_i
.globl _Z48__device_stub__Z23multiply_kernel_add_cpuPiS_S_iPiS_S_i
.type _Z48__device_stub__Z23multiply_kernel_add_cpuPiS_S_iPiS_S_i, @function
_Z48__device_stub__Z23multiply_kernel_add_cpuPiS_S_iPiS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23multiply_kernel_add_cpuPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z48__device_stub__Z23multiply_kernel_add_cpuPiS_S_iPiS_S_i, .-_Z48__device_stub__Z23multiply_kernel_add_cpuPiS_S_iPiS_S_i
.globl _Z23multiply_kernel_add_cpuPiS_S_i
.type _Z23multiply_kernel_add_cpuPiS_S_i, @function
_Z23multiply_kernel_add_cpuPiS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z23multiply_kernel_add_cpuPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z23multiply_kernel_add_cpuPiS_S_i, .-_Z23multiply_kernel_add_cpuPiS_S_i
.globl _Z46__device_stub__Z23multiply_cpu_add_kernelPiS_iPiS_i
.type _Z46__device_stub__Z23multiply_cpu_add_kernelPiS_iPiS_i, @function
_Z46__device_stub__Z23multiply_cpu_add_kernelPiS_iPiS_i:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23multiply_cpu_add_kernelPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z46__device_stub__Z23multiply_cpu_add_kernelPiS_iPiS_i, .-_Z46__device_stub__Z23multiply_cpu_add_kernelPiS_iPiS_i
.globl _Z23multiply_cpu_add_kernelPiS_i
.type _Z23multiply_cpu_add_kernelPiS_i, @function
_Z23multiply_cpu_add_kernelPiS_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z23multiply_cpu_add_kernelPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z23multiply_cpu_add_kernelPiS_i, .-_Z23multiply_cpu_add_kernelPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Max Threads per Block: %d\n"
.LC1:
.string "Total Global Memory: %d\n"
.LC2:
.string "Shared Memory: %d\n"
.LC3:
.string "Major Compute Capability: %d\n"
.LC4:
.string "Minor Compute Capability: %d\n"
.LC5:
.string "Enter size of array: "
.LC6:
.string "%d"
.LC7:
.string "Too big to fit on Device!\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "Enter number of threads per block: "
.align 8
.LC9:
.string "Max threads per block exceeded\n"
.align 8
.LC10:
.string "\nEnter number of blocks per grid: "
.section .rodata.str1.1
.LC11:
.string "Error T x B < N, try again\n"
.LC12:
.string "Not enough Space on Device!"
.LC13:
.string "Device Inner Product: %d "
.LC14:
.string "Time: %f ms.\n"
.LC15:
.string "CPU Inner Product: %d "
.section .rodata.str1.8
.align 8
.LC16:
.string "Multiplication on Device. Addition on CPU. Inner product: %d "
.align 8
.LC17:
.string "Multiplication on CPU. Addition on Device. Inner Product: %d "
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $1144, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movl $4096, -1184(%rbp)
movl $10, -1180(%rbp)
movl $1, -1176(%rbp)
leaq -1088(%rbp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl -768(%rbp), %r14d
movq -800(%rbp), %r12
movq -792(%rbp), %rbx
movl -728(%rbp), %r15d
movl -724(%rbp), %r13d
movl %r14d, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %r13
leaq .LC6(%rip), %rbx
leaq .LC8(%rip), %r15
jmp .L44
.L78:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L41:
movl -1184(%rbp), %edx
movl -1180(%rbp), %eax
imull -1176(%rbp), %eax
cmpl %edx, %eax
jge .L43
.L44:
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq -1184(%rbp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movslq -1184(%rbp), %rax
leaq (%rax,%rax,2), %rax
cmpq %r12, %rax
jge .L78
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq -1180(%rbp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
cmpl %r14d, -1180(%rbp)
jg .L79
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq -1176(%rbp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl -1184(%rbp), %edx
movl -1180(%rbp), %eax
imull -1176(%rbp), %eax
cmpl %edx, %eax
jl .L80
.L43:
movslq %edx, %rdx
leaq 0(,%rdx,4), %rsi
leaq 15(%rsi), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L45:
cmpq %rdx, %rsp
je .L46
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L45
.L79:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L41
.L80:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L41
.L46:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L47
orq $0, -8(%rsp,%rax)
.L47:
movq %rsp, %rbx
leaq 15(%rsi), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L48:
cmpq %rdx, %rsp
je .L49
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L48
.L49:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L50
orq $0, -8(%rsp,%rax)
.L50:
movq %rsp, %r12
leaq 15(%rsi), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L51:
cmpq %rdx, %rsp
je .L52
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L51
.L52:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L53
orq $0, -8(%rsp,%rax)
.L53:
movq %rsp, %r13
leaq -1168(%rbp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L81
movslq -1184(%rbp), %rsi
salq $2, %rsi
leaq -1160(%rbp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L82
leaq -1152(%rbp), %rdi
movl $4, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L83
movslq -1184(%rbp), %rsi
salq $2, %rsi
leaq -1144(%rbp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L60
movl -1184(%rbp), %ecx
testl %ecx, %ecx
jle .L62
movslq %ecx, %rdx
movl $0, %eax
.L64:
movl %eax, (%rbx,%rax,4)
movl %eax, (%r12,%rax,4)
addq $1, %rax
cmpq %rdx, %rax
jne .L64
.L62:
movl $0, -1092(%rbp)
movslq %ecx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq -1168(%rbp), %rdi
call cudaMemcpy@PLT
movslq -1184(%rbp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r12, %rsi
movq -1160(%rbp), %rdi
call cudaMemcpy@PLT
leaq -1092(%rbp), %rsi
movl $1, %ecx
movl $4, %edx
movq -1152(%rbp), %rdi
call cudaMemcpy@PLT
leaq -1136(%rbp), %rdi
call cudaEventCreate@PLT
leaq -1128(%rbp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq -1136(%rbp), %rdi
call cudaEventRecord@PLT
movl -1180(%rbp), %eax
movl %eax, -1104(%rbp)
movl $1, -1100(%rbp)
movl $1, -1096(%rbp)
movl -1176(%rbp), %eax
movl %eax, -1116(%rbp)
movl $1, -1112(%rbp)
movl $1, -1108(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -1104(%rbp), %rdx
movl $1, %ecx
movq -1116(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L84
.L65:
leaq -1092(%rbp), %r15
movl $2, %ecx
movl $4, %edx
movq -1152(%rbp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq -1128(%rbp), %rdi
call cudaEventRecord@PLT
movq -1128(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -1172(%rbp), %r14
movq -1128(%rbp), %rdx
movq -1136(%rbp), %rsi
movq %r14, %rdi
call cudaEventElapsedTime@PLT
movl -1092(%rbp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd -1172(%rbp), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, -1092(%rbp)
movl $0, %esi
movq -1136(%rbp), %rdi
call cudaEventRecord@PLT
movl -1184(%rbp), %ecx
movq %r15, %rdx
movq %r12, %rsi
movq %rbx, %rdi
call _Z12multiply_cpuPiS_S_i
movl $0, %esi
movq -1128(%rbp), %rdi
call cudaEventRecord@PLT
movq -1128(%rbp), %rdi
call cudaEventSynchronize@PLT
movq -1128(%rbp), %rdx
movq -1136(%rbp), %rsi
movq %r14, %rdi
call cudaEventElapsedTime@PLT
movl -1092(%rbp), %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd -1172(%rbp), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, -1092(%rbp)
movl $0, %esi
movq -1136(%rbp), %rdi
call cudaEventRecord@PLT
movl -1180(%rbp), %eax
movl %eax, -1104(%rbp)
movl $1, -1100(%rbp)
movl $1, -1096(%rbp)
movl -1176(%rbp), %eax
movl %eax, -1116(%rbp)
movl $1, -1112(%rbp)
movl $1, -1108(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -1104(%rbp), %rdx
movl $1, %ecx
movq -1116(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L85
.L66:
movslq -1184(%rbp), %rdx
salq $2, %rdx
movl $2, %ecx
movq -1144(%rbp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl -1184(%rbp), %edx
testl %edx, %edx
jle .L67
movl -1092(%rbp), %ecx
movq %r13, %rax
movslq %edx, %rdx
leaq 0(%r13,%rdx,4), %rsi
.L68:
addl (%rax), %ecx
addq $4, %rax
cmpq %rsi, %rax
jne .L68
movl %ecx, -1092(%rbp)
.L67:
movl $0, %esi
movq -1128(%rbp), %rdi
call cudaEventRecord@PLT
movq -1128(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -1172(%rbp), %rdi
movq -1128(%rbp), %rdx
movq -1136(%rbp), %rsi
call cudaEventElapsedTime@PLT
movl -1092(%rbp), %edx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd -1172(%rbp), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, -1092(%rbp)
movl $0, %esi
movq -1136(%rbp), %rdi
call cudaEventRecord@PLT
movl -1184(%rbp), %esi
testl %esi, %esi
jle .L69
movslq %esi, %rcx
salq $2, %rcx
movl $0, %eax
.L70:
movl (%rbx,%rax), %edx
imull (%r12,%rax), %edx
movl %edx, 0(%r13,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L70
.L69:
movslq %esi, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r13, %rsi
movq -1144(%rbp), %rdi
call cudaMemcpy@PLT
leaq -1092(%rbp), %rsi
movl $1, %ecx
movl $4, %edx
movq -1152(%rbp), %rdi
call cudaMemcpy@PLT
movl -1180(%rbp), %eax
movl %eax, -1104(%rbp)
movl $1, -1100(%rbp)
movl $1, -1096(%rbp)
movl -1176(%rbp), %eax
movl %eax, -1116(%rbp)
movl $1, -1112(%rbp)
movl $1, -1108(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -1104(%rbp), %rdx
movl $1, %ecx
movq -1116(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L86
.L71:
leaq -1092(%rbp), %rdi
movl $2, %ecx
movl $4, %edx
movq -1152(%rbp), %rsi
call cudaMemcpy@PLT
movl $0, %esi
movq -1128(%rbp), %rdi
call cudaEventRecord@PLT
movq -1128(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -1172(%rbp), %rdi
movq -1128(%rbp), %rdx
movq -1136(%rbp), %rsi
call cudaEventElapsedTime@PLT
movl -1092(%rbp), %edx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd -1172(%rbp), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq -1136(%rbp), %rdi
call cudaEventDestroy@PLT
movq -1128(%rbp), %rdi
call cudaEventDestroy@PLT
movq -1144(%rbp), %rdi
call cudaFree@PLT
.L63:
movq -1152(%rbp), %rdi
call cudaFree@PLT
.L59:
movq -1160(%rbp), %rdi
call cudaFree@PLT
.L57:
movq -1168(%rbp), %rdi
call cudaFree@PLT
.L55:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L87
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L81:
.cfi_restore_state
leaq .LC12(%rip), %rdi
call puts@PLT
jmp .L55
.L82:
leaq .LC12(%rip), %rdi
call puts@PLT
jmp .L57
.L83:
leaq .LC12(%rip), %rdi
call puts@PLT
jmp .L59
.L60:
leaq .LC12(%rip), %rdi
call puts@PLT
jmp .L63
.L84:
movl -1184(%rbp), %ecx
movq -1152(%rbp), %rdx
movq -1160(%rbp), %rsi
movq -1168(%rbp), %rdi
call _Z40__device_stub__Z15multiply_kernelPiS_S_iPiS_S_i
jmp .L65
.L85:
movl -1184(%rbp), %ecx
movq -1144(%rbp), %rdx
movq -1160(%rbp), %rsi
movq -1168(%rbp), %rdi
call _Z48__device_stub__Z23multiply_kernel_add_cpuPiS_S_iPiS_S_i
jmp .L66
.L86:
movl -1184(%rbp), %edx
movq -1152(%rbp), %rsi
movq -1144(%rbp), %rdi
call _Z46__device_stub__Z23multiply_cpu_add_kernelPiS_iPiS_i
jmp .L71
.L87:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC18:
.string "_Z23multiply_cpu_add_kernelPiS_i"
.align 8
.LC19:
.string "_Z23multiply_kernel_add_cpuPiS_S_i"
.section .rodata.str1.1
.LC20:
.string "_Z15multiply_kernelPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z23multiply_cpu_add_kernelPiS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z23multiply_kernel_add_cpuPiS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z15multiply_kernelPiS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "innerproduct.hip"
.globl _Z12multiply_cpuPiS_S_i # -- Begin function _Z12multiply_cpuPiS_S_i
.p2align 4, 0x90
.type _Z12multiply_cpuPiS_S_i,@function
_Z12multiply_cpuPiS_S_i: # @_Z12multiply_cpuPiS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
movl %ecx, %eax
movq %rsp, %r8
leaq 15(,%rax,4), %r9
andq $-16, %r9
subq %r9, %r8
movq %r8, %rsp
testl %ecx, %ecx
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rsi,%r9,4), %r10d
imull (%rdi,%r9,4), %r10d
movl %r10d, (%r8,%r9,4)
incq %r9
cmpq %r9, %rax
jne .LBB0_2
.LBB0_3: # %.preheader
testl %ecx, %ecx
jle .LBB0_7
# %bb.4: # %.lr.ph18
movl (%rdx), %ecx
xorl %esi, %esi
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
addl (%r8,%rsi,4), %ecx
incq %rsi
cmpq %rsi, %rax
jne .LBB0_5
# %bb.6: # %._crit_edge
movl %ecx, (%rdx)
.LBB0_7:
movq %rbp, %rsp
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end0:
.size _Z12multiply_cpuPiS_S_i, .Lfunc_end0-_Z12multiply_cpuPiS_S_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__multiply_kernelPiS_S_i # -- Begin function _Z30__device_stub__multiply_kernelPiS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__multiply_kernelPiS_S_i,@function
_Z30__device_stub__multiply_kernelPiS_S_i: # @_Z30__device_stub__multiply_kernelPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15multiply_kernelPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z30__device_stub__multiply_kernelPiS_S_i, .Lfunc_end1-_Z30__device_stub__multiply_kernelPiS_S_i
.cfi_endproc
# -- End function
.globl _Z38__device_stub__multiply_kernel_add_cpuPiS_S_i # -- Begin function _Z38__device_stub__multiply_kernel_add_cpuPiS_S_i
.p2align 4, 0x90
.type _Z38__device_stub__multiply_kernel_add_cpuPiS_S_i,@function
_Z38__device_stub__multiply_kernel_add_cpuPiS_S_i: # @_Z38__device_stub__multiply_kernel_add_cpuPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23multiply_kernel_add_cpuPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z38__device_stub__multiply_kernel_add_cpuPiS_S_i, .Lfunc_end2-_Z38__device_stub__multiply_kernel_add_cpuPiS_S_i
.cfi_endproc
# -- End function
.globl _Z38__device_stub__multiply_cpu_add_kernelPiS_i # -- Begin function _Z38__device_stub__multiply_cpu_add_kernelPiS_i
.p2align 4, 0x90
.type _Z38__device_stub__multiply_cpu_add_kernelPiS_i,@function
_Z38__device_stub__multiply_cpu_add_kernelPiS_i: # @_Z38__device_stub__multiply_cpu_add_kernelPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23multiply_cpu_add_kernelPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z38__device_stub__multiply_cpu_add_kernelPiS_i, .Lfunc_end3-_Z38__device_stub__multiply_cpu_add_kernelPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $1544, %rsp # imm = 0x608
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movl $4096, -44(%rbp) # imm = 0x1000
movl $10, -52(%rbp)
movl $1, -72(%rbp)
leaq -1584(%rbp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl -1264(%rbp), %ebx
movq -1296(%rbp), %r14
movl -1288(%rbp), %r12d
movl -1224(%rbp), %r13d
movl -1220(%rbp), %r15d
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl %r13d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.4, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
leaq -44(%rbp), %r15
leaq -52(%rbp), %r12
leaq -72(%rbp), %r13
jmp .LBB4_1
.p2align 4, 0x90
.LBB4_4: # %.sink.split
# in Loop: Header=BB4_1 Depth=1
callq puts
.LBB4_5: # in Loop: Header=BB4_1 Depth=1
movl -72(%rbp), %ecx
imull -52(%rbp), %ecx
movl -44(%rbp), %eax
cmpl %eax, %ecx
jge .LBB4_6
.LBB4_1: # =>This Inner Loop Header: Depth=1
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl $.L.str.6, %edi
movq %r15, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movslq -44(%rbp), %rax
leaq (%rax,%rax,2), %rax
movl $.Lstr.2, %edi
cmpq %r14, %rax
jge .LBB4_4
# %bb.2: # in Loop: Header=BB4_1 Depth=1
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl $.L.str.6, %edi
movq %r12, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movl $.Lstr.1, %edi
cmpl %ebx, -52(%rbp)
jg .LBB4_4
# %bb.3: # in Loop: Header=BB4_1 Depth=1
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl $.L.str.6, %edi
movq %r13, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movl -72(%rbp), %eax
imull -52(%rbp), %eax
movl $.Lstr, %edi
cmpl -44(%rbp), %eax
jl .LBB4_4
jmp .LBB4_5
.LBB4_6:
movq %rsp, %r12
movq %rsp, %rbx
leaq 15(,%rax,4), %rax
andq $-16, %rax
subq %rax, %rbx
movq %rbx, %rsp
movslq -44(%rbp), %rsi
movl %esi, %eax
movq %rsp, %r15
leaq 15(,%rax,4), %rax
andq $-16, %rax
subq %rax, %r15
movq %r15, %rsp
movq %rsp, %r14
subq %rax, %r14
movq %r14, %rsp
shlq $2, %rsi
leaq -112(%rbp), %rdi
callq hipMalloc
testl %eax, %eax
je .LBB4_8
# %bb.7:
movl $.L.str.12, %edi
callq puts
jmp .LBB4_33
.LBB4_8:
movslq -44(%rbp), %rsi
shlq $2, %rsi
leaq -104(%rbp), %rdi
callq hipMalloc
testl %eax, %eax
je .LBB4_10
# %bb.9:
movl $.L.str.12, %edi
callq puts
jmp .LBB4_32
.LBB4_10:
leaq -88(%rbp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
je .LBB4_12
# %bb.11:
movl $.L.str.12, %edi
callq puts
jmp .LBB4_31
.LBB4_12:
movslq -44(%rbp), %rsi
shlq $2, %rsi
leaq -96(%rbp), %rdi
callq hipMalloc
testl %eax, %eax
je .LBB4_13
# %bb.34:
movl $.L.str.12, %edi
callq puts
jmp .LBB4_30
.LBB4_13: # %.preheader
movl -44(%rbp), %eax
testl %eax, %eax
jle .LBB4_16
# %bb.14: # %.lr.ph.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_15: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, (%rbx,%rcx,4)
movl %ecx, (%r15,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB4_15
.LBB4_16: # %._crit_edge
movabsq $4294967296, %r13 # imm = 0x100000000
movl $0, -48(%rbp)
movq -112(%rbp), %rdi
movslq %eax, %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq -104(%rbp), %rdi
movslq -44(%rbp), %rdx
shlq $2, %rdx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq -88(%rbp), %rdi
leaq -48(%rbp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
leaq -80(%rbp), %rdi
callq hipEventCreate
leaq -64(%rbp), %rdi
callq hipEventCreate
movq -80(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl -72(%rbp), %edi
movl -52(%rbp), %edx
orq %r13, %rdi
orq %r13, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_18
# %bb.17:
movq -112(%rbp), %rdi
movq -104(%rbp), %rsi
movq -88(%rbp), %rdx
movl -44(%rbp), %ecx
callq _Z30__device_stub__multiply_kernelPiS_S_i
.LBB4_18:
movq -88(%rbp), %rsi
leaq -48(%rbp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq -64(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -64(%rbp), %rdi
callq hipEventSynchronize
movq -80(%rbp), %rsi
movq -64(%rbp), %rdx
leaq -68(%rbp), %r13
movq %r13, %rdi
callq hipEventElapsedTime
movl -48(%rbp), %esi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movss -68(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.14, %edi
movb $1, %al
callq printf
movl $0, -48(%rbp)
movq -80(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl -44(%rbp), %ecx
movq %rbx, %rdi
movq %r15, %rsi
leaq -48(%rbp), %rdx
callq _Z12multiply_cpuPiS_S_i
movq -64(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -64(%rbp), %rdi
callq hipEventSynchronize
movq -80(%rbp), %rsi
movq -64(%rbp), %rdx
movq %r13, %rdi
callq hipEventElapsedTime
movl -48(%rbp), %esi
movl $.L.str.15, %edi
xorl %eax, %eax
callq printf
movss -68(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.14, %edi
movb $1, %al
callq printf
movl $0, -48(%rbp)
movq -80(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl -72(%rbp), %edi
movl -52(%rbp), %edx
movabsq $4294967296, %r13 # imm = 0x100000000
orq %r13, %rdi
orq %r13, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_20
# %bb.19:
movq -112(%rbp), %rdi
movq -104(%rbp), %rsi
movq -96(%rbp), %rdx
movl -44(%rbp), %ecx
callq _Z38__device_stub__multiply_kernel_add_cpuPiS_S_i
.LBB4_20:
movq -96(%rbp), %rsi
movslq -44(%rbp), %rdx
shlq $2, %rdx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl -44(%rbp), %eax
testl %eax, %eax
jle .LBB4_24
# %bb.21: # %.lr.ph66.preheader
movl -48(%rbp), %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_22: # %.lr.ph66
# =>This Inner Loop Header: Depth=1
addl (%r14,%rdx,4), %ecx
incq %rdx
cmpq %rdx, %rax
jne .LBB4_22
# %bb.23: # %._crit_edge67
movl %ecx, -48(%rbp)
.LBB4_24:
movq -64(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -64(%rbp), %rdi
callq hipEventSynchronize
movq -80(%rbp), %rsi
movq -64(%rbp), %rdx
leaq -68(%rbp), %rdi
callq hipEventElapsedTime
movl -48(%rbp), %esi
movl $.L.str.16, %edi
xorl %eax, %eax
callq printf
movss -68(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.14, %edi
movb $1, %al
callq printf
movl $0, -48(%rbp)
movq -80(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl -44(%rbp), %eax
testl %eax, %eax
jle .LBB4_27
# %bb.25: # %.lr.ph71.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_26: # %.lr.ph71
# =>This Inner Loop Header: Depth=1
movl (%r15,%rcx,4), %edx
imull (%rbx,%rcx,4), %edx
movl %edx, (%r14,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB4_26
.LBB4_27: # %._crit_edge72
movq -96(%rbp), %rdi
movslq %eax, %rdx
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq -88(%rbp), %rdi
leaq -48(%rbp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movl -72(%rbp), %edi
movl -52(%rbp), %edx
orq %r13, %rdi
orq %r13, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_29
# %bb.28:
movq -96(%rbp), %rdi
movq -88(%rbp), %rsi
movl -44(%rbp), %edx
callq _Z38__device_stub__multiply_cpu_add_kernelPiS_i
.LBB4_29:
movq -88(%rbp), %rsi
leaq -48(%rbp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq -64(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -64(%rbp), %rdi
callq hipEventSynchronize
movq -80(%rbp), %rsi
movq -64(%rbp), %rdx
leaq -68(%rbp), %rdi
callq hipEventElapsedTime
movl -48(%rbp), %esi
movl $.L.str.17, %edi
xorl %eax, %eax
callq printf
movss -68(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.14, %edi
movb $1, %al
callq printf
movq -80(%rbp), %rdi
callq hipEventDestroy
movq -64(%rbp), %rdi
callq hipEventDestroy
movq -96(%rbp), %rdi
callq hipFree
.LBB4_30:
movq -88(%rbp), %rdi
callq hipFree
.LBB4_31:
movq -104(%rbp), %rdi
callq hipFree
.LBB4_32:
movq -112(%rbp), %rdi
callq hipFree
.LBB4_33:
movq %r12, %rsp
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15multiply_kernelPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23multiply_kernel_add_cpuPiS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23multiply_cpu_add_kernelPiS_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15multiply_kernelPiS_S_i,@object # @_Z15multiply_kernelPiS_S_i
.section .rodata,"a",@progbits
.globl _Z15multiply_kernelPiS_S_i
.p2align 3, 0x0
_Z15multiply_kernelPiS_S_i:
.quad _Z30__device_stub__multiply_kernelPiS_S_i
.size _Z15multiply_kernelPiS_S_i, 8
.type _Z23multiply_kernel_add_cpuPiS_S_i,@object # @_Z23multiply_kernel_add_cpuPiS_S_i
.globl _Z23multiply_kernel_add_cpuPiS_S_i
.p2align 3, 0x0
_Z23multiply_kernel_add_cpuPiS_S_i:
.quad _Z38__device_stub__multiply_kernel_add_cpuPiS_S_i
.size _Z23multiply_kernel_add_cpuPiS_S_i, 8
.type _Z23multiply_cpu_add_kernelPiS_i,@object # @_Z23multiply_cpu_add_kernelPiS_i
.globl _Z23multiply_cpu_add_kernelPiS_i
.p2align 3, 0x0
_Z23multiply_cpu_add_kernelPiS_i:
.quad _Z38__device_stub__multiply_cpu_add_kernelPiS_i
.size _Z23multiply_cpu_add_kernelPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Max Threads per Block: %d\n"
.size .L.str, 27
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Total Global Memory: %d\n"
.size .L.str.1, 25
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Shared Memory: %d\n"
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Major Compute Capability: %d\n"
.size .L.str.3, 30
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Minor Compute Capability: %d\n"
.size .L.str.4, 30
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Enter size of array: "
.size .L.str.5, 22
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d"
.size .L.str.6, 3
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Enter number of threads per block: "
.size .L.str.8, 36
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\nEnter number of blocks per grid: "
.size .L.str.10, 35
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Not enough Space on Device!"
.size .L.str.12, 28
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Device Inner Product: %d "
.size .L.str.13, 26
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Time: %f ms.\n"
.size .L.str.14, 14
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "CPU Inner Product: %d "
.size .L.str.15, 23
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Multiplication on Device. Addition on CPU. Inner product: %d "
.size .L.str.16, 62
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Multiplication on CPU. Addition on Device. Inner Product: %d "
.size .L.str.17, 62
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15multiply_kernelPiS_S_i"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z23multiply_kernel_add_cpuPiS_S_i"
.size .L__unnamed_2, 35
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z23multiply_cpu_add_kernelPiS_i"
.size .L__unnamed_3, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error T x B < N, try again"
.size .Lstr, 27
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Max threads per block exceeded"
.size .Lstr.1, 31
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Too big to fit on Device!"
.size .Lstr.2, 26
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__multiply_kernelPiS_S_i
.addrsig_sym _Z38__device_stub__multiply_kernel_add_cpuPiS_S_i
.addrsig_sym _Z38__device_stub__multiply_cpu_add_kernelPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15multiply_kernelPiS_S_i
.addrsig_sym _Z23multiply_kernel_add_cpuPiS_S_i
.addrsig_sym _Z23multiply_cpu_add_kernelPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void FloatDivByConstant(float *A, float constant)
{
unsigned int i = blockIdx.x * gridDim.y * gridDim.z * blockDim.x + blockIdx.y * gridDim.z * blockDim.x + blockIdx.z * blockDim.x + threadIdx.x;
A[i]=A[i]/constant;
}
|
code for sm_80
Function : _Z18FloatDivByConstantPff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0040*/ S2R R5, SR_CTAID.Z ; /* 0x0000000000057919 */
/* 0x000e680000002700 */
/*0050*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0x10], R3 ; /* 0x0000040000007a24 */
/* 0x001fe400078e0203 */
/*0070*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc400078e00ff */
/*0080*/ IMAD R0, R0, c[0x0][0x14], R5 ; /* 0x0000050000007a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fc800078e0207 */
/*00a0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0003 */
/*00b0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ MUFU.RCP R0, c[0x0][0x168] ; /* 0x00005a0000007b08 */
/* 0x000e220000001000 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff057624 */
/* 0x000fe200078e00ff */
/*00e0*/ BSSY B0, 0x1a0 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*00f0*/ FFMA R5, R0, -R5, 1 ; /* 0x3f80000000057423 */
/* 0x001fc80000000805 */
/*0100*/ FFMA R5, R0, R5, R0 ; /* 0x0000000500057223 */
/* 0x000fe20000000000 */
/*0110*/ FCHK P0, R4, c[0x0][0x168] ; /* 0x00005a0004007b02 */
/* 0x004e260000000000 */
/*0120*/ FFMA R0, R4, R5, RZ ; /* 0x0000000504007223 */
/* 0x000fc800000000ff */
/*0130*/ FFMA R6, R0, -c[0x0][0x168], R4 ; /* 0x80005a0000067a23 */
/* 0x000fc80000000004 */
/*0140*/ FFMA R5, R5, R6, R0 ; /* 0x0000000605057223 */
/* 0x000fe20000000000 */
/*0150*/ @!P0 BRA 0x190 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0160*/ MOV R0, 0x180 ; /* 0x0000018000007802 */
/* 0x000fe40000000f00 */
/*0170*/ CALL.REL.NOINC 0x1c0 ; /* 0x0000004000007944 */
/* 0x000fea0003c00000 */
/*0180*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0006 */
/*0190*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0c7624 */
/* 0x000fe200078e00ff */
/*01d0*/ SHF.R.U32.HI R5, RZ, 0x17, R4.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011604 */
/*01e0*/ BSSY B1, 0x830 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*01f0*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0004 */
/*0200*/ SHF.R.U32.HI R6, RZ, 0x17, R12 ; /* 0x00000017ff067819 */
/* 0x000fe2000001160c */
/*0210*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff087624 */
/* 0x000fe200078e00ff */
/*0220*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*0230*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fc400078ec0ff */
/*0240*/ IADD3 R10, R5, -0x1, RZ ; /* 0xffffffff050a7810 */
/* 0x000fe40007ffe0ff */
/*0250*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fc80007ffe0ff */
/*0260*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*0270*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*0280*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0290*/ @!P0 BRA 0x410 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*02a0*/ FSETP.GTU.FTZ.AND P1, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fe40003f3c200 */
/*02b0*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fc80003f1c200 */
/*02c0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*02d0*/ @P0 BRA 0x810 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*02e0*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*02f0*/ @!P0 BRA 0x7f0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0300*/ FSETP.NEU.FTZ.AND P2, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f5d200 */
/*0310*/ FSETP.NEU.FTZ.AND P1, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fe40003f3d200 */
/*0320*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fd60003f1d200 */
/*0330*/ @!P1 BRA !P2, 0x7f0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0340*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*0350*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0360*/ @P1 BRA 0x7d0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0370*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0380*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0390*/ @P0 BRA 0x7a0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*03a0*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*03b0*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*03c0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*03d0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*03e0*/ @!P0 FFMA R7, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004078823 */
/* 0x000fe400000000ff */
/*03f0*/ @!P1 FFMA R8, R12, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000c089823 */
/* 0x000fe200000000ff */
/*0400*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*0410*/ LEA R11, R6, 0xc0800000, 0x17 ; /* 0xc0800000060b7811 */
/* 0x000fe200078eb8ff */
/*0420*/ BSSY B2, 0x790 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0430*/ IADD3 R5, R5, -0x7f, RZ ; /* 0xffffff8105057810 */
/* 0x000fc60007ffe0ff */
/*0440*/ IMAD.IADD R11, R8, 0x1, -R11 ; /* 0x00000001080b7824 */
/* 0x000fe200078e0a0b */
/*0450*/ IADD3 R6, R5.reuse, 0x7f, -R6 ; /* 0x0000007f05067810 */
/* 0x040fe20007ffe806 */
/*0460*/ IMAD R7, R5, -0x800000, R7 ; /* 0xff80000005077824 */
/* 0x000fe400078e0207 */
/*0470*/ MUFU.RCP R4, R11 ; /* 0x0000000b00047308 */
/* 0x000e220000001000 */
/*0480*/ FADD.FTZ R8, -R11, -RZ ; /* 0x800000ff0b087221 */
/* 0x000fe40000010100 */
/*0490*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x000fe400078e0209 */
/*04a0*/ FFMA R13, R4, R8, 1 ; /* 0x3f800000040d7423 */
/* 0x001fc80000000008 */
/*04b0*/ FFMA R10, R4, R13, R4 ; /* 0x0000000d040a7223 */
/* 0x000fc80000000004 */
/*04c0*/ FFMA R4, R7, R10, RZ ; /* 0x0000000a07047223 */
/* 0x000fc800000000ff */
/*04d0*/ FFMA R13, R8, R4, R7 ; /* 0x00000004080d7223 */
/* 0x000fc80000000007 */
/*04e0*/ FFMA R13, R10, R13, R4 ; /* 0x0000000d0a0d7223 */
/* 0x000fc80000000004 */
/*04f0*/ FFMA R8, R8, R13, R7 ; /* 0x0000000d08087223 */
/* 0x000fc80000000007 */
/*0500*/ FFMA R4, R10, R8, R13 ; /* 0x000000080a047223 */
/* 0x000fca000000000d */
/*0510*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fc80000011604 */
/*0520*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*0530*/ IMAD.IADD R9, R5, 0x1, R6 ; /* 0x0000000105097824 */
/* 0x000fca00078e0206 */
/*0540*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*0550*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0560*/ @!P0 BRA 0x770 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0570*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*0580*/ @P0 BRA 0x740 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0590*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*05a0*/ @P0 BRA 0x780 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*05b0*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*05c0*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*05d0*/ @!P0 BRA 0x780 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*05e0*/ FFMA.RZ R5, R10.reuse, R8.reuse, R13.reuse ; /* 0x000000080a057223 */
/* 0x1c0fe2000000c00d */
/*05f0*/ ISETP.NE.AND P2, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720c */
/* 0x040fe20003f45270 */
/*0600*/ FFMA.RM R6, R10.reuse, R8.reuse, R13.reuse ; /* 0x000000080a067223 */
/* 0x1c0fe2000000400d */
/*0610*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*0620*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0630*/ FFMA.RP R5, R10, R8, R13 ; /* 0x000000080a057223 */
/* 0x000fe2000000800d */
/*0640*/ IADD3 R8, R9, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x000fe20007ffe0ff */
/*0650*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*0660*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*0670*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*0680*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*0690*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*06a0*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*06b0*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*06c0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*06d0*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*06e0*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*06f0*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0700*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*0710*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fca00078e0205 */
/*0720*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*0730*/ BRA 0x780 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0740*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*0750*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0760*/ BRA 0x780 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0770*/ IMAD R4, R6, 0x800000, R4 ; /* 0x0080000006047824 */
/* 0x000fe400078e0204 */
/*0780*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0790*/ BRA 0x820 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*07a0*/ LOP3.LUT R4, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008047812 */
/* 0x000fc800078e4807 */
/*07b0*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*07c0*/ BRA 0x820 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*07d0*/ LOP3.LUT R4, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008047812 */
/* 0x000fe200078e4807 */
/*07e0*/ BRA 0x820 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*07f0*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*0800*/ BRA 0x820 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0810*/ FADD.FTZ R4, R4, c[0x0][0x168] ; /* 0x00005a0004047621 */
/* 0x000fe40000010000 */
/*0820*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0830*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0004 */
/*0840*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0850*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0860*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff79004007950 */
/* 0x000fea0003c3ffff */
/*0870*/ BRA 0x870; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void FloatDivByConstant(float *A, float constant)
{
unsigned int i = blockIdx.x * gridDim.y * gridDim.z * blockDim.x + blockIdx.y * gridDim.z * blockDim.x + blockIdx.z * blockDim.x + threadIdx.x;
A[i]=A[i]/constant;
}
|
.file "tmpxft_000ac54b_00000000-6_FloatDivByConstant.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z18FloatDivByConstantPffPff
.type _Z39__device_stub__Z18FloatDivByConstantPffPff, @function
_Z39__device_stub__Z18FloatDivByConstantPffPff:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18FloatDivByConstantPff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z18FloatDivByConstantPffPff, .-_Z39__device_stub__Z18FloatDivByConstantPffPff
.globl _Z18FloatDivByConstantPff
.type _Z18FloatDivByConstantPff, @function
_Z18FloatDivByConstantPff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z18FloatDivByConstantPffPff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18FloatDivByConstantPff, .-_Z18FloatDivByConstantPff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18FloatDivByConstantPff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18FloatDivByConstantPff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void FloatDivByConstant(float *A, float constant)
{
unsigned int i = blockIdx.x * gridDim.y * gridDim.z * blockDim.x + blockIdx.y * gridDim.z * blockDim.x + blockIdx.z * blockDim.x + threadIdx.x;
A[i]=A[i]/constant;
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void FloatDivByConstant(float *A, float constant)
{
unsigned int i = blockIdx.x * gridDim.y * gridDim.z * blockDim.x + blockIdx.y * gridDim.z * blockDim.x + blockIdx.z * blockDim.x + threadIdx.x;
A[i]=A[i]/constant;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void FloatDivByConstant(float *A, float constant)
{
unsigned int i = blockIdx.x * gridDim.y * gridDim.z * blockDim.x + blockIdx.y * gridDim.z * blockDim.x + blockIdx.z * blockDim.x + threadIdx.x;
A[i]=A[i]/constant;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18FloatDivByConstantPff
.globl _Z18FloatDivByConstantPff
.p2align 8
.type _Z18FloatDivByConstantPff,@function
_Z18FloatDivByConstantPff:
s_clause 0x3
s_load_b64 s[2:3], s[0:1], 0x14
s_load_b32 s6, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s14
s_mul_i32 s2, s2, s3
s_and_b32 s3, s6, 0xffff
s_add_i32 s2, s2, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v3, null, s0, s0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
v_fmac_f32_e32 v4, v5, v4
v_div_scale_f32 v5, vcc_lo, v2, s0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v5, v4
v_fma_f32 v7, -v3, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v7, v4
v_fma_f32 v3, -v3, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v3, v3, v4, v6
v_div_fixup_f32 v2, v3, s0, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18FloatDivByConstantPff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18FloatDivByConstantPff, .Lfunc_end0-_Z18FloatDivByConstantPff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18FloatDivByConstantPff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18FloatDivByConstantPff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void FloatDivByConstant(float *A, float constant)
{
unsigned int i = blockIdx.x * gridDim.y * gridDim.z * blockDim.x + blockIdx.y * gridDim.z * blockDim.x + blockIdx.z * blockDim.x + threadIdx.x;
A[i]=A[i]/constant;
}
|
.text
.file "FloatDivByConstant.hip"
.globl _Z33__device_stub__FloatDivByConstantPff # -- Begin function _Z33__device_stub__FloatDivByConstantPff
.p2align 4, 0x90
.type _Z33__device_stub__FloatDivByConstantPff,@function
_Z33__device_stub__FloatDivByConstantPff: # @_Z33__device_stub__FloatDivByConstantPff
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z18FloatDivByConstantPff, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z33__device_stub__FloatDivByConstantPff, .Lfunc_end0-_Z33__device_stub__FloatDivByConstantPff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18FloatDivByConstantPff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18FloatDivByConstantPff,@object # @_Z18FloatDivByConstantPff
.section .rodata,"a",@progbits
.globl _Z18FloatDivByConstantPff
.p2align 3, 0x0
_Z18FloatDivByConstantPff:
.quad _Z33__device_stub__FloatDivByConstantPff
.size _Z18FloatDivByConstantPff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18FloatDivByConstantPff"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__FloatDivByConstantPff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18FloatDivByConstantPff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z18FloatDivByConstantPff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0040*/ S2R R5, SR_CTAID.Z ; /* 0x0000000000057919 */
/* 0x000e680000002700 */
/*0050*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0x10], R3 ; /* 0x0000040000007a24 */
/* 0x001fe400078e0203 */
/*0070*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc400078e00ff */
/*0080*/ IMAD R0, R0, c[0x0][0x14], R5 ; /* 0x0000050000007a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fc800078e0207 */
/*00a0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0003 */
/*00b0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ MUFU.RCP R0, c[0x0][0x168] ; /* 0x00005a0000007b08 */
/* 0x000e220000001000 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff057624 */
/* 0x000fe200078e00ff */
/*00e0*/ BSSY B0, 0x1a0 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*00f0*/ FFMA R5, R0, -R5, 1 ; /* 0x3f80000000057423 */
/* 0x001fc80000000805 */
/*0100*/ FFMA R5, R0, R5, R0 ; /* 0x0000000500057223 */
/* 0x000fe20000000000 */
/*0110*/ FCHK P0, R4, c[0x0][0x168] ; /* 0x00005a0004007b02 */
/* 0x004e260000000000 */
/*0120*/ FFMA R0, R4, R5, RZ ; /* 0x0000000504007223 */
/* 0x000fc800000000ff */
/*0130*/ FFMA R6, R0, -c[0x0][0x168], R4 ; /* 0x80005a0000067a23 */
/* 0x000fc80000000004 */
/*0140*/ FFMA R5, R5, R6, R0 ; /* 0x0000000605057223 */
/* 0x000fe20000000000 */
/*0150*/ @!P0 BRA 0x190 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0160*/ MOV R0, 0x180 ; /* 0x0000018000007802 */
/* 0x000fe40000000f00 */
/*0170*/ CALL.REL.NOINC 0x1c0 ; /* 0x0000004000007944 */
/* 0x000fea0003c00000 */
/*0180*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0006 */
/*0190*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0c7624 */
/* 0x000fe200078e00ff */
/*01d0*/ SHF.R.U32.HI R5, RZ, 0x17, R4.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011604 */
/*01e0*/ BSSY B1, 0x830 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*01f0*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0004 */
/*0200*/ SHF.R.U32.HI R6, RZ, 0x17, R12 ; /* 0x00000017ff067819 */
/* 0x000fe2000001160c */
/*0210*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff087624 */
/* 0x000fe200078e00ff */
/*0220*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*0230*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fc400078ec0ff */
/*0240*/ IADD3 R10, R5, -0x1, RZ ; /* 0xffffffff050a7810 */
/* 0x000fe40007ffe0ff */
/*0250*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fc80007ffe0ff */
/*0260*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*0270*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*0280*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0290*/ @!P0 BRA 0x410 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*02a0*/ FSETP.GTU.FTZ.AND P1, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fe40003f3c200 */
/*02b0*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fc80003f1c200 */
/*02c0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*02d0*/ @P0 BRA 0x810 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*02e0*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*02f0*/ @!P0 BRA 0x7f0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0300*/ FSETP.NEU.FTZ.AND P2, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f5d200 */
/*0310*/ FSETP.NEU.FTZ.AND P1, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fe40003f3d200 */
/*0320*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fd60003f1d200 */
/*0330*/ @!P1 BRA !P2, 0x7f0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0340*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*0350*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0360*/ @P1 BRA 0x7d0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0370*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0380*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0390*/ @P0 BRA 0x7a0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*03a0*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*03b0*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*03c0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*03d0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*03e0*/ @!P0 FFMA R7, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004078823 */
/* 0x000fe400000000ff */
/*03f0*/ @!P1 FFMA R8, R12, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000c089823 */
/* 0x000fe200000000ff */
/*0400*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*0410*/ LEA R11, R6, 0xc0800000, 0x17 ; /* 0xc0800000060b7811 */
/* 0x000fe200078eb8ff */
/*0420*/ BSSY B2, 0x790 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0430*/ IADD3 R5, R5, -0x7f, RZ ; /* 0xffffff8105057810 */
/* 0x000fc60007ffe0ff */
/*0440*/ IMAD.IADD R11, R8, 0x1, -R11 ; /* 0x00000001080b7824 */
/* 0x000fe200078e0a0b */
/*0450*/ IADD3 R6, R5.reuse, 0x7f, -R6 ; /* 0x0000007f05067810 */
/* 0x040fe20007ffe806 */
/*0460*/ IMAD R7, R5, -0x800000, R7 ; /* 0xff80000005077824 */
/* 0x000fe400078e0207 */
/*0470*/ MUFU.RCP R4, R11 ; /* 0x0000000b00047308 */
/* 0x000e220000001000 */
/*0480*/ FADD.FTZ R8, -R11, -RZ ; /* 0x800000ff0b087221 */
/* 0x000fe40000010100 */
/*0490*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x000fe400078e0209 */
/*04a0*/ FFMA R13, R4, R8, 1 ; /* 0x3f800000040d7423 */
/* 0x001fc80000000008 */
/*04b0*/ FFMA R10, R4, R13, R4 ; /* 0x0000000d040a7223 */
/* 0x000fc80000000004 */
/*04c0*/ FFMA R4, R7, R10, RZ ; /* 0x0000000a07047223 */
/* 0x000fc800000000ff */
/*04d0*/ FFMA R13, R8, R4, R7 ; /* 0x00000004080d7223 */
/* 0x000fc80000000007 */
/*04e0*/ FFMA R13, R10, R13, R4 ; /* 0x0000000d0a0d7223 */
/* 0x000fc80000000004 */
/*04f0*/ FFMA R8, R8, R13, R7 ; /* 0x0000000d08087223 */
/* 0x000fc80000000007 */
/*0500*/ FFMA R4, R10, R8, R13 ; /* 0x000000080a047223 */
/* 0x000fca000000000d */
/*0510*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fc80000011604 */
/*0520*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*0530*/ IMAD.IADD R9, R5, 0x1, R6 ; /* 0x0000000105097824 */
/* 0x000fca00078e0206 */
/*0540*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*0550*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0560*/ @!P0 BRA 0x770 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0570*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*0580*/ @P0 BRA 0x740 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0590*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*05a0*/ @P0 BRA 0x780 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*05b0*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*05c0*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*05d0*/ @!P0 BRA 0x780 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*05e0*/ FFMA.RZ R5, R10.reuse, R8.reuse, R13.reuse ; /* 0x000000080a057223 */
/* 0x1c0fe2000000c00d */
/*05f0*/ ISETP.NE.AND P2, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720c */
/* 0x040fe20003f45270 */
/*0600*/ FFMA.RM R6, R10.reuse, R8.reuse, R13.reuse ; /* 0x000000080a067223 */
/* 0x1c0fe2000000400d */
/*0610*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*0620*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0630*/ FFMA.RP R5, R10, R8, R13 ; /* 0x000000080a057223 */
/* 0x000fe2000000800d */
/*0640*/ IADD3 R8, R9, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x000fe20007ffe0ff */
/*0650*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*0660*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*0670*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*0680*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*0690*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*06a0*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*06b0*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*06c0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*06d0*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*06e0*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*06f0*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0700*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*0710*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fca00078e0205 */
/*0720*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*0730*/ BRA 0x780 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0740*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*0750*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0760*/ BRA 0x780 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0770*/ IMAD R4, R6, 0x800000, R4 ; /* 0x0080000006047824 */
/* 0x000fe400078e0204 */
/*0780*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0790*/ BRA 0x820 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*07a0*/ LOP3.LUT R4, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008047812 */
/* 0x000fc800078e4807 */
/*07b0*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*07c0*/ BRA 0x820 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*07d0*/ LOP3.LUT R4, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008047812 */
/* 0x000fe200078e4807 */
/*07e0*/ BRA 0x820 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*07f0*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*0800*/ BRA 0x820 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0810*/ FADD.FTZ R4, R4, c[0x0][0x168] ; /* 0x00005a0004047621 */
/* 0x000fe40000010000 */
/*0820*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0830*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0004 */
/*0840*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0850*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0860*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff79004007950 */
/* 0x000fea0003c3ffff */
/*0870*/ BRA 0x870; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18FloatDivByConstantPff
.globl _Z18FloatDivByConstantPff
.p2align 8
.type _Z18FloatDivByConstantPff,@function
_Z18FloatDivByConstantPff:
s_clause 0x3
s_load_b64 s[2:3], s[0:1], 0x14
s_load_b32 s6, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s14
s_mul_i32 s2, s2, s3
s_and_b32 s3, s6, 0xffff
s_add_i32 s2, s2, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v3, null, s0, s0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
v_fmac_f32_e32 v4, v5, v4
v_div_scale_f32 v5, vcc_lo, v2, s0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v5, v4
v_fma_f32 v7, -v3, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v7, v4
v_fma_f32 v3, -v3, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v3, v3, v4, v6
v_div_fixup_f32 v2, v3, s0, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18FloatDivByConstantPff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18FloatDivByConstantPff, .Lfunc_end0-_Z18FloatDivByConstantPff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18FloatDivByConstantPff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18FloatDivByConstantPff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000ac54b_00000000-6_FloatDivByConstant.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z18FloatDivByConstantPffPff
.type _Z39__device_stub__Z18FloatDivByConstantPffPff, @function
_Z39__device_stub__Z18FloatDivByConstantPffPff:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18FloatDivByConstantPff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z18FloatDivByConstantPffPff, .-_Z39__device_stub__Z18FloatDivByConstantPffPff
.globl _Z18FloatDivByConstantPff
.type _Z18FloatDivByConstantPff, @function
_Z18FloatDivByConstantPff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z18FloatDivByConstantPffPff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18FloatDivByConstantPff, .-_Z18FloatDivByConstantPff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18FloatDivByConstantPff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18FloatDivByConstantPff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "FloatDivByConstant.hip"
.globl _Z33__device_stub__FloatDivByConstantPff # -- Begin function _Z33__device_stub__FloatDivByConstantPff
.p2align 4, 0x90
.type _Z33__device_stub__FloatDivByConstantPff,@function
_Z33__device_stub__FloatDivByConstantPff: # @_Z33__device_stub__FloatDivByConstantPff
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z18FloatDivByConstantPff, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z33__device_stub__FloatDivByConstantPff, .Lfunc_end0-_Z33__device_stub__FloatDivByConstantPff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18FloatDivByConstantPff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18FloatDivByConstantPff,@object # @_Z18FloatDivByConstantPff
.section .rodata,"a",@progbits
.globl _Z18FloatDivByConstantPff
.p2align 3, 0x0
_Z18FloatDivByConstantPff:
.quad _Z33__device_stub__FloatDivByConstantPff
.size _Z18FloatDivByConstantPff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18FloatDivByConstantPff"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__FloatDivByConstantPff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18FloatDivByConstantPff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <cuda_runtime.h>
#include <thrust/device_ptr.h>
#include <thrust/sort.h>
extern void sort_uint_internal(void* dev_ptr, unsigned numElements, void* output_ptr)
{
if(output_ptr) {
cudaMemcpy(output_ptr, dev_ptr, numElements * sizeof(unsigned), cudaMemcpyDeviceToDevice);
} else {
output_ptr = dev_ptr;
}
thrust::device_ptr<unsigned> dp((unsigned*)output_ptr);
thrust::stable_sort(dp, dp + numElements);
}
extern void sort_double_internal(void* dev_ptr, unsigned numElements, void* output_ptr)
{
if(output_ptr) {
cudaMemcpy(output_ptr, dev_ptr, numElements * sizeof(double), cudaMemcpyDeviceToDevice);
} else {
output_ptr = dev_ptr;
}
thrust::device_ptr<double> dp((double*)output_ptr);
thrust::stable_sort(dp, dp + numElements);
}
|
#include <hip/hip_runtime.h>
#include <thrust/device_ptr.h>
#include <thrust/sort.h>
extern void sort_uint_internal(void* dev_ptr, unsigned numElements, void* output_ptr)
{
if(output_ptr) {
hipMemcpy(output_ptr, dev_ptr, numElements * sizeof(unsigned), hipMemcpyDeviceToDevice);
} else {
output_ptr = dev_ptr;
}
thrust::device_ptr<unsigned> dp((unsigned*)output_ptr);
thrust::stable_sort(dp, dp + numElements);
}
extern void sort_double_internal(void* dev_ptr, unsigned numElements, void* output_ptr)
{
if(output_ptr) {
hipMemcpy(output_ptr, dev_ptr, numElements * sizeof(double), hipMemcpyDeviceToDevice);
} else {
output_ptr = dev_ptr;
}
thrust::device_ptr<double> dp((double*)output_ptr);
thrust::stable_sort(dp, dp + numElements);
}
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "kernel.cuh"
void error(char const* str)
{
fprintf(stderr, "%s\n", str);
exit(1);
}
void cuda_check(cudaError_t err, char const* str)
{
if (err != cudaSuccess) {
fprintf(stderr, "%s: CUDA error %d (%s)\n",
str, err, cudaGetErrorString(err));
}
}
__global__ void fractal(int nrows, int ncols, int max_iter, double startX, double startY, double zoom, int* result) //373 - 326
{
int x_idx = threadIdx.x + blockIdx.x * blockDim.x;
int y_idx = threadIdx.y + blockIdx.y * blockDim.y;
if (x_idx >= ncols || y_idx >= nrows)
return;
int l = x_idx + y_idx * ncols;
double x = ((x_idx - ncols / 2) * zoom + startX) / ncols * 3.5 - 0.75;
double y = ((y_idx - nrows / 2) * zoom + startY) / nrows * 2.0;
double re = x, im = y;
for (int i = 1; i < max_iter; ++i)
{
if (re * re + im * im >= 4)
{
result[l] = i;
return;
}
double reTemp = re * re - im * im + x;
im = 2 * re * im + y;
re = reTemp;
}
result[l] = 0;
}
#if __DEBUG
__global__ void fractal_old(int nrows, int ncols, int* result) //398.86642 - 343.53
{
int x_idx = threadIdx.x + blockIdx.x * blockDim.x;
int y_idx = threadIdx.y + blockIdx.y * blockDim.y;
if (x_idx >= nrows || y_idx >= ncols)
return;
int l = x_idx * ncols + y_idx;
double x = (double)x_idx / nrows * 3.5 - 2.5;
double y = (double)y_idx / ncols * 2.0 - 1.0;
double re = x, im = y;
for (int i = 1; i < MAX_ITERATIONS; ++i)
{
if (re * re + im * im >= 4)
{
result[l] = i;
return;
}
double reTemp = re * re - im * im + x;
im = 2 * re * im + y;
re = reTemp;
}
result[l] = 0;
}
#endif
int* mendelbrot_kernel(int nrows, int ncols, int max_iter, double startX, double startY, double zoom)
{
cudaError_t err;
cudaEvent_t start, end;
int* d_result, * h_result;
size_t res_size = nrows * ncols * sizeof(int);
float time;
err = cudaMalloc(&d_result, res_size);
cuda_check(err, "cudaMalloc");
err = cudaMallocHost(&h_result, res_size);
cuda_check(err, "cudaMallocHost");
cudaEventCreate(&start);
cudaEventCreate(&end);
dim3 dimBlock(32, 32);
dim3 dimGrid((ncols + 31) / 32, (nrows + 31) / 32);
cudaEventRecord(start);
fractal << <dimGrid, dimBlock >> > (nrows, ncols, max_iter, startX, startY, zoom, d_result);
cudaEventRecord(end);
err = cudaMemcpy(h_result, d_result, res_size, cudaMemcpyDeviceToHost);
cuda_check(err, "cudaMalloc");
err = cudaEventSynchronize(end);
cuda_check(err, "sync");
cudaEventElapsedTime(&time, start, end);
//printf("Tempo passato = %f\n", time);
err = cudaFree(d_result);
cuda_check(err, "cudaFree");
return h_result;
}
#if __DEBUG
int main()
{
int* result = kernel_start(12000, 8000);
//int* result = kernel_start();
// for (int j = NCOLS - 1; j >= 0; --j)
// {
// for (int i = 0; i < NROWS; i++)
// {
// printf("%d ", result[i * NCOLS + j]);
// }
// printf("\n");
// }
// for (int j = 0; j < NROWS; ++j)
// {
// for (int i = 0; i < NCOLS; ++i)
// {
// printf("%d ", result[j * NCOLS + i]);
// }
// printf("\n");
// }
return 0;
}
#endif
|
code for sm_80
Function : _Z7fractaliiidddPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0030*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e680000002600 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x164], PT ; /* 0x0000590005007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R4, R4, c[0x0][0x4], R3 ; /* 0x0000010004047a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R4, c[0x0][0x160], P0 ; /* 0x0000580004007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ I2F.F64 R2, c[0x0][0x164] ; /* 0x0000590000027b12 */
/* 0x000e220000201c00 */
/*00b0*/ ULDC UR4, c[0x0][0x164] ; /* 0x0000590000047ab9 */
/* 0x000fe20000000800 */
/*00c0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*00d0*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fe2000f8f083f */
/*00e0*/ BSSY B0, 0x280 ; /* 0x0000019000007945 */
/* 0x000fe60003800000 */
/*00f0*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011404 */
/*0100*/ IADD3 R0, R5, -UR4, RZ ; /* 0x8000000405007c10 */
/* 0x000fe2000fffe0ff */
/*0110*/ MUFU.RCP64H R9, R3 ; /* 0x0000000300097308 */
/* 0x001e240000001800 */
/*0120*/ DFMA R6, -R2, R8, 1 ; /* 0x3ff000000206742b */
/* 0x001e0c0000000108 */
/*0130*/ DFMA R10, R6, R6, R6 ; /* 0x00000006060a722b */
/* 0x0010480000000006 */
/*0140*/ I2F.F64 R6, R0 ; /* 0x0000000000067312 */
/* 0x0010a40000201c00 */
/*0150*/ DFMA R10, R8, R10, R8 ; /* 0x0000000a080a722b */
/* 0x0022e40000000008 */
/*0160*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff087624 */
/* 0x002fe400078e00ff */
/*0170*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff097624 */
/* 0x000fe400078e00ff */
/*0180*/ DFMA R12, -R2, R10, 1 ; /* 0x3ff00000020c742b */
/* 0x008e62000000010a */
/*0190*/ IMAD R0, R4, c[0x0][0x164], R5 ; /* 0x0000590004007a24 */
/* 0x001fca00078e0205 */
/*01a0*/ DFMA R12, R10, R12, R10 ; /* 0x0000000c0a0c722b */
/* 0x002fc8000000000a */
/*01b0*/ DFMA R8, R6, R8, c[0x0][0x170] ; /* 0x00005c000608762b */
/* 0x004e0c0000000008 */
/*01c0*/ DMUL R6, R8, R12 ; /* 0x0000000c08067228 */
/* 0x001e080000000000 */
/*01d0*/ FSETP.GEU.AND P1, PT, |R9|, 6.5827683646048100446e-37, PT ; /* 0x036000000900780b */
/* 0x000fe40003f2e200 */
/*01e0*/ DFMA R10, -R2, R6, R8 ; /* 0x00000006020a722b */
/* 0x001e0c0000000108 */
/*01f0*/ DFMA R6, R12, R10, R6 ; /* 0x0000000a0c06722b */
/* 0x001e140000000006 */
/*0200*/ FFMA R10, RZ, R3, R7 ; /* 0x00000003ff0a7223 */
/* 0x001fca0000000007 */
/*0210*/ FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ; /* 0x001000000a00780b */
/* 0x000fda0003f04200 */
/*0220*/ @P0 BRA P1, 0x270 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*0230*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0008 */
/*0240*/ MOV R12, 0x270 ; /* 0x00000270000c7802 */
/* 0x000fe20000000f00 */
/*0250*/ IMAD.MOV.U32 R11, RZ, RZ, R9 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0009 */
/*0260*/ CALL.REL.NOINC 0x680 ; /* 0x0000041000007944 */
/* 0x000fea0003c00000 */
/*0270*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0280*/ I2F.F64 R2, c[0x0][0x160] ; /* 0x0000580000027b12 */
/* 0x000e220000201c00 */
/*0290*/ ULDC UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe20000000800 */
/*02a0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*02b0*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fe2000f8f083f */
/*02c0*/ BSSY B0, 0x4a0 ; /* 0x000001d000007945 */
/* 0x000fe60003800000 */
/*02d0*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011404 */
/*02e0*/ IADD3 R14, R4, -UR4, RZ ; /* 0x80000004040e7c10 */
/* 0x000fe2000fffe0ff */
/*02f0*/ MUFU.RCP64H R9, R3 ; /* 0x0000000300097308 */
/* 0x001e300000001800 */
/*0300*/ I2F.F64 R4, R14 ; /* 0x0000000e00047312 */
/* 0x000ea20000201c00 */
/*0310*/ DFMA R10, -R2, R8, 1 ; /* 0x3ff00000020a742b */
/* 0x001e0c0000000108 */
/*0320*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0330*/ DFMA R10, R8, R10, R8 ; /* 0x0000000a080a722b */
/* 0x0010e40000000008 */
/*0340*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff087624 */
/* 0x001fe400078e00ff */
/*0350*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff097624 */
/* 0x000fe400078e00ff */
/*0360*/ DFMA R12, -R2, R10, 1 ; /* 0x3ff00000020c742b */
/* 0x008e08000000010a */
/*0370*/ DFMA R8, R4, R8, c[0x0][0x178] ; /* 0x00005e000408762b */
/* 0x004fc80000000008 */
/*0380*/ DFMA R12, R10, R12, R10 ; /* 0x0000000c0a0c722b */
/* 0x001e0c000000000a */
/*0390*/ DMUL R4, R8, R12 ; /* 0x0000000c08047228 */
/* 0x001e220000000000 */
/*03a0*/ FSETP.GEU.AND P1, PT, |R9|, 6.5827683646048100446e-37, PT ; /* 0x036000000900780b */
/* 0x000fca0003f2e200 */
/*03b0*/ DFMA R10, -R2, R4, R8 ; /* 0x00000004020a722b */
/* 0x001e0c0000000108 */
/*03c0*/ DFMA R10, R12, R10, R4 ; /* 0x0000000a0c0a722b */
/* 0x0010a40000000004 */
/*03d0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff047424 */
/* 0x001fe400078e00ff */
/*03e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x400c0000 ; /* 0x400c0000ff057424 */
/* 0x000fcc00078e00ff */
/*03f0*/ FFMA R12, RZ, R3, R11 ; /* 0x00000003ff0c7223 */
/* 0x004fe2000000000b */
/*0400*/ DFMA R4, R6, R4, -0.75 ; /* 0xbfe800000604742b */
/* 0x0000880000000004 */
/*0410*/ FSETP.GT.AND P0, PT, |R12|, 1.469367938527859385e-39, PT ; /* 0x001000000c00780b */
/* 0x000fda0003f04200 */
/*0420*/ @P0 BRA P1, 0x490 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*0430*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a7224 */
/* 0x005fe200078e0008 */
/*0440*/ MOV R12, 0x470 ; /* 0x00000470000c7802 */
/* 0x000fe20000000f00 */
/*0450*/ IMAD.MOV.U32 R11, RZ, RZ, R9 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0009 */
/*0460*/ CALL.REL.NOINC 0x680 ; /* 0x0000021000007944 */
/* 0x002fea0003c00000 */
/*0470*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0006 */
/*0480*/ IMAD.MOV.U32 R11, RZ, RZ, R7 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0007 */
/*0490*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x005fea0003800000 */
/*04a0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*04b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*04c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*04d0*/ DADD R14, R10, R10 ; /* 0x000000000a0e7229 */
/* 0x0000a4000000000a */
/*04e0*/ ISETP.GE.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fe20003f06270 */
/*04f0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x188] ; /* 0x0000620000027625 */
/* 0x000fd800078e0203 */
/*0500*/ @!P0 BRA 0x630 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0510*/ BSSY B0, 0x660 ; /* 0x0000014000007945 */
/* 0x005fe20003800000 */
/*0520*/ IMAD.MOV.U32 R17, RZ, RZ, 0x1 ; /* 0x00000001ff117424 */
/* 0x002fe400078e00ff */
/*0530*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000e */
/*0540*/ IMAD.MOV.U32 R7, RZ, RZ, R15 ; /* 0x000000ffff077224 */
/* 0x000fe400078e000f */
/*0550*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0004 */
/*0560*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0005 */
/*0570*/ DMUL R10, R6, R6 ; /* 0x00000006060a7228 */
/* 0x000fc80000000000 */
/*0580*/ DMUL R12, R8, R8 ; /* 0x00000008080c7228 */
/* 0x000e0c0000000000 */
/*0590*/ DADD R18, R10, R12 ; /* 0x000000000a127229 */
/* 0x001e0c000000000c */
/*05a0*/ DSETP.GE.AND P0, PT, R18, 4, PT ; /* 0x401000001200742a */
/* 0x001e1c0003f06000 */
/*05b0*/ @P0 BRA 0x650 ; /* 0x0000009000000947 */
/* 0x001fea0003800000 */
/*05c0*/ IADD3 R17, R17, 0x1, RZ ; /* 0x0000000111117810 */
/* 0x000fe20007ffe0ff */
/*05d0*/ DADD R10, -R10, R12 ; /* 0x000000000a0a7229 */
/* 0x000e06000000010c */
/*05e0*/ ISETP.GE.AND P0, PT, R17, c[0x0][0x168], PT ; /* 0x00005a0011007a0c */
/* 0x000fe20003f06270 */
/*05f0*/ DADD R12, R8, R8 ; /* 0x00000000080c7229 */
/* 0x000e480000000008 */
/*0600*/ DADD R8, R4, R10 ; /* 0x0000000004087229 */
/* 0x001088000000000a */
/*0610*/ DFMA R6, R12, R6, R14 ; /* 0x000000060c06722b */
/* 0x002048000000000e */
/*0620*/ @!P0 BRA 0x570 ; /* 0xffffff4000008947 */
/* 0x007fea000383ffff */
/*0630*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x005fe2000c101904 */
/*0640*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0650*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0660*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x000fe2000c101904 */
/*0670*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0680*/ FSETP.GEU.AND P0, PT, |R3|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000300780b */
/* 0x040fe20003f0e200 */
/*0690*/ IMAD.MOV.U32 R8, RZ, RZ, R2.reuse ; /* 0x000000ffff087224 */
/* 0x100fe200078e0002 */
/*06a0*/ LOP3.LUT R6, R3, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff03067812 */
/* 0x000fe200078ec0ff */
/*06b0*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0003 */
/*06c0*/ FSETP.GEU.AND P2, PT, |R11|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000b00780b */
/* 0x040fe20003f4e200 */
/*06d0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0e7424 */
/* 0x000fe200078e00ff */
/*06e0*/ LOP3.LUT R7, R6, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000006077812 */
/* 0x000fe200078efcff */
/*06f0*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0002 */
/*0700*/ LOP3.LUT R13, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b0d7812 */
/* 0x000fe200078ec0ff */
/*0710*/ IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; /* 0x00000001ff127424 */
/* 0x000fe200078e00ff */
/*0720*/ LOP3.LUT R20, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003147812 */
/* 0x000fe200078ec0ff */
/*0730*/ BSSY B1, 0xc40 ; /* 0x0000050000017945 */
/* 0x000fe40003800000 */
/*0740*/ @!P0 DMUL R6, R8, 8.98846567431157953865e+307 ; /* 0x7fe0000008068828 */
/* 0x000e220000000000 */
/*0750*/ ISETP.GE.U32.AND P1, PT, R13, R20, PT ; /* 0x000000140d00720c */
/* 0x000fc60003f26070 */
/*0760*/ @!P2 LOP3.LUT R2, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000902a812 */
/* 0x000fe200078ec0ff */
/*0770*/ @!P2 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff10a224 */
/* 0x000fe200078e00ff */
/*0780*/ MUFU.RCP64H R19, R7 ; /* 0x0000000700137308 */
/* 0x001e220000001800 */
/*0790*/ SEL R3, R14.reuse, 0x63400000, !P1 ; /* 0x634000000e037807 */
/* 0x040fe40004800000 */
/*07a0*/ @!P2 ISETP.GE.U32.AND P3, PT, R13, R2, PT ; /* 0x000000020d00a20c */
/* 0x000fe20003f66070 */
/*07b0*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000a */
/*07c0*/ LOP3.LUT R3, R3, 0x800fffff, R11, 0xf8, !PT ; /* 0x800fffff03037812 */
/* 0x000fe400078ef80b */
/*07d0*/ @!P2 SEL R15, R14, 0x63400000, !P3 ; /* 0x634000000e0fa807 */
/* 0x000fc80005800000 */
/*07e0*/ @!P2 LOP3.LUT R15, R15, 0x80000000, R11, 0xf8, !PT ; /* 0x800000000f0fa812 */
/* 0x000fc800078ef80b */
/*07f0*/ @!P2 LOP3.LUT R17, R15, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000f11a812 */
/* 0x000fe200078efcff */
/*0800*/ DFMA R22, R18, -R6, 1 ; /* 0x3ff000001216742b */
/* 0x001e220000000806 */
/*0810*/ IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e000d */
/*0820*/ @!P2 DFMA R2, R2, 2, -R16 ; /* 0x400000000202a82b */
/* 0x000fc80000000810 */
/*0830*/ DFMA R22, R22, R22, R22 ; /* 0x000000161616722b */
/* 0x001e0c0000000016 */
/*0840*/ DFMA R18, R18, R22, R18 ; /* 0x000000161212722b */
/* 0x0010620000000012 */
/*0850*/ @!P2 LOP3.LUT R15, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000030fa812 */
/* 0x000fe200078ec0ff */
/*0860*/ IMAD.MOV.U32 R22, RZ, RZ, R20 ; /* 0x000000ffff167224 */
/* 0x001fe200078e0014 */
/*0870*/ @!P0 LOP3.LUT R22, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007168812 */
/* 0x000fe400078ec0ff */
/*0880*/ IADD3 R20, R15, -0x1, RZ ; /* 0xffffffff0f147810 */
/* 0x000fe20007ffe0ff */
/*0890*/ DFMA R16, R18, -R6, 1 ; /* 0x3ff000001210742b */
/* 0x002e220000000806 */
/*08a0*/ IADD3 R23, R22, -0x1, RZ ; /* 0xffffffff16177810 */
/* 0x000fe40007ffe0ff */
/*08b0*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fc60003f04070 */
/*08c0*/ DFMA R16, R18, R16, R18 ; /* 0x000000101210722b */
/* 0x001e220000000012 */
/*08d0*/ ISETP.GT.U32.OR P0, PT, R23, 0x7feffffe, P0 ; /* 0x7feffffe1700780c */
/* 0x000fca0000704470 */
/*08e0*/ DMUL R18, R16, R2 ; /* 0x0000000210127228 */
/* 0x001e0c0000000000 */
/*08f0*/ DFMA R20, R18, -R6, R2 ; /* 0x800000061214722b */
/* 0x001e0c0000000002 */
/*0900*/ DFMA R16, R16, R20, R18 ; /* 0x000000141010722b */
/* 0x0010620000000012 */
/*0910*/ @P0 BRA 0xae0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0920*/ LOP3.LUT R18, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009127812 */
/* 0x001fc800078ec0ff */
/*0930*/ ISETP.GE.U32.AND P0, PT, R13.reuse, R18, PT ; /* 0x000000120d00720c */
/* 0x040fe20003f06070 */
/*0940*/ IMAD.IADD R10, R13, 0x1, -R18 ; /* 0x000000010d0a7824 */
/* 0x000fc600078e0a12 */
/*0950*/ SEL R13, R14, 0x63400000, !P0 ; /* 0x634000000e0d7807 */
/* 0x000fe40004000000 */
/*0960*/ IMNMX R10, R10, -0x46a00000, !PT ; /* 0xb96000000a0a7817 */
/* 0x000fc80007800200 */
/*0970*/ IMNMX R10, R10, 0x46a00000, PT ; /* 0x46a000000a0a7817 */
/* 0x000fca0003800200 */
/*0980*/ IMAD.IADD R13, R10, 0x1, -R13 ; /* 0x000000010a0d7824 */
/* 0x000fe400078e0a0d */
/*0990*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fc600078e00ff */
/*09a0*/ IADD3 R11, R13, 0x7fe00000, RZ ; /* 0x7fe000000d0b7810 */
/* 0x000fcc0007ffe0ff */
/*09b0*/ DMUL R18, R16, R10 ; /* 0x0000000a10127228 */
/* 0x002e140000000000 */
/*09c0*/ FSETP.GTU.AND P0, PT, |R19|, 1.469367938527859385e-39, PT ; /* 0x001000001300780b */
/* 0x001fda0003f0c200 */
/*09d0*/ @P0 BRA 0xc30 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*09e0*/ DFMA R2, R16, -R6, R2 ; /* 0x800000061002722b */
/* 0x000e220000000002 */
/*09f0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fd200078e00ff */
/*0a00*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*0a10*/ LOP3.LUT R9, R3, 0x80000000, R9, 0x48, !PT ; /* 0x8000000003097812 */
/* 0x000fc800078e4809 */
/*0a20*/ LOP3.LUT R11, R9, R11, RZ, 0xfc, !PT ; /* 0x0000000b090b7212 */
/* 0x000fce00078efcff */
/*0a30*/ @!P0 BRA 0xc30 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0a40*/ IMAD.MOV R3, RZ, RZ, -R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0d */
/*0a50*/ DMUL.RP R10, R16, R10 ; /* 0x0000000a100a7228 */
/* 0x000e220000008000 */
/*0a60*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0a70*/ DFMA R2, R18, -R2, R16 ; /* 0x800000021202722b */
/* 0x000e460000000010 */
/*0a80*/ LOP3.LUT R9, R11, R9, RZ, 0x3c, !PT ; /* 0x000000090b097212 */
/* 0x001fc600078e3cff */
/*0a90*/ IADD3 R2, -R13, -0x43300000, RZ ; /* 0xbcd000000d027810 */
/* 0x002fc80007ffe1ff */
/*0aa0*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*0ab0*/ FSEL R18, R10, R18, !P0 ; /* 0x000000120a127208 */
/* 0x000fe40004000000 */
/*0ac0*/ FSEL R19, R9, R19, !P0 ; /* 0x0000001309137208 */
/* 0x000fe20004000000 */
/*0ad0*/ BRA 0xc30 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0ae0*/ DSETP.NAN.AND P0, PT, R10, R10, PT ; /* 0x0000000a0a00722a */
/* 0x000e9c0003f08000 */
/*0af0*/ @P0 BRA 0xc10 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0b00*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e9c0003f08000 */
/*0b10*/ @P0 BRA 0xbe0 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0b20*/ ISETP.NE.AND P0, PT, R15, R22, PT ; /* 0x000000160f00720c */
/* 0x000fe20003f05270 */
/*0b30*/ IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; /* 0x00000000ff127424 */
/* 0x001fe400078e00ff */
/*0b40*/ IMAD.MOV.U32 R19, RZ, RZ, -0x80000 ; /* 0xfff80000ff137424 */
/* 0x000fd400078e00ff */
/*0b50*/ @!P0 BRA 0xc30 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0b60*/ ISETP.NE.AND P0, PT, R15, 0x7ff00000, PT ; /* 0x7ff000000f00780c */
/* 0x000fe40003f05270 */
/*0b70*/ LOP3.LUT R19, R11, 0x80000000, R9, 0x48, !PT ; /* 0x800000000b137812 */
/* 0x000fe400078e4809 */
/*0b80*/ ISETP.EQ.OR P0, PT, R22, RZ, !P0 ; /* 0x000000ff1600720c */
/* 0x000fda0004702670 */
/*0b90*/ @P0 LOP3.LUT R2, R19, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000013020812 */
/* 0x000fe200078efcff */
/*0ba0*/ @!P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff128224 */
/* 0x000fe400078e00ff */
/*0bb0*/ @P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff120224 */
/* 0x000fe400078e00ff */
/*0bc0*/ @P0 IMAD.MOV.U32 R19, RZ, RZ, R2 ; /* 0x000000ffff130224 */
/* 0x000fe200078e0002 */
/*0bd0*/ BRA 0xc30 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0be0*/ LOP3.LUT R19, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000009137812 */
/* 0x001fe200078efcff */
/*0bf0*/ IMAD.MOV.U32 R18, RZ, RZ, R8 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0008 */
/*0c00*/ BRA 0xc30 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0c10*/ LOP3.LUT R19, R11, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000b137812 */
/* 0x001fe200078efcff */
/*0c20*/ IMAD.MOV.U32 R18, RZ, RZ, R10 ; /* 0x000000ffff127224 */
/* 0x000fe400078e000a */
/*0c30*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0c40*/ IMAD.MOV.U32 R13, RZ, RZ, 0x0 ; /* 0x00000000ff0d7424 */
/* 0x000fe400078e00ff */
/*0c50*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fc400078e0012 */
/*0c60*/ IMAD.MOV.U32 R7, RZ, RZ, R19 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0013 */
/*0c70*/ RET.REL.NODEC R12 0x0 ; /* 0xfffff3800c007950 */
/* 0x000fec0003c3ffff */
/*0c80*/ BRA 0xc80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "kernel.cuh"
void error(char const* str)
{
fprintf(stderr, "%s\n", str);
exit(1);
}
void cuda_check(cudaError_t err, char const* str)
{
if (err != cudaSuccess) {
fprintf(stderr, "%s: CUDA error %d (%s)\n",
str, err, cudaGetErrorString(err));
}
}
__global__ void fractal(int nrows, int ncols, int max_iter, double startX, double startY, double zoom, int* result) //373 - 326
{
int x_idx = threadIdx.x + blockIdx.x * blockDim.x;
int y_idx = threadIdx.y + blockIdx.y * blockDim.y;
if (x_idx >= ncols || y_idx >= nrows)
return;
int l = x_idx + y_idx * ncols;
double x = ((x_idx - ncols / 2) * zoom + startX) / ncols * 3.5 - 0.75;
double y = ((y_idx - nrows / 2) * zoom + startY) / nrows * 2.0;
double re = x, im = y;
for (int i = 1; i < max_iter; ++i)
{
if (re * re + im * im >= 4)
{
result[l] = i;
return;
}
double reTemp = re * re - im * im + x;
im = 2 * re * im + y;
re = reTemp;
}
result[l] = 0;
}
#if __DEBUG
__global__ void fractal_old(int nrows, int ncols, int* result) //398.86642 - 343.53
{
int x_idx = threadIdx.x + blockIdx.x * blockDim.x;
int y_idx = threadIdx.y + blockIdx.y * blockDim.y;
if (x_idx >= nrows || y_idx >= ncols)
return;
int l = x_idx * ncols + y_idx;
double x = (double)x_idx / nrows * 3.5 - 2.5;
double y = (double)y_idx / ncols * 2.0 - 1.0;
double re = x, im = y;
for (int i = 1; i < MAX_ITERATIONS; ++i)
{
if (re * re + im * im >= 4)
{
result[l] = i;
return;
}
double reTemp = re * re - im * im + x;
im = 2 * re * im + y;
re = reTemp;
}
result[l] = 0;
}
#endif
int* mendelbrot_kernel(int nrows, int ncols, int max_iter, double startX, double startY, double zoom)
{
cudaError_t err;
cudaEvent_t start, end;
int* d_result, * h_result;
size_t res_size = nrows * ncols * sizeof(int);
float time;
err = cudaMalloc(&d_result, res_size);
cuda_check(err, "cudaMalloc");
err = cudaMallocHost(&h_result, res_size);
cuda_check(err, "cudaMallocHost");
cudaEventCreate(&start);
cudaEventCreate(&end);
dim3 dimBlock(32, 32);
dim3 dimGrid((ncols + 31) / 32, (nrows + 31) / 32);
cudaEventRecord(start);
fractal << <dimGrid, dimBlock >> > (nrows, ncols, max_iter, startX, startY, zoom, d_result);
cudaEventRecord(end);
err = cudaMemcpy(h_result, d_result, res_size, cudaMemcpyDeviceToHost);
cuda_check(err, "cudaMalloc");
err = cudaEventSynchronize(end);
cuda_check(err, "sync");
cudaEventElapsedTime(&time, start, end);
//printf("Tempo passato = %f\n", time);
err = cudaFree(d_result);
cuda_check(err, "cudaFree");
return h_result;
}
#if __DEBUG
int main()
{
int* result = kernel_start(12000, 8000);
//int* result = kernel_start();
// for (int j = NCOLS - 1; j >= 0; --j)
// {
// for (int i = 0; i < NROWS; i++)
// {
// printf("%d ", result[i * NCOLS + j]);
// }
// printf("\n");
// }
// for (int j = 0; j < NROWS; ++j)
// {
// for (int i = 0; i < NCOLS; ++i)
// {
// printf("%d ", result[j * NCOLS + i]);
// }
// printf("\n");
// }
return 0;
}
#endif
|
.file "tmpxft_000f16a5_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s\n"
.text
.globl _Z5errorPKc
.type _Z5errorPKc, @function
_Z5errorPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rdi, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z5errorPKc, .-_Z5errorPKc
.section .rodata.str1.1
.LC1:
.string "%s: CUDA error %d (%s)\n"
.text
.globl _Z10cuda_check9cudaErrorPKc
.type _Z10cuda_check9cudaErrorPKc, @function
_Z10cuda_check9cudaErrorPKc:
.LFB2058:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L11
ret
.L11:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebx
movq %rsi, %rbp
call cudaGetErrorString@PLT
movq %rax, %r9
movl %ebx, %r8d
movq %rbp, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z10cuda_check9cudaErrorPKc, .-_Z10cuda_check9cudaErrorPKc
.globl _Z32__device_stub__Z7fractaliiidddPiiiidddPi
.type _Z32__device_stub__Z7fractaliiidddPiiiidddPi, @function
_Z32__device_stub__Z7fractaliiidddPiiiidddPi:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movsd %xmm0, 24(%rsp)
movsd %xmm1, 16(%rsp)
movsd %xmm2, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7fractaliiidddPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z32__device_stub__Z7fractaliiidddPiiiidddPi, .-_Z32__device_stub__Z7fractaliiidddPiiiidddPi
.globl _Z7fractaliiidddPi
.type _Z7fractaliiidddPi, @function
_Z7fractaliiidddPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z7fractaliiidddPiiiidddPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7fractaliiidddPi, .-_Z7fractaliiidddPi
.section .rodata.str1.1
.LC2:
.string "cudaMalloc"
.LC3:
.string "cudaMallocHost"
.LC4:
.string "sync"
.LC5:
.string "cudaFree"
.text
.globl _Z17mendelbrot_kerneliiiddd
.type _Z17mendelbrot_kerneliiiddd, @function
_Z17mendelbrot_kerneliiiddd:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $120, %rsp
.cfi_def_cfa_offset 160
movl %edi, %ebp
movl %esi, %r12d
movl %edx, %r13d
movsd %xmm0, 8(%rsp)
movsd %xmm1, 16(%rsp)
movsd %xmm2, 24(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl %edi, %ebx
imull %esi, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 64(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
leaq .LC2(%rip), %rsi
call _Z10cuda_check9cudaErrorPKc
leaq 72(%rsp), %rdi
movl $0, %edx
movq %rbx, %rsi
call cudaHostAlloc@PLT
movl %eax, %edi
leaq .LC3(%rip), %rsi
call _Z10cuda_check9cudaErrorPKc
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $32, 80(%rsp)
movl $32, 84(%rsp)
movl $1, 88(%rsp)
leal 62(%r12), %eax
movl %r12d, %edx
addl $31, %edx
cmovns %edx, %eax
sarl $5, %eax
movl %eax, 92(%rsp)
leal 62(%rbp), %eax
movl %ebp, %edx
addl $31, %edx
cmovns %edx, %eax
sarl $5, %eax
movl %eax, 96(%rsp)
movl $1, 100(%rsp)
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L21:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 64(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
leaq .LC2(%rip), %rsi
call _Z10cuda_check9cudaErrorPKc
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %edi
leaq .LC4(%rip), %rsi
call _Z10cuda_check9cudaErrorPKc
leaq 44(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
leaq .LC5(%rip), %rsi
call _Z10cuda_check9cudaErrorPKc
movq 72(%rsp), %rax
movq 104(%rsp), %rdx
subq %fs:40, %rdx
jne .L25
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq 64(%rsp), %rcx
movsd 24(%rsp), %xmm2
movsd 16(%rsp), %xmm1
movsd 8(%rsp), %xmm0
movl %r13d, %edx
movl %r12d, %esi
movl %ebp, %edi
call _Z32__device_stub__Z7fractaliiidddPiiiidddPi
jmp .L21
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z17mendelbrot_kerneliiiddd, .-_Z17mendelbrot_kerneliiiddd
.section .rodata.str1.1
.LC6:
.string "_Z7fractaliiidddPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z7fractaliiidddPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "kernel.cuh"
void error(char const* str)
{
fprintf(stderr, "%s\n", str);
exit(1);
}
void cuda_check(cudaError_t err, char const* str)
{
if (err != cudaSuccess) {
fprintf(stderr, "%s: CUDA error %d (%s)\n",
str, err, cudaGetErrorString(err));
}
}
__global__ void fractal(int nrows, int ncols, int max_iter, double startX, double startY, double zoom, int* result) //373 - 326
{
int x_idx = threadIdx.x + blockIdx.x * blockDim.x;
int y_idx = threadIdx.y + blockIdx.y * blockDim.y;
if (x_idx >= ncols || y_idx >= nrows)
return;
int l = x_idx + y_idx * ncols;
double x = ((x_idx - ncols / 2) * zoom + startX) / ncols * 3.5 - 0.75;
double y = ((y_idx - nrows / 2) * zoom + startY) / nrows * 2.0;
double re = x, im = y;
for (int i = 1; i < max_iter; ++i)
{
if (re * re + im * im >= 4)
{
result[l] = i;
return;
}
double reTemp = re * re - im * im + x;
im = 2 * re * im + y;
re = reTemp;
}
result[l] = 0;
}
#if __DEBUG
__global__ void fractal_old(int nrows, int ncols, int* result) //398.86642 - 343.53
{
int x_idx = threadIdx.x + blockIdx.x * blockDim.x;
int y_idx = threadIdx.y + blockIdx.y * blockDim.y;
if (x_idx >= nrows || y_idx >= ncols)
return;
int l = x_idx * ncols + y_idx;
double x = (double)x_idx / nrows * 3.5 - 2.5;
double y = (double)y_idx / ncols * 2.0 - 1.0;
double re = x, im = y;
for (int i = 1; i < MAX_ITERATIONS; ++i)
{
if (re * re + im * im >= 4)
{
result[l] = i;
return;
}
double reTemp = re * re - im * im + x;
im = 2 * re * im + y;
re = reTemp;
}
result[l] = 0;
}
#endif
int* mendelbrot_kernel(int nrows, int ncols, int max_iter, double startX, double startY, double zoom)
{
cudaError_t err;
cudaEvent_t start, end;
int* d_result, * h_result;
size_t res_size = nrows * ncols * sizeof(int);
float time;
err = cudaMalloc(&d_result, res_size);
cuda_check(err, "cudaMalloc");
err = cudaMallocHost(&h_result, res_size);
cuda_check(err, "cudaMallocHost");
cudaEventCreate(&start);
cudaEventCreate(&end);
dim3 dimBlock(32, 32);
dim3 dimGrid((ncols + 31) / 32, (nrows + 31) / 32);
cudaEventRecord(start);
fractal << <dimGrid, dimBlock >> > (nrows, ncols, max_iter, startX, startY, zoom, d_result);
cudaEventRecord(end);
err = cudaMemcpy(h_result, d_result, res_size, cudaMemcpyDeviceToHost);
cuda_check(err, "cudaMalloc");
err = cudaEventSynchronize(end);
cuda_check(err, "sync");
cudaEventElapsedTime(&time, start, end);
//printf("Tempo passato = %f\n", time);
err = cudaFree(d_result);
cuda_check(err, "cudaFree");
return h_result;
}
#if __DEBUG
int main()
{
int* result = kernel_start(12000, 8000);
//int* result = kernel_start();
// for (int j = NCOLS - 1; j >= 0; --j)
// {
// for (int i = 0; i < NROWS; i++)
// {
// printf("%d ", result[i * NCOLS + j]);
// }
// printf("\n");
// }
// for (int j = 0; j < NROWS; ++j)
// {
// for (int i = 0; i < NCOLS; ++i)
// {
// printf("%d ", result[j * NCOLS + i]);
// }
// printf("\n");
// }
return 0;
}
#endif
|
#ifndef __KERNEL_CUDA
#define __KERNEL_CUDA
#include <stdio.h>
#include <hip/hip_runtime.h>
////////////////////////////////////////////////////////////
///
/// Starts the CUDA kernel with the given inputs
///
/// \param nrows Number of rows (height)
/// \param ncols Number of columns (width)
/// \param max_iter Max number of iterations per pixel
/// \param startX Horizontal offset
/// \param startY Vertical offset
/// \param zoom Zoom coefficient
///
/// \return Array of size (nrows * ncols) containing the number of iteration per point if it is less than max_iter, 0 otherwise
///
////////////////////////////////////////////////////////////
int* mendelbrot_kernel(int nrows, int ncols, int max_iter, double startX, double startY, double zoom);
#endif // __KERNEL_PRO_
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#ifndef __KERNEL_CUDA
#define __KERNEL_CUDA
#include <stdio.h>
#include <hip/hip_runtime.h>
////////////////////////////////////////////////////////////
///
/// Starts the CUDA kernel with the given inputs
///
/// \param nrows Number of rows (height)
/// \param ncols Number of columns (width)
/// \param max_iter Max number of iterations per pixel
/// \param startX Horizontal offset
/// \param startY Vertical offset
/// \param zoom Zoom coefficient
///
/// \return Array of size (nrows * ncols) containing the number of iteration per point if it is less than max_iter, 0 otherwise
///
////////////////////////////////////////////////////////////
int* mendelbrot_kernel(int nrows, int ncols, int max_iter, double startX, double startY, double zoom);
#endif // __KERNEL_PRO_
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#ifndef __KERNEL_CUDA
#define __KERNEL_CUDA
#include <stdio.h>
#include <hip/hip_runtime.h>
////////////////////////////////////////////////////////////
///
/// Starts the CUDA kernel with the given inputs
///
/// \param nrows Number of rows (height)
/// \param ncols Number of columns (width)
/// \param max_iter Max number of iterations per pixel
/// \param startX Horizontal offset
/// \param startY Vertical offset
/// \param zoom Zoom coefficient
///
/// \return Array of size (nrows * ncols) containing the number of iteration per point if it is less than max_iter, 0 otherwise
///
////////////////////////////////////////////////////////////
int* mendelbrot_kernel(int nrows, int ncols, int max_iter, double startX, double startY, double zoom);
#endif // __KERNEL_PRO_
|
.text
.file "kernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z7fractaliiidddPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0030*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e680000002600 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x164], PT ; /* 0x0000590005007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R4, R4, c[0x0][0x4], R3 ; /* 0x0000010004047a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R4, c[0x0][0x160], P0 ; /* 0x0000580004007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ I2F.F64 R2, c[0x0][0x164] ; /* 0x0000590000027b12 */
/* 0x000e220000201c00 */
/*00b0*/ ULDC UR4, c[0x0][0x164] ; /* 0x0000590000047ab9 */
/* 0x000fe20000000800 */
/*00c0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*00d0*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fe2000f8f083f */
/*00e0*/ BSSY B0, 0x280 ; /* 0x0000019000007945 */
/* 0x000fe60003800000 */
/*00f0*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011404 */
/*0100*/ IADD3 R0, R5, -UR4, RZ ; /* 0x8000000405007c10 */
/* 0x000fe2000fffe0ff */
/*0110*/ MUFU.RCP64H R9, R3 ; /* 0x0000000300097308 */
/* 0x001e240000001800 */
/*0120*/ DFMA R6, -R2, R8, 1 ; /* 0x3ff000000206742b */
/* 0x001e0c0000000108 */
/*0130*/ DFMA R10, R6, R6, R6 ; /* 0x00000006060a722b */
/* 0x0010480000000006 */
/*0140*/ I2F.F64 R6, R0 ; /* 0x0000000000067312 */
/* 0x0010a40000201c00 */
/*0150*/ DFMA R10, R8, R10, R8 ; /* 0x0000000a080a722b */
/* 0x0022e40000000008 */
/*0160*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff087624 */
/* 0x002fe400078e00ff */
/*0170*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff097624 */
/* 0x000fe400078e00ff */
/*0180*/ DFMA R12, -R2, R10, 1 ; /* 0x3ff00000020c742b */
/* 0x008e62000000010a */
/*0190*/ IMAD R0, R4, c[0x0][0x164], R5 ; /* 0x0000590004007a24 */
/* 0x001fca00078e0205 */
/*01a0*/ DFMA R12, R10, R12, R10 ; /* 0x0000000c0a0c722b */
/* 0x002fc8000000000a */
/*01b0*/ DFMA R8, R6, R8, c[0x0][0x170] ; /* 0x00005c000608762b */
/* 0x004e0c0000000008 */
/*01c0*/ DMUL R6, R8, R12 ; /* 0x0000000c08067228 */
/* 0x001e080000000000 */
/*01d0*/ FSETP.GEU.AND P1, PT, |R9|, 6.5827683646048100446e-37, PT ; /* 0x036000000900780b */
/* 0x000fe40003f2e200 */
/*01e0*/ DFMA R10, -R2, R6, R8 ; /* 0x00000006020a722b */
/* 0x001e0c0000000108 */
/*01f0*/ DFMA R6, R12, R10, R6 ; /* 0x0000000a0c06722b */
/* 0x001e140000000006 */
/*0200*/ FFMA R10, RZ, R3, R7 ; /* 0x00000003ff0a7223 */
/* 0x001fca0000000007 */
/*0210*/ FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ; /* 0x001000000a00780b */
/* 0x000fda0003f04200 */
/*0220*/ @P0 BRA P1, 0x270 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*0230*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0008 */
/*0240*/ MOV R12, 0x270 ; /* 0x00000270000c7802 */
/* 0x000fe20000000f00 */
/*0250*/ IMAD.MOV.U32 R11, RZ, RZ, R9 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0009 */
/*0260*/ CALL.REL.NOINC 0x680 ; /* 0x0000041000007944 */
/* 0x000fea0003c00000 */
/*0270*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0280*/ I2F.F64 R2, c[0x0][0x160] ; /* 0x0000580000027b12 */
/* 0x000e220000201c00 */
/*0290*/ ULDC UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe20000000800 */
/*02a0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*02b0*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fe2000f8f083f */
/*02c0*/ BSSY B0, 0x4a0 ; /* 0x000001d000007945 */
/* 0x000fe60003800000 */
/*02d0*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011404 */
/*02e0*/ IADD3 R14, R4, -UR4, RZ ; /* 0x80000004040e7c10 */
/* 0x000fe2000fffe0ff */
/*02f0*/ MUFU.RCP64H R9, R3 ; /* 0x0000000300097308 */
/* 0x001e300000001800 */
/*0300*/ I2F.F64 R4, R14 ; /* 0x0000000e00047312 */
/* 0x000ea20000201c00 */
/*0310*/ DFMA R10, -R2, R8, 1 ; /* 0x3ff00000020a742b */
/* 0x001e0c0000000108 */
/*0320*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0330*/ DFMA R10, R8, R10, R8 ; /* 0x0000000a080a722b */
/* 0x0010e40000000008 */
/*0340*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff087624 */
/* 0x001fe400078e00ff */
/*0350*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff097624 */
/* 0x000fe400078e00ff */
/*0360*/ DFMA R12, -R2, R10, 1 ; /* 0x3ff00000020c742b */
/* 0x008e08000000010a */
/*0370*/ DFMA R8, R4, R8, c[0x0][0x178] ; /* 0x00005e000408762b */
/* 0x004fc80000000008 */
/*0380*/ DFMA R12, R10, R12, R10 ; /* 0x0000000c0a0c722b */
/* 0x001e0c000000000a */
/*0390*/ DMUL R4, R8, R12 ; /* 0x0000000c08047228 */
/* 0x001e220000000000 */
/*03a0*/ FSETP.GEU.AND P1, PT, |R9|, 6.5827683646048100446e-37, PT ; /* 0x036000000900780b */
/* 0x000fca0003f2e200 */
/*03b0*/ DFMA R10, -R2, R4, R8 ; /* 0x00000004020a722b */
/* 0x001e0c0000000108 */
/*03c0*/ DFMA R10, R12, R10, R4 ; /* 0x0000000a0c0a722b */
/* 0x0010a40000000004 */
/*03d0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff047424 */
/* 0x001fe400078e00ff */
/*03e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x400c0000 ; /* 0x400c0000ff057424 */
/* 0x000fcc00078e00ff */
/*03f0*/ FFMA R12, RZ, R3, R11 ; /* 0x00000003ff0c7223 */
/* 0x004fe2000000000b */
/*0400*/ DFMA R4, R6, R4, -0.75 ; /* 0xbfe800000604742b */
/* 0x0000880000000004 */
/*0410*/ FSETP.GT.AND P0, PT, |R12|, 1.469367938527859385e-39, PT ; /* 0x001000000c00780b */
/* 0x000fda0003f04200 */
/*0420*/ @P0 BRA P1, 0x490 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*0430*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a7224 */
/* 0x005fe200078e0008 */
/*0440*/ MOV R12, 0x470 ; /* 0x00000470000c7802 */
/* 0x000fe20000000f00 */
/*0450*/ IMAD.MOV.U32 R11, RZ, RZ, R9 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0009 */
/*0460*/ CALL.REL.NOINC 0x680 ; /* 0x0000021000007944 */
/* 0x002fea0003c00000 */
/*0470*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0006 */
/*0480*/ IMAD.MOV.U32 R11, RZ, RZ, R7 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0007 */
/*0490*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x005fea0003800000 */
/*04a0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*04b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*04c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*04d0*/ DADD R14, R10, R10 ; /* 0x000000000a0e7229 */
/* 0x0000a4000000000a */
/*04e0*/ ISETP.GE.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fe20003f06270 */
/*04f0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x188] ; /* 0x0000620000027625 */
/* 0x000fd800078e0203 */
/*0500*/ @!P0 BRA 0x630 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0510*/ BSSY B0, 0x660 ; /* 0x0000014000007945 */
/* 0x005fe20003800000 */
/*0520*/ IMAD.MOV.U32 R17, RZ, RZ, 0x1 ; /* 0x00000001ff117424 */
/* 0x002fe400078e00ff */
/*0530*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000e */
/*0540*/ IMAD.MOV.U32 R7, RZ, RZ, R15 ; /* 0x000000ffff077224 */
/* 0x000fe400078e000f */
/*0550*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0004 */
/*0560*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0005 */
/*0570*/ DMUL R10, R6, R6 ; /* 0x00000006060a7228 */
/* 0x000fc80000000000 */
/*0580*/ DMUL R12, R8, R8 ; /* 0x00000008080c7228 */
/* 0x000e0c0000000000 */
/*0590*/ DADD R18, R10, R12 ; /* 0x000000000a127229 */
/* 0x001e0c000000000c */
/*05a0*/ DSETP.GE.AND P0, PT, R18, 4, PT ; /* 0x401000001200742a */
/* 0x001e1c0003f06000 */
/*05b0*/ @P0 BRA 0x650 ; /* 0x0000009000000947 */
/* 0x001fea0003800000 */
/*05c0*/ IADD3 R17, R17, 0x1, RZ ; /* 0x0000000111117810 */
/* 0x000fe20007ffe0ff */
/*05d0*/ DADD R10, -R10, R12 ; /* 0x000000000a0a7229 */
/* 0x000e06000000010c */
/*05e0*/ ISETP.GE.AND P0, PT, R17, c[0x0][0x168], PT ; /* 0x00005a0011007a0c */
/* 0x000fe20003f06270 */
/*05f0*/ DADD R12, R8, R8 ; /* 0x00000000080c7229 */
/* 0x000e480000000008 */
/*0600*/ DADD R8, R4, R10 ; /* 0x0000000004087229 */
/* 0x001088000000000a */
/*0610*/ DFMA R6, R12, R6, R14 ; /* 0x000000060c06722b */
/* 0x002048000000000e */
/*0620*/ @!P0 BRA 0x570 ; /* 0xffffff4000008947 */
/* 0x007fea000383ffff */
/*0630*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x005fe2000c101904 */
/*0640*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0650*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0660*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x000fe2000c101904 */
/*0670*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0680*/ FSETP.GEU.AND P0, PT, |R3|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000300780b */
/* 0x040fe20003f0e200 */
/*0690*/ IMAD.MOV.U32 R8, RZ, RZ, R2.reuse ; /* 0x000000ffff087224 */
/* 0x100fe200078e0002 */
/*06a0*/ LOP3.LUT R6, R3, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff03067812 */
/* 0x000fe200078ec0ff */
/*06b0*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0003 */
/*06c0*/ FSETP.GEU.AND P2, PT, |R11|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000b00780b */
/* 0x040fe20003f4e200 */
/*06d0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0e7424 */
/* 0x000fe200078e00ff */
/*06e0*/ LOP3.LUT R7, R6, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000006077812 */
/* 0x000fe200078efcff */
/*06f0*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0002 */
/*0700*/ LOP3.LUT R13, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b0d7812 */
/* 0x000fe200078ec0ff */
/*0710*/ IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; /* 0x00000001ff127424 */
/* 0x000fe200078e00ff */
/*0720*/ LOP3.LUT R20, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003147812 */
/* 0x000fe200078ec0ff */
/*0730*/ BSSY B1, 0xc40 ; /* 0x0000050000017945 */
/* 0x000fe40003800000 */
/*0740*/ @!P0 DMUL R6, R8, 8.98846567431157953865e+307 ; /* 0x7fe0000008068828 */
/* 0x000e220000000000 */
/*0750*/ ISETP.GE.U32.AND P1, PT, R13, R20, PT ; /* 0x000000140d00720c */
/* 0x000fc60003f26070 */
/*0760*/ @!P2 LOP3.LUT R2, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000902a812 */
/* 0x000fe200078ec0ff */
/*0770*/ @!P2 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff10a224 */
/* 0x000fe200078e00ff */
/*0780*/ MUFU.RCP64H R19, R7 ; /* 0x0000000700137308 */
/* 0x001e220000001800 */
/*0790*/ SEL R3, R14.reuse, 0x63400000, !P1 ; /* 0x634000000e037807 */
/* 0x040fe40004800000 */
/*07a0*/ @!P2 ISETP.GE.U32.AND P3, PT, R13, R2, PT ; /* 0x000000020d00a20c */
/* 0x000fe20003f66070 */
/*07b0*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000a */
/*07c0*/ LOP3.LUT R3, R3, 0x800fffff, R11, 0xf8, !PT ; /* 0x800fffff03037812 */
/* 0x000fe400078ef80b */
/*07d0*/ @!P2 SEL R15, R14, 0x63400000, !P3 ; /* 0x634000000e0fa807 */
/* 0x000fc80005800000 */
/*07e0*/ @!P2 LOP3.LUT R15, R15, 0x80000000, R11, 0xf8, !PT ; /* 0x800000000f0fa812 */
/* 0x000fc800078ef80b */
/*07f0*/ @!P2 LOP3.LUT R17, R15, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000f11a812 */
/* 0x000fe200078efcff */
/*0800*/ DFMA R22, R18, -R6, 1 ; /* 0x3ff000001216742b */
/* 0x001e220000000806 */
/*0810*/ IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e000d */
/*0820*/ @!P2 DFMA R2, R2, 2, -R16 ; /* 0x400000000202a82b */
/* 0x000fc80000000810 */
/*0830*/ DFMA R22, R22, R22, R22 ; /* 0x000000161616722b */
/* 0x001e0c0000000016 */
/*0840*/ DFMA R18, R18, R22, R18 ; /* 0x000000161212722b */
/* 0x0010620000000012 */
/*0850*/ @!P2 LOP3.LUT R15, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000030fa812 */
/* 0x000fe200078ec0ff */
/*0860*/ IMAD.MOV.U32 R22, RZ, RZ, R20 ; /* 0x000000ffff167224 */
/* 0x001fe200078e0014 */
/*0870*/ @!P0 LOP3.LUT R22, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007168812 */
/* 0x000fe400078ec0ff */
/*0880*/ IADD3 R20, R15, -0x1, RZ ; /* 0xffffffff0f147810 */
/* 0x000fe20007ffe0ff */
/*0890*/ DFMA R16, R18, -R6, 1 ; /* 0x3ff000001210742b */
/* 0x002e220000000806 */
/*08a0*/ IADD3 R23, R22, -0x1, RZ ; /* 0xffffffff16177810 */
/* 0x000fe40007ffe0ff */
/*08b0*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fc60003f04070 */
/*08c0*/ DFMA R16, R18, R16, R18 ; /* 0x000000101210722b */
/* 0x001e220000000012 */
/*08d0*/ ISETP.GT.U32.OR P0, PT, R23, 0x7feffffe, P0 ; /* 0x7feffffe1700780c */
/* 0x000fca0000704470 */
/*08e0*/ DMUL R18, R16, R2 ; /* 0x0000000210127228 */
/* 0x001e0c0000000000 */
/*08f0*/ DFMA R20, R18, -R6, R2 ; /* 0x800000061214722b */
/* 0x001e0c0000000002 */
/*0900*/ DFMA R16, R16, R20, R18 ; /* 0x000000141010722b */
/* 0x0010620000000012 */
/*0910*/ @P0 BRA 0xae0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0920*/ LOP3.LUT R18, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009127812 */
/* 0x001fc800078ec0ff */
/*0930*/ ISETP.GE.U32.AND P0, PT, R13.reuse, R18, PT ; /* 0x000000120d00720c */
/* 0x040fe20003f06070 */
/*0940*/ IMAD.IADD R10, R13, 0x1, -R18 ; /* 0x000000010d0a7824 */
/* 0x000fc600078e0a12 */
/*0950*/ SEL R13, R14, 0x63400000, !P0 ; /* 0x634000000e0d7807 */
/* 0x000fe40004000000 */
/*0960*/ IMNMX R10, R10, -0x46a00000, !PT ; /* 0xb96000000a0a7817 */
/* 0x000fc80007800200 */
/*0970*/ IMNMX R10, R10, 0x46a00000, PT ; /* 0x46a000000a0a7817 */
/* 0x000fca0003800200 */
/*0980*/ IMAD.IADD R13, R10, 0x1, -R13 ; /* 0x000000010a0d7824 */
/* 0x000fe400078e0a0d */
/*0990*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fc600078e00ff */
/*09a0*/ IADD3 R11, R13, 0x7fe00000, RZ ; /* 0x7fe000000d0b7810 */
/* 0x000fcc0007ffe0ff */
/*09b0*/ DMUL R18, R16, R10 ; /* 0x0000000a10127228 */
/* 0x002e140000000000 */
/*09c0*/ FSETP.GTU.AND P0, PT, |R19|, 1.469367938527859385e-39, PT ; /* 0x001000001300780b */
/* 0x001fda0003f0c200 */
/*09d0*/ @P0 BRA 0xc30 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*09e0*/ DFMA R2, R16, -R6, R2 ; /* 0x800000061002722b */
/* 0x000e220000000002 */
/*09f0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fd200078e00ff */
/*0a00*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*0a10*/ LOP3.LUT R9, R3, 0x80000000, R9, 0x48, !PT ; /* 0x8000000003097812 */
/* 0x000fc800078e4809 */
/*0a20*/ LOP3.LUT R11, R9, R11, RZ, 0xfc, !PT ; /* 0x0000000b090b7212 */
/* 0x000fce00078efcff */
/*0a30*/ @!P0 BRA 0xc30 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0a40*/ IMAD.MOV R3, RZ, RZ, -R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0d */
/*0a50*/ DMUL.RP R10, R16, R10 ; /* 0x0000000a100a7228 */
/* 0x000e220000008000 */
/*0a60*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0a70*/ DFMA R2, R18, -R2, R16 ; /* 0x800000021202722b */
/* 0x000e460000000010 */
/*0a80*/ LOP3.LUT R9, R11, R9, RZ, 0x3c, !PT ; /* 0x000000090b097212 */
/* 0x001fc600078e3cff */
/*0a90*/ IADD3 R2, -R13, -0x43300000, RZ ; /* 0xbcd000000d027810 */
/* 0x002fc80007ffe1ff */
/*0aa0*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*0ab0*/ FSEL R18, R10, R18, !P0 ; /* 0x000000120a127208 */
/* 0x000fe40004000000 */
/*0ac0*/ FSEL R19, R9, R19, !P0 ; /* 0x0000001309137208 */
/* 0x000fe20004000000 */
/*0ad0*/ BRA 0xc30 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0ae0*/ DSETP.NAN.AND P0, PT, R10, R10, PT ; /* 0x0000000a0a00722a */
/* 0x000e9c0003f08000 */
/*0af0*/ @P0 BRA 0xc10 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0b00*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e9c0003f08000 */
/*0b10*/ @P0 BRA 0xbe0 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0b20*/ ISETP.NE.AND P0, PT, R15, R22, PT ; /* 0x000000160f00720c */
/* 0x000fe20003f05270 */
/*0b30*/ IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; /* 0x00000000ff127424 */
/* 0x001fe400078e00ff */
/*0b40*/ IMAD.MOV.U32 R19, RZ, RZ, -0x80000 ; /* 0xfff80000ff137424 */
/* 0x000fd400078e00ff */
/*0b50*/ @!P0 BRA 0xc30 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0b60*/ ISETP.NE.AND P0, PT, R15, 0x7ff00000, PT ; /* 0x7ff000000f00780c */
/* 0x000fe40003f05270 */
/*0b70*/ LOP3.LUT R19, R11, 0x80000000, R9, 0x48, !PT ; /* 0x800000000b137812 */
/* 0x000fe400078e4809 */
/*0b80*/ ISETP.EQ.OR P0, PT, R22, RZ, !P0 ; /* 0x000000ff1600720c */
/* 0x000fda0004702670 */
/*0b90*/ @P0 LOP3.LUT R2, R19, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000013020812 */
/* 0x000fe200078efcff */
/*0ba0*/ @!P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff128224 */
/* 0x000fe400078e00ff */
/*0bb0*/ @P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff120224 */
/* 0x000fe400078e00ff */
/*0bc0*/ @P0 IMAD.MOV.U32 R19, RZ, RZ, R2 ; /* 0x000000ffff130224 */
/* 0x000fe200078e0002 */
/*0bd0*/ BRA 0xc30 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0be0*/ LOP3.LUT R19, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000009137812 */
/* 0x001fe200078efcff */
/*0bf0*/ IMAD.MOV.U32 R18, RZ, RZ, R8 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0008 */
/*0c00*/ BRA 0xc30 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0c10*/ LOP3.LUT R19, R11, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000b137812 */
/* 0x001fe200078efcff */
/*0c20*/ IMAD.MOV.U32 R18, RZ, RZ, R10 ; /* 0x000000ffff127224 */
/* 0x000fe400078e000a */
/*0c30*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0c40*/ IMAD.MOV.U32 R13, RZ, RZ, 0x0 ; /* 0x00000000ff0d7424 */
/* 0x000fe400078e00ff */
/*0c50*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fc400078e0012 */
/*0c60*/ IMAD.MOV.U32 R7, RZ, RZ, R19 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0013 */
/*0c70*/ RET.REL.NODEC R12 0x0 ; /* 0xfffff3800c007950 */
/* 0x000fec0003c3ffff */
/*0c80*/ BRA 0xc80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000f16a5_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s\n"
.text
.globl _Z5errorPKc
.type _Z5errorPKc, @function
_Z5errorPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rdi, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z5errorPKc, .-_Z5errorPKc
.section .rodata.str1.1
.LC1:
.string "%s: CUDA error %d (%s)\n"
.text
.globl _Z10cuda_check9cudaErrorPKc
.type _Z10cuda_check9cudaErrorPKc, @function
_Z10cuda_check9cudaErrorPKc:
.LFB2058:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L11
ret
.L11:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebx
movq %rsi, %rbp
call cudaGetErrorString@PLT
movq %rax, %r9
movl %ebx, %r8d
movq %rbp, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z10cuda_check9cudaErrorPKc, .-_Z10cuda_check9cudaErrorPKc
.globl _Z32__device_stub__Z7fractaliiidddPiiiidddPi
.type _Z32__device_stub__Z7fractaliiidddPiiiidddPi, @function
_Z32__device_stub__Z7fractaliiidddPiiiidddPi:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movsd %xmm0, 24(%rsp)
movsd %xmm1, 16(%rsp)
movsd %xmm2, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7fractaliiidddPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z32__device_stub__Z7fractaliiidddPiiiidddPi, .-_Z32__device_stub__Z7fractaliiidddPiiiidddPi
.globl _Z7fractaliiidddPi
.type _Z7fractaliiidddPi, @function
_Z7fractaliiidddPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z7fractaliiidddPiiiidddPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7fractaliiidddPi, .-_Z7fractaliiidddPi
.section .rodata.str1.1
.LC2:
.string "cudaMalloc"
.LC3:
.string "cudaMallocHost"
.LC4:
.string "sync"
.LC5:
.string "cudaFree"
.text
.globl _Z17mendelbrot_kerneliiiddd
.type _Z17mendelbrot_kerneliiiddd, @function
_Z17mendelbrot_kerneliiiddd:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $120, %rsp
.cfi_def_cfa_offset 160
movl %edi, %ebp
movl %esi, %r12d
movl %edx, %r13d
movsd %xmm0, 8(%rsp)
movsd %xmm1, 16(%rsp)
movsd %xmm2, 24(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl %edi, %ebx
imull %esi, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 64(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
leaq .LC2(%rip), %rsi
call _Z10cuda_check9cudaErrorPKc
leaq 72(%rsp), %rdi
movl $0, %edx
movq %rbx, %rsi
call cudaHostAlloc@PLT
movl %eax, %edi
leaq .LC3(%rip), %rsi
call _Z10cuda_check9cudaErrorPKc
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $32, 80(%rsp)
movl $32, 84(%rsp)
movl $1, 88(%rsp)
leal 62(%r12), %eax
movl %r12d, %edx
addl $31, %edx
cmovns %edx, %eax
sarl $5, %eax
movl %eax, 92(%rsp)
leal 62(%rbp), %eax
movl %ebp, %edx
addl $31, %edx
cmovns %edx, %eax
sarl $5, %eax
movl %eax, 96(%rsp)
movl $1, 100(%rsp)
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L21:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 64(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
leaq .LC2(%rip), %rsi
call _Z10cuda_check9cudaErrorPKc
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %edi
leaq .LC4(%rip), %rsi
call _Z10cuda_check9cudaErrorPKc
leaq 44(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
leaq .LC5(%rip), %rsi
call _Z10cuda_check9cudaErrorPKc
movq 72(%rsp), %rax
movq 104(%rsp), %rdx
subq %fs:40, %rdx
jne .L25
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq 64(%rsp), %rcx
movsd 24(%rsp), %xmm2
movsd 16(%rsp), %xmm1
movsd 8(%rsp), %xmm0
movl %r13d, %edx
movl %r12d, %esi
movl %ebp, %edi
call _Z32__device_stub__Z7fractaliiidddPiiiidddPi
jmp .L21
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z17mendelbrot_kerneliiiddd, .-_Z17mendelbrot_kerneliiiddd
.section .rodata.str1.1
.LC6:
.string "_Z7fractaliiidddPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z7fractaliiidddPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "kernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
extern "C"
{
__global__ void Dstanh(const int lengthX, const double sf, const double *gradc, const double *fc, double *gradn)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthX)
{
gradn[i] += sf*gradc[i]*(1.0-(fc[i]/sf)*(fc[i]/sf));
}
}
}
|
code for sm_80
Function : Dstanh
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R8, R0, R3, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fcc00078e0203 */
/*0090*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0203 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee2000c1e1b00 */
/*00c0*/ MUFU.RCP64H R5, c[0x0][0x16c] ; /* 0x00005b0000057b08 */
/* 0x000e220000001800 */
/*00d0*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0a7624 */
/* 0x000fe200078e00ff */
/*00e0*/ BSSY B0, 0x210 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*00f0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff0b7624 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fcc00078e00ff */
/*0110*/ DFMA R6, R4, -R10, 1 ; /* 0x3ff000000406742b */
/* 0x001e0c000000080a */
/*0120*/ DFMA R6, R6, R6, R6 ; /* 0x000000060606722b */
/* 0x001e0c0000000006 */
/*0130*/ DFMA R6, R4, R6, R4 ; /* 0x000000060406722b */
/* 0x001e0c0000000004 */
/*0140*/ DFMA R4, R6, -R10, 1 ; /* 0x3ff000000604742b */
/* 0x001e0c000000080a */
/*0150*/ DFMA R4, R6, R4, R6 ; /* 0x000000040604722b */
/* 0x001e8c0000000006 */
/*0160*/ DMUL R6, R8, R4 ; /* 0x0000000408067228 */
/* 0x004e220000000000 */
/*0170*/ FSETP.GEU.AND P1, PT, |R9|, 6.5827683646048100446e-37, PT ; /* 0x036000000900780b */
/* 0x000fca0003f2e200 */
/*0180*/ DFMA R10, R6, -c[0x0][0x168], R8 ; /* 0x80005a00060a7a2b */
/* 0x001e080000000008 */
/*0190*/ DMUL R2, R2, c[0x0][0x168] ; /* 0x00005a0002027a28 */
/* 0x008fc80000000000 */
/*01a0*/ DFMA R4, R4, R10, R6 ; /* 0x0000000a0404722b */
/* 0x001e140000000006 */
/*01b0*/ FFMA R6, RZ, c[0x0][0x16c], R5 ; /* 0x00005b00ff067a23 */
/* 0x001fca0000000005 */
/*01c0*/ FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; /* 0x001000000600780b */
/* 0x000fda0003f04200 */
/*01d0*/ @P0 BRA P1, 0x200 ; /* 0x0000002000000947 */
/* 0x000fea0000800000 */
/*01e0*/ MOV R10, 0x200 ; /* 0x00000200000a7802 */
/* 0x000fe40000000f00 */
/*01f0*/ CALL.REL.NOINC 0x280 ; /* 0x0000008000007944 */
/* 0x000fea0003c00000 */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.WIDE R6, R0, R7, c[0x0][0x180] ; /* 0x0000600000067625 */
/* 0x000fca00078e0207 */
/*0230*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea2000c1e1b00 */
/*0240*/ DFMA R4, -R4, R4, 1 ; /* 0x3ff000000404742b */
/* 0x000e8c0000000104 */
/*0250*/ DFMA R2, R2, R4, R8 ; /* 0x000000040202722b */
/* 0x004e0e0000000008 */
/*0260*/ STG.E.64 [R6.64], R2 ; /* 0x0000000206007986 */
/* 0x001fe2000c101b04 */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff0b7624 */
/* 0x000fe200078e00ff */
/*0290*/ FSETP.GEU.AND P2, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f4e200 */
/*02a0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff137424 */
/* 0x000fe200078e00ff */
/*02b0*/ LOP3.LUT R21, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009157812 */
/* 0x000fe200078ec0ff */
/*02c0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; /* 0x00000001ff0c7424 */
/* 0x000fe200078e00ff */
/*02d0*/ FSETP.GEU.AND P0, PT, |R11|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000b00780b */
/* 0x040fe20003f0e200 */
/*02e0*/ BSSY B1, 0x830 ; /* 0x0000054000017945 */
/* 0x000fe20003800000 */
/*02f0*/ LOP3.LUT R4, R11.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff0b047812 */
/* 0x040fe200078ec0ff */
/*0300*/ IMAD.MOV.U32 R20, RZ, RZ, R21 ; /* 0x000000ffff147224 */
/* 0x000fe200078e0015 */
/*0310*/ LOP3.LUT R18, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b127812 */
/* 0x000fc400078ec0ff */
/*0320*/ LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000004057812 */
/* 0x000fe200078efcff */
/*0330*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0340*/ ISETP.GE.U32.AND P1, PT, R21, R18, PT ; /* 0x000000121500720c */
/* 0x000fe20003f26070 */
/*0350*/ IMAD.MOV.U32 R23, RZ, RZ, R18 ; /* 0x000000ffff177224 */
/* 0x000fc600078e0012 */
/*0360*/ SEL R19, R19, 0x63400000, !P1 ; /* 0x6340000013137807 */
/* 0x000fe20004800000 */
/*0370*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff068624 */
/* 0x000fe400078e00ff */
/*0380*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff078624 */
/* 0x000fe200078e00ff */
/*0390*/ @!P2 LOP3.LUT R14, R19, 0x80000000, R9, 0xf8, !PT ; /* 0x80000000130ea812 */
/* 0x000fc800078ef809 */
/*03a0*/ @!P2 LOP3.LUT R15, R14, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000e0fa812 */
/* 0x000fe200078efcff */
/*03b0*/ @!P0 DMUL R4, R6, 8.98846567431157953865e+307 ; /* 0x7fe0000006048828 */
/* 0x000e220000000000 */
/*03c0*/ @!P2 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0ea224 */
/* 0x000fca00078e00ff */
/*03d0*/ MUFU.RCP64H R13, R5 ; /* 0x00000005000d7308 */
/* 0x001e280000001800 */
/*03e0*/ @!P0 LOP3.LUT R23, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005178812 */
/* 0x000fc800078ec0ff */
/*03f0*/ IADD3 R22, R23, -0x1, RZ ; /* 0xffffffff17167810 */
/* 0x000fe20007ffe0ff */
/*0400*/ DFMA R6, R12, -R4, 1 ; /* 0x3ff000000c06742b */
/* 0x001e0c0000000804 */
/*0410*/ DFMA R16, R6, R6, R6 ; /* 0x000000060610722b */
/* 0x0010640000000006 */
/*0420*/ LOP3.LUT R7, R19, 0x800fffff, R9, 0xf8, !PT ; /* 0x800fffff13077812 */
/* 0x001fe200078ef809 */
/*0430*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fc600078e0008 */
/*0440*/ DFMA R12, R12, R16, R12 ; /* 0x000000100c0c722b */
/* 0x002e08000000000c */
/*0450*/ @!P2 DFMA R6, R6, 2, -R14 ; /* 0x400000000606a82b */
/* 0x000e48000000080e */
/*0460*/ DFMA R14, R12, -R4, 1 ; /* 0x3ff000000c0e742b */
/* 0x001e0c0000000804 */
/*0470*/ @!P2 LOP3.LUT R20, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000714a812 */
/* 0x002fe200078ec0ff */
/*0480*/ DFMA R12, R12, R14, R12 ; /* 0x0000000e0c0c722b */
/* 0x001e06000000000c */
/*0490*/ IADD3 R16, R20, -0x1, RZ ; /* 0xffffffff14107810 */
/* 0x000fc60007ffe0ff */
/*04a0*/ DMUL R14, R12, R6 ; /* 0x000000060c0e7228 */
/* 0x001e220000000000 */
/*04b0*/ ISETP.GT.U32.AND P0, PT, R16, 0x7feffffe, PT ; /* 0x7feffffe1000780c */
/* 0x000fc80003f04070 */
/*04c0*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fe20000704470 */
/*04d0*/ DFMA R16, R14, -R4, R6 ; /* 0x800000040e10722b */
/* 0x001e0c0000000006 */
/*04e0*/ DFMA R16, R12, R16, R14 ; /* 0x000000100c10722b */
/* 0x00104c000000000e */
/*04f0*/ @P0 BRA 0x6a0 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*0500*/ IMAD.IADD R18, R21, 0x1, -R18 ; /* 0x0000000115127824 */
/* 0x003fe400078e0a12 */
/*0510*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fc600078e00ff */
/*0520*/ IMNMX R18, R18, -0x46a00000, !PT ; /* 0xb960000012127817 */
/* 0x000fc80007800200 */
/*0530*/ IMNMX R18, R18, 0x46a00000, PT ; /* 0x46a0000012127817 */
/* 0x000fca0003800200 */
/*0540*/ IMAD.IADD R18, R18, 0x1, -R19 ; /* 0x0000000112127824 */
/* 0x000fca00078e0a13 */
/*0550*/ IADD3 R9, R18, 0x7fe00000, RZ ; /* 0x7fe0000012097810 */
/* 0x000fcc0007ffe0ff */
/*0560*/ DMUL R12, R16, R8 ; /* 0x00000008100c7228 */
/* 0x000e140000000000 */
/*0570*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x001fda0003f0c200 */
/*0580*/ @P0 BRA 0x820 ; /* 0x0000029000000947 */
/* 0x000fea0003800000 */
/*0590*/ DFMA R4, R16, -R4, R6 ; /* 0x800000041004722b */
/* 0x000e220000000006 */
/*05a0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fd200078e00ff */
/*05b0*/ FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720b */
/* 0x041fe40003f0d000 */
/*05c0*/ LOP3.LUT R4, R5, c[0x0][0x16c], RZ, 0x3c, !PT ; /* 0x00005b0005047a12 */
/* 0x000fc800078e3cff */
/*05d0*/ LOP3.LUT R7, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004077812 */
/* 0x000fc800078ec0ff */
/*05e0*/ LOP3.LUT R9, R7, R9, RZ, 0xfc, !PT ; /* 0x0000000907097212 */
/* 0x000fc600078efcff */
/*05f0*/ @!P0 BRA 0x820 ; /* 0x0000022000008947 */
/* 0x000fea0003800000 */
/*0600*/ IMAD.MOV R5, RZ, RZ, -R18 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a12 */
/*0610*/ DMUL.RP R8, R16, R8 ; /* 0x0000000810087228 */
/* 0x000e220000008000 */
/*0620*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fcc00078e00ff */
/*0630*/ DFMA R4, R12, -R4, R16 ; /* 0x800000040c04722b */
/* 0x000e460000000010 */
/*0640*/ LOP3.LUT R7, R9, R7, RZ, 0x3c, !PT ; /* 0x0000000709077212 */
/* 0x001fc600078e3cff */
/*0650*/ IADD3 R4, -R18, -0x43300000, RZ ; /* 0xbcd0000012047810 */
/* 0x002fc80007ffe1ff */
/*0660*/ FSETP.NEU.AND P0, PT, |R5|, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f0d200 */
/*0670*/ FSEL R12, R8, R12, !P0 ; /* 0x0000000c080c7208 */
/* 0x000fe40004000000 */
/*0680*/ FSEL R13, R7, R13, !P0 ; /* 0x0000000d070d7208 */
/* 0x000fe20004000000 */
/*0690*/ BRA 0x820 ; /* 0x0000018000007947 */
/* 0x000fea0003800000 */
/*06a0*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x003e1c0003f08000 */
/*06b0*/ @P0 BRA 0x800 ; /* 0x0000014000000947 */
/* 0x001fea0003800000 */
/*06c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe400078e00ff */
/*06d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fcc00078e00ff */
/*06e0*/ DSETP.NAN.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a000400762a */
/* 0x000e1c0003f08000 */
/*06f0*/ @P0 BRA 0x7d0 ; /* 0x000000d000000947 */
/* 0x001fea0003800000 */
/*0700*/ ISETP.NE.AND P0, PT, R20, R23, PT ; /* 0x000000171400720c */
/* 0x000fe20003f05270 */
/*0710*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*0720*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*0730*/ @!P0 BRA 0x820 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0740*/ ISETP.NE.AND P0, PT, R20, 0x7ff00000, PT ; /* 0x7ff000001400780c */
/* 0x000fe40003f05270 */
/*0750*/ LOP3.LUT R8, R9, c[0x0][0x16c], RZ, 0x3c, !PT ; /* 0x00005b0009087a12 */
/* 0x000fe400078e3cff */
/*0760*/ ISETP.EQ.OR P0, PT, R23, RZ, !P0 ; /* 0x000000ff1700720c */
/* 0x000fe40004702670 */
/*0770*/ LOP3.LUT R13, R8, 0x80000000, RZ, 0xc0, !PT ; /* 0x80000000080d7812 */
/* 0x000fd600078ec0ff */
/*0780*/ @P0 LOP3.LUT R4, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d040812 */
/* 0x000fe200078efcff */
/*0790*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*07a0*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*07b0*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R4 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0004 */
/*07c0*/ BRA 0x820 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*07d0*/ LOP3.LUT R13, R11, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000b0d7812 */
/* 0x000fe200078efcff */
/*07e0*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0c7624 */
/* 0x000fe200078e00ff */
/*07f0*/ BRA 0x820 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0800*/ LOP3.LUT R13, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000090d7812 */
/* 0x000fe200078efcff */
/*0810*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0008 */
/*0820*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0830*/ IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; /* 0x00000000ff0b7424 */
/* 0x000fe400078e00ff */
/*0840*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fc400078e000c */
/*0850*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000d */
/*0860*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff7900a007950 */
/* 0x000fec0003c3ffff */
/*0870*/ BRA 0x870; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
extern "C"
{
__global__ void Dstanh(const int lengthX, const double sf, const double *gradc, const double *fc, double *gradn)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthX)
{
gradn[i] += sf*gradc[i]*(1.0-(fc[i]/sf)*(fc[i]/sf));
}
}
}
|
.file "tmpxft_00193ff6_00000000-6_Dstanh.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z6DstanhidPKdS0_PdidPKdS0_Pd
.type _Z33__device_stub__Z6DstanhidPKdS0_PdidPKdS0_Pd, @function
_Z33__device_stub__Z6DstanhidPKdS0_PdidPKdS0_Pd:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 44(%rsp)
movsd %xmm0, 32(%rsp)
movq %rsi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq Dstanh(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z6DstanhidPKdS0_PdidPKdS0_Pd, .-_Z33__device_stub__Z6DstanhidPKdS0_PdidPKdS0_Pd
.globl Dstanh
.type Dstanh, @function
Dstanh:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z6DstanhidPKdS0_PdidPKdS0_Pd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size Dstanh, .-Dstanh
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Dstanh"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq Dstanh(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
extern "C"
{
__global__ void Dstanh(const int lengthX, const double sf, const double *gradc, const double *fc, double *gradn)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthX)
{
gradn[i] += sf*gradc[i]*(1.0-(fc[i]/sf)*(fc[i]/sf));
}
}
}
|
#include <hip/hip_runtime.h>
extern "C"
{
__global__ void Dstanh(const int lengthX, const double sf, const double *gradc, const double *fc, double *gradn)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthX)
{
gradn[i] += sf*gradc[i]*(1.0-(fc[i]/sf)*(fc[i]/sf));
}
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
extern "C"
{
__global__ void Dstanh(const int lengthX, const double sf, const double *gradc, const double *fc, double *gradn)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthX)
{
gradn[i] += sf*gradc[i]*(1.0-(fc[i]/sf)*(fc[i]/sf));
}
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected Dstanh
.globl Dstanh
.p2align 8
.type Dstanh,@function
Dstanh:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v8, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
v_add_co_u32 v0, vcc_lo, s6, v0
global_load_b64 v[8:9], v[8:9], off
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b64 v[12:13], v[0:1], off
s_waitcnt vmcnt(2)
v_div_scale_f64 v[4:5], null, s[0:1], s[0:1], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
v_div_scale_f64 v[10:11], vcc_lo, v[2:3], s[0:1], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[14:15], v[10:11], v[6:7]
v_fma_f64 v[4:5], -v[4:5], v[14:15], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[14:15]
v_div_fixup_f64 v[2:3], v[4:5], s[0:1], v[2:3]
s_waitcnt vmcnt(1)
v_mul_f64 v[4:5], v[8:9], s[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], -v[2:3], v[2:3], 1.0
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[4:5], v[2:3], v[12:13]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel Dstanh
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size Dstanh, .Lfunc_end0-Dstanh
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: Dstanh
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: Dstanh.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
extern "C"
{
__global__ void Dstanh(const int lengthX, const double sf, const double *gradc, const double *fc, double *gradn)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthX)
{
gradn[i] += sf*gradc[i]*(1.0-(fc[i]/sf)*(fc[i]/sf));
}
}
}
|
.text
.file "Dstanh.hip"
.globl __device_stub__Dstanh # -- Begin function __device_stub__Dstanh
.p2align 4, 0x90
.type __device_stub__Dstanh,@function
__device_stub__Dstanh: # @__device_stub__Dstanh
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movsd %xmm0, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $Dstanh, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size __device_stub__Dstanh, .Lfunc_end0-__device_stub__Dstanh
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $Dstanh, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type Dstanh,@object # @Dstanh
.section .rodata,"a",@progbits
.globl Dstanh
.p2align 3, 0x0
Dstanh:
.quad __device_stub__Dstanh
.size Dstanh, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "Dstanh"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__Dstanh
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym Dstanh
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : Dstanh
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R8, R0, R3, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fcc00078e0203 */
/*0090*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0203 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee2000c1e1b00 */
/*00c0*/ MUFU.RCP64H R5, c[0x0][0x16c] ; /* 0x00005b0000057b08 */
/* 0x000e220000001800 */
/*00d0*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0a7624 */
/* 0x000fe200078e00ff */
/*00e0*/ BSSY B0, 0x210 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*00f0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff0b7624 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fcc00078e00ff */
/*0110*/ DFMA R6, R4, -R10, 1 ; /* 0x3ff000000406742b */
/* 0x001e0c000000080a */
/*0120*/ DFMA R6, R6, R6, R6 ; /* 0x000000060606722b */
/* 0x001e0c0000000006 */
/*0130*/ DFMA R6, R4, R6, R4 ; /* 0x000000060406722b */
/* 0x001e0c0000000004 */
/*0140*/ DFMA R4, R6, -R10, 1 ; /* 0x3ff000000604742b */
/* 0x001e0c000000080a */
/*0150*/ DFMA R4, R6, R4, R6 ; /* 0x000000040604722b */
/* 0x001e8c0000000006 */
/*0160*/ DMUL R6, R8, R4 ; /* 0x0000000408067228 */
/* 0x004e220000000000 */
/*0170*/ FSETP.GEU.AND P1, PT, |R9|, 6.5827683646048100446e-37, PT ; /* 0x036000000900780b */
/* 0x000fca0003f2e200 */
/*0180*/ DFMA R10, R6, -c[0x0][0x168], R8 ; /* 0x80005a00060a7a2b */
/* 0x001e080000000008 */
/*0190*/ DMUL R2, R2, c[0x0][0x168] ; /* 0x00005a0002027a28 */
/* 0x008fc80000000000 */
/*01a0*/ DFMA R4, R4, R10, R6 ; /* 0x0000000a0404722b */
/* 0x001e140000000006 */
/*01b0*/ FFMA R6, RZ, c[0x0][0x16c], R5 ; /* 0x00005b00ff067a23 */
/* 0x001fca0000000005 */
/*01c0*/ FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; /* 0x001000000600780b */
/* 0x000fda0003f04200 */
/*01d0*/ @P0 BRA P1, 0x200 ; /* 0x0000002000000947 */
/* 0x000fea0000800000 */
/*01e0*/ MOV R10, 0x200 ; /* 0x00000200000a7802 */
/* 0x000fe40000000f00 */
/*01f0*/ CALL.REL.NOINC 0x280 ; /* 0x0000008000007944 */
/* 0x000fea0003c00000 */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.WIDE R6, R0, R7, c[0x0][0x180] ; /* 0x0000600000067625 */
/* 0x000fca00078e0207 */
/*0230*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea2000c1e1b00 */
/*0240*/ DFMA R4, -R4, R4, 1 ; /* 0x3ff000000404742b */
/* 0x000e8c0000000104 */
/*0250*/ DFMA R2, R2, R4, R8 ; /* 0x000000040202722b */
/* 0x004e0e0000000008 */
/*0260*/ STG.E.64 [R6.64], R2 ; /* 0x0000000206007986 */
/* 0x001fe2000c101b04 */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff0b7624 */
/* 0x000fe200078e00ff */
/*0290*/ FSETP.GEU.AND P2, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f4e200 */
/*02a0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff137424 */
/* 0x000fe200078e00ff */
/*02b0*/ LOP3.LUT R21, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009157812 */
/* 0x000fe200078ec0ff */
/*02c0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; /* 0x00000001ff0c7424 */
/* 0x000fe200078e00ff */
/*02d0*/ FSETP.GEU.AND P0, PT, |R11|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000b00780b */
/* 0x040fe20003f0e200 */
/*02e0*/ BSSY B1, 0x830 ; /* 0x0000054000017945 */
/* 0x000fe20003800000 */
/*02f0*/ LOP3.LUT R4, R11.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff0b047812 */
/* 0x040fe200078ec0ff */
/*0300*/ IMAD.MOV.U32 R20, RZ, RZ, R21 ; /* 0x000000ffff147224 */
/* 0x000fe200078e0015 */
/*0310*/ LOP3.LUT R18, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b127812 */
/* 0x000fc400078ec0ff */
/*0320*/ LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000004057812 */
/* 0x000fe200078efcff */
/*0330*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0340*/ ISETP.GE.U32.AND P1, PT, R21, R18, PT ; /* 0x000000121500720c */
/* 0x000fe20003f26070 */
/*0350*/ IMAD.MOV.U32 R23, RZ, RZ, R18 ; /* 0x000000ffff177224 */
/* 0x000fc600078e0012 */
/*0360*/ SEL R19, R19, 0x63400000, !P1 ; /* 0x6340000013137807 */
/* 0x000fe20004800000 */
/*0370*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff068624 */
/* 0x000fe400078e00ff */
/*0380*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff078624 */
/* 0x000fe200078e00ff */
/*0390*/ @!P2 LOP3.LUT R14, R19, 0x80000000, R9, 0xf8, !PT ; /* 0x80000000130ea812 */
/* 0x000fc800078ef809 */
/*03a0*/ @!P2 LOP3.LUT R15, R14, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000e0fa812 */
/* 0x000fe200078efcff */
/*03b0*/ @!P0 DMUL R4, R6, 8.98846567431157953865e+307 ; /* 0x7fe0000006048828 */
/* 0x000e220000000000 */
/*03c0*/ @!P2 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0ea224 */
/* 0x000fca00078e00ff */
/*03d0*/ MUFU.RCP64H R13, R5 ; /* 0x00000005000d7308 */
/* 0x001e280000001800 */
/*03e0*/ @!P0 LOP3.LUT R23, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005178812 */
/* 0x000fc800078ec0ff */
/*03f0*/ IADD3 R22, R23, -0x1, RZ ; /* 0xffffffff17167810 */
/* 0x000fe20007ffe0ff */
/*0400*/ DFMA R6, R12, -R4, 1 ; /* 0x3ff000000c06742b */
/* 0x001e0c0000000804 */
/*0410*/ DFMA R16, R6, R6, R6 ; /* 0x000000060610722b */
/* 0x0010640000000006 */
/*0420*/ LOP3.LUT R7, R19, 0x800fffff, R9, 0xf8, !PT ; /* 0x800fffff13077812 */
/* 0x001fe200078ef809 */
/*0430*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fc600078e0008 */
/*0440*/ DFMA R12, R12, R16, R12 ; /* 0x000000100c0c722b */
/* 0x002e08000000000c */
/*0450*/ @!P2 DFMA R6, R6, 2, -R14 ; /* 0x400000000606a82b */
/* 0x000e48000000080e */
/*0460*/ DFMA R14, R12, -R4, 1 ; /* 0x3ff000000c0e742b */
/* 0x001e0c0000000804 */
/*0470*/ @!P2 LOP3.LUT R20, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000714a812 */
/* 0x002fe200078ec0ff */
/*0480*/ DFMA R12, R12, R14, R12 ; /* 0x0000000e0c0c722b */
/* 0x001e06000000000c */
/*0490*/ IADD3 R16, R20, -0x1, RZ ; /* 0xffffffff14107810 */
/* 0x000fc60007ffe0ff */
/*04a0*/ DMUL R14, R12, R6 ; /* 0x000000060c0e7228 */
/* 0x001e220000000000 */
/*04b0*/ ISETP.GT.U32.AND P0, PT, R16, 0x7feffffe, PT ; /* 0x7feffffe1000780c */
/* 0x000fc80003f04070 */
/*04c0*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fe20000704470 */
/*04d0*/ DFMA R16, R14, -R4, R6 ; /* 0x800000040e10722b */
/* 0x001e0c0000000006 */
/*04e0*/ DFMA R16, R12, R16, R14 ; /* 0x000000100c10722b */
/* 0x00104c000000000e */
/*04f0*/ @P0 BRA 0x6a0 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*0500*/ IMAD.IADD R18, R21, 0x1, -R18 ; /* 0x0000000115127824 */
/* 0x003fe400078e0a12 */
/*0510*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fc600078e00ff */
/*0520*/ IMNMX R18, R18, -0x46a00000, !PT ; /* 0xb960000012127817 */
/* 0x000fc80007800200 */
/*0530*/ IMNMX R18, R18, 0x46a00000, PT ; /* 0x46a0000012127817 */
/* 0x000fca0003800200 */
/*0540*/ IMAD.IADD R18, R18, 0x1, -R19 ; /* 0x0000000112127824 */
/* 0x000fca00078e0a13 */
/*0550*/ IADD3 R9, R18, 0x7fe00000, RZ ; /* 0x7fe0000012097810 */
/* 0x000fcc0007ffe0ff */
/*0560*/ DMUL R12, R16, R8 ; /* 0x00000008100c7228 */
/* 0x000e140000000000 */
/*0570*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x001fda0003f0c200 */
/*0580*/ @P0 BRA 0x820 ; /* 0x0000029000000947 */
/* 0x000fea0003800000 */
/*0590*/ DFMA R4, R16, -R4, R6 ; /* 0x800000041004722b */
/* 0x000e220000000006 */
/*05a0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fd200078e00ff */
/*05b0*/ FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720b */
/* 0x041fe40003f0d000 */
/*05c0*/ LOP3.LUT R4, R5, c[0x0][0x16c], RZ, 0x3c, !PT ; /* 0x00005b0005047a12 */
/* 0x000fc800078e3cff */
/*05d0*/ LOP3.LUT R7, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004077812 */
/* 0x000fc800078ec0ff */
/*05e0*/ LOP3.LUT R9, R7, R9, RZ, 0xfc, !PT ; /* 0x0000000907097212 */
/* 0x000fc600078efcff */
/*05f0*/ @!P0 BRA 0x820 ; /* 0x0000022000008947 */
/* 0x000fea0003800000 */
/*0600*/ IMAD.MOV R5, RZ, RZ, -R18 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a12 */
/*0610*/ DMUL.RP R8, R16, R8 ; /* 0x0000000810087228 */
/* 0x000e220000008000 */
/*0620*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fcc00078e00ff */
/*0630*/ DFMA R4, R12, -R4, R16 ; /* 0x800000040c04722b */
/* 0x000e460000000010 */
/*0640*/ LOP3.LUT R7, R9, R7, RZ, 0x3c, !PT ; /* 0x0000000709077212 */
/* 0x001fc600078e3cff */
/*0650*/ IADD3 R4, -R18, -0x43300000, RZ ; /* 0xbcd0000012047810 */
/* 0x002fc80007ffe1ff */
/*0660*/ FSETP.NEU.AND P0, PT, |R5|, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f0d200 */
/*0670*/ FSEL R12, R8, R12, !P0 ; /* 0x0000000c080c7208 */
/* 0x000fe40004000000 */
/*0680*/ FSEL R13, R7, R13, !P0 ; /* 0x0000000d070d7208 */
/* 0x000fe20004000000 */
/*0690*/ BRA 0x820 ; /* 0x0000018000007947 */
/* 0x000fea0003800000 */
/*06a0*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x003e1c0003f08000 */
/*06b0*/ @P0 BRA 0x800 ; /* 0x0000014000000947 */
/* 0x001fea0003800000 */
/*06c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe400078e00ff */
/*06d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fcc00078e00ff */
/*06e0*/ DSETP.NAN.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a000400762a */
/* 0x000e1c0003f08000 */
/*06f0*/ @P0 BRA 0x7d0 ; /* 0x000000d000000947 */
/* 0x001fea0003800000 */
/*0700*/ ISETP.NE.AND P0, PT, R20, R23, PT ; /* 0x000000171400720c */
/* 0x000fe20003f05270 */
/*0710*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*0720*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*0730*/ @!P0 BRA 0x820 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0740*/ ISETP.NE.AND P0, PT, R20, 0x7ff00000, PT ; /* 0x7ff000001400780c */
/* 0x000fe40003f05270 */
/*0750*/ LOP3.LUT R8, R9, c[0x0][0x16c], RZ, 0x3c, !PT ; /* 0x00005b0009087a12 */
/* 0x000fe400078e3cff */
/*0760*/ ISETP.EQ.OR P0, PT, R23, RZ, !P0 ; /* 0x000000ff1700720c */
/* 0x000fe40004702670 */
/*0770*/ LOP3.LUT R13, R8, 0x80000000, RZ, 0xc0, !PT ; /* 0x80000000080d7812 */
/* 0x000fd600078ec0ff */
/*0780*/ @P0 LOP3.LUT R4, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d040812 */
/* 0x000fe200078efcff */
/*0790*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*07a0*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*07b0*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R4 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0004 */
/*07c0*/ BRA 0x820 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*07d0*/ LOP3.LUT R13, R11, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000b0d7812 */
/* 0x000fe200078efcff */
/*07e0*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0c7624 */
/* 0x000fe200078e00ff */
/*07f0*/ BRA 0x820 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0800*/ LOP3.LUT R13, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000090d7812 */
/* 0x000fe200078efcff */
/*0810*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0008 */
/*0820*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0830*/ IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; /* 0x00000000ff0b7424 */
/* 0x000fe400078e00ff */
/*0840*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fc400078e000c */
/*0850*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000d */
/*0860*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff7900a007950 */
/* 0x000fec0003c3ffff */
/*0870*/ BRA 0x870; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected Dstanh
.globl Dstanh
.p2align 8
.type Dstanh,@function
Dstanh:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v8, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
v_add_co_u32 v0, vcc_lo, s6, v0
global_load_b64 v[8:9], v[8:9], off
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b64 v[12:13], v[0:1], off
s_waitcnt vmcnt(2)
v_div_scale_f64 v[4:5], null, s[0:1], s[0:1], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
v_div_scale_f64 v[10:11], vcc_lo, v[2:3], s[0:1], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[14:15], v[10:11], v[6:7]
v_fma_f64 v[4:5], -v[4:5], v[14:15], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[14:15]
v_div_fixup_f64 v[2:3], v[4:5], s[0:1], v[2:3]
s_waitcnt vmcnt(1)
v_mul_f64 v[4:5], v[8:9], s[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], -v[2:3], v[2:3], 1.0
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[4:5], v[2:3], v[12:13]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel Dstanh
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size Dstanh, .Lfunc_end0-Dstanh
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: Dstanh
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: Dstanh.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00193ff6_00000000-6_Dstanh.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z6DstanhidPKdS0_PdidPKdS0_Pd
.type _Z33__device_stub__Z6DstanhidPKdS0_PdidPKdS0_Pd, @function
_Z33__device_stub__Z6DstanhidPKdS0_PdidPKdS0_Pd:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 44(%rsp)
movsd %xmm0, 32(%rsp)
movq %rsi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq Dstanh(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z6DstanhidPKdS0_PdidPKdS0_Pd, .-_Z33__device_stub__Z6DstanhidPKdS0_PdidPKdS0_Pd
.globl Dstanh
.type Dstanh, @function
Dstanh:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z6DstanhidPKdS0_PdidPKdS0_Pd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size Dstanh, .-Dstanh
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Dstanh"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq Dstanh(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "Dstanh.hip"
.globl __device_stub__Dstanh # -- Begin function __device_stub__Dstanh
.p2align 4, 0x90
.type __device_stub__Dstanh,@function
__device_stub__Dstanh: # @__device_stub__Dstanh
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movsd %xmm0, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $Dstanh, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size __device_stub__Dstanh, .Lfunc_end0-__device_stub__Dstanh
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $Dstanh, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type Dstanh,@object # @Dstanh
.section .rodata,"a",@progbits
.globl Dstanh
.p2align 3, 0x0
Dstanh:
.quad __device_stub__Dstanh
.size Dstanh, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "Dstanh"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__Dstanh
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym Dstanh
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <cuda.h>
#include <sys/time.h>
#include <chrono>
#define BLOCK_COUNT 256u
#define HALF_BLOCK_COUNT 128u
#define BANKS 16
#define LOG_2_BANKS 4
// macro used for computing
// Bank-Conflict-Free Shared Memory Array Indices
#define AVOID_BANK_CONFLICTS(idx) ((idx) >> BANKS + (idx) >> (LOG_2_BANKS << 1))
#define CSC(call) do { \
cudaError_t res = call; \
if (res != cudaSuccess) { \
fprintf(stderr, "CUDA Error in %s:%d: %s\n", __FILE__, __LINE__, cudaGetErrorString(res)); \
exit(0); \
} \
} while (0)
__global__ void Histogram(unsigned char* data, int size, int* histo)
{
// выделяем разделяемую память, объем памяти равен количеству корзинок
__shared__ int tmp[BLOCK_COUNT];
// вычисляем абсолютный идентификатор
int idx = blockDim.x * blockIdx.x + threadIdx.x;
// смещение
int offset = gridDim.x * blockDim.x;
// заполним временный массив нулем,
// фактически заполняем 256 элементов как 0 в общей памяти
tmp[threadIdx.x] = 0;
__syncthreads(); // потоки ожидают выполнения заполнения нулем tmp
// перебираем все элементы буфера data,
// пока абс идентификатор не коснется значения size
while (idx < size)
{
// извлекаем значение, находящееся в буфере
// и увеличиваем счетчик в массиве разделяемой памяти
atomicAdd(&tmp[data[idx]], 1);
idx += offset; // увеличение абс идентиф по смещение
}
__syncthreads(); // ждем все потоки
// обновляем окончательный результат в массиве histo
int i = threadIdx.x;
while (i < BLOCK_COUNT)
{
atomicAdd(&histo[i], tmp[i]);
i += blockDim.x;
}
}
__global__ void Scan(int* histo, int* prefixSum)
{
__shared__ int tmp[BLOCK_COUNT];
int threadId = threadIdx.x;
int offset = 1;
int aIdx = threadIdx.x;
int bIdx = threadIdx.x + HALF_BLOCK_COUNT;
int bankOffsetA = AVOID_BANK_CONFLICTS(aIdx);
int bankOffsetB = AVOID_BANK_CONFLICTS(bIdx);
// загружаем данные из гистограммы в общую память
tmp[aIdx + bankOffsetA] = histo[aIdx];
tmp[bIdx + bankOffsetB] = histo[bIdx];
// строим сумму на месте вверх по дереву
{
int lvl = BLOCK_COUNT >> 1;
while (lvl > 0)
{
__syncthreads();
if (threadId < lvl)
{
int aIndex = (offset * (threadId * 2 + 1) - 1);
int bIndex = (offset * (threadId * 2 + 2) - 1);
aIndex += AVOID_BANK_CONFLICTS(aIndex);
bIndex += AVOID_BANK_CONFLICTS(bIndex);
tmp[bIndex] += tmp[aIndex];
}
offset <<= 1;
lvl >>= 1;
}
}
// очищаем последний элемент
if (threadId == 0)
{
tmp[BLOCK_COUNT - 1 + AVOID_BANK_CONFLICTS(BLOCK_COUNT - 1)] = 0;
}
// идем вниз по "дереву" и строим сканирование
{
int lvl = 1;
while (lvl < BLOCK_COUNT)
{
offset >>= 1;
__syncthreads();
if (threadId < lvl)
{
int aIndex = (offset * (threadId * 2 + 1) - 1);
int bIndex = (offset * (threadId * 2 + 2) - 1);
aIndex += AVOID_BANK_CONFLICTS(aIndex);
bIndex += AVOID_BANK_CONFLICTS(bIndex);
int temp = tmp[aIndex];
tmp[aIndex] = tmp[bIndex];
tmp[bIndex] += temp;
}
lvl <<= 1;
}
}
__syncthreads();
// записываем результаты в массив prefixSum
prefixSum[aIdx] = histo[aIdx] + tmp[aIdx + bankOffsetA];
prefixSum[bIdx] = histo[bIdx] + tmp[bIdx + bankOffsetB];
}
__global__ void CountSort(unsigned char* data, int* prefixSum, unsigned char* result, int size)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int offset = gridDim.x * blockDim.x;
int i = idx, j;
while (i < size)
{
// j = prefixSum[i] - 1;
// bound = i ? prefixSum[i - 1] : 0;
// while (j >= bound)
// {
// data[j] = i;
// --j;
// }
j = atomicSub(&prefixSum[data[i]], 1) - 1;
result[j] = data[i];
i += offset;
}
}
int main()
{
int size;
freopen(NULL, "rb", stdin);
fread(&size, sizeof(int), 1, stdin);
unsigned char* data = new unsigned char[size];
fread(data, sizeof(unsigned char), size, stdin);
fclose(stdin);
unsigned char* deviceData;
unsigned char* deviceResult;
int* deviceHisto;
int* devicePrefix;
float elapsedTime;
cudaEvent_t start, stop;
CSC(cudaEventCreate(&start));
CSC(cudaEventCreate(&stop));
CSC(cudaMalloc((void**)&deviceData, sizeof(unsigned char) * size));
CSC(cudaMemcpy(deviceData, data, sizeof(unsigned char) * size, cudaMemcpyHostToDevice));
CSC(cudaMalloc((void**)&deviceHisto, sizeof(int) * BLOCK_COUNT));
CSC(cudaMalloc((void**)&devicePrefix, sizeof(int) * BLOCK_COUNT));
CSC(cudaMemset(deviceHisto, 0, sizeof(int) * BLOCK_COUNT));
CSC(cudaMalloc((void**)&deviceResult, sizeof(unsigned char) * size));
CSC(cudaEventRecord(start));
Histogram<<<BLOCK_COUNT, BLOCK_COUNT>>>(deviceData, size, deviceHisto);
cudaThreadSynchronize(); // wait end
CSC(cudaGetLastError());
Scan<<<1, HALF_BLOCK_COUNT>>>(deviceHisto, devicePrefix);
cudaThreadSynchronize(); // wait end
CSC(cudaGetLastError());
CountSort<<<1, BLOCK_COUNT>>>(deviceData, devicePrefix, deviceResult, size);
cudaThreadSynchronize(); // wait end
CSC(cudaGetLastError());
CSC(cudaEventRecord(stop));
CSC(cudaEventSynchronize(stop));
CSC(cudaEventElapsedTime(&elapsedTime, start, stop));
CSC(cudaEventDestroy(start));
CSC(cudaEventDestroy(stop));
printf("Time : %f ms \n", elapsedTime);
CSC(cudaMemcpy(data, deviceResult, sizeof(unsigned char) * size, cudaMemcpyDeviceToHost));
// freopen(NULL, "wb", stdout);
// fwrite(data, sizeof(unsigned char), size, stdout);
// fclose(stdout);
CSC(cudaFree(deviceData));
CSC(cudaFree(deviceHisto));
CSC(cudaFree(devicePrefix));
delete[] data;
return 0;
}
|
.file "tmpxft_0007fcd3_00000000-6_lab5_time.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3771:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3771:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9HistogramPhiPiPhiPi
.type _Z31__device_stub__Z9HistogramPhiPiPhiPi, @function
_Z31__device_stub__Z9HistogramPhiPiPhiPi:
.LFB3793:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9HistogramPhiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3793:
.size _Z31__device_stub__Z9HistogramPhiPiPhiPi, .-_Z31__device_stub__Z9HistogramPhiPiPhiPi
.globl _Z9HistogramPhiPi
.type _Z9HistogramPhiPi, @function
_Z9HistogramPhiPi:
.LFB3794:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9HistogramPhiPiPhiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3794:
.size _Z9HistogramPhiPi, .-_Z9HistogramPhiPi
.globl _Z25__device_stub__Z4ScanPiS_PiS_
.type _Z25__device_stub__Z4ScanPiS_PiS_, @function
_Z25__device_stub__Z4ScanPiS_PiS_:
.LFB3795:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4ScanPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3795:
.size _Z25__device_stub__Z4ScanPiS_PiS_, .-_Z25__device_stub__Z4ScanPiS_PiS_
.globl _Z4ScanPiS_
.type _Z4ScanPiS_, @function
_Z4ScanPiS_:
.LFB3796:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z4ScanPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3796:
.size _Z4ScanPiS_, .-_Z4ScanPiS_
.globl _Z33__device_stub__Z9CountSortPhPiS_iPhPiS_i
.type _Z33__device_stub__Z9CountSortPhPiS_iPhPiS_i, @function
_Z33__device_stub__Z9CountSortPhPiS_iPhPiS_i:
.LFB3797:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9CountSortPhPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3797:
.size _Z33__device_stub__Z9CountSortPhPiS_iPhPiS_i, .-_Z33__device_stub__Z9CountSortPhPiS_iPhPiS_i
.globl _Z9CountSortPhPiS_i
.type _Z9CountSortPhPiS_i, @function
_Z9CountSortPhPiS_i:
.LFB3798:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9CountSortPhPiS_iPhPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3798:
.size _Z9CountSortPhPiS_i, .-_Z9CountSortPhPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "rb"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/lveltman/PGP/master/lab5/lab5_time.cu"
.section .rodata.str1.1
.LC2:
.string "CUDA Error in %s:%d: %s\n"
.LC3:
.string "Time : %f ms \n"
.text
.globl main
.type main, @function
main:
.LFB3768:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $104, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq stdin(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $0, %edi
call freopen@PLT
leaq 12(%rsp), %rdi
movq stdin(%rip), %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movslq 12(%rsp), %rbp
movq %rbp, %rdi
call _Znam@PLT
movq %rax, %rbx
movslq 12(%rsp), %rcx
movq stdin(%rip), %r8
movl $1, %edx
movq %rbp, %rsi
movq %rax, %rdi
call __fread_chk@PLT
movq stdin(%rip), %rdi
call fclose@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
je .L28
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $179, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L28:
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
je .L29
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $180, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L29:
movslq 12(%rsp), %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
je .L30
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $182, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L30:
movslq 12(%rsp), %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L31
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $183, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L31:
leaq 32(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
testl %eax, %eax
je .L32
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $185, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L32:
leaq 40(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
testl %eax, %eax
je .L33
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $186, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L33:
movl $1024, %edx
movl $0, %esi
movq 32(%rsp), %rdi
call cudaMemset@PLT
testl %eax, %eax
je .L34
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $187, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L34:
movslq 12(%rsp), %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
je .L35
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $189, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L35:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
testl %eax, %eax
je .L36
call cudaGetErrorString@PLT
movq %rax, %r9
movl $191, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L36:
movl $256, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $256, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L37:
call cudaThreadSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
je .L38
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $195, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L54:
movq 32(%rsp), %rdx
movl 12(%rsp), %esi
movq 16(%rsp), %rdi
call _Z31__device_stub__Z9HistogramPhiPiPhiPi
jmp .L37
.L38:
movl $128, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L39:
call cudaThreadSynchronize@PLT
call cudaGetLastError@PLT
movl %eax, %edi
testl %eax, %eax
je .L40
call cudaGetErrorString@PLT
movq %rax, %r9
movl $199, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L55:
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z25__device_stub__Z4ScanPiS_PiS_
jmp .L39
.L40:
movl $256, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L56
.L41:
call cudaThreadSynchronize@PLT
call cudaGetLastError@PLT
movl %eax, %edi
testl %eax, %eax
je .L42
call cudaGetErrorString@PLT
movq %rax, %r9
movl $203, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L56:
movl 12(%rsp), %ecx
movq 24(%rsp), %rdx
movq 40(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z33__device_stub__Z9CountSortPhPiS_iPhPiS_i
jmp .L41
.L42:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
testl %eax, %eax
je .L43
call cudaGetErrorString@PLT
movq %rax, %r9
movl $205, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L43:
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %edi
testl %eax, %eax
je .L44
call cudaGetErrorString@PLT
movq %rax, %r9
movl $206, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L44:
leaq 76(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %edi
testl %eax, %eax
je .L45
call cudaGetErrorString@PLT
movq %rax, %r9
movl $208, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L45:
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movl %eax, %edi
testl %eax, %eax
je .L46
call cudaGetErrorString@PLT
movq %rax, %r9
movl $209, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L46:
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movl %eax, %edi
testl %eax, %eax
je .L47
call cudaGetErrorString@PLT
movq %rax, %r9
movl $210, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L47:
pxor %xmm0, %xmm0
cvtss2sd 76(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq 12(%rsp), %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
testl %eax, %eax
je .L48
call cudaGetErrorString@PLT
movq %rax, %r9
movl $213, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L48:
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
testl %eax, %eax
je .L49
call cudaGetErrorString@PLT
movq %rax, %r9
movl $219, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L49:
movq 32(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
testl %eax, %eax
je .L50
call cudaGetErrorString@PLT
movq %rax, %r9
movl $220, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L50:
movq 40(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
testl %eax, %eax
jne .L57
movq %rbx, %rdi
call _ZdaPv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L58
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
call cudaGetErrorString@PLT
movq %rax, %r9
movl $221, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L58:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3768:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z9CountSortPhPiS_i"
.LC5:
.string "_Z4ScanPiS_"
.LC6:
.string "_Z9HistogramPhiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3800:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z9CountSortPhPiS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z4ScanPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z9HistogramPhiPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3800:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <cuda.h>
#include <sys/time.h>
#include <chrono>
#define BLOCK_COUNT 256u
#define HALF_BLOCK_COUNT 128u
#define BANKS 16
#define LOG_2_BANKS 4
// macro used for computing
// Bank-Conflict-Free Shared Memory Array Indices
#define AVOID_BANK_CONFLICTS(idx) ((idx) >> BANKS + (idx) >> (LOG_2_BANKS << 1))
#define CSC(call) do { \
cudaError_t res = call; \
if (res != cudaSuccess) { \
fprintf(stderr, "CUDA Error in %s:%d: %s\n", __FILE__, __LINE__, cudaGetErrorString(res)); \
exit(0); \
} \
} while (0)
__global__ void Histogram(unsigned char* data, int size, int* histo)
{
// выделяем разделяемую память, объем памяти равен количеству корзинок
__shared__ int tmp[BLOCK_COUNT];
// вычисляем абсолютный идентификатор
int idx = blockDim.x * blockIdx.x + threadIdx.x;
// смещение
int offset = gridDim.x * blockDim.x;
// заполним временный массив нулем,
// фактически заполняем 256 элементов как 0 в общей памяти
tmp[threadIdx.x] = 0;
__syncthreads(); // потоки ожидают выполнения заполнения нулем tmp
// перебираем все элементы буфера data,
// пока абс идентификатор не коснется значения size
while (idx < size)
{
// извлекаем значение, находящееся в буфере
// и увеличиваем счетчик в массиве разделяемой памяти
atomicAdd(&tmp[data[idx]], 1);
idx += offset; // увеличение абс идентиф по смещение
}
__syncthreads(); // ждем все потоки
// обновляем окончательный результат в массиве histo
int i = threadIdx.x;
while (i < BLOCK_COUNT)
{
atomicAdd(&histo[i], tmp[i]);
i += blockDim.x;
}
}
__global__ void Scan(int* histo, int* prefixSum)
{
__shared__ int tmp[BLOCK_COUNT];
int threadId = threadIdx.x;
int offset = 1;
int aIdx = threadIdx.x;
int bIdx = threadIdx.x + HALF_BLOCK_COUNT;
int bankOffsetA = AVOID_BANK_CONFLICTS(aIdx);
int bankOffsetB = AVOID_BANK_CONFLICTS(bIdx);
// загружаем данные из гистограммы в общую память
tmp[aIdx + bankOffsetA] = histo[aIdx];
tmp[bIdx + bankOffsetB] = histo[bIdx];
// строим сумму на месте вверх по дереву
{
int lvl = BLOCK_COUNT >> 1;
while (lvl > 0)
{
__syncthreads();
if (threadId < lvl)
{
int aIndex = (offset * (threadId * 2 + 1) - 1);
int bIndex = (offset * (threadId * 2 + 2) - 1);
aIndex += AVOID_BANK_CONFLICTS(aIndex);
bIndex += AVOID_BANK_CONFLICTS(bIndex);
tmp[bIndex] += tmp[aIndex];
}
offset <<= 1;
lvl >>= 1;
}
}
// очищаем последний элемент
if (threadId == 0)
{
tmp[BLOCK_COUNT - 1 + AVOID_BANK_CONFLICTS(BLOCK_COUNT - 1)] = 0;
}
// идем вниз по "дереву" и строим сканирование
{
int lvl = 1;
while (lvl < BLOCK_COUNT)
{
offset >>= 1;
__syncthreads();
if (threadId < lvl)
{
int aIndex = (offset * (threadId * 2 + 1) - 1);
int bIndex = (offset * (threadId * 2 + 2) - 1);
aIndex += AVOID_BANK_CONFLICTS(aIndex);
bIndex += AVOID_BANK_CONFLICTS(bIndex);
int temp = tmp[aIndex];
tmp[aIndex] = tmp[bIndex];
tmp[bIndex] += temp;
}
lvl <<= 1;
}
}
__syncthreads();
// записываем результаты в массив prefixSum
prefixSum[aIdx] = histo[aIdx] + tmp[aIdx + bankOffsetA];
prefixSum[bIdx] = histo[bIdx] + tmp[bIdx + bankOffsetB];
}
__global__ void CountSort(unsigned char* data, int* prefixSum, unsigned char* result, int size)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int offset = gridDim.x * blockDim.x;
int i = idx, j;
while (i < size)
{
// j = prefixSum[i] - 1;
// bound = i ? prefixSum[i - 1] : 0;
// while (j >= bound)
// {
// data[j] = i;
// --j;
// }
j = atomicSub(&prefixSum[data[i]], 1) - 1;
result[j] = data[i];
i += offset;
}
}
int main()
{
int size;
freopen(NULL, "rb", stdin);
fread(&size, sizeof(int), 1, stdin);
unsigned char* data = new unsigned char[size];
fread(data, sizeof(unsigned char), size, stdin);
fclose(stdin);
unsigned char* deviceData;
unsigned char* deviceResult;
int* deviceHisto;
int* devicePrefix;
float elapsedTime;
cudaEvent_t start, stop;
CSC(cudaEventCreate(&start));
CSC(cudaEventCreate(&stop));
CSC(cudaMalloc((void**)&deviceData, sizeof(unsigned char) * size));
CSC(cudaMemcpy(deviceData, data, sizeof(unsigned char) * size, cudaMemcpyHostToDevice));
CSC(cudaMalloc((void**)&deviceHisto, sizeof(int) * BLOCK_COUNT));
CSC(cudaMalloc((void**)&devicePrefix, sizeof(int) * BLOCK_COUNT));
CSC(cudaMemset(deviceHisto, 0, sizeof(int) * BLOCK_COUNT));
CSC(cudaMalloc((void**)&deviceResult, sizeof(unsigned char) * size));
CSC(cudaEventRecord(start));
Histogram<<<BLOCK_COUNT, BLOCK_COUNT>>>(deviceData, size, deviceHisto);
cudaThreadSynchronize(); // wait end
CSC(cudaGetLastError());
Scan<<<1, HALF_BLOCK_COUNT>>>(deviceHisto, devicePrefix);
cudaThreadSynchronize(); // wait end
CSC(cudaGetLastError());
CountSort<<<1, BLOCK_COUNT>>>(deviceData, devicePrefix, deviceResult, size);
cudaThreadSynchronize(); // wait end
CSC(cudaGetLastError());
CSC(cudaEventRecord(stop));
CSC(cudaEventSynchronize(stop));
CSC(cudaEventElapsedTime(&elapsedTime, start, stop));
CSC(cudaEventDestroy(start));
CSC(cudaEventDestroy(stop));
printf("Time : %f ms \n", elapsedTime);
CSC(cudaMemcpy(data, deviceResult, sizeof(unsigned char) * size, cudaMemcpyDeviceToHost));
// freopen(NULL, "wb", stdout);
// fwrite(data, sizeof(unsigned char), size, stdout);
// fclose(stdout);
CSC(cudaFree(deviceData));
CSC(cudaFree(deviceHisto));
CSC(cudaFree(devicePrefix));
delete[] data;
return 0;
}
|
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#include <chrono>
#define BLOCK_COUNT 256u
#define HALF_BLOCK_COUNT 128u
#define BANKS 16
#define LOG_2_BANKS 4
// macro used for computing
// Bank-Conflict-Free Shared Memory Array Indices
#define AVOID_BANK_CONFLICTS(idx) ((idx) >> BANKS + (idx) >> (LOG_2_BANKS << 1))
#define CSC(call) do { \
hipError_t res = call; \
if (res != hipSuccess) { \
fprintf(stderr, "CUDA Error in %s:%d: %s\n", __FILE__, __LINE__, hipGetErrorString(res)); \
exit(0); \
} \
} while (0)
__global__ void Histogram(unsigned char* data, int size, int* histo)
{
// выделяем разделяемую память, объем памяти равен количеству корзинок
__shared__ int tmp[BLOCK_COUNT];
// вычисляем абсолютный идентификатор
int idx = blockDim.x * blockIdx.x + threadIdx.x;
// смещение
int offset = gridDim.x * blockDim.x;
// заполним временный массив нулем,
// фактически заполняем 256 элементов как 0 в общей памяти
tmp[threadIdx.x] = 0;
__syncthreads(); // потоки ожидают выполнения заполнения нулем tmp
// перебираем все элементы буфера data,
// пока абс идентификатор не коснется значения size
while (idx < size)
{
// извлекаем значение, находящееся в буфере
// и увеличиваем счетчик в массиве разделяемой памяти
atomicAdd(&tmp[data[idx]], 1);
idx += offset; // увеличение абс идентиф по смещение
}
__syncthreads(); // ждем все потоки
// обновляем окончательный результат в массиве histo
int i = threadIdx.x;
while (i < BLOCK_COUNT)
{
atomicAdd(&histo[i], tmp[i]);
i += blockDim.x;
}
}
__global__ void Scan(int* histo, int* prefixSum)
{
__shared__ int tmp[BLOCK_COUNT];
int threadId = threadIdx.x;
int offset = 1;
int aIdx = threadIdx.x;
int bIdx = threadIdx.x + HALF_BLOCK_COUNT;
int bankOffsetA = AVOID_BANK_CONFLICTS(aIdx);
int bankOffsetB = AVOID_BANK_CONFLICTS(bIdx);
// загружаем данные из гистограммы в общую память
tmp[aIdx + bankOffsetA] = histo[aIdx];
tmp[bIdx + bankOffsetB] = histo[bIdx];
// строим сумму на месте вверх по дереву
{
int lvl = BLOCK_COUNT >> 1;
while (lvl > 0)
{
__syncthreads();
if (threadId < lvl)
{
int aIndex = (offset * (threadId * 2 + 1) - 1);
int bIndex = (offset * (threadId * 2 + 2) - 1);
aIndex += AVOID_BANK_CONFLICTS(aIndex);
bIndex += AVOID_BANK_CONFLICTS(bIndex);
tmp[bIndex] += tmp[aIndex];
}
offset <<= 1;
lvl >>= 1;
}
}
// очищаем последний элемент
if (threadId == 0)
{
tmp[BLOCK_COUNT - 1 + AVOID_BANK_CONFLICTS(BLOCK_COUNT - 1)] = 0;
}
// идем вниз по "дереву" и строим сканирование
{
int lvl = 1;
while (lvl < BLOCK_COUNT)
{
offset >>= 1;
__syncthreads();
if (threadId < lvl)
{
int aIndex = (offset * (threadId * 2 + 1) - 1);
int bIndex = (offset * (threadId * 2 + 2) - 1);
aIndex += AVOID_BANK_CONFLICTS(aIndex);
bIndex += AVOID_BANK_CONFLICTS(bIndex);
int temp = tmp[aIndex];
tmp[aIndex] = tmp[bIndex];
tmp[bIndex] += temp;
}
lvl <<= 1;
}
}
__syncthreads();
// записываем результаты в массив prefixSum
prefixSum[aIdx] = histo[aIdx] + tmp[aIdx + bankOffsetA];
prefixSum[bIdx] = histo[bIdx] + tmp[bIdx + bankOffsetB];
}
__global__ void CountSort(unsigned char* data, int* prefixSum, unsigned char* result, int size)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int offset = gridDim.x * blockDim.x;
int i = idx, j;
while (i < size)
{
// j = prefixSum[i] - 1;
// bound = i ? prefixSum[i - 1] : 0;
// while (j >= bound)
// {
// data[j] = i;
// --j;
// }
j = atomicSub(&prefixSum[data[i]], 1) - 1;
result[j] = data[i];
i += offset;
}
}
int main()
{
int size;
freopen(NULL, "rb", stdin);
fread(&size, sizeof(int), 1, stdin);
unsigned char* data = new unsigned char[size];
fread(data, sizeof(unsigned char), size, stdin);
fclose(stdin);
unsigned char* deviceData;
unsigned char* deviceResult;
int* deviceHisto;
int* devicePrefix;
float elapsedTime;
hipEvent_t start, stop;
CSC(hipEventCreate(&start));
CSC(hipEventCreate(&stop));
CSC(hipMalloc((void**)&deviceData, sizeof(unsigned char) * size));
CSC(hipMemcpy(deviceData, data, sizeof(unsigned char) * size, hipMemcpyHostToDevice));
CSC(hipMalloc((void**)&deviceHisto, sizeof(int) * BLOCK_COUNT));
CSC(hipMalloc((void**)&devicePrefix, sizeof(int) * BLOCK_COUNT));
CSC(hipMemset(deviceHisto, 0, sizeof(int) * BLOCK_COUNT));
CSC(hipMalloc((void**)&deviceResult, sizeof(unsigned char) * size));
CSC(hipEventRecord(start));
Histogram<<<BLOCK_COUNT, BLOCK_COUNT>>>(deviceData, size, deviceHisto);
hipDeviceSynchronize(); // wait end
CSC(hipGetLastError());
Scan<<<1, HALF_BLOCK_COUNT>>>(deviceHisto, devicePrefix);
hipDeviceSynchronize(); // wait end
CSC(hipGetLastError());
CountSort<<<1, BLOCK_COUNT>>>(deviceData, devicePrefix, deviceResult, size);
hipDeviceSynchronize(); // wait end
CSC(hipGetLastError());
CSC(hipEventRecord(stop));
CSC(hipEventSynchronize(stop));
CSC(hipEventElapsedTime(&elapsedTime, start, stop));
CSC(hipEventDestroy(start));
CSC(hipEventDestroy(stop));
printf("Time : %f ms \n", elapsedTime);
CSC(hipMemcpy(data, deviceResult, sizeof(unsigned char) * size, hipMemcpyDeviceToHost));
// freopen(NULL, "wb", stdout);
// fwrite(data, sizeof(unsigned char), size, stdout);
// fclose(stdout);
CSC(hipFree(deviceData));
CSC(hipFree(deviceHisto));
CSC(hipFree(devicePrefix));
delete[] data;
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#include <chrono>
#define BLOCK_COUNT 256u
#define HALF_BLOCK_COUNT 128u
#define BANKS 16
#define LOG_2_BANKS 4
// macro used for computing
// Bank-Conflict-Free Shared Memory Array Indices
#define AVOID_BANK_CONFLICTS(idx) ((idx) >> BANKS + (idx) >> (LOG_2_BANKS << 1))
#define CSC(call) do { \
hipError_t res = call; \
if (res != hipSuccess) { \
fprintf(stderr, "CUDA Error in %s:%d: %s\n", __FILE__, __LINE__, hipGetErrorString(res)); \
exit(0); \
} \
} while (0)
__global__ void Histogram(unsigned char* data, int size, int* histo)
{
// выделяем разделяемую память, объем памяти равен количеству корзинок
__shared__ int tmp[BLOCK_COUNT];
// вычисляем абсолютный идентификатор
int idx = blockDim.x * blockIdx.x + threadIdx.x;
// смещение
int offset = gridDim.x * blockDim.x;
// заполним временный массив нулем,
// фактически заполняем 256 элементов как 0 в общей памяти
tmp[threadIdx.x] = 0;
__syncthreads(); // потоки ожидают выполнения заполнения нулем tmp
// перебираем все элементы буфера data,
// пока абс идентификатор не коснется значения size
while (idx < size)
{
// извлекаем значение, находящееся в буфере
// и увеличиваем счетчик в массиве разделяемой памяти
atomicAdd(&tmp[data[idx]], 1);
idx += offset; // увеличение абс идентиф по смещение
}
__syncthreads(); // ждем все потоки
// обновляем окончательный результат в массиве histo
int i = threadIdx.x;
while (i < BLOCK_COUNT)
{
atomicAdd(&histo[i], tmp[i]);
i += blockDim.x;
}
}
__global__ void Scan(int* histo, int* prefixSum)
{
__shared__ int tmp[BLOCK_COUNT];
int threadId = threadIdx.x;
int offset = 1;
int aIdx = threadIdx.x;
int bIdx = threadIdx.x + HALF_BLOCK_COUNT;
int bankOffsetA = AVOID_BANK_CONFLICTS(aIdx);
int bankOffsetB = AVOID_BANK_CONFLICTS(bIdx);
// загружаем данные из гистограммы в общую память
tmp[aIdx + bankOffsetA] = histo[aIdx];
tmp[bIdx + bankOffsetB] = histo[bIdx];
// строим сумму на месте вверх по дереву
{
int lvl = BLOCK_COUNT >> 1;
while (lvl > 0)
{
__syncthreads();
if (threadId < lvl)
{
int aIndex = (offset * (threadId * 2 + 1) - 1);
int bIndex = (offset * (threadId * 2 + 2) - 1);
aIndex += AVOID_BANK_CONFLICTS(aIndex);
bIndex += AVOID_BANK_CONFLICTS(bIndex);
tmp[bIndex] += tmp[aIndex];
}
offset <<= 1;
lvl >>= 1;
}
}
// очищаем последний элемент
if (threadId == 0)
{
tmp[BLOCK_COUNT - 1 + AVOID_BANK_CONFLICTS(BLOCK_COUNT - 1)] = 0;
}
// идем вниз по "дереву" и строим сканирование
{
int lvl = 1;
while (lvl < BLOCK_COUNT)
{
offset >>= 1;
__syncthreads();
if (threadId < lvl)
{
int aIndex = (offset * (threadId * 2 + 1) - 1);
int bIndex = (offset * (threadId * 2 + 2) - 1);
aIndex += AVOID_BANK_CONFLICTS(aIndex);
bIndex += AVOID_BANK_CONFLICTS(bIndex);
int temp = tmp[aIndex];
tmp[aIndex] = tmp[bIndex];
tmp[bIndex] += temp;
}
lvl <<= 1;
}
}
__syncthreads();
// записываем результаты в массив prefixSum
prefixSum[aIdx] = histo[aIdx] + tmp[aIdx + bankOffsetA];
prefixSum[bIdx] = histo[bIdx] + tmp[bIdx + bankOffsetB];
}
__global__ void CountSort(unsigned char* data, int* prefixSum, unsigned char* result, int size)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int offset = gridDim.x * blockDim.x;
int i = idx, j;
while (i < size)
{
// j = prefixSum[i] - 1;
// bound = i ? prefixSum[i - 1] : 0;
// while (j >= bound)
// {
// data[j] = i;
// --j;
// }
j = atomicSub(&prefixSum[data[i]], 1) - 1;
result[j] = data[i];
i += offset;
}
}
int main()
{
int size;
freopen(NULL, "rb", stdin);
fread(&size, sizeof(int), 1, stdin);
unsigned char* data = new unsigned char[size];
fread(data, sizeof(unsigned char), size, stdin);
fclose(stdin);
unsigned char* deviceData;
unsigned char* deviceResult;
int* deviceHisto;
int* devicePrefix;
float elapsedTime;
hipEvent_t start, stop;
CSC(hipEventCreate(&start));
CSC(hipEventCreate(&stop));
CSC(hipMalloc((void**)&deviceData, sizeof(unsigned char) * size));
CSC(hipMemcpy(deviceData, data, sizeof(unsigned char) * size, hipMemcpyHostToDevice));
CSC(hipMalloc((void**)&deviceHisto, sizeof(int) * BLOCK_COUNT));
CSC(hipMalloc((void**)&devicePrefix, sizeof(int) * BLOCK_COUNT));
CSC(hipMemset(deviceHisto, 0, sizeof(int) * BLOCK_COUNT));
CSC(hipMalloc((void**)&deviceResult, sizeof(unsigned char) * size));
CSC(hipEventRecord(start));
Histogram<<<BLOCK_COUNT, BLOCK_COUNT>>>(deviceData, size, deviceHisto);
hipDeviceSynchronize(); // wait end
CSC(hipGetLastError());
Scan<<<1, HALF_BLOCK_COUNT>>>(deviceHisto, devicePrefix);
hipDeviceSynchronize(); // wait end
CSC(hipGetLastError());
CountSort<<<1, BLOCK_COUNT>>>(deviceData, devicePrefix, deviceResult, size);
hipDeviceSynchronize(); // wait end
CSC(hipGetLastError());
CSC(hipEventRecord(stop));
CSC(hipEventSynchronize(stop));
CSC(hipEventElapsedTime(&elapsedTime, start, stop));
CSC(hipEventDestroy(start));
CSC(hipEventDestroy(stop));
printf("Time : %f ms \n", elapsedTime);
CSC(hipMemcpy(data, deviceResult, sizeof(unsigned char) * size, hipMemcpyDeviceToHost));
// freopen(NULL, "wb", stdout);
// fwrite(data, sizeof(unsigned char), size, stdout);
// fclose(stdout);
CSC(hipFree(deviceData));
CSC(hipFree(deviceHisto));
CSC(hipFree(devicePrefix));
delete[] data;
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9HistogramPhiPi
.globl _Z9HistogramPhiPi
.p2align 8
.type _Z9HistogramPhiPi,@function
_Z9HistogramPhiPi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x8
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_lshlrev_b32_e32 v2, 2, v0
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b64 s[8:9], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v1
v_mov_b32_e32 v4, 1
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s2, s4
v_add_co_u32 v2, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_ashr_i32 s7, s3, 31
s_mov_b32 s8, 0
.LBB0_2:
global_load_u8 v5, v[2:3], off
v_add_nc_u32_e32 v1, s3, v1
v_add_co_u32 v2, s2, v2, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s2, s7, v3, s2
v_cmp_le_i32_e32 vcc_lo, s5, v1
s_or_b32 s8, vcc_lo, s8
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v5, 2, v5
ds_add_u32 v5, v4
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s6
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 0x100, v0
s_cbranch_execz .LBB0_6
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v3, 2, v0
s_lshl_b32 s2, s4, 2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s0, s0, v3
v_add_co_ci_u32_e64 v2, null, s1, 0, s0
s_mov_b32 s1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, s1
.LBB0_5:
ds_load_b32 v4, v3
v_add_nc_u32_e32 v0, s4, v0
v_add_nc_u32_e32 v3, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e32 vcc_lo, 0xff, v0
s_or_b32 s3, vcc_lo, s3
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v[1:2], v4, off
v_add_co_u32 v1, s0, v1, s2
v_add_co_ci_u32_e64 v2, s0, s1, v2, s0
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_5
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9HistogramPhiPi
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9HistogramPhiPi, .Lfunc_end0-_Z9HistogramPhiPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z4ScanPiS_
.globl _Z4ScanPiS_
.p2align 8
.type _Z4ScanPiS_,@function
_Z4ScanPiS_:
s_load_b64 s[2:3], s[0:1], 0x0
v_add_nc_u32_e32 v5, 0x80, v0
v_lshlrev_b32_e32 v6, 2, v0
v_lshlrev_b32_e32 v9, 1, v0
s_delay_alu instid0(VALU_DEP_3)
v_lshlrev_b32_e32 v7, 2, v5
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v10, v6, s[2:3]
global_load_b32 v11, v7, s[2:3]
v_add_co_u32 v3, s4, s2, v6
v_add_co_u32 v1, s2, s2, v7
v_add_co_ci_u32_e64 v4, null, s3, 0, s4
v_add_co_ci_u32_e64 v2, null, s3, 0, s2
v_or_b32_e32 v8, 1, v9
v_add_nc_u32_e32 v9, 2, v9
s_movk_i32 s3, 0x80
s_mov_b32 s2, 1
s_waitcnt vmcnt(0)
ds_store_2addr_stride64_b32 v6, v10, v11 offset1:2
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_2
.p2align 6
.LBB1_1:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 1
s_lshl_b32 s2, s2, 1
s_cmp_gt_u32 s3, 1
s_mov_b32 s3, s4
s_cbranch_scc0 .LBB1_4
.LBB1_2:
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB1_1
v_mul_lo_u32 v10, s2, v8
v_mul_lo_u32 v11, s2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v12, -1, v10
v_add_nc_u32_e32 v10, 15, v10
v_add_nc_u32_e32 v13, -1, v11
v_add_nc_u32_e32 v11, 15, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v10, v10, v12
v_ashrrev_i32_e32 v11, v11, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v10, 8, v10
v_ashrrev_i32_e32 v11, 8, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_lshl_u32 v10, v10, v12, 2
v_add_lshl_u32 v11, v11, v13, 2
ds_load_b32 v10, v10
ds_load_b32 v12, v11
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v10, v12, v10
ds_store_b32 v11, v10
s_branch .LBB1_1
.LBB1_4:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_6
v_mov_b32_e32 v8, 0
ds_store_b32 v8, v8
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s2
v_lshlrev_b32_e32 v9, 1, v0
s_mov_b32 s3, 1
s_movk_i32 s2, 0x100
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v8, 1, v9
v_add_nc_u32_e32 v9, 2, v9
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_8
.p2align 6
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s4
s_lshl_b32 s4, s3, 1
s_cmpk_lt_u32 s3, 0x80
s_mov_b32 s3, s4
s_cbranch_scc0 .LBB1_10
.LBB1_8:
s_lshr_b32 s2, s2, 1
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB1_7
v_mad_u32_u24 v10, s2, v9, -1
v_mad_u32_u24 v11, s2, v9, 15
v_mad_u32_u24 v12, s2, v8, 15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, v11, v10
v_ashrrev_i32_e32 v11, 8, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_lshl_u32 v10, v11, v10, 2
v_mad_u32_u24 v11, s2, v8, -1
ds_load_b32 v13, v10
v_ashrrev_i32_e32 v12, v12, v11
v_ashrrev_i32_e32 v12, 8, v12
s_delay_alu instid0(VALU_DEP_1)
v_add_lshl_u32 v11, v12, v11, 2
ds_load_b32 v12, v11
s_waitcnt lgkmcnt(1)
ds_store_b32 v11, v13
ds_load_b32 v11, v10
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v11, v11, v12
ds_store_b32 v10, v11
s_branch .LBB1_7
.LBB1_10:
s_set_inst_prefetch_distance 0x2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
global_load_b32 v3, v[3:4], off
ds_load_b32 v4, v6
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
ds_load_b32 v6, v7
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
global_store_b32 v0, v3, s[0:1]
global_load_b32 v0, v[1:2], off
v_lshlrev_b32_e32 v1, 2, v5
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v6, v0
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4ScanPiS_
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 5
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z4ScanPiS_, .Lfunc_end1-_Z4ScanPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9CountSortPhPiS_i
.globl _Z9CountSortPhPiS_i
.p2align 8
.type _Z9CountSortPhPiS_i,@function
_Z9CountSortPhPiS_i:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB2_3
s_load_b32 s8, s[2:3], 0x0
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v0, 31, v1
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s5, s8, s5
s_add_u32 s6, s6, -1
v_add_co_u32 v2, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v0, vcc_lo
v_mov_b32_e32 v0, -1
s_addc_u32 s7, s7, -1
s_ashr_i32 s8, s5, 31
.p2align 6
.LBB2_2:
global_load_u8 v4, v[2:3], off
v_add_nc_u32_e32 v1, s5, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, s4, v1
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v4, 2, v4
global_atomic_add_u32 v4, v4, v0, s[2:3] glc
global_load_u8 v6, v[2:3], off
v_add_co_u32 v2, s0, v2, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s8, v3, s0
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_u32 v4, s1, s6, v4
v_add_co_ci_u32_e64 v5, s1, s7, v5, s1
s_waitcnt vmcnt(0)
global_store_b8 v[4:5], v6, off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB2_2
.LBB2_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9CountSortPhPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z9CountSortPhPiS_i, .Lfunc_end2-_Z9CountSortPhPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9HistogramPhiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9HistogramPhiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4ScanPiS_
.private_segment_fixed_size: 0
.sgpr_count: 5
.sgpr_spill_count: 0
.symbol: _Z4ScanPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9CountSortPhPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9CountSortPhPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#include <chrono>
#define BLOCK_COUNT 256u
#define HALF_BLOCK_COUNT 128u
#define BANKS 16
#define LOG_2_BANKS 4
// macro used for computing
// Bank-Conflict-Free Shared Memory Array Indices
#define AVOID_BANK_CONFLICTS(idx) ((idx) >> BANKS + (idx) >> (LOG_2_BANKS << 1))
#define CSC(call) do { \
hipError_t res = call; \
if (res != hipSuccess) { \
fprintf(stderr, "CUDA Error in %s:%d: %s\n", __FILE__, __LINE__, hipGetErrorString(res)); \
exit(0); \
} \
} while (0)
__global__ void Histogram(unsigned char* data, int size, int* histo)
{
// выделяем разделяемую память, объем памяти равен количеству корзинок
__shared__ int tmp[BLOCK_COUNT];
// вычисляем абсолютный идентификатор
int idx = blockDim.x * blockIdx.x + threadIdx.x;
// смещение
int offset = gridDim.x * blockDim.x;
// заполним временный массив нулем,
// фактически заполняем 256 элементов как 0 в общей памяти
tmp[threadIdx.x] = 0;
__syncthreads(); // потоки ожидают выполнения заполнения нулем tmp
// перебираем все элементы буфера data,
// пока абс идентификатор не коснется значения size
while (idx < size)
{
// извлекаем значение, находящееся в буфере
// и увеличиваем счетчик в массиве разделяемой памяти
atomicAdd(&tmp[data[idx]], 1);
idx += offset; // увеличение абс идентиф по смещение
}
__syncthreads(); // ждем все потоки
// обновляем окончательный результат в массиве histo
int i = threadIdx.x;
while (i < BLOCK_COUNT)
{
atomicAdd(&histo[i], tmp[i]);
i += blockDim.x;
}
}
__global__ void Scan(int* histo, int* prefixSum)
{
__shared__ int tmp[BLOCK_COUNT];
int threadId = threadIdx.x;
int offset = 1;
int aIdx = threadIdx.x;
int bIdx = threadIdx.x + HALF_BLOCK_COUNT;
int bankOffsetA = AVOID_BANK_CONFLICTS(aIdx);
int bankOffsetB = AVOID_BANK_CONFLICTS(bIdx);
// загружаем данные из гистограммы в общую память
tmp[aIdx + bankOffsetA] = histo[aIdx];
tmp[bIdx + bankOffsetB] = histo[bIdx];
// строим сумму на месте вверх по дереву
{
int lvl = BLOCK_COUNT >> 1;
while (lvl > 0)
{
__syncthreads();
if (threadId < lvl)
{
int aIndex = (offset * (threadId * 2 + 1) - 1);
int bIndex = (offset * (threadId * 2 + 2) - 1);
aIndex += AVOID_BANK_CONFLICTS(aIndex);
bIndex += AVOID_BANK_CONFLICTS(bIndex);
tmp[bIndex] += tmp[aIndex];
}
offset <<= 1;
lvl >>= 1;
}
}
// очищаем последний элемент
if (threadId == 0)
{
tmp[BLOCK_COUNT - 1 + AVOID_BANK_CONFLICTS(BLOCK_COUNT - 1)] = 0;
}
// идем вниз по "дереву" и строим сканирование
{
int lvl = 1;
while (lvl < BLOCK_COUNT)
{
offset >>= 1;
__syncthreads();
if (threadId < lvl)
{
int aIndex = (offset * (threadId * 2 + 1) - 1);
int bIndex = (offset * (threadId * 2 + 2) - 1);
aIndex += AVOID_BANK_CONFLICTS(aIndex);
bIndex += AVOID_BANK_CONFLICTS(bIndex);
int temp = tmp[aIndex];
tmp[aIndex] = tmp[bIndex];
tmp[bIndex] += temp;
}
lvl <<= 1;
}
}
__syncthreads();
// записываем результаты в массив prefixSum
prefixSum[aIdx] = histo[aIdx] + tmp[aIdx + bankOffsetA];
prefixSum[bIdx] = histo[bIdx] + tmp[bIdx + bankOffsetB];
}
__global__ void CountSort(unsigned char* data, int* prefixSum, unsigned char* result, int size)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int offset = gridDim.x * blockDim.x;
int i = idx, j;
while (i < size)
{
// j = prefixSum[i] - 1;
// bound = i ? prefixSum[i - 1] : 0;
// while (j >= bound)
// {
// data[j] = i;
// --j;
// }
j = atomicSub(&prefixSum[data[i]], 1) - 1;
result[j] = data[i];
i += offset;
}
}
int main()
{
int size;
freopen(NULL, "rb", stdin);
fread(&size, sizeof(int), 1, stdin);
unsigned char* data = new unsigned char[size];
fread(data, sizeof(unsigned char), size, stdin);
fclose(stdin);
unsigned char* deviceData;
unsigned char* deviceResult;
int* deviceHisto;
int* devicePrefix;
float elapsedTime;
hipEvent_t start, stop;
CSC(hipEventCreate(&start));
CSC(hipEventCreate(&stop));
CSC(hipMalloc((void**)&deviceData, sizeof(unsigned char) * size));
CSC(hipMemcpy(deviceData, data, sizeof(unsigned char) * size, hipMemcpyHostToDevice));
CSC(hipMalloc((void**)&deviceHisto, sizeof(int) * BLOCK_COUNT));
CSC(hipMalloc((void**)&devicePrefix, sizeof(int) * BLOCK_COUNT));
CSC(hipMemset(deviceHisto, 0, sizeof(int) * BLOCK_COUNT));
CSC(hipMalloc((void**)&deviceResult, sizeof(unsigned char) * size));
CSC(hipEventRecord(start));
Histogram<<<BLOCK_COUNT, BLOCK_COUNT>>>(deviceData, size, deviceHisto);
hipDeviceSynchronize(); // wait end
CSC(hipGetLastError());
Scan<<<1, HALF_BLOCK_COUNT>>>(deviceHisto, devicePrefix);
hipDeviceSynchronize(); // wait end
CSC(hipGetLastError());
CountSort<<<1, BLOCK_COUNT>>>(deviceData, devicePrefix, deviceResult, size);
hipDeviceSynchronize(); // wait end
CSC(hipGetLastError());
CSC(hipEventRecord(stop));
CSC(hipEventSynchronize(stop));
CSC(hipEventElapsedTime(&elapsedTime, start, stop));
CSC(hipEventDestroy(start));
CSC(hipEventDestroy(stop));
printf("Time : %f ms \n", elapsedTime);
CSC(hipMemcpy(data, deviceResult, sizeof(unsigned char) * size, hipMemcpyDeviceToHost));
// freopen(NULL, "wb", stdout);
// fwrite(data, sizeof(unsigned char), size, stdout);
// fclose(stdout);
CSC(hipFree(deviceData));
CSC(hipFree(deviceHisto));
CSC(hipFree(devicePrefix));
delete[] data;
return 0;
}
|
.text
.file "lab5_time.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__HistogramPhiPi # -- Begin function _Z24__device_stub__HistogramPhiPi
.p2align 4, 0x90
.type _Z24__device_stub__HistogramPhiPi,@function
_Z24__device_stub__HistogramPhiPi: # @_Z24__device_stub__HistogramPhiPi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9HistogramPhiPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__HistogramPhiPi, .Lfunc_end0-_Z24__device_stub__HistogramPhiPi
.cfi_endproc
# -- End function
.globl _Z19__device_stub__ScanPiS_ # -- Begin function _Z19__device_stub__ScanPiS_
.p2align 4, 0x90
.type _Z19__device_stub__ScanPiS_,@function
_Z19__device_stub__ScanPiS_: # @_Z19__device_stub__ScanPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4ScanPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z19__device_stub__ScanPiS_, .Lfunc_end1-_Z19__device_stub__ScanPiS_
.cfi_endproc
# -- End function
.globl _Z24__device_stub__CountSortPhPiS_i # -- Begin function _Z24__device_stub__CountSortPhPiS_i
.p2align 4, 0x90
.type _Z24__device_stub__CountSortPhPiS_i,@function
_Z24__device_stub__CountSortPhPiS_i: # @_Z24__device_stub__CountSortPhPiS_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9CountSortPhPiS_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z24__device_stub__CountSortPhPiS_i, .Lfunc_end2-_Z24__device_stub__CountSortPhPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $168, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq stdin(%rip), %rdx
movl $.L.str, %esi
xorl %edi, %edi
callq freopen
movq stdin(%rip), %rcx
leaq 68(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq fread
movl 68(%rsp), %ebp
movslq %ebp, %r14
movq %r14, %rdi
callq _Znam
movq %rax, %rbx
movq stdin(%rip), %rcx
movl $1, %esi
movq %rax, %rdi
movq %r14, %rdx
callq fread
movq stdin(%rip), %rdi
callq fclose
leaq 96(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB3_1
# %bb.3:
leaq 72(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB3_4
# %bb.5:
leaq 88(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_6
# %bb.7:
movq 88(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_8
# %bb.9:
leaq 80(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
testl %eax, %eax
jne .LBB3_10
# %bb.11:
leaq 104(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
testl %eax, %eax
jne .LBB3_12
# %bb.13:
movq 80(%rsp), %rdi
movl $1024, %edx # imm = 0x400
xorl %esi, %esi
callq hipMemset
testl %eax, %eax
jne .LBB3_14
# %bb.15:
leaq 160(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_16
# %bb.17:
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB3_18
# %bb.19:
movabsq $4294967552, %r14 # imm = 0x100000100
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_21
# %bb.20:
movq 88(%rsp), %rax
movq 80(%rsp), %rcx
movq %rax, 56(%rsp)
movl %ebp, 112(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 40(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z9HistogramPhiPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_21:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB3_22
# %bb.23:
leaq -255(%r14), %r15
leaq -128(%r14), %rdx
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_25
# %bb.24:
movq 80(%rsp), %rax
movq 104(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 40(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z4ScanPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_25:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB3_26
# %bb.27:
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_29
# %bb.28:
movq 88(%rsp), %rax
movq 104(%rsp), %rcx
movq 160(%rsp), %rdx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
movq %rdx, 40(%rsp)
movl %ebp, 124(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 124(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
movq %rsp, %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z9CountSortPhPiS_i, %edi
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_29:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB3_30
# %bb.31:
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB3_32
# %bb.33:
movq 72(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB3_34
# %bb.35:
movq 96(%rsp), %rsi
movq 72(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB3_36
# %bb.37:
movq 96(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB3_38
# %bb.39:
movq 72(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB3_40
# %bb.41:
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 160(%rsp), %rsi
movslq 68(%rsp), %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_42
# %bb.43:
movq 88(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_44
# %bb.45:
movq 80(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_46
# %bb.47:
movq 104(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_48
# %bb.49:
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_1:
.cfi_def_cfa_offset 208
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $179, %ecx
jmp .LBB3_2
.LBB3_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $180, %ecx
jmp .LBB3_2
.LBB3_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $182, %ecx
jmp .LBB3_2
.LBB3_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $183, %ecx
jmp .LBB3_2
.LBB3_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $185, %ecx
jmp .LBB3_2
.LBB3_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $186, %ecx
jmp .LBB3_2
.LBB3_14:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $187, %ecx
jmp .LBB3_2
.LBB3_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $189, %ecx
jmp .LBB3_2
.LBB3_18:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $191, %ecx
jmp .LBB3_2
.LBB3_22:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $195, %ecx
jmp .LBB3_2
.LBB3_26:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $199, %ecx
jmp .LBB3_2
.LBB3_30:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $203, %ecx
jmp .LBB3_2
.LBB3_32:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $205, %ecx
jmp .LBB3_2
.LBB3_34:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $206, %ecx
jmp .LBB3_2
.LBB3_36:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $208, %ecx
jmp .LBB3_2
.LBB3_38:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $209, %ecx
jmp .LBB3_2
.LBB3_40:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $210, %ecx
jmp .LBB3_2
.LBB3_42:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $213, %ecx
jmp .LBB3_2
.LBB3_44:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $219, %ecx
jmp .LBB3_2
.LBB3_46:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $220, %ecx
jmp .LBB3_2
.LBB3_48:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $221, %ecx
.LBB3_2:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
xorl %edi, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9HistogramPhiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4ScanPiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9CountSortPhPiS_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9HistogramPhiPi,@object # @_Z9HistogramPhiPi
.section .rodata,"a",@progbits
.globl _Z9HistogramPhiPi
.p2align 3, 0x0
_Z9HistogramPhiPi:
.quad _Z24__device_stub__HistogramPhiPi
.size _Z9HistogramPhiPi, 8
.type _Z4ScanPiS_,@object # @_Z4ScanPiS_
.globl _Z4ScanPiS_
.p2align 3, 0x0
_Z4ScanPiS_:
.quad _Z19__device_stub__ScanPiS_
.size _Z4ScanPiS_, 8
.type _Z9CountSortPhPiS_i,@object # @_Z9CountSortPhPiS_i
.globl _Z9CountSortPhPiS_i
.p2align 3, 0x0
_Z9CountSortPhPiS_i:
.quad _Z24__device_stub__CountSortPhPiS_i
.size _Z9CountSortPhPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "rb"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CUDA Error in %s:%d: %s\n"
.size .L.str.1, 25
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/lveltman/PGP/master/lab5/lab5_time.hip"
.size .L.str.2, 96
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Time : %f ms \n"
.size .L.str.3, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9HistogramPhiPi"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z4ScanPiS_"
.size .L__unnamed_2, 12
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z9CountSortPhPiS_i"
.size .L__unnamed_3, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__HistogramPhiPi
.addrsig_sym _Z19__device_stub__ScanPiS_
.addrsig_sym _Z24__device_stub__CountSortPhPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9HistogramPhiPi
.addrsig_sym _Z4ScanPiS_
.addrsig_sym _Z9CountSortPhPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0007fcd3_00000000-6_lab5_time.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3771:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3771:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9HistogramPhiPiPhiPi
.type _Z31__device_stub__Z9HistogramPhiPiPhiPi, @function
_Z31__device_stub__Z9HistogramPhiPiPhiPi:
.LFB3793:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9HistogramPhiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3793:
.size _Z31__device_stub__Z9HistogramPhiPiPhiPi, .-_Z31__device_stub__Z9HistogramPhiPiPhiPi
.globl _Z9HistogramPhiPi
.type _Z9HistogramPhiPi, @function
_Z9HistogramPhiPi:
.LFB3794:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9HistogramPhiPiPhiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3794:
.size _Z9HistogramPhiPi, .-_Z9HistogramPhiPi
.globl _Z25__device_stub__Z4ScanPiS_PiS_
.type _Z25__device_stub__Z4ScanPiS_PiS_, @function
_Z25__device_stub__Z4ScanPiS_PiS_:
.LFB3795:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4ScanPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3795:
.size _Z25__device_stub__Z4ScanPiS_PiS_, .-_Z25__device_stub__Z4ScanPiS_PiS_
.globl _Z4ScanPiS_
.type _Z4ScanPiS_, @function
_Z4ScanPiS_:
.LFB3796:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z4ScanPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3796:
.size _Z4ScanPiS_, .-_Z4ScanPiS_
.globl _Z33__device_stub__Z9CountSortPhPiS_iPhPiS_i
.type _Z33__device_stub__Z9CountSortPhPiS_iPhPiS_i, @function
_Z33__device_stub__Z9CountSortPhPiS_iPhPiS_i:
.LFB3797:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9CountSortPhPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3797:
.size _Z33__device_stub__Z9CountSortPhPiS_iPhPiS_i, .-_Z33__device_stub__Z9CountSortPhPiS_iPhPiS_i
.globl _Z9CountSortPhPiS_i
.type _Z9CountSortPhPiS_i, @function
_Z9CountSortPhPiS_i:
.LFB3798:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9CountSortPhPiS_iPhPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3798:
.size _Z9CountSortPhPiS_i, .-_Z9CountSortPhPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "rb"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/lveltman/PGP/master/lab5/lab5_time.cu"
.section .rodata.str1.1
.LC2:
.string "CUDA Error in %s:%d: %s\n"
.LC3:
.string "Time : %f ms \n"
.text
.globl main
.type main, @function
main:
.LFB3768:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $104, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq stdin(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $0, %edi
call freopen@PLT
leaq 12(%rsp), %rdi
movq stdin(%rip), %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movslq 12(%rsp), %rbp
movq %rbp, %rdi
call _Znam@PLT
movq %rax, %rbx
movslq 12(%rsp), %rcx
movq stdin(%rip), %r8
movl $1, %edx
movq %rbp, %rsi
movq %rax, %rdi
call __fread_chk@PLT
movq stdin(%rip), %rdi
call fclose@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
je .L28
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $179, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L28:
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
je .L29
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $180, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L29:
movslq 12(%rsp), %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
je .L30
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $182, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L30:
movslq 12(%rsp), %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L31
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $183, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L31:
leaq 32(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
testl %eax, %eax
je .L32
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $185, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L32:
leaq 40(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
testl %eax, %eax
je .L33
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $186, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L33:
movl $1024, %edx
movl $0, %esi
movq 32(%rsp), %rdi
call cudaMemset@PLT
testl %eax, %eax
je .L34
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $187, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L34:
movslq 12(%rsp), %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
je .L35
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $189, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L35:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
testl %eax, %eax
je .L36
call cudaGetErrorString@PLT
movq %rax, %r9
movl $191, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L36:
movl $256, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $256, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L37:
call cudaThreadSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
je .L38
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $195, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L54:
movq 32(%rsp), %rdx
movl 12(%rsp), %esi
movq 16(%rsp), %rdi
call _Z31__device_stub__Z9HistogramPhiPiPhiPi
jmp .L37
.L38:
movl $128, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L39:
call cudaThreadSynchronize@PLT
call cudaGetLastError@PLT
movl %eax, %edi
testl %eax, %eax
je .L40
call cudaGetErrorString@PLT
movq %rax, %r9
movl $199, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L55:
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z25__device_stub__Z4ScanPiS_PiS_
jmp .L39
.L40:
movl $256, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L56
.L41:
call cudaThreadSynchronize@PLT
call cudaGetLastError@PLT
movl %eax, %edi
testl %eax, %eax
je .L42
call cudaGetErrorString@PLT
movq %rax, %r9
movl $203, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L56:
movl 12(%rsp), %ecx
movq 24(%rsp), %rdx
movq 40(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z33__device_stub__Z9CountSortPhPiS_iPhPiS_i
jmp .L41
.L42:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
testl %eax, %eax
je .L43
call cudaGetErrorString@PLT
movq %rax, %r9
movl $205, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L43:
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %edi
testl %eax, %eax
je .L44
call cudaGetErrorString@PLT
movq %rax, %r9
movl $206, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L44:
leaq 76(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %edi
testl %eax, %eax
je .L45
call cudaGetErrorString@PLT
movq %rax, %r9
movl $208, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L45:
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movl %eax, %edi
testl %eax, %eax
je .L46
call cudaGetErrorString@PLT
movq %rax, %r9
movl $209, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L46:
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movl %eax, %edi
testl %eax, %eax
je .L47
call cudaGetErrorString@PLT
movq %rax, %r9
movl $210, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L47:
pxor %xmm0, %xmm0
cvtss2sd 76(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq 12(%rsp), %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
testl %eax, %eax
je .L48
call cudaGetErrorString@PLT
movq %rax, %r9
movl $213, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L48:
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
testl %eax, %eax
je .L49
call cudaGetErrorString@PLT
movq %rax, %r9
movl $219, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L49:
movq 32(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
testl %eax, %eax
je .L50
call cudaGetErrorString@PLT
movq %rax, %r9
movl $220, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L50:
movq 40(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
testl %eax, %eax
jne .L57
movq %rbx, %rdi
call _ZdaPv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L58
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
call cudaGetErrorString@PLT
movq %rax, %r9
movl $221, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L58:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3768:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z9CountSortPhPiS_i"
.LC5:
.string "_Z4ScanPiS_"
.LC6:
.string "_Z9HistogramPhiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3800:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z9CountSortPhPiS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z4ScanPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z9HistogramPhiPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3800:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "lab5_time.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__HistogramPhiPi # -- Begin function _Z24__device_stub__HistogramPhiPi
.p2align 4, 0x90
.type _Z24__device_stub__HistogramPhiPi,@function
_Z24__device_stub__HistogramPhiPi: # @_Z24__device_stub__HistogramPhiPi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9HistogramPhiPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__HistogramPhiPi, .Lfunc_end0-_Z24__device_stub__HistogramPhiPi
.cfi_endproc
# -- End function
.globl _Z19__device_stub__ScanPiS_ # -- Begin function _Z19__device_stub__ScanPiS_
.p2align 4, 0x90
.type _Z19__device_stub__ScanPiS_,@function
_Z19__device_stub__ScanPiS_: # @_Z19__device_stub__ScanPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4ScanPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z19__device_stub__ScanPiS_, .Lfunc_end1-_Z19__device_stub__ScanPiS_
.cfi_endproc
# -- End function
.globl _Z24__device_stub__CountSortPhPiS_i # -- Begin function _Z24__device_stub__CountSortPhPiS_i
.p2align 4, 0x90
.type _Z24__device_stub__CountSortPhPiS_i,@function
_Z24__device_stub__CountSortPhPiS_i: # @_Z24__device_stub__CountSortPhPiS_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9CountSortPhPiS_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z24__device_stub__CountSortPhPiS_i, .Lfunc_end2-_Z24__device_stub__CountSortPhPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $168, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq stdin(%rip), %rdx
movl $.L.str, %esi
xorl %edi, %edi
callq freopen
movq stdin(%rip), %rcx
leaq 68(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq fread
movl 68(%rsp), %ebp
movslq %ebp, %r14
movq %r14, %rdi
callq _Znam
movq %rax, %rbx
movq stdin(%rip), %rcx
movl $1, %esi
movq %rax, %rdi
movq %r14, %rdx
callq fread
movq stdin(%rip), %rdi
callq fclose
leaq 96(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB3_1
# %bb.3:
leaq 72(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB3_4
# %bb.5:
leaq 88(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_6
# %bb.7:
movq 88(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_8
# %bb.9:
leaq 80(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
testl %eax, %eax
jne .LBB3_10
# %bb.11:
leaq 104(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
testl %eax, %eax
jne .LBB3_12
# %bb.13:
movq 80(%rsp), %rdi
movl $1024, %edx # imm = 0x400
xorl %esi, %esi
callq hipMemset
testl %eax, %eax
jne .LBB3_14
# %bb.15:
leaq 160(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_16
# %bb.17:
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB3_18
# %bb.19:
movabsq $4294967552, %r14 # imm = 0x100000100
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_21
# %bb.20:
movq 88(%rsp), %rax
movq 80(%rsp), %rcx
movq %rax, 56(%rsp)
movl %ebp, 112(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 40(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z9HistogramPhiPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_21:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB3_22
# %bb.23:
leaq -255(%r14), %r15
leaq -128(%r14), %rdx
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_25
# %bb.24:
movq 80(%rsp), %rax
movq 104(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 40(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z4ScanPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_25:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB3_26
# %bb.27:
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_29
# %bb.28:
movq 88(%rsp), %rax
movq 104(%rsp), %rcx
movq 160(%rsp), %rdx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
movq %rdx, 40(%rsp)
movl %ebp, 124(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 124(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
movq %rsp, %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z9CountSortPhPiS_i, %edi
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_29:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB3_30
# %bb.31:
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB3_32
# %bb.33:
movq 72(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB3_34
# %bb.35:
movq 96(%rsp), %rsi
movq 72(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB3_36
# %bb.37:
movq 96(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB3_38
# %bb.39:
movq 72(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB3_40
# %bb.41:
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 160(%rsp), %rsi
movslq 68(%rsp), %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_42
# %bb.43:
movq 88(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_44
# %bb.45:
movq 80(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_46
# %bb.47:
movq 104(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_48
# %bb.49:
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_1:
.cfi_def_cfa_offset 208
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $179, %ecx
jmp .LBB3_2
.LBB3_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $180, %ecx
jmp .LBB3_2
.LBB3_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $182, %ecx
jmp .LBB3_2
.LBB3_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $183, %ecx
jmp .LBB3_2
.LBB3_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $185, %ecx
jmp .LBB3_2
.LBB3_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $186, %ecx
jmp .LBB3_2
.LBB3_14:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $187, %ecx
jmp .LBB3_2
.LBB3_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $189, %ecx
jmp .LBB3_2
.LBB3_18:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $191, %ecx
jmp .LBB3_2
.LBB3_22:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $195, %ecx
jmp .LBB3_2
.LBB3_26:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $199, %ecx
jmp .LBB3_2
.LBB3_30:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $203, %ecx
jmp .LBB3_2
.LBB3_32:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $205, %ecx
jmp .LBB3_2
.LBB3_34:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $206, %ecx
jmp .LBB3_2
.LBB3_36:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $208, %ecx
jmp .LBB3_2
.LBB3_38:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $209, %ecx
jmp .LBB3_2
.LBB3_40:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $210, %ecx
jmp .LBB3_2
.LBB3_42:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $213, %ecx
jmp .LBB3_2
.LBB3_44:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $219, %ecx
jmp .LBB3_2
.LBB3_46:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $220, %ecx
jmp .LBB3_2
.LBB3_48:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $221, %ecx
.LBB3_2:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
xorl %edi, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9HistogramPhiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4ScanPiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9CountSortPhPiS_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9HistogramPhiPi,@object # @_Z9HistogramPhiPi
.section .rodata,"a",@progbits
.globl _Z9HistogramPhiPi
.p2align 3, 0x0
_Z9HistogramPhiPi:
.quad _Z24__device_stub__HistogramPhiPi
.size _Z9HistogramPhiPi, 8
.type _Z4ScanPiS_,@object # @_Z4ScanPiS_
.globl _Z4ScanPiS_
.p2align 3, 0x0
_Z4ScanPiS_:
.quad _Z19__device_stub__ScanPiS_
.size _Z4ScanPiS_, 8
.type _Z9CountSortPhPiS_i,@object # @_Z9CountSortPhPiS_i
.globl _Z9CountSortPhPiS_i
.p2align 3, 0x0
_Z9CountSortPhPiS_i:
.quad _Z24__device_stub__CountSortPhPiS_i
.size _Z9CountSortPhPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "rb"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CUDA Error in %s:%d: %s\n"
.size .L.str.1, 25
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/lveltman/PGP/master/lab5/lab5_time.hip"
.size .L.str.2, 96
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Time : %f ms \n"
.size .L.str.3, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9HistogramPhiPi"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z4ScanPiS_"
.size .L__unnamed_2, 12
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z9CountSortPhPiS_i"
.size .L__unnamed_3, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__HistogramPhiPi
.addrsig_sym _Z19__device_stub__ScanPiS_
.addrsig_sym _Z24__device_stub__CountSortPhPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9HistogramPhiPi
.addrsig_sym _Z4ScanPiS_
.addrsig_sym _Z9CountSortPhPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <iostream>
#include <thrust/sort.h>
using namespace std;
bool searchFunction(int *array, int *array2, int k, int m){
int first = array2[k];
int second = array[k];
for (int i=0; i<m; i++){
if (array[i]>first){
return false;
}
else if (array[i]==first){
if (array2[i]==second){
return true;
}
}
}
return false;
}
int main(int argc, char const *argv[])
{
/* code */
string a, b;
int n, m;
cin>>a>>b>>n>>m;
int *array = new int [m];
int *array2 = new int [m];
cout<<a<<" "<<b<<" "<<n<<" "<<m<<endl;
for (int i = 0; i < m; ++i)
{
/* code */
int start;
int end;
// char c;
cin>>start>>end;
array[i]=start;
array2[i]=end;
//
}
// for (int i=0; i<2*m; i++){
// cout<<array[i]<<"\t"<<array2[i]<<endl;
// }
thrust::sort_by_key(array2, array2 + m, array);
thrust::sort_by_key(array, array + m, array2);
int count = 1;
// cout<<array[0]<<"\t"<<array2[0]<<endl;
for (int i=1; i<m; i++){
if (array[i] < array2[i]){
// cout<<array[i]<<"\t"<<array2[i]<<endl;
count++;
}
else if (!searchFunction(array, array2, i, m)){
// cout<<array[i]<<"\t"<<array2[i]<<endl;
count++;
}
}
cout<<"m "<<count<<endl;
return 0;
}
|
code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <iostream>
#include <thrust/sort.h>
using namespace std;
bool searchFunction(int *array, int *array2, int k, int m){
int first = array2[k];
int second = array[k];
for (int i=0; i<m; i++){
if (array[i]>first){
return false;
}
else if (array[i]==first){
if (array2[i]==second){
return true;
}
}
}
return false;
}
int main(int argc, char const *argv[])
{
/* code */
string a, b;
int n, m;
cin>>a>>b>>n>>m;
int *array = new int [m];
int *array2 = new int [m];
cout<<a<<" "<<b<<" "<<n<<" "<<m<<endl;
for (int i = 0; i < m; ++i)
{
/* code */
int start;
int end;
// char c;
cin>>start>>end;
array[i]=start;
array2[i]=end;
//
}
// for (int i=0; i<2*m; i++){
// cout<<array[i]<<"\t"<<array2[i]<<endl;
// }
thrust::sort_by_key(array2, array2 + m, array);
thrust::sort_by_key(array, array + m, array2);
int count = 1;
// cout<<array[0]<<"\t"<<array2[0]<<endl;
for (int i=1; i<m; i++){
if (array[i] < array2[i]){
// cout<<array[i]<<"\t"<<array2[i]<<endl;
count++;
}
else if (!searchFunction(array, array2, i, m)){
// cout<<array[i]<<"\t"<<array2[i]<<endl;
count++;
}
}
cout<<"m "<<count<<endl;
return 0;
}
|
#include <hip/hip_runtime.h>
#include <iostream>
#include <thrust/sort.h>
using namespace std;
bool searchFunction(int *array, int *array2, int k, int m){
int first = array2[k];
int second = array[k];
for (int i=0; i<m; i++){
if (array[i]>first){
return false;
}
else if (array[i]==first){
if (array2[i]==second){
return true;
}
}
}
return false;
}
int main(int argc, char const *argv[])
{
/* code */
string a, b;
int n, m;
cin>>a>>b>>n>>m;
int *array = new int [m];
int *array2 = new int [m];
cout<<a<<" "<<b<<" "<<n<<" "<<m<<endl;
for (int i = 0; i < m; ++i)
{
/* code */
int start;
int end;
// char c;
cin>>start>>end;
array[i]=start;
array2[i]=end;
//
}
// for (int i=0; i<2*m; i++){
// cout<<array[i]<<"\t"<<array2[i]<<endl;
// }
thrust::sort_by_key(array2, array2 + m, array);
thrust::sort_by_key(array, array + m, array2);
int count = 1;
// cout<<array[0]<<"\t"<<array2[0]<<endl;
for (int i=1; i<m; i++){
if (array[i] < array2[i]){
// cout<<array[i]<<"\t"<<array2[i]<<endl;
count++;
}
else if (!searchFunction(array, array2, i, m)){
// cout<<array[i]<<"\t"<<array2[i]<<endl;
count++;
}
}
cout<<"m "<<count<<endl;
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <iostream>
#include <thrust/sort.h>
using namespace std;
bool searchFunction(int *array, int *array2, int k, int m){
int first = array2[k];
int second = array[k];
for (int i=0; i<m; i++){
if (array[i]>first){
return false;
}
else if (array[i]==first){
if (array2[i]==second){
return true;
}
}
}
return false;
}
int main(int argc, char const *argv[])
{
/* code */
string a, b;
int n, m;
cin>>a>>b>>n>>m;
int *array = new int [m];
int *array2 = new int [m];
cout<<a<<" "<<b<<" "<<n<<" "<<m<<endl;
for (int i = 0; i < m; ++i)
{
/* code */
int start;
int end;
// char c;
cin>>start>>end;
array[i]=start;
array2[i]=end;
//
}
// for (int i=0; i<2*m; i++){
// cout<<array[i]<<"\t"<<array2[i]<<endl;
// }
thrust::sort_by_key(array2, array2 + m, array);
thrust::sort_by_key(array, array + m, array2);
int count = 1;
// cout<<array[0]<<"\t"<<array2[0]<<endl;
for (int i=1; i<m; i++){
if (array[i] < array2[i]){
// cout<<array[i]<<"\t"<<array2[i]<<endl;
count++;
}
else if (!searchFunction(array, array2, i, m)){
// cout<<array[i]<<"\t"<<array2[i]<<endl;
count++;
}
}
cout<<"m "<<count<<endl;
return 0;
}
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void kernel(const unsigned char * src, unsigned char * dst, int level, const size_t width, const size_t height)
{
const size_t xIndex = blockIdx.x * blockDim.x + threadIdx.x;
const size_t yIndex = blockIdx.y * blockDim.y + threadIdx.y;
if (xIndex < width && yIndex < height)
{
size_t o = yIndex * width + xIndex;
if (level == 256)
{
*(dst + o) = 0;
}
else
{
*(dst + o) = (*(src + o) >= level) ? 255 : 0;
}
// Notice how the below version avoids having an 'if' statement.
// I wonder if this is truly correct - I'll have to test this
// carefully someday but it works correctly. I figured the
// subtraction should cause an underflow which the shift might
// propagate through the rest of the byte so as to cause 255.
// *(dst + o) = ~((*(src + o) - level - 1) >> 7);
}
}
|
code for sm_80
Function : _Z6kernelPKhPhimm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0030*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R0 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.U32.AND P1, PT, R3, c[0x0][0x180], PT ; /* 0x0000600003007a0c */
/* 0x000fe20003f26070 */
/*0070*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x002fc600078e0205 */
/*0080*/ ISETP.GE.U32.AND.EX P1, PT, RZ, c[0x0][0x184], PT, P1 ; /* 0x00006100ff007a0c */
/* 0x000fe40003f26110 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fc80003f06070 */
/*00a0*/ ISETP.GE.U32.OR.EX P0, PT, RZ, c[0x0][0x17c], P1, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0000f06500 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fc600078e00ff */
/*00f0*/ ISETP.NE.AND P0, PT, R6, 0x100, PT ; /* 0x000001000600780c */
/* 0x000fe20003f05270 */
/*0100*/ IMAD.WIDE.U32 R4, R3, c[0x0][0x178], R4 ; /* 0x00005e0003047a25 */
/* 0x000fc800078e0004 */
/*0110*/ IMAD R0, R3, c[0x0][0x17c], R5 ; /* 0x00005f0003007a24 */
/* 0x000fe200078e0205 */
/*0120*/ IADD3 R2, P1, R4, c[0x0][0x168], RZ ; /* 0x00005a0004027a10 */
/* 0x000fc80007f3e0ff */
/*0130*/ IADD3.X R3, R0, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000037a10 */
/* 0x000fc60000ffe4ff */
/*0140*/ @!P0 BRA 0x1c0 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R4, P0, R4, c[0x0][0x160], RZ ; /* 0x0000580004047a10 */
/* 0x000fc80007f1e0ff */
/*0160*/ IADD3.X R5, R0, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000057a10 */
/* 0x000fca00007fe4ff */
/*0170*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1100 */
/*0180*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x004fc80003f06270 */
/*0190*/ SEL R7, RZ, 0xff, !P0 ; /* 0x000000ffff077807 */
/* 0x000fca0004000000 */
/*01a0*/ STG.E.U8 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101104 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101104 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void kernel(const unsigned char * src, unsigned char * dst, int level, const size_t width, const size_t height)
{
const size_t xIndex = blockIdx.x * blockDim.x + threadIdx.x;
const size_t yIndex = blockIdx.y * blockDim.y + threadIdx.y;
if (xIndex < width && yIndex < height)
{
size_t o = yIndex * width + xIndex;
if (level == 256)
{
*(dst + o) = 0;
}
else
{
*(dst + o) = (*(src + o) >= level) ? 255 : 0;
}
// Notice how the below version avoids having an 'if' statement.
// I wonder if this is truly correct - I'll have to test this
// carefully someday but it works correctly. I figured the
// subtraction should cause an underflow which the shift might
// propagate through the rest of the byte so as to cause 255.
// *(dst + o) = ~((*(src + o) - level - 1) >> 7);
}
}
|
.file "tmpxft_00064058_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z6kernelPKhPhimmPKhPhimm
.type _Z31__device_stub__Z6kernelPKhPhimmPKhPhimm, @function
_Z31__device_stub__Z6kernelPKhPhimmPKhPhimm:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6kernelPKhPhimm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z6kernelPKhPhimmPKhPhimm, .-_Z31__device_stub__Z6kernelPKhPhimmPKhPhimm
.globl _Z6kernelPKhPhimm
.type _Z6kernelPKhPhimm, @function
_Z6kernelPKhPhimm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6kernelPKhPhimmPKhPhimm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6kernelPKhPhimm, .-_Z6kernelPKhPhimm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelPKhPhimm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPKhPhimm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void kernel(const unsigned char * src, unsigned char * dst, int level, const size_t width, const size_t height)
{
const size_t xIndex = blockIdx.x * blockDim.x + threadIdx.x;
const size_t yIndex = blockIdx.y * blockDim.y + threadIdx.y;
if (xIndex < width && yIndex < height)
{
size_t o = yIndex * width + xIndex;
if (level == 256)
{
*(dst + o) = 0;
}
else
{
*(dst + o) = (*(src + o) >= level) ? 255 : 0;
}
// Notice how the below version avoids having an 'if' statement.
// I wonder if this is truly correct - I'll have to test this
// carefully someday but it works correctly. I figured the
// subtraction should cause an underflow which the shift might
// propagate through the rest of the byte so as to cause 255.
// *(dst + o) = ~((*(src + o) - level - 1) >> 7);
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel(const unsigned char * src, unsigned char * dst, int level, const size_t width, const size_t height)
{
const size_t xIndex = blockIdx.x * blockDim.x + threadIdx.x;
const size_t yIndex = blockIdx.y * blockDim.y + threadIdx.y;
if (xIndex < width && yIndex < height)
{
size_t o = yIndex * width + xIndex;
if (level == 256)
{
*(dst + o) = 0;
}
else
{
*(dst + o) = (*(src + o) >= level) ? 255 : 0;
}
// Notice how the below version avoids having an 'if' statement.
// I wonder if this is truly correct - I'll have to test this
// carefully someday but it works correctly. I figured the
// subtraction should cause an underflow which the shift might
// propagate through the rest of the byte so as to cause 255.
// *(dst + o) = ~((*(src + o) - level - 1) >> 7);
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel(const unsigned char * src, unsigned char * dst, int level, const size_t width, const size_t height)
{
const size_t xIndex = blockIdx.x * blockDim.x + threadIdx.x;
const size_t yIndex = blockIdx.y * blockDim.y + threadIdx.y;
if (xIndex < width && yIndex < height)
{
size_t o = yIndex * width + xIndex;
if (level == 256)
{
*(dst + o) = 0;
}
else
{
*(dst + o) = (*(src + o) >= level) ? 255 : 0;
}
// Notice how the below version avoids having an 'if' statement.
// I wonder if this is truly correct - I'll have to test this
// carefully someday but it works correctly. I figured the
// subtraction should cause an underflow which the shift might
// propagate through the rest of the byte so as to cause 255.
// *(dst + o) = ~((*(src + o) - level - 1) >> 7);
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPKhPhimm
.globl _Z6kernelPKhPhimm
.p2align 8
.type _Z6kernelPKhPhimm,@function
_Z6kernelPKhPhimm:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mov_b32_e32 v3, 0
v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mov_b32_e32 v5, v3
v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s2, s[6:7], v[4:5]
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
s_load_b32 s2, s[0:1], 0x10
v_mad_u64_u32 v[0:1], null, v4, s4, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v4, s5, v[1:2]
v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, 0
s_waitcnt lgkmcnt(0)
s_cmpk_eq_i32 s2, 0x100
s_cbranch_scc1 .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_load_u8 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_le_i32_e32 vcc_lo, s2, v2
v_cndmask_b32_e64 v2, 0, -1, vcc_lo
.LBB0_3:
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b8 v[0:1], v2, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPKhPhimm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPKhPhimm, .Lfunc_end0-_Z6kernelPKhPhimm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPKhPhimm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPKhPhimm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel(const unsigned char * src, unsigned char * dst, int level, const size_t width, const size_t height)
{
const size_t xIndex = blockIdx.x * blockDim.x + threadIdx.x;
const size_t yIndex = blockIdx.y * blockDim.y + threadIdx.y;
if (xIndex < width && yIndex < height)
{
size_t o = yIndex * width + xIndex;
if (level == 256)
{
*(dst + o) = 0;
}
else
{
*(dst + o) = (*(src + o) >= level) ? 255 : 0;
}
// Notice how the below version avoids having an 'if' statement.
// I wonder if this is truly correct - I'll have to test this
// carefully someday but it works correctly. I figured the
// subtraction should cause an underflow which the shift might
// propagate through the rest of the byte so as to cause 255.
// *(dst + o) = ~((*(src + o) - level - 1) >> 7);
}
}
|
.text
.file "kernel.hip"
.globl _Z21__device_stub__kernelPKhPhimm # -- Begin function _Z21__device_stub__kernelPKhPhimm
.p2align 4, 0x90
.type _Z21__device_stub__kernelPKhPhimm,@function
_Z21__device_stub__kernelPKhPhimm: # @_Z21__device_stub__kernelPKhPhimm
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6kernelPKhPhimm, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPKhPhimm, .Lfunc_end0-_Z21__device_stub__kernelPKhPhimm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPKhPhimm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPKhPhimm,@object # @_Z6kernelPKhPhimm
.section .rodata,"a",@progbits
.globl _Z6kernelPKhPhimm
.p2align 3, 0x0
_Z6kernelPKhPhimm:
.quad _Z21__device_stub__kernelPKhPhimm
.size _Z6kernelPKhPhimm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelPKhPhimm"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPKhPhimm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPKhPhimm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z6kernelPKhPhimm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0030*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R0 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.U32.AND P1, PT, R3, c[0x0][0x180], PT ; /* 0x0000600003007a0c */
/* 0x000fe20003f26070 */
/*0070*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x002fc600078e0205 */
/*0080*/ ISETP.GE.U32.AND.EX P1, PT, RZ, c[0x0][0x184], PT, P1 ; /* 0x00006100ff007a0c */
/* 0x000fe40003f26110 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fc80003f06070 */
/*00a0*/ ISETP.GE.U32.OR.EX P0, PT, RZ, c[0x0][0x17c], P1, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0000f06500 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fc600078e00ff */
/*00f0*/ ISETP.NE.AND P0, PT, R6, 0x100, PT ; /* 0x000001000600780c */
/* 0x000fe20003f05270 */
/*0100*/ IMAD.WIDE.U32 R4, R3, c[0x0][0x178], R4 ; /* 0x00005e0003047a25 */
/* 0x000fc800078e0004 */
/*0110*/ IMAD R0, R3, c[0x0][0x17c], R5 ; /* 0x00005f0003007a24 */
/* 0x000fe200078e0205 */
/*0120*/ IADD3 R2, P1, R4, c[0x0][0x168], RZ ; /* 0x00005a0004027a10 */
/* 0x000fc80007f3e0ff */
/*0130*/ IADD3.X R3, R0, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000037a10 */
/* 0x000fc60000ffe4ff */
/*0140*/ @!P0 BRA 0x1c0 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R4, P0, R4, c[0x0][0x160], RZ ; /* 0x0000580004047a10 */
/* 0x000fc80007f1e0ff */
/*0160*/ IADD3.X R5, R0, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000057a10 */
/* 0x000fca00007fe4ff */
/*0170*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1100 */
/*0180*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x004fc80003f06270 */
/*0190*/ SEL R7, RZ, 0xff, !P0 ; /* 0x000000ffff077807 */
/* 0x000fca0004000000 */
/*01a0*/ STG.E.U8 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101104 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101104 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPKhPhimm
.globl _Z6kernelPKhPhimm
.p2align 8
.type _Z6kernelPKhPhimm,@function
_Z6kernelPKhPhimm:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mov_b32_e32 v3, 0
v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mov_b32_e32 v5, v3
v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s2, s[6:7], v[4:5]
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
s_load_b32 s2, s[0:1], 0x10
v_mad_u64_u32 v[0:1], null, v4, s4, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v4, s5, v[1:2]
v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, 0
s_waitcnt lgkmcnt(0)
s_cmpk_eq_i32 s2, 0x100
s_cbranch_scc1 .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_load_u8 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_le_i32_e32 vcc_lo, s2, v2
v_cndmask_b32_e64 v2, 0, -1, vcc_lo
.LBB0_3:
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b8 v[0:1], v2, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPKhPhimm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPKhPhimm, .Lfunc_end0-_Z6kernelPKhPhimm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPKhPhimm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPKhPhimm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00064058_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z6kernelPKhPhimmPKhPhimm
.type _Z31__device_stub__Z6kernelPKhPhimmPKhPhimm, @function
_Z31__device_stub__Z6kernelPKhPhimmPKhPhimm:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6kernelPKhPhimm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z6kernelPKhPhimmPKhPhimm, .-_Z31__device_stub__Z6kernelPKhPhimmPKhPhimm
.globl _Z6kernelPKhPhimm
.type _Z6kernelPKhPhimm, @function
_Z6kernelPKhPhimm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6kernelPKhPhimmPKhPhimm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6kernelPKhPhimm, .-_Z6kernelPKhPhimm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelPKhPhimm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPKhPhimm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "kernel.hip"
.globl _Z21__device_stub__kernelPKhPhimm # -- Begin function _Z21__device_stub__kernelPKhPhimm
.p2align 4, 0x90
.type _Z21__device_stub__kernelPKhPhimm,@function
_Z21__device_stub__kernelPKhPhimm: # @_Z21__device_stub__kernelPKhPhimm
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6kernelPKhPhimm, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPKhPhimm, .Lfunc_end0-_Z21__device_stub__kernelPKhPhimm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPKhPhimm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPKhPhimm,@object # @_Z6kernelPKhPhimm
.section .rodata,"a",@progbits
.globl _Z6kernelPKhPhimm
.p2align 3, 0x0
_Z6kernelPKhPhimm:
.quad _Z21__device_stub__kernelPKhPhimm
.size _Z6kernelPKhPhimm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelPKhPhimm"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPKhPhimm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPKhPhimm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
/*
Boggle Environment - Board and Tile Class
Miguel Aroca-Ouellette
05/14/2016
*/
#include <iostream>
#include <stdlib.h>
#include <string>
#include <cassert>
#include <time.h>
#include "boggle_env.cuh"
#define NUM_LETTERS 26
/*Constructor: Set dimensions of board.*/
CUDA_CALLABLE_MEMBER
Board::Board(int _width, int _height)
{
width = _width;
height = _height;
grid = (Tile *)malloc(sizeof(Tile)*height*width);
}
/* Destructor */
CUDA_CALLABLE_MEMBER
Board::~Board()
{
free(grid);
}
/*Copy construtor*/
CUDA_CALLABLE_MEMBER
Board::Board(const Board &obj)
{
//printf("Copy constructor allocating grid.\n");
width = obj.width;
height = obj.height;
grid = (Tile *)malloc(sizeof(Tile)*height*width);
for (int y = 0; y < height; y++)
{
for (int x = 0; x < width; x++)
{
grid[x + y*width].letter = obj.grid[x + y*width].letter;
grid[x + y*width].x = x;
grid[x + y*width].y = y;
grid[x + y*width].used = false;
for (int i = 0; i < NUM_ADJ; i++)
{
grid[x + y*width].adj_available[i] = true;
grid[x + y*width].adj_list[i] = NULL;
}
getAllAdj(&grid[x + y*width], grid[x + y*width].adj_list);
}
}
}
/*Populates the board with random letters.*/
void Board::genRandLetters()
{
//random seed
for (int y = 0; y < height; y++)
{
for (int x = 0; x < width; x++)
{
//get random number between 0 and 25 -> letters
char rand_char = 'a' + rand() % NUM_LETTERS;
grid[x + y*width].letter = rand_char;
grid[x + y*width].x = x;
grid[x + y*width].y = y;
grid[x + y*width].used = false;
for (int i = 0; i < NUM_ADJ; i++)
{
grid[x + y*width].adj_available[i] = true;
grid[x + y*width].adj_list[i] = NULL;
}
getAllAdj(&grid[x + y*width], grid[x + y*width].adj_list);
}
}
}
/*Set letters. Ensure that it is the right size.*/
void Board::setLetters(string letters)
{
assert(letters.length() == width*height);
int x, y;
for (int i = 0; i < (width*height); i++)
{
x = i % width;
y = i / width;
grid[x+y*width].x = x;
grid[x+y*width].y = y;
grid[x+y*width].letter = letters[i];
grid[x+y*width].used = false;
for (int i = 0; i < NUM_ADJ; i++)
{
grid[x + y*width].adj_available[i] = true;
grid[x + y*width].adj_list[i] = NULL;
}
getAllAdj(&grid[x + y*width], grid[x + y*width].adj_list);
}
}
/* Returns list of adjancent tiles filtered by adj_available list */
void Board::getAdjList(Tile *center, Tile **adj)
{
for (int i = 0; i < NUM_ADJ; i++)
{
if ((center->adj_list[i] != NULL) && (center->adj_available[i]))
{
adj[i] = center->adj_list[i];
}
else
adj[i] = NULL;
}
}
/*Get adjacent tile letters which are not used. Origin is top left.
Inputs: (x,y) coordinate of center tile.
Pointer to adjacency list to fill. MUST BE ABLE TO ACCOMODATE 8 LETTERS.
Returns indicates size of filled adjacenct list.*/
int Board::getAdj(Tile* center, Tile **adj)
{
int size = 0;
int x = center->x;
int y = center->y;
if ((x > 0) && (y > 0)) //top left
pushTile(adj, x - 1, y - 1, &size, false);
if ((x > 0) && (y < (height - 1))) //bottom left
pushTile(adj, x - 1, y + 1, &size, false);
if ((x < (width - 1)) && (y > 0)) //top right
pushTile(adj, x + 1, y - 1, &size, false);
if ((x < (width - 1)) && (y < (height - 1))) //bottom right
pushTile(adj, x + 1, y + 1, &size, false);
if (y > 0) //top center
pushTile(adj, x, y - 1, &size, false);
if (y < (height - 1)) //bottom center
pushTile(adj, x, y + 1, &size, false);
if (x > 0) //left center
pushTile(adj, x - 1, y, &size, false);
if (x < (width - 1)) //right center
pushTile(adj, x + 1, y, &size, false);
return size;
}
/*Private: Helper function for get_adj. Only assigns the tile if it is unused. Increments counts.*/
void Board::pushTile(Tile **target, int x, int y, int *count, bool all)
{
if ((!grid[x+y*width].used) || all)
target[(*count)++] = &grid[x+y*width];
}
/*Get adjacent tile letters which are not used. Origin is top left.
Inputs: (x,y) coordinate of center tile.
Pointer to adjacency list to fill. MUST BE ABLE TO ACCOMODATE 8 LETTERS.
Returns indicates size of filled adjacenct list.*/
int Board::getAllAdj(Tile* center, Tile **adj)
{
int size = 0;
int x = center->x;
int y = center->y;
if ((x > 0) && (y > 0)) //top left
pushTile(adj, x - 1, y - 1, &size, true);
if ((x > 0) && (y < (height - 1))) //bottom left
pushTile(adj, x - 1, y + 1, &size, true);
if ((x < (width - 1)) && (y > 0)) //top right
pushTile(adj, x + 1, y - 1, &size, true);
if ((x < (width - 1)) && (y < (height - 1))) //bottom right
pushTile(adj, x + 1, y + 1, &size, true);
if (y > 0) //top center
pushTile(adj, x, y - 1, &size, true);
if (y < (height - 1)) //bottom center
pushTile(adj, x, y + 1, &size, true);
if (x > 0) //left center
pushTile(adj, x - 1, y, &size, true);
if (x < (width - 1)) //right center
pushTile(adj, x + 1, y, &size, true);
return size;
}
/* Prints the boggle board*/
void Board::printBoard()
{
for (int y = 0; y < height; y++)
{
for (int x = 0; x < width; x++)
printf("%c ",grid[x+y*width].letter);
printf("\n");
}
}
/* Prints the used tiles as 1, otherwise 0*/
void Board::printUsed()
{
for (int y = 0; y < height; y++)
{
for (int x = 0; x < width; x++)
printf("%c ", ((grid[x + y*width].used) ? grid[x + y*width].letter : ' '));
printf("\n");
}
}
/*Getter for tile.*/
Tile* Board::getTile(int x, int y)
{
return &grid[x+y*width];
}
/*Returns all tiles in the board.*/
void Board::getAllTiles(Tile *all_tiles[])
{
for (int y = 0; y < height; y++)
{
for (int x = 0; x < width; x++)
all_tiles[y*width + x] = getTile(x, y);
}
}
/* Resets all tiles on board to unused*/
void Board::resetBoard()
{
for (int y = 0; y < height; y++)
{
for (int x = 0; x < width; x++)
{
grid[x + y*width].used = false;
for (int i = 0; i < NUM_ADJ; i++)
grid[x + y*width].adj_available[i] = true;
}
}
}
/*Checks if the Tile is in the list of Tiles */
bool checkTileList(Tile *check, Tile **list, int size)
{
for (int i = 0; i < size; i++)
{
if (check == list[i])
return true;
}
return false;
}
/* Returns the number of tiles with this letter. */
int Board::getLetterCount(char c)
{
int count = 0;
for (int y = 0; y < height; y++)
{
for (int x = 0; x < width; x++)
{
if (grid[x + y*width].letter == c)
count++;
}
}
return count;
}
/*Returns all tiles in the board that match a given letter.
Should call getLetterCount before hand to get size.*/
void Board::getTilesByLetter(Tile *all_tiles[], char c)
{
int i = 0;
for (int x = 0; x < height*width; x++)
{
if (grid[x].letter == c)
all_tiles[i++] = &grid[x];
}
}
|
code for sm_80
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
/*
Boggle Environment - Board and Tile Class
Miguel Aroca-Ouellette
05/14/2016
*/
#include <iostream>
#include <stdlib.h>
#include <string>
#include <cassert>
#include <time.h>
#include "boggle_env.cuh"
#define NUM_LETTERS 26
/*Constructor: Set dimensions of board.*/
CUDA_CALLABLE_MEMBER
Board::Board(int _width, int _height)
{
width = _width;
height = _height;
grid = (Tile *)malloc(sizeof(Tile)*height*width);
}
/* Destructor */
CUDA_CALLABLE_MEMBER
Board::~Board()
{
free(grid);
}
/*Copy construtor*/
CUDA_CALLABLE_MEMBER
Board::Board(const Board &obj)
{
//printf("Copy constructor allocating grid.\n");
width = obj.width;
height = obj.height;
grid = (Tile *)malloc(sizeof(Tile)*height*width);
for (int y = 0; y < height; y++)
{
for (int x = 0; x < width; x++)
{
grid[x + y*width].letter = obj.grid[x + y*width].letter;
grid[x + y*width].x = x;
grid[x + y*width].y = y;
grid[x + y*width].used = false;
for (int i = 0; i < NUM_ADJ; i++)
{
grid[x + y*width].adj_available[i] = true;
grid[x + y*width].adj_list[i] = NULL;
}
getAllAdj(&grid[x + y*width], grid[x + y*width].adj_list);
}
}
}
/*Populates the board with random letters.*/
void Board::genRandLetters()
{
//random seed
for (int y = 0; y < height; y++)
{
for (int x = 0; x < width; x++)
{
//get random number between 0 and 25 -> letters
char rand_char = 'a' + rand() % NUM_LETTERS;
grid[x + y*width].letter = rand_char;
grid[x + y*width].x = x;
grid[x + y*width].y = y;
grid[x + y*width].used = false;
for (int i = 0; i < NUM_ADJ; i++)
{
grid[x + y*width].adj_available[i] = true;
grid[x + y*width].adj_list[i] = NULL;
}
getAllAdj(&grid[x + y*width], grid[x + y*width].adj_list);
}
}
}
/*Set letters. Ensure that it is the right size.*/
void Board::setLetters(string letters)
{
assert(letters.length() == width*height);
int x, y;
for (int i = 0; i < (width*height); i++)
{
x = i % width;
y = i / width;
grid[x+y*width].x = x;
grid[x+y*width].y = y;
grid[x+y*width].letter = letters[i];
grid[x+y*width].used = false;
for (int i = 0; i < NUM_ADJ; i++)
{
grid[x + y*width].adj_available[i] = true;
grid[x + y*width].adj_list[i] = NULL;
}
getAllAdj(&grid[x + y*width], grid[x + y*width].adj_list);
}
}
/* Returns list of adjancent tiles filtered by adj_available list */
void Board::getAdjList(Tile *center, Tile **adj)
{
for (int i = 0; i < NUM_ADJ; i++)
{
if ((center->adj_list[i] != NULL) && (center->adj_available[i]))
{
adj[i] = center->adj_list[i];
}
else
adj[i] = NULL;
}
}
/*Get adjacent tile letters which are not used. Origin is top left.
Inputs: (x,y) coordinate of center tile.
Pointer to adjacency list to fill. MUST BE ABLE TO ACCOMODATE 8 LETTERS.
Returns indicates size of filled adjacenct list.*/
int Board::getAdj(Tile* center, Tile **adj)
{
int size = 0;
int x = center->x;
int y = center->y;
if ((x > 0) && (y > 0)) //top left
pushTile(adj, x - 1, y - 1, &size, false);
if ((x > 0) && (y < (height - 1))) //bottom left
pushTile(adj, x - 1, y + 1, &size, false);
if ((x < (width - 1)) && (y > 0)) //top right
pushTile(adj, x + 1, y - 1, &size, false);
if ((x < (width - 1)) && (y < (height - 1))) //bottom right
pushTile(adj, x + 1, y + 1, &size, false);
if (y > 0) //top center
pushTile(adj, x, y - 1, &size, false);
if (y < (height - 1)) //bottom center
pushTile(adj, x, y + 1, &size, false);
if (x > 0) //left center
pushTile(adj, x - 1, y, &size, false);
if (x < (width - 1)) //right center
pushTile(adj, x + 1, y, &size, false);
return size;
}
/*Private: Helper function for get_adj. Only assigns the tile if it is unused. Increments counts.*/
void Board::pushTile(Tile **target, int x, int y, int *count, bool all)
{
if ((!grid[x+y*width].used) || all)
target[(*count)++] = &grid[x+y*width];
}
/*Get adjacent tile letters which are not used. Origin is top left.
Inputs: (x,y) coordinate of center tile.
Pointer to adjacency list to fill. MUST BE ABLE TO ACCOMODATE 8 LETTERS.
Returns indicates size of filled adjacenct list.*/
int Board::getAllAdj(Tile* center, Tile **adj)
{
int size = 0;
int x = center->x;
int y = center->y;
if ((x > 0) && (y > 0)) //top left
pushTile(adj, x - 1, y - 1, &size, true);
if ((x > 0) && (y < (height - 1))) //bottom left
pushTile(adj, x - 1, y + 1, &size, true);
if ((x < (width - 1)) && (y > 0)) //top right
pushTile(adj, x + 1, y - 1, &size, true);
if ((x < (width - 1)) && (y < (height - 1))) //bottom right
pushTile(adj, x + 1, y + 1, &size, true);
if (y > 0) //top center
pushTile(adj, x, y - 1, &size, true);
if (y < (height - 1)) //bottom center
pushTile(adj, x, y + 1, &size, true);
if (x > 0) //left center
pushTile(adj, x - 1, y, &size, true);
if (x < (width - 1)) //right center
pushTile(adj, x + 1, y, &size, true);
return size;
}
/* Prints the boggle board*/
void Board::printBoard()
{
for (int y = 0; y < height; y++)
{
for (int x = 0; x < width; x++)
printf("%c ",grid[x+y*width].letter);
printf("\n");
}
}
/* Prints the used tiles as 1, otherwise 0*/
void Board::printUsed()
{
for (int y = 0; y < height; y++)
{
for (int x = 0; x < width; x++)
printf("%c ", ((grid[x + y*width].used) ? grid[x + y*width].letter : ' '));
printf("\n");
}
}
/*Getter for tile.*/
Tile* Board::getTile(int x, int y)
{
return &grid[x+y*width];
}
/*Returns all tiles in the board.*/
void Board::getAllTiles(Tile *all_tiles[])
{
for (int y = 0; y < height; y++)
{
for (int x = 0; x < width; x++)
all_tiles[y*width + x] = getTile(x, y);
}
}
/* Resets all tiles on board to unused*/
void Board::resetBoard()
{
for (int y = 0; y < height; y++)
{
for (int x = 0; x < width; x++)
{
grid[x + y*width].used = false;
for (int i = 0; i < NUM_ADJ; i++)
grid[x + y*width].adj_available[i] = true;
}
}
}
/*Checks if the Tile is in the list of Tiles */
bool checkTileList(Tile *check, Tile **list, int size)
{
for (int i = 0; i < size; i++)
{
if (check == list[i])
return true;
}
return false;
}
/* Returns the number of tiles with this letter. */
int Board::getLetterCount(char c)
{
int count = 0;
for (int y = 0; y < height; y++)
{
for (int x = 0; x < width; x++)
{
if (grid[x + y*width].letter == c)
count++;
}
}
return count;
}
/*Returns all tiles in the board that match a given letter.
Should call getLetterCount before hand to get size.*/
void Board::getTilesByLetter(Tile *all_tiles[], char c)
{
int i = 0;
for (int x = 0; x < height*width; x++)
{
if (grid[x].letter == c)
all_tiles[i++] = &grid[x];
}
}
|
.file "tmpxft_0003880d_00000000-6_boggle_env.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.globl _ZN5BoardC2Eii
.type _ZN5BoardC2Eii, @function
_ZN5BoardC2Eii:
.LFB3673:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movl %esi, (%rdi)
movl %edx, 4(%rdi)
movslq %edx, %rdx
movslq %esi, %rsi
imulq %rsi, %rdx
leaq (%rdx,%rdx,4), %rax
leaq (%rdx,%rax,2), %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, 8(%rbx)
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZN5BoardC2Eii, .-_ZN5BoardC2Eii
.globl _ZN5BoardC1Eii
.set _ZN5BoardC1Eii,_ZN5BoardC2Eii
.align 2
.globl _ZN5BoardD2Ev
.type _ZN5BoardD2Ev, @function
_ZN5BoardD2Ev:
.LFB3676:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 8(%rdi), %rdi
call free@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3676:
.size _ZN5BoardD2Ev, .-_ZN5BoardD2Ev
.globl _ZN5BoardD1Ev
.set _ZN5BoardD1Ev,_ZN5BoardD2Ev
.align 2
.globl _ZN5Board10getAdjListEP4TilePS1_
.type _ZN5Board10getAdjListEP4TilePS1_, @function
_ZN5Board10getAdjListEP4TilePS1_:
.LFB3683:
.cfi_startproc
endbr64
movl $0, %eax
movl $0, %edi
jmp .L9
.L8:
movq %rcx, (%rdx,%rax,8)
addq $1, %rax
cmpq $8, %rax
je .L12
.L9:
movq 24(%rsi,%rax,8), %rcx
testq %rcx, %rcx
je .L8
cmpb $0, 10(%rsi,%rax)
cmove %rdi, %rcx
jmp .L8
.L12:
ret
.cfi_endproc
.LFE3683:
.size _ZN5Board10getAdjListEP4TilePS1_, .-_ZN5Board10getAdjListEP4TilePS1_
.align 2
.globl _ZN5Board8pushTileEPP4TileiiPib
.type _ZN5Board8pushTileEPP4TileiiPib, @function
_ZN5Board8pushTileEPP4TileiiPib:
.LFB3685:
.cfi_startproc
endbr64
imull (%rdi), %ecx
addl %edx, %ecx
movslq %ecx, %rcx
leaq (%rcx,%rcx,4), %rdx
leaq (%rcx,%rdx,2), %rdx
movq 8(%rdi), %rax
leaq (%rax,%rdx,8), %rdx
cmpb $1, 9(%rdx)
jne .L16
testb %r9b, %r9b
je .L13
.L16:
movl (%r8), %eax
leal 1(%rax), %ecx
movl %ecx, (%r8)
cltq
movq %rdx, (%rsi,%rax,8)
.L13:
ret
.cfi_endproc
.LFE3685:
.size _ZN5Board8pushTileEPP4TileiiPib, .-_ZN5Board8pushTileEPP4TileiiPib
.align 2
.globl _ZN5Board6getAdjEP4TilePS1_
.type _ZN5Board6getAdjEP4TilePS1_, @function
_ZN5Board6getAdjEP4TilePS1_:
.LFB3684:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $16, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %rdx, %r13
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $0, 4(%rsp)
movl (%rsi), %ebp
movl 4(%rsi), %r12d
testl %r12d, %r12d
setg %r14b
testl %ebp, %ebp
jle .L18
testb %r14b, %r14b
jne .L37
.L18:
testl %ebp, %ebp
jg .L38
.L20:
movl (%rbx), %eax
subl $1, %eax
cmpl %ebp, %eax
setg %al
testb %r14b, %r14b
je .L22
testb %al, %al
jne .L39
.L22:
testb %al, %al
jne .L25
.L26:
testl %r12d, %r12d
jle .L27
.L24:
leal -1(%r12), %ecx
movl $0, %r9d
leaq 4(%rsp), %r8
movl %ebp, %edx
movq %r13, %rsi
movq %rbx, %rdi
call _ZN5Board8pushTileEPP4TileiiPib
.L27:
movl 4(%rbx), %eax
subl $1, %eax
cmpl %r12d, %eax
jg .L40
.L28:
testl %ebp, %ebp
jg .L41
.L29:
movl (%rbx), %eax
subl $1, %eax
cmpl %ebp, %eax
jg .L42
.L30:
movl 4(%rsp), %eax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L43
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
leal -1(%r12), %ecx
leal -1(%rbp), %edx
movl $0, %r9d
leaq 4(%rsp), %r8
movq %r13, %rsi
call _ZN5Board8pushTileEPP4TileiiPib
movl 4(%rbx), %eax
subl $1, %eax
cmpl %r12d, %eax
jle .L20
.L19:
leal 1(%r12), %ecx
leal -1(%rbp), %edx
movl $0, %r9d
leaq 4(%rsp), %r8
movq %r13, %rsi
movq %rbx, %rdi
call _ZN5Board8pushTileEPP4TileiiPib
jmp .L20
.L39:
leal -1(%r12), %ecx
leal 1(%rbp), %edx
movl $0, %r9d
leaq 4(%rsp), %r8
movq %r13, %rsi
movq %rbx, %rdi
call _ZN5Board8pushTileEPP4TileiiPib
movl (%rbx), %eax
subl $1, %eax
cmpl %eax, %ebp
jge .L24
movl 4(%rbx), %eax
subl $1, %eax
cmpl %eax, %r12d
jge .L24
jmp .L31
.L40:
leal 1(%r12), %ecx
movl $0, %r9d
leaq 4(%rsp), %r8
movl %ebp, %edx
movq %r13, %rsi
movq %rbx, %rdi
call _ZN5Board8pushTileEPP4TileiiPib
jmp .L28
.L41:
leal -1(%rbp), %edx
movl $0, %r9d
leaq 4(%rsp), %r8
movl %r12d, %ecx
movq %r13, %rsi
movq %rbx, %rdi
call _ZN5Board8pushTileEPP4TileiiPib
jmp .L29
.L42:
leal 1(%rbp), %edx
movl $0, %r9d
leaq 4(%rsp), %r8
movl %r12d, %ecx
movq %r13, %rsi
movq %rbx, %rdi
call _ZN5Board8pushTileEPP4TileiiPib
jmp .L30
.L25:
movl 4(%rbx), %eax
subl $1, %eax
cmpl %eax, %r12d
jge .L28
.L31:
leal 1(%r12), %ecx
leal 1(%rbp), %edx
movl $0, %r9d
leaq 4(%rsp), %r8
movq %r13, %rsi
movq %rbx, %rdi
call _ZN5Board8pushTileEPP4TileiiPib
jmp .L26
.L38:
movl 4(%rbx), %eax
subl $1, %eax
cmpl %eax, %r12d
jl .L19
movl (%rbx), %eax
subl $1, %eax
cmpl %eax, %ebp
setl %al
jmp .L22
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3684:
.size _ZN5Board6getAdjEP4TilePS1_, .-_ZN5Board6getAdjEP4TilePS1_
.align 2
.globl _ZN5Board9getAllAdjEP4TilePS1_
.type _ZN5Board9getAllAdjEP4TilePS1_, @function
_ZN5Board9getAllAdjEP4TilePS1_:
.LFB3686:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $16, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %rdx, %r13
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $0, 4(%rsp)
movl (%rsi), %ebp
movl 4(%rsi), %r12d
testl %r12d, %r12d
setg %r14b
testl %ebp, %ebp
jle .L45
testb %r14b, %r14b
jne .L64
.L45:
testl %ebp, %ebp
jg .L65
.L47:
movl (%rbx), %eax
subl $1, %eax
cmpl %ebp, %eax
setg %al
testb %r14b, %r14b
je .L49
testb %al, %al
jne .L66
.L49:
testb %al, %al
jne .L52
.L53:
testl %r12d, %r12d
jle .L54
.L51:
leal -1(%r12), %ecx
movl $1, %r9d
leaq 4(%rsp), %r8
movl %ebp, %edx
movq %r13, %rsi
movq %rbx, %rdi
call _ZN5Board8pushTileEPP4TileiiPib
.L54:
movl 4(%rbx), %eax
subl $1, %eax
cmpl %r12d, %eax
jg .L67
.L55:
testl %ebp, %ebp
jg .L68
.L56:
movl (%rbx), %eax
subl $1, %eax
cmpl %ebp, %eax
jg .L69
.L57:
movl 4(%rsp), %eax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L70
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L64:
.cfi_restore_state
leal -1(%r12), %ecx
leal -1(%rbp), %edx
movl $1, %r9d
leaq 4(%rsp), %r8
movq %r13, %rsi
call _ZN5Board8pushTileEPP4TileiiPib
movl 4(%rbx), %eax
subl $1, %eax
cmpl %r12d, %eax
jle .L47
.L46:
leal 1(%r12), %ecx
leal -1(%rbp), %edx
movl $1, %r9d
leaq 4(%rsp), %r8
movq %r13, %rsi
movq %rbx, %rdi
call _ZN5Board8pushTileEPP4TileiiPib
jmp .L47
.L66:
leal -1(%r12), %ecx
leal 1(%rbp), %edx
movl $1, %r9d
leaq 4(%rsp), %r8
movq %r13, %rsi
movq %rbx, %rdi
call _ZN5Board8pushTileEPP4TileiiPib
movl (%rbx), %eax
subl $1, %eax
cmpl %eax, %ebp
jge .L51
movl 4(%rbx), %eax
subl $1, %eax
cmpl %eax, %r12d
jge .L51
jmp .L58
.L67:
leal 1(%r12), %ecx
movl $1, %r9d
leaq 4(%rsp), %r8
movl %ebp, %edx
movq %r13, %rsi
movq %rbx, %rdi
call _ZN5Board8pushTileEPP4TileiiPib
jmp .L55
.L68:
leal -1(%rbp), %edx
movl $1, %r9d
leaq 4(%rsp), %r8
movl %r12d, %ecx
movq %r13, %rsi
movq %rbx, %rdi
call _ZN5Board8pushTileEPP4TileiiPib
jmp .L56
.L69:
leal 1(%rbp), %edx
movl $1, %r9d
leaq 4(%rsp), %r8
movl %r12d, %ecx
movq %r13, %rsi
movq %rbx, %rdi
call _ZN5Board8pushTileEPP4TileiiPib
jmp .L57
.L52:
movl 4(%rbx), %eax
subl $1, %eax
cmpl %eax, %r12d
jge .L55
.L58:
leal 1(%r12), %ecx
leal 1(%rbp), %edx
movl $1, %r9d
leaq 4(%rsp), %r8
movq %r13, %rsi
movq %rbx, %rdi
call _ZN5Board8pushTileEPP4TileiiPib
jmp .L53
.L65:
movl 4(%rbx), %eax
subl $1, %eax
cmpl %eax, %r12d
jl .L46
movl (%rbx), %eax
subl $1, %eax
cmpl %eax, %ebp
setl %al
jmp .L49
.L70:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3686:
.size _ZN5Board9getAllAdjEP4TilePS1_, .-_ZN5Board9getAllAdjEP4TilePS1_
.align 2
.globl _ZN5BoardC2ERKS_
.type _ZN5BoardC2ERKS_, @function
_ZN5BoardC2ERKS_:
.LFB3679:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movq %rsi, %r13
movl (%rsi), %edx
movl %edx, (%rdi)
movl 4(%rsi), %ebx
movl %ebx, 4(%rdi)
movslq %ebx, %rax
movslq %edx, %rdx
imulq %rdx, %rax
leaq (%rax,%rax,4), %rdx
leaq (%rax,%rdx,2), %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, 8(%rbp)
movl $0, %r12d
testl %ebx, %ebx
jg .L72
.L71:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L84:
.cfi_restore_state
leaq 24(%rsi), %rdx
movq %rbp, %rdi
call _ZN5Board9getAllAdjEP4TilePS1_
addl $1, %ebx
movl 0(%rbp), %eax
cmpl %ebx, %eax
jle .L76
.L75:
imull %r12d, %eax
addl %ebx, %eax
cltq
leaq (%rax,%rax,4), %rdx
leaq (%rax,%rdx,2), %rax
salq $3, %rax
movq %rax, %rsi
addq 8(%rbp), %rsi
movq 8(%r13), %rdx
movzbl 8(%rdx,%rax), %eax
movb %al, 8(%rsi)
movl %ebx, (%rsi)
movl %r12d, 4(%rsi)
movb $0, 9(%rsi)
movl $0, %eax
.L74:
movb $1, 10(%rsi,%rax)
movq $0, 24(%rsi,%rax,8)
addq $1, %rax
cmpq $8, %rax
jne .L74
jmp .L84
.L76:
addl $1, %r12d
cmpl %r12d, 4(%rbp)
jle .L71
.L72:
movl 0(%rbp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L75
jmp .L76
.cfi_endproc
.LFE3679:
.size _ZN5BoardC2ERKS_, .-_ZN5BoardC2ERKS_
.globl _ZN5BoardC1ERKS_
.set _ZN5BoardC1ERKS_,_ZN5BoardC2ERKS_
.align 2
.globl _ZN5Board14genRandLettersEv
.type _ZN5Board14genRandLettersEv, @function
_ZN5Board14genRandLettersEv:
.LFB3681:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movl $0, %r12d
cmpl $0, 4(%rdi)
jg .L86
.L85:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L98:
.cfi_restore_state
movl %r12d, %eax
imull (%rbx), %eax
addl %ebp, %eax
cltq
leaq (%rax,%rax,4), %rdx
leaq (%rax,%rdx,2), %rdx
movq 8(%rbx), %rax
leaq (%rax,%rdx,8), %rsi
leaq 24(%rsi), %rdx
movq %rbx, %rdi
call _ZN5Board9getAllAdjEP4TilePS1_
addl $1, %ebp
cmpl %ebp, (%rbx)
jle .L90
.L89:
call rand@PLT
movl %r12d, %edx
imull (%rbx), %edx
addl %ebp, %edx
movslq %edx, %rdx
leaq (%rdx,%rdx,4), %rcx
leaq (%rdx,%rcx,2), %rcx
salq $3, %rcx
addq 8(%rbx), %rcx
movslq %eax, %rdx
imulq $1321528399, %rdx, %rdx
sarq $35, %rdx
movl %eax, %esi
sarl $31, %esi
subl %esi, %edx
imull $26, %edx, %edx
subl %edx, %eax
addl $97, %eax
movb %al, 8(%rcx)
movl %r12d, %eax
imull (%rbx), %eax
addl %ebp, %eax
cltq
leaq (%rax,%rax,4), %rdx
leaq (%rax,%rdx,2), %rax
salq $3, %rax
addq 8(%rbx), %rax
movl %ebp, (%rax)
movl %r12d, %eax
imull (%rbx), %eax
addl %ebp, %eax
cltq
leaq (%rax,%rax,4), %rdx
leaq (%rax,%rdx,2), %rax
salq $3, %rax
addq 8(%rbx), %rax
movl %r12d, 4(%rax)
movl %r12d, %eax
imull (%rbx), %eax
addl %ebp, %eax
cltq
leaq (%rax,%rax,4), %rdx
leaq (%rax,%rdx,2), %rax
salq $3, %rax
addq 8(%rbx), %rax
movb $0, 9(%rax)
movl $0, %edx
.L88:
movl %r12d, %eax
imull (%rbx), %eax
addl %ebp, %eax
cltq
leaq (%rax,%rax,4), %rcx
leaq (%rax,%rcx,2), %rax
salq $3, %rax
addq 8(%rbx), %rax
movslq %edx, %rcx
movb $1, 10(%rax,%rcx)
movl %r12d, %eax
imull (%rbx), %eax
addl %ebp, %eax
cltq
leaq (%rax,%rax,4), %rsi
leaq (%rax,%rsi,2), %rax
salq $3, %rax
addq 8(%rbx), %rax
movq $0, 24(%rax,%rcx,8)
addl $1, %edx
cmpl $8, %edx
jne .L88
jmp .L98
.L90:
addl $1, %r12d
cmpl %r12d, 4(%rbx)
jle .L85
.L86:
movl $0, %ebp
cmpl $0, (%rbx)
jg .L89
jmp .L90
.cfi_endproc
.LFE3681:
.size _ZN5Board14genRandLettersEv, .-_ZN5Board14genRandLettersEv
.align 2
.globl _ZN5Board10setLettersENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.type _ZN5Board10setLettersENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, @function
_ZN5Board10setLettersENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE:
.LFB3682:
.cfi_startproc
endbr64
movl (%rdi), %ecx
movl %ecx, %eax
imull 4(%rdi), %eax
testl %eax, %eax
jle .L106
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %rsi, %r13
movl $0, %r12d
movl $0, %ebp
jmp .L102
.L110:
imull (%rbx), %eax
addl %edx, %eax
cltq
leaq (%rax,%rax,4), %rdx
leaq (%rax,%rdx,2), %rdx
movq 8(%rbx), %rax
leaq (%rax,%rdx,8), %rsi
leaq 24(%rsi), %rdx
movq %rbx, %rdi
call _ZN5Board9getAllAdjEP4TilePS1_
movl (%rbx), %ecx
addq $1, %rbp
addq $88, %r12
movl %ecx, %eax
imull 4(%rbx), %eax
cmpl %ebp, %eax
jle .L109
.L102:
movl %ebp, %eax
cltd
idivl %ecx
movq 8(%rbx), %rcx
movl %edx, (%rcx,%r12)
movl %eax, %ecx
imull (%rbx), %ecx
addl %edx, %ecx
movslq %ecx, %rcx
leaq (%rcx,%rcx,4), %rsi
leaq (%rcx,%rsi,2), %rcx
salq $3, %rcx
addq 8(%rbx), %rcx
movl %eax, 4(%rcx)
movq 0(%r13), %rcx
movzbl (%rcx,%rbp), %esi
movl %eax, %ecx
imull (%rbx), %ecx
addl %edx, %ecx
movslq %ecx, %rcx
leaq (%rcx,%rcx,4), %rdi
leaq (%rcx,%rdi,2), %rcx
salq $3, %rcx
addq 8(%rbx), %rcx
movb %sil, 8(%rcx)
movl %eax, %ecx
imull (%rbx), %ecx
addl %edx, %ecx
movslq %ecx, %rcx
leaq (%rcx,%rcx,4), %rsi
leaq (%rcx,%rsi,2), %rcx
salq $3, %rcx
addq 8(%rbx), %rcx
movb $0, 9(%rcx)
movl $0, %esi
.L101:
movl %eax, %ecx
imull (%rbx), %ecx
addl %edx, %ecx
movslq %ecx, %rcx
leaq (%rcx,%rcx,4), %rdi
leaq (%rcx,%rdi,2), %rcx
salq $3, %rcx
addq 8(%rbx), %rcx
movslq %esi, %rdi
movb $1, 10(%rcx,%rdi)
movl %eax, %ecx
imull (%rbx), %ecx
addl %edx, %ecx
movslq %ecx, %rcx
leaq (%rcx,%rcx,4), %r8
leaq (%rcx,%r8,2), %rcx
salq $3, %rcx
addq 8(%rbx), %rcx
movq $0, 24(%rcx,%rdi,8)
addl $1, %esi
cmpl $8, %esi
jne .L101
jmp .L110
.L109:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L106:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE3682:
.size _ZN5Board10setLettersENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .-_ZN5Board10setLettersENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%c "
.LC1:
.string "\n"
.text
.align 2
.globl _ZN5Board10printBoardEv
.type _ZN5Board10printBoardEv, @function
_ZN5Board10printBoardEv:
.LFB3687:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %rbp
movl $0, %r12d
leaq .LC0(%rip), %r13
leaq .LC1(%rip), %r14
cmpl $0, 4(%rdi)
jg .L112
.L111:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L114:
.cfi_restore_state
imull %r12d, %eax
addl %ebx, %eax
cltq
leaq (%rax,%rax,4), %rdx
leaq (%rax,%rdx,2), %rax
salq $3, %rax
addq 8(%rbp), %rax
movsbl 8(%rax), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
movl 0(%rbp), %eax
cmpl %ebx, %eax
jg .L114
.L115:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r12d
cmpl %r12d, 4(%rbp)
jle .L111
.L112:
movl 0(%rbp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L114
jmp .L115
.cfi_endproc
.LFE3687:
.size _ZN5Board10printBoardEv, .-_ZN5Board10printBoardEv
.align 2
.globl _ZN5Board9printUsedEv
.type _ZN5Board9printUsedEv, @function
_ZN5Board9printUsedEv:
.LFB3688:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movl $0, %r12d
leaq .LC0(%rip), %r14
movl $32, %r13d
leaq .LC1(%rip), %r15
cmpl $0, 4(%rdi)
jg .L123
.L122:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L125:
.cfi_restore_state
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
movl 0(%rbp), %eax
cmpl %ebx, %eax
jle .L127
.L126:
imull %r12d, %eax
addl %ebx, %eax
cltq
leaq (%rax,%rax,4), %rdx
leaq (%rax,%rdx,2), %rdx
movq 8(%rbp), %rax
leaq (%rax,%rdx,8), %rax
movl %r13d, %edx
cmpb $0, 9(%rax)
je .L125
movsbl 8(%rax), %edx
jmp .L125
.L127:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r12d
cmpl %r12d, 4(%rbp)
jle .L122
.L123:
movl 0(%rbp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L126
jmp .L127
.cfi_endproc
.LFE3688:
.size _ZN5Board9printUsedEv, .-_ZN5Board9printUsedEv
.align 2
.globl _ZN5Board7getTileEii
.type _ZN5Board7getTileEii, @function
_ZN5Board7getTileEii:
.LFB3689:
.cfi_startproc
endbr64
imull (%rdi), %edx
addl %esi, %edx
movslq %edx, %rdx
leaq (%rdx,%rdx,4), %rax
leaq (%rdx,%rax,2), %rdx
movq 8(%rdi), %rax
leaq (%rax,%rdx,8), %rax
ret
.cfi_endproc
.LFE3689:
.size _ZN5Board7getTileEii, .-_ZN5Board7getTileEii
.align 2
.globl _ZN5Board11getAllTilesEPP4Tile
.type _ZN5Board11getAllTilesEPP4Tile, @function
_ZN5Board11getAllTilesEPP4Tile:
.LFB3690:
.cfi_startproc
endbr64
movl $0, %r9d
cmpl $0, 4(%rdi)
jg .L137
ret
.L139:
imull %r9d, %eax
addl %edx, %eax
cltq
leaq (%rax,%rax,4), %rcx
leaq (%rax,%rcx,2), %r8
movq 8(%rdi), %rcx
leaq (%rcx,%r8,8), %rcx
movq %rcx, (%rsi,%rax,8)
addl $1, %edx
movl (%rdi), %eax
cmpl %edx, %eax
jg .L139
.L140:
addl $1, %r9d
cmpl %r9d, 4(%rdi)
jle .L136
.L137:
movl (%rdi), %eax
movl $0, %edx
testl %eax, %eax
jg .L139
jmp .L140
.L136:
ret
.cfi_endproc
.LFE3690:
.size _ZN5Board11getAllTilesEPP4Tile, .-_ZN5Board11getAllTilesEPP4Tile
.align 2
.globl _ZN5Board10resetBoardEv
.type _ZN5Board10resetBoardEv, @function
_ZN5Board10resetBoardEv:
.LFB3691:
.cfi_startproc
endbr64
movq %rdi, %rcx
movl $0, %r8d
cmpl $0, 4(%rdi)
jg .L147
ret
.L158:
addl $1, %edi
movl (%rcx), %eax
cmpl %edi, %eax
jle .L151
.L150:
imull %r8d, %eax
addl %edi, %eax
cltq
leaq (%rax,%rax,4), %rdx
leaq (%rax,%rdx,2), %rax
salq $3, %rax
addq 8(%rcx), %rax
movb $0, 9(%rax)
movl $0, %edx
.L149:
movl %r8d, %eax
imull (%rcx), %eax
addl %edi, %eax
cltq
leaq (%rax,%rax,4), %rsi
leaq (%rax,%rsi,2), %rax
salq $3, %rax
addq 8(%rcx), %rax
movslq %edx, %rsi
movb $1, 10(%rax,%rsi)
addl $1, %edx
cmpl $8, %edx
jne .L149
jmp .L158
.L151:
addl $1, %r8d
cmpl %r8d, 4(%rcx)
jle .L146
.L147:
movl (%rcx), %eax
movl $0, %edi
testl %eax, %eax
jg .L150
jmp .L151
.L146:
ret
.cfi_endproc
.LFE3691:
.size _ZN5Board10resetBoardEv, .-_ZN5Board10resetBoardEv
.globl _Z13checkTileListP4TilePS0_i
.type _Z13checkTileListP4TilePS0_i, @function
_Z13checkTileListP4TilePS0_i:
.LFB3692:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L162
movq %rsi, %rax
movslq %edx, %rdx
leaq (%rsi,%rdx,8), %rdx
.L161:
cmpq %rdi, (%rax)
je .L163
addq $8, %rax
cmpq %rdx, %rax
jne .L161
movl $0, %eax
ret
.L162:
movl $0, %eax
ret
.L163:
movl $1, %eax
ret
.cfi_endproc
.LFE3692:
.size _Z13checkTileListP4TilePS0_i, .-_Z13checkTileListP4TilePS0_i
.align 2
.globl _ZN5Board14getLetterCountEc
.type _ZN5Board14getLetterCountEc, @function
_ZN5Board14getLetterCountEc:
.LFB3693:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl 4(%rdi), %ebp
testl %ebp, %ebp
jle .L172
movq %rdi, %rbx
movl %esi, %ecx
movl (%rdi), %r10d
movl $0, %r8d
movl $0, %edi
movl $0, %esi
movslq %r10d, %r12
jmp .L167
.L168:
addq $88, %rax
cmpq %rdx, %rax
je .L171
.L169:
cmpb %cl, 8(%rax)
jne .L168
addl $1, %esi
jmp .L168
.L171:
addl $1, %edi
addl %r10d, %r8d
cmpl %ebp, %edi
je .L165
.L167:
testl %r10d, %r10d
jle .L171
movq 8(%rbx), %r9
movslq %r8d, %rdx
leaq (%rdx,%rdx,4), %rax
leaq (%rdx,%rax,2), %rax
leaq (%r9,%rax,8), %rax
addq %r12, %rdx
leaq (%rdx,%rdx,4), %r11
leaq (%rdx,%r11,2), %rdx
leaq (%r9,%rdx,8), %rdx
jmp .L169
.L172:
movl $0, %esi
.L165:
movl %esi, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3693:
.size _ZN5Board14getLetterCountEc, .-_ZN5Board14getLetterCountEc
.align 2
.globl _ZN5Board16getTilesByLetterEPP4Tilec
.type _ZN5Board16getTilesByLetterEPP4Tilec, @function
_ZN5Board16getTilesByLetterEPP4Tilec:
.LFB3694:
.cfi_startproc
endbr64
movq %rdi, %rcx
movl 4(%rdi), %eax
imull (%rdi), %eax
testl %eax, %eax
jle .L175
movl $0, %r8d
movl $0, %edi
movl $0, %r9d
jmp .L178
.L177:
addl $1, %edi
addq $88, %r8
movl 4(%rcx), %eax
imull (%rcx), %eax
cmpl %edi, %eax
jle .L175
.L178:
movq %r8, %rax
addq 8(%rcx), %rax
cmpb %dl, 8(%rax)
jne .L177
movslq %r9d, %r10
movq %rax, (%rsi,%r10,8)
leal 1(%r9), %r9d
jmp .L177
.L175:
ret
.cfi_endproc
.LFE3694:
.size _ZN5Board16getTilesByLetterEPP4Tilec, .-_ZN5Board16getTilesByLetterEPP4Tilec
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3720:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3720:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/*
Boggle Environment - Board and Tile Class
Miguel Aroca-Ouellette
05/14/2016
*/
#include <iostream>
#include <stdlib.h>
#include <string>
#include <cassert>
#include <time.h>
#include "boggle_env.cuh"
#define NUM_LETTERS 26
/*Constructor: Set dimensions of board.*/
CUDA_CALLABLE_MEMBER
Board::Board(int _width, int _height)
{
width = _width;
height = _height;
grid = (Tile *)malloc(sizeof(Tile)*height*width);
}
/* Destructor */
CUDA_CALLABLE_MEMBER
Board::~Board()
{
free(grid);
}
/*Copy construtor*/
CUDA_CALLABLE_MEMBER
Board::Board(const Board &obj)
{
//printf("Copy constructor allocating grid.\n");
width = obj.width;
height = obj.height;
grid = (Tile *)malloc(sizeof(Tile)*height*width);
for (int y = 0; y < height; y++)
{
for (int x = 0; x < width; x++)
{
grid[x + y*width].letter = obj.grid[x + y*width].letter;
grid[x + y*width].x = x;
grid[x + y*width].y = y;
grid[x + y*width].used = false;
for (int i = 0; i < NUM_ADJ; i++)
{
grid[x + y*width].adj_available[i] = true;
grid[x + y*width].adj_list[i] = NULL;
}
getAllAdj(&grid[x + y*width], grid[x + y*width].adj_list);
}
}
}
/*Populates the board with random letters.*/
void Board::genRandLetters()
{
//random seed
for (int y = 0; y < height; y++)
{
for (int x = 0; x < width; x++)
{
//get random number between 0 and 25 -> letters
char rand_char = 'a' + rand() % NUM_LETTERS;
grid[x + y*width].letter = rand_char;
grid[x + y*width].x = x;
grid[x + y*width].y = y;
grid[x + y*width].used = false;
for (int i = 0; i < NUM_ADJ; i++)
{
grid[x + y*width].adj_available[i] = true;
grid[x + y*width].adj_list[i] = NULL;
}
getAllAdj(&grid[x + y*width], grid[x + y*width].adj_list);
}
}
}
/*Set letters. Ensure that it is the right size.*/
void Board::setLetters(string letters)
{
assert(letters.length() == width*height);
int x, y;
for (int i = 0; i < (width*height); i++)
{
x = i % width;
y = i / width;
grid[x+y*width].x = x;
grid[x+y*width].y = y;
grid[x+y*width].letter = letters[i];
grid[x+y*width].used = false;
for (int i = 0; i < NUM_ADJ; i++)
{
grid[x + y*width].adj_available[i] = true;
grid[x + y*width].adj_list[i] = NULL;
}
getAllAdj(&grid[x + y*width], grid[x + y*width].adj_list);
}
}
/* Returns list of adjancent tiles filtered by adj_available list */
void Board::getAdjList(Tile *center, Tile **adj)
{
for (int i = 0; i < NUM_ADJ; i++)
{
if ((center->adj_list[i] != NULL) && (center->adj_available[i]))
{
adj[i] = center->adj_list[i];
}
else
adj[i] = NULL;
}
}
/*Get adjacent tile letters which are not used. Origin is top left.
Inputs: (x,y) coordinate of center tile.
Pointer to adjacency list to fill. MUST BE ABLE TO ACCOMODATE 8 LETTERS.
Returns indicates size of filled adjacenct list.*/
int Board::getAdj(Tile* center, Tile **adj)
{
int size = 0;
int x = center->x;
int y = center->y;
if ((x > 0) && (y > 0)) //top left
pushTile(adj, x - 1, y - 1, &size, false);
if ((x > 0) && (y < (height - 1))) //bottom left
pushTile(adj, x - 1, y + 1, &size, false);
if ((x < (width - 1)) && (y > 0)) //top right
pushTile(adj, x + 1, y - 1, &size, false);
if ((x < (width - 1)) && (y < (height - 1))) //bottom right
pushTile(adj, x + 1, y + 1, &size, false);
if (y > 0) //top center
pushTile(adj, x, y - 1, &size, false);
if (y < (height - 1)) //bottom center
pushTile(adj, x, y + 1, &size, false);
if (x > 0) //left center
pushTile(adj, x - 1, y, &size, false);
if (x < (width - 1)) //right center
pushTile(adj, x + 1, y, &size, false);
return size;
}
/*Private: Helper function for get_adj. Only assigns the tile if it is unused. Increments counts.*/
void Board::pushTile(Tile **target, int x, int y, int *count, bool all)
{
if ((!grid[x+y*width].used) || all)
target[(*count)++] = &grid[x+y*width];
}
/*Get adjacent tile letters which are not used. Origin is top left.
Inputs: (x,y) coordinate of center tile.
Pointer to adjacency list to fill. MUST BE ABLE TO ACCOMODATE 8 LETTERS.
Returns indicates size of filled adjacenct list.*/
int Board::getAllAdj(Tile* center, Tile **adj)
{
int size = 0;
int x = center->x;
int y = center->y;
if ((x > 0) && (y > 0)) //top left
pushTile(adj, x - 1, y - 1, &size, true);
if ((x > 0) && (y < (height - 1))) //bottom left
pushTile(adj, x - 1, y + 1, &size, true);
if ((x < (width - 1)) && (y > 0)) //top right
pushTile(adj, x + 1, y - 1, &size, true);
if ((x < (width - 1)) && (y < (height - 1))) //bottom right
pushTile(adj, x + 1, y + 1, &size, true);
if (y > 0) //top center
pushTile(adj, x, y - 1, &size, true);
if (y < (height - 1)) //bottom center
pushTile(adj, x, y + 1, &size, true);
if (x > 0) //left center
pushTile(adj, x - 1, y, &size, true);
if (x < (width - 1)) //right center
pushTile(adj, x + 1, y, &size, true);
return size;
}
/* Prints the boggle board*/
void Board::printBoard()
{
for (int y = 0; y < height; y++)
{
for (int x = 0; x < width; x++)
printf("%c ",grid[x+y*width].letter);
printf("\n");
}
}
/* Prints the used tiles as 1, otherwise 0*/
void Board::printUsed()
{
for (int y = 0; y < height; y++)
{
for (int x = 0; x < width; x++)
printf("%c ", ((grid[x + y*width].used) ? grid[x + y*width].letter : ' '));
printf("\n");
}
}
/*Getter for tile.*/
Tile* Board::getTile(int x, int y)
{
return &grid[x+y*width];
}
/*Returns all tiles in the board.*/
void Board::getAllTiles(Tile *all_tiles[])
{
for (int y = 0; y < height; y++)
{
for (int x = 0; x < width; x++)
all_tiles[y*width + x] = getTile(x, y);
}
}
/* Resets all tiles on board to unused*/
void Board::resetBoard()
{
for (int y = 0; y < height; y++)
{
for (int x = 0; x < width; x++)
{
grid[x + y*width].used = false;
for (int i = 0; i < NUM_ADJ; i++)
grid[x + y*width].adj_available[i] = true;
}
}
}
/*Checks if the Tile is in the list of Tiles */
bool checkTileList(Tile *check, Tile **list, int size)
{
for (int i = 0; i < size; i++)
{
if (check == list[i])
return true;
}
return false;
}
/* Returns the number of tiles with this letter. */
int Board::getLetterCount(char c)
{
int count = 0;
for (int y = 0; y < height; y++)
{
for (int x = 0; x < width; x++)
{
if (grid[x + y*width].letter == c)
count++;
}
}
return count;
}
/*Returns all tiles in the board that match a given letter.
Should call getLetterCount before hand to get size.*/
void Board::getTilesByLetter(Tile *all_tiles[], char c)
{
int i = 0;
for (int x = 0; x < height*width; x++)
{
if (grid[x].letter == c)
all_tiles[i++] = &grid[x];
}
}
|
#ifdef __HIPCC__
#define CUDA_CALLABLE_MEMBER __host__ __device__
#else
#define CUDA_CALLABLE_MEMBER
#endif
#ifndef BOGGLE_ENV_H
#define BOGGLE_ENV_H
/* --- Boggle Environment header --- */
#include <string>
#include <hip/hip_runtime.h>
using namespace std;
#define NUM_ADJ 8 //tiles can have at most 8 adjacent tiles
/*Letter Tile struct*/
struct Tile
{
int x;
int y;
char letter;
bool used;
bool adj_available[NUM_ADJ]; //list which denotes if adjacency available
Tile* adj_list[NUM_ADJ]; //list which holds adjacencies
};
/*Boggle Board Class.*/
class Board {
int width, height;
CUDA_CALLABLE_MEMBER void pushTile(Tile **target, int x, int y, int *count, bool all);
public:
CUDA_CALLABLE_MEMBER Board(int _width, int _height);
CUDA_CALLABLE_MEMBER Board(const Board &obj);
CUDA_CALLABLE_MEMBER ~Board();
void genRandLetters();
void setLetters(string letters);
CUDA_CALLABLE_MEMBER int getAdj(Tile* center, Tile **adj);
CUDA_CALLABLE_MEMBER void getAdjList(Tile *center, Tile **adj);
CUDA_CALLABLE_MEMBER int getAllAdj(Tile* center, Tile **adj);
CUDA_CALLABLE_MEMBER Tile* getTile(int x, int y);
CUDA_CALLABLE_MEMBER void getAllTiles(Tile *all_tiles[]);
CUDA_CALLABLE_MEMBER int getNumTiles() { return width*height; }
int getHeight() { return height; }
int getWidth() { return width; }
CUDA_CALLABLE_MEMBER void resetBoard();
CUDA_CALLABLE_MEMBER void printBoard();
CUDA_CALLABLE_MEMBER void printUsed();
CUDA_CALLABLE_MEMBER int getLetterCount(char c);
CUDA_CALLABLE_MEMBER void getTilesByLetter(Tile *all_tiles[], char c);
Tile *grid; //necessary for cuda memory allocation
};
CUDA_CALLABLE_MEMBER bool checkTileList(Tile *check, Tile **list, int size); //returns true if in list
#endif
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#ifdef __HIPCC__
#define CUDA_CALLABLE_MEMBER __host__ __device__
#else
#define CUDA_CALLABLE_MEMBER
#endif
#ifndef BOGGLE_ENV_H
#define BOGGLE_ENV_H
/* --- Boggle Environment header --- */
#include <string>
#include <hip/hip_runtime.h>
using namespace std;
#define NUM_ADJ 8 //tiles can have at most 8 adjacent tiles
/*Letter Tile struct*/
struct Tile
{
int x;
int y;
char letter;
bool used;
bool adj_available[NUM_ADJ]; //list which denotes if adjacency available
Tile* adj_list[NUM_ADJ]; //list which holds adjacencies
};
/*Boggle Board Class.*/
class Board {
int width, height;
CUDA_CALLABLE_MEMBER void pushTile(Tile **target, int x, int y, int *count, bool all);
public:
CUDA_CALLABLE_MEMBER Board(int _width, int _height);
CUDA_CALLABLE_MEMBER Board(const Board &obj);
CUDA_CALLABLE_MEMBER ~Board();
void genRandLetters();
void setLetters(string letters);
CUDA_CALLABLE_MEMBER int getAdj(Tile* center, Tile **adj);
CUDA_CALLABLE_MEMBER void getAdjList(Tile *center, Tile **adj);
CUDA_CALLABLE_MEMBER int getAllAdj(Tile* center, Tile **adj);
CUDA_CALLABLE_MEMBER Tile* getTile(int x, int y);
CUDA_CALLABLE_MEMBER void getAllTiles(Tile *all_tiles[]);
CUDA_CALLABLE_MEMBER int getNumTiles() { return width*height; }
int getHeight() { return height; }
int getWidth() { return width; }
CUDA_CALLABLE_MEMBER void resetBoard();
CUDA_CALLABLE_MEMBER void printBoard();
CUDA_CALLABLE_MEMBER void printUsed();
CUDA_CALLABLE_MEMBER int getLetterCount(char c);
CUDA_CALLABLE_MEMBER void getTilesByLetter(Tile *all_tiles[], char c);
Tile *grid; //necessary for cuda memory allocation
};
CUDA_CALLABLE_MEMBER bool checkTileList(Tile *check, Tile **list, int size); //returns true if in list
#endif
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#ifdef __HIPCC__
#define CUDA_CALLABLE_MEMBER __host__ __device__
#else
#define CUDA_CALLABLE_MEMBER
#endif
#ifndef BOGGLE_ENV_H
#define BOGGLE_ENV_H
/* --- Boggle Environment header --- */
#include <string>
#include <hip/hip_runtime.h>
using namespace std;
#define NUM_ADJ 8 //tiles can have at most 8 adjacent tiles
/*Letter Tile struct*/
struct Tile
{
int x;
int y;
char letter;
bool used;
bool adj_available[NUM_ADJ]; //list which denotes if adjacency available
Tile* adj_list[NUM_ADJ]; //list which holds adjacencies
};
/*Boggle Board Class.*/
class Board {
int width, height;
CUDA_CALLABLE_MEMBER void pushTile(Tile **target, int x, int y, int *count, bool all);
public:
CUDA_CALLABLE_MEMBER Board(int _width, int _height);
CUDA_CALLABLE_MEMBER Board(const Board &obj);
CUDA_CALLABLE_MEMBER ~Board();
void genRandLetters();
void setLetters(string letters);
CUDA_CALLABLE_MEMBER int getAdj(Tile* center, Tile **adj);
CUDA_CALLABLE_MEMBER void getAdjList(Tile *center, Tile **adj);
CUDA_CALLABLE_MEMBER int getAllAdj(Tile* center, Tile **adj);
CUDA_CALLABLE_MEMBER Tile* getTile(int x, int y);
CUDA_CALLABLE_MEMBER void getAllTiles(Tile *all_tiles[]);
CUDA_CALLABLE_MEMBER int getNumTiles() { return width*height; }
int getHeight() { return height; }
int getWidth() { return width; }
CUDA_CALLABLE_MEMBER void resetBoard();
CUDA_CALLABLE_MEMBER void printBoard();
CUDA_CALLABLE_MEMBER void printUsed();
CUDA_CALLABLE_MEMBER int getLetterCount(char c);
CUDA_CALLABLE_MEMBER void getTilesByLetter(Tile *all_tiles[], char c);
Tile *grid; //necessary for cuda memory allocation
};
CUDA_CALLABLE_MEMBER bool checkTileList(Tile *check, Tile **list, int size); //returns true if in list
#endif
|
.text
.file "boggle_env.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0003880d_00000000-6_boggle_env.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.globl _ZN5BoardC2Eii
.type _ZN5BoardC2Eii, @function
_ZN5BoardC2Eii:
.LFB3673:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movl %esi, (%rdi)
movl %edx, 4(%rdi)
movslq %edx, %rdx
movslq %esi, %rsi
imulq %rsi, %rdx
leaq (%rdx,%rdx,4), %rax
leaq (%rdx,%rax,2), %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, 8(%rbx)
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZN5BoardC2Eii, .-_ZN5BoardC2Eii
.globl _ZN5BoardC1Eii
.set _ZN5BoardC1Eii,_ZN5BoardC2Eii
.align 2
.globl _ZN5BoardD2Ev
.type _ZN5BoardD2Ev, @function
_ZN5BoardD2Ev:
.LFB3676:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 8(%rdi), %rdi
call free@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3676:
.size _ZN5BoardD2Ev, .-_ZN5BoardD2Ev
.globl _ZN5BoardD1Ev
.set _ZN5BoardD1Ev,_ZN5BoardD2Ev
.align 2
.globl _ZN5Board10getAdjListEP4TilePS1_
.type _ZN5Board10getAdjListEP4TilePS1_, @function
_ZN5Board10getAdjListEP4TilePS1_:
.LFB3683:
.cfi_startproc
endbr64
movl $0, %eax
movl $0, %edi
jmp .L9
.L8:
movq %rcx, (%rdx,%rax,8)
addq $1, %rax
cmpq $8, %rax
je .L12
.L9:
movq 24(%rsi,%rax,8), %rcx
testq %rcx, %rcx
je .L8
cmpb $0, 10(%rsi,%rax)
cmove %rdi, %rcx
jmp .L8
.L12:
ret
.cfi_endproc
.LFE3683:
.size _ZN5Board10getAdjListEP4TilePS1_, .-_ZN5Board10getAdjListEP4TilePS1_
.align 2
.globl _ZN5Board8pushTileEPP4TileiiPib
.type _ZN5Board8pushTileEPP4TileiiPib, @function
_ZN5Board8pushTileEPP4TileiiPib:
.LFB3685:
.cfi_startproc
endbr64
imull (%rdi), %ecx
addl %edx, %ecx
movslq %ecx, %rcx
leaq (%rcx,%rcx,4), %rdx
leaq (%rcx,%rdx,2), %rdx
movq 8(%rdi), %rax
leaq (%rax,%rdx,8), %rdx
cmpb $1, 9(%rdx)
jne .L16
testb %r9b, %r9b
je .L13
.L16:
movl (%r8), %eax
leal 1(%rax), %ecx
movl %ecx, (%r8)
cltq
movq %rdx, (%rsi,%rax,8)
.L13:
ret
.cfi_endproc
.LFE3685:
.size _ZN5Board8pushTileEPP4TileiiPib, .-_ZN5Board8pushTileEPP4TileiiPib
.align 2
.globl _ZN5Board6getAdjEP4TilePS1_
.type _ZN5Board6getAdjEP4TilePS1_, @function
_ZN5Board6getAdjEP4TilePS1_:
.LFB3684:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $16, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %rdx, %r13
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $0, 4(%rsp)
movl (%rsi), %ebp
movl 4(%rsi), %r12d
testl %r12d, %r12d
setg %r14b
testl %ebp, %ebp
jle .L18
testb %r14b, %r14b
jne .L37
.L18:
testl %ebp, %ebp
jg .L38
.L20:
movl (%rbx), %eax
subl $1, %eax
cmpl %ebp, %eax
setg %al
testb %r14b, %r14b
je .L22
testb %al, %al
jne .L39
.L22:
testb %al, %al
jne .L25
.L26:
testl %r12d, %r12d
jle .L27
.L24:
leal -1(%r12), %ecx
movl $0, %r9d
leaq 4(%rsp), %r8
movl %ebp, %edx
movq %r13, %rsi
movq %rbx, %rdi
call _ZN5Board8pushTileEPP4TileiiPib
.L27:
movl 4(%rbx), %eax
subl $1, %eax
cmpl %r12d, %eax
jg .L40
.L28:
testl %ebp, %ebp
jg .L41
.L29:
movl (%rbx), %eax
subl $1, %eax
cmpl %ebp, %eax
jg .L42
.L30:
movl 4(%rsp), %eax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L43
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
leal -1(%r12), %ecx
leal -1(%rbp), %edx
movl $0, %r9d
leaq 4(%rsp), %r8
movq %r13, %rsi
call _ZN5Board8pushTileEPP4TileiiPib
movl 4(%rbx), %eax
subl $1, %eax
cmpl %r12d, %eax
jle .L20
.L19:
leal 1(%r12), %ecx
leal -1(%rbp), %edx
movl $0, %r9d
leaq 4(%rsp), %r8
movq %r13, %rsi
movq %rbx, %rdi
call _ZN5Board8pushTileEPP4TileiiPib
jmp .L20
.L39:
leal -1(%r12), %ecx
leal 1(%rbp), %edx
movl $0, %r9d
leaq 4(%rsp), %r8
movq %r13, %rsi
movq %rbx, %rdi
call _ZN5Board8pushTileEPP4TileiiPib
movl (%rbx), %eax
subl $1, %eax
cmpl %eax, %ebp
jge .L24
movl 4(%rbx), %eax
subl $1, %eax
cmpl %eax, %r12d
jge .L24
jmp .L31
.L40:
leal 1(%r12), %ecx
movl $0, %r9d
leaq 4(%rsp), %r8
movl %ebp, %edx
movq %r13, %rsi
movq %rbx, %rdi
call _ZN5Board8pushTileEPP4TileiiPib
jmp .L28
.L41:
leal -1(%rbp), %edx
movl $0, %r9d
leaq 4(%rsp), %r8
movl %r12d, %ecx
movq %r13, %rsi
movq %rbx, %rdi
call _ZN5Board8pushTileEPP4TileiiPib
jmp .L29
.L42:
leal 1(%rbp), %edx
movl $0, %r9d
leaq 4(%rsp), %r8
movl %r12d, %ecx
movq %r13, %rsi
movq %rbx, %rdi
call _ZN5Board8pushTileEPP4TileiiPib
jmp .L30
.L25:
movl 4(%rbx), %eax
subl $1, %eax
cmpl %eax, %r12d
jge .L28
.L31:
leal 1(%r12), %ecx
leal 1(%rbp), %edx
movl $0, %r9d
leaq 4(%rsp), %r8
movq %r13, %rsi
movq %rbx, %rdi
call _ZN5Board8pushTileEPP4TileiiPib
jmp .L26
.L38:
movl 4(%rbx), %eax
subl $1, %eax
cmpl %eax, %r12d
jl .L19
movl (%rbx), %eax
subl $1, %eax
cmpl %eax, %ebp
setl %al
jmp .L22
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3684:
.size _ZN5Board6getAdjEP4TilePS1_, .-_ZN5Board6getAdjEP4TilePS1_
.align 2
.globl _ZN5Board9getAllAdjEP4TilePS1_
.type _ZN5Board9getAllAdjEP4TilePS1_, @function
_ZN5Board9getAllAdjEP4TilePS1_:
.LFB3686:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $16, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %rdx, %r13
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $0, 4(%rsp)
movl (%rsi), %ebp
movl 4(%rsi), %r12d
testl %r12d, %r12d
setg %r14b
testl %ebp, %ebp
jle .L45
testb %r14b, %r14b
jne .L64
.L45:
testl %ebp, %ebp
jg .L65
.L47:
movl (%rbx), %eax
subl $1, %eax
cmpl %ebp, %eax
setg %al
testb %r14b, %r14b
je .L49
testb %al, %al
jne .L66
.L49:
testb %al, %al
jne .L52
.L53:
testl %r12d, %r12d
jle .L54
.L51:
leal -1(%r12), %ecx
movl $1, %r9d
leaq 4(%rsp), %r8
movl %ebp, %edx
movq %r13, %rsi
movq %rbx, %rdi
call _ZN5Board8pushTileEPP4TileiiPib
.L54:
movl 4(%rbx), %eax
subl $1, %eax
cmpl %r12d, %eax
jg .L67
.L55:
testl %ebp, %ebp
jg .L68
.L56:
movl (%rbx), %eax
subl $1, %eax
cmpl %ebp, %eax
jg .L69
.L57:
movl 4(%rsp), %eax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L70
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L64:
.cfi_restore_state
leal -1(%r12), %ecx
leal -1(%rbp), %edx
movl $1, %r9d
leaq 4(%rsp), %r8
movq %r13, %rsi
call _ZN5Board8pushTileEPP4TileiiPib
movl 4(%rbx), %eax
subl $1, %eax
cmpl %r12d, %eax
jle .L47
.L46:
leal 1(%r12), %ecx
leal -1(%rbp), %edx
movl $1, %r9d
leaq 4(%rsp), %r8
movq %r13, %rsi
movq %rbx, %rdi
call _ZN5Board8pushTileEPP4TileiiPib
jmp .L47
.L66:
leal -1(%r12), %ecx
leal 1(%rbp), %edx
movl $1, %r9d
leaq 4(%rsp), %r8
movq %r13, %rsi
movq %rbx, %rdi
call _ZN5Board8pushTileEPP4TileiiPib
movl (%rbx), %eax
subl $1, %eax
cmpl %eax, %ebp
jge .L51
movl 4(%rbx), %eax
subl $1, %eax
cmpl %eax, %r12d
jge .L51
jmp .L58
.L67:
leal 1(%r12), %ecx
movl $1, %r9d
leaq 4(%rsp), %r8
movl %ebp, %edx
movq %r13, %rsi
movq %rbx, %rdi
call _ZN5Board8pushTileEPP4TileiiPib
jmp .L55
.L68:
leal -1(%rbp), %edx
movl $1, %r9d
leaq 4(%rsp), %r8
movl %r12d, %ecx
movq %r13, %rsi
movq %rbx, %rdi
call _ZN5Board8pushTileEPP4TileiiPib
jmp .L56
.L69:
leal 1(%rbp), %edx
movl $1, %r9d
leaq 4(%rsp), %r8
movl %r12d, %ecx
movq %r13, %rsi
movq %rbx, %rdi
call _ZN5Board8pushTileEPP4TileiiPib
jmp .L57
.L52:
movl 4(%rbx), %eax
subl $1, %eax
cmpl %eax, %r12d
jge .L55
.L58:
leal 1(%r12), %ecx
leal 1(%rbp), %edx
movl $1, %r9d
leaq 4(%rsp), %r8
movq %r13, %rsi
movq %rbx, %rdi
call _ZN5Board8pushTileEPP4TileiiPib
jmp .L53
.L65:
movl 4(%rbx), %eax
subl $1, %eax
cmpl %eax, %r12d
jl .L46
movl (%rbx), %eax
subl $1, %eax
cmpl %eax, %ebp
setl %al
jmp .L49
.L70:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3686:
.size _ZN5Board9getAllAdjEP4TilePS1_, .-_ZN5Board9getAllAdjEP4TilePS1_
.align 2
.globl _ZN5BoardC2ERKS_
.type _ZN5BoardC2ERKS_, @function
_ZN5BoardC2ERKS_:
.LFB3679:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movq %rsi, %r13
movl (%rsi), %edx
movl %edx, (%rdi)
movl 4(%rsi), %ebx
movl %ebx, 4(%rdi)
movslq %ebx, %rax
movslq %edx, %rdx
imulq %rdx, %rax
leaq (%rax,%rax,4), %rdx
leaq (%rax,%rdx,2), %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, 8(%rbp)
movl $0, %r12d
testl %ebx, %ebx
jg .L72
.L71:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L84:
.cfi_restore_state
leaq 24(%rsi), %rdx
movq %rbp, %rdi
call _ZN5Board9getAllAdjEP4TilePS1_
addl $1, %ebx
movl 0(%rbp), %eax
cmpl %ebx, %eax
jle .L76
.L75:
imull %r12d, %eax
addl %ebx, %eax
cltq
leaq (%rax,%rax,4), %rdx
leaq (%rax,%rdx,2), %rax
salq $3, %rax
movq %rax, %rsi
addq 8(%rbp), %rsi
movq 8(%r13), %rdx
movzbl 8(%rdx,%rax), %eax
movb %al, 8(%rsi)
movl %ebx, (%rsi)
movl %r12d, 4(%rsi)
movb $0, 9(%rsi)
movl $0, %eax
.L74:
movb $1, 10(%rsi,%rax)
movq $0, 24(%rsi,%rax,8)
addq $1, %rax
cmpq $8, %rax
jne .L74
jmp .L84
.L76:
addl $1, %r12d
cmpl %r12d, 4(%rbp)
jle .L71
.L72:
movl 0(%rbp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L75
jmp .L76
.cfi_endproc
.LFE3679:
.size _ZN5BoardC2ERKS_, .-_ZN5BoardC2ERKS_
.globl _ZN5BoardC1ERKS_
.set _ZN5BoardC1ERKS_,_ZN5BoardC2ERKS_
.align 2
.globl _ZN5Board14genRandLettersEv
.type _ZN5Board14genRandLettersEv, @function
_ZN5Board14genRandLettersEv:
.LFB3681:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movl $0, %r12d
cmpl $0, 4(%rdi)
jg .L86
.L85:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L98:
.cfi_restore_state
movl %r12d, %eax
imull (%rbx), %eax
addl %ebp, %eax
cltq
leaq (%rax,%rax,4), %rdx
leaq (%rax,%rdx,2), %rdx
movq 8(%rbx), %rax
leaq (%rax,%rdx,8), %rsi
leaq 24(%rsi), %rdx
movq %rbx, %rdi
call _ZN5Board9getAllAdjEP4TilePS1_
addl $1, %ebp
cmpl %ebp, (%rbx)
jle .L90
.L89:
call rand@PLT
movl %r12d, %edx
imull (%rbx), %edx
addl %ebp, %edx
movslq %edx, %rdx
leaq (%rdx,%rdx,4), %rcx
leaq (%rdx,%rcx,2), %rcx
salq $3, %rcx
addq 8(%rbx), %rcx
movslq %eax, %rdx
imulq $1321528399, %rdx, %rdx
sarq $35, %rdx
movl %eax, %esi
sarl $31, %esi
subl %esi, %edx
imull $26, %edx, %edx
subl %edx, %eax
addl $97, %eax
movb %al, 8(%rcx)
movl %r12d, %eax
imull (%rbx), %eax
addl %ebp, %eax
cltq
leaq (%rax,%rax,4), %rdx
leaq (%rax,%rdx,2), %rax
salq $3, %rax
addq 8(%rbx), %rax
movl %ebp, (%rax)
movl %r12d, %eax
imull (%rbx), %eax
addl %ebp, %eax
cltq
leaq (%rax,%rax,4), %rdx
leaq (%rax,%rdx,2), %rax
salq $3, %rax
addq 8(%rbx), %rax
movl %r12d, 4(%rax)
movl %r12d, %eax
imull (%rbx), %eax
addl %ebp, %eax
cltq
leaq (%rax,%rax,4), %rdx
leaq (%rax,%rdx,2), %rax
salq $3, %rax
addq 8(%rbx), %rax
movb $0, 9(%rax)
movl $0, %edx
.L88:
movl %r12d, %eax
imull (%rbx), %eax
addl %ebp, %eax
cltq
leaq (%rax,%rax,4), %rcx
leaq (%rax,%rcx,2), %rax
salq $3, %rax
addq 8(%rbx), %rax
movslq %edx, %rcx
movb $1, 10(%rax,%rcx)
movl %r12d, %eax
imull (%rbx), %eax
addl %ebp, %eax
cltq
leaq (%rax,%rax,4), %rsi
leaq (%rax,%rsi,2), %rax
salq $3, %rax
addq 8(%rbx), %rax
movq $0, 24(%rax,%rcx,8)
addl $1, %edx
cmpl $8, %edx
jne .L88
jmp .L98
.L90:
addl $1, %r12d
cmpl %r12d, 4(%rbx)
jle .L85
.L86:
movl $0, %ebp
cmpl $0, (%rbx)
jg .L89
jmp .L90
.cfi_endproc
.LFE3681:
.size _ZN5Board14genRandLettersEv, .-_ZN5Board14genRandLettersEv
.align 2
.globl _ZN5Board10setLettersENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.type _ZN5Board10setLettersENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, @function
_ZN5Board10setLettersENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE:
.LFB3682:
.cfi_startproc
endbr64
movl (%rdi), %ecx
movl %ecx, %eax
imull 4(%rdi), %eax
testl %eax, %eax
jle .L106
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %rsi, %r13
movl $0, %r12d
movl $0, %ebp
jmp .L102
.L110:
imull (%rbx), %eax
addl %edx, %eax
cltq
leaq (%rax,%rax,4), %rdx
leaq (%rax,%rdx,2), %rdx
movq 8(%rbx), %rax
leaq (%rax,%rdx,8), %rsi
leaq 24(%rsi), %rdx
movq %rbx, %rdi
call _ZN5Board9getAllAdjEP4TilePS1_
movl (%rbx), %ecx
addq $1, %rbp
addq $88, %r12
movl %ecx, %eax
imull 4(%rbx), %eax
cmpl %ebp, %eax
jle .L109
.L102:
movl %ebp, %eax
cltd
idivl %ecx
movq 8(%rbx), %rcx
movl %edx, (%rcx,%r12)
movl %eax, %ecx
imull (%rbx), %ecx
addl %edx, %ecx
movslq %ecx, %rcx
leaq (%rcx,%rcx,4), %rsi
leaq (%rcx,%rsi,2), %rcx
salq $3, %rcx
addq 8(%rbx), %rcx
movl %eax, 4(%rcx)
movq 0(%r13), %rcx
movzbl (%rcx,%rbp), %esi
movl %eax, %ecx
imull (%rbx), %ecx
addl %edx, %ecx
movslq %ecx, %rcx
leaq (%rcx,%rcx,4), %rdi
leaq (%rcx,%rdi,2), %rcx
salq $3, %rcx
addq 8(%rbx), %rcx
movb %sil, 8(%rcx)
movl %eax, %ecx
imull (%rbx), %ecx
addl %edx, %ecx
movslq %ecx, %rcx
leaq (%rcx,%rcx,4), %rsi
leaq (%rcx,%rsi,2), %rcx
salq $3, %rcx
addq 8(%rbx), %rcx
movb $0, 9(%rcx)
movl $0, %esi
.L101:
movl %eax, %ecx
imull (%rbx), %ecx
addl %edx, %ecx
movslq %ecx, %rcx
leaq (%rcx,%rcx,4), %rdi
leaq (%rcx,%rdi,2), %rcx
salq $3, %rcx
addq 8(%rbx), %rcx
movslq %esi, %rdi
movb $1, 10(%rcx,%rdi)
movl %eax, %ecx
imull (%rbx), %ecx
addl %edx, %ecx
movslq %ecx, %rcx
leaq (%rcx,%rcx,4), %r8
leaq (%rcx,%r8,2), %rcx
salq $3, %rcx
addq 8(%rbx), %rcx
movq $0, 24(%rcx,%rdi,8)
addl $1, %esi
cmpl $8, %esi
jne .L101
jmp .L110
.L109:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L106:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE3682:
.size _ZN5Board10setLettersENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .-_ZN5Board10setLettersENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%c "
.LC1:
.string "\n"
.text
.align 2
.globl _ZN5Board10printBoardEv
.type _ZN5Board10printBoardEv, @function
_ZN5Board10printBoardEv:
.LFB3687:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %rbp
movl $0, %r12d
leaq .LC0(%rip), %r13
leaq .LC1(%rip), %r14
cmpl $0, 4(%rdi)
jg .L112
.L111:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L114:
.cfi_restore_state
imull %r12d, %eax
addl %ebx, %eax
cltq
leaq (%rax,%rax,4), %rdx
leaq (%rax,%rdx,2), %rax
salq $3, %rax
addq 8(%rbp), %rax
movsbl 8(%rax), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
movl 0(%rbp), %eax
cmpl %ebx, %eax
jg .L114
.L115:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r12d
cmpl %r12d, 4(%rbp)
jle .L111
.L112:
movl 0(%rbp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L114
jmp .L115
.cfi_endproc
.LFE3687:
.size _ZN5Board10printBoardEv, .-_ZN5Board10printBoardEv
.align 2
.globl _ZN5Board9printUsedEv
.type _ZN5Board9printUsedEv, @function
_ZN5Board9printUsedEv:
.LFB3688:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movl $0, %r12d
leaq .LC0(%rip), %r14
movl $32, %r13d
leaq .LC1(%rip), %r15
cmpl $0, 4(%rdi)
jg .L123
.L122:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L125:
.cfi_restore_state
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
movl 0(%rbp), %eax
cmpl %ebx, %eax
jle .L127
.L126:
imull %r12d, %eax
addl %ebx, %eax
cltq
leaq (%rax,%rax,4), %rdx
leaq (%rax,%rdx,2), %rdx
movq 8(%rbp), %rax
leaq (%rax,%rdx,8), %rax
movl %r13d, %edx
cmpb $0, 9(%rax)
je .L125
movsbl 8(%rax), %edx
jmp .L125
.L127:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r12d
cmpl %r12d, 4(%rbp)
jle .L122
.L123:
movl 0(%rbp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L126
jmp .L127
.cfi_endproc
.LFE3688:
.size _ZN5Board9printUsedEv, .-_ZN5Board9printUsedEv
.align 2
.globl _ZN5Board7getTileEii
.type _ZN5Board7getTileEii, @function
_ZN5Board7getTileEii:
.LFB3689:
.cfi_startproc
endbr64
imull (%rdi), %edx
addl %esi, %edx
movslq %edx, %rdx
leaq (%rdx,%rdx,4), %rax
leaq (%rdx,%rax,2), %rdx
movq 8(%rdi), %rax
leaq (%rax,%rdx,8), %rax
ret
.cfi_endproc
.LFE3689:
.size _ZN5Board7getTileEii, .-_ZN5Board7getTileEii
.align 2
.globl _ZN5Board11getAllTilesEPP4Tile
.type _ZN5Board11getAllTilesEPP4Tile, @function
_ZN5Board11getAllTilesEPP4Tile:
.LFB3690:
.cfi_startproc
endbr64
movl $0, %r9d
cmpl $0, 4(%rdi)
jg .L137
ret
.L139:
imull %r9d, %eax
addl %edx, %eax
cltq
leaq (%rax,%rax,4), %rcx
leaq (%rax,%rcx,2), %r8
movq 8(%rdi), %rcx
leaq (%rcx,%r8,8), %rcx
movq %rcx, (%rsi,%rax,8)
addl $1, %edx
movl (%rdi), %eax
cmpl %edx, %eax
jg .L139
.L140:
addl $1, %r9d
cmpl %r9d, 4(%rdi)
jle .L136
.L137:
movl (%rdi), %eax
movl $0, %edx
testl %eax, %eax
jg .L139
jmp .L140
.L136:
ret
.cfi_endproc
.LFE3690:
.size _ZN5Board11getAllTilesEPP4Tile, .-_ZN5Board11getAllTilesEPP4Tile
.align 2
.globl _ZN5Board10resetBoardEv
.type _ZN5Board10resetBoardEv, @function
_ZN5Board10resetBoardEv:
.LFB3691:
.cfi_startproc
endbr64
movq %rdi, %rcx
movl $0, %r8d
cmpl $0, 4(%rdi)
jg .L147
ret
.L158:
addl $1, %edi
movl (%rcx), %eax
cmpl %edi, %eax
jle .L151
.L150:
imull %r8d, %eax
addl %edi, %eax
cltq
leaq (%rax,%rax,4), %rdx
leaq (%rax,%rdx,2), %rax
salq $3, %rax
addq 8(%rcx), %rax
movb $0, 9(%rax)
movl $0, %edx
.L149:
movl %r8d, %eax
imull (%rcx), %eax
addl %edi, %eax
cltq
leaq (%rax,%rax,4), %rsi
leaq (%rax,%rsi,2), %rax
salq $3, %rax
addq 8(%rcx), %rax
movslq %edx, %rsi
movb $1, 10(%rax,%rsi)
addl $1, %edx
cmpl $8, %edx
jne .L149
jmp .L158
.L151:
addl $1, %r8d
cmpl %r8d, 4(%rcx)
jle .L146
.L147:
movl (%rcx), %eax
movl $0, %edi
testl %eax, %eax
jg .L150
jmp .L151
.L146:
ret
.cfi_endproc
.LFE3691:
.size _ZN5Board10resetBoardEv, .-_ZN5Board10resetBoardEv
.globl _Z13checkTileListP4TilePS0_i
.type _Z13checkTileListP4TilePS0_i, @function
_Z13checkTileListP4TilePS0_i:
.LFB3692:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L162
movq %rsi, %rax
movslq %edx, %rdx
leaq (%rsi,%rdx,8), %rdx
.L161:
cmpq %rdi, (%rax)
je .L163
addq $8, %rax
cmpq %rdx, %rax
jne .L161
movl $0, %eax
ret
.L162:
movl $0, %eax
ret
.L163:
movl $1, %eax
ret
.cfi_endproc
.LFE3692:
.size _Z13checkTileListP4TilePS0_i, .-_Z13checkTileListP4TilePS0_i
.align 2
.globl _ZN5Board14getLetterCountEc
.type _ZN5Board14getLetterCountEc, @function
_ZN5Board14getLetterCountEc:
.LFB3693:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl 4(%rdi), %ebp
testl %ebp, %ebp
jle .L172
movq %rdi, %rbx
movl %esi, %ecx
movl (%rdi), %r10d
movl $0, %r8d
movl $0, %edi
movl $0, %esi
movslq %r10d, %r12
jmp .L167
.L168:
addq $88, %rax
cmpq %rdx, %rax
je .L171
.L169:
cmpb %cl, 8(%rax)
jne .L168
addl $1, %esi
jmp .L168
.L171:
addl $1, %edi
addl %r10d, %r8d
cmpl %ebp, %edi
je .L165
.L167:
testl %r10d, %r10d
jle .L171
movq 8(%rbx), %r9
movslq %r8d, %rdx
leaq (%rdx,%rdx,4), %rax
leaq (%rdx,%rax,2), %rax
leaq (%r9,%rax,8), %rax
addq %r12, %rdx
leaq (%rdx,%rdx,4), %r11
leaq (%rdx,%r11,2), %rdx
leaq (%r9,%rdx,8), %rdx
jmp .L169
.L172:
movl $0, %esi
.L165:
movl %esi, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3693:
.size _ZN5Board14getLetterCountEc, .-_ZN5Board14getLetterCountEc
.align 2
.globl _ZN5Board16getTilesByLetterEPP4Tilec
.type _ZN5Board16getTilesByLetterEPP4Tilec, @function
_ZN5Board16getTilesByLetterEPP4Tilec:
.LFB3694:
.cfi_startproc
endbr64
movq %rdi, %rcx
movl 4(%rdi), %eax
imull (%rdi), %eax
testl %eax, %eax
jle .L175
movl $0, %r8d
movl $0, %edi
movl $0, %r9d
jmp .L178
.L177:
addl $1, %edi
addq $88, %r8
movl 4(%rcx), %eax
imull (%rcx), %eax
cmpl %edi, %eax
jle .L175
.L178:
movq %r8, %rax
addq 8(%rcx), %rax
cmpb %dl, 8(%rax)
jne .L177
movslq %r9d, %r10
movq %rax, (%rsi,%r10,8)
leal 1(%r9), %r9d
jmp .L177
.L175:
ret
.cfi_endproc
.LFE3694:
.size _ZN5Board16getTilesByLetterEPP4Tilec, .-_ZN5Board16getTilesByLetterEPP4Tilec
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3720:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3720:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "boggle_env.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <cuda.h>
#include <stdio.h>
void printMatrix(float *matrix, int rows, int columns)
{
for (int i = 0; i < rows; i++) {
for (int j = 0; j < columns; j++)
printf("%g ", matrix[i * rows + j]);
printf("\n");
}
printf("\n");
}
#define CUDA_CHECK_RETURN(value)\
{\
cudaError_t _m_cudaStat = value;\
if (_m_cudaStat != cudaSuccess) {\
fprintf(stderr, "Error %s at line %d in file %s\n",\
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__);\
exit(1);\
}\
}
__global__ void initMatrix_1D(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
matrix[i] = i;
}
__global__ void initMatrix_2D_I(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int I = gridDim.x * blockDim.x;
// int J = gridDim.y * blockDim.y;
// matrix[j * I + i] = j * I + i;
// matrix[i + j * I] = i;
// matrix[i + j * I] = j;
// matrix[i + j * I] = I;
// matrix[i + j * I] = J;
matrix[i + j * I] = threadIdx.x;
// matrix[i + j * I] = threadIdx.y;
// matrix[i + j * I] = gridDim.x;
// matrix[i + j * I] = gridDim.y;
// matrix[i + j * I] = blockDim.x;
// matrix[i + j * I] = blockDim.y;
// matrix[i + j * I] = blockIdx.x;
// matrix[i + j * I] = blockIdx.y;
}
__global__ void initMatrix_2D_J(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
// int I = gridDim.x * blockDim.x;
int J = gridDim.y * blockDim.y;
matrix[j + i * J] = j + i * J;
}
__global__ void transp(float *matrix1, float *matrix2, float *check)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int I = gridDim.x * blockDim.x;
matrix2[i * I + j] = matrix1[j * I + i];
check[i * I + j] = j * I + i;
}
int main(int argc, char *argv[])
{
int blocks = (argc > 1) ? atoi(argv[1]) : 8;
int threads = (argc > 2) ? atoi(argv[2]) : 4;
int rows = 8;
int columns = 8;
int size_matrix = rows * columns;
float *dmatrix1, *hmatrix1;
float *dmatrix2, *hmatrix2;
float *dcheck, *hcheck;
float *dmatrix3, *hmatrix3;
cudaMalloc((void**) &dmatrix1, size_matrix * sizeof(float));
cudaMalloc((void**) &dmatrix2, size_matrix * sizeof(float));
cudaMalloc((void**) &dcheck, size_matrix * sizeof(float));
cudaMalloc((void**) &dmatrix3, size_matrix * sizeof(float));
hmatrix1 = (float*) calloc(size_matrix, sizeof(float));
hmatrix2 = (float*) calloc(size_matrix, sizeof(float));
hcheck = (float*) calloc(size_matrix, sizeof(float));
hmatrix3 = (float*) calloc(size_matrix, sizeof(float));
initMatrix_2D_I<<<dim3(2, 2), dim3(8)>>>(dmatrix3);
cudaDeviceSynchronize();
cudaMemcpy(hmatrix3, dmatrix3, size_matrix * sizeof(float), cudaMemcpyDeviceToHost);
printMatrix(hmatrix3, rows, columns);
// initMatrix_1D<<<dim3(blocks), dim3(threads)>>>(dmatrix1);
initMatrix_2D_I<<<dim3(blocks), dim3(2, 2)>>>(dmatrix1);
cudaDeviceSynchronize();
cudaMemcpy(hmatrix1, dmatrix1, size_matrix * sizeof(float), cudaMemcpyDeviceToHost);
printMatrix(hmatrix1, rows, columns);
#if 0
initMatrix_2D_J<<<dim3(blocks), dim3(2, 2)>>>(dmatrix2);
cudaDeviceSynchronize();
cudaMemcpy(hmatrix2, dmatrix2, size_matrix * sizeof(float), cudaMemcpyDeviceToHost);
printMatrix(hmatrix2, rows, columns);
#endif
transp<<<dim3(blocks), dim3(2, 2)>>>(dmatrix1, dmatrix2, dcheck);
cudaDeviceSynchronize();
cudaMemcpy(hmatrix2, dmatrix2, size_matrix * sizeof(float), cudaMemcpyDeviceToHost);
printMatrix(hmatrix2, rows, columns);
cudaMemcpy(hcheck, dcheck, size_matrix * sizeof(float), cudaMemcpyDeviceToHost);
printMatrix(hcheck, rows, columns);
cudaFree(dmatrix1);
cudaFree(dmatrix2);
cudaFree(dcheck);
free(hmatrix1);
free(hmatrix2);
free(hcheck);
return 0;
}
|
code for sm_80
Function : _Z6transpPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC UR4, c[0x0][0xc] ; /* 0x0000030000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe20000000800 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0060*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe4000f8e023f */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002200 */
/*0090*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002600 */
/*00a0*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc400078e0200 */
/*00b0*/ IMAD R5, R2, c[0x0][0x4], R5 ; /* 0x0000010002057a24 */
/* 0x002fc800078e0205 */
/*00c0*/ IMAD R8, R5, UR4, R0 ; /* 0x0000000405087c24 */
/* 0x000fc8000f8e0200 */
/*00d0*/ IMAD.WIDE R2, R8, R7, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x000fcc00078e0207 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ I2F R9, R8 ; /* 0x0000000800097306 */
/* 0x000e220000201400 */
/*0100*/ IMAD R0, R0, UR4, R5 ; /* 0x0000000400007c24 */
/* 0x000fc8000f8e0205 */
/*0110*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*0120*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*0130*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe8000c101906 */
/*0140*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x001fe2000c101906 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15initMatrix_2D_JPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0040*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e680000002600 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000ea20000002200 */
/*0060*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fe200078e0200 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc600000001ff */
/*0080*/ IMAD R0, R0, c[0x0][0x10], R7 ; /* 0x0000040000007a24 */
/* 0x002fc800078e0207 */
/*0090*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x004fc800078e0205 */
/*00a0*/ I2F R5, R0 ; /* 0x0000000000057306 */
/* 0x000e220000201400 */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15initMatrix_2D_IPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e680000002100 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002500 */
/*0060*/ IMAD R0, R5, c[0x0][0x4], R0 ; /* 0x0000010005007a24 */
/* 0x001fe400078e0200 */
/*0070*/ I2F.U32 R5, R7 ; /* 0x0000000700057306 */
/* 0x002e240000201000 */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x004fe200078e0203 */
/*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc600000001ff */
/*00a0*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x000fce00078e0207 */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13initMatrix_1DPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0040*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fe200078e0200 */
/*0050*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc600000001ff */
/*0060*/ I2F R5, R0 ; /* 0x0000000000057306 */
/* 0x000e2e0000201400 */
/*0070*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <cuda.h>
#include <stdio.h>
void printMatrix(float *matrix, int rows, int columns)
{
for (int i = 0; i < rows; i++) {
for (int j = 0; j < columns; j++)
printf("%g ", matrix[i * rows + j]);
printf("\n");
}
printf("\n");
}
#define CUDA_CHECK_RETURN(value)\
{\
cudaError_t _m_cudaStat = value;\
if (_m_cudaStat != cudaSuccess) {\
fprintf(stderr, "Error %s at line %d in file %s\n",\
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__);\
exit(1);\
}\
}
__global__ void initMatrix_1D(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
matrix[i] = i;
}
__global__ void initMatrix_2D_I(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int I = gridDim.x * blockDim.x;
// int J = gridDim.y * blockDim.y;
// matrix[j * I + i] = j * I + i;
// matrix[i + j * I] = i;
// matrix[i + j * I] = j;
// matrix[i + j * I] = I;
// matrix[i + j * I] = J;
matrix[i + j * I] = threadIdx.x;
// matrix[i + j * I] = threadIdx.y;
// matrix[i + j * I] = gridDim.x;
// matrix[i + j * I] = gridDim.y;
// matrix[i + j * I] = blockDim.x;
// matrix[i + j * I] = blockDim.y;
// matrix[i + j * I] = blockIdx.x;
// matrix[i + j * I] = blockIdx.y;
}
__global__ void initMatrix_2D_J(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
// int I = gridDim.x * blockDim.x;
int J = gridDim.y * blockDim.y;
matrix[j + i * J] = j + i * J;
}
__global__ void transp(float *matrix1, float *matrix2, float *check)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int I = gridDim.x * blockDim.x;
matrix2[i * I + j] = matrix1[j * I + i];
check[i * I + j] = j * I + i;
}
int main(int argc, char *argv[])
{
int blocks = (argc > 1) ? atoi(argv[1]) : 8;
int threads = (argc > 2) ? atoi(argv[2]) : 4;
int rows = 8;
int columns = 8;
int size_matrix = rows * columns;
float *dmatrix1, *hmatrix1;
float *dmatrix2, *hmatrix2;
float *dcheck, *hcheck;
float *dmatrix3, *hmatrix3;
cudaMalloc((void**) &dmatrix1, size_matrix * sizeof(float));
cudaMalloc((void**) &dmatrix2, size_matrix * sizeof(float));
cudaMalloc((void**) &dcheck, size_matrix * sizeof(float));
cudaMalloc((void**) &dmatrix3, size_matrix * sizeof(float));
hmatrix1 = (float*) calloc(size_matrix, sizeof(float));
hmatrix2 = (float*) calloc(size_matrix, sizeof(float));
hcheck = (float*) calloc(size_matrix, sizeof(float));
hmatrix3 = (float*) calloc(size_matrix, sizeof(float));
initMatrix_2D_I<<<dim3(2, 2), dim3(8)>>>(dmatrix3);
cudaDeviceSynchronize();
cudaMemcpy(hmatrix3, dmatrix3, size_matrix * sizeof(float), cudaMemcpyDeviceToHost);
printMatrix(hmatrix3, rows, columns);
// initMatrix_1D<<<dim3(blocks), dim3(threads)>>>(dmatrix1);
initMatrix_2D_I<<<dim3(blocks), dim3(2, 2)>>>(dmatrix1);
cudaDeviceSynchronize();
cudaMemcpy(hmatrix1, dmatrix1, size_matrix * sizeof(float), cudaMemcpyDeviceToHost);
printMatrix(hmatrix1, rows, columns);
#if 0
initMatrix_2D_J<<<dim3(blocks), dim3(2, 2)>>>(dmatrix2);
cudaDeviceSynchronize();
cudaMemcpy(hmatrix2, dmatrix2, size_matrix * sizeof(float), cudaMemcpyDeviceToHost);
printMatrix(hmatrix2, rows, columns);
#endif
transp<<<dim3(blocks), dim3(2, 2)>>>(dmatrix1, dmatrix2, dcheck);
cudaDeviceSynchronize();
cudaMemcpy(hmatrix2, dmatrix2, size_matrix * sizeof(float), cudaMemcpyDeviceToHost);
printMatrix(hmatrix2, rows, columns);
cudaMemcpy(hcheck, dcheck, size_matrix * sizeof(float), cudaMemcpyDeviceToHost);
printMatrix(hcheck, rows, columns);
cudaFree(dmatrix1);
cudaFree(dmatrix2);
cudaFree(dcheck);
free(hmatrix1);
free(hmatrix2);
free(hcheck);
return 0;
}
|
.file "tmpxft_001a1550_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%g "
.LC1:
.string "\n"
.text
.globl _Z11printMatrixPfii
.type _Z11printMatrixPfii, @function
_Z11printMatrixPfii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %edx, 12(%rsp)
testl %esi, %esi
jle .L4
movl %esi, %r15d
movl $0, %r14d
movl $0, %r13d
movl %edx, %eax
cltq
movq %rax, 24(%rsp)
leaq .LC0(%rip), %r12
jmp .L5
.L7:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L6:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
.L8:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, %r15d
je .L4
.L5:
cmpl $0, 12(%rsp)
jg .L7
jmp .L8
.L4:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11printMatrixPfii, .-_Z11printMatrixPfii
.globl _Z33__device_stub__Z13initMatrix_1DPfPf
.type _Z33__device_stub__Z13initMatrix_1DPfPf, @function
_Z33__device_stub__Z13initMatrix_1DPfPf:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13initMatrix_1DPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z13initMatrix_1DPfPf, .-_Z33__device_stub__Z13initMatrix_1DPfPf
.globl _Z13initMatrix_1DPf
.type _Z13initMatrix_1DPf, @function
_Z13initMatrix_1DPf:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z13initMatrix_1DPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z13initMatrix_1DPf, .-_Z13initMatrix_1DPf
.globl _Z35__device_stub__Z15initMatrix_2D_IPfPf
.type _Z35__device_stub__Z15initMatrix_2D_IPfPf, @function
_Z35__device_stub__Z15initMatrix_2D_IPfPf:
.LFB2085:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15initMatrix_2D_IPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z35__device_stub__Z15initMatrix_2D_IPfPf, .-_Z35__device_stub__Z15initMatrix_2D_IPfPf
.globl _Z15initMatrix_2D_IPf
.type _Z15initMatrix_2D_IPf, @function
_Z15initMatrix_2D_IPf:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z15initMatrix_2D_IPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z15initMatrix_2D_IPf, .-_Z15initMatrix_2D_IPf
.globl _Z35__device_stub__Z15initMatrix_2D_JPfPf
.type _Z35__device_stub__Z15initMatrix_2D_JPfPf, @function
_Z35__device_stub__Z15initMatrix_2D_JPfPf:
.LFB2087:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15initMatrix_2D_JPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z35__device_stub__Z15initMatrix_2D_JPfPf, .-_Z35__device_stub__Z15initMatrix_2D_JPfPf
.globl _Z15initMatrix_2D_JPf
.type _Z15initMatrix_2D_JPf, @function
_Z15initMatrix_2D_JPf:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z15initMatrix_2D_JPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z15initMatrix_2D_JPf, .-_Z15initMatrix_2D_JPf
.globl _Z29__device_stub__Z6transpPfS_S_PfS_S_
.type _Z29__device_stub__Z6transpPfS_S_PfS_S_, @function
_Z29__device_stub__Z6transpPfS_S_PfS_S_:
.LFB2089:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6transpPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z29__device_stub__Z6transpPfS_S_PfS_S_, .-_Z29__device_stub__Z6transpPfS_S_PfS_S_
.globl _Z6transpPfS_S_
.type _Z6transpPfS_S_, @function
_Z6transpPfS_S_:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6transpPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z6transpPfS_S_, .-_Z6transpPfS_S_
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $8, %r14d
cmpl $1, %edi
jg .L51
.L44:
movq %rsp, %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
movl $4, %esi
movl $64, %edi
call calloc@PLT
movq %rax, %r12
movl $4, %esi
movl $64, %edi
call calloc@PLT
movq %rax, %rbp
movl $4, %esi
movl $64, %edi
call calloc@PLT
movq %rax, %rbx
movl $4, %esi
movl $64, %edi
call calloc@PLT
movq %rax, %r13
movl $8, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $2, 32(%rsp)
movl $2, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L45:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $256, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $8, %edx
movl $8, %esi
movq %r13, %rdi
call _Z11printMatrixPfii
movl $2, 44(%rsp)
movl $2, 48(%rsp)
movl $1, 52(%rsp)
movl %r14d, %r13d
movl %r14d, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L46:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $256, %edx
movq (%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $8, %edx
movl $8, %esi
movq %r12, %rdi
call _Z11printMatrixPfii
movl $2, 44(%rsp)
movl $2, 48(%rsp)
movl $1, 52(%rsp)
movl %r13d, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L47:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $256, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $8, %edx
movl $8, %esi
movq %rbp, %rdi
call _Z11printMatrixPfii
movl $2, %ecx
movl $256, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $8, %edx
movl $8, %esi
movq %rbx, %rdi
call _Z11printMatrixPfii
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L55
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
movl %edi, %ebx
movq %rsi, %rbp
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r14d
cmpl $2, %ebx
jle .L44
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
jmp .L44
.L52:
movq 24(%rsp), %rdi
call _Z35__device_stub__Z15initMatrix_2D_IPfPf
jmp .L45
.L53:
movq (%rsp), %rdi
call _Z35__device_stub__Z15initMatrix_2D_IPfPf
jmp .L46
.L54:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z29__device_stub__Z6transpPfS_S_PfS_S_
jmp .L47
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6transpPfS_S_"
.LC3:
.string "_Z15initMatrix_2D_JPf"
.LC4:
.string "_Z15initMatrix_2D_IPf"
.LC5:
.string "_Z13initMatrix_1DPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6transpPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z15initMatrix_2D_JPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z15initMatrix_2D_IPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z13initMatrix_1DPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <cuda.h>
#include <stdio.h>
void printMatrix(float *matrix, int rows, int columns)
{
for (int i = 0; i < rows; i++) {
for (int j = 0; j < columns; j++)
printf("%g ", matrix[i * rows + j]);
printf("\n");
}
printf("\n");
}
#define CUDA_CHECK_RETURN(value)\
{\
cudaError_t _m_cudaStat = value;\
if (_m_cudaStat != cudaSuccess) {\
fprintf(stderr, "Error %s at line %d in file %s\n",\
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__);\
exit(1);\
}\
}
__global__ void initMatrix_1D(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
matrix[i] = i;
}
__global__ void initMatrix_2D_I(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int I = gridDim.x * blockDim.x;
// int J = gridDim.y * blockDim.y;
// matrix[j * I + i] = j * I + i;
// matrix[i + j * I] = i;
// matrix[i + j * I] = j;
// matrix[i + j * I] = I;
// matrix[i + j * I] = J;
matrix[i + j * I] = threadIdx.x;
// matrix[i + j * I] = threadIdx.y;
// matrix[i + j * I] = gridDim.x;
// matrix[i + j * I] = gridDim.y;
// matrix[i + j * I] = blockDim.x;
// matrix[i + j * I] = blockDim.y;
// matrix[i + j * I] = blockIdx.x;
// matrix[i + j * I] = blockIdx.y;
}
__global__ void initMatrix_2D_J(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
// int I = gridDim.x * blockDim.x;
int J = gridDim.y * blockDim.y;
matrix[j + i * J] = j + i * J;
}
__global__ void transp(float *matrix1, float *matrix2, float *check)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int I = gridDim.x * blockDim.x;
matrix2[i * I + j] = matrix1[j * I + i];
check[i * I + j] = j * I + i;
}
int main(int argc, char *argv[])
{
int blocks = (argc > 1) ? atoi(argv[1]) : 8;
int threads = (argc > 2) ? atoi(argv[2]) : 4;
int rows = 8;
int columns = 8;
int size_matrix = rows * columns;
float *dmatrix1, *hmatrix1;
float *dmatrix2, *hmatrix2;
float *dcheck, *hcheck;
float *dmatrix3, *hmatrix3;
cudaMalloc((void**) &dmatrix1, size_matrix * sizeof(float));
cudaMalloc((void**) &dmatrix2, size_matrix * sizeof(float));
cudaMalloc((void**) &dcheck, size_matrix * sizeof(float));
cudaMalloc((void**) &dmatrix3, size_matrix * sizeof(float));
hmatrix1 = (float*) calloc(size_matrix, sizeof(float));
hmatrix2 = (float*) calloc(size_matrix, sizeof(float));
hcheck = (float*) calloc(size_matrix, sizeof(float));
hmatrix3 = (float*) calloc(size_matrix, sizeof(float));
initMatrix_2D_I<<<dim3(2, 2), dim3(8)>>>(dmatrix3);
cudaDeviceSynchronize();
cudaMemcpy(hmatrix3, dmatrix3, size_matrix * sizeof(float), cudaMemcpyDeviceToHost);
printMatrix(hmatrix3, rows, columns);
// initMatrix_1D<<<dim3(blocks), dim3(threads)>>>(dmatrix1);
initMatrix_2D_I<<<dim3(blocks), dim3(2, 2)>>>(dmatrix1);
cudaDeviceSynchronize();
cudaMemcpy(hmatrix1, dmatrix1, size_matrix * sizeof(float), cudaMemcpyDeviceToHost);
printMatrix(hmatrix1, rows, columns);
#if 0
initMatrix_2D_J<<<dim3(blocks), dim3(2, 2)>>>(dmatrix2);
cudaDeviceSynchronize();
cudaMemcpy(hmatrix2, dmatrix2, size_matrix * sizeof(float), cudaMemcpyDeviceToHost);
printMatrix(hmatrix2, rows, columns);
#endif
transp<<<dim3(blocks), dim3(2, 2)>>>(dmatrix1, dmatrix2, dcheck);
cudaDeviceSynchronize();
cudaMemcpy(hmatrix2, dmatrix2, size_matrix * sizeof(float), cudaMemcpyDeviceToHost);
printMatrix(hmatrix2, rows, columns);
cudaMemcpy(hcheck, dcheck, size_matrix * sizeof(float), cudaMemcpyDeviceToHost);
printMatrix(hcheck, rows, columns);
cudaFree(dmatrix1);
cudaFree(dmatrix2);
cudaFree(dcheck);
free(hmatrix1);
free(hmatrix2);
free(hcheck);
return 0;
}
|
#include <hip/hip_runtime.h>
#include <stdio.h>
void printMatrix(float *matrix, int rows, int columns)
{
for (int i = 0; i < rows; i++) {
for (int j = 0; j < columns; j++)
printf("%g ", matrix[i * rows + j]);
printf("\n");
}
printf("\n");
}
#define CUDA_CHECK_RETURN(value)\
{\
hipError_t _m_cudaStat = value;\
if (_m_cudaStat != hipSuccess) {\
fprintf(stderr, "Error %s at line %d in file %s\n",\
hipGetErrorString(_m_cudaStat), __LINE__, __FILE__);\
exit(1);\
}\
}
__global__ void initMatrix_1D(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
matrix[i] = i;
}
__global__ void initMatrix_2D_I(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int I = gridDim.x * blockDim.x;
// int J = gridDim.y * blockDim.y;
// matrix[j * I + i] = j * I + i;
// matrix[i + j * I] = i;
// matrix[i + j * I] = j;
// matrix[i + j * I] = I;
// matrix[i + j * I] = J;
matrix[i + j * I] = threadIdx.x;
// matrix[i + j * I] = threadIdx.y;
// matrix[i + j * I] = gridDim.x;
// matrix[i + j * I] = gridDim.y;
// matrix[i + j * I] = blockDim.x;
// matrix[i + j * I] = blockDim.y;
// matrix[i + j * I] = blockIdx.x;
// matrix[i + j * I] = blockIdx.y;
}
__global__ void initMatrix_2D_J(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
// int I = gridDim.x * blockDim.x;
int J = gridDim.y * blockDim.y;
matrix[j + i * J] = j + i * J;
}
__global__ void transp(float *matrix1, float *matrix2, float *check)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int I = gridDim.x * blockDim.x;
matrix2[i * I + j] = matrix1[j * I + i];
check[i * I + j] = j * I + i;
}
int main(int argc, char *argv[])
{
int blocks = (argc > 1) ? atoi(argv[1]) : 8;
int threads = (argc > 2) ? atoi(argv[2]) : 4;
int rows = 8;
int columns = 8;
int size_matrix = rows * columns;
float *dmatrix1, *hmatrix1;
float *dmatrix2, *hmatrix2;
float *dcheck, *hcheck;
float *dmatrix3, *hmatrix3;
hipMalloc((void**) &dmatrix1, size_matrix * sizeof(float));
hipMalloc((void**) &dmatrix2, size_matrix * sizeof(float));
hipMalloc((void**) &dcheck, size_matrix * sizeof(float));
hipMalloc((void**) &dmatrix3, size_matrix * sizeof(float));
hmatrix1 = (float*) calloc(size_matrix, sizeof(float));
hmatrix2 = (float*) calloc(size_matrix, sizeof(float));
hcheck = (float*) calloc(size_matrix, sizeof(float));
hmatrix3 = (float*) calloc(size_matrix, sizeof(float));
initMatrix_2D_I<<<dim3(2, 2), dim3(8)>>>(dmatrix3);
hipDeviceSynchronize();
hipMemcpy(hmatrix3, dmatrix3, size_matrix * sizeof(float), hipMemcpyDeviceToHost);
printMatrix(hmatrix3, rows, columns);
// initMatrix_1D<<<dim3(blocks), dim3(threads)>>>(dmatrix1);
initMatrix_2D_I<<<dim3(blocks), dim3(2, 2)>>>(dmatrix1);
hipDeviceSynchronize();
hipMemcpy(hmatrix1, dmatrix1, size_matrix * sizeof(float), hipMemcpyDeviceToHost);
printMatrix(hmatrix1, rows, columns);
#if 0
initMatrix_2D_J<<<dim3(blocks), dim3(2, 2)>>>(dmatrix2);
hipDeviceSynchronize();
hipMemcpy(hmatrix2, dmatrix2, size_matrix * sizeof(float), hipMemcpyDeviceToHost);
printMatrix(hmatrix2, rows, columns);
#endif
transp<<<dim3(blocks), dim3(2, 2)>>>(dmatrix1, dmatrix2, dcheck);
hipDeviceSynchronize();
hipMemcpy(hmatrix2, dmatrix2, size_matrix * sizeof(float), hipMemcpyDeviceToHost);
printMatrix(hmatrix2, rows, columns);
hipMemcpy(hcheck, dcheck, size_matrix * sizeof(float), hipMemcpyDeviceToHost);
printMatrix(hcheck, rows, columns);
hipFree(dmatrix1);
hipFree(dmatrix2);
hipFree(dcheck);
free(hmatrix1);
free(hmatrix2);
free(hcheck);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
void printMatrix(float *matrix, int rows, int columns)
{
for (int i = 0; i < rows; i++) {
for (int j = 0; j < columns; j++)
printf("%g ", matrix[i * rows + j]);
printf("\n");
}
printf("\n");
}
#define CUDA_CHECK_RETURN(value)\
{\
hipError_t _m_cudaStat = value;\
if (_m_cudaStat != hipSuccess) {\
fprintf(stderr, "Error %s at line %d in file %s\n",\
hipGetErrorString(_m_cudaStat), __LINE__, __FILE__);\
exit(1);\
}\
}
__global__ void initMatrix_1D(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
matrix[i] = i;
}
__global__ void initMatrix_2D_I(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int I = gridDim.x * blockDim.x;
// int J = gridDim.y * blockDim.y;
// matrix[j * I + i] = j * I + i;
// matrix[i + j * I] = i;
// matrix[i + j * I] = j;
// matrix[i + j * I] = I;
// matrix[i + j * I] = J;
matrix[i + j * I] = threadIdx.x;
// matrix[i + j * I] = threadIdx.y;
// matrix[i + j * I] = gridDim.x;
// matrix[i + j * I] = gridDim.y;
// matrix[i + j * I] = blockDim.x;
// matrix[i + j * I] = blockDim.y;
// matrix[i + j * I] = blockIdx.x;
// matrix[i + j * I] = blockIdx.y;
}
__global__ void initMatrix_2D_J(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
// int I = gridDim.x * blockDim.x;
int J = gridDim.y * blockDim.y;
matrix[j + i * J] = j + i * J;
}
__global__ void transp(float *matrix1, float *matrix2, float *check)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int I = gridDim.x * blockDim.x;
matrix2[i * I + j] = matrix1[j * I + i];
check[i * I + j] = j * I + i;
}
int main(int argc, char *argv[])
{
int blocks = (argc > 1) ? atoi(argv[1]) : 8;
int threads = (argc > 2) ? atoi(argv[2]) : 4;
int rows = 8;
int columns = 8;
int size_matrix = rows * columns;
float *dmatrix1, *hmatrix1;
float *dmatrix2, *hmatrix2;
float *dcheck, *hcheck;
float *dmatrix3, *hmatrix3;
hipMalloc((void**) &dmatrix1, size_matrix * sizeof(float));
hipMalloc((void**) &dmatrix2, size_matrix * sizeof(float));
hipMalloc((void**) &dcheck, size_matrix * sizeof(float));
hipMalloc((void**) &dmatrix3, size_matrix * sizeof(float));
hmatrix1 = (float*) calloc(size_matrix, sizeof(float));
hmatrix2 = (float*) calloc(size_matrix, sizeof(float));
hcheck = (float*) calloc(size_matrix, sizeof(float));
hmatrix3 = (float*) calloc(size_matrix, sizeof(float));
initMatrix_2D_I<<<dim3(2, 2), dim3(8)>>>(dmatrix3);
hipDeviceSynchronize();
hipMemcpy(hmatrix3, dmatrix3, size_matrix * sizeof(float), hipMemcpyDeviceToHost);
printMatrix(hmatrix3, rows, columns);
// initMatrix_1D<<<dim3(blocks), dim3(threads)>>>(dmatrix1);
initMatrix_2D_I<<<dim3(blocks), dim3(2, 2)>>>(dmatrix1);
hipDeviceSynchronize();
hipMemcpy(hmatrix1, dmatrix1, size_matrix * sizeof(float), hipMemcpyDeviceToHost);
printMatrix(hmatrix1, rows, columns);
#if 0
initMatrix_2D_J<<<dim3(blocks), dim3(2, 2)>>>(dmatrix2);
hipDeviceSynchronize();
hipMemcpy(hmatrix2, dmatrix2, size_matrix * sizeof(float), hipMemcpyDeviceToHost);
printMatrix(hmatrix2, rows, columns);
#endif
transp<<<dim3(blocks), dim3(2, 2)>>>(dmatrix1, dmatrix2, dcheck);
hipDeviceSynchronize();
hipMemcpy(hmatrix2, dmatrix2, size_matrix * sizeof(float), hipMemcpyDeviceToHost);
printMatrix(hmatrix2, rows, columns);
hipMemcpy(hcheck, dcheck, size_matrix * sizeof(float), hipMemcpyDeviceToHost);
printMatrix(hcheck, rows, columns);
hipFree(dmatrix1);
hipFree(dmatrix2);
hipFree(dcheck);
free(hmatrix1);
free(hmatrix2);
free(hcheck);
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13initMatrix_1DPf
.globl _Z13initMatrix_1DPf
.p2align 8
.type _Z13initMatrix_1DPf,@function
_Z13initMatrix_1DPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f32_i32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13initMatrix_1DPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13initMatrix_1DPf, .Lfunc_end0-_Z13initMatrix_1DPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15initMatrix_2D_IPf
.globl _Z15initMatrix_2D_IPf
.p2align 8
.type _Z15initMatrix_2D_IPf,@function
_Z15initMatrix_2D_IPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b32 s3, s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
v_mad_u64_u32 v[1:2], null, v3, s2, v[0:1]
v_cvt_f32_u32_e32 v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15initMatrix_2D_IPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15initMatrix_2D_IPf, .Lfunc_end1-_Z15initMatrix_2D_IPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15initMatrix_2D_JPf
.globl _Z15initMatrix_2D_JPf
.p2align 8
.type _Z15initMatrix_2D_JPf,@function
_Z15initMatrix_2D_JPf:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x14
s_load_b32 s4, s[0:1], 0xc
v_and_b32_e32 v1, 0x3ff, v0
s_mov_b32 s2, s15
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s14, s5, v[1:2]
v_mad_u64_u32 v[3:4], null, v2, s4, s[2:3]
s_lshr_b32 s2, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, v3, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f32_i32_e32 v4, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15initMatrix_2D_JPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z15initMatrix_2D_JPf, .Lfunc_end2-_Z15initMatrix_2D_JPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6transpPfS_S_
.globl _Z6transpPfS_S_
.p2align 8
.type _Z6transpPfS_S_,@function
_Z6transpPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s4, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_mul_i32 s3, s3, s4
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s3, v[2:3]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v6, v[4:5], off
v_mad_u64_u32 v[4:5], null, v2, s3, v[3:4]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[4:5]
v_cvt_f32_i32_e32 v5, v0
v_add_co_u32 v3, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[3:4], v6, off
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6transpPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z6transpPfS_S_, .Lfunc_end3-_Z6transpPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13initMatrix_1DPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13initMatrix_1DPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15initMatrix_2D_IPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15initMatrix_2D_IPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15initMatrix_2D_JPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15initMatrix_2D_JPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6transpPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6transpPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
void printMatrix(float *matrix, int rows, int columns)
{
for (int i = 0; i < rows; i++) {
for (int j = 0; j < columns; j++)
printf("%g ", matrix[i * rows + j]);
printf("\n");
}
printf("\n");
}
#define CUDA_CHECK_RETURN(value)\
{\
hipError_t _m_cudaStat = value;\
if (_m_cudaStat != hipSuccess) {\
fprintf(stderr, "Error %s at line %d in file %s\n",\
hipGetErrorString(_m_cudaStat), __LINE__, __FILE__);\
exit(1);\
}\
}
__global__ void initMatrix_1D(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
matrix[i] = i;
}
__global__ void initMatrix_2D_I(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int I = gridDim.x * blockDim.x;
// int J = gridDim.y * blockDim.y;
// matrix[j * I + i] = j * I + i;
// matrix[i + j * I] = i;
// matrix[i + j * I] = j;
// matrix[i + j * I] = I;
// matrix[i + j * I] = J;
matrix[i + j * I] = threadIdx.x;
// matrix[i + j * I] = threadIdx.y;
// matrix[i + j * I] = gridDim.x;
// matrix[i + j * I] = gridDim.y;
// matrix[i + j * I] = blockDim.x;
// matrix[i + j * I] = blockDim.y;
// matrix[i + j * I] = blockIdx.x;
// matrix[i + j * I] = blockIdx.y;
}
__global__ void initMatrix_2D_J(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
// int I = gridDim.x * blockDim.x;
int J = gridDim.y * blockDim.y;
matrix[j + i * J] = j + i * J;
}
__global__ void transp(float *matrix1, float *matrix2, float *check)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int I = gridDim.x * blockDim.x;
matrix2[i * I + j] = matrix1[j * I + i];
check[i * I + j] = j * I + i;
}
int main(int argc, char *argv[])
{
int blocks = (argc > 1) ? atoi(argv[1]) : 8;
int threads = (argc > 2) ? atoi(argv[2]) : 4;
int rows = 8;
int columns = 8;
int size_matrix = rows * columns;
float *dmatrix1, *hmatrix1;
float *dmatrix2, *hmatrix2;
float *dcheck, *hcheck;
float *dmatrix3, *hmatrix3;
hipMalloc((void**) &dmatrix1, size_matrix * sizeof(float));
hipMalloc((void**) &dmatrix2, size_matrix * sizeof(float));
hipMalloc((void**) &dcheck, size_matrix * sizeof(float));
hipMalloc((void**) &dmatrix3, size_matrix * sizeof(float));
hmatrix1 = (float*) calloc(size_matrix, sizeof(float));
hmatrix2 = (float*) calloc(size_matrix, sizeof(float));
hcheck = (float*) calloc(size_matrix, sizeof(float));
hmatrix3 = (float*) calloc(size_matrix, sizeof(float));
initMatrix_2D_I<<<dim3(2, 2), dim3(8)>>>(dmatrix3);
hipDeviceSynchronize();
hipMemcpy(hmatrix3, dmatrix3, size_matrix * sizeof(float), hipMemcpyDeviceToHost);
printMatrix(hmatrix3, rows, columns);
// initMatrix_1D<<<dim3(blocks), dim3(threads)>>>(dmatrix1);
initMatrix_2D_I<<<dim3(blocks), dim3(2, 2)>>>(dmatrix1);
hipDeviceSynchronize();
hipMemcpy(hmatrix1, dmatrix1, size_matrix * sizeof(float), hipMemcpyDeviceToHost);
printMatrix(hmatrix1, rows, columns);
#if 0
initMatrix_2D_J<<<dim3(blocks), dim3(2, 2)>>>(dmatrix2);
hipDeviceSynchronize();
hipMemcpy(hmatrix2, dmatrix2, size_matrix * sizeof(float), hipMemcpyDeviceToHost);
printMatrix(hmatrix2, rows, columns);
#endif
transp<<<dim3(blocks), dim3(2, 2)>>>(dmatrix1, dmatrix2, dcheck);
hipDeviceSynchronize();
hipMemcpy(hmatrix2, dmatrix2, size_matrix * sizeof(float), hipMemcpyDeviceToHost);
printMatrix(hmatrix2, rows, columns);
hipMemcpy(hcheck, dcheck, size_matrix * sizeof(float), hipMemcpyDeviceToHost);
printMatrix(hcheck, rows, columns);
hipFree(dmatrix1);
hipFree(dmatrix2);
hipFree(dcheck);
free(hmatrix1);
free(hmatrix2);
free(hcheck);
return 0;
}
|
.text
.file "main.hip"
.globl _Z11printMatrixPfii # -- Begin function _Z11printMatrixPfii
.p2align 4, 0x90
.type _Z11printMatrixPfii,@function
_Z11printMatrixPfii: # @_Z11printMatrixPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, 4(%rsp) # 4-byte Spill
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB0_6
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebp
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl 4(%rsp), %r12d # 4-byte Reload
xorl %r13d, %r13d
xorl %r14d, %r14d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addl %ebp, %r13d
cmpq 16(%rsp), %r14 # 8-byte Folded Reload
je .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
cmpl $0, 4(%rsp) # 4-byte Folded Reload
jle .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB0_4
jmp .LBB0_5
.LBB0_6: # %._crit_edge14
movl $10, %edi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end0:
.size _Z11printMatrixPfii, .Lfunc_end0-_Z11printMatrixPfii
.cfi_endproc
# -- End function
.globl _Z28__device_stub__initMatrix_1DPf # -- Begin function _Z28__device_stub__initMatrix_1DPf
.p2align 4, 0x90
.type _Z28__device_stub__initMatrix_1DPf,@function
_Z28__device_stub__initMatrix_1DPf: # @_Z28__device_stub__initMatrix_1DPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z13initMatrix_1DPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z28__device_stub__initMatrix_1DPf, .Lfunc_end1-_Z28__device_stub__initMatrix_1DPf
.cfi_endproc
# -- End function
.globl _Z30__device_stub__initMatrix_2D_IPf # -- Begin function _Z30__device_stub__initMatrix_2D_IPf
.p2align 4, 0x90
.type _Z30__device_stub__initMatrix_2D_IPf,@function
_Z30__device_stub__initMatrix_2D_IPf: # @_Z30__device_stub__initMatrix_2D_IPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z15initMatrix_2D_IPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z30__device_stub__initMatrix_2D_IPf, .Lfunc_end2-_Z30__device_stub__initMatrix_2D_IPf
.cfi_endproc
# -- End function
.globl _Z30__device_stub__initMatrix_2D_JPf # -- Begin function _Z30__device_stub__initMatrix_2D_JPf
.p2align 4, 0x90
.type _Z30__device_stub__initMatrix_2D_JPf,@function
_Z30__device_stub__initMatrix_2D_JPf: # @_Z30__device_stub__initMatrix_2D_JPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z15initMatrix_2D_JPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z30__device_stub__initMatrix_2D_JPf, .Lfunc_end3-_Z30__device_stub__initMatrix_2D_JPf
.cfi_endproc
# -- End function
.globl _Z21__device_stub__transpPfS_S_ # -- Begin function _Z21__device_stub__transpPfS_S_
.p2align 4, 0x90
.type _Z21__device_stub__transpPfS_S_,@function
_Z21__device_stub__transpPfS_S_: # @_Z21__device_stub__transpPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6transpPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z21__device_stub__transpPfS_S_, .Lfunc_end4-_Z21__device_stub__transpPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967304, %r12 # imm = 0x100000008
movq %r12, %r13
cmpl $2, %edi
jl .LBB5_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, %eax
leaq (%r12,%rax), %r13
addq $-8, %r13
.LBB5_2:
movabsq $8589934594, %rbx # imm = 0x200000002
leaq 40(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
leaq 72(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
leaq 64(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
leaq 112(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movl $64, %edi
movl $4, %esi
callq calloc
movq %rax, 104(%rsp) # 8-byte Spill
movl $64, %edi
movl $4, %esi
callq calloc
movq %rax, %r14
movl $64, %edi
movl $4, %esi
callq calloc
movq %rax, %r15
movl $64, %edi
movl $4, %esi
callq calloc
movq %rax, %rbp
movq %rbx, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_4
# %bb.3:
movq 112(%rsp), %rax
movq %rax, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, (%rsp)
leaq 80(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movq %rsp, %r9
movl $_Z15initMatrix_2D_IPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_4:
callq hipDeviceSynchronize
movq 112(%rsp), %rsi
movl $256, %edx # imm = 0x100
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB5_6 Depth 2
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB5_6: # Parent Loop BB5_5 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $8, %rbx
jne .LBB5_6
# %bb.7: # %._crit_edge.i
# in Loop: Header=BB5_5 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addq $32, %rbp
cmpq $8, %r12
jne .LBB5_5
# %bb.8: # %_Z11printMatrixPfii.exit
movl $10, %edi
callq putchar@PLT
movq %r13, %rdi
movl $1, %esi
movabsq $8589934594, %rdx # imm = 0x200000002
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_10
# %bb.9:
movq 40(%rsp), %rax
movq %rax, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, (%rsp)
leaq 80(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movq %rsp, %r9
movl $_Z15initMatrix_2D_IPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_10:
callq hipDeviceSynchronize
movq 40(%rsp), %rsi
movl $256, %edx # imm = 0x100
movq 104(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_11: # %.preheader.i56
# =>This Loop Header: Depth=1
# Child Loop BB5_12 Depth 2
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB5_12: # Parent Loop BB5_11 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $8, %rbx
jne .LBB5_12
# %bb.13: # %._crit_edge.i61
# in Loop: Header=BB5_11 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addq $32, %rbp
cmpq $8, %r12
jne .LBB5_11
# %bb.14: # %_Z11printMatrixPfii.exit66
movl $10, %edi
callq putchar@PLT
movq %r13, %rdi
movl $1, %esi
movabsq $8589934594, %rdx # imm = 0x200000002
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_16
# %bb.15:
movq 40(%rsp), %rax
movq 72(%rsp), %rcx
movq 64(%rsp), %rdx
movq %rax, 32(%rsp)
movq %rcx, 24(%rsp)
movq %rdx, (%rsp)
leaq 32(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6transpPfS_S_, %edi
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_16:
callq hipDeviceSynchronize
movq 72(%rsp), %rsi
movl $256, %edx # imm = 0x100
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
movq %r14, %r13
.p2align 4, 0x90
.LBB5_17: # %.preheader.i73
# =>This Loop Header: Depth=1
# Child Loop BB5_18 Depth 2
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB5_18: # Parent Loop BB5_17 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r13,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $8, %rbx
jne .LBB5_18
# %bb.19: # %._crit_edge.i78
# in Loop: Header=BB5_17 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addq $32, %r13
cmpq $8, %r12
jne .LBB5_17
# %bb.20: # %_Z11printMatrixPfii.exit83
movl $10, %edi
callq putchar@PLT
movq 64(%rsp), %rsi
movl $256, %edx # imm = 0x100
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
movq %r15, %r13
.p2align 4, 0x90
.LBB5_21: # %.preheader.i84
# =>This Loop Header: Depth=1
# Child Loop BB5_22 Depth 2
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB5_22: # Parent Loop BB5_21 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r13,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $8, %rbx
jne .LBB5_22
# %bb.23: # %._crit_edge.i89
# in Loop: Header=BB5_21 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addq $32, %r13
cmpq $8, %r12
jne .LBB5_21
# %bb.24: # %_Z11printMatrixPfii.exit94
movl $10, %edi
callq putchar@PLT
movq 40(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 104(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13initMatrix_1DPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15initMatrix_2D_IPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15initMatrix_2D_JPf, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6transpPfS_S_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%g "
.size .L.str, 4
.type _Z13initMatrix_1DPf,@object # @_Z13initMatrix_1DPf
.section .rodata,"a",@progbits
.globl _Z13initMatrix_1DPf
.p2align 3, 0x0
_Z13initMatrix_1DPf:
.quad _Z28__device_stub__initMatrix_1DPf
.size _Z13initMatrix_1DPf, 8
.type _Z15initMatrix_2D_IPf,@object # @_Z15initMatrix_2D_IPf
.globl _Z15initMatrix_2D_IPf
.p2align 3, 0x0
_Z15initMatrix_2D_IPf:
.quad _Z30__device_stub__initMatrix_2D_IPf
.size _Z15initMatrix_2D_IPf, 8
.type _Z15initMatrix_2D_JPf,@object # @_Z15initMatrix_2D_JPf
.globl _Z15initMatrix_2D_JPf
.p2align 3, 0x0
_Z15initMatrix_2D_JPf:
.quad _Z30__device_stub__initMatrix_2D_JPf
.size _Z15initMatrix_2D_JPf, 8
.type _Z6transpPfS_S_,@object # @_Z6transpPfS_S_
.globl _Z6transpPfS_S_
.p2align 3, 0x0
_Z6transpPfS_S_:
.quad _Z21__device_stub__transpPfS_S_
.size _Z6transpPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13initMatrix_1DPf"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15initMatrix_2D_IPf"
.size .L__unnamed_2, 22
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z15initMatrix_2D_JPf"
.size .L__unnamed_3, 22
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z6transpPfS_S_"
.size .L__unnamed_4, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__initMatrix_1DPf
.addrsig_sym _Z30__device_stub__initMatrix_2D_IPf
.addrsig_sym _Z30__device_stub__initMatrix_2D_JPf
.addrsig_sym _Z21__device_stub__transpPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13initMatrix_1DPf
.addrsig_sym _Z15initMatrix_2D_IPf
.addrsig_sym _Z15initMatrix_2D_JPf
.addrsig_sym _Z6transpPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z6transpPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC UR4, c[0x0][0xc] ; /* 0x0000030000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe20000000800 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0060*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe4000f8e023f */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002200 */
/*0090*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002600 */
/*00a0*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc400078e0200 */
/*00b0*/ IMAD R5, R2, c[0x0][0x4], R5 ; /* 0x0000010002057a24 */
/* 0x002fc800078e0205 */
/*00c0*/ IMAD R8, R5, UR4, R0 ; /* 0x0000000405087c24 */
/* 0x000fc8000f8e0200 */
/*00d0*/ IMAD.WIDE R2, R8, R7, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x000fcc00078e0207 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ I2F R9, R8 ; /* 0x0000000800097306 */
/* 0x000e220000201400 */
/*0100*/ IMAD R0, R0, UR4, R5 ; /* 0x0000000400007c24 */
/* 0x000fc8000f8e0205 */
/*0110*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*0120*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*0130*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe8000c101906 */
/*0140*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x001fe2000c101906 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15initMatrix_2D_JPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0040*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e680000002600 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000ea20000002200 */
/*0060*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fe200078e0200 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc600000001ff */
/*0080*/ IMAD R0, R0, c[0x0][0x10], R7 ; /* 0x0000040000007a24 */
/* 0x002fc800078e0207 */
/*0090*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x004fc800078e0205 */
/*00a0*/ I2F R5, R0 ; /* 0x0000000000057306 */
/* 0x000e220000201400 */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15initMatrix_2D_IPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e680000002100 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002500 */
/*0060*/ IMAD R0, R5, c[0x0][0x4], R0 ; /* 0x0000010005007a24 */
/* 0x001fe400078e0200 */
/*0070*/ I2F.U32 R5, R7 ; /* 0x0000000700057306 */
/* 0x002e240000201000 */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x004fe200078e0203 */
/*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc600000001ff */
/*00a0*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x000fce00078e0207 */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13initMatrix_1DPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0040*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fe200078e0200 */
/*0050*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc600000001ff */
/*0060*/ I2F R5, R0 ; /* 0x0000000000057306 */
/* 0x000e2e0000201400 */
/*0070*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13initMatrix_1DPf
.globl _Z13initMatrix_1DPf
.p2align 8
.type _Z13initMatrix_1DPf,@function
_Z13initMatrix_1DPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f32_i32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13initMatrix_1DPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13initMatrix_1DPf, .Lfunc_end0-_Z13initMatrix_1DPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15initMatrix_2D_IPf
.globl _Z15initMatrix_2D_IPf
.p2align 8
.type _Z15initMatrix_2D_IPf,@function
_Z15initMatrix_2D_IPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b32 s3, s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
v_mad_u64_u32 v[1:2], null, v3, s2, v[0:1]
v_cvt_f32_u32_e32 v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15initMatrix_2D_IPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15initMatrix_2D_IPf, .Lfunc_end1-_Z15initMatrix_2D_IPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15initMatrix_2D_JPf
.globl _Z15initMatrix_2D_JPf
.p2align 8
.type _Z15initMatrix_2D_JPf,@function
_Z15initMatrix_2D_JPf:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x14
s_load_b32 s4, s[0:1], 0xc
v_and_b32_e32 v1, 0x3ff, v0
s_mov_b32 s2, s15
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s14, s5, v[1:2]
v_mad_u64_u32 v[3:4], null, v2, s4, s[2:3]
s_lshr_b32 s2, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, v3, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f32_i32_e32 v4, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15initMatrix_2D_JPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z15initMatrix_2D_JPf, .Lfunc_end2-_Z15initMatrix_2D_JPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6transpPfS_S_
.globl _Z6transpPfS_S_
.p2align 8
.type _Z6transpPfS_S_,@function
_Z6transpPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s4, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_mul_i32 s3, s3, s4
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s3, v[2:3]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v6, v[4:5], off
v_mad_u64_u32 v[4:5], null, v2, s3, v[3:4]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[4:5]
v_cvt_f32_i32_e32 v5, v0
v_add_co_u32 v3, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[3:4], v6, off
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6transpPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z6transpPfS_S_, .Lfunc_end3-_Z6transpPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13initMatrix_1DPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13initMatrix_1DPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15initMatrix_2D_IPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15initMatrix_2D_IPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15initMatrix_2D_JPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15initMatrix_2D_JPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6transpPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6transpPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001a1550_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%g "
.LC1:
.string "\n"
.text
.globl _Z11printMatrixPfii
.type _Z11printMatrixPfii, @function
_Z11printMatrixPfii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %edx, 12(%rsp)
testl %esi, %esi
jle .L4
movl %esi, %r15d
movl $0, %r14d
movl $0, %r13d
movl %edx, %eax
cltq
movq %rax, 24(%rsp)
leaq .LC0(%rip), %r12
jmp .L5
.L7:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L6:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
.L8:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, %r15d
je .L4
.L5:
cmpl $0, 12(%rsp)
jg .L7
jmp .L8
.L4:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11printMatrixPfii, .-_Z11printMatrixPfii
.globl _Z33__device_stub__Z13initMatrix_1DPfPf
.type _Z33__device_stub__Z13initMatrix_1DPfPf, @function
_Z33__device_stub__Z13initMatrix_1DPfPf:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13initMatrix_1DPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z13initMatrix_1DPfPf, .-_Z33__device_stub__Z13initMatrix_1DPfPf
.globl _Z13initMatrix_1DPf
.type _Z13initMatrix_1DPf, @function
_Z13initMatrix_1DPf:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z13initMatrix_1DPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z13initMatrix_1DPf, .-_Z13initMatrix_1DPf
.globl _Z35__device_stub__Z15initMatrix_2D_IPfPf
.type _Z35__device_stub__Z15initMatrix_2D_IPfPf, @function
_Z35__device_stub__Z15initMatrix_2D_IPfPf:
.LFB2085:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15initMatrix_2D_IPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z35__device_stub__Z15initMatrix_2D_IPfPf, .-_Z35__device_stub__Z15initMatrix_2D_IPfPf
.globl _Z15initMatrix_2D_IPf
.type _Z15initMatrix_2D_IPf, @function
_Z15initMatrix_2D_IPf:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z15initMatrix_2D_IPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z15initMatrix_2D_IPf, .-_Z15initMatrix_2D_IPf
.globl _Z35__device_stub__Z15initMatrix_2D_JPfPf
.type _Z35__device_stub__Z15initMatrix_2D_JPfPf, @function
_Z35__device_stub__Z15initMatrix_2D_JPfPf:
.LFB2087:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15initMatrix_2D_JPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z35__device_stub__Z15initMatrix_2D_JPfPf, .-_Z35__device_stub__Z15initMatrix_2D_JPfPf
.globl _Z15initMatrix_2D_JPf
.type _Z15initMatrix_2D_JPf, @function
_Z15initMatrix_2D_JPf:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z15initMatrix_2D_JPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z15initMatrix_2D_JPf, .-_Z15initMatrix_2D_JPf
.globl _Z29__device_stub__Z6transpPfS_S_PfS_S_
.type _Z29__device_stub__Z6transpPfS_S_PfS_S_, @function
_Z29__device_stub__Z6transpPfS_S_PfS_S_:
.LFB2089:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6transpPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z29__device_stub__Z6transpPfS_S_PfS_S_, .-_Z29__device_stub__Z6transpPfS_S_PfS_S_
.globl _Z6transpPfS_S_
.type _Z6transpPfS_S_, @function
_Z6transpPfS_S_:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6transpPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z6transpPfS_S_, .-_Z6transpPfS_S_
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $8, %r14d
cmpl $1, %edi
jg .L51
.L44:
movq %rsp, %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
movl $4, %esi
movl $64, %edi
call calloc@PLT
movq %rax, %r12
movl $4, %esi
movl $64, %edi
call calloc@PLT
movq %rax, %rbp
movl $4, %esi
movl $64, %edi
call calloc@PLT
movq %rax, %rbx
movl $4, %esi
movl $64, %edi
call calloc@PLT
movq %rax, %r13
movl $8, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $2, 32(%rsp)
movl $2, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L45:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $256, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $8, %edx
movl $8, %esi
movq %r13, %rdi
call _Z11printMatrixPfii
movl $2, 44(%rsp)
movl $2, 48(%rsp)
movl $1, 52(%rsp)
movl %r14d, %r13d
movl %r14d, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L46:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $256, %edx
movq (%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $8, %edx
movl $8, %esi
movq %r12, %rdi
call _Z11printMatrixPfii
movl $2, 44(%rsp)
movl $2, 48(%rsp)
movl $1, 52(%rsp)
movl %r13d, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L47:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $256, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $8, %edx
movl $8, %esi
movq %rbp, %rdi
call _Z11printMatrixPfii
movl $2, %ecx
movl $256, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $8, %edx
movl $8, %esi
movq %rbx, %rdi
call _Z11printMatrixPfii
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L55
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
movl %edi, %ebx
movq %rsi, %rbp
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r14d
cmpl $2, %ebx
jle .L44
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
jmp .L44
.L52:
movq 24(%rsp), %rdi
call _Z35__device_stub__Z15initMatrix_2D_IPfPf
jmp .L45
.L53:
movq (%rsp), %rdi
call _Z35__device_stub__Z15initMatrix_2D_IPfPf
jmp .L46
.L54:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z29__device_stub__Z6transpPfS_S_PfS_S_
jmp .L47
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6transpPfS_S_"
.LC3:
.string "_Z15initMatrix_2D_JPf"
.LC4:
.string "_Z15initMatrix_2D_IPf"
.LC5:
.string "_Z13initMatrix_1DPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6transpPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z15initMatrix_2D_JPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z15initMatrix_2D_IPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z13initMatrix_1DPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "main.hip"
.globl _Z11printMatrixPfii # -- Begin function _Z11printMatrixPfii
.p2align 4, 0x90
.type _Z11printMatrixPfii,@function
_Z11printMatrixPfii: # @_Z11printMatrixPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, 4(%rsp) # 4-byte Spill
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB0_6
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebp
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl 4(%rsp), %r12d # 4-byte Reload
xorl %r13d, %r13d
xorl %r14d, %r14d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addl %ebp, %r13d
cmpq 16(%rsp), %r14 # 8-byte Folded Reload
je .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
cmpl $0, 4(%rsp) # 4-byte Folded Reload
jle .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB0_4
jmp .LBB0_5
.LBB0_6: # %._crit_edge14
movl $10, %edi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end0:
.size _Z11printMatrixPfii, .Lfunc_end0-_Z11printMatrixPfii
.cfi_endproc
# -- End function
.globl _Z28__device_stub__initMatrix_1DPf # -- Begin function _Z28__device_stub__initMatrix_1DPf
.p2align 4, 0x90
.type _Z28__device_stub__initMatrix_1DPf,@function
_Z28__device_stub__initMatrix_1DPf: # @_Z28__device_stub__initMatrix_1DPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z13initMatrix_1DPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z28__device_stub__initMatrix_1DPf, .Lfunc_end1-_Z28__device_stub__initMatrix_1DPf
.cfi_endproc
# -- End function
.globl _Z30__device_stub__initMatrix_2D_IPf # -- Begin function _Z30__device_stub__initMatrix_2D_IPf
.p2align 4, 0x90
.type _Z30__device_stub__initMatrix_2D_IPf,@function
_Z30__device_stub__initMatrix_2D_IPf: # @_Z30__device_stub__initMatrix_2D_IPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z15initMatrix_2D_IPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z30__device_stub__initMatrix_2D_IPf, .Lfunc_end2-_Z30__device_stub__initMatrix_2D_IPf
.cfi_endproc
# -- End function
.globl _Z30__device_stub__initMatrix_2D_JPf # -- Begin function _Z30__device_stub__initMatrix_2D_JPf
.p2align 4, 0x90
.type _Z30__device_stub__initMatrix_2D_JPf,@function
_Z30__device_stub__initMatrix_2D_JPf: # @_Z30__device_stub__initMatrix_2D_JPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z15initMatrix_2D_JPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z30__device_stub__initMatrix_2D_JPf, .Lfunc_end3-_Z30__device_stub__initMatrix_2D_JPf
.cfi_endproc
# -- End function
.globl _Z21__device_stub__transpPfS_S_ # -- Begin function _Z21__device_stub__transpPfS_S_
.p2align 4, 0x90
.type _Z21__device_stub__transpPfS_S_,@function
_Z21__device_stub__transpPfS_S_: # @_Z21__device_stub__transpPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6transpPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z21__device_stub__transpPfS_S_, .Lfunc_end4-_Z21__device_stub__transpPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967304, %r12 # imm = 0x100000008
movq %r12, %r13
cmpl $2, %edi
jl .LBB5_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, %eax
leaq (%r12,%rax), %r13
addq $-8, %r13
.LBB5_2:
movabsq $8589934594, %rbx # imm = 0x200000002
leaq 40(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
leaq 72(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
leaq 64(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
leaq 112(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movl $64, %edi
movl $4, %esi
callq calloc
movq %rax, 104(%rsp) # 8-byte Spill
movl $64, %edi
movl $4, %esi
callq calloc
movq %rax, %r14
movl $64, %edi
movl $4, %esi
callq calloc
movq %rax, %r15
movl $64, %edi
movl $4, %esi
callq calloc
movq %rax, %rbp
movq %rbx, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_4
# %bb.3:
movq 112(%rsp), %rax
movq %rax, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, (%rsp)
leaq 80(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movq %rsp, %r9
movl $_Z15initMatrix_2D_IPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_4:
callq hipDeviceSynchronize
movq 112(%rsp), %rsi
movl $256, %edx # imm = 0x100
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB5_6 Depth 2
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB5_6: # Parent Loop BB5_5 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $8, %rbx
jne .LBB5_6
# %bb.7: # %._crit_edge.i
# in Loop: Header=BB5_5 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addq $32, %rbp
cmpq $8, %r12
jne .LBB5_5
# %bb.8: # %_Z11printMatrixPfii.exit
movl $10, %edi
callq putchar@PLT
movq %r13, %rdi
movl $1, %esi
movabsq $8589934594, %rdx # imm = 0x200000002
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_10
# %bb.9:
movq 40(%rsp), %rax
movq %rax, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, (%rsp)
leaq 80(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movq %rsp, %r9
movl $_Z15initMatrix_2D_IPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_10:
callq hipDeviceSynchronize
movq 40(%rsp), %rsi
movl $256, %edx # imm = 0x100
movq 104(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_11: # %.preheader.i56
# =>This Loop Header: Depth=1
# Child Loop BB5_12 Depth 2
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB5_12: # Parent Loop BB5_11 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $8, %rbx
jne .LBB5_12
# %bb.13: # %._crit_edge.i61
# in Loop: Header=BB5_11 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addq $32, %rbp
cmpq $8, %r12
jne .LBB5_11
# %bb.14: # %_Z11printMatrixPfii.exit66
movl $10, %edi
callq putchar@PLT
movq %r13, %rdi
movl $1, %esi
movabsq $8589934594, %rdx # imm = 0x200000002
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_16
# %bb.15:
movq 40(%rsp), %rax
movq 72(%rsp), %rcx
movq 64(%rsp), %rdx
movq %rax, 32(%rsp)
movq %rcx, 24(%rsp)
movq %rdx, (%rsp)
leaq 32(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6transpPfS_S_, %edi
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_16:
callq hipDeviceSynchronize
movq 72(%rsp), %rsi
movl $256, %edx # imm = 0x100
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
movq %r14, %r13
.p2align 4, 0x90
.LBB5_17: # %.preheader.i73
# =>This Loop Header: Depth=1
# Child Loop BB5_18 Depth 2
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB5_18: # Parent Loop BB5_17 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r13,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $8, %rbx
jne .LBB5_18
# %bb.19: # %._crit_edge.i78
# in Loop: Header=BB5_17 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addq $32, %r13
cmpq $8, %r12
jne .LBB5_17
# %bb.20: # %_Z11printMatrixPfii.exit83
movl $10, %edi
callq putchar@PLT
movq 64(%rsp), %rsi
movl $256, %edx # imm = 0x100
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
movq %r15, %r13
.p2align 4, 0x90
.LBB5_21: # %.preheader.i84
# =>This Loop Header: Depth=1
# Child Loop BB5_22 Depth 2
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB5_22: # Parent Loop BB5_21 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r13,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $8, %rbx
jne .LBB5_22
# %bb.23: # %._crit_edge.i89
# in Loop: Header=BB5_21 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addq $32, %r13
cmpq $8, %r12
jne .LBB5_21
# %bb.24: # %_Z11printMatrixPfii.exit94
movl $10, %edi
callq putchar@PLT
movq 40(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 104(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13initMatrix_1DPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15initMatrix_2D_IPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15initMatrix_2D_JPf, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6transpPfS_S_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%g "
.size .L.str, 4
.type _Z13initMatrix_1DPf,@object # @_Z13initMatrix_1DPf
.section .rodata,"a",@progbits
.globl _Z13initMatrix_1DPf
.p2align 3, 0x0
_Z13initMatrix_1DPf:
.quad _Z28__device_stub__initMatrix_1DPf
.size _Z13initMatrix_1DPf, 8
.type _Z15initMatrix_2D_IPf,@object # @_Z15initMatrix_2D_IPf
.globl _Z15initMatrix_2D_IPf
.p2align 3, 0x0
_Z15initMatrix_2D_IPf:
.quad _Z30__device_stub__initMatrix_2D_IPf
.size _Z15initMatrix_2D_IPf, 8
.type _Z15initMatrix_2D_JPf,@object # @_Z15initMatrix_2D_JPf
.globl _Z15initMatrix_2D_JPf
.p2align 3, 0x0
_Z15initMatrix_2D_JPf:
.quad _Z30__device_stub__initMatrix_2D_JPf
.size _Z15initMatrix_2D_JPf, 8
.type _Z6transpPfS_S_,@object # @_Z6transpPfS_S_
.globl _Z6transpPfS_S_
.p2align 3, 0x0
_Z6transpPfS_S_:
.quad _Z21__device_stub__transpPfS_S_
.size _Z6transpPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13initMatrix_1DPf"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15initMatrix_2D_IPf"
.size .L__unnamed_2, 22
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z15initMatrix_2D_JPf"
.size .L__unnamed_3, 22
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z6transpPfS_S_"
.size .L__unnamed_4, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__initMatrix_1DPf
.addrsig_sym _Z30__device_stub__initMatrix_2D_IPf
.addrsig_sym _Z30__device_stub__initMatrix_2D_JPf
.addrsig_sym _Z21__device_stub__transpPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13initMatrix_1DPf
.addrsig_sym _Z15initMatrix_2D_IPf
.addrsig_sym _Z15initMatrix_2D_JPf
.addrsig_sym _Z6transpPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <math.h>
// sin(x*x)*cos(x)*x - x*x
#define XMIN 0.0
#define XMAX 10.0
#define N 10000
double vh[N], vd[N];
__device__ __host__ double funcion(double x) {
return sin(x*x)*cos(x)*x - x*x;
}
__global__ void kernelEvaluaFuncion(double *v, double xmin, double xmax, int n){
int i=threadIdx.x + blockIdx.x*blockDim.x;
double dx= (xmax-xmin)/(double)(n-1);
double x = xmin + i*dx;
v[i] = funcion(x);
}
void llenaPolinomioEnDevice(double *v, int n) {
double *vD;
int size = n*sizeof(double);
cudaMalloc(&vD, size);
kernelEvaluaFuncion<<<10, 1000>>>(vD, XMIN, XMAX, n);
cudaMemcpy(v, vD, size, cudaMemcpyDeviceToHost);
cudaFree(vD);
}
void llenaPolinomioEnHost(double *v, int n) {
int i;
double x, dx;
dx = (XMAX-XMIN)/(double)(N-1);
x = XMIN;
for (i=0; i<N; i++) {
v[i] = funcion(x);
x+=dx;
}
}
int main() {
int i;
double x, dx;
dx = (XMAX-XMIN)/(double)(N-1);
llenaPolinomioEnHost(vh, N);
llenaPolinomioEnDevice(vd, N);
x = XMIN;
for (i=0; i<N; i++) {
printf("%4d %4.2lf %6.12lf %6.12lf\n", i, x, vh[i], vd[i]);
x+=dx;
}
}
|
.file "tmpxft_00037217_00000000-6_polinomio.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7funciond
.type _Z7funciond, @function
_Z7funciond:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movapd %xmm0, %xmm1
movsd %xmm0, 8(%rsp)
mulsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp)
movapd %xmm1, %xmm0
call sin@PLT
movsd %xmm0, 24(%rsp)
movsd 8(%rsp), %xmm0
call cos@PLT
mulsd 24(%rsp), %xmm0
mulsd 8(%rsp), %xmm0
subsd 16(%rsp), %xmm0
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z7funciond, .-_Z7funciond
.globl _Z20llenaPolinomioEnHostPdi
.type _Z20llenaPolinomioEnHostPdi, @function
_Z20llenaPolinomioEnHostPdi:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
leaq 80000(%rdi), %rbp
movl $0x000000000, %r12d
.L6:
movq %r12, %xmm0
call _Z7funciond
movsd %xmm0, (%rbx)
movq %r12, %xmm1
addsd .LC1(%rip), %xmm1
movq %xmm1, %r12
addq $8, %rbx
cmpq %rbp, %rbx
jne .L6
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z20llenaPolinomioEnHostPdi, .-_Z20llenaPolinomioEnHostPdi
.globl _Z42__device_stub__Z19kernelEvaluaFuncionPdddiPdddi
.type _Z42__device_stub__Z19kernelEvaluaFuncionPdddiPdddi, @function
_Z42__device_stub__Z19kernelEvaluaFuncionPdddiPdddi:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19kernelEvaluaFuncionPdddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z42__device_stub__Z19kernelEvaluaFuncionPdddiPdddi, .-_Z42__device_stub__Z19kernelEvaluaFuncionPdddiPdddi
.globl _Z19kernelEvaluaFuncionPdddi
.type _Z19kernelEvaluaFuncionPdddi, @function
_Z19kernelEvaluaFuncionPdddi:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z19kernelEvaluaFuncionPdddiPdddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z19kernelEvaluaFuncionPdddi, .-_Z19kernelEvaluaFuncionPdddi
.globl _Z22llenaPolinomioEnDevicePdi
.type _Z22llenaPolinomioEnDevicePdi, @function
_Z22llenaPolinomioEnDevicePdi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leal 0(,%rsi,8), %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1000, 28(%rsp)
movl $1, 32(%rsp)
movl $10, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L18:
movl $2, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl %ebp, %esi
movsd .LC2(%rip), %xmm1
pxor %xmm0, %xmm0
movq 8(%rsp), %rdi
call _Z42__device_stub__Z19kernelEvaluaFuncionPdddiPdddi
jmp .L18
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z22llenaPolinomioEnDevicePdi, .-_Z22llenaPolinomioEnDevicePdi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "%4d %4.2lf %6.12lf %6.12lf\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl $10000, %esi
leaq vh(%rip), %rdi
call _Z20llenaPolinomioEnHostPdi
movl $10000, %esi
leaq vd(%rip), %rdi
call _Z22llenaPolinomioEnDevicePdi
movl $0, %ebx
movl $0x000000000, %r14d
leaq vd(%rip), %r13
leaq vh(%rip), %r12
leaq .LC3(%rip), %rbp
.L24:
movsd 0(%r13,%rbx,8), %xmm2
movsd (%r12,%rbx,8), %xmm1
movq %r14, %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
movq %r14, %xmm3
addsd .LC1(%rip), %xmm3
movq %xmm3, %r14
addq $1, %rbx
cmpq $10000, %rbx
jne .L24
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "_Z19kernelEvaluaFuncionPdddi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z19kernelEvaluaFuncionPdddi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl vd
.bss
.align 32
.type vd, @object
.size vd, 80000
vd:
.zero 80000
.globl vh
.align 32
.type vh, @object
.size vh, 80000
vh:
.zero 80000
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 897308399
.long 1062232761
.align 8
.LC2:
.long 0
.long 1076101120
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <math.h>
// sin(x*x)*cos(x)*x - x*x
#define XMIN 0.0
#define XMAX 10.0
#define N 10000
double vh[N], vd[N];
__device__ __host__ double funcion(double x) {
return sin(x*x)*cos(x)*x - x*x;
}
__global__ void kernelEvaluaFuncion(double *v, double xmin, double xmax, int n){
int i=threadIdx.x + blockIdx.x*blockDim.x;
double dx= (xmax-xmin)/(double)(n-1);
double x = xmin + i*dx;
v[i] = funcion(x);
}
void llenaPolinomioEnDevice(double *v, int n) {
double *vD;
int size = n*sizeof(double);
cudaMalloc(&vD, size);
kernelEvaluaFuncion<<<10, 1000>>>(vD, XMIN, XMAX, n);
cudaMemcpy(v, vD, size, cudaMemcpyDeviceToHost);
cudaFree(vD);
}
void llenaPolinomioEnHost(double *v, int n) {
int i;
double x, dx;
dx = (XMAX-XMIN)/(double)(N-1);
x = XMIN;
for (i=0; i<N; i++) {
v[i] = funcion(x);
x+=dx;
}
}
int main() {
int i;
double x, dx;
dx = (XMAX-XMIN)/(double)(N-1);
llenaPolinomioEnHost(vh, N);
llenaPolinomioEnDevice(vd, N);
x = XMIN;
for (i=0; i<N; i++) {
printf("%4d %4.2lf %6.12lf %6.12lf\n", i, x, vh[i], vd[i]);
x+=dx;
}
}
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
// sin(x*x)*cos(x)*x - x*x
#define XMIN 0.0
#define XMAX 10.0
#define N 10000
double vh[N], vd[N];
__device__ __host__ double funcion(double x) {
return sin(x*x)*cos(x)*x - x*x;
}
__global__ void kernelEvaluaFuncion(double *v, double xmin, double xmax, int n){
int i=threadIdx.x + blockIdx.x*blockDim.x;
double dx= (xmax-xmin)/(double)(n-1);
double x = xmin + i*dx;
v[i] = funcion(x);
}
void llenaPolinomioEnDevice(double *v, int n) {
double *vD;
int size = n*sizeof(double);
hipMalloc(&vD, size);
kernelEvaluaFuncion<<<10, 1000>>>(vD, XMIN, XMAX, n);
hipMemcpy(v, vD, size, hipMemcpyDeviceToHost);
hipFree(vD);
}
void llenaPolinomioEnHost(double *v, int n) {
int i;
double x, dx;
dx = (XMAX-XMIN)/(double)(N-1);
x = XMIN;
for (i=0; i<N; i++) {
v[i] = funcion(x);
x+=dx;
}
}
int main() {
int i;
double x, dx;
dx = (XMAX-XMIN)/(double)(N-1);
llenaPolinomioEnHost(vh, N);
llenaPolinomioEnDevice(vd, N);
x = XMIN;
for (i=0; i<N; i++) {
printf("%4d %4.2lf %6.12lf %6.12lf\n", i, x, vh[i], vd[i]);
x+=dx;
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
// sin(x*x)*cos(x)*x - x*x
#define XMIN 0.0
#define XMAX 10.0
#define N 10000
double vh[N], vd[N];
__device__ __host__ double funcion(double x) {
return sin(x*x)*cos(x)*x - x*x;
}
__global__ void kernelEvaluaFuncion(double *v, double xmin, double xmax, int n){
int i=threadIdx.x + blockIdx.x*blockDim.x;
double dx= (xmax-xmin)/(double)(n-1);
double x = xmin + i*dx;
v[i] = funcion(x);
}
void llenaPolinomioEnDevice(double *v, int n) {
double *vD;
int size = n*sizeof(double);
hipMalloc(&vD, size);
kernelEvaluaFuncion<<<10, 1000>>>(vD, XMIN, XMAX, n);
hipMemcpy(v, vD, size, hipMemcpyDeviceToHost);
hipFree(vD);
}
void llenaPolinomioEnHost(double *v, int n) {
int i;
double x, dx;
dx = (XMAX-XMIN)/(double)(N-1);
x = XMIN;
for (i=0; i<N; i++) {
v[i] = funcion(x);
x+=dx;
}
}
int main() {
int i;
double x, dx;
dx = (XMAX-XMIN)/(double)(N-1);
llenaPolinomioEnHost(vh, N);
llenaPolinomioEnDevice(vd, N);
x = XMIN;
for (i=0; i<N; i++) {
printf("%4d %4.2lf %6.12lf %6.12lf\n", i, x, vh[i], vd[i]);
x+=dx;
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19kernelEvaluaFuncionPdddi
.globl _Z19kernelEvaluaFuncionPdddi
.p2align 8
.type _Z19kernelEvaluaFuncionPdddi,@function
_Z19kernelEvaluaFuncionPdddi:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b32 s3, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, -1
v_add_f64 v[3:4], s[6:7], -s[4:5]
v_cvt_f64_i32_e32 v[5:6], s2
s_and_b32 s2, s3, 0xffff
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[1:2], null, v[5:6], v[5:6], v[3:4]
v_div_scale_f64 v[11:12], vcc_lo, v[3:4], v[5:6], v[3:4]
v_rcp_f64_e32 v[7:8], v[1:2]
s_waitcnt_depctr 0xfff
v_fma_f64 v[9:10], -v[1:2], v[7:8], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
v_fma_f64 v[9:10], -v[1:2], v[7:8], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
v_mul_f64 v[9:10], v[11:12], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[1:2], -v[1:2], v[9:10], v[11:12]
v_div_fmas_f64 v[7:8], v[1:2], v[7:8], v[9:10]
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f64 v[2:3], v[7:8], v[5:6], v[3:4]
v_cvt_f64_i32_e32 v[4:5], v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[2:3], v[4:5], s[4:5]
v_mul_f64 v[4:5], v[2:3], v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ngt_f64_e64 0x41d00000, |v[4:5]|
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_2
v_ldexp_f64 v[6:7], |v[4:5]|, 0xffffff80
v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[4:5]|
v_trig_preop_f64 v[8:9], |v[4:5]|, 0
v_and_b32_e32 v0, 0x7fffffff, v5
v_trig_preop_f64 v[10:11], |v[4:5]|, 1
v_trig_preop_f64 v[20:21], |v[4:5]|, 2
v_mov_b32_e32 v28, 0
s_mov_b32 s5, 0x3ff921fb
s_mov_b32 s4, 0x54442d18
s_mov_b32 s7, 0x3c91a626
s_mov_b32 s6, 0x33145c07
v_cndmask_b32_e32 v7, v0, v7, vcc_lo
v_cndmask_b32_e32 v6, v4, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f64 v[12:13], v[8:9], v[6:7]
v_mul_f64 v[14:15], v[10:11], v[6:7]
v_fma_f64 v[8:9], v[8:9], v[6:7], -v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[10:11], v[6:7], -v[14:15]
v_add_f64 v[16:17], v[14:15], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[18:19], v[16:17], -v[14:15]
v_add_f64 v[24:25], v[12:13], v[16:17]
v_add_f64 v[22:23], v[16:17], -v[18:19]
v_add_f64 v[8:9], v[8:9], -v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_ldexp_f64 v[18:19], v[24:25], -2
v_add_f64 v[12:13], v[24:25], -v[12:13]
v_add_f64 v[14:15], v[14:15], -v[22:23]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[18:19]|
v_add_f64 v[12:13], v[16:17], -v[12:13]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[8:9], v[8:9], v[14:15]
v_fract_f64_e32 v[14:15], v[18:19]
v_cndmask_b32_e32 v14, 0, v14, vcc_lo
v_mul_f64 v[26:27], v[20:21], v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v15, 0, v15, vcc_lo
v_ldexp_f64 v[14:15], v[14:15], 2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[22:23], v[26:27], v[10:11]
v_fma_f64 v[6:7], v[20:21], v[6:7], -v[26:27]
v_add_f64 v[16:17], v[22:23], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[18:19], v[12:13], v[16:17]
v_add_f64 v[24:25], v[18:19], v[14:15]
v_add_f64 v[12:13], v[18:19], -v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_gt_f64_e32 vcc_lo, 0, v[24:25]
v_add_f64 v[24:25], v[22:23], -v[26:27]
v_add_f64 v[12:13], v[16:17], -v[12:13]
v_cndmask_b32_e64 v29, 0, 0x40100000, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[33:34], v[22:23], -v[24:25]
v_add_f64 v[10:11], v[10:11], -v[24:25]
v_add_f64 v[14:15], v[14:15], v[28:29]
v_add_f64 v[29:30], v[16:17], -v[22:23]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[24:25], v[26:27], -v[33:34]
v_add_f64 v[31:32], v[18:19], v[14:15]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[35:36], v[16:17], -v[29:30]
v_add_f64 v[8:9], v[8:9], -v[29:30]
v_add_f64 v[10:11], v[10:11], v[24:25]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_i32_f64_e32 v0, v[31:32]
v_add_f64 v[22:23], v[22:23], -v[35:36]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f64_i32_e32 v[29:30], v0
v_add_f64 v[8:9], v[8:9], v[22:23]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[14:15], v[14:15], -v[29:30]
v_add_f64 v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[18:19], v[14:15]
v_add_f64 v[6:7], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[8:9], v[10:11], -v[14:15]
v_cmp_le_f64_e32 vcc_lo, 0.5, v[10:11]
v_add_f64 v[6:7], v[12:13], v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_f64 v[8:9], v[18:19], -v[8:9]
v_cndmask_b32_e64 v29, 0, 0x3ff00000, vcc_lo
v_add_co_ci_u32_e64 v0, s2, 0, v0, vcc_lo
v_add_f64 v[6:7], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[8:9], v[10:11], -v[28:29]
v_add_f64 v[10:11], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f64 v[12:13], v[10:11], s[4:5]
v_add_f64 v[8:9], v[10:11], -v[8:9]
v_fma_f64 v[14:15], v[10:11], s[4:5], -v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[6:7], -v[8:9]
v_fma_f64 v[8:9], v[10:11], s[6:7], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[6:7], s[4:5], v[8:9]
v_add_f64 v[6:7], v[12:13], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[10:11], v[6:7], -v[12:13]
v_add_f64 v[8:9], v[8:9], -v[10:11]
.LBB0_2:
s_and_not1_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_4
s_mov_b32 s5, 0x3fe45f30
s_mov_b32 s4, 0x6dc9c883
s_mov_b32 s7, 0xbc91a626
v_mul_f64 v[6:7], |v[4:5]|, s[4:5]
s_mov_b32 s5, 0xbff921fb
s_mov_b32 s4, 0x54442d18
s_mov_b32 s6, 0x33145c00
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[10:11], v[6:7]
v_fma_f64 v[6:7], v[10:11], s[4:5], |v[4:5]|
v_mul_f64 v[8:9], v[10:11], s[6:7]
s_mov_b32 s5, 0xb97b839a
s_mov_b32 s4, 0x252049c0
v_cvt_i32_f64_e32 v0, v[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[14:15], v[10:11], s[6:7], v[6:7]
v_add_f64 v[12:13], v[6:7], v[8:9]
s_mov_b32 s7, 0x3c91a626
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[6:7], v[6:7], -v[12:13]
v_add_f64 v[12:13], v[12:13], -v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[6:7], v[8:9]
v_fma_f64 v[8:9], v[10:11], s[6:7], v[8:9]
v_add_f64 v[6:7], v[12:13], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[6:7], -v[8:9]
v_fma_f64 v[8:9], v[10:11], s[4:5], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[14:15], v[8:9]
v_add_f64 v[12:13], v[6:7], -v[14:15]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[8:9], v[8:9], -v[12:13]
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
v_cmpx_ngt_f64_e64 0x41d00000, |v[2:3]|
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_6
v_ldexp_f64 v[10:11], |v[2:3]|, 0xffffff80
v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[2:3]|
v_trig_preop_f64 v[12:13], |v[2:3]|, 0
v_and_b32_e32 v14, 0x7fffffff, v3
v_trig_preop_f64 v[24:25], |v[2:3]|, 2
v_mov_b32_e32 v32, 0
s_mov_b32 s5, 0x3ff921fb
s_mov_b32 s4, 0x54442d18
s_mov_b32 s7, 0x3c91a626
s_mov_b32 s6, 0x33145c07
v_cndmask_b32_e32 v11, v14, v11, vcc_lo
v_cndmask_b32_e32 v10, v2, v10, vcc_lo
v_trig_preop_f64 v[14:15], |v[2:3]|, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[16:17], v[12:13], v[10:11]
v_mul_f64 v[18:19], v[14:15], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[12:13], v[12:13], v[10:11], -v[16:17]
v_fma_f64 v[14:15], v[14:15], v[10:11], -v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[20:21], v[18:19], v[12:13]
v_add_f64 v[22:23], v[20:21], -v[18:19]
v_add_f64 v[28:29], v[16:17], v[20:21]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[26:27], v[20:21], -v[22:23]
v_add_f64 v[12:13], v[12:13], -v[22:23]
v_ldexp_f64 v[22:23], v[28:29], -2
v_add_f64 v[16:17], v[28:29], -v[16:17]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[18:19], v[18:19], -v[26:27]
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[22:23]|
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[16:17], v[20:21], -v[16:17]
v_add_f64 v[12:13], v[12:13], v[18:19]
v_fract_f64_e32 v[18:19], v[22:23]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v19, 0, v19 :: v_dual_cndmask_b32 v18, 0, v18
v_mul_f64 v[30:31], v[24:25], v[10:11]
v_ldexp_f64 v[18:19], v[18:19], 2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[26:27], v[30:31], v[14:15]
v_fma_f64 v[10:11], v[24:25], v[10:11], -v[30:31]
v_add_f64 v[20:21], v[26:27], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[22:23], v[16:17], v[20:21]
v_add_f64 v[28:29], v[22:23], v[18:19]
v_add_f64 v[16:17], v[22:23], -v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_gt_f64_e32 vcc_lo, 0, v[28:29]
v_add_f64 v[28:29], v[26:27], -v[30:31]
v_cndmask_b32_e64 v33, 0, 0x40100000, vcc_lo
v_add_f64 v[37:38], v[26:27], -v[28:29]
v_add_f64 v[14:15], v[14:15], -v[28:29]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[18:19], v[18:19], v[32:33]
v_add_f64 v[33:34], v[20:21], -v[26:27]
v_add_f64 v[28:29], v[30:31], -v[37:38]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[35:36], v[22:23], v[18:19]
v_add_f64 v[39:40], v[20:21], -v[33:34]
v_add_f64 v[12:13], v[12:13], -v[33:34]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[14:15], v[14:15], v[28:29]
v_cvt_i32_f64_e32 v35, v[35:36]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[26:27], v[26:27], -v[39:40]
v_cvt_f64_i32_e32 v[33:34], v35
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[12:13], v[12:13], v[26:27]
v_add_f64 v[18:19], v[18:19], -v[33:34]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[12:13], v[14:15], v[12:13]
v_add_f64 v[14:15], v[20:21], -v[16:17]
v_add_f64 v[24:25], v[22:23], v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[10:11], v[12:13]
v_add_f64 v[12:13], v[24:25], -v[18:19]
v_cmp_le_f64_e32 vcc_lo, 0.5, v[24:25]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[10:11], v[14:15], v[10:11]
v_add_f64 v[12:13], v[22:23], -v[12:13]
v_cndmask_b32_e64 v33, 0, 0x3ff00000, vcc_lo
v_add_co_ci_u32_e64 v14, s2, 0, v35, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[10:11], v[10:11], v[12:13]
v_add_f64 v[12:13], v[24:25], -v[32:33]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[15:16], v[12:13], v[10:11]
v_mul_f64 v[17:18], v[15:16], s[4:5]
v_add_f64 v[12:13], v[15:16], -v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[19:20], v[15:16], s[4:5], -v[17:18]
v_add_f64 v[10:11], v[10:11], -v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[15:16], s[6:7], v[19:20]
v_fma_f64 v[12:13], v[10:11], s[4:5], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[10:11], v[17:18], v[12:13]
v_add_f64 v[15:16], v[10:11], -v[17:18]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[12:13], v[12:13], -v[15:16]
.LBB0_6:
s_and_not1_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_8
s_mov_b32 s5, 0x3fe45f30
s_mov_b32 s4, 0x6dc9c883
s_mov_b32 s7, 0xbc91a626
v_mul_f64 v[10:11], |v[2:3]|, s[4:5]
s_mov_b32 s5, 0xbff921fb
s_mov_b32 s4, 0x54442d18
s_mov_b32 s6, 0x33145c00
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[14:15], v[10:11]
v_fma_f64 v[10:11], v[14:15], s[4:5], |v[2:3]|
v_mul_f64 v[12:13], v[14:15], s[6:7]
s_mov_b32 s5, 0xb97b839a
s_mov_b32 s4, 0x252049c0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[18:19], v[14:15], s[6:7], v[10:11]
v_add_f64 v[16:17], v[10:11], v[12:13]
s_mov_b32 s7, 0x3c91a626
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[10:11], v[10:11], -v[16:17]
v_add_f64 v[16:17], v[16:17], -v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[10:11], v[12:13]
v_fma_f64 v[12:13], v[14:15], s[6:7], v[12:13]
v_add_f64 v[10:11], v[16:17], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[10:11], v[10:11], -v[12:13]
v_fma_f64 v[12:13], v[14:15], s[4:5], v[10:11]
v_cvt_i32_f64_e32 v14, v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[10:11], v[18:19], v[12:13]
v_add_f64 v[16:17], v[10:11], -v[18:19]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[12:13], v[12:13], -v[16:17]
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s2
v_mul_f64 v[15:16], v[6:7], v[6:7]
v_mul_f64 v[17:18], v[10:11], v[10:11]
s_mov_b32 s3, 0xbe5ae600
s_mov_b32 s2, 0xb42fdfa7
s_mov_b32 s5, 0x3de5e0b2
s_mov_b32 s4, 0xf9a43bb8
s_mov_b32 s7, 0xbda907db
s_mov_b32 s6, 0x46cc5e42
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f64 v[35:36], v[8:9], 0.5
v_mul_f64 v[37:38], v[12:13], 0.5
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[19:20], v[15:16], s[4:5], s[2:3]
v_fma_f64 v[21:22], v[17:18], s[4:5], s[2:3]
s_mov_b32 s3, 0x3ec71de3
s_mov_b32 s5, 0x3e21eeb6
s_mov_b32 s4, 0x9037ab78
s_mov_b32 s2, 0x796cde01
v_fma_f64 v[23:24], v[15:16], s[6:7], s[4:5]
v_mul_f64 v[25:26], v[15:16], 0.5
v_fma_f64 v[27:28], v[17:18], s[6:7], s[4:5]
v_mul_f64 v[29:30], v[17:18], 0.5
s_mov_b32 s5, 0xbe927e4f
s_mov_b32 s4, 0xa17f65f6
v_mul_f64 v[39:40], v[6:7], -v[15:16]
v_mul_f64 v[41:42], v[10:11], -v[17:18]
v_fma_f64 v[19:20], v[15:16], v[19:20], s[2:3]
v_fma_f64 v[21:22], v[17:18], v[21:22], s[2:3]
s_mov_b32 s3, 0xbf2a01a0
s_mov_b32 s2, 0x19e83e5c
v_fma_f64 v[23:24], v[15:16], v[23:24], s[4:5]
v_add_f64 v[31:32], -v[25:26], 1.0
v_fma_f64 v[27:28], v[17:18], v[27:28], s[4:5]
v_add_f64 v[33:34], -v[29:30], 1.0
s_mov_b32 s5, 0x3efa01a0
s_mov_b32 s4, 0x19f4ec90
v_fma_f64 v[19:20], v[15:16], v[19:20], s[2:3]
v_fma_f64 v[21:22], v[17:18], v[21:22], s[2:3]
s_mov_b32 s3, 0x3f811111
s_mov_b32 s2, 0x11110bb3
v_fma_f64 v[23:24], v[15:16], v[23:24], s[4:5]
v_add_f64 v[43:44], -v[31:32], 1.0
v_fma_f64 v[27:28], v[17:18], v[27:28], s[4:5]
v_add_f64 v[45:46], -v[33:34], 1.0
s_mov_b32 s5, 0x3fa55555
v_fma_f64 v[19:20], v[15:16], v[19:20], s[2:3]
v_fma_f64 v[21:22], v[17:18], v[21:22], s[2:3]
s_mov_b32 s3, 0xbf56c16c
s_mov_b32 s2, 0x16c16967
s_delay_alu instid0(SALU_CYCLE_1)
v_fma_f64 v[23:24], v[15:16], v[23:24], s[2:3]
v_add_f64 v[25:26], v[43:44], -v[25:26]
v_fma_f64 v[27:28], v[17:18], v[27:28], s[2:3]
v_add_f64 v[29:30], v[45:46], -v[29:30]
s_mov_b32 s2, 0x55555555
s_mov_b32 s3, 0xbfc55555
s_mov_b32 s4, s2
v_fma_f64 v[19:20], v[39:40], v[19:20], v[35:36]
v_fma_f64 v[21:22], v[41:42], v[21:22], v[37:38]
v_mul_f64 v[35:36], v[15:16], v[15:16]
v_mul_f64 v[37:38], v[17:18], v[17:18]
v_fma_f64 v[23:24], v[15:16], v[23:24], s[4:5]
v_fma_f64 v[25:26], v[6:7], -v[8:9], v[25:26]
v_fma_f64 v[27:28], v[17:18], v[27:28], s[4:5]
v_cmp_class_f64_e64 s4, v[2:3], 0x1f8
v_fma_f64 v[8:9], v[15:16], v[19:20], -v[8:9]
v_fma_f64 v[15:16], v[10:11], -v[12:13], v[29:30]
v_fma_f64 v[12:13], v[17:18], v[21:22], -v[12:13]
v_fma_f64 v[17:18], v[35:36], v[23:24], v[25:26]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[8:9], v[39:40], s[2:3], v[8:9]
v_fma_f64 v[15:16], v[37:38], v[27:28], v[15:16]
s_delay_alu instid0(VALU_DEP_4)
v_fma_f64 v[12:13], v[41:42], s[2:3], v[12:13]
v_cmp_class_f64_e64 s3, v[4:5], 0x1f8
v_add_f64 v[17:18], v[31:32], v[17:18]
v_add_f64 v[6:7], v[6:7], -v[8:9]
v_add_f64 v[8:9], v[33:34], v[15:16]
v_add_f64 v[10:11], v[10:11], -v[12:13]
v_and_b32_e32 v13, 1, v14
v_and_b32_e32 v12, 1, v0
v_lshlrev_b32_e32 v0, 30, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e64 s2, 0, v13
v_cmp_eq_u32_e32 vcc_lo, 0, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v5
v_dual_cndmask_b32 v7, v18, v7 :: v_dual_and_b32 v0, 0x80000000, v0
v_cndmask_b32_e32 v6, v17, v6, vcc_lo
v_cndmask_b32_e64 v8, v10, v8, s2
v_lshlrev_b32_e32 v10, 30, v14
v_xor_b32_e32 v11, 0x80000000, v11
v_xor_b32_e32 v0, v7, v0
v_cndmask_b32_e64 v6, 0, v6, s3
v_cndmask_b32_e64 v8, 0, v8, s4
v_and_b32_e32 v10, 0x80000000, v10
v_cndmask_b32_e64 v9, v11, v9, s2
v_cndmask_b32_e64 v7, 0x7ff80000, v0, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v9, v9, v10
v_cndmask_b32_e64 v9, 0x7ff80000, v9, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[6:7], v[6:7], v[8:9]
v_fma_f64 v[3:4], v[2:3], v[6:7], -v[4:5]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19kernelEvaluaFuncionPdddi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 47
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19kernelEvaluaFuncionPdddi, .Lfunc_end0-_Z19kernelEvaluaFuncionPdddi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19kernelEvaluaFuncionPdddi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19kernelEvaluaFuncionPdddi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 47
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
// sin(x*x)*cos(x)*x - x*x
#define XMIN 0.0
#define XMAX 10.0
#define N 10000
double vh[N], vd[N];
__device__ __host__ double funcion(double x) {
return sin(x*x)*cos(x)*x - x*x;
}
__global__ void kernelEvaluaFuncion(double *v, double xmin, double xmax, int n){
int i=threadIdx.x + blockIdx.x*blockDim.x;
double dx= (xmax-xmin)/(double)(n-1);
double x = xmin + i*dx;
v[i] = funcion(x);
}
void llenaPolinomioEnDevice(double *v, int n) {
double *vD;
int size = n*sizeof(double);
hipMalloc(&vD, size);
kernelEvaluaFuncion<<<10, 1000>>>(vD, XMIN, XMAX, n);
hipMemcpy(v, vD, size, hipMemcpyDeviceToHost);
hipFree(vD);
}
void llenaPolinomioEnHost(double *v, int n) {
int i;
double x, dx;
dx = (XMAX-XMIN)/(double)(N-1);
x = XMIN;
for (i=0; i<N; i++) {
v[i] = funcion(x);
x+=dx;
}
}
int main() {
int i;
double x, dx;
dx = (XMAX-XMIN)/(double)(N-1);
llenaPolinomioEnHost(vh, N);
llenaPolinomioEnDevice(vd, N);
x = XMIN;
for (i=0; i<N; i++) {
printf("%4d %4.2lf %6.12lf %6.12lf\n", i, x, vh[i], vd[i]);
x+=dx;
}
}
|
.text
.file "polinomio.hip"
.globl _Z7funciond # -- Begin function _Z7funciond
.p2align 4, 0x90
.type _Z7funciond,@function
_Z7funciond: # @_Z7funciond
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movsd %xmm0, (%rsp) # 8-byte Spill
mulsd %xmm0, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
callq sin
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
mulsd 8(%rsp), %xmm0 # 8-byte Folded Reload
mulsd (%rsp), %xmm0 # 8-byte Folded Reload
subsd 16(%rsp), %xmm0 # 8-byte Folded Reload
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z7funciond, .Lfunc_end0-_Z7funciond
.cfi_endproc
# -- End function
.globl _Z34__device_stub__kernelEvaluaFuncionPdddi # -- Begin function _Z34__device_stub__kernelEvaluaFuncionPdddi
.p2align 4, 0x90
.type _Z34__device_stub__kernelEvaluaFuncionPdddi,@function
_Z34__device_stub__kernelEvaluaFuncionPdddi: # @_Z34__device_stub__kernelEvaluaFuncionPdddi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movsd %xmm0, 64(%rsp)
movsd %xmm1, 56(%rsp)
movl %esi, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19kernelEvaluaFuncionPdddi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z34__device_stub__kernelEvaluaFuncionPdddi, .Lfunc_end1-_Z34__device_stub__kernelEvaluaFuncionPdddi
.cfi_endproc
# -- End function
.globl _Z22llenaPolinomioEnDevicePdi # -- Begin function _Z22llenaPolinomioEnDevicePdi
.p2align 4, 0x90
.type _Z22llenaPolinomioEnDevicePdi,@function
_Z22llenaPolinomioEnDevicePdi: # @_Z22llenaPolinomioEnDevicePdi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %r15d
movq %rdi, %rbx
leal (,%r15,8), %eax
movslq %eax, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movabsq $4294967306, %rdi # imm = 0x10000000A
leaq 990(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq $0, 80(%rsp)
movabsq $4621819117588971520, %rax # imm = 0x4024000000000000
movq %rax, 72(%rsp)
movl %r15d, 20(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19kernelEvaluaFuncionPdddi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z22llenaPolinomioEnDevicePdi, .Lfunc_end2-_Z22llenaPolinomioEnDevicePdi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z20llenaPolinomioEnHostPdi
.LCPI3_0:
.quad 0x3f5062b9357bd6ef # double 0.0010001000100010001
.text
.globl _Z20llenaPolinomioEnHostPdi
.p2align 4, 0x90
.type _Z20llenaPolinomioEnHostPdi,@function
_Z20llenaPolinomioEnHostPdi: # @_Z20llenaPolinomioEnHostPdi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
xorpd %xmm0, %xmm0
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movsd %xmm0, (%rsp) # 8-byte Spill
mulsd %xmm0, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
callq sin
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
mulsd 8(%rsp), %xmm0 # 8-byte Folded Reload
mulsd (%rsp), %xmm0 # 8-byte Folded Reload
subsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%rbx,%r14,8)
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd .LCPI3_0(%rip), %xmm0
incq %r14
cmpq $10000, %r14 # imm = 0x2710
jne .LBB3_1
# %bb.2:
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z20llenaPolinomioEnHostPdi, .Lfunc_end3-_Z20llenaPolinomioEnHostPdi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x3f5062b9357bd6ef # double 0.0010001000100010001
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
xorpd %xmm0, %xmm0
movq $-80000, %rbx # imm = 0xFFFEC780
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
movsd %xmm0, 8(%rsp) # 8-byte Spill
mulsd %xmm0, %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
callq sin
movsd %xmm0, 16(%rsp) # 8-byte Spill
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
mulsd 16(%rsp), %xmm0 # 8-byte Folded Reload
mulsd 8(%rsp), %xmm0 # 8-byte Folded Reload
subsd 24(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, vh+80000(%rbx)
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd .LCPI4_0(%rip), %xmm0
addq $8, %rbx
jne .LBB4_1
# %bb.2: # %_Z20llenaPolinomioEnHostPdi.exit
movl $vd, %edi
movl $10000, %esi # imm = 0x2710
callq _Z22llenaPolinomioEnDevicePdi
xorpd %xmm0, %xmm0
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_3: # =>This Inner Loop Header: Depth=1
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsd vh(,%rbx,8), %xmm1 # xmm1 = mem[0],zero
movsd vd(,%rbx,8), %xmm2 # xmm2 = mem[0],zero
movl $.L.str, %edi
movl %ebx, %esi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $3, %al
callq printf
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd .LCPI4_0(%rip), %xmm0
incq %rbx
cmpq $10000, %rbx # imm = 0x2710
jne .LBB4_3
# %bb.4:
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19kernelEvaluaFuncionPdddi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type vh,@object # @vh
.bss
.globl vh
.p2align 4, 0x0
vh:
.zero 80000
.size vh, 80000
.type vd,@object # @vd
.globl vd
.p2align 4, 0x0
vd:
.zero 80000
.size vd, 80000
.type _Z19kernelEvaluaFuncionPdddi,@object # @_Z19kernelEvaluaFuncionPdddi
.section .rodata,"a",@progbits
.globl _Z19kernelEvaluaFuncionPdddi
.p2align 3, 0x0
_Z19kernelEvaluaFuncionPdddi:
.quad _Z34__device_stub__kernelEvaluaFuncionPdddi
.size _Z19kernelEvaluaFuncionPdddi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%4d %4.2lf %6.12lf %6.12lf\n"
.size .L.str, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19kernelEvaluaFuncionPdddi"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__kernelEvaluaFuncionPdddi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym vd
.addrsig_sym _Z19kernelEvaluaFuncionPdddi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00037217_00000000-6_polinomio.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7funciond
.type _Z7funciond, @function
_Z7funciond:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movapd %xmm0, %xmm1
movsd %xmm0, 8(%rsp)
mulsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp)
movapd %xmm1, %xmm0
call sin@PLT
movsd %xmm0, 24(%rsp)
movsd 8(%rsp), %xmm0
call cos@PLT
mulsd 24(%rsp), %xmm0
mulsd 8(%rsp), %xmm0
subsd 16(%rsp), %xmm0
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z7funciond, .-_Z7funciond
.globl _Z20llenaPolinomioEnHostPdi
.type _Z20llenaPolinomioEnHostPdi, @function
_Z20llenaPolinomioEnHostPdi:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
leaq 80000(%rdi), %rbp
movl $0x000000000, %r12d
.L6:
movq %r12, %xmm0
call _Z7funciond
movsd %xmm0, (%rbx)
movq %r12, %xmm1
addsd .LC1(%rip), %xmm1
movq %xmm1, %r12
addq $8, %rbx
cmpq %rbp, %rbx
jne .L6
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z20llenaPolinomioEnHostPdi, .-_Z20llenaPolinomioEnHostPdi
.globl _Z42__device_stub__Z19kernelEvaluaFuncionPdddiPdddi
.type _Z42__device_stub__Z19kernelEvaluaFuncionPdddiPdddi, @function
_Z42__device_stub__Z19kernelEvaluaFuncionPdddiPdddi:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19kernelEvaluaFuncionPdddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z42__device_stub__Z19kernelEvaluaFuncionPdddiPdddi, .-_Z42__device_stub__Z19kernelEvaluaFuncionPdddiPdddi
.globl _Z19kernelEvaluaFuncionPdddi
.type _Z19kernelEvaluaFuncionPdddi, @function
_Z19kernelEvaluaFuncionPdddi:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z19kernelEvaluaFuncionPdddiPdddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z19kernelEvaluaFuncionPdddi, .-_Z19kernelEvaluaFuncionPdddi
.globl _Z22llenaPolinomioEnDevicePdi
.type _Z22llenaPolinomioEnDevicePdi, @function
_Z22llenaPolinomioEnDevicePdi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leal 0(,%rsi,8), %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1000, 28(%rsp)
movl $1, 32(%rsp)
movl $10, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L18:
movl $2, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl %ebp, %esi
movsd .LC2(%rip), %xmm1
pxor %xmm0, %xmm0
movq 8(%rsp), %rdi
call _Z42__device_stub__Z19kernelEvaluaFuncionPdddiPdddi
jmp .L18
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z22llenaPolinomioEnDevicePdi, .-_Z22llenaPolinomioEnDevicePdi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "%4d %4.2lf %6.12lf %6.12lf\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl $10000, %esi
leaq vh(%rip), %rdi
call _Z20llenaPolinomioEnHostPdi
movl $10000, %esi
leaq vd(%rip), %rdi
call _Z22llenaPolinomioEnDevicePdi
movl $0, %ebx
movl $0x000000000, %r14d
leaq vd(%rip), %r13
leaq vh(%rip), %r12
leaq .LC3(%rip), %rbp
.L24:
movsd 0(%r13,%rbx,8), %xmm2
movsd (%r12,%rbx,8), %xmm1
movq %r14, %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
movq %r14, %xmm3
addsd .LC1(%rip), %xmm3
movq %xmm3, %r14
addq $1, %rbx
cmpq $10000, %rbx
jne .L24
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "_Z19kernelEvaluaFuncionPdddi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z19kernelEvaluaFuncionPdddi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl vd
.bss
.align 32
.type vd, @object
.size vd, 80000
vd:
.zero 80000
.globl vh
.align 32
.type vh, @object
.size vh, 80000
vh:
.zero 80000
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 897308399
.long 1062232761
.align 8
.LC2:
.long 0
.long 1076101120
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "polinomio.hip"
.globl _Z7funciond # -- Begin function _Z7funciond
.p2align 4, 0x90
.type _Z7funciond,@function
_Z7funciond: # @_Z7funciond
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movsd %xmm0, (%rsp) # 8-byte Spill
mulsd %xmm0, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
callq sin
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
mulsd 8(%rsp), %xmm0 # 8-byte Folded Reload
mulsd (%rsp), %xmm0 # 8-byte Folded Reload
subsd 16(%rsp), %xmm0 # 8-byte Folded Reload
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z7funciond, .Lfunc_end0-_Z7funciond
.cfi_endproc
# -- End function
.globl _Z34__device_stub__kernelEvaluaFuncionPdddi # -- Begin function _Z34__device_stub__kernelEvaluaFuncionPdddi
.p2align 4, 0x90
.type _Z34__device_stub__kernelEvaluaFuncionPdddi,@function
_Z34__device_stub__kernelEvaluaFuncionPdddi: # @_Z34__device_stub__kernelEvaluaFuncionPdddi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movsd %xmm0, 64(%rsp)
movsd %xmm1, 56(%rsp)
movl %esi, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19kernelEvaluaFuncionPdddi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z34__device_stub__kernelEvaluaFuncionPdddi, .Lfunc_end1-_Z34__device_stub__kernelEvaluaFuncionPdddi
.cfi_endproc
# -- End function
.globl _Z22llenaPolinomioEnDevicePdi # -- Begin function _Z22llenaPolinomioEnDevicePdi
.p2align 4, 0x90
.type _Z22llenaPolinomioEnDevicePdi,@function
_Z22llenaPolinomioEnDevicePdi: # @_Z22llenaPolinomioEnDevicePdi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %r15d
movq %rdi, %rbx
leal (,%r15,8), %eax
movslq %eax, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movabsq $4294967306, %rdi # imm = 0x10000000A
leaq 990(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq $0, 80(%rsp)
movabsq $4621819117588971520, %rax # imm = 0x4024000000000000
movq %rax, 72(%rsp)
movl %r15d, 20(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19kernelEvaluaFuncionPdddi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z22llenaPolinomioEnDevicePdi, .Lfunc_end2-_Z22llenaPolinomioEnDevicePdi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z20llenaPolinomioEnHostPdi
.LCPI3_0:
.quad 0x3f5062b9357bd6ef # double 0.0010001000100010001
.text
.globl _Z20llenaPolinomioEnHostPdi
.p2align 4, 0x90
.type _Z20llenaPolinomioEnHostPdi,@function
_Z20llenaPolinomioEnHostPdi: # @_Z20llenaPolinomioEnHostPdi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
xorpd %xmm0, %xmm0
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movsd %xmm0, (%rsp) # 8-byte Spill
mulsd %xmm0, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
callq sin
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
mulsd 8(%rsp), %xmm0 # 8-byte Folded Reload
mulsd (%rsp), %xmm0 # 8-byte Folded Reload
subsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%rbx,%r14,8)
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd .LCPI3_0(%rip), %xmm0
incq %r14
cmpq $10000, %r14 # imm = 0x2710
jne .LBB3_1
# %bb.2:
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z20llenaPolinomioEnHostPdi, .Lfunc_end3-_Z20llenaPolinomioEnHostPdi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x3f5062b9357bd6ef # double 0.0010001000100010001
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
xorpd %xmm0, %xmm0
movq $-80000, %rbx # imm = 0xFFFEC780
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
movsd %xmm0, 8(%rsp) # 8-byte Spill
mulsd %xmm0, %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
callq sin
movsd %xmm0, 16(%rsp) # 8-byte Spill
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
mulsd 16(%rsp), %xmm0 # 8-byte Folded Reload
mulsd 8(%rsp), %xmm0 # 8-byte Folded Reload
subsd 24(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, vh+80000(%rbx)
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd .LCPI4_0(%rip), %xmm0
addq $8, %rbx
jne .LBB4_1
# %bb.2: # %_Z20llenaPolinomioEnHostPdi.exit
movl $vd, %edi
movl $10000, %esi # imm = 0x2710
callq _Z22llenaPolinomioEnDevicePdi
xorpd %xmm0, %xmm0
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_3: # =>This Inner Loop Header: Depth=1
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsd vh(,%rbx,8), %xmm1 # xmm1 = mem[0],zero
movsd vd(,%rbx,8), %xmm2 # xmm2 = mem[0],zero
movl $.L.str, %edi
movl %ebx, %esi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $3, %al
callq printf
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd .LCPI4_0(%rip), %xmm0
incq %rbx
cmpq $10000, %rbx # imm = 0x2710
jne .LBB4_3
# %bb.4:
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19kernelEvaluaFuncionPdddi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type vh,@object # @vh
.bss
.globl vh
.p2align 4, 0x0
vh:
.zero 80000
.size vh, 80000
.type vd,@object # @vd
.globl vd
.p2align 4, 0x0
vd:
.zero 80000
.size vd, 80000
.type _Z19kernelEvaluaFuncionPdddi,@object # @_Z19kernelEvaluaFuncionPdddi
.section .rodata,"a",@progbits
.globl _Z19kernelEvaluaFuncionPdddi
.p2align 3, 0x0
_Z19kernelEvaluaFuncionPdddi:
.quad _Z34__device_stub__kernelEvaluaFuncionPdddi
.size _Z19kernelEvaluaFuncionPdddi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%4d %4.2lf %6.12lf %6.12lf\n"
.size .L.str, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19kernelEvaluaFuncionPdddi"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__kernelEvaluaFuncionPdddi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym vd
.addrsig_sym _Z19kernelEvaluaFuncionPdddi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
static struct timeval ti;
bool IN(int x, int y, int w, int h) {
return (x) >= 0 && (y) >= 0 && (x) < (w) && (y) < (h);
}
int maxProf(unsigned char * arr, int matDim){
int max_value = 0;
for (int i = 0; i < matDim; ++i) {
if (arr[i] > max_value)
max_value = arr[i];
}
return max_value;
}
void displayMat(unsigned char * arr, char * name, int matDim){
printf("Matrice de %s \n \n", name);
for(int y = 0; y < matDim; ++y){
for(int x = 0; x < matDim; ++x){
printf("%d ", (int)arr[y * matDim + x]);
}
printf("\n");
}
printf("\n");
}
void initArraysDs(unsigned char * _tabDepth, int4 * _tabParents, int w, int h) {
int sw1 = w - 1, sw2 = sw1 >> 1;
int sh1 = h - 1, sh2 = sh1 >> 1;
int niveau = 1;
while(sw2){
for(int y = sh2; y < h; y += sh1){
for(int x = sw2; x < w; x += sw1){
if(_tabDepth[y * w + x]) continue;
_tabDepth[y * w + x] = niveau;
_tabParents[y * w + x].x = (y - sh2) * w + x - sw2;
_tabParents[y * w + x].y = (y - sh2) * w + x + sw2;
_tabParents[y * w + x].z = (y + sh2) * w + x + sw2;
_tabParents[y * w + x].w = (y + sh2) * w + x - sw2;
}
}
niveau++;
for(int y = 0; y < h; y += sh1){
for(int x = sw2; x < w; x += sw1){
int yp, xp;
if(_tabDepth[y * w + x]) continue;
yp = y - sh2; xp = x; // parent haut
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].x = yp * w + xp;
} else{
_tabParents[y * w + x].x = -1;
}
yp = y; xp = x + sw2; // parent droit
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].y = yp * w + xp;
} else{
_tabParents[y * w + x].y = -1;
}
yp = y + sh2; xp = x; // parent bas
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].z = yp * w + xp;
} else{
_tabParents[y * w + x].z = -1;
}
yp = y; xp = x - sw2; // parent gauche
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].w = yp * w + xp;
} else{
_tabParents[y * w + x].w = -1;
}
_tabDepth[y * w + x] = niveau;
}
}
for(int y = sh2; y < h; y += sh1){
for(int x = 0; x < w; x += sw1){
int yp, xp;
if(_tabDepth[y * w + x]) continue;
yp = y - sh2; xp = x; // parent haut
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].x = yp * w + xp;
} else{
_tabParents[y * w + x].x = -1;
}
yp = y; xp = x + sw2; // parent droit
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].y = yp * w + xp;
} else{
_tabParents[y * w + x].y = -1;
}
yp = y + sh2; xp = x; // parent bas
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].z = yp * w + xp;
} else{
_tabParents[y * w + x].z = -1;
}
yp = y; xp = x - sw2; // parent gauche
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].w = yp * w + xp;
} else{
_tabParents[y * w + x].w = -1;
}
_tabDepth[y * w + x] = niveau;
}
}
niveau ++;
sw1 = sw2;
sw2 >>= 1;
sh1 = sh2;
sh2 >>= 1;
}
}
void initArraysTe(unsigned char * _tabDepth, int4 * _tabParents, int x0, int y0, int stride, int sx, int sy, int p) {
int w_2 = sx >> 1, h_2 = sy >> 1, j;
int x[9] = { x0, x0 + sx, x0 + sx,
x0, x0 + w_2, x0 + sx, x0 + w_2,
x0, x0 + w_2 };
int y[9] = { y0,
y0, y0 + sy, y0 + sy,
y0, y0 + h_2, y0 + sy, y0 + h_2, y0 + h_2 };
for(int i = 0, i1 = 1; i < 4; ++i, i1 = (i1 + 1) % 4) {
if(_tabDepth[j = y[i + 4] * stride + x[i + 4]]) continue;
//Parents
_tabParents[j].x = y[i] * stride + x[i];
_tabParents[j].y = y[i1] * stride + x[i1];
_tabParents[j].z = -1;
_tabParents[j].w = -1;
//prof
_tabDepth[j] = p;
}
if(!_tabDepth[j = y[8] * stride + x[8]]) {
for(int i = 0; i < 4; ++i) {
//prof
_tabDepth[j] = p;
//Tab parent
if(i == 1){
_tabParents[j].x = y[i] * stride + x[i];
} else if(i == 2){
_tabParents[j].y = y[i] * stride + x[i];
} else if(i == 3) {
_tabParents[j].z = y[i] * stride + x[i];
} else {
_tabParents[j].w = y[i] * stride + x[i];
}
}
}
if(w_2 > 1) {
initArraysTe(_tabDepth, _tabParents, x[0], y[0], stride, w_2, h_2, ++p);
initArraysTe(_tabDepth, _tabParents, x[4], y[4], stride, w_2, h_2, p);
initArraysTe(_tabDepth, _tabParents, x[8], y[8], stride, w_2, h_2, p);
initArraysTe(_tabDepth, _tabParents, x[7], y[7], stride, w_2, h_2, p);
}
}
void triangleEdgeCPU(unsigned char * data, int x0, int y0, int stride, int sx, int sy, int p) {
int niveau = 1;
int w_2 = sx >> 1, h_2 = sy >> 1, j;
int x[9] = { x0, x0 + sx, x0 + sx,
x0, x0 + w_2, x0 + sx, x0 + w_2,
x0, x0 + w_2 };
int y[9] = { y0,
y0, y0 + sy, y0 + sy,
y0, y0 + h_2, y0 + sy, y0 + h_2, y0 + h_2 };
for(int i = 0, i1 = 1; i < 4; ++i, i1 = (i1 + 1) % 4) {
if(data[j = y[i + 4] * stride + x[i + 4]]) continue;
data[j] = ((int)data[y[i] * stride + x[i]] +
data[y[i1] * stride + x[i1]]) >> 1;
}
if(!data[j = y[8] * stride + x[8]]) {
int v = 0;
for(int i = 0; i < 4; ++i)
v += data[y[i] * stride + x[i]];
data[j] = v >> 2;
}
if(w_2 > 1) {
triangleEdgeCPU(data, x[0], y[0], stride, w_2, h_2, ++p);
triangleEdgeCPU(data, x[4], y[4], stride, w_2, h_2, p);
triangleEdgeCPU(data, x[8], y[8], stride, w_2, h_2, p);
triangleEdgeCPU(data, x[7], y[7], stride, w_2, h_2, p);
}
}
void diamontCPU(int w, int h, unsigned char * data) {
int sw1 = w - 1, sw2 = sw1 >> 1;
int sh1 = h - 1, sh2 = sh1 >> 1;
while(sw2){
for(int y = sh2; y < h; y += sh1){
for(int x = sw2; x < w; x += sw1){
if(data[y * w + x]) continue;
data[y * w + x] = (data[(y - sh2) * w + x - sw2] +
data[(y - sh2) * w + x + sw2] +
data[(y + sh2) * w + x + sw2] +
data[(y + sh2) * w + x - sw2]) >> 2;
}
}
for(int y = 0; y < h; y += sh1){
for(int x = sw2; x < w; x += sw1){
int yp, xp;
int nbp = 0, v = 0;
if(data[y * w + x]) continue;
yp = y - sh2; xp = x; // parent haut
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y; xp = x + sw2; // parent droit
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y + sh2; xp = x; // parent bas
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y; xp = x - sw2; // parent gauche
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
data[y * w + x] = v / nbp;
}
}
for(int y = sh2; y < h; y += sh1){
for(int x = 0; x < w; x += sw1){
int yp, xp;
int nbp = 0, v = 0;
if(data[y * w + x]) continue;
yp = y - sh2; xp = x; // parent haut
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y; xp = x + sw2; // parent droit
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y + sh2; xp = x; // parent bas
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y; xp = x - sw2; // parent gauche
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
data[y * w + x] = v / nbp;
}
}
sw1 = sw2;
sw2 >>= 1;
sh1 = sh2;
sh2 >>= 1;
}
}
__global__ void generateImg(unsigned char * data, unsigned char * img, unsigned char * tabDepth, int4 * _tabParents, int i, int tailleTab) {
int thx = blockIdx.x * blockDim.x + threadIdx.x;
int thy = blockIdx.y * blockDim.y + threadIdx.y;
int ThId = thy * tailleTab + thx;
int nbPar = 0;
if(data[ThId] == 0 && tabDepth[ThId] == i && i != 1) {
if(_tabParents[ThId].x != -1) nbPar ++;
if(_tabParents[ThId].y != -1) nbPar ++;
if(_tabParents[ThId].z != -1) nbPar ++;
if(_tabParents[ThId].w != -1) nbPar ++;
data[ThId] = (data[_tabParents[ThId].x] + data[_tabParents[ThId].y] + data[_tabParents[ThId].z] + data[_tabParents[ThId].w]) / nbPar;
img[ThId] = data[ThId];
}
}
void initTime(void) {
gettimeofday(&ti, (struct timezone*) 0);
}
double getTime(void) {
struct timeval t;
double diff;
gettimeofday(&t, (struct timezone*) 0);
diff = (t.tv_sec - ti.tv_sec) * 1000000
+ (t.tv_usec - ti.tv_usec);
return diff/1000.;
}
|
code for sm_80
Function : _Z11generateImgPhS_S_P4int4ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0040*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R9, R9, c[0x0][0x0], R0 ; /* 0x0000000009097a24 */
/* 0x001fe400078e0200 */
/*0070*/ IMAD R0, R2, c[0x0][0x4], R3 ; /* 0x0000010002007a24 */
/* 0x002fc800078e0203 */
/*0080*/ IMAD R9, R0, c[0x0][0x184], R9 ; /* 0x0000610000097a24 */
/* 0x000fca00078e0209 */
/*0090*/ SHF.R.S32.HI R0, RZ, 0x1f, R9 ; /* 0x0000001fff007819 */
/* 0x000fe40000011409 */
/*00a0*/ IADD3 R2, P0, R9, c[0x0][0x160], RZ ; /* 0x0000580009027a10 */
/* 0x000fc80007f1e0ff */
/*00b0*/ IADD3.X R3, R0, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000037a10 */
/* 0x000fca00007fe4ff */
/*00c0*/ LDG.E.U8 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1100 */
/*00d0*/ BSSY B0, 0x170 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*00e0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff067624 */
/* 0x000fe200078e00ff */
/*00f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0100*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x004fda0003f25270 */
/*0110*/ @P1 BRA 0x160 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R4, P0, R9, c[0x0][0x170], RZ ; /* 0x00005c0009047a10 */
/* 0x000fc80007f1e0ff */
/*0130*/ IADD3.X R5, R0, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0000057a10 */
/* 0x000fca00007fe4ff */
/*0140*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1100 */
/*0150*/ ISETP.EQ.AND P0, PT, R4, c[0x0][0x180], PT ; /* 0x0000600004007a0c */
/* 0x004fd00003f02270 */
/*0160*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.EQ.OR P0, PT, R6, 0x1, !P0 ; /* 0x000000010600780c */
/* 0x000fda0004702670 */
/*0180*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0190*/ LEA R4, P0, R9, c[0x0][0x178], 0x4 ; /* 0x00005e0009047a11 */
/* 0x000fc800078020ff */
/*01a0*/ LEA.HI.X R5, R9, c[0x0][0x17c], R0, 0x4, P0 ; /* 0x00005f0009057a11 */
/* 0x000fcc00000f2400 */
/*01b0*/ LDG.E.128 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1d00 */
/*01c0*/ IADD3 R10, P0, R4, c[0x0][0x160], RZ ; /* 0x00005800040a7a10 */
/* 0x004fe40007f1e0ff */
/*01d0*/ IADD3 R12, P1, R5.reuse, c[0x0][0x160], RZ ; /* 0x00005800050c7a10 */
/* 0x040fe40007f3e0ff */
/*01e0*/ IADD3 R14, P2, R6, c[0x0][0x160], RZ ; /* 0x00005800060e7a10 */
/* 0x000fe40007f5e0ff */
/*01f0*/ LEA.HI.X.SX32 R11, R4, c[0x0][0x164], 0x1, P0 ; /* 0x00005900040b7a11 */
/* 0x000fe400000f0eff */
/*0200*/ LEA.HI.X.SX32 R13, R5, c[0x0][0x164], 0x1, P1 ; /* 0x00005900050d7a11 */
/* 0x000fc400008f0eff */
/*0210*/ IADD3 R16, P0, R7.reuse, c[0x0][0x160], RZ ; /* 0x0000580007107a10 */
/* 0x040fe20007f1e0ff */
/*0220*/ LDG.E.U8 R8, [R10.64] ; /* 0x000000040a087981 */
/* 0x0000a2000c1e1100 */
/*0230*/ LEA.HI.X.SX32 R15, R6, c[0x0][0x164], 0x1, P2 ; /* 0x00005900060f7a11 */
/* 0x000fe400010f0eff */
/*0240*/ LEA.HI.X.SX32 R17, R7, c[0x0][0x164], 0x1, P0 ; /* 0x0000590007117a11 */
/* 0x000fe200000f0eff */
/*0250*/ LDG.E.U8 R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ea8000c1e1100 */
/*0260*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea8000c1e1100 */
/*0270*/ LDG.E.U8 R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee2000c1e1100 */
/*0280*/ ISETP.NE.AND P3, PT, R5, -0x1, PT ; /* 0xffffffff0500780c */
/* 0x000fe20003f65270 */
/*0290*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe200078e00ff */
/*02a0*/ ISETP.NE.AND P0, PT, R4, -0x1, PT ; /* 0xffffffff0400780c */
/* 0x000fc40003f05270 */
/*02b0*/ ISETP.NE.AND P1, PT, R6, -0x1, PT ; /* 0xffffffff0600780c */
/* 0x000fe40003f25270 */
/*02c0*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fe40004000000 */
/*02d0*/ ISETP.NE.AND P2, PT, R7, -0x1, PT ; /* 0xffffffff0700780c */
/* 0x000fca0003f45270 */
/*02e0*/ @P3 SEL R4, R5, 0x2, !P0 ; /* 0x0000000205043807 */
/* 0x000fe40004000000 */
/*02f0*/ SEL R5, RZ, 0x1, !P1 ; /* 0x00000001ff057807 */
/* 0x000fca0004800000 */
/*0300*/ IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104047824 */
/* 0x000fca00078e0205 */
/*0310*/ IADD3 R11, R4, 0x1, RZ ; /* 0x00000001040b7810 */
/* 0x001fe20007ffe0ff */
/*0320*/ @!P2 IMAD.MOV R11, RZ, RZ, R4 ; /* 0x000000ffff0ba224 */
/* 0x000fc800078e0204 */
/*0330*/ I2F.U32.RP R6, R11 ; /* 0x0000000b00067306 */
/* 0x000e300000209000 */
/*0340*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0350*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0360*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0370*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0380*/ IMAD.MOV R10, RZ, RZ, -R5 ; /* 0x000000ffff0a7224 */
/* 0x002fc800078e0a05 */
/*0390*/ IMAD R7, R10, R11, RZ ; /* 0x0000000b0a077224 */
/* 0x000fc800078e02ff */
/*03a0*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fe200078e0004 */
/*03b0*/ ISETP.NE.U32.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f45070 */
/*03c0*/ IADD3 R8, R14, R13, R8 ; /* 0x0000000d0e087210 */
/* 0x004fca0007ffe008 */
/*03d0*/ IMAD.IADD R8, R8, 0x1, R17 ; /* 0x0000000108087824 */
/* 0x008fc800078e0211 */
/*03e0*/ IMAD.HI.U32 R7, R5, R8, RZ ; /* 0x0000000805077227 */
/* 0x000fc800078e00ff */
/*03f0*/ IMAD.MOV R5, RZ, RZ, -R7 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a07 */
/*0400*/ IMAD R8, R5, R11, R8 ; /* 0x0000000b05087224 */
/* 0x000fca00078e0208 */
/*0410*/ ISETP.GE.U32.AND P0, PT, R8, R11, PT ; /* 0x0000000b0800720c */
/* 0x000fda0003f06070 */
/*0420*/ @P0 IMAD.IADD R8, R8, 0x1, -R11 ; /* 0x0000000108080824 */
/* 0x000fca00078e0a0b */
/*0430*/ ISETP.GE.U32.AND P1, PT, R8, R11, PT ; /* 0x0000000b0800720c */
/* 0x000fe40003f26070 */
/*0440*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fe40007ffe0ff */
/*0450*/ IADD3 R4, P0, R9, c[0x0][0x168], RZ ; /* 0x00005a0009047a10 */
/* 0x000fc80007f1e0ff */
/*0460*/ IADD3.X R5, R0, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0000057a10 */
/* 0x000fca00007fe4ff */
/*0470*/ @P1 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107071810 */
/* 0x000fe40007ffe0ff */
/*0480*/ @!P2 LOP3.LUT R7, RZ, R11, RZ, 0x33, !PT ; /* 0x0000000bff07a212 */
/* 0x000fca00078e33ff */
/*0490*/ STG.E.U8 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101104 */
/*04a0*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101104 */
/*04b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04c0*/ BRA 0x4c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
static struct timeval ti;
bool IN(int x, int y, int w, int h) {
return (x) >= 0 && (y) >= 0 && (x) < (w) && (y) < (h);
}
int maxProf(unsigned char * arr, int matDim){
int max_value = 0;
for (int i = 0; i < matDim; ++i) {
if (arr[i] > max_value)
max_value = arr[i];
}
return max_value;
}
void displayMat(unsigned char * arr, char * name, int matDim){
printf("Matrice de %s \n \n", name);
for(int y = 0; y < matDim; ++y){
for(int x = 0; x < matDim; ++x){
printf("%d ", (int)arr[y * matDim + x]);
}
printf("\n");
}
printf("\n");
}
void initArraysDs(unsigned char * _tabDepth, int4 * _tabParents, int w, int h) {
int sw1 = w - 1, sw2 = sw1 >> 1;
int sh1 = h - 1, sh2 = sh1 >> 1;
int niveau = 1;
while(sw2){
for(int y = sh2; y < h; y += sh1){
for(int x = sw2; x < w; x += sw1){
if(_tabDepth[y * w + x]) continue;
_tabDepth[y * w + x] = niveau;
_tabParents[y * w + x].x = (y - sh2) * w + x - sw2;
_tabParents[y * w + x].y = (y - sh2) * w + x + sw2;
_tabParents[y * w + x].z = (y + sh2) * w + x + sw2;
_tabParents[y * w + x].w = (y + sh2) * w + x - sw2;
}
}
niveau++;
for(int y = 0; y < h; y += sh1){
for(int x = sw2; x < w; x += sw1){
int yp, xp;
if(_tabDepth[y * w + x]) continue;
yp = y - sh2; xp = x; // parent haut
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].x = yp * w + xp;
} else{
_tabParents[y * w + x].x = -1;
}
yp = y; xp = x + sw2; // parent droit
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].y = yp * w + xp;
} else{
_tabParents[y * w + x].y = -1;
}
yp = y + sh2; xp = x; // parent bas
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].z = yp * w + xp;
} else{
_tabParents[y * w + x].z = -1;
}
yp = y; xp = x - sw2; // parent gauche
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].w = yp * w + xp;
} else{
_tabParents[y * w + x].w = -1;
}
_tabDepth[y * w + x] = niveau;
}
}
for(int y = sh2; y < h; y += sh1){
for(int x = 0; x < w; x += sw1){
int yp, xp;
if(_tabDepth[y * w + x]) continue;
yp = y - sh2; xp = x; // parent haut
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].x = yp * w + xp;
} else{
_tabParents[y * w + x].x = -1;
}
yp = y; xp = x + sw2; // parent droit
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].y = yp * w + xp;
} else{
_tabParents[y * w + x].y = -1;
}
yp = y + sh2; xp = x; // parent bas
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].z = yp * w + xp;
} else{
_tabParents[y * w + x].z = -1;
}
yp = y; xp = x - sw2; // parent gauche
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].w = yp * w + xp;
} else{
_tabParents[y * w + x].w = -1;
}
_tabDepth[y * w + x] = niveau;
}
}
niveau ++;
sw1 = sw2;
sw2 >>= 1;
sh1 = sh2;
sh2 >>= 1;
}
}
void initArraysTe(unsigned char * _tabDepth, int4 * _tabParents, int x0, int y0, int stride, int sx, int sy, int p) {
int w_2 = sx >> 1, h_2 = sy >> 1, j;
int x[9] = { x0, x0 + sx, x0 + sx,
x0, x0 + w_2, x0 + sx, x0 + w_2,
x0, x0 + w_2 };
int y[9] = { y0,
y0, y0 + sy, y0 + sy,
y0, y0 + h_2, y0 + sy, y0 + h_2, y0 + h_2 };
for(int i = 0, i1 = 1; i < 4; ++i, i1 = (i1 + 1) % 4) {
if(_tabDepth[j = y[i + 4] * stride + x[i + 4]]) continue;
//Parents
_tabParents[j].x = y[i] * stride + x[i];
_tabParents[j].y = y[i1] * stride + x[i1];
_tabParents[j].z = -1;
_tabParents[j].w = -1;
//prof
_tabDepth[j] = p;
}
if(!_tabDepth[j = y[8] * stride + x[8]]) {
for(int i = 0; i < 4; ++i) {
//prof
_tabDepth[j] = p;
//Tab parent
if(i == 1){
_tabParents[j].x = y[i] * stride + x[i];
} else if(i == 2){
_tabParents[j].y = y[i] * stride + x[i];
} else if(i == 3) {
_tabParents[j].z = y[i] * stride + x[i];
} else {
_tabParents[j].w = y[i] * stride + x[i];
}
}
}
if(w_2 > 1) {
initArraysTe(_tabDepth, _tabParents, x[0], y[0], stride, w_2, h_2, ++p);
initArraysTe(_tabDepth, _tabParents, x[4], y[4], stride, w_2, h_2, p);
initArraysTe(_tabDepth, _tabParents, x[8], y[8], stride, w_2, h_2, p);
initArraysTe(_tabDepth, _tabParents, x[7], y[7], stride, w_2, h_2, p);
}
}
void triangleEdgeCPU(unsigned char * data, int x0, int y0, int stride, int sx, int sy, int p) {
int niveau = 1;
int w_2 = sx >> 1, h_2 = sy >> 1, j;
int x[9] = { x0, x0 + sx, x0 + sx,
x0, x0 + w_2, x0 + sx, x0 + w_2,
x0, x0 + w_2 };
int y[9] = { y0,
y0, y0 + sy, y0 + sy,
y0, y0 + h_2, y0 + sy, y0 + h_2, y0 + h_2 };
for(int i = 0, i1 = 1; i < 4; ++i, i1 = (i1 + 1) % 4) {
if(data[j = y[i + 4] * stride + x[i + 4]]) continue;
data[j] = ((int)data[y[i] * stride + x[i]] +
data[y[i1] * stride + x[i1]]) >> 1;
}
if(!data[j = y[8] * stride + x[8]]) {
int v = 0;
for(int i = 0; i < 4; ++i)
v += data[y[i] * stride + x[i]];
data[j] = v >> 2;
}
if(w_2 > 1) {
triangleEdgeCPU(data, x[0], y[0], stride, w_2, h_2, ++p);
triangleEdgeCPU(data, x[4], y[4], stride, w_2, h_2, p);
triangleEdgeCPU(data, x[8], y[8], stride, w_2, h_2, p);
triangleEdgeCPU(data, x[7], y[7], stride, w_2, h_2, p);
}
}
void diamontCPU(int w, int h, unsigned char * data) {
int sw1 = w - 1, sw2 = sw1 >> 1;
int sh1 = h - 1, sh2 = sh1 >> 1;
while(sw2){
for(int y = sh2; y < h; y += sh1){
for(int x = sw2; x < w; x += sw1){
if(data[y * w + x]) continue;
data[y * w + x] = (data[(y - sh2) * w + x - sw2] +
data[(y - sh2) * w + x + sw2] +
data[(y + sh2) * w + x + sw2] +
data[(y + sh2) * w + x - sw2]) >> 2;
}
}
for(int y = 0; y < h; y += sh1){
for(int x = sw2; x < w; x += sw1){
int yp, xp;
int nbp = 0, v = 0;
if(data[y * w + x]) continue;
yp = y - sh2; xp = x; // parent haut
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y; xp = x + sw2; // parent droit
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y + sh2; xp = x; // parent bas
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y; xp = x - sw2; // parent gauche
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
data[y * w + x] = v / nbp;
}
}
for(int y = sh2; y < h; y += sh1){
for(int x = 0; x < w; x += sw1){
int yp, xp;
int nbp = 0, v = 0;
if(data[y * w + x]) continue;
yp = y - sh2; xp = x; // parent haut
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y; xp = x + sw2; // parent droit
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y + sh2; xp = x; // parent bas
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y; xp = x - sw2; // parent gauche
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
data[y * w + x] = v / nbp;
}
}
sw1 = sw2;
sw2 >>= 1;
sh1 = sh2;
sh2 >>= 1;
}
}
__global__ void generateImg(unsigned char * data, unsigned char * img, unsigned char * tabDepth, int4 * _tabParents, int i, int tailleTab) {
int thx = blockIdx.x * blockDim.x + threadIdx.x;
int thy = blockIdx.y * blockDim.y + threadIdx.y;
int ThId = thy * tailleTab + thx;
int nbPar = 0;
if(data[ThId] == 0 && tabDepth[ThId] == i && i != 1) {
if(_tabParents[ThId].x != -1) nbPar ++;
if(_tabParents[ThId].y != -1) nbPar ++;
if(_tabParents[ThId].z != -1) nbPar ++;
if(_tabParents[ThId].w != -1) nbPar ++;
data[ThId] = (data[_tabParents[ThId].x] + data[_tabParents[ThId].y] + data[_tabParents[ThId].z] + data[_tabParents[ThId].w]) / nbPar;
img[ThId] = data[ThId];
}
}
void initTime(void) {
gettimeofday(&ti, (struct timezone*) 0);
}
double getTime(void) {
struct timeval t;
double diff;
gettimeofday(&t, (struct timezone*) 0);
diff = (t.tv_sec - ti.tv_sec) * 1000000
+ (t.tv_usec - ti.tv_usec);
return diff/1000.;
}
|
.file "tmpxft_0006b0f8_00000000-6_functions.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z2INiiii
.type _Z2INiiii, @function
_Z2INiiii:
.LFB2057:
.cfi_startproc
endbr64
movl $0, %eax
movl %edi, %r8d
orl %esi, %r8d
js .L3
cmpl %edx, %edi
setl %al
cmpl %ecx, %esi
setl %dl
andl %edx, %eax
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z2INiiii, .-_Z2INiiii
.globl _Z7maxProfPhi
.type _Z7maxProfPhi, @function
_Z7maxProfPhi:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L9
movq %rdi, %rax
movslq %esi, %rsi
addq %rsi, %rdi
movl $0, %edx
.L8:
movzbl (%rax), %ecx
cmpl %ecx, %edx
cmovl %ecx, %edx
addq $1, %rax
cmpq %rdi, %rax
jne .L8
.L6:
movl %edx, %eax
ret
.L9:
movl $0, %edx
jmp .L6
.cfi_endproc
.LFE2058:
.size _Z7maxProfPhi, .-_Z7maxProfPhi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Matrice de %s \n \n"
.LC1:
.string "%d "
.LC2:
.string "\n"
.text
.globl _Z10displayMatPhPci
.type _Z10displayMatPhPci, @function
_Z10displayMatPhPci:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movl %edx, %ebx
movl %edx, 4(%rsp)
movq %rsi, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L12
movslq %ebx, %r15
addq %r15, %rbp
movl $0, %r13d
leaq .LC1(%rip), %r12
leaq (%r15,%r15), %rax
movq %rax, 8(%rsp)
.L13:
movq %rbp, %r14
subq %r15, %r14
movq %r14, %rbx
.L14:
movzbl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbp, %rbx
jne .L14
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
movq 8(%rsp), %rax
leaq (%rax,%r14), %rbp
cmpl %r13d, 4(%rsp)
jne .L13
.L12:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z10displayMatPhPci, .-_Z10displayMatPhPci
.globl _Z12initArraysDsPhP4int4ii
.type _Z12initArraysDsPhP4int4ii, @function
_Z12initArraysDsPhP4int4ii:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $112, %rsp
.cfi_def_cfa_offset 168
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movl %edx, %r15d
movl %ecx, %r13d
leal -1(%rdx), %eax
movl %eax, 20(%rsp)
leal -1(%rcx), %edx
movl %edx, %ecx
sarl %ecx
movl $2, 16(%rsp)
movl $1, 104(%rsp)
sarl %eax
je .L17
movl %ecx, %esi
movl %eax, %ecx
movl %edx, 80(%rsp)
movl %r13d, %eax
movl %r15d, %r13d
movl %eax, %r15d
jmp .L18
.L20:
addq %r10, %rdx
addq %r11, %rsi
cmpl %edx, %r13d
jle .L24
.L21:
cmpb $0, (%rdi,%rdx)
jne .L20
movb %r15b, (%rdi,%rdx)
leal (%r9,%rdx), %r8d
movl %r8d, (%rsi)
leal (%r12,%rdx), %r8d
movl %r8d, 4(%rsi)
leal 0(%rbp,%rdx), %r8d
movl %r8d, 8(%rsi)
leal (%rbx,%rdx), %r8d
movl %r8d, 12(%rsi)
jmp .L20
.L24:
movl 80(%rsp), %esi
addl %esi, %r14d
addl %eax, %r9d
addl %eax, %r12d
addl %eax, %ebp
addl %eax, %ebx
cmpl %r14d, (%rsp)
jle .L22
.L55:
cmpl %ecx, %r13d
jle .L24
movslq %ecx, %rdx
movl 8(%rsp), %esi
leal (%r9,%rsi), %edi
movslq %edi, %rdi
leaq (%rdx,%rdi), %rsi
salq $4, %rsi
movq 72(%rsp), %r8
addq %r8, %rsi
movq 64(%rsp), %r8
addq %r8, %rdi
jmp .L21
.L22:
movl 12(%rsp), %esi
movl (%rsp), %r15d
testl %r15d, %r15d
jle .L25
.L56:
movl 80(%rsp), %edi
imull %r13d, %edi
movl %ecx, 8(%rsp)
movl %ecx, %r8d
negl %r8d
movl %esi, %r9d
movl %r13d, %edx
imull %esi, %edx
movl %ecx, %eax
subl %edx, %eax
movl %eax, 100(%rsp)
leal (%rdx,%rcx), %eax
movl %eax, 96(%rsp)
movslq 20(%rsp), %r10
movq %r10, %rax
salq $4, %rax
movq %rax, 24(%rsp)
movl %ecx, 52(%rsp)
movl $0, %edx
movl %esi, 108(%rsp)
movl %edx, %r14d
movl %ecx, %edx
movq %r10, 32(%rsp)
jmp .L26
.L28:
movl $-1, 0(%rbp)
jmp .L29
.L30:
movl $-1, 4(%rbp)
jmp .L31
.L32:
movl $-1, 8(%rbp)
jmp .L33
.L34:
movl $-1, 12(%rbp)
.L35:
movzbl 16(%rsp), %eax
movb %al, (%r14,%rbx)
.L27:
movq 32(%rsp), %rax
addq %rax, %rbx
movq 24(%rsp), %rax
addq %rax, %rbp
cmpl %ebx, %r13d
jle .L65
.L36:
cmpb $0, (%r14,%rbx)
jne .L27
movl %ebx, %r12d
movl %ebx, 12(%rsp)
movl %r15d, %ecx
movl %r13d, %edx
movl 40(%rsp), %esi
movl %ebx, %edi
call _Z2INiiii
testb %al, %al
je .L28
movl 60(%rsp), %eax
addl %ebx, %eax
movl %eax, 0(%rbp)
.L29:
movl 8(%rsp), %eax
leal (%r12,%rax), %edi
movl %r15d, %ecx
movl %r13d, %edx
movl (%rsp), %esi
call _Z2INiiii
testb %al, %al
je .L30
movl 52(%rsp), %eax
addl %r12d, %eax
movl %eax, 4(%rbp)
.L31:
movl %r15d, %ecx
movl %r13d, %edx
movl 44(%rsp), %esi
movl 12(%rsp), %edi
call _Z2INiiii
testb %al, %al
je .L32
movl 56(%rsp), %eax
addl %r12d, %eax
movl %eax, 8(%rbp)
.L33:
movl %r12d, %edi
movl 8(%rsp), %eax
subl %eax, %edi
movl %r15d, %ecx
movl %r13d, %edx
movl (%rsp), %esi
call _Z2INiiii
testb %al, %al
je .L34
movl 48(%rsp), %eax
addl %eax, %r12d
movl %r12d, 12(%rbp)
jmp .L35
.L65:
movl 84(%rsp), %edx
movl (%rsp), %r14d
movl 48(%rsp), %r8d
movl 88(%rsp), %edi
movl 92(%rsp), %r9d
.L39:
movl 80(%rsp), %eax
addl %eax, %r14d
addl %edi, %r8d
addl %edi, 52(%rsp)
cmpl %r14d, %r15d
jle .L37
.L26:
cmpl %edx, %r13d
jle .L39
movl %r14d, %eax
subl %r9d, %eax
movl %eax, 40(%rsp)
movl 100(%rsp), %eax
addl %r8d, %eax
movl %eax, 60(%rsp)
leal (%r9,%r14), %eax
movl %eax, 44(%rsp)
movl 96(%rsp), %eax
addl %r8d, %eax
movl %eax, 56(%rsp)
movslq %edx, %rbx
movl 8(%rsp), %eax
addl %r8d, %eax
cltq
leaq (%rbx,%rax), %rbp
salq $4, %rbp
movq 72(%rsp), %rcx
addq %rcx, %rbp
movq 64(%rsp), %rcx
addq %rcx, %rax
movl %edx, 84(%rsp)
movl %r14d, (%rsp)
movq %rax, %r14
movl %r8d, 48(%rsp)
movl %edi, 88(%rsp)
movl %r9d, 92(%rsp)
jmp .L36
.L37:
movl %edx, %ecx
movl 108(%rsp), %esi
cmpl %esi, %r15d
jle .L40
.L25:
movl 80(%rsp), %eax
imull %r13d, %eax
movl %esi, %r10d
movl %r13d, %edx
imull %esi, %edx
movl %ecx, 12(%rsp)
movl %edx, %r8d
subl %ecx, %r8d
leal (%rdx,%rdx), %r9d
movl %ecx, %edi
subl %edx, %edi
movslq 20(%rsp), %rdx
movq %rdx, %rbx
salq $4, %rbx
movq %rbx, 24(%rsp)
movl %esi, %r14d
movl %ecx, 96(%rsp)
movl %esi, 100(%rsp)
movq %rdx, 32(%rsp)
jmp .L41
.L43:
movl $-1, 0(%rbp)
jmp .L44
.L45:
movl $-1, 4(%rbp)
jmp .L46
.L47:
movl $-1, 8(%rbp)
jmp .L48
.L49:
movl $-1, 12(%rbp)
.L50:
movq (%rsp), %rax
movzbl 16(%rsp), %ecx
movb %cl, (%rax)
.L42:
movl 20(%rsp), %eax
addl %eax, %ebx
movq 32(%rsp), %rax
addq %rax, %r12
movq 24(%rsp), %rax
addq %rax, %rbp
cmpl %ebx, %r13d
jle .L66
.L51:
movq %r12, (%rsp)
cmpb $0, (%r12)
jne .L42
movl %r15d, %ecx
movl %r13d, %edx
movl 40(%rsp), %esi
movl %ebx, %edi
call _Z2INiiii
testb %al, %al
je .L43
movl 56(%rsp), %eax
addl %ebx, %eax
movl %eax, 0(%rbp)
.L44:
movl %ebx, %r14d
movl 12(%rsp), %eax
leal (%rbx,%rax), %edi
movl %r15d, %ecx
movl %r13d, %edx
movl 8(%rsp), %esi
call _Z2INiiii
testb %al, %al
je .L45
movl 60(%rsp), %eax
addl %ebx, %eax
movl %eax, 4(%rbp)
.L46:
movl %r15d, %ecx
movl %r13d, %edx
movl 44(%rsp), %esi
movl %ebx, %edi
call _Z2INiiii
testb %al, %al
je .L47
movl 52(%rsp), %eax
addl %r14d, %eax
movl %eax, 8(%rbp)
.L48:
movl %r14d, %edi
movl 12(%rsp), %eax
subl %eax, %edi
movl %r15d, %ecx
movl %r13d, %edx
movl 8(%rsp), %esi
call _Z2INiiii
testb %al, %al
je .L49
movl 48(%rsp), %eax
addl %eax, %r14d
movl %r14d, 12(%rbp)
jmp .L50
.L66:
movl 8(%rsp), %r14d
movl 48(%rsp), %r8d
movl 84(%rsp), %eax
movl 88(%rsp), %r10d
movl 52(%rsp), %r9d
movl 92(%rsp), %edi
.L53:
movl 80(%rsp), %ecx
addl %ecx, %r14d
addl %eax, %r8d
addl %eax, %r9d
cmpl %r14d, %r15d
jle .L63
.L41:
testl %r13d, %r13d
jle .L53
movl %r14d, %ecx
subl %r10d, %ecx
movl %ecx, 40(%rsp)
leal (%r8,%rdi), %ecx
movl %ecx, 56(%rsp)
leal (%r10,%r14), %ecx
movl %ecx, 44(%rsp)
movl 12(%rsp), %ecx
leal (%r8,%rcx), %ebp
movslq %ebp, %rbp
movq 64(%rsp), %rcx
leaq (%rcx,%rbp), %r12
salq $4, %rbp
movq 72(%rsp), %rcx
addq %rcx, %rbp
leal (%r9,%rdi), %ecx
movl %ecx, 60(%rsp)
movl $0, %ebx
movl %r14d, 8(%rsp)
movl %r8d, 48(%rsp)
movl %eax, 84(%rsp)
movl %r10d, 88(%rsp)
movl %r9d, 52(%rsp)
movl %edi, 92(%rsp)
jmp .L51
.L63:
movl 96(%rsp), %ecx
movl 100(%rsp), %esi
.L40:
addl $2, 104(%rsp)
movl %esi, %eax
sarl %eax
addl $2, 16(%rsp)
movl %ecx, 20(%rsp)
movl %esi, 80(%rsp)
sarl %ecx
je .L17
movl %eax, %esi
.L18:
cmpl %esi, %r15d
jle .L54
movl 80(%rsp), %eax
imull %r13d, %eax
movl %ecx, %r12d
movl %ecx, %r9d
negl %r9d
movl %r13d, %edx
imull %esi, %edx
leal (%rdx,%rdx), %ebx
leal (%rcx,%rbx), %ebp
subl %ecx, %ebx
addl %ecx, %edx
movl %edx, 8(%rsp)
movslq 20(%rsp), %r10
movq %r10, %r11
salq $4, %r11
movl %esi, %r14d
movl %esi, 12(%rsp)
movl %r15d, (%rsp)
movl 104(%rsp), %r15d
jmp .L55
.L54:
testl %r15d, %r15d
jg .L56
jmp .L40
.L17:
addq $112, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z12initArraysDsPhP4int4ii, .-_Z12initArraysDsPhP4int4ii
.globl _Z12initArraysTePhP4int4iiiiii
.type _Z12initArraysTePhP4int4iiiiii, @function
_Z12initArraysTePhP4int4iiiiii:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %rdi, %rbp
movq %rsi, 8(%rsp)
movl %edx, %r13d
movl %ecx, %r12d
movl %r8d, %ebx
movl 192(%rsp), %eax
movl 200(%rsp), %r14d
movq %fs:40, %rdx
movq %rdx, 120(%rsp)
xorl %edx, %edx
movl %r9d, %ecx
sarl %ecx
movl %ecx, 16(%rsp)
movl %eax, %esi
sarl %esi
movl %esi, 24(%rsp)
movl %r13d, 32(%rsp)
addl %r13d, %r9d
movl %r9d, 36(%rsp)
movl %r9d, 40(%rsp)
movl %r13d, 44(%rsp)
leal (%rcx,%r13), %r15d
movl %r15d, 48(%rsp)
movl %r9d, 52(%rsp)
movl %r15d, 56(%rsp)
movl %r13d, 60(%rsp)
movl %r12d, 80(%rsp)
movl %r12d, 84(%rsp)
leal (%rax,%r12), %r10d
movl %r10d, 88(%rsp)
movl %r10d, 92(%rsp)
movl %r12d, 96(%rsp)
leal (%rsi,%r12), %eax
movl %eax, 20(%rsp)
movl %eax, 100(%rsp)
movl %r10d, 104(%rsp)
movl %eax, 108(%rsp)
leaq 80(%rsp), %rcx
leaq 32(%rsp), %rsi
leaq 96(%rsp), %r11
movl $1, %edx
movl %r9d, 28(%rsp)
jmp .L69
.L68:
addl $1, %edx
movl %edx, %eax
sarl $31, %eax
shrl $30, %eax
addl %eax, %edx
andl $3, %edx
subl %eax, %edx
addq $4, %rcx
addq $4, %rsi
cmpq %r11, %rcx
je .L80
.L69:
movl %ebx, %eax
imull 16(%rcx), %eax
addl 16(%rsi), %eax
cltq
leaq 0(%rbp,%rax), %r8
cmpb $0, (%r8)
jne .L68
salq $4, %rax
movq 8(%rsp), %rdi
addq %rdi, %rax
movl %ebx, %edi
imull (%rcx), %edi
addl (%rsi), %edi
movl %edi, (%rax)
movslq %edx, %r9
movl %ebx, %edi
imull 80(%rsp,%r9,4), %edi
addl 32(%rsp,%r9,4), %edi
movl %edi, 4(%rax)
movl $-1, 8(%rax)
movl $-1, 12(%rax)
movb %r14b, (%r8)
jmp .L68
.L80:
movl 28(%rsp), %r9d
movl 20(%rsp), %eax
imull %ebx, %eax
addl %r15d, %eax
cltq
leaq 0(%rbp,%rax), %rcx
cmpb $0, (%rcx)
jne .L70
salq $4, %rax
movq 8(%rsp), %rsi
leaq (%rsi,%rax), %rdx
movl $0, %eax
leaq 80(%rsp), %rdi
jmp .L75
.L81:
movl %r12d, %esi
imull %ebx, %esi
addl %r9d, %esi
movl %esi, (%rdx)
.L72:
addq $1, %rax
.L75:
movb %r14b, (%rcx)
cmpl $1, %eax
je .L81
cmpl $2, %eax
je .L82
cmpl $3, %eax
je .L83
movl %ebx, %esi
imull (%rdi,%rax,4), %esi
addl 32(%rsp,%rax,4), %esi
movl %esi, 12(%rdx)
jmp .L72
.L82:
movl %r10d, %esi
imull %ebx, %esi
addl %r9d, %esi
movl %esi, 4(%rdx)
jmp .L72
.L83:
imull %ebx, %r10d
addl %r13d, %r10d
movl %r10d, 8(%rdx)
.L70:
movl 16(%rsp), %eax
cmpl $1, %eax
jg .L84
.L67:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L85
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L84:
.cfi_restore_state
addl $1, %r14d
pushq %r14
.cfi_def_cfa_offset 200
movl 32(%rsp), %ecx
pushq %rcx
.cfi_def_cfa_offset 208
movl %eax, 32(%rsp)
movl %eax, %r9d
movl %ebx, %r8d
movl %r12d, %ecx
movl %r13d, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call _Z12initArraysTePhP4int4iiiiii
pushq %r14
.cfi_def_cfa_offset 216
movl 48(%rsp), %ecx
pushq %rcx
.cfi_def_cfa_offset 224
movl 48(%rsp), %r9d
movl %ebx, %r8d
movl %r12d, %ecx
movl %r15d, %edx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call _Z12initArraysTePhP4int4iiiiii
addq $32, %rsp
.cfi_def_cfa_offset 192
pushq %r14
.cfi_def_cfa_offset 200
movl 32(%rsp), %ecx
pushq %rcx
.cfi_def_cfa_offset 208
movl 32(%rsp), %r12d
movl %r12d, %r9d
movl %ebx, %r8d
movl 36(%rsp), %ecx
movl %r15d, %edx
movq 24(%rsp), %r15
movq %r15, %rsi
movq %rbp, %rdi
call _Z12initArraysTePhP4int4iiiiii
pushq %r14
.cfi_def_cfa_offset 216
movl 48(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 224
movl %r12d, %r9d
movl %ebx, %r8d
movl 52(%rsp), %ecx
movl %r13d, %edx
movq %r15, %rsi
movq %rbp, %rdi
call _Z12initArraysTePhP4int4iiiiii
addq $32, %rsp
.cfi_def_cfa_offset 192
jmp .L67
.L85:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z12initArraysTePhP4int4iiiiii, .-_Z12initArraysTePhP4int4iiiiii
.globl _Z15triangleEdgeCPUPhiiiiii
.type _Z15triangleEdgeCPUPhiiiiii, @function
_Z15triangleEdgeCPUPhiiiiii:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rdi, %rbx
movl %esi, %r12d
movl %edx, %r13d
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl %r8d, %eax
sarl %eax
movl %eax, 4(%rsp)
movl %r9d, %edi
sarl %edi
movl %edi, 8(%rsp)
movl %esi, 16(%rsp)
addl %esi, %r8d
movl %r8d, 20(%rsp)
movl %r8d, 24(%rsp)
movl %esi, 28(%rsp)
leal (%rax,%rsi), %r14d
movl %r14d, 32(%rsp)
movl %r8d, 36(%rsp)
movl %r14d, 40(%rsp)
movl %esi, 44(%rsp)
movl %edx, 64(%rsp)
movl %edx, 68(%rsp)
addl %edx, %r9d
movl %r9d, 72(%rsp)
movl %r9d, 76(%rsp)
movl %edx, 80(%rsp)
leal (%rdi,%rdx), %r15d
movl %r15d, 84(%rsp)
movl %r9d, 88(%rsp)
movl %r15d, 92(%rsp)
leaq 64(%rsp), %rcx
leaq 16(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $1, %edx
jmp .L88
.L87:
addl $1, %edx
movl %edx, %eax
sarl $31, %eax
shrl $30, %eax
addl %eax, %edx
andl $3, %edx
subl %eax, %edx
addq $4, %rcx
addq $4, %rsi
cmpq %rdi, %rcx
je .L96
.L88:
movl %ebp, %eax
imull 16(%rcx), %eax
addl 16(%rsi), %eax
cltq
addq %rbx, %rax
cmpb $0, (%rax)
jne .L87
movl %ebp, %r8d
imull (%rcx), %r8d
addl (%rsi), %r8d
movslq %r8d, %r8
movzbl (%rbx,%r8), %r8d
movslq %edx, %r10
movl %ebp, %r9d
imull 64(%rsp,%r10,4), %r9d
addl 16(%rsp,%r10,4), %r9d
movslq %r9d, %r9
movzbl (%rbx,%r9), %r9d
addl %r9d, %r8d
sarl %r8d
movb %r8b, (%rax)
jmp .L87
.L96:
movl %r15d, %ecx
imull %ebp, %ecx
addl %r14d, %ecx
movslq %ecx, %rcx
addq %rbx, %rcx
cmpb $0, (%rcx)
jne .L89
movl $0, %edx
movl $0, %esi
leaq 64(%rsp), %rdi
.L90:
movl %ebp, %eax
imull (%rdx,%rdi), %eax
addl 16(%rsp,%rdx), %eax
cltq
movzbl (%rbx,%rax), %eax
addl %eax, %esi
addq $4, %rdx
cmpq $16, %rdx
jne .L90
sarl $2, %esi
movb %sil, (%rcx)
.L89:
movl 4(%rsp), %eax
cmpl $1, %eax
jg .L97
.L86:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L98
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L97:
.cfi_restore_state
movl 176(%rsp), %esi
leal 1(%rsi), %edi
subq $8, %rsp
.cfi_def_cfa_offset 184
movl %edi, 20(%rsp)
pushq %rdi
.cfi_def_cfa_offset 192
movl 24(%rsp), %r9d
movl %eax, 20(%rsp)
movl %eax, %r8d
movl %ebp, %ecx
movl %r13d, %edx
movl %r12d, %esi
movq %rbx, %rdi
call _Z15triangleEdgeCPUPhiiiiii
movl 28(%rsp), %edi
movl %edi, (%rsp)
movl 24(%rsp), %r9d
movl 20(%rsp), %r8d
movl %ebp, %ecx
movl %r13d, %edx
movl %r14d, %esi
movq %rbx, %rdi
call _Z15triangleEdgeCPUPhiiiiii
movl 28(%rsp), %edi
movl %edi, (%rsp)
movl 24(%rsp), %r9d
movl 20(%rsp), %r13d
movl %r13d, %r8d
movl %ebp, %ecx
movl %r15d, %edx
movl %r14d, %esi
movq %rbx, %rdi
call _Z15triangleEdgeCPUPhiiiiii
movl 28(%rsp), %edi
movl %edi, (%rsp)
movl 24(%rsp), %r9d
movl %r13d, %r8d
movl %ebp, %ecx
movl %r15d, %edx
movl %r12d, %esi
movq %rbx, %rdi
call _Z15triangleEdgeCPUPhiiiiii
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L86
.L98:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z15triangleEdgeCPUPhiiiiii, .-_Z15triangleEdgeCPUPhiiiiii
.globl _Z10diamontCPUiiPh
.type _Z10diamontCPUiiPh, @function
_Z10diamontCPUiiPh:
.LFB2063:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $96, %rsp
.cfi_def_cfa_offset 152
leal -1(%rdi), %ebx
movl %ebx, 40(%rsp)
leal -1(%rsi), %r10d
movl %r10d, %eax
sarl %eax
sarl %ebx
je .L99
movl %esi, %r15d
movl %ebx, %esi
movl %r10d, 68(%rsp)
movl %r15d, %ebx
movl %edi, %r15d
movq %rdx, (%rsp)
movl %ebx, %r14d
jmp .L100
.L102:
addq %r10, %rax
cmpl %eax, %r15d
jle .L142
.L103:
cmpb $0, (%r8,%rax)
jne .L102
leal (%r9,%rax), %ecx
movslq %ecx, %rcx
movzbl (%r11,%rcx), %ecx
leal (%r12,%rax), %esi
movslq %esi, %rsi
movzbl (%r11,%rsi), %esi
addl %esi, %ecx
leal 0(%rbp,%rax), %esi
movslq %esi, %rsi
movzbl (%r11,%rsi), %esi
addl %esi, %ecx
leal (%rbx,%rax), %esi
movslq %esi, %rsi
movzbl (%r11,%rsi), %esi
addl %esi, %ecx
sarl $2, %ecx
movb %cl, (%r8,%rax)
jmp .L102
.L142:
movl 8(%rsp), %esi
.L106:
movl 68(%rsp), %eax
addl %eax, %edi
addl %r13d, %r9d
addl %r13d, %r12d
addl %r13d, %ebp
addl %r13d, %ebx
cmpl %edi, %r14d
jle .L104
.L129:
leal (%r9,%rdx), %r8d
movslq %esi, %rax
movslq %r8d, %r8
addq %r11, %r8
cmpl %esi, %r15d
jle .L106
movl %esi, 8(%rsp)
jmp .L103
.L104:
movl 16(%rsp), %eax
testl %r14d, %r14d
jle .L107
.L130:
movl 68(%rsp), %ebp
imull %r15d, %ebp
movl %esi, 24(%rsp)
movl %esi, %r8d
negl %r8d
movl %eax, %r12d
movl %r15d, %edx
imull %eax, %edx
movl %esi, %r13d
subl %edx, %r13d
leal (%rdx,%rsi), %ebx
movl %ebx, 84(%rsp)
movl %esi, 56(%rsp)
movl $0, %ecx
movslq 40(%rsp), %rbx
movq %rbx, 32(%rsp)
movl %eax, 92(%rsp)
movl %r8d, %eax
movl %ecx, %r8d
movl %r13d, 88(%rsp)
movl %esi, %r13d
movl %r12d, %esi
movl %eax, %ecx
jmp .L108
.L131:
movl $0, %ebp
movl $0, %r13d
.L110:
movl 24(%rsp), %eax
leal (%r12,%rax), %edi
movl %r14d, %ecx
movl %r15d, %edx
movl 16(%rsp), %esi
call _Z2INiiii
testb %al, %al
je .L111
addl $1, %r13d
movl 56(%rsp), %eax
addl %r12d, %eax
cltq
movq (%rsp), %rdx
movzbl (%rdx,%rax), %eax
addl %eax, %ebp
.L111:
movl %r14d, %ecx
movl %r15d, %edx
movl 48(%rsp), %esi
movl 28(%rsp), %edi
call _Z2INiiii
testb %al, %al
je .L112
addl $1, %r13d
movl 64(%rsp), %eax
addl %r12d, %eax
cltq
movq (%rsp), %rdx
movzbl (%rdx,%rax), %eax
addl %eax, %ebp
.L112:
movl %r12d, %edi
movl 24(%rsp), %eax
subl %eax, %edi
movl %r14d, %ecx
movl %r15d, %edx
movl 16(%rsp), %esi
call _Z2INiiii
testb %al, %al
je .L113
addl $1, %r13d
movl 52(%rsp), %eax
addl %eax, %r12d
movslq %r12d, %r12
movq (%rsp), %rax
movzbl (%rax,%r12), %eax
addl %eax, %ebp
.L113:
movl %ebp, %eax
cltd
idivl %r13d
movq 8(%rsp), %rdx
movb %al, (%rdx,%rbx)
.L109:
movq 32(%rsp), %rax
addq %rax, %rbx
cmpl %ebx, %r15d
jle .L143
.L114:
movq 8(%rsp), %rax
cmpb $0, (%rax,%rbx)
jne .L109
movl %ebx, %r12d
movl %ebx, 28(%rsp)
movl %r14d, %ecx
movl %r15d, %edx
movl 44(%rsp), %esi
movl %ebx, %edi
call _Z2INiiii
testb %al, %al
je .L131
movl 60(%rsp), %eax
addl %ebx, %eax
cltq
movq (%rsp), %rdx
movzbl (%rdx,%rax), %ebp
movl $1, %r13d
jmp .L110
.L143:
movl 72(%rsp), %r13d
movl 16(%rsp), %r8d
movl 52(%rsp), %ecx
movl 76(%rsp), %ebp
movl 80(%rsp), %esi
.L117:
movl 68(%rsp), %eax
addl %eax, %r8d
addl %ebp, %ecx
addl %ebp, 56(%rsp)
cmpl %r8d, %r14d
jle .L115
.L108:
cmpl %r13d, %r15d
jle .L117
movl 24(%rsp), %eax
addl %ecx, %eax
movl %r8d, %ebx
subl %esi, %ebx
movl %ebx, 44(%rsp)
movl 88(%rsp), %ebx
addl %ecx, %ebx
movl %ebx, 60(%rsp)
leal (%rsi,%r8), %ebx
movl %ebx, 48(%rsp)
movl 84(%rsp), %ebx
addl %ecx, %ebx
movl %ebx, 64(%rsp)
movslq %r13d, %rbx
cltq
movq (%rsp), %rdx
addq %rdx, %rax
movq %rax, 8(%rsp)
movl %r13d, 72(%rsp)
movl %r8d, 16(%rsp)
movl %ecx, 52(%rsp)
movl %ebp, 76(%rsp)
movl %esi, 80(%rsp)
jmp .L114
.L115:
movl %r13d, %esi
movl 92(%rsp), %eax
cmpl %eax, %r14d
jle .L118
.L107:
movl 68(%rsp), %ebp
imull %r15d, %ebp
movl %r15d, %edx
imull %eax, %edx
movl %esi, 28(%rsp)
movl %edx, %r8d
subl %esi, %r8d
leal (%rdx,%rdx), %r9d
movl %esi, %r13d
subl %edx, %r13d
movslq 40(%rsp), %rbx
movq %rbx, 32(%rsp)
movl %esi, 84(%rsp)
movl %eax, 88(%rsp)
movl %eax, %esi
movl %ebp, %r12d
movl %eax, %edx
movl %r13d, %ecx
jmp .L119
.L132:
movl $0, %r12d
movl $0, %r13d
.L121:
movl %ebx, %r14d
movl 28(%rsp), %eax
leal (%rbx,%rax), %edi
movl 8(%rsp), %ecx
movl %r15d, %edx
movl 24(%rsp), %esi
call _Z2INiiii
testb %al, %al
je .L122
addl $1, %r13d
movl 64(%rsp), %eax
addl %ebx, %eax
cltq
movq (%rsp), %rdx
movzbl (%rdx,%rax), %eax
addl %eax, %r12d
.L122:
movl 8(%rsp), %ecx
movl %r15d, %edx
movl 48(%rsp), %esi
movl %ebx, %edi
call _Z2INiiii
testb %al, %al
je .L123
addl $1, %r13d
movl 56(%rsp), %eax
addl %r14d, %eax
cltq
movq (%rsp), %rdx
movzbl (%rdx,%rax), %eax
addl %eax, %r12d
.L123:
movl %r14d, %edi
movl 28(%rsp), %eax
subl %eax, %edi
movl 8(%rsp), %ecx
movl %r15d, %edx
movl 24(%rsp), %esi
call _Z2INiiii
testb %al, %al
je .L124
addl $1, %r13d
movl 52(%rsp), %eax
addl %eax, %r14d
movslq %r14d, %r14
movq (%rsp), %rax
movzbl (%rax,%r14), %eax
addl %eax, %r12d
.L124:
movl %r12d, %eax
cltd
idivl %r13d
movq 16(%rsp), %rdx
movb %al, (%rdx)
.L120:
movl 40(%rsp), %eax
addl %eax, %ebx
movq 32(%rsp), %rax
addq %rax, %rbp
cmpl %ebx, %r15d
jle .L144
.L125:
movq %rbp, 16(%rsp)
cmpb $0, 0(%rbp)
jne .L120
movl 8(%rsp), %ecx
movl %r15d, %edx
movl 44(%rsp), %esi
movl %ebx, %edi
call _Z2INiiii
testb %al, %al
je .L132
movl 60(%rsp), %eax
addl %ebx, %eax
cltq
movq (%rsp), %rdx
movzbl (%rdx,%rax), %r12d
movl $1, %r13d
jmp .L121
.L144:
movl 24(%rsp), %esi
movl 52(%rsp), %r8d
movl 72(%rsp), %r12d
movl 76(%rsp), %edx
movl 56(%rsp), %r9d
movl 80(%rsp), %ecx
movl 8(%rsp), %r14d
.L127:
movl 68(%rsp), %eax
addl %eax, %esi
addl %r12d, %r8d
addl %r12d, %r9d
cmpl %esi, %r14d
jle .L140
.L119:
testl %r15d, %r15d
jle .L127
movl %esi, %eax
subl %edx, %eax
movl %eax, 44(%rsp)
leal (%r8,%rcx), %eax
movl %eax, 60(%rsp)
leal (%rdx,%rsi), %eax
movl %eax, 48(%rsp)
movl 28(%rsp), %eax
addl %r8d, %eax
cltq
movq (%rsp), %rbx
leaq (%rbx,%rax), %rbp
leal (%r9,%rcx), %eax
movl %eax, 64(%rsp)
movl $0, %ebx
movl %esi, 24(%rsp)
movl %r8d, 52(%rsp)
movl %r12d, 72(%rsp)
movl %edx, 76(%rsp)
movl %r9d, 56(%rsp)
movl %ecx, 80(%rsp)
movl %r14d, 8(%rsp)
jmp .L125
.L140:
movl 84(%rsp), %esi
movl 88(%rsp), %eax
.L118:
movl %eax, %edi
sarl %edi
movl %esi, 40(%rsp)
movl %eax, 68(%rsp)
movl %esi, %edx
sarl %edx
je .L99
movl %edi, %eax
movl %edx, %esi
.L100:
cmpl %eax, %r14d
jle .L128
movl 68(%rsp), %r13d
imull %r15d, %r13d
movl %esi, %r12d
movl %esi, %r9d
negl %r9d
movl %r15d, %edx
imull %eax, %edx
leal (%rdx,%rdx), %ebx
leal (%rsi,%rbx), %ebp
subl %esi, %ebx
leal (%rdx,%rsi), %ecx
movl %eax, %edi
movslq 40(%rsp), %r10
movl %eax, 16(%rsp)
movl %ecx, %edx
movq (%rsp), %r11
jmp .L129
.L128:
testl %r14d, %r14d
jg .L130
jmp .L118
.L99:
addq $96, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _Z10diamontCPUiiPh, .-_Z10diamontCPUiiPh
.globl _Z8initTimev
.type _Z8initTimev, @function
_Z8initTimev:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $0, %esi
leaq _ZL2ti(%rip), %rdi
call gettimeofday@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _Z8initTimev, .-_Z8initTimev
.globl _Z7getTimev
.type _Z7getTimev, @function
_Z7getTimev:
.LFB2065:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
movq (%rsp), %rax
subq _ZL2ti(%rip), %rax
imulq $1000000, %rax, %rax
addq 8(%rsp), %rax
subq 8+_ZL2ti(%rip), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC3(%rip), %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L150
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L150:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2065:
.size _Z7getTimev, .-_Z7getTimev
.globl _Z43__device_stub__Z11generateImgPhS_S_P4int4iiPhS_S_P4int4ii
.type _Z43__device_stub__Z11generateImgPhS_S_P4int4iiPhS_S_P4int4ii, @function
_Z43__device_stub__Z11generateImgPhS_S_P4int4iiPhS_S_P4int4ii:
.LFB2090:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L155
.L151:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L156
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L155:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11generateImgPhS_S_P4int4ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L151
.L156:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z43__device_stub__Z11generateImgPhS_S_P4int4iiPhS_S_P4int4ii, .-_Z43__device_stub__Z11generateImgPhS_S_P4int4iiPhS_S_P4int4ii
.globl _Z11generateImgPhS_S_P4int4ii
.type _Z11generateImgPhS_S_P4int4ii, @function
_Z11generateImgPhS_S_P4int4ii:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z11generateImgPhS_S_P4int4iiPhS_S_P4int4ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z11generateImgPhS_S_P4int4ii, .-_Z11generateImgPhS_S_P4int4ii
.section .rodata.str1.1
.LC4:
.string "_Z11generateImgPhS_S_P4int4ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z11generateImgPhS_S_P4int4ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL2ti
.comm _ZL2ti,16,16
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
static struct timeval ti;
bool IN(int x, int y, int w, int h) {
return (x) >= 0 && (y) >= 0 && (x) < (w) && (y) < (h);
}
int maxProf(unsigned char * arr, int matDim){
int max_value = 0;
for (int i = 0; i < matDim; ++i) {
if (arr[i] > max_value)
max_value = arr[i];
}
return max_value;
}
void displayMat(unsigned char * arr, char * name, int matDim){
printf("Matrice de %s \n \n", name);
for(int y = 0; y < matDim; ++y){
for(int x = 0; x < matDim; ++x){
printf("%d ", (int)arr[y * matDim + x]);
}
printf("\n");
}
printf("\n");
}
void initArraysDs(unsigned char * _tabDepth, int4 * _tabParents, int w, int h) {
int sw1 = w - 1, sw2 = sw1 >> 1;
int sh1 = h - 1, sh2 = sh1 >> 1;
int niveau = 1;
while(sw2){
for(int y = sh2; y < h; y += sh1){
for(int x = sw2; x < w; x += sw1){
if(_tabDepth[y * w + x]) continue;
_tabDepth[y * w + x] = niveau;
_tabParents[y * w + x].x = (y - sh2) * w + x - sw2;
_tabParents[y * w + x].y = (y - sh2) * w + x + sw2;
_tabParents[y * w + x].z = (y + sh2) * w + x + sw2;
_tabParents[y * w + x].w = (y + sh2) * w + x - sw2;
}
}
niveau++;
for(int y = 0; y < h; y += sh1){
for(int x = sw2; x < w; x += sw1){
int yp, xp;
if(_tabDepth[y * w + x]) continue;
yp = y - sh2; xp = x; // parent haut
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].x = yp * w + xp;
} else{
_tabParents[y * w + x].x = -1;
}
yp = y; xp = x + sw2; // parent droit
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].y = yp * w + xp;
} else{
_tabParents[y * w + x].y = -1;
}
yp = y + sh2; xp = x; // parent bas
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].z = yp * w + xp;
} else{
_tabParents[y * w + x].z = -1;
}
yp = y; xp = x - sw2; // parent gauche
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].w = yp * w + xp;
} else{
_tabParents[y * w + x].w = -1;
}
_tabDepth[y * w + x] = niveau;
}
}
for(int y = sh2; y < h; y += sh1){
for(int x = 0; x < w; x += sw1){
int yp, xp;
if(_tabDepth[y * w + x]) continue;
yp = y - sh2; xp = x; // parent haut
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].x = yp * w + xp;
} else{
_tabParents[y * w + x].x = -1;
}
yp = y; xp = x + sw2; // parent droit
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].y = yp * w + xp;
} else{
_tabParents[y * w + x].y = -1;
}
yp = y + sh2; xp = x; // parent bas
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].z = yp * w + xp;
} else{
_tabParents[y * w + x].z = -1;
}
yp = y; xp = x - sw2; // parent gauche
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].w = yp * w + xp;
} else{
_tabParents[y * w + x].w = -1;
}
_tabDepth[y * w + x] = niveau;
}
}
niveau ++;
sw1 = sw2;
sw2 >>= 1;
sh1 = sh2;
sh2 >>= 1;
}
}
void initArraysTe(unsigned char * _tabDepth, int4 * _tabParents, int x0, int y0, int stride, int sx, int sy, int p) {
int w_2 = sx >> 1, h_2 = sy >> 1, j;
int x[9] = { x0, x0 + sx, x0 + sx,
x0, x0 + w_2, x0 + sx, x0 + w_2,
x0, x0 + w_2 };
int y[9] = { y0,
y0, y0 + sy, y0 + sy,
y0, y0 + h_2, y0 + sy, y0 + h_2, y0 + h_2 };
for(int i = 0, i1 = 1; i < 4; ++i, i1 = (i1 + 1) % 4) {
if(_tabDepth[j = y[i + 4] * stride + x[i + 4]]) continue;
//Parents
_tabParents[j].x = y[i] * stride + x[i];
_tabParents[j].y = y[i1] * stride + x[i1];
_tabParents[j].z = -1;
_tabParents[j].w = -1;
//prof
_tabDepth[j] = p;
}
if(!_tabDepth[j = y[8] * stride + x[8]]) {
for(int i = 0; i < 4; ++i) {
//prof
_tabDepth[j] = p;
//Tab parent
if(i == 1){
_tabParents[j].x = y[i] * stride + x[i];
} else if(i == 2){
_tabParents[j].y = y[i] * stride + x[i];
} else if(i == 3) {
_tabParents[j].z = y[i] * stride + x[i];
} else {
_tabParents[j].w = y[i] * stride + x[i];
}
}
}
if(w_2 > 1) {
initArraysTe(_tabDepth, _tabParents, x[0], y[0], stride, w_2, h_2, ++p);
initArraysTe(_tabDepth, _tabParents, x[4], y[4], stride, w_2, h_2, p);
initArraysTe(_tabDepth, _tabParents, x[8], y[8], stride, w_2, h_2, p);
initArraysTe(_tabDepth, _tabParents, x[7], y[7], stride, w_2, h_2, p);
}
}
void triangleEdgeCPU(unsigned char * data, int x0, int y0, int stride, int sx, int sy, int p) {
int niveau = 1;
int w_2 = sx >> 1, h_2 = sy >> 1, j;
int x[9] = { x0, x0 + sx, x0 + sx,
x0, x0 + w_2, x0 + sx, x0 + w_2,
x0, x0 + w_2 };
int y[9] = { y0,
y0, y0 + sy, y0 + sy,
y0, y0 + h_2, y0 + sy, y0 + h_2, y0 + h_2 };
for(int i = 0, i1 = 1; i < 4; ++i, i1 = (i1 + 1) % 4) {
if(data[j = y[i + 4] * stride + x[i + 4]]) continue;
data[j] = ((int)data[y[i] * stride + x[i]] +
data[y[i1] * stride + x[i1]]) >> 1;
}
if(!data[j = y[8] * stride + x[8]]) {
int v = 0;
for(int i = 0; i < 4; ++i)
v += data[y[i] * stride + x[i]];
data[j] = v >> 2;
}
if(w_2 > 1) {
triangleEdgeCPU(data, x[0], y[0], stride, w_2, h_2, ++p);
triangleEdgeCPU(data, x[4], y[4], stride, w_2, h_2, p);
triangleEdgeCPU(data, x[8], y[8], stride, w_2, h_2, p);
triangleEdgeCPU(data, x[7], y[7], stride, w_2, h_2, p);
}
}
void diamontCPU(int w, int h, unsigned char * data) {
int sw1 = w - 1, sw2 = sw1 >> 1;
int sh1 = h - 1, sh2 = sh1 >> 1;
while(sw2){
for(int y = sh2; y < h; y += sh1){
for(int x = sw2; x < w; x += sw1){
if(data[y * w + x]) continue;
data[y * w + x] = (data[(y - sh2) * w + x - sw2] +
data[(y - sh2) * w + x + sw2] +
data[(y + sh2) * w + x + sw2] +
data[(y + sh2) * w + x - sw2]) >> 2;
}
}
for(int y = 0; y < h; y += sh1){
for(int x = sw2; x < w; x += sw1){
int yp, xp;
int nbp = 0, v = 0;
if(data[y * w + x]) continue;
yp = y - sh2; xp = x; // parent haut
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y; xp = x + sw2; // parent droit
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y + sh2; xp = x; // parent bas
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y; xp = x - sw2; // parent gauche
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
data[y * w + x] = v / nbp;
}
}
for(int y = sh2; y < h; y += sh1){
for(int x = 0; x < w; x += sw1){
int yp, xp;
int nbp = 0, v = 0;
if(data[y * w + x]) continue;
yp = y - sh2; xp = x; // parent haut
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y; xp = x + sw2; // parent droit
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y + sh2; xp = x; // parent bas
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y; xp = x - sw2; // parent gauche
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
data[y * w + x] = v / nbp;
}
}
sw1 = sw2;
sw2 >>= 1;
sh1 = sh2;
sh2 >>= 1;
}
}
__global__ void generateImg(unsigned char * data, unsigned char * img, unsigned char * tabDepth, int4 * _tabParents, int i, int tailleTab) {
int thx = blockIdx.x * blockDim.x + threadIdx.x;
int thy = blockIdx.y * blockDim.y + threadIdx.y;
int ThId = thy * tailleTab + thx;
int nbPar = 0;
if(data[ThId] == 0 && tabDepth[ThId] == i && i != 1) {
if(_tabParents[ThId].x != -1) nbPar ++;
if(_tabParents[ThId].y != -1) nbPar ++;
if(_tabParents[ThId].z != -1) nbPar ++;
if(_tabParents[ThId].w != -1) nbPar ++;
data[ThId] = (data[_tabParents[ThId].x] + data[_tabParents[ThId].y] + data[_tabParents[ThId].z] + data[_tabParents[ThId].w]) / nbPar;
img[ThId] = data[ThId];
}
}
void initTime(void) {
gettimeofday(&ti, (struct timezone*) 0);
}
double getTime(void) {
struct timeval t;
double diff;
gettimeofday(&t, (struct timezone*) 0);
diff = (t.tv_sec - ti.tv_sec) * 1000000
+ (t.tv_usec - ti.tv_usec);
return diff/1000.;
}
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
static struct timeval ti;
bool IN(int x, int y, int w, int h) {
return (x) >= 0 && (y) >= 0 && (x) < (w) && (y) < (h);
}
int maxProf(unsigned char * arr, int matDim){
int max_value = 0;
for (int i = 0; i < matDim; ++i) {
if (arr[i] > max_value)
max_value = arr[i];
}
return max_value;
}
void displayMat(unsigned char * arr, char * name, int matDim){
printf("Matrice de %s \n \n", name);
for(int y = 0; y < matDim; ++y){
for(int x = 0; x < matDim; ++x){
printf("%d ", (int)arr[y * matDim + x]);
}
printf("\n");
}
printf("\n");
}
void initArraysDs(unsigned char * _tabDepth, int4 * _tabParents, int w, int h) {
int sw1 = w - 1, sw2 = sw1 >> 1;
int sh1 = h - 1, sh2 = sh1 >> 1;
int niveau = 1;
while(sw2){
for(int y = sh2; y < h; y += sh1){
for(int x = sw2; x < w; x += sw1){
if(_tabDepth[y * w + x]) continue;
_tabDepth[y * w + x] = niveau;
_tabParents[y * w + x].x = (y - sh2) * w + x - sw2;
_tabParents[y * w + x].y = (y - sh2) * w + x + sw2;
_tabParents[y * w + x].z = (y + sh2) * w + x + sw2;
_tabParents[y * w + x].w = (y + sh2) * w + x - sw2;
}
}
niveau++;
for(int y = 0; y < h; y += sh1){
for(int x = sw2; x < w; x += sw1){
int yp, xp;
if(_tabDepth[y * w + x]) continue;
yp = y - sh2; xp = x; // parent haut
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].x = yp * w + xp;
} else{
_tabParents[y * w + x].x = -1;
}
yp = y; xp = x + sw2; // parent droit
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].y = yp * w + xp;
} else{
_tabParents[y * w + x].y = -1;
}
yp = y + sh2; xp = x; // parent bas
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].z = yp * w + xp;
} else{
_tabParents[y * w + x].z = -1;
}
yp = y; xp = x - sw2; // parent gauche
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].w = yp * w + xp;
} else{
_tabParents[y * w + x].w = -1;
}
_tabDepth[y * w + x] = niveau;
}
}
for(int y = sh2; y < h; y += sh1){
for(int x = 0; x < w; x += sw1){
int yp, xp;
if(_tabDepth[y * w + x]) continue;
yp = y - sh2; xp = x; // parent haut
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].x = yp * w + xp;
} else{
_tabParents[y * w + x].x = -1;
}
yp = y; xp = x + sw2; // parent droit
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].y = yp * w + xp;
} else{
_tabParents[y * w + x].y = -1;
}
yp = y + sh2; xp = x; // parent bas
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].z = yp * w + xp;
} else{
_tabParents[y * w + x].z = -1;
}
yp = y; xp = x - sw2; // parent gauche
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].w = yp * w + xp;
} else{
_tabParents[y * w + x].w = -1;
}
_tabDepth[y * w + x] = niveau;
}
}
niveau ++;
sw1 = sw2;
sw2 >>= 1;
sh1 = sh2;
sh2 >>= 1;
}
}
void initArraysTe(unsigned char * _tabDepth, int4 * _tabParents, int x0, int y0, int stride, int sx, int sy, int p) {
int w_2 = sx >> 1, h_2 = sy >> 1, j;
int x[9] = { x0, x0 + sx, x0 + sx,
x0, x0 + w_2, x0 + sx, x0 + w_2,
x0, x0 + w_2 };
int y[9] = { y0,
y0, y0 + sy, y0 + sy,
y0, y0 + h_2, y0 + sy, y0 + h_2, y0 + h_2 };
for(int i = 0, i1 = 1; i < 4; ++i, i1 = (i1 + 1) % 4) {
if(_tabDepth[j = y[i + 4] * stride + x[i + 4]]) continue;
//Parents
_tabParents[j].x = y[i] * stride + x[i];
_tabParents[j].y = y[i1] * stride + x[i1];
_tabParents[j].z = -1;
_tabParents[j].w = -1;
//prof
_tabDepth[j] = p;
}
if(!_tabDepth[j = y[8] * stride + x[8]]) {
for(int i = 0; i < 4; ++i) {
//prof
_tabDepth[j] = p;
//Tab parent
if(i == 1){
_tabParents[j].x = y[i] * stride + x[i];
} else if(i == 2){
_tabParents[j].y = y[i] * stride + x[i];
} else if(i == 3) {
_tabParents[j].z = y[i] * stride + x[i];
} else {
_tabParents[j].w = y[i] * stride + x[i];
}
}
}
if(w_2 > 1) {
initArraysTe(_tabDepth, _tabParents, x[0], y[0], stride, w_2, h_2, ++p);
initArraysTe(_tabDepth, _tabParents, x[4], y[4], stride, w_2, h_2, p);
initArraysTe(_tabDepth, _tabParents, x[8], y[8], stride, w_2, h_2, p);
initArraysTe(_tabDepth, _tabParents, x[7], y[7], stride, w_2, h_2, p);
}
}
void triangleEdgeCPU(unsigned char * data, int x0, int y0, int stride, int sx, int sy, int p) {
int niveau = 1;
int w_2 = sx >> 1, h_2 = sy >> 1, j;
int x[9] = { x0, x0 + sx, x0 + sx,
x0, x0 + w_2, x0 + sx, x0 + w_2,
x0, x0 + w_2 };
int y[9] = { y0,
y0, y0 + sy, y0 + sy,
y0, y0 + h_2, y0 + sy, y0 + h_2, y0 + h_2 };
for(int i = 0, i1 = 1; i < 4; ++i, i1 = (i1 + 1) % 4) {
if(data[j = y[i + 4] * stride + x[i + 4]]) continue;
data[j] = ((int)data[y[i] * stride + x[i]] +
data[y[i1] * stride + x[i1]]) >> 1;
}
if(!data[j = y[8] * stride + x[8]]) {
int v = 0;
for(int i = 0; i < 4; ++i)
v += data[y[i] * stride + x[i]];
data[j] = v >> 2;
}
if(w_2 > 1) {
triangleEdgeCPU(data, x[0], y[0], stride, w_2, h_2, ++p);
triangleEdgeCPU(data, x[4], y[4], stride, w_2, h_2, p);
triangleEdgeCPU(data, x[8], y[8], stride, w_2, h_2, p);
triangleEdgeCPU(data, x[7], y[7], stride, w_2, h_2, p);
}
}
void diamontCPU(int w, int h, unsigned char * data) {
int sw1 = w - 1, sw2 = sw1 >> 1;
int sh1 = h - 1, sh2 = sh1 >> 1;
while(sw2){
for(int y = sh2; y < h; y += sh1){
for(int x = sw2; x < w; x += sw1){
if(data[y * w + x]) continue;
data[y * w + x] = (data[(y - sh2) * w + x - sw2] +
data[(y - sh2) * w + x + sw2] +
data[(y + sh2) * w + x + sw2] +
data[(y + sh2) * w + x - sw2]) >> 2;
}
}
for(int y = 0; y < h; y += sh1){
for(int x = sw2; x < w; x += sw1){
int yp, xp;
int nbp = 0, v = 0;
if(data[y * w + x]) continue;
yp = y - sh2; xp = x; // parent haut
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y; xp = x + sw2; // parent droit
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y + sh2; xp = x; // parent bas
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y; xp = x - sw2; // parent gauche
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
data[y * w + x] = v / nbp;
}
}
for(int y = sh2; y < h; y += sh1){
for(int x = 0; x < w; x += sw1){
int yp, xp;
int nbp = 0, v = 0;
if(data[y * w + x]) continue;
yp = y - sh2; xp = x; // parent haut
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y; xp = x + sw2; // parent droit
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y + sh2; xp = x; // parent bas
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y; xp = x - sw2; // parent gauche
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
data[y * w + x] = v / nbp;
}
}
sw1 = sw2;
sw2 >>= 1;
sh1 = sh2;
sh2 >>= 1;
}
}
__global__ void generateImg(unsigned char * data, unsigned char * img, unsigned char * tabDepth, int4 * _tabParents, int i, int tailleTab) {
int thx = blockIdx.x * blockDim.x + threadIdx.x;
int thy = blockIdx.y * blockDim.y + threadIdx.y;
int ThId = thy * tailleTab + thx;
int nbPar = 0;
if(data[ThId] == 0 && tabDepth[ThId] == i && i != 1) {
if(_tabParents[ThId].x != -1) nbPar ++;
if(_tabParents[ThId].y != -1) nbPar ++;
if(_tabParents[ThId].z != -1) nbPar ++;
if(_tabParents[ThId].w != -1) nbPar ++;
data[ThId] = (data[_tabParents[ThId].x] + data[_tabParents[ThId].y] + data[_tabParents[ThId].z] + data[_tabParents[ThId].w]) / nbPar;
img[ThId] = data[ThId];
}
}
void initTime(void) {
gettimeofday(&ti, (struct timezone*) 0);
}
double getTime(void) {
struct timeval t;
double diff;
gettimeofday(&t, (struct timezone*) 0);
diff = (t.tv_sec - ti.tv_sec) * 1000000
+ (t.tv_usec - ti.tv_usec);
return diff/1000.;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
static struct timeval ti;
bool IN(int x, int y, int w, int h) {
return (x) >= 0 && (y) >= 0 && (x) < (w) && (y) < (h);
}
int maxProf(unsigned char * arr, int matDim){
int max_value = 0;
for (int i = 0; i < matDim; ++i) {
if (arr[i] > max_value)
max_value = arr[i];
}
return max_value;
}
void displayMat(unsigned char * arr, char * name, int matDim){
printf("Matrice de %s \n \n", name);
for(int y = 0; y < matDim; ++y){
for(int x = 0; x < matDim; ++x){
printf("%d ", (int)arr[y * matDim + x]);
}
printf("\n");
}
printf("\n");
}
void initArraysDs(unsigned char * _tabDepth, int4 * _tabParents, int w, int h) {
int sw1 = w - 1, sw2 = sw1 >> 1;
int sh1 = h - 1, sh2 = sh1 >> 1;
int niveau = 1;
while(sw2){
for(int y = sh2; y < h; y += sh1){
for(int x = sw2; x < w; x += sw1){
if(_tabDepth[y * w + x]) continue;
_tabDepth[y * w + x] = niveau;
_tabParents[y * w + x].x = (y - sh2) * w + x - sw2;
_tabParents[y * w + x].y = (y - sh2) * w + x + sw2;
_tabParents[y * w + x].z = (y + sh2) * w + x + sw2;
_tabParents[y * w + x].w = (y + sh2) * w + x - sw2;
}
}
niveau++;
for(int y = 0; y < h; y += sh1){
for(int x = sw2; x < w; x += sw1){
int yp, xp;
if(_tabDepth[y * w + x]) continue;
yp = y - sh2; xp = x; // parent haut
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].x = yp * w + xp;
} else{
_tabParents[y * w + x].x = -1;
}
yp = y; xp = x + sw2; // parent droit
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].y = yp * w + xp;
} else{
_tabParents[y * w + x].y = -1;
}
yp = y + sh2; xp = x; // parent bas
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].z = yp * w + xp;
} else{
_tabParents[y * w + x].z = -1;
}
yp = y; xp = x - sw2; // parent gauche
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].w = yp * w + xp;
} else{
_tabParents[y * w + x].w = -1;
}
_tabDepth[y * w + x] = niveau;
}
}
for(int y = sh2; y < h; y += sh1){
for(int x = 0; x < w; x += sw1){
int yp, xp;
if(_tabDepth[y * w + x]) continue;
yp = y - sh2; xp = x; // parent haut
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].x = yp * w + xp;
} else{
_tabParents[y * w + x].x = -1;
}
yp = y; xp = x + sw2; // parent droit
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].y = yp * w + xp;
} else{
_tabParents[y * w + x].y = -1;
}
yp = y + sh2; xp = x; // parent bas
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].z = yp * w + xp;
} else{
_tabParents[y * w + x].z = -1;
}
yp = y; xp = x - sw2; // parent gauche
if(IN(xp, yp, w, h)){
_tabParents[y * w + x].w = yp * w + xp;
} else{
_tabParents[y * w + x].w = -1;
}
_tabDepth[y * w + x] = niveau;
}
}
niveau ++;
sw1 = sw2;
sw2 >>= 1;
sh1 = sh2;
sh2 >>= 1;
}
}
void initArraysTe(unsigned char * _tabDepth, int4 * _tabParents, int x0, int y0, int stride, int sx, int sy, int p) {
int w_2 = sx >> 1, h_2 = sy >> 1, j;
int x[9] = { x0, x0 + sx, x0 + sx,
x0, x0 + w_2, x0 + sx, x0 + w_2,
x0, x0 + w_2 };
int y[9] = { y0,
y0, y0 + sy, y0 + sy,
y0, y0 + h_2, y0 + sy, y0 + h_2, y0 + h_2 };
for(int i = 0, i1 = 1; i < 4; ++i, i1 = (i1 + 1) % 4) {
if(_tabDepth[j = y[i + 4] * stride + x[i + 4]]) continue;
//Parents
_tabParents[j].x = y[i] * stride + x[i];
_tabParents[j].y = y[i1] * stride + x[i1];
_tabParents[j].z = -1;
_tabParents[j].w = -1;
//prof
_tabDepth[j] = p;
}
if(!_tabDepth[j = y[8] * stride + x[8]]) {
for(int i = 0; i < 4; ++i) {
//prof
_tabDepth[j] = p;
//Tab parent
if(i == 1){
_tabParents[j].x = y[i] * stride + x[i];
} else if(i == 2){
_tabParents[j].y = y[i] * stride + x[i];
} else if(i == 3) {
_tabParents[j].z = y[i] * stride + x[i];
} else {
_tabParents[j].w = y[i] * stride + x[i];
}
}
}
if(w_2 > 1) {
initArraysTe(_tabDepth, _tabParents, x[0], y[0], stride, w_2, h_2, ++p);
initArraysTe(_tabDepth, _tabParents, x[4], y[4], stride, w_2, h_2, p);
initArraysTe(_tabDepth, _tabParents, x[8], y[8], stride, w_2, h_2, p);
initArraysTe(_tabDepth, _tabParents, x[7], y[7], stride, w_2, h_2, p);
}
}
void triangleEdgeCPU(unsigned char * data, int x0, int y0, int stride, int sx, int sy, int p) {
int niveau = 1;
int w_2 = sx >> 1, h_2 = sy >> 1, j;
int x[9] = { x0, x0 + sx, x0 + sx,
x0, x0 + w_2, x0 + sx, x0 + w_2,
x0, x0 + w_2 };
int y[9] = { y0,
y0, y0 + sy, y0 + sy,
y0, y0 + h_2, y0 + sy, y0 + h_2, y0 + h_2 };
for(int i = 0, i1 = 1; i < 4; ++i, i1 = (i1 + 1) % 4) {
if(data[j = y[i + 4] * stride + x[i + 4]]) continue;
data[j] = ((int)data[y[i] * stride + x[i]] +
data[y[i1] * stride + x[i1]]) >> 1;
}
if(!data[j = y[8] * stride + x[8]]) {
int v = 0;
for(int i = 0; i < 4; ++i)
v += data[y[i] * stride + x[i]];
data[j] = v >> 2;
}
if(w_2 > 1) {
triangleEdgeCPU(data, x[0], y[0], stride, w_2, h_2, ++p);
triangleEdgeCPU(data, x[4], y[4], stride, w_2, h_2, p);
triangleEdgeCPU(data, x[8], y[8], stride, w_2, h_2, p);
triangleEdgeCPU(data, x[7], y[7], stride, w_2, h_2, p);
}
}
void diamontCPU(int w, int h, unsigned char * data) {
int sw1 = w - 1, sw2 = sw1 >> 1;
int sh1 = h - 1, sh2 = sh1 >> 1;
while(sw2){
for(int y = sh2; y < h; y += sh1){
for(int x = sw2; x < w; x += sw1){
if(data[y * w + x]) continue;
data[y * w + x] = (data[(y - sh2) * w + x - sw2] +
data[(y - sh2) * w + x + sw2] +
data[(y + sh2) * w + x + sw2] +
data[(y + sh2) * w + x - sw2]) >> 2;
}
}
for(int y = 0; y < h; y += sh1){
for(int x = sw2; x < w; x += sw1){
int yp, xp;
int nbp = 0, v = 0;
if(data[y * w + x]) continue;
yp = y - sh2; xp = x; // parent haut
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y; xp = x + sw2; // parent droit
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y + sh2; xp = x; // parent bas
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y; xp = x - sw2; // parent gauche
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
data[y * w + x] = v / nbp;
}
}
for(int y = sh2; y < h; y += sh1){
for(int x = 0; x < w; x += sw1){
int yp, xp;
int nbp = 0, v = 0;
if(data[y * w + x]) continue;
yp = y - sh2; xp = x; // parent haut
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y; xp = x + sw2; // parent droit
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y + sh2; xp = x; // parent bas
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
yp = y; xp = x - sw2; // parent gauche
if(IN(xp, yp, w, h)){
++nbp;
v += data[yp * w + xp] ;
}
data[y * w + x] = v / nbp;
}
}
sw1 = sw2;
sw2 >>= 1;
sh1 = sh2;
sh2 >>= 1;
}
}
__global__ void generateImg(unsigned char * data, unsigned char * img, unsigned char * tabDepth, int4 * _tabParents, int i, int tailleTab) {
int thx = blockIdx.x * blockDim.x + threadIdx.x;
int thy = blockIdx.y * blockDim.y + threadIdx.y;
int ThId = thy * tailleTab + thx;
int nbPar = 0;
if(data[ThId] == 0 && tabDepth[ThId] == i && i != 1) {
if(_tabParents[ThId].x != -1) nbPar ++;
if(_tabParents[ThId].y != -1) nbPar ++;
if(_tabParents[ThId].z != -1) nbPar ++;
if(_tabParents[ThId].w != -1) nbPar ++;
data[ThId] = (data[_tabParents[ThId].x] + data[_tabParents[ThId].y] + data[_tabParents[ThId].z] + data[_tabParents[ThId].w]) / nbPar;
img[ThId] = data[ThId];
}
}
void initTime(void) {
gettimeofday(&ti, (struct timezone*) 0);
}
double getTime(void) {
struct timeval t;
double diff;
gettimeofday(&t, (struct timezone*) 0);
diff = (t.tv_sec - ti.tv_sec) * 1000000
+ (t.tv_usec - ti.tv_usec);
return diff/1000.;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11generateImgPhS_S_P15HIP_vector_typeIiLj4EEii
.globl _Z11generateImgPhS_S_P15HIP_vector_typeIiLj4EEii
.p2align 8
.type _Z11generateImgPhS_S_P15HIP_vector_typeIiLj4EEii,@function
_Z11generateImgPhS_S_P15HIP_vector_typeIiLj4EEii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s5, s[0:1], 0x24
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_load_b64 s[2:3], s[0:1], 0x0
s_mul_i32 s14, s14, s4
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s5
v_add3_u32 v0, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
global_load_u8 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u16_e32 0, v4
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s6, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
s_cmp_lg_u32 s6, 1
s_cselect_b32 s4, -1, 0
global_load_u8 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s6, v4
s_and_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x18
v_lshlrev_b64 v[4:5], 4, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b128 v[4:7], v[4:5], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v9, 31, v4
v_ashrrev_i32_e32 v10, 31, v5
v_add_co_u32 v15, vcc_lo, s2, v4
v_ashrrev_i32_e32 v12, 31, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v16, vcc_lo, s3, v9, vcc_lo
v_add_co_u32 v17, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v18, vcc_lo, s3, v10, vcc_lo
v_ashrrev_i32_e32 v14, 31, v7
v_add_co_u32 v19, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v20, vcc_lo, s3, v12, vcc_lo
s_clause 0x1
global_load_u8 v21, v[15:16], off
global_load_u8 v17, v[17:18], off
v_add_co_u32 v15, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v16, vcc_lo, s3, v14, vcc_lo
s_clause 0x1
global_load_u8 v18, v[19:20], off
global_load_u8 v15, v[15:16], off
v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v11, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u64_e32 vcc_lo, -1, v[8:9]
v_mov_b32_e32 v9, v5
v_cndmask_b32_e64 v4, 0, 1, vcc_lo
v_cndmask_b32_e64 v5, 1, 2, vcc_lo
v_cmp_ne_u64_e32 vcc_lo, -1, v[11:12]
v_cndmask_b32_e64 v6, 0, 1, vcc_lo
v_cmp_eq_u64_e32 vcc_lo, -1, v[9:10]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v13, v7 :: v_dual_cndmask_b32 v4, v5, v4
v_cmp_ne_u64_e32 vcc_lo, -1, v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u16 v4, v4, v6
v_cndmask_b32_e64 v5, 0, 1, vcc_lo
v_add_nc_u16 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cvt_f32_ubyte0_e32 v4, v4
s_waitcnt vmcnt(2)
v_add_nc_u16 v6, v17, v21
s_waitcnt vmcnt(1)
v_add_nc_u16 v5, v6, v18
v_rcp_iflag_f32_e32 v6, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u16 v5, v5, v15
v_and_b32_e32 v5, 0xffff, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v6, v5, v6
v_trunc_f32_e32 v6, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v5, -v6, v4, v5
v_cvt_u32_f32_e32 v6, v6
v_cmp_ge_f32_e64 vcc_lo, |v5|, |v4|
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v6, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b8 v[2:3], v4, off
global_store_b8 v[0:1], v4, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11generateImgPhS_S_P15HIP_vector_typeIiLj4EEii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 22
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11generateImgPhS_S_P15HIP_vector_typeIiLj4EEii, .Lfunc_end0-_Z11generateImgPhS_S_P15HIP_vector_typeIiLj4EEii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11generateImgPhS_S_P15HIP_vector_typeIiLj4EEii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11generateImgPhS_S_P15HIP_vector_typeIiLj4EEii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 22
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
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